PIC16C712/716 8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM Devices included in this Data Sheet: Pin Diagrams • PIC16C712 • PIC16C716 18-pin PDIP, SOIC, Windowed CERDIP Microcontroller Core Features: RA2/AN2 1 18 RA1/AN1 • High-performance RISC CPU RA3/AN3/VREF 2 17 RA0/AN0 RA4/T0CKI 3 62 16 OSC1/CLKIN • Only 35 single-word instructions to learn MCLR/VPP 4 7171 15 OSC2/CLKOUT VSS 5 CC 14 VDD • All single-cycle instructions except for program RB0/INT 6 1616 13 RB7 branches which are two cycle RB1/T1ORSBO2//TT11OCSKII 78 PICPIC 1112 RRBB65 • Operating speed: DC – 20 MHz clock input RB3/CCP1 9 10 RB4 DC – 200 ns instruction cycle Program Device Data Memory Memory 20-pin SSOP PIC16C712 1K 128 PIC16C716 2K 128 RA2/AN2 1 20 RA1/AN1 RA3/AN3/VREF 2 19 RA0/AN0 • Interrupt capability RA4/T0CKI 3 62 18 OSC1/CLKIN (up to 7 internal/external interrupt sources) MCLR/VPP 4 7171 17 OSC2/CLKOUT VSS 5 CC 16 VDD • Eight-level deep hardware stack VSS 6 1616 15 VDD • Direct, Indirect and Relative Addressing modes RB1/T1OSOR/BT01/CINKTI 78 PICPIC 1134 RRBB76 • Power-on Reset (POR) RB2/T1OSI 9 12 RB5 RB3/CCP1 10 11 RB4 • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC Peripheral Features: oscillator for reliable operation • Brown-out detection circuitry for • Timer0: 8-bit timer/counter with 8-bit prescaler Brown-out Reset (BOR) • Timer1: 16-bit timer/counter with prescaler • Programmable code-protection can be incremented during Sleep via external • Power-saving Sleep mode crystal/clock • Selectable oscillator options • Timer2: 8-bit timer/counter with 8-bit period • Low-power, high-speed CMOS EPROM register, prescaler and postscaler technology • Capture, Compare, PWM module • Fully static design • Capture is 16-bit, max. resolution is 12.5 ns, • In-Circuit Serial Programming(ICSP™) Compare is 16-bit, max. resolution is 200 ns, PWM maximum resolution is 10-bit • Wide operating voltage range: 2.5V to 5.5V • 8-bit multi-channel Analog-to-Digital converter • High Sink/Source Current 25/25 mA (cid:129) Commercial, Industrial and Extended temperature ranges • Low-power consumption: - < 2 mA @ 5V, 4 MHz - 22.5 A, typical @ 3V, 32 kHz - < 1 A, typical standby current  1999-2013 Microchip Technology Inc. DS41106C-page 1

PIC16C712/716 Key Features PIC16C712 PIC16C716 PIC® Mid-Range Reference Manual (DS33023) Operating Frequency DC – 20 MHz DC – 20 MHz Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) Program Memory (14-bit words) 1K 2K Data Memory (bytes) 128 128 Interrupts 7 7 I/O Ports Ports A,B Ports A,B Timers 3 3 Capture/Compare/PWM modules 1 1 8-bit Analog-to-Digital Module 4 input channels 4 input channels PIC16C7XX FAMILY OF DEVICES PIC16C710 PIC16C71 PIC16C711 PIC16C712 PIC16C715 PIC16C716 PIC16C72A PIC16C73B Maximum Frequency 20 20 20 20 20 20 20 20 Clock of Operation (MHz) EPROM Program 512 1K 1K 1K 2K 2K 2K 4K Memory Memory (x14 words) Data Memory (bytes) 36 36 68 128 128 128 128 192 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR1 TMR1 TMR1 TMR1 TMR2 TMR2 TMR2 TMR2 Capture/Compare/ — — — 1 — 1 1 2 Peripherals PWM Module(s) Serial Port(s) — — — — — — SPI/I2C SPI/I2C, (SPI™/I2C™, USART) USART A/D Converter (8-bit) 4 4 4 4 4 4 5 5 Channels Interrupt Sources 4 4 4 7 4 7 8 11 I/O Pins 13 13 13 13 13 13 22 22 Voltage Range (Volts) 2.5-6.0 3.0-6.0 2.5-6.0 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 In-Circuit Serial Yes Yes Yes Yes Yes Yes Yes Yes Features Programming™ Brown-out Reset Yes — Yes Yes Yes Yes Yes Yes Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC SOIC; SOIC; SOIC; SOIC; SOIC, SSOP SOIC 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP DS41106C-page 2  1999-2013 Microchip Technology Inc.

PIC16C712/716 Table of Contents 1.0 Device Overview..........................................................................................................................................................................5 2.0 Memory Organization...................................................................................................................................................................9 3.0 I/O Ports.....................................................................................................................................................................................21 4.0 Timer0 Module...........................................................................................................................................................................29 5.0 Timer1 Module...........................................................................................................................................................................31 6.0 Timer2 Module...........................................................................................................................................................................36 7.0 Capture/Compare/PWM (CCP) Module(s).................................................................................................................................39 8.0 Analog-to-Digital Converter (A/D) Module..................................................................................................................................45 9.0 Special Features of the CPU......................................................................................................................................................51 10.0 Instruction Set Summary............................................................................................................................................................67 11.0 Development Support.................................................................................................................................................................69 12.0 Electrical Characteristics............................................................................................................................................................73 13.0 Packaging Information................................................................................................................................................................89 Revision History ..................................................................................................................................................................................95 Conversion Considerations .................................................................................................................................................................95 Migration from Base-line to Mid-Range Devices .................................................................................................................................95 Index ...................................................................................................................................................................................................97 On-Line Support.................................................................................................................................................................................101 Reader Response..............................................................................................................................................................................102 PIC16C712/716 Product Identification System..................................................................................................................................103 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  1999-2013 Microchip Technology Inc. DS41106C-page 3

PIC16C712/716 NOTES: DS41106C-page 4  1999-2013 Microchip Technology Inc.

PIC16C712/716 1.0 DEVICE OVERVIEW There are two devices (PIC16C712, PIC16C716) covered by this data sheet. This document contains device-specific information. Additional information may be found in the PIC® Mid- Figure1-1 is the block diagram for both devices. The pinouts are listed in Table1-1. Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representa- tive or downloaded from the Microchip web site. The Reference Manual should be considered a comple- mentary document to this data sheet, and is highly rec- ommended reading for a better understanding of the device architecture and operation of the peripheral modules. FIGURE 1-1: PIC16C712/716 BLOCK DIAGRAM 13 Data Bus 8 PORTA EPROM Program Counter 1K X 14 RA0/AN0 or RA1/AN1 2K x 14 RA2/AN2 RAM Program 8 Level Stack RA3/AN3/VREF Memory (13-bit) 128 x 8 RA4/T0CKI File Registers Program Bus 14 RAM Addr(1) 9 PORTB Instruction Reg Addr MUX RB0/INT RB1/T1OSO/T1CKI Direct Addr 7 8 InAddirderct RB2/T1OSI RB3/CCP1 FSR Reg RB4 RB5 STATUS Reg RB6 8 RB7 3 Power-up MUX Timer Instruction Oscillator Decode & Start-up Timer ALU Control Power-on Reset 8 OSC1/CLKIN Timing Watchdog OSC2/CLKOUT Generation Timer W Reg Brown-out Reset MCLR VDD, VSS Timer0 Timer1 Timer2 CCP1 A/D Note 1: Higher order bits are from the STATUS register.  1999-2013 Microchip Technology Inc. DS41106C-page 5

PIC16C712/716 TABLE 1-1: PIC16C712/716 PINOUT DESCRIPTION Pin PIC16C712/716 Pin Buffer Name DIP, SOIC SSOP Type Type Description MCLR/VPP 4 4 MCLR I ST Master clear (Reset) input. This pin is an active low Reset to the device. VPP P Programming voltage input OSC1/CLKIN 16 18 OSC1 I ST Oscillator crystal input or external clock source input. ST buffer when config- ured in RC mode. CMOS otherwise. CLKIN I CMOS External clock source input. OSC2/CLKOUT 15 17 OSC2 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. CLKOUT O — In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/AN0 17 19 RA0 I/O TTL Digital I/O AN0 I Analog Analog input 0 RA1/AN1 18 20 RA1 I/O TTL Digital I/O AN1 I Analog Analog input 1 RA2/AN2 1 1 RA2 I/O TTL Digital I/O AN2 I Analog Analog input 2 RA3/AN3/VREF 2 2 RA3 I/O TTL Digital I/O AN3 I Analog Analog input 3 VREF I Analog A/D Reference Voltage input. RA4/T0CKI 3 3 RA4 I/O ST/OD Digital I/O. Open drain when configured as output. T0CKI I ST Timer0 external clock input Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels OD = Open drain output SM = SMBus compatible input. An external resistor is required if this pin is used as an output NPU = N-channel pull-up PU = Weak internal pull-up No-P diode = No P-diode to VDD AN = Analog input or output I = input O = output P = Power L = LCD Driver DS41106C-page 6  1999-2013 Microchip Technology Inc.

PIC16C712/716 TABLE 1-1: PIC16C712/716 PINOUT DESCRIPTION (CONTINUED) Pin PIC16C712/716 Pin Buffer Name DIP, SOIC SSOP Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT 6 7 RB0 I/O TTL Digital I/O INT I ST External Interrupt RB1/T1OSO/T1CKI 7 8 RB1 T1OSO I/O TTL Digital I/O O — Timer1 oscillator output. Connects to T1CKI crystal in oscillator mode. I ST Timer1 external clock input. RB2/T1OSI 8 9 RB2 I/O TTL Digital I/O T1OSI I — Timer1 oscillator input. Connects to crystal in oscillator mode. RB3/CCP1 9 10 RB3 I/O TTL Digital I/O CCP1 I/O ST Capture1 input, Compare1 output, PWM1 output. RB4 10 12 I/O TTL Digital I/O Interrupt on change pin. RB5 11 12 I/O TTL Digital I/O Interrupt on change pin. RB6 12 13 I/O TTL Digital I/O Interrupt on change pin. I ST ICSP programming clock. RB7 13 14 I/O TTL Digital I/O Interrupt on change pin. I/O ST ICSP programming data. VSS 5 5, 6 P — Ground reference for logic and I/O pins. VDD 14 15, 16 P — Positive supply for logic and I/O pins. Legend: TTL = TTL-compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels OD = Open drain output SM = SMBus compatible input. An external resistor is required if this pin is used as an output NPU = N-channel pull-up PU = Weak internal pull-up No-P diode = No P-diode to VDD AN = Analog input or output I = input O = output P = Power L = LCD Driver  1999-2013 Microchip Technology Inc. DS41106C-page 7

PIC16C712/716 NOTES: DS41106C-page 8  1999-2013 Microchip Technology Inc.

PIC16C712/716 2.0 MEMORY ORGANIZATION FIGURE 2-2: PROGRAM MEMORY MAP AND STACK OF PIC16C716 There are two memory blocks in each of these PIC® microcontroller devices. Each block (Program Memory PC<12:0> and Data Memory) has its own bus so that concurrent access can occur. CALL, RETURN 13 RETFIE, RETLW Additional information on device memory may be found in the PIC® Mid-Range Reference Manual, (DS33023). Stack Level 1 2.1 Program Memory Organization The PIC16C712/716 has a 13-bit Program Counter Stack Level 8 (PC) capable of addressing an 8K x 14 program mem- ory space. PIC16C712 has 1K x 14 words of program memory and PIC16C716 has 2K x 14 words of program Reset Vector 0000h memory. Accessing a location above the physically implemented address will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is y Interrupt Vector 0004h at 0004h. or me 0005h ec FIGURE 2-1: PROGRAM MEMORY MAP Mpa r S AND STACK OF THE se On-chip Program U PIC16C712 Memory PC<12:0> 07FFh CALL, RETURN 13 0800h RETFIE, RETLW Stack Level 1 1FFFh Stack Level 8 Reset Vector 0000h y Interrupt Vector 0004h r o me 0005h ec Ma p r S e s On-chip Program U Memory 03FFh 0400h 1FFFh  1999-2013 Microchip Technology Inc. DS41106C-page 9

PIC16C712/716 2.2 Data Memory Organization FIGURE 2-3: REGISTER FILE MAP The data memory is partitioned into multiple banks File File which contain the General Purpose Registers and the Address Address Special Function Registers. Bits RP1 and RP0 are the 00h INDF(1) INDF(1) 80h bank select bits. 01h TMR0 OPTION_REG 81h RP1(1) RP0 (STATUS<6:5>) 02h PCL PCL 82h 03h STATUS STATUS 83h = 00  Bank 0 = 01  Bank 1 04h FSR FSR 84h = 10  Bank 2 (not implemented) 05h PORTA TRISA 85h = 11  Bank 3 (not implemented) 06h PORTB TRISB 86h Note 1: Maintain this bit clear to ensure upward 07h DATACCP TRISCCP 87h compatibility with future products. 08h 88h Each bank extends up to 7Fh (128 bytes). The lower 09h 89h locations of each bank are reserved for the Special 0Ah PCLATH PCLATH 8Ah Function Registers. Above the Special Function Regis- 0Bh INTCON INTCON 8Bh ters are General Purpose Registers, implemented as 0Ch PIR1 PIE1 8Ch static RAM. All implemented banks contain Special Function Registers. Some “high use” Special Function 0Dh 8Dh Registers from one bank may be mirrored in another 0Eh TMR1L PCON 8Eh bank for code reduction and quicker access. 0Fh TMR1H 8Fh 10h T1CON 90h 2.2.1 GENERAL PURPOSE REGISTER 11h TMR2 91h FILE 12h T2CON PR2 92h The register file can be accessed either directly, or 13h 93h indirectly through the File Select Register FSR (see 14h 94h Section2.5 “Indirect Addressing, INDF and FSR Registers”). 15h CCPR1L 95h 16h CCPR1H 96h 17h CCP1CON 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh 1Eh ADRES 9Eh 1Fh ADCON0 ADCON1 9Fh 20h General A0h Purpose General Registers BFh Purpose 32 Bytes Registers C0h 96 Bytes 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. DS41106C-page 10  1999-2013 Microchip Technology Inc.

PIC16C712/716 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers The Special Function Registers are registers used by associated with the core functions are described in the CPU and Peripheral Modules for controlling the detail in this section. Those related to the operation of desired operation of the device. These registers are the peripheral features are described in detail in that implemented as static RAM. A list of these registers is peripheral feature section. give in Table2-1. TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY Value on: Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets (4) Bank 0 00h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h PCL(1) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS(1) IRP(4) RP1(4) RP0 TO PD Z DC C rr01 1xxx rr0q quuu 04h FSR(1) Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 05h PORTA(5,6) — — —(7) PORTA Data Latch when written: PORTA pins when read --xx xxxx --xu uuuu 06h PORTB(5,6) PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h DATACCP —(7) —(7) —(7) —(7) —(7) DCCP —(7) DT1CK xxxx xxxx xxxx xuxu 08h-09h — Unimplemented — — 0Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h-14h 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h-1Dh — Unimplemented — — 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved. Always maintain these bits clear. 5: On any device Reset, these pins are configured as inputs. 6: This is the value that will be in the port output latch. 7: Reserved bits; Do Not Use.  1999-2013 Microchip Technology Inc. DS41106C-page 11

PIC16C712/716 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on: Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets (4) Bank 1 80h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 OPTION_ 81h RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 REG 82h PCL(1) Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 83h STATUS(1) IRP(4) RP1(4) RP0 TO PD Z DC C rr01 1xxx rr0q quuu 84h FSR(1) Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu 85h TRISA — — —(7) PORTA Data Direction Register --x1 1111 --x1 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISCCP —(7) —(7) —(7) —(7) —(7) TCCP —(7) TT1CK xxxx x1x1 xxxx x1x1 88h-89h — Unimplemented — — 8Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh-91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h-9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved. Always maintain these bits clear. 5: On any device Reset, these pins are configured as inputs. 6: This is the value that will be in the port output latch. 7: Reserved bits; Do Not Use. DS41106C-page 12  1999-2013 Microchip Technology Inc.

PIC16C712/716 2.2.2.1 Status Register It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The STATUS register, shown in Figure2-4, contains STATUS register because these instructions do not the arithmetic status of the ALU, the Reset status and affect the Z, C or DC bits from the STATUS register. For the bank select bits for data memory. other instructions, not affecting any Status bits, see the The STATUS register can be the destination for any “Instruction Set Summary.” instruction, as with any other register. If the STATUS Note1: These devices do not use bits IRP and register is the destination for an instruction that affects RP1 (STATUS<7:6>). Maintain these bits the Z, DC or C bits, then the write to these three bits is clear to ensure upward compatibility with disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not future products. writable. Therefore, the result of an instruction with the 2: The C and DC bits operate as a borrow STATUS register as destination may be different than and digit borrow bit, respectively, in sub- intended. traction. See the SUBLW and SUBWF For example, CLRF STATUS will clear the upper-three instructions for examples. bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 2-4: STATUS REGISTER (ADDRESS 03h, 83h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) – not implemented, maintain clear 0 = Bank 0, 1 (00h-FFh) – not implemented, maintain clear bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) Each bank is 128 bytes Note: RP1 = not implemented, maintain clear bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT Time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.  1999-2013 Microchip Technology Inc. DS41106C-page 13

PIC16C712/716 2.2.2.2 OPTION_REG Register Note: To achieve a 1:1 prescaler assignment for The OPTION_REG register is a readable and writable the TMR0 register, assign the prescaler to register, which contains various control bits to configure the Watchdog Timer. the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. FIGURE 2-5: OPTION_REG REGISTER (ADDRESS 81h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR Reset bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS41106C-page 14  1999-2013 Microchip Technology Inc.

PIC16C712/716 2.2.2.3 INTCON Register Note: Interrupt flag bits get set when an interrupt The INTCON Register is a readable and writable regis- condition occurs, regardless of the state of ter which contains various enable and flag bits for the its corresponding enable bit or the global TMR0 register overflow, RB Port change and External enable bit, GIE (INTCON<7>). User soft- RB0/INT pin interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 2-6: INTCON REGISTER (ADDRESS 0Bh, 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: IINTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state  1999-2013 Microchip Technology Inc. DS41106C-page 15

PIC16C712/716 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to This register contains the individual enable bits for the enable any peripheral interrupt. peripheral interrupts. FIGURE 2-7: PIE1 REGISTER (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE — — — CCP1IE TMR2IE TMR1IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7: Unimplemented: Read as ‘0’ bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5-3: Unimplemented: Read as ‘0’ bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS41106C-page 16  1999-2013 Microchip Technology Inc.

PIC16C712/716 2.2.2.5 PIR1 Register Note: Interrupt flag bits get set when an interrupt This register contains the individual flag bits for the condition occurs, regardless of the state of peripheral interrupts. its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 2-8: PIR1 REGISTER (ADDRESS 0Ch) U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF — — — CCP1IF TMR2IF TMR1IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7: Unimplemented: Read as ‘0’ bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5-3: Unimplemented: Read as ‘0’ bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode: Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow  1999-2013 Microchip Technology Inc. DS41106C-page 17

PIC16C712/716 2.2.2.6 PCON Register Note: If the BODEN Configuration bit is set, BOR The Power Control (PCON) register contains a flag bit is ‘1’ on Power-on Reset. If the BODEN to allow differentiation between a Power-on Reset Configuration bit is clear, BOR is unknown (POR) to an external MCLR Reset or WDT Reset. on Power-on Reset. These devices contain an additional bit to differentiate The BOR Status bit is a “don’t care” and is a Brown-out Reset condition from a Power-on Reset not necessarily predictable if the brown-out condition. circuit is disabled (the BODEN Configura- tion bit is clear). BOR must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. FIGURE 2-9: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7-2: Unimplemented: Read as ‘0’ bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) DS41106C-page 18  1999-2013 Microchip Technology Inc.

PIC16C712/716 2.3 PCL and PCLATH 2.4 Program Memory Paging The Program Counter (PC) specifies the address of the The CALL and GOTO instructions provide 11 bits of instruction to fetch for execution. The PC is 13 bits address to allow branching within any 2K program wide. The low byte is called the PCL register. This reg- memory page. When doing a CALL or GOTO instruction, ister is readable and writable. The high byte is called the upper bit of the address is provided by the PCH register. This register contains the PC<12:8> PCLATH<3>. When doing a CALL or GOTO instruction, bits and is not directly readable or writable. All updates the user must ensure that the page select bit is pro- to the PCH register go through the PCLATH register. grammed so that the desired program memory page is addressed. If a return from a CALL instruction (or inter- 2.3.1 STACK rupt) is executed, the entire 13-bit PC is pushed onto The stack allows a combination of up to 8 program calls the stack. Therefore, manipulation of the PCLATH<3> and interrupts to occur. The stack contains the return bit is not required for the return instructions (which address from this branch in program execution. POPs the address from the stack). Mid-range devices have an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).  1999-2013 Microchip Technology Inc. DS41106C-page 19

PIC16C712/716 2.5 Indirect Addressing, INDF and EXAMPLE 2-2: HOW TO CLEAR RAM FSR Registers USING INDIRECT ADDRESSING The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is MOVLW 0x20 ;initialize pointer contained in the FSR register (FSR is a pointer). This is MOVWF FSR ; to RAM indirect addressing. NEXT CLRF INDF ;clear INDF register INCF FSR ;inc pointer BTFSS FSR,4 ;all done? EXAMPLE 2-1: INDIRECT ADDRESSING GOTO NEXT ;NO, clear next • Register file 05 contains the value 10h CONTINUE : ;YES, continue • Register file 06 contains the value 0Ah • Load the value 05 into the FSR register • A read of the INDF register will return the value of 10h An effective 9-bit address is obtained by concatenating • Increment the value of the FSR register by one the 8-bit FSR register and the IRP bit (STATUS<7>), as (FSR = 06) shown in Figure2-10. However, IRP is not used in the • A read of the INDR register now will return the PIC16C712/716. value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although Status bits may be affected). A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example2-2. FIGURE 2-10: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 from opcode 0 IRP 7 FSR register 0 (2) (2) bank select location select bank select location select 00 01 10 11 00h 80h 100h 180h Data (3) (3) Memory(1) 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register file map detail see Figure2-3. 2: Maintain clear for upward compatibility with future products. 3: Not implemented. DS41106C-page 20  1999-2013 Microchip Technology Inc.

PIC16C712/716 3.0 I/O PORTS Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI Some pins for these I/O ports are multiplexed with an pin is a Schmitt Trigger input and an open drain output. alternate function for the peripheral features on the All other RA port pins have TTL input levels and full device. In general, when a peripheral is enabled, that CMOS output drivers. pin may not be used as a general purpose I/O pin. PORTA pins, RA3:0, are multiplexed with analog Additional information on I/O ports may be found in the inputs and analog VREF input. The operation of each PIC® Mid-Range Reference Manual, (DS33023). pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). 3.1 PORTA and the TRISA Register Note: On a Power-on Reset, these pins are PORTA is a 5-bit wide bidirectional port. The corre- configured as analog inputs and read as sponding data direction register is TRISA. Setting a ‘0’. TRISA bit (= 1) will make the corresponding PORTA pin The TRISA register controls the direction of the RA an input, (i.e., put the corresponding output driver in a pins, even when they are being used as analog inputs. High-Impedance mode). Clearing a TRISA bit (= 0) will The user must ensure the bits in the TRISA register are make the corresponding PORTA pin an output, (i.e., put maintained set when using them as analog inputs. the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the EXAMPLE 3-1: INITIALIZING PORTA pins whereas writing to it will write to the port latch. All BCF STATUS, RP0 ; write operations are read-modify-write operations. CLRF PORTA ; Initialize PORTA by Therefore, a write to a port implies that the port pins are ; clearing output read, the value is modified, and then written to the port ; data latches data latch. BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xEF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<4> as outputs BCF STATUS, RP0 ; Return to Bank 0  1999-2013 Microchip Technology Inc. DS41106C-page 21

PIC16C712/716 FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 DATA BUS D Q VDD WR VDD PORT CK Q P Data Latch D Q N I/O pin WR TRIS CK Q VSS VSS Analog input TRIS Latch mode RD TRIS TTL Input Buffer Q D EN RD PORT To A/D Converter FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN DATA BUS D Q WR PORT CK Q I/O Pin N Data Latch D Q VSS VSS WTRRIS CK Q STrcighgmeitrt Input TRIS Latch Buffer RD TRIS Q D ENEN RD PORT TMR0 Clock Input DS41106C-page 22  1999-2013 Microchip Technology Inc.

PIC16C712/716 TABLE 3-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input RA1/AN1 bit 1 TTL Input/output or analog input RA2/AN2 bit 2 TTL Input/output or analog input RA3/AN3/VREF bit 3 TTL Input/output or analog input or VREF Input/output or external clock input for Timer0 RA4/T0CKI bit 4 ST Output is open drain type Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 05h PORTA — — —(1) RA4 RA3 RA2 RA1 RA0 --xx xxxx --xu uuuu 85h TRISA — — —(1) PORTA Data Direction Register --11 1111 --11 1111 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: Reserved bits; Do Not Use.  1999-2013 Microchip Technology Inc. DS41106C-page 23

PIC16C712/716 3.2 PORTB and the TRISB Register Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is per- PORTB is an 8-bit wide bidirectional port. The corre- formed by clearing bit RBPU (OPTION_REG<7>). The sponding data direction register is TRISB. Setting a weak pull-up is automatically turned off when the port TRISB bit (= 1) will make the corresponding PORTB pin is configured as an output. The pull-ups are pin an input, (i.e., put the corresponding output driver in disabled on a Power-on Reset. a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output, (i.e., put the contents of the output latch on the selected pin). EXAMPLE 3-2: INITIALIZING PORTB BCF STATUS, RP0 ; CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs FIGURE 3-3: BLOCK DIAGRAM OF RB0 PIN VDD RBPU(1) weak VDD P pull-up Data Latch DATA BUS D Q WR PORT I/O CK pin TRIS Latch D Q TTL VSS Input WR TRIS CK Buffer RD TRIS Q D RD PORT EN RB0/INT Schmitt Trigger RD PORT Buffer Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). DS41106C-page 24  1999-2013 Microchip Technology Inc.

PIC16C712/716 PORTB pins RB3:RB1 are multiplexed with several PORTB. The “mismatch” outputs of RB7:RB4 are peripheral functions (Table3-3). PORTB pins RB3:RB0 OR’ed together to generate the RB Port Change have Schmitt Trigger input buffers. Interrupt with flag bit RBIF (INTCON<0>). When enabling peripheral functions, care should be This interrupt can wake the device from Sleep. The taken in defining TRIS bits for each PORTB pin. Some user, in the Interrupt Service Routine, can clear the peripherals override the TRIS bit to make a pin an out- interrupt in the following manner: put, while other peripherals override the TRIS bit to a) Any read or write of PORTB will end the make a pin an input. Since the TRIS bit override is in mismatch condition. effect while the peripheral is enabled, read-modify- b) Clear flag bit RBIF. write instructions (BSF, BCF, XORWF) with TRISB as destination should be avoided. The user should refer to A mismatch condition will continue to set flag bit RBIF. the corresponding peripheral section for the correct Reading PORTB will end the mismatch condition and TRIS bit settings. allow flag bit RBIF to be cleared. Four of PORTB’s pins, RB7:RB4, have an interrupt-on- The interrupt-on-change feature is recommended for change feature. Only pins configured as inputs can wake-up on key depression operation and operations cause this interrupt to occur (i.e., any RB7:RB4 pin where PORTB is only used for the interrupt-on-change configured as an output is excluded from the interrupt- feature. Polling of PORTB is not recommended while on-change comparison). The input pins, RB7:RB4, are using the interrupt-on-change feature. compared with the old value latched on the last read of FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN RBPU(1) TMR1CS T1OSCEN T1CS 1 Data Bus 0 RD DATACCP DATACCP<0> D Q VDD DWART ACCP CK Q PWPuella-ukp VDD TRISCCP<0> 1 D Q RB1/T1OSO/T1CKI WR CK Q 0 TRISCCP PORTB<1> 1 D Q VSS WR CK Q 0 PORTB TRISB<1> D Q WR TRISB CK Q T1OSCEN TMR1CS 1 TTL Buffer RD PORTB 0 T1CLKIN ST Buffer Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).  1999-2013 Microchip Technology Inc. DS41106C-page 25

PIC16C712/716 FIGURE 3-5: BLOCK DIAGRAM OF RB2/T1OSI PIN VDD RBPU(1) weak T1OSCEN Ppull-up VDD PORTB<2> DATA BUS D Q RB1/T1OSO/T1CKI WR PORTB CK Q TRISB<2> VSS D Q WR TRISB CK Q T1OSCEN RD PORTB TTL Buffer Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1 PIN RBPU(1) CCPON DATA BUS 1 CCPIN T RD 0 U DATACCP CCPON PO DATACCP<2> CC 1 D Q 0 WR CK Q VDD DATACCP weak TRISCCP<2> Ppull-up VDD D Q WR CK Q 1 TRISCCP RB3/CCP1 CCP 0 Output Mode PORTB<3> D Q 1 VSS WR CK Q 0 PORTB TRISB<3> D Q WR CK Q TRISB CCPON 1 RD PORTB 0 TTL Buffer Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). DS41106C-page 26  1999-2013 Microchip Technology Inc.

PIC16C712/716 FIGURE 3-7: BLOCK DIAGRAM OF RB7:RB4 PINS VDD RBPU(1) weak VDD P pull-up Data Latch DATA BUS D Q I/O WR PORT CK pin TRIS Latch D Q VSS WR TRIS TTL CK Buffer ST Buffer RD TRIS Latch Q D RD PORT EN Q1 Set RBIF From other Q D RB7:RB4 pins RD PORT EN Q3 RB7:RB6 in Serial Programming mode Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). TABLE 3-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit 0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1/T1OS0/ bit 1 TTL/ST(1) Input/output pin or Timer1 oscillator output, or Timer1 clock input. Internal T1CKI software programmable weak pull-up. See Timer1 section for detailed operation. RB2/T1OSI bit 2 TTL/ST(1) Input/output pin or Timer1 oscillator input. Internal software programmable weak pull-up. See Timer1 section for detailed operation. RB3/CCP1 bit 3 TTL/ST(1) Input/output pin or Capture 1 input, or Compare 1 output, or PWM1 output. Internal software programmable weak pull-up. See CCP1 section for detailed operation. RB4 bit 4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit 5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6 bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note1: This buffer is a Schmitt Trigger input when configured as the external interrupt or peripheral input. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.  1999-2013 Microchip Technology Inc. DS41106C-page 27

PIC16C712/716 TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS41106C-page 28  1999-2013 Microchip Technology Inc.

PIC16C712/716 4.0 TIMER0 MODULE Additional information on external clock requirements is available in the PIC® Mid-Range Reference Manual, The Timer0 module timer/counter has the following (DS33023). features: • 8-bit timer/counter 4.2 Prescaler • Readable and writable An 8-bit counter is available as a prescaler for the • Internal or external clock select Timer0 module or as a postscaler for the Watchdog • Edge select for external clock Timer, respectively (Figure4-2). For simplicity, this • 8-bit software programmable prescaler counter is being referred to as “prescaler” throughout • Interrupt on overflow from FFh to 00h this data sheet. Note that there is only one prescaler available, which is mutually exclusively shared Figure4-1 is a simplified block diagram of the Timer0 between the Timer0 module and the Watchdog Timer. module. Thus, a prescaler assignment for the Timer0 module Additional information on timer modules is available in means that there is no prescaler for the Watchdog the PIC® Mid-Range Reference Manual, (DS33023). Timer and vice-versa. The prescaler is not readable or writable. 4.1 Timer0 Operation The PSA and PS2:PS0 bits (OPTION_REG<3:0>) Timer0 can operate as a timer or as a counter. determine the prescaler assignment and prescale ratio. Timer mode is selected by clearing bit T0CS Clearing bit PSA will assign the prescaler to the Timer0 (OPTION_REG<5>). In timer mode, the Timer0 mod- module. When the prescaler is assigned to the Timer0 ule will increment every instruction cycle (without pres- module, prescale values of 1:2, 1:4, ..., 1:256 are caler). If the TMR0 register is written, the increment is selectable. inhibited for the following two instruction cycles. The Setting bit PSA will assign the prescaler to the Watch- user can work around this by writing an adjusted value dog Timer (WDT). When the prescaler is assigned to to the TMR0 register. the WDT, prescale values of 1:1, 1:2, ..., 1:128 are Counter mode is selected by setting bit T0CS selectable. (OPTION_REG<5>). In Counter mode, Timer0 will When assigned to the Timer0 module, all instructions increment on every rising or falling edge of pin RA4/ writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, T0CKI. The incrementing edge is determined by the BSF 1,x....etc.) will clear the prescaler. When Timer0 Source Edge Select bit T0SE assigned to WDT, a CLRWDT instruction will clear the (OPTION_REG<4>). Clearing bit T0SE selects the prescaler along with the WDT. rising edge. Restrictions on the external clock input are discussed below. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler When an external clock input is used for Timer0, it must count, but will not change the prescaler meet certain requirements. The requirements ensure assignment. the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. FIGURE 4-1: TIMER0 BLOCK DIAGRAM Data Bus FOSC/4 0 PSout 8 1 Sync with 1 Internal TMR0 clocks RA4/T0CKI Programmable 0 PSout pin Prescaler(2) T0SE(1) (2-cycle delay) 3 Set Interrupt PS2, PS1, PS0(1) PSA(1) Flag bit T0IF T0CS(1) on overflow Note1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure4-2 for detailed block diagram).  1999-2013 Microchip Technology Inc. DS41106C-page 29

PIC16C712/716 4.2.1 SWITCHING PRESCALER 4.3 Timer0 Interrupt ASSIGNMENT The TMR0 interrupt is generated when the TMR0 The prescaler assignment is fully under software register overflows from FFh to 00h. This overflow sets control (i.e., it can be changed “on the fly” during bit T0IF (INTCON<2>). The interrupt can be masked by program execution). clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module Interrupt Note: To avoid an unintended device Reset, a Service Routine before re-enabling this interrupt. The specific instruction sequence (shown in the PIC® Mid-Range Reference Manual, TMR0 interrupt cannot awaken the processor from Sleep since the timer is shut off during Sleep. DS33023) must be executed when chang- ing the prescaler assignment from Timer0 to the WDT. This sequence must be fol- lowed even if the WDT is disabled. FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (=Fosc/4) Data Bus 8 M 0 1 RA4/T0CKI U M SYNC pin X U 2 TMR0 Reg 1 0 X Cycles T0SE T0CS PSA Set flag bit T0IF on Overflow 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8-to-1 MUX PS2:PS0 PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0 Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — —(1) Bit 4 PORTA Data Direction Register --11 1111 --11 1111 Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: Reserved bit; Do Not Use. DS41106C-page 30  1999-2013 Microchip Technology Inc.

PIC16C712/716 5.0 TIMER1 MODULE 5.1 Timer1 Operation The Timer1 module timer/counter has the following Timer1 can operate in one of these modes: features: • As a timer • 16-bit timer/counter • As a synchronous counter (Two 8-bit registers; TMR1H and TMR1L) • As an asynchronous counter • Readable and writable (Both registers) The operating mode is determined by the clock select • Internal or external clock select bit, TMR1CS (T1CON<1>). (cid:129) Interrupt on overflow from FFFFh to 0000h In timer mode, Timer1 increments every instruction • Reset from CCP module trigger cycle. In counter mode, it increments on every rising Timer1 has a control register, shown in Figure5-1. edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing When the Timer1 oscillator is enabled (T1OSCEN is control bit TMR1ON (T1CON<0>). set), the RB2/T1OSI and RB1/T1OSO/T1CKI pins Figure5-2 is a simplified block diagram of the Timer1 become inputs. That is, the TRISB<2:1> value is module. ignored. Additional information on timer modules is available in Timer1 also has an internal “Reset input”. This Reset the PIC® Mid-Range Reference Manual, (DS33023). can be generated by the CCP module (see Section7.0 “Capture/Compare/PWM (CCP) Module(s)”). FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit W = Writable bit bit7 bit0 U = Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7-6: Unimplemented: Read as ‘0’ bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RB1/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1  1999-2013 Microchip Technology Inc. DS41106C-page 31

PIC16C712/716 FIGURE 5-2: TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow Synchronized TMR1 0 clock input TMR1H TMR1L 1 TMR1ON on/off T1SYNC T1OSC RB1/T1OSO/T1CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 RB2/T1OSI Oscillator(1) Clock 2 Sleep input T1CKPS1:T1CKPS0 TMR1CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 5.2 Timer1 Module and PORTB Operation When Timer1 is configured as timer running from the main oscillator, PORTB<2:1> operate as normal I/O lines. When Timer1 is configured to function as a counter however, the clock source selection may affect the operation of PORTB<2:1>. Multiplexing details of the Timer1 clock selection on PORTB are shown in Figure 3-4 and Figure 3-5. The clock source for Timer1 in the Counter mode can be from one of the following: 1. External circuit connected to the RB1/T1OSO/ T1CKI pin 2. Firmware controlled DATACCP<0> bit, DT1CKI 3. Timer1 oscillator Table5-1 shows the details of Timer1 mode selections, control bit settings, TMR1 and PORTB operations. DS41106C-page 32  1999-2013 Microchip Technology Inc.

PIC16C712/716 TABLE 5-1: TMR1 MODULE AND PORTB OPERATION TMR1 Module Clock Source Control Bits TMR1 Module Operation PORTB<2:1> Operation Mode Off N/A T1CON = --xx 0x00 Off PORTB<2:1> function as normal I/O Timer FOSC/4 T1CON = --xx 0x01 TMR1 module uses the main PORTB<2:1> function as normal oscillator as clock source. I/O TMR1ON can turn on or turn off Timer1. Counter External circuit T1CON = --xx 0x11 TMR1 module uses the external PORTB<2> functions as normal TR1SCCP = ---- -x-1 signal on the RB1/T1OSO/ I/O. PORTB<1> always reads ‘0’ T1CKI pin as a clock source. when configured as input. If TMR1ON can turn on or turn off PORTB<1> is configured as out- Timer1. DT1CK can read the put, reading PORTB<1> will signal on the RB1/T1OSO/ read the data latch. Writing to T1CKI pin. PORTB<1> will always store the Firmware T1CON = --xx 0x11 DATACCP<0> bit drives RB1/ result in the data latch, but not to TR1SCCP = ---- -x-0 T1OSO/T1CKI and produces the RB1/T1OSO/T1CKI pin. If the TMR1 clock source. the TMR1CS bit is cleared TMR1ON can turn on or turn off (TMR1 reverts to the timer Timer1. The DATACCP<0> bit, mode), then pin PORTB<1> will DT1CK, can read and write to be driven with the value in the the RB1/T1OSO/T1CKI pin. data latch. Timer1 oscillator T1CON = --xx 1x11 RB1/T1OSO/T1CKI and RB2/ PORTB<2:1> always read ‘0’ T1OSI are configured as a 2 pin when configured as inputs. If crystal oscillator. RB1/T1OSI/ PORTB<2:1> are configured as T1CKI is the clock input for outputs, reading PORTB<2:1> TMR1. TMR1ON can turn on or will read the data latches. Writ- turn off Timer1. DATACCP<1> ing to PORTB<2:1> will always bit, DT1CK, always reads ‘0’ as store the result in the data input and can not write to the latches, but not to the RB2/ RB1/T1OSO/T1CK1 pin. T1OSI and RB1/T1OSO/T1CKI pins. If the TMR1CS and T1OSCEN bits are cleared (TMR1 reverts to the timer mode and TMR1 oscillator is disabled), then pin PORTB<2:1> will be driven with the value in the data latches.  1999-2013 Microchip Technology Inc. DS41106C-page 33

PIC16C712/716 5.3 Timer1 Oscillator 5.4 Timer1 Interrupt A crystal oscillator circuit is built in between pins T1OSI The TMR1 Register pair (TMR1H:TMR1L) increments (input) and T1OSO (amplifier output). It is enabled by from 0000h to FFFFh and rolls over to 0000h. The setting control bit T1OSCEN (T1CON<3>). The oscilla- TMR1 interrupt, if enabled, is generated on overflow tor is a low-power oscillator rated up to 200 kHz. It will which is latched in interrupt flag bit TMR1IF (PIR1<0>). continue to run during Sleep. It is primarily intended for This interrupt can be enabled/disabled by setting/clear- a 32 kHz crystal. Table5-2 shows the capacitor ing TMR1 interrupt enable bit TMR1IE (PIE1<0>). selection for the Timer1 oscillator. 5.5 Resetting Timer1 using a CCP The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure Trigger Output proper oscillator start-up. If the CCP module is configured in Compare mode to generate a “Special Event Trigger” (CCP1M3:CCP1M0 TABLE 5-2: CAPACITOR SELECTION FOR = 1011), this signal will reset Timer1 and start an A/D THE TIMER1 OSCILLATOR conversion (if the A/D module is enabled). Osc Type Freq. C1 C2 Note: The Special Event Triggers from the CCP1 module will not set interrupt flag bit LP 32 kHz 33 pF 33 pF TMR1IF (PIR1<0>). 100 kHz 15 pF 15 pF Timer1 must be configured for either Timer or Synchro- 200 kHz 15 pF 15 pF nized Counter mode to take advantage of this feature. These values are for design guidance only. If Timer1 is running in Asynchronous Counter mode, Note1: Higher capacitance increases the stability of this reset operation may not work. oscillator but also increases the start-up In the event that a write to Timer1 coincides with a time. Special Event Trigger from CCP1, the write will take 2: Since each resonator/crystal has its own precedence. characteristics, the user should consult the resonator/crystal manufacturer for In this mode of operation, the CCPR1H:CCPR1L appropriate values of external components. registers pair effectively becomes the period register for Timer1. TABLE 5-3: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000 8Ch PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 07h DATACC — — — — — DCCP — DT1CK ---- -x-x ---- -u-u P 87h TRISCCP — — — — — TCCP — TT1CK ---- -1-1 ---- -1-1 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module. DS41106C-page 34  1999-2013 Microchip Technology Inc.

PIC16C712/716 NOTES:  1999-2013 Microchip Technology Inc. DS41106C-page 35

PIC16C712/716 6.0 TIMER2 MODULE Timer2 has a control register, shown in Figure6-1. Timer2 can be shut off by clearing control bit TMR2ON The Timer2 module timer has the following features: (T2CON<2>) to minimize power consumption. • 8-bit timer (TMR2 register) Figure6-2 is a simplified block diagram of the Timer2 • 8-bit period register (PR2) module. • Readable and writable (both registers) Additional information on timer modules is available in • Software programmable prescaler (1:1, 1:4, 1:16) the PIC® Mid-Range Reference Manual, (DS33023). • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match of PR2 FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3TOUTPS2TOUTPS1TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7: Unimplemented: Read as ‘0’ bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale 0011 = 1:4 Postscale 0100 = 1:5 Postscale 0101 = 1:6 Postscale 0110 = 1:7 Postscale 0111 = 1:8 Postscale 1000 = 1:9 Postscale 1001 = 1:10 Postscale 1010 = 1:11 Postscale 1011 = 1:12 Postscale 1100 = 1:13 Postscale 1101 = 1:14 Postscale 1110 = 1:15 Postscale 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 FIGURE 6-2: TIMER2 BLOCK DIAGRAM Sets flag TMR2 bit TMR2IF output Reset Prescaler TMR2 Reg FOSC/4 1:1, 1:4, 1:16 Postscaler Comparator 2 1:1 to 1:16 EQ 4 PR2 Reg DS41106C-page 36  1999-2013 Microchip Technology Inc.

PIC16C712/716 6.1 Timer2 Operation 6.2 Timer2 Interrupt Timer2 can be used as the PWM time base for PWM The Timer2 module has an 8-bit period register PR2. mode of the CCP module. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is The TMR2 register is readable and writable, and is a readable and writable register. The PR2 register is cleared on any device Reset. initialized to FFh upon Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — CCP1IF TMR2IF TMR1IF -00- -000 0000 -000 8Ch PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 0000 -000 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.  1999-2013 Microchip Technology Inc. DS41106C-page 37

PIC16C712/716 NOTES: DS41106C-page 38  1999-2013 Microchip Technology Inc.

PIC16C712/716 7.0 CAPTURE/COMPARE/PWM Additional information on the CCP module is available (CCP) MODULE(S) in the PIC® Mid-Range Reference Manual, (DS33023). Each CCP (Capture/Compare/PWM) module contains TABLE 7-1: CCP MODE – TIMER a 16-bit register, which can operate as a 16-bit capture RESOURCE register, as a 16-bit compare register or as a PWM CCP Mode Timer Resource master/slave Duty Cycle register. Table7-1 shows the timer resources of the CCP module modes. Capture Timer1 Capture/Compare/PWM Register 1 (CCPR1) is com- Compare Timer1 prised of two 8-bit registers: CCPR1L (low byte) and PWM Timer2 CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ -n =Value at POR Reset bit 7-6: Unimplemented: Read as ‘0’ bit 5-4: DC1B1:DC1B0: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode FIGURE 7-2: TRISCCP REGISTER (ADDRESS 87H) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — — — TCCP — TT1CK R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ -n =Value at POR Reset bit 7-3: Reserved bits; Do Not Use bit 2: TCCP – Tri-state control bit for CCP 0 = Output pin driven 1 = Output pin tristated bit 1: Reserved bit; Do Not Use bit 0: TT1CK – Tri-state control bit for T1CKI pin 0 = T1CKI pin is an output 1 = T1CKI pin is an input  1999-2013 Microchip Technology Inc. DS41106C-page 39

PIC16C712/716 7.1 Capture Mode 7.1.4 CCP PRESCALER In Capture mode, CCPR1H:CCPR1L captures the There are four prescaler settings, specified by bits 16-bit value of the TMR1 register when an event occurs CCP1M3:CCP1M0. Whenever the CCP module is on pin RB3/CCP1. An event is defined as: turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any • every falling edge Reset will clear the prescaler counter. • every rising edge Switching from one capture prescaler to another may • every 4th rising edge generate an interrupt. Also, the prescaler counter will • every 16th rising edge not be cleared, therefore the first capture may be from An event is selected by control bits CCP1M3:CCP1M0 a non-zero prescaler. Example7-1 shows the recom- (CCP1CON<3:0>). When a capture is made, the inter- mended method for switching between capture pres- rupt request flag bit CCP1IF (PIR1<2>) is set. It must calers. This example also clears the prescaler counter be cleared in software. If another capture occurs before and will not generate the “false” interrupt. the value in register CCPR1 is read, the old captured value will be lost. EXAMPLE 7-1: CHANGING BETWEEN CAPTURE PRESCALERS FIGURE 7-3: CAPTURE MODE OPERATION BLOCK CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with DIAGRAM ; the new prescaler ; mode value and CCP ON Set flag bit CCP1IF Prescaler (PIR1<2>) MOVWF CCP1CON ;Load CCP1CON with this  1, 4, 16 ; value RB3/CCP1 CCPR1H CCPR1L Pin and Capture edge detect Enable TMR1H TMR1L CCP1CON<3:0> Q’s 7.1.1 CCP PIN CONFIGURATION In Capture mode, the CCP output must be disabled by setting the TRISCCP<2> bit. Note: If the RB3/CCP1 is configured as an out- put by clearing the TRISCCP<2> bit, a write to the DCCP bit can cause a capture condition. 7.1.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro- nized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 7.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in Operating mode. DS41106C-page 40  1999-2013 Microchip Technology Inc.

PIC16C712/716 7.2 Compare Mode 7.2.1 CCP PIN CONFIGURATION In Compare mode, the 16-bit CCPR1 register value is The user must configure the RB3/CCP1 pin as the CCP constantly compared against the TMR1 register pair output by clearing the TRISCCP<2> bit. value. When a match occurs, the RB3/CCP1 pin is Note: Clearing the CCP1CON register will force either: the RB3/CCP1 compare output latch to • driven High the default low level. This is neither the • driven Low PORTB I/O data latch nor the DATACCP latch. • remains Unchanged The action on the pin is based on the value of control 7.2.2 TIMER1 MODE SELECTION bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the Timer1 must be running in Timer mode or Synchro- same time, interrupt flag bit CCP1IF is set. nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the FIGURE 7-4: COMPARE MODE compare operation may not work. OPERATION BLOCK DIAGRAM 7.2.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 Special Event Trigger will: pin is not affected. Only a CCP interrupt is generated (if Reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), enabled). and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion 7.2.4 SPECIAL EVENT TRIGGER Special Event Trigger In this mode, an internal hardware trigger is generated which may be used to initiate an action. Set flag bit CCP1IF (PIR1<2>) The Special Event Trigger output of CCP1 resets the CCPR1H CCPR1L TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Q S Output RB3/CCP1 R Logic match Comparator Timer1. Pin The Special Event Trigger output of CCP1 also starts TRISCCP<2> TMR1H TMR1L Output Enable CCP1CON<3:0> an A/D conversion (if the A/D module is enabled). Mode Select Note: The Special Event Trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). TABLE 7-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 07h DATACCP — — — — — DCCP — DT1CK xxxx xxxx xxxx xuxu 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 87h TRISCCP — — — — — TCCP — TT1CK xxxx x1x1 xxxx x1x1 8Ch PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.  1999-2013 Microchip Technology Inc. DS41106C-page 41

PIC16C712/716 7.3 PWM Mode 7.3.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2 produces up to a 10-bit resolution PWM output. Since register. The PWM period can be calculated using the the CCP1 pin is multiplexed with the PORTB data latch, following formula: the TRISCCP<2> bit must be cleared to make the PWM period = [(PR2) + 1] • 4 (cid:129) TOSC (cid:129) CCP1 pin an output. (TMR2 prescale value) Note: Clearing the CCP1CON register will force PWM frequency is defined as 1 / [PWM period]. the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events low level. This is neither the PORTB I/O occur on the next increment cycle: data latch nor the DATACCP latch. • TMR2 is cleared Figure7-5 shows a simplified block diagram of the • The CCP1 pin is set (exception: if PWM duty CCP module in PWM mode. cycle=0%, the CCP1 pin will not be set) For a step by step procedure on how to set up the CCP • The PWM duty cycle is latched from CCPR1L into module for PWM operation, see Section7.3.3 “Set- CCPR1H Up for PWM Operation”. Note: The Timer2 postscaler (see Section6.0 FIGURE 7-5: SIMPLIFIED PWM BLOCK “Timer2 Module”) is not used in the DIAGRAM determination of the PWM frequency. The postscaler could be used to have a servo CCP1CON<5:4> Duty cycle registers update rate at a different frequency than the PWM output. CCPR1L 7.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1H (Slave) CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the Comparator R Q two LSbs. This 10-bit value is represented by RB3/CCP1 CCPR1L:CCP1CON<5:4>. The following equation is TMR2 (Note 1) used to calculate the PWM duty cycle in time: S PWM duty cycle = (CCPR1L:CCP1CON<5:4>) (cid:129) Comparator TRISCCP<2> Tosc (cid:129) (TMR2 prescale value) Clear Timer, CCP1 pin and CCPR1L and CCP1CON<5:4> can be written to at any PR2 latch D.C. time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock occurs (i.e., the period is complete). In PWM mode, or 2 bits of the prescaler to create 10-bit time base. CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are A PWM output (Figure7-6) has a time base (period) used to double buffer the PWM duty cycle. This double and a time that the output stays high (duty cycle). The buffering is essential for glitchless PWM operation. frequency of the PWM is the inverse of the period (1/ When the CCPR1H and 2-bit latch match TMR2 period). concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. FIGURE 7-6: PWM OUTPUT Maximum PWM resolution (bits) for a given PWM frequency: Period = PR2+1 FOSC = log( FPWM) bits log(2) Duty Cycle TMR2 = PR2 Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be TMR2 = Duty Cycle (CCPR1H) cleared. TMR2 = PR2 For an example PWM period and duty cycle calcula- tion, see the PIC® Mid-Range Reference Manual, (DS33023). DS41106C-page 42  1999-2013 Microchip Technology Inc.

PIC16C712/716 7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISCCP<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. TABLE 7-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 7-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 07h DATACCP — — — — — DCCP — DT1CK xxxx xxxx xxxx xuxu 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000 11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 87h TRISCCP — — — — — TCCP — TT1CK xxxx x1x1 xxxx x1x1 8Ch PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- -000 92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.  1999-2013 Microchip Technology Inc. DS41106C-page 43

PIC16C712/716 7.4 CCP1 Module and PORTB Operation When the CCP module is disabled, PORTB<3> operates as a normal I/O pin. When the CCP module is enabled, PORTB<3> operation is affected. Multiplexing details of the CCP1 module are shown on PORTB<3>, refer to Figure 3.6. Table 7-5 below shows the effects of the CCP module . operation on PORTB<3> TABLE 7-5: CCP1 MODULE AND PORTB OPERATION CCP1 Module Control Bits CCP1 Module Operation PORTB<3> Operation Mode Off CCP1CON = --xx 0000 Off PORTB<3> functions as normal I/O. Capture CCP1CON = --xx 01xx The CCP1 module will capture an event PORTB<3> always reads ‘0’ when TRISCCP = ---- -1-x on the RB3/CCP1 pin which is driven by configured as input. If PORTB<3> is an external circuit. The DCCP bit can configured as output, reading read the signal on the RB3/CCP1 pin. PORTB<3> will read the data latch. CCP1CON = --xx 01xx The CCP1 module will capture an event Writing to PORTB<3> will always TRISCCP = ---- -0-x on the RB3/CCP1 pin which is driven by store the result in the data latch, but it the DCCP bit. The DCCP bit can read does not drive the RB3/CCP1 pin. the signal on the RB3/CCP1 pin. Compare CCP1CON = --xx 10xx The CCP1 module produces an output TRISCCP = ---- -0-x on the RB3/CCP1 pin when a compare event occurs. The DCCP bit can read the signal on the RB3/CCP1 pin. PWM CCP1CON = --xx 11xx The CCP1 module produces the PWM TRISCCP = ---- -0-x signal on the RB3/CCP1 pin. The DCCP bit can read the signal on the RB3/CCP1 pin. DS41106C-page 44  1999-2013 Microchip Technology Inc.

PIC16C712/716 8.0 ANALOG-TO-DIGITAL Additional information on the A/D module is available in CONVERTER (A/D) MODULE the PIC® Mid-Range Reference Manual, (DS33023). The A/D module has three registers. These registers The Analog-to-Digital (A/D) Converter module has four are: inputs. • A/D Result Register (ADRES) The A/D allows conversion of an analog input signal to • A/D Control Register 0 (ADCON0) a corresponding 8-bit digital number (refer to Applica- • A/D Control Register 1 (ADCON1) tion Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, A device Reset forces all registers to their Reset state. which generates the result via successive approxima- This forces the A/D module to be turned off, and any tion. The analog reference voltage is software select- conversion is aborted. able to either the device’s positive supply voltage (VDD) The ADCON0 register, shown in Figure8-1, controls or the voltage level on the RA3/AN3/VREF pin. the operation of the A/D module. The ADCON1 regis- The A/D converter has a unique feature of being able ter, shown in Figure8-2, configures the functions of the to operate while the device is in Sleep mode. To port pins. The port pins can be configured as analog operate in Sleep, the A/D conversion clock must be inputs (RA3 can also be a voltage reference) or as derived from the A/D’s internal RC oscillator. digital I/O. FIGURE 8-1: ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON R =Readable bit bit7 bit0 W =Writable bit U =Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal ADC RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 1xx = reserved, do not use bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: Unimplemented: Read as ‘0’ bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current  1999-2013 Microchip Technology Inc. DS41106C-page 45

PIC16C712/716 FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 R =Readable bit bit7 bit0 W =Writable bit U =Unimplemented bit, read as ‘0’ -n = Value at POR Reset bit 7-3: Unimplemented: Read as ‘0’ bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA3 VREF 0x0 A A A A VDD 0x1 A A A VREF RA3 100 A A D A VDD 101 A A D VREF RA3 11x D D D D VDD A = Analog input D = Digital I/O DS41106C-page 46  1999-2013 Microchip Technology Inc.

PIC16C712/716 The ADRES register contains the result of the A/D 1. Configure the A/D module: conversion. When the A/D conversion is complete, the • Configure analog pins/voltage reference/ result is loaded into the ADRES register, the GO/DONE and digital I/O (ADCON1) bit (ADCON0<2>) is cleared and the A/D Interrupt Flag • Select A/D input channel (ADCON0) bit ADIF is set. The block diagram of the A/D module is • Select A/D conversion clock (ADCON0) shown in Figure8-3. • Turn on A/D module (ADCON0) The value that is in the ADRES register is not modified 2. Configure A/D interrupt (if desired): for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. • Clear ADIF bit • Set ADIE bit After the A/D module has been configured as desired, the selected channel must be acquired before the • Set GIE bit conversion is started. The analog input channels must 3. Wait the required acquisition time. have their corresponding TRIS bits selected as an 4. Start conversion: input. To determine acquisition time, see Section8.1 (cid:129) Set GO/DONE bit (ADCON0) “A/D Acquisition Requirements”. After this acquisi- 5. Wait for A/D conversion to complete, by either: tion time has elapsed, the A/D conversion can be (cid:129) Polling for the GO/DONE bit to be cleared started. The following steps should be followed for doing an A/D conversion: OR • Waiting for the A/D interrupt 6. Read A/D Result register (ADRES), clear bit ADIF if required. 7. For the next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts. FIGURE 8-3: A/D BLOCK DIAGRAM CHS2:CHS0 VIN (Input voltage) 011 RA3/AN3/VREF 010 A/D RA2/AN2 Converter 001 RA1/AN1 VDD 000 RA0/AN0 000 or VREF 011000 oorr 110 or 111 (Reference voltage) 001 or 011 or 101 PCFG2:PCFG0  1999-2013 Microchip Technology Inc. DS41106C-page 47

PIC16C712/716 8.1 A/D Acquisition Requirements To calculate the minimum acquisition time, TACQ, see the PIC® Mid-Range Reference Manual, (DS33023). For the A/D converter to meet its specified accuracy, This equation calculates the acquisition time to within the Charge Holding capacitor (CHOLD) must be allowed 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error to fully charge to the input channel voltage level. The is the maximum error allowed for the A/D to meet its analog input model is shown in Figure8-4. The source specified accuracy. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge Note: When the conversion is started, the hold- the capacitor CHOLD. The sampling switch (RSS) ing capacitor is disconnected from the impedance varies over the device voltage (VDD). The input pin. source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. FIGURE 8-4: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC  1k SS RSS CHOLD VA CPIN I leakage = DAC capacitance 5 pF VT = 0.6V  500 nA = 51.2 pF VSS Legend: CPIN = input capacitance 6V VT = threshold voltage 5V I leakage = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch (k) DS41106C-page 48  1999-2013 Microchip Technology Inc.

PIC16C712/716 8.2 Selecting the A/D Conversion 8.3 Configuring Analog Port Pins Clock The ADCON1 and TRISA registers control the opera- The A/D conversion time per bit is defined as TAD. The tion of the A/D port pins. The port pins that are desired A/D conversion requires 9.5TAD per 8-bit conversion. as analog inputs must have their corresponding TRIS The source of the A/D conversion clock is software bits set (input). If the TRIS bit is cleared (output), the selectable. The four possible options for TAD are: digital output level (VOH or VOL) will be converted. (cid:129) 2TOSC The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. (cid:129) 8TOSC (cid:129) 32TOSC Note1: When reading the port register, all pins • Internal RC oscillator configured as analog input channels will read as cleared (a low level). Pins For correct A/D conversions, the A/D conversion clock configured as digital inputs, will convert (TAD) must be selected to ensure a minimum TAD time an analog input. Analog levels on a of 1.6 s. digitally configured input will not affect the Table8-1 shows the resultant TAD times derived from conversion accuracy. the device operating frequencies and the A/D clock 2: Analog levels on any pin that is defined as source selected. a digital input (including the AN3:AN0 pins), may cause the input buffer to consume current that is out of the devices specification. TABLE 8-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Device Frequency Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz 2TOSC 00 100 ns(2) 400 ns(2) 1.6 s 6 s 8TOSC 01 400 ns(2) 1.6 s 6.4 s 24 s(3) 32TOSC 10 1.6 s 6.4 s 25.6 s(3) 96 s(3) RC(5) 11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1) Legend:Shaded cells are outside of recommended range. Note1: The RC source has a typical TAD time of 4 s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for Sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section.  1999-2013 Microchip Technology Inc. DS41106C-page 49

PIC16C712/716 8.4 A/D Conversions GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is Note: The GO/DONE bit should NOT be set in reset to automatically repeat the A/D acquisition period the same instruction that turns on the A/D. with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input 8.5 Use of the CCP Trigger channel must be selected and the minimum acquisition done before the “Special Event Trigger” sets the GO/ An A/D conversion can be started by the “Special Event DONE bit (starts a conversion). Trigger” of the CCP1 module. This requires that the If the A/D module is not enabled (ADON is cleared), CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be then the “Special Event Trigger” will be ignored by the programmed as 1011 and that the A/D module is A/D module, but will still reset the Timer1 counter. enabled (ADON bit is set). When the trigger occurs, the TABLE 8-2: SUMMARY OF A/D REGISTERS Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets BOR 05h PORTA — — —(1) RA4 RA3 RA2 RA1 RA0 --xx xxxx --xu uuuu 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — CCP1IF TMR2IF TMR1IF -0-- -000 -0-- -000 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 85h TRISA — — —(1) PORTA Data Direction Register ---1 1111 ---1 1111 8Ch PIE1 — ADIE — — — CCP1IE TMR2IE TMR1IE -0-- -000 -0-- 0000 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: Reserved bits; Do Not Use. DS41106C-page 50  1999-2013 Microchip Technology Inc.

PIC16C712/716 9.0 SPECIAL FEATURES OF THE Sleep mode is designed to offer a very low-current CPU Power-Down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up, or The PIC16C712/716 devices have a host of features through an interrupt. Several oscillator options are also intended to maximize system reliability, minimize cost made available to allow the part to fit the application. through elimination of external components, provide The RC oscillator option saves system cost, while the power-saving operating modes and offer code LP crystal option saves power. A set of Configuration protection. These are: bits are used to select various options. • OSC Selection Additional information on special features is available • Reset: in the PIC® Mid-Range Reference Manual, (DS33023). - Power-on Reset (POR) 9.1 Configuration Bits - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) The Configuration bits can be programmed (read as - Brown-out Reset (BOR) ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped in • Interrupts program memory location 2007h. • Watchdog Timer (WDT) The user will note that address 2007h is beyond the • Sleep user program memory space. In fact, it belongs to • Code protection the special test/configuration memory space • ID locations (2000h-3FFFh), which can be accessed only during • In-Circuit Serial Programming™ (ICSP™) programming. These devices have a Watchdog Timer, which can be shut off only through Configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only and is designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry.  1999-2013 Microchip Technology Inc. DS41106C-page 51

PIC16C712/716 FIGURE 9-1: CONFIGURATION WORD CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register:CONFIG Address2007h bit13 bit0 bit 13-8, 5-4: CP1:CP0: Code Protection bits (2) Code Protection for 2K Program memory (PIC16C716) 11 = Programming code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected bit 13-8, 5-4: Code Protection for 1K Program memory bits (PIC16C712) 11 = Programming code protection off 10 = Programming code protection off 01 = 0200h-03FFh code-protected 00 = 0000h-03FFh code-protected bit 7: Unimplemented: Read as ‘1’ bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. DS41106C-page 52  1999-2013 Microchip Technology Inc.

PIC16C712/716 9.2 Oscillator Configurations TABLE 9-1: CERAMIC RESONATORS Ranges Tested: 9.2.1 OSCILLATOR TYPES Mode Freq OSC1 OSC2 The PIC16CXXX can be operated in four different Oscillator modes. The user can program two XT 455 kHz 68-100 pF 68-100 pF Configuration bits (FOSC1 and FOSC0) to select one 2.0 MHz 15-68 pF 15-68 pF of these four modes: 4.0 MHz 15-68 pF 15-68 pF • LP Low-Power Crystal HS 8.0 MHz 10-68 pF 10-68 pF 16.0 MHz 10-22 pF 10-22 pF • XT Crystal/Resonator These values are for design guidance only. See • HS High-Speed Crystal/Resonator notes at bottom of page. • RC Resistor/Capacitor TABLE 9-2: CAPACITOR SELECTION FOR 9.2.2 CRYSTAL OSCILLATOR/CERAMIC CRYSTAL OSCILLATOR RESONATORS Crystal Cap. Range Cap. Range In XT, LP or HS modes, a crystal or ceramic resonator Osc Type Freq C1 C2 is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure9-2). The LP 32 kHz 33 pF 33 pF PIC16CXXX oscillator design requires the use of a par- 200 kHz 15 pF 15 pF allel cut crystal. Use of a series cut crystal may give a XT 200 kHz 47-68 pF 47-68 pF frequency out of the crystal manufacturers specifica- 1 MHz 15 pF 15 pF tions. When in XT, LP or HS modes, the device can 4 MHz 15 pF 15 pF have an external clock source to drive the OSC1/ CLKIN pin (Figure9-3). HS 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF FIGURE 9-2: CRYSTAL/CERAMIC 20 MHz 15-33 pF 15-33 pF RESONATOR OPERATION These values are for design guidance only. See (HS, XT OR LP notes at bottom of page. OSC CONFIGURATION) C1(1) OSC1 Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table9-1). To 2: Higher capacitance increases the stability XTAL RF(3) intelorngaicl of the oscillator, but also increases the OSC2 Sleep start-up time. RS(2) 3: Since each resonator/crystal has its own C2(1) PIC16C7XX characteristics, the user should consult the resonator/crystal manufacturer for Note 1: See Table9-1 and Table9-2 for appropriate values of external compo- recommended values of C1 and C2. nents. 2: A series resistor (RS) may be required for 4: Rs may be required in HS mode, as well AT strip cut crystals. as XT mode to avoid overdriving crystals 3: RF varies with the crystal chosen. with low drive level specification. FIGURE 9-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock from OSC1 ext. system PIC16C7XX Open OSC2  1999-2013 Microchip Technology Inc. DS41106C-page 53

PIC16C712/716 9.2.3 RC OSCILLATOR 9.3 Reset For timing insensitive applications, the “RC” device The PIC16CXXX differentiates between various kinds option offers additional cost savings. The RC oscillator of Reset: frequency is a function of the supply voltage, the resis- • Power-on Reset (POR) tor (REXT) and capacitor (CEXT) values and the operat- ing temperature. In addition to this, the oscillator • MCLR Reset during normal operation frequency will vary from unit-to-unit due to normal pro- • MCLR Reset during Sleep cess parameter variation. Furthermore, the difference • WDT Reset (during normal operation) in lead frame capacitance between package types will • WDT Wake-up (during Sleep) also affect the oscillation frequency, especially for low • Brown-out Reset (BOR) CEXT values. The user also needs to take into account variation due to tolerance of external R and C Some registers are not affected in any Reset condition; components used. Figure9-4 shows how the R/C their status is unknown on POR and unchanged in any combination is connected to the PIC16CXXX. other Reset. Most other registers are reset to a “Reset state” on Power-on Reset (POR), on the MCLR and FIGURE 9-4: RC OSCILLATOR MODE WDT Reset, on MCLR Reset during Sleep and Brown- out Reset (BOR). They are not affected by a WDT VDD Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different Reset situations as indicated in REXT Internal Table9-4. These bits are used in software to determine OSC1 Clock the nature of the Reset. See Table9-6 for a full description of Reset states of all registers. CEXT PIC16C7XX A simplified block diagram of the on-chip Reset circuit VSS is shown in Figure9-6. OSC2/CLKOUT FOSC/4 The PIC microcontrollers have a MCLR noise filter in Recommended values: 3 k  REXT  100 k the MCLR Reset path. The filter will detect and ignore CEXT > 20pF small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. DS41106C-page 54  1999-2013 Microchip Technology Inc.

PIC16C712/716 9.4 Power-On Reset (POR) 9.5 Power-up Timer (PWRT) A Power-on Reset pulse is generated on-chip when The Power-up Timer provides a fixed nominal time-out VDD rise is detected (to a level of 1.5V-2.1V). To take (parameter #33), on power-up only, from the POR. The advantage of the POR, just tie the MCLR pin directly (or Power-up Timer operates on an internal RC oscillator. through a resistor) to VDD. This will eliminate external The chip is kept in Reset as long as the PWRT is active. RC components usually needed to create a Power-on The PWRT’s time delay allows VDD to rise to an Reset. A maximum rise time for VDD is specified acceptable level. A Configuration bit is provided to (parameter D004). For a slow rise time, see Figure9-5. enable/disable the PWRT. When the device starts normal operation (exits the The power-up time delay will vary from chip to chip due Reset condition), device operating parameters (volt- to VDD, temperature, and process variation. See DC age, frequency, temperature,...) must be met to ensure parameters for details. operation. If these conditions are not met, the device must be held in Reset until the operating conditions are 9.6 Oscillator Start-up Timer (OST) met. Brown-out Reset may be used to meet the start- up conditions. The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the FIGURE 9-5: EXTERNAL POWER-ON PWRT delay is over (parameter #32). This ensures that the crystal oscillator or resonator has started and RESET CIRCUIT (FOR stabilized. SLOW VDD POWER-UP) The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from VDD VDD Sleep. R 9.7 Brown-Out Reset (BOR) R1 MCLR The PIC16C712/716 members have on-chip Brown- C PIC16C7XX out Reset circuitry. A Configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V, refer Note1: External Power-on Reset circuit is to VBOR parameter D005(VBOR) for a time greater than required only if VDD power-up slope is too parameter (TBOR) in Table12-6. The brown-out situa- tion will reset the chip. A Reset is not guaranteed to slow. The diode D helps discharge the capacitor quickly when VDD powers down. occur if VDD falls below 4.0V for less than parameter (TBOR). 2: R < 40 k is recommended to make sure On any Reset (Power-on, Brown-out, Watchdog, etc.) that voltage drop across R does not violate the device’s electrical specification. the chip will remain in Reset until VDD rises above VBOR. The Power-up Timer will now be invoked and will 3: R1 = 100 to 1 k will limit any current keep the chip in Reset an additional 72ms. flowing into MCLR from external capacitor C in the event of MCLR/VPP pin break- If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset down due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-Up Timer will execute a 72ms Reset. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure9-7 shows typical Brown-out situations. For operations where the desired brown-out voltage is other than 4V, an external brown-out circuit must be used. Figure 9-8, 9-9 and 9-10 show examples of external brown-out protection circuits.  1999-2013 Microchip Technology Inc. DS41106C-page 55

PIC16C712/716 FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR SLEEP WDT WDT Module Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset BODEN S OST/PWRT OST Chip_Reset 10-bit Ripple counter R Q OSC1 (1) PWRT On-chip RC OSC 10-bit Ripple counter PWRT See Table 9-3 for time-out Enable PWRT BODEN situations. Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. FIGURE 9-7: BROWN-OUT SITUATIONS VDD VBOR Internal 72 ms Reset VDD VBOR Internal <72 ms 72 ms Reset VDD VBOR Internal 72 ms Reset DS41106C-page 56  1999-2013 Microchip Technology Inc.

PIC16C712/716 FIGURE 9-8: EXTERNAL BROWN-OUT FIGURE 9-10: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 PROTECTION CIRCUIT 3 VDD VDD VDD 33k MCP809 VDD Q1 bypass Vss capacitor 10k MCLR VDD RST 40k PIC16C7XX MCLR PIC16C7XX This brown-out protection circuit employs Microchip Technology’s MCP809 microcontroller Note1: This circuit will activate Reset when supervisor. The MCP8XX and MCP1XX families VDD goes below (Vz + 0.7V) where of supervisors provide push-pull and open Vz=Zener voltage. collector outputs with both high and low active 2: Internal Brown-out Reset circuitry Reset pins. There are 7 different trip point should be disabled when using this selections to accommodate 5V and 3V systems circuit. 9.8 Time-out Sequence FIGURE 9-9: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has VDD VDD expired. Then OST is activated. The total time-out will R1 vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT Q1 disabled, there will be no time-out at all. Figure9-11, MCLR Figure9-12, and Figure9-13 depict time-out R2 40k sequences on power-up. PIC16C7XX Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure9-13). This is useful for testing purposes or to synchronize more than one PIC16CXXX device Note1: This brown-out circuit is less expensive, operating in parallel. albeit less accurate. Transistor Q1 turns off when VDD is below a certain level Table9-5 shows the Reset conditions for some Special such that: Function Registers, while Table9-6 shows the Reset conditions for all the registers. R1 VDD x = 0.7V R1 + R2 2: Internal Brown-out Reset should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.  1999-2013 Microchip Technology Inc. DS41106C-page 57

PIC16C712/716 9.9 Power Control/Status Register The BOR Status bit is a “don’t care” and is not neces- (PCON) sarily predictable if the brown-out circuit is disabled (the BODEN Configuration bit is clear). BOR must then be The Power Control/Status Register, PCON has two set by the user and checked on subsequent Resets to bits. see if it is clear, indicating a brown-out has occurred. Bit 0 is Brown-out Reset Status bit, BOR. If the BODEN Bit 1 is POR (Power-on Reset Status bit). It is cleared Configuration bit is set, BOR is ‘1’ on Power-on Reset. on a Power-on Reset and unaffected otherwise. The If the BODEN Configuration bit is clear, BOR is user must set this bit following a Power-on Reset. unknown on Power-on Reset. TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Wake-up from Oscillator Configuration Brown-out Sleep PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — TABLE 9-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during Sleep or interrupt wake-up from Sleep TABLE 9-5: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 Interrupt wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, – = unimplemented bit read as ‘0’. Note1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). DS41106C-page 58  1999-2013 Microchip Technology Inc.

PIC16C712/716 TABLE 9-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16C712/716 Register Power-on Reset, MCLR Resets Wake-up via WDT or Brown-out Reset WDT Reset Interrupt W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000h 0000h PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA(4) --0x 0000 --xx xxxx --xu uuuu PORTB(5) xxxx xxxx uuuu uuuu uuuu uuuu DATACCP ---- -x-x ---- -u-u ---- -u-u PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 -00x 0000 -00u uuuu -uuu(1) ---- 0000 ---- 0000 ---- uuuu(1) PIR1 -0-- 0000 -0-- 0000 -u-- uuuu(1) TMR1L xxxx xxxx uuuu uuuu uuuu uuuu TMR1H xxxx xxxx uuuu uuuu uuuu uuuu T1CON --00 0000 --uu uuuu --uu uuuu TMR2 0000 0000 0000 0000 uuuu uuuu T2CON -000 0000 -000 0000 -uuu uuuu CCPR1L xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON --00 0000 --00 0000 --uu uuuu ADRES xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 1111 1111 1111 1111 uuuu uuuu TRISA --11 1111 --11 1111 --uu uuuu TRISB 1111 1111 1111 1111 uuuu uuuu TRISCCP xxxx x1x1 xxxx x1x1 xxxx xuxu ---- 0000 ---- 0000 ---- uuuu PIE1 -0-- 0000 -0-- 0000 -u-- uuuu PCON ---- --0q ---- --uq ---- --uq PR2 1111 1111 1111 1111 1111 1111 ADCON1 ---- -000 ---- -000 ---- -uuu Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table9-5 for Reset value for specific condition. 4: On any device Reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch.  1999-2013 Microchip Technology Inc. DS41106C-page 59

PIC16C712/716 FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS41106C-page 60  1999-2013 Microchip Technology Inc.

PIC16C712/716 9.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in The PIC16C712/716 devices have up to 7 sources of the INTCON register. interrupt. The Interrupt Control Register (INTCON) The peripheral interrupt flags are contained in the records individual interrupt requests in flag bits. It also Special Function Registers, PIR1 and PIR2. The corre- has individual and global interrupt enable bits. sponding interrupt enable bits are contained in Special Note: Individual interrupt flag bits are set regard- Function Registers, PIE1 and PIE2, and the peripheral less of the status of their corresponding interrupt enable bit is contained in Special Function mask bit or the GIE bit. Register, INTCON. A Global Interrupt Enable bit, GIE (INTCON<7>) When an interrupt is responded to, the GIE bit is enables (if set) all unmasked interrupts or disables (if cleared to disable any further interrupt, the return cleared) all interrupts. When bit GIE is enabled, and an address is pushed onto the stack and the PC is loaded interrupt’s flag bit and mask bit are set, the interrupt will with 0004h. Once in the Interrupt Service Routine, the vector immediately. Individual interrupts can be source(s) of the interrupt can be determined by polling disabled through their corresponding enable bits in the interrupt flag bits. The interrupt flag bit(s) must be various registers. Individual interrupt bits are set, cleared in software before re-enabling interrupts to regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts. cleared on Reset. For external interrupt events, such as the INT pin or The “return from interrupt” instruction, RETFIE, exits PORTB change interrupt, the interrupt latency will be the interrupt routine, as well as sets the GIE bit, which three or four instruction cycles. The exact latency re-enables interrupts. depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. FIGURE 9-14: INTERRUPT LOGIC Wake-up (If in Sleep mode) T0IF T0IE INTF INTE Interrupt to CPU ADIF RBIF ADIE RBIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE  1999-2013 Microchip Technology Inc. DS41106C-page 61

PIC16C712/716 9.10.1 INT INTERRUPT 9.11 Context Saving During Interrupts External interrupt on RB0/INT pin is edge triggered, During an interrupt, only the return PC value is saved either rising if bit INTEDG (OPTION_REG<6>) is set, on the stack. Typically, users may wish to save key reg- or falling if the INTEDG bit is clear. When a valid edge isters during an interrupt, (i.e., W register and STATUS appears on the RB0/INT pin, flag bit INTF register). This will have to be implemented in software. (INTCON<1>) is set. This interrupt can be disabled by Example9-1 stores and restores the W and STATUS clearing enable bit INTE (INTCON<4>). Flag bit INTF registers. The register, W_TEMP, must be defined in must be cleared in software in the Interrupt Service each bank and must be defined at the same offset from Routine before re-enabling this interrupt. The INT inter- the bank base address (i.e., if W_TEMP is defined at rupt can wake-up the processor from Sleep, if bit INTE 0x20 in bank 0, it must also be defined at 0xA0 in bank was set prior to going into Sleep. The status of global 1). interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following The example: wake-up. See Section9.13 “Power-down Mode a) Stores the W register. (Sleep)” for details on Sleep mode. b) Stores the STATUS register in bank 0. 9.10.2 TMR0 INTERRUPT c) Stores the PCLATH register. d) Executes the Interrupt Service Routine code An overflow (FFh  00h) in the TMR0 register will set (User-generated). flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE e) Restores the STATUS register (and bank select (INTCON<5>). (Section4.0 “Timer0 Module”) bit). f) Restores the W and PCLATH registers. 9.10.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section3.2 “PORTB and the TRISB Register”) EXAMPLE 9-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page BCF STATUS, IRP ;Return to Bank 0 MOVF FSR, W ;Copy FSR to W MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP : :(ISR) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS41106C-page 62  1999-2013 Microchip Technology Inc.

PIC16C712/716 9.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Electrical Specifications section under TWDT (parame- The Watchdog Timer is as a free running, on-chip, RC ter #31). Values for the WDT prescaler (actually a oscillator which does not require any external compo- postscaler, but shared with the Timer0 prescaler) may nents. This RC oscillator is separate from the RC oscil- be assigned using the OPTION_REG register. lator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and Note: The CLRWDT and SLEEP instructions clear OSC2/CLKOUT pins of the device have been stopped, the WDT and the postscaler, if assigned to for example, by execution of a SLEEP instruction. the WDT, and prevent it from timing out and generating a device Reset condition. During normal operation, a WDT Time-out generates a device Reset (Watchdog Timer Reset). If the device is . in Sleep mode, a WDT Time-out causes the device to Note: When a CLRWDT instruction is executed wake-up and continue with normal operation (Watch- and the prescaler is assigned to the WDT, dog Timer Wake-up). The TO bit in the STATUS regis- the prescaler count will be cleared, but the ter will be cleared upon a Watchdog Timer Time-out. prescaler assignment is not changed. The WDT can be permanently disabled by clearing Configuration bit WDTE (Section9.1 “Configuration Bits”). FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure4-2) 0 M Postscaler 1 WDT Timer U X 8 8-to-1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure4-2) 0 1 MUX PSA WDT Note: PSA and PS2:PS0 are bits in the OPTION_REG register. Time-out FIGURE 9-16: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bits 13:8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) — BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h OPTION_REG N/A RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend:Shaded cells are not used by the Watchdog Timer. Note1: See Figure9-1 for operation of these bits.  1999-2013 Microchip Technology Inc. DS41106C-page 63

PIC16C712/716 9.13 Power-down Mode (Sleep) Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or high-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power- down the A/D and the disable external clocks. Pull all I/ O pins, that are high-impedance inputs, high or low externally to avoid switching currents caused by float- ing inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 9.13.1 WAKE-UP FROM SLEEP The device can wake up from Sleep through one of the following events: 1. External Reset input on MCLR pin. 2. Watchdog Timer Wake-up (if WDT was enabled). 3. Interrupt from INT pin, RB port change, or some peripheral interrupts. External MCLR Reset will cause a device Reset. All other events are considered a continuation of program execution and cause a “wake-up”. The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT Time-out occurred (and caused wake-up). The following peripheral interrupts can wake the device from Sleep: 1. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 2. CCP Capture mode interrupt. 3. Special Event Trigger (Timer1 in Asynchronous mode using an external clock). Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. DS41106C-page 64  1999-2013 Microchip Technology Inc.

PIC16C712/716 When the SLEEP instruction is being executed, the next postscaler will not be cleared, the TO bit will not instruction (PC + 1) is pre-fetched. For the device to be set and PD bits will not be cleared. wake-up through an interrupt event, the corresponding • If the interrupt occurs during or after the execu- interrupt enable bit must be set (enabled). Wake-up is tion of a SLEEP instruction, the device will imme- regardless of the state of the GIE bit. If the GIE bit is diately wake-up from Sleep. The SLEEP clear (disabled), the device continues execution at the instruction will be completely executed before the instruction after the SLEEP instruction. If the GIE bit is wake-up. Therefore, the WDT and WDT set (enabled), the device executes the instruction after postscaler will be cleared, the TO bit will be set the SLEEP instruction and then branches to the inter- and the PD bit will be cleared. rupt address (0004h). In cases where the execution of Even if the flag bits were checked before executing a the instruction following SLEEP is not desirable, the SLEEP instruction, it may be possible for flag bits to user should have a NOP after the SLEEP instruction. become set before the SLEEP instruction completes. To 9.13.2 WAKE-UP USING INTERRUPTS determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction When global interrupts are disabled (GIE cleared) and was executed as a NOP. any interrupt source has both its interrupt enable bit To ensure that the WDT is cleared, a CLRWDT instruc- and interrupt flag bit set, one of the following will occur: tion should be executed before a SLEEP instruction. • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT FIGURE 9-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit Processor in (INTCON<7>) Sleep INSTRUCTION FLOW PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h Ifnestctrhuecdtion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Ienxsetrcuuctetidon Inst(PC - 1) Sleep Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC Osc mode. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 9.14 Program Verification/Code 9.15 ID Locations Protection Four memory locations (2000h-2003h) are designated If the code protection bit(s) have not been as ID locations where the user can store checksum or programmed, the on-chip program memory can be other code-identification numbers. These locations are read out for verification purposes. not accessible during normal execution, but are read- able and writable during Program/Verify. It is Note: Microchip does not recommend code recommended that only the 4 Least Significant bits of protecting windowed devices. the ID location are used. For ROM devices, these values are submitted along with the ROM code.  1999-2013 Microchip Technology Inc. DS41106C-page 65

PIC16C712/716 9.16 In-Circuit Serial Programming™ PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details on serial programming, please refer to the In-Circuit Serial Programming™ (ICSP™) Guide, (DS30277). DS41106C-page 66  1999-2013 Microchip Technology Inc.

PIC16C712/716 10.0 INSTRUCTION SET SUMMARY All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- Each PIC16CXXX instruction is a 14-bit word divided gram counter is changed as a result of an instruction. into an OPCODE which specifies the instruction type In this case, the execution takes two instruction cycles and one or more operands which further specify the with the second cycle executed as a NOP. One instruc- operation of the instruction. The PIC16CXXX instruc- tion cycle consists of four oscillator periods. Thus, for tion set summary in Table10-2 lists byte-oriented, bit- an oscillator frequency of 4 MHz, the normal instruction oriented, and literal and control operations. execution time is 1 s. If a conditional test is true or the Table10-1 shows the opcode field descriptions. program counter is changed as a result of an For byte-oriented instructions, ‘f’ represents a file instruction, the instruction execution time is 2 s. register designator and ‘d’ represents a destination Table10-2 lists the instructions recognized by the designator. The file register designator specifies which MPASM assembler. file register is to be used by the instruction. Figure10-1 shows the general formats that the The destination designator specifies where the result of instructions can have. the operation is to be placed. If ‘d’ is zero, the result is Note: To maintain upward compatibility with placed in the W register. If ‘d’ is one, the result is placed future PIC16CXXX products, do not use in the file register specified in the instruction. the OPTION and TRIS instructions. For bit-oriented instructions, ‘b’ represents a bit field designator which selects the number of the bit affected All examples use the following format to represent a by the operation, while ‘f’ represents the number of the hexadecimal number: file in which the bit is located. 0xhh For literal and control operations, ‘k’ represents an where h signifies a hexadecimal digit. eight or eleven bit constant or literal value. FIGURE 10-1: GENERAL FORMAT FOR TABLE 10-1: OPCODE FIELD INSTRUCTIONS DESCRIPTIONS Byte-oriented file register operations Field Description 13 8 7 6 0 OPCODE d f (FILE #) f Register file address (0x00 to 0x7F) W Working register (accumulator) d = 0 for destination W d = 1 for destination f b Bit address within an 8-bit file register f = 7-bit file register address k Literal field, constant data or label x Don’t care location (= 0 or 1) Bit-oriented file register operations The assembler will generate code with x = 0. It is the 13 10 9 7 6 0 recommended form of use for compatibility with all OPCODE b (BIT #) f (FILE #) Microchip software tools. d Destination select; d = 0: store result in W, b = 3-bit bit address d = 1: store result in file register f. f = 7-bit file register address Default is d = 1 PC Program Counter Literal and control operations TO Time-out bit PD Power-down bit General Z Zero bit 13 8 7 0 DC Digit Carry bit OPCODE k (literal) C Carry bit k = 8-bit immediate value The instruction set is highly orthogonal and is grouped into three basic categories: CALL and GOTO instructions only • Byte-oriented operations 13 11 10 0 • Bit-oriented operations OPCODE k (literal) • Literal and control operations k = 11-bit immediate value A description of each instruction is available in the PIC® Mid-Range Reference Manual, (DS33023).  1999-2013 Microchip Technology Inc. DS41106C-page 67

PIC16C712/716 TABLE 10-2: PIC16CXXX INSTRUCTION SET Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0000 0011 Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS41106C-page 68  1999-2013 Microchip Technology Inc.

PIC16C712/716 11.0 DEVELOPMENT SUPPORT 11.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- • Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB ICE 4000 In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive on-line help • Low-Cost Demonstration and Development • Integration of select third party tools, such as Boards and Evaluation Kits HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  1999-2013 Microchip Technology Inc. DS41106C-page 69

PIC16C712/716 11.2 MPASM Assembler 11.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 11.6 MPLAB SIM Software Simulator 11.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 family of microcontrollers and a comprehensive stimulus controller. Registers can be dsPIC30F family of digital signal controllers. These logged to files for further run-time analysis. The trace compilers provide powerful integration capabilities, buffer and logic analyzer display extend the power of superior code optimization and ease of use not found the simulator to record and track program execution, with other compilers. actions on I/O, as well as internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 11.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41106C-page 70  1999-2013 Microchip Technology Inc.

PIC16C712/716 11.7 MPLAB ICE 2000 11.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC micro- PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes controllers. Software control of the MPLAB ICE 2000 the in-circuit debugging capability built into theFlash In-Circuit Emulator is advanced by the MPLAB Inte- devices. This feature, along with Microchip’s In-Circuit grated Development Environment, which allows edit- Serial ProgrammingTM (ICSPTM) protocol, offers cost- ing, building, downloading and source debugging from effective, in-circuit Flash debugging from the graphical a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 11.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 11.8 MPLAB ICE 4000 package types. The ICSP™ cable assembly is included High-Performance as a standard item. In Stand-Alone mode, the MPLAB In-Circuit Emulator PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set The MPLAB ICE 4000 In-Circuit Emulator is intended to code protection in this mode. The MPLAB PM3 provide the product development engineer with a connects to the host PC via an RS-232 or USB cable. complete microcontroller design tool set for high-end The MPLAB PM3 has high-speed communications and PIC MCUs and dsPIC DSCs. Software control of the optimized algorithms for quick programming of large MPLAB ICE 4000 In-Circuit Emulator is provided by the memory devices and incorporates an SD/MMC card for MPLAB Integrated Development Environment, which file storage and secure data applications. allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed perfor- mance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, and up to 2 Mb of emulation memory. The MPLAB ICE 4000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.  1999-2013 Microchip Technology Inc. DS41106C-page 71

PIC16C712/716 11.11 PICSTART Plus Development 11.12 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demon- stration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart® battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. DS41106C-page 72  1999-2013 Microchip Technology Inc.

PIC16C712/716 12.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Voltage on RA4 with respect to Vss...............................................................................................................0V to +8.5V Total power dissipation (Note 1) (PDIP and SOIC)...................................................................................................1.0W Total power dissipation (Note 1) (SSOP)................................................................................................................0.65W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA and PORTB (combined).................................................................................200 mA Maximum current sourced by PORTA and PORTB (combined)...........................................................................200 mA Note1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  1999-2013 Microchip Technology Inc. DS41106C-page 73

PIC16C712/716 FIGURE 12-1: PIC16C712/716 VOLTAGE-FREQUENCY GRAPH, -40°C < TA < +125°C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 30 40 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC16LC712/716 VOLTAGE-FREQUENCY GRAPH, 0°C < TA < +70°C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41106C-page 74  1999-2013 Microchip Technology Inc.

PIC16C712/716 12.1 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial DC CHARACTERISTICS -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage 4.0 — 5.5 V XT, RC and LP osc mode D001A 4.5 — 5.5 V HS osc mode VBOR* — 5.5 V BOR enabled(7) D002* VDR RAM Data Retention Voltage(1) — 1.5 — V D003 VPOR VDD Start Voltage to ensure inter- — VSS — V See section on Power-on Reset for details nal Power-on Reset signal D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms PWRT enabled (PWRTE bit clear) D004A* Power-on Reset signal TBD — — PWRT disabled (PWRTE bit set) See section on Power-on Reset for details D005 VBOR Brown-out Reset 3.65 — 4.35 V BODEN bit set voltage trip point D010 IDD Supply Current(2,5) — 0.8 2.5 mA FOSC = 4 MHz, VDD = 4.0V D013 — 4.0 8.0 mA FOSC = 20 MHz, VDD = 4.0V D020 IPD Power-down Current(3,5) — 10.5 42 A VDD = 4.0V, WDT enabled,-40C to +85C — 1.5 16 A VDD = 4.0V, WDT disabled, 0C to +70C D021 — 1.5 19 A VDD = 4.0V, WDT disabled,-40C to +85C D021B — 2.5 19 A VDD = 4.0V, WDT disabled,-40C to +125C Module Differential Current(6) D022* IWDT Watchdog Timer — 6.0 20 A WDTE bit set, VDD = 4.0V D022A* IBOR Brown-out Reset — TBD 200 A BODEN bit set, VDD = 5.0V 1A FOSC LP Oscillator Operating Frequency 0 — 200 KHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS. 4: For RC Osc mode, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to this trip point.  1999-2013 Microchip Technology Inc. DS41106C-page 75

PIC16C712/716 12.2 DC Characteristics:PIC16LC712/716-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial Param Sym. Characteristic Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage 2.5 — 5.5 V VBOR* — 5.5 V BOR enabled (Note 7) D002* VDR RAM Data Retention Voltage(1) — 1.5 — V D003 VPOR VDD Start Voltage to ensure inter- — VSS — V See section on Power-on Reset for details nal Power-on Reset signal D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms PWRT enabled (PWRTE bit clear) D004A* Power-on Reset signal TBD — — PWRT disabled (PWRTE bit set) See section on Power-on Reset for details D005 VBOR Brown-out Reset 3.65 — 4.35 V BODEN bit set voltage trip point D010 IDD Supply Current(2,5) — 2.0 3.8 mA XT, RC osc modes FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A — 22.5 48 A LP osc mode FOSC = 32 kHz, VDD = 3.0V, WDT disabled D020 IPD Power-down Current(3,5) — 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D021 — 0.9 5 A VDD = 3.0V, WDT disabled, 0C to +70C D021A — 0.9 5 A VDD = 3.0V, WDT disabled, -40C to +85C Module Differential Current(6) D022* IWDT Watchdog Timer — 6.0 20 A WDTE bit set, VDD = 4.0V D022A* IBOR Brown-out Reset — TBD 200 A BODEN bit set, VDD = 5.0V 1A FOSC LP Oscillator Operating Frequency 0 — 200 KHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD and VSS. 4: For RC Osc mode, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will operate correctly to this trip point. DS41106C-page 76  1999-2013 Microchip Technology Inc.

PIC16C712/716 12.3 DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712716-20 (Commercial, Industrial, Extended) PIC16LC712/716-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended DC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section12.1 “DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended)” and Section12.2 “DC Characteristics: PIC16LC712/ 716-04 (Commercial, Industrial)” Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Input Low Voltage VIL I/O ports D030 with TTL buffer VSS — 0.8V V 4.5V  VDD  5.5V D030A VSS — 0.15VDD V otherwise D031 with Schmitt Trigger buffer VSS — 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss — 0.2VDD V D033 OSC1 (in XT, HS and LP Vss — 0.3VDD V (Note 1) modes) Input High Voltage VIH I/O ports — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD  5.5V D040A 0.25VDD — VDD V otherwise + 0.8V D041 with Schmitt Trigger buffer 0.8VDD — VDD V For entire VDD range D042 MCLR 0.8VDD — VDD V D042A OSC1 (XT, HS and LP modes) 0.7VDD — VDD V (Note 1) D043 OSC1 (in RC mode) 0.9VDD — VDD V Input Leakage Current (Notes 2, 3) D060 IIL I/O ports — — 1 A Vss VPIN VDD, Pin at high-impedance D061 MCLR, RA4/T0CKI — — 5 A Vss VPIN VDD D063 OSC1 — — 5 A Vss VPIN VDD, XT, HS and LP osc modes D070 IPURB PORTB weak pull-up current 50 250 400 A VDD = 5V, VPIN = VSS * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC MCU be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1999-2013 Microchip Technology Inc. DS41106C-page 77

PIC16C712/716 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended DC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section12.1 “DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended)” and Section12.2 “DC Characteristics: PIC16LC712/ 716-04 (Commercial, Industrial)” Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Output Low Voltage D080 VOL I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C D083 OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC Osc mode) -40C to +85C — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C Output High Voltage D090 VOH I/O ports (Note 3) VDD-0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C VDD-0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C D092 OSC2/CLKOUT (RC Osc VDD-0.7 — — V IOH = -1.3 mA, VDD = 4.5V, mode) -40C to +85C VDD-0.7 — — V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C D150* VOD Open-Drain High Voltage — — 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 CIO All I/O pins and OSC2 (in RC — — 50 pF mode) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC MCU be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS41106C-page 78  1999-2013 Microchip Technology Inc.

PIC16C712/716 12.4 AC (Timing) Characteristics 12.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance  1999-2013 Microchip Technology Inc. DS41106C-page 79

PIC16C712/716 12.4.2 TIMING CONDITIONS The temperature and voltages specified in Table12-1 apply to all timing specifications, unless otherwise noted. Figure12-3 specifies the load conditions for the timing specifications. TABLE 12-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended AC CHARACTERISTICS Operating voltage VDD range as described in DC spec Section12.1 “DC Characteristics: PIC16C712/716-04 (Commercial, Industrial, Extended) PIC16C712/716-20 (Commercial, Industrial, Extended)” and Section12.2 “DC Characteristics: PIC16LC712/716-04 (Com- mercial, Industrial)”. LC parts operate for commercial/industrial temp’s only. FIGURE 12-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS CL Legend: Pin RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKOUT 15 pF for OSC2 output DS41106C-page 80  1999-2013 Microchip Technology Inc.

PIC16C712/716 12.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 12-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 12-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 1A FOSC External CLKIN Frequency DC — 4 MHz RC and XT osc modes (Note 1) DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 TOSC External CLKIN Period 250 — — ns RC and XT osc modes (Note 1) 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3* TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4* TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.  1999-2013 Microchip Technology Inc. DS41106C-page 81

PIC16C712/716 FIGURE 12-5: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure12-3 for load conditions. TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1¦ to CLKOUT¦ — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT Ø to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT ¦ Tosc + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT ¦ 0 — — ns Note 1 17* TosH2ioV OSC1¦ (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1¦ (Q2 cycle) to Port input Standard 100 — — ns 18A* invalid (I/O in hold time) Extended (LC) 200 — — ns 19* TioV2osH Port input valid to OSC1¦ (I/O in setup time) 0 — — ns 20* TioR Port output rise time Standard — 10 40 ns 20A* Extended (LC) — — 80 ns 21* TioF Port output fall time Standard — 10 40 ns 21A* Extended (LC) — — 80 ns 22††* TINP INT pin high or low time TCY — — ns 23††* TRBP RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. DS41106C-page 82  1999-2013 Microchip Technology Inc.

PIC16C712/716 FIGURE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure12-3 for load conditions. FIGURE 12-7: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* TWDT Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +125°C (No Prescaler) 32 TOST Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* TPWRT Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34 TIOZ I/O High-impedance from MCLR — — 2.1 s Low or WDT Reset 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  BVDD (D005) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1999-2013 Microchip Technology Inc. DS41106C-page 83

PIC16C712/716 FIGURE 12-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure12-3 for load conditions. TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4,..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, Standard 15 — — ns parameter 47 Prescaler = Extended (LC) 25 — — ns 2,4,8 Asynchronous Standard 30 — — ns Extended (LC) 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, Standard 15 — — ns parameter 47 Prescaler = Extended (LC) 25 — — ns 2,4,8 Asynchronous Standard 30 — — ns Extended (LC) 50 — — ns 47* Tt1P T1CKI input period Synchronous Standard Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N Extended (LC) Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous Standard 60 — — ns Extended (LC) 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41106C-page 84  1999-2013 Microchip Technology Inc.

PIC16C712/716 FIGURE 12-9: CAPTURE/COMPARE/PWM TIMINGS CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure12-3 for load conditions. TABLE 12-6: CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym. Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 input low No Prescaler 0.5TCY + 20 — — ns time With Prescaler Standard 10 — — ns Extended (LC) 20 — — ns 51* TccH CCP1 input high No Prescaler 0.5TCY + 20 — — ns time With Prescaler Standard 10 — — ns Extended (LC) 20 — — ns 52* TccP CCP1 input period 3TCY + 40 — — ns N = prescale value N (1,4, or 16) 53* TccR CCP1 output rise time Standard — 10 25 ns Extended (LC) — 25 45 ns 54* TccF CCP1 output fall time Standard — 10 25 ns Extended (LC) — 25 45 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1999-2013 Microchip Technology Inc. DS41106C-page 85

PIC16C712/716 TABLE 12-7: A/D CONVERTER CHARACTERISTICS: PIC16C712/716-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C712/716-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC712/716-04 (COMMERCIAL, INDUSTRIAL) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. A01 NR Resolution — — 8-bits bit VREF = VDD = 5.12V, VSS £ VAIN £ VREF A02 EABS Total Absolute error — — < ± 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V, VSS £ VAIN £ VREF A10 — Monotonicity — guaranteed — — VSS £ VAIN £ VREF (Note 3) A20 VREF Reference voltage 2.5V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 k analog voltage source A40 IAD A/D conversion cur- Standard — 180 — A Average current consump- rent (VDD) Extended (LC) — 90 — A tion when A/D is on. (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section9.1 “Configuration Bits”. — — 10 A During A/D Conversion cycle 2: * These parameters are characterized but not tested. 3: † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes. DS41106C-page 86  1999-2013 Microchip Technology Inc.

PIC16C712/716 FIGURE 12-10: A/D CONVERSION TIMING BSF ADCON0, GO 1 Tcy 134 (TOSC/2) (1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 12-8: A/D CONVERSION REQUIREMENTS Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 130 TAD A/D clock period Standard 1.6 — — s TOSC based, VREF  3.0V Extended (LC) 2.0 — — s TOSC based, VREF full range Standard 2.0 4.0 6.0 s A/D RC Mode Extended (LC) 3.0 6.0 9.0 s A/D RC Mode 131 TCNV Conversion time (not including S/H time) 11 — 11 TAD (Note 1) 132 TACQ Acquisition time (Note 2) 20 — s 5* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 20.0mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert Æ sample time 1.5 § — — TAD : * These parameters are characterized but not tested. : † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. : §This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section9.1 “Configuration Bits” for min. conditions.  1999-2013 Microchip Technology Inc. DS41106C-page 87

PIC16C712/716 NOTES: DS41106C-page 88  1999-2013 Microchip Technology Inc.

PIC16C712/716 13.0 PACKAGING INFORMATION 13.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16C716-04/P XXXXXXXXXXXXXXXXX 0510017 YYWWNNN 18-Lead CERDIP Windowed Example XXXXXXXX PIC16C XXXXXXXX 716/JW YYWWNNN 0510017 18-Lead SOIC (.300”) Example XXXXXXXXXXXX PIC16C712-20 XXXXXXXXXXXX /SO XXXXXXXXXXXX 0510017 YYWWNNN 20-Lead SSOP Example XXXXXXXXXXX PIC16C712 XXXXXXXXXXX -20I/SS YYWWNNN 0510017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  1999-2013 Microchip Technology Inc. DS41106C-page 89

PIC16C712/716 13.2 Package Details The following sections give the technical details of the packages. 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A c L A1 B1  B p eB Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .890 .898 .905 22.61 22.80 22.99 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 DS41106C-page 90  1999-2013 Microchip Technology Inc.

PIC16C712/716 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E p E1 D 2 B n 1 h  45 c A A2   L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .291 .295 .299 7.39 7.49 7.59 Overall Length D .446 .454 .462 11.33 11.53 11.73 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle  0 4 8 0 4 8 Lead Thickness c .009 .011 .012 0.23 0.27 0.30 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top  0 12 15 0 12 15 Mold Draft Angle Bottom  0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051  1999-2013 Microchip Technology Inc. DS41106C-page 91

PIC16C712/716 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 W2 D 2 n 1 W1 E A A2 c L A1 eB B1 B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .170 .183 .195 4.32 4.64 4.95 Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19 Standoff A1 .015 .023 .030 0.38 0.57 0.76 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Ceramic Pkg. Width E1 .285 .290 .295 7.24 7.37 7.49 Overall Length D .880 .900 .920 22.35 22.86 23.37 Tip to Seating Plane L .125 .138 .150 3.18 3.49 3.81 Lead Thickness c .008 .010 .012 0.20 0.25 0.30 Upper Lead Width B1 .050 .055 .060 1.27 1.40 1.52 Lower Lead Width B .016 .019 .021 0.41 0.47 0.53 Overall Row Spacing § eB .345 .385 .425 8.76 9.78 10.80 Window Width W1 .130 .140 .150 3.30 3.56 3.81 Window Length W2 .190 .200 .210 4.83 5.08 5.33 * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010 DS41106C-page 92  1999-2013 Microchip Technology Inc.

PIC16C712/716 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1  c A A2  L A1  Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p .026 0.65 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .322 7.59 7.85 8.18 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .278 .284 .289 7.06 7.20 7.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle  0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072  1999-2013 Microchip Technology Inc. DS41106C-page 93

PIC16C712/716 NOTES: DS41106C-page 94  1999-2013 Microchip Technology Inc.

PIC16C712/716 APPENDIX A: REVISION HISTORY 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These Version Date Revision Description timers are invoked selectively to avoid unneces- sary delays on power-up and wake-up. A 2/99 This is a new data sheet. How- ever, the devices described in this 12. PORTB has weak pull-ups and interrupt on data sheet are the upgrades to change feature. the devices found in the 13. T0CKI pin is also a port pin (RA4) now. PIC16C6X Data Sheet, 14. FSR is made a full eight-bit register. DS30234, and the PIC16C7X 15. “In-circuit serial programming” is made possible. Data Sheet, DS30390. The user can program PIC16CXX devices using B 9/05 Removed Preliminary Status. only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) C 1/13 Added a note to each package and RB7 (data in/out). outline drawing. 16. PCON STATUS register is added with a Power- on Reset Status bit (POR). 17. Code protection scheme is enhanced such that APPENDIX B: CONVERSION portions of the program memory can be CONSIDERATIONS protected, while the remainder is unprotected. 18. Brown-out protection circuitry has been added. There are no previous versions of this device. Controlled by Configuration Word bit BODEN. Brown-out Reset ensures the device is placed in a Reset condition if VDD dips below a fixed APPENDIX C: MIGRATION FROM setpoint. BASE-LINE TO To convert code written for PIC16C5X to PIC16CXXX, MID-RANGE DEVICES the user should take the following steps: 1. Remove any program memory page select This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a mid-range device (i.e., operations (PA2, PA1, PA0 bits) for CALL, GOTO. PIC16CXXX). 2. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits The following are the list of modifications over the are set properly under the new scheme. PIC16C5X microcontroller family: 3. Eliminate any data memory page switching. 1. Instruction word length is increased to 14-bits. Redefine data variables to reallocate them. This allows larger page sizes both in program 4. Verify all writes to STATUS, OPTION, and FSR memory (2K now as opposed to 512 before) and registers since these have changed. register file (128 bytes now versus 32 bytes 5. Change Reset vector to 0000h. before). 2. A PC high latch register (PCLATH) is added to handle program memory paging. Bits PA2, PA1, PA0 are removed from STATUS register. 3. Data memory paging is redefined slightly. STATUS register is modified. 4. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compati- bility with PIC16C5X. 5. OPTION_REG and TRIS registers are made addressable. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8 deep. 8. Reset vector is changed to 0000h. 9. Reset of all registers is revisited. Five different Reset (and wake-up) types are recognized. Registers are reset differently. 10. Wake-up from Sleep through interrupt is added.  1999-2013 Microchip Technology Inc. DS41106C-page 95

PIC16C712/716 NOTES: DS41106C-page 96  1999-2013 Microchip Technology Inc.

PIC16C712/716 INDEX A Enable (CCP1IE Bit).................................................. 16 Flag (CCP1IF Bit)...................................................... 17 A/D..................................................................................... 45 PWM Mode. See PWM A/D Converter Enable (ADIE Bit)............................... 16 Timer Resources....................................................... 39 A/D Converter Flag (ADIF Bit)............................. 17, 47 Timing Diagram......................................................... 85 A/D Converter Interrupt, Configuring .........................47 CCP1CON Register........................................................... 39 ADCON0 Register................................................ 11, 45 CCP1M3:CCP1M0 Bits............................................. 39 ADCON1 Register.......................................... 12, 45, 46 CCP1X:CCP1Y Bits................................................... 39 ADRES Register ............................................11, 45, 47 Code Protection........................................................... 51, 65 Analog Port Pins, Configuring.................................... 49 CP1:CP0 Bits............................................................. 52 Block Diagram............................................................ 47 Compare (CCP Module).................................................... 41 Block Diagram, Analog Input Model........................... 48 Block Diagram ...........................................................41 Channel Select (CHS2:CHS0 Bits)............................ 45 CCP Pin Configuration.............................................. 41 Clock Select (ADCS1:ADCS0 Bits)............................ 45 CCPR1H:CCPR1L Registers.................................... 41 Configuring the Module.............................................. 47 Software Interrupt...................................................... 41 Conversion Clock (Tad)............................................. 49 Special Event Trigger.................................... 34, 41, 50 Conversion Status (GO/DONE Bit)...................... 45, 47 Timer1 Mode Selection.............................................. 41 Conversions............................................................... 50 Configuration Bits.............................................................. 51 Converter Characteristics.......................................... 86 Conversion Considerations ................................................95 Module On/Off (ADON Bit)......................................... 45 Customer Change Notification Service ............................101 Port Configuration Control (PCFG2:PCFG0 Bits)...... 46 Customer Notification Service......................................... 101 Sampling Requirements............................................. 48 Customer Support............................................................ 101 Special Event Trigger (CCP)................................ 41, 50 Timing Diagram.......................................................... 87 D Absolute Maximum Ratings............................................... 73 Data Memory..................................................................... 10 ADCON0 Register........................................................ 11, 45 Bank Select (RP1:RP0 Bits) ................................10, 13 ADCS1:ADCS0 Bits................................................... 45 General Purpose Registers....................................... 10 ADON Bit................................................................... 45 Register File Map...................................................... 10 CHS2:CHS0 Bits........................................................ 45 Special Function Registers........................................ 11 GO/DONE Bit....................................................... 45, 47 DC Characteristics....................................................... 75, 77 ADCON1 Register ..................................................12, 45, 46 Development Support ........................................................69 PCFG2:PCFG0 Bits................................................... 46 Direct Addressing ..............................................................20 ADRES Register ....................................................11, 45, 47 Analog-to-Digital Converter. See A/D Architecture E PIC16C712/716 Block Diagram................................... 5 Electrical Characteristics................................................... 73 Assembler Errata ...................................................................................3 MPASM Assembler.................................................... 70 External Power-on Reset Circuit........................................ 55 B F Banking, Data Memory................................................ 10, 13 Family of Devices BOR. See Brown-out Reset PIC16C7XX................................................................. 2 Brown-Out Reset (BOR).................................................... 55 Firmware Instructions........................................................ 67 Brown-out Reset (BOR)................................... 51, 54, 58, 59 BOR Enable (BODEN Bit).......................................... 52 I BOR Status (BOR Bit)................................................ 18 I/O Ports............................................................................ 21 Timing Diagram.......................................................... 83 ID Locations................................................................. 51, 65 C In-Circuit Serial Programming™ (ICSP™)................... 51, 65 Indirect Addressing............................................................ 20 C Compilers FSR Register................................................. 10, 11, 20 MPLAB C18............................................................... 70 INDF Register............................................................ 11 MPLAB C30............................................................... 70 Instruction Format.............................................................. 67 Capture (CCP Module)...................................................... 40 Instruction Set.................................................................... 67 Block Diagram............................................................ 40 Summary Table......................................................... 68 CCP Pin Configuration............................................... 40 INT Interrupt (RB0/INT). See Interrupt Sources CCPR1H:CCPR1L Registers..................................... 40 INTCON Register......................................................... 11, 15 Changing Between Capture Prescalers..................... 40 GIE Bit....................................................................... 15 Software Interrupt...................................................... 40 INTE Bit..................................................................... 15 Timer1 Mode Selection ..............................................40 INTF Bit..................................................................... 15 Capture/Compare/PWM (CCP).......................................... 39 PEIE Bit..................................................................... 15 Capture Mode. See Capture RBIE Bit..................................................................... 15 CCP1CON Register............................................. 11, 39 RBIF Bit............................................................... 15, 24 CCPR1H Register................................................ 11, 39 T0IE Bit...................................................................... 15 CCPR1L Register................................................ 11, 39 T0IF Bit...................................................................... 15 Compare Mode. See Compare Internet Address...............................................................101  1999-2013 Microchip Technology Inc. DS41106C-page 97

PIC16C712/716 Interrupt Sources.......................................................... 51, 61 XT........................................................................ 53, 58 A/D Conversion Complete......................................... 47 Oscillator, Timer1......................................................... 31, 34 Block Diagram.............................................................61 Oscillator, WDT.................................................................. 63 Capture Complete (CCP)............................................40 P Compare Complete (CCP)......................................... 41 Interrupt-on-Change (RB7:RB4 )............................... 24 Packaging.......................................................................... 89 RB0/INT Pin, External................................................ 62 Details........................................................................ 90 TMR0 Overflow.................................................... 30, 62 Paging, Program Memory.............................................. 9, 19 TMR1 Overflow.................................................... 31, 34 PCON Register............................................................ 18, 58 TMR2 to PR2 Match ..................................................37 BOR Bit...................................................................... 18 TMR2 to PR2 Match (PWM)................................ 36, 42 POR Bit...................................................................... 18 Interrupts, Context Saving During ......................................62 PICSTART Plus Development Programmer...................... 72 Interrupts, Enable Bits PIE1 Register............................................................... 12, 16 A/D Converter Enable (ADIE Bit)............................... 16 ADIE Bit..................................................................... 16 CCP1 Enable (CCP1IE Bit).................................. 16, 40 CCP1IE Bit................................................................ 16 Global Interrupt Enable (GIE Bit)......................... 15, 61 TMR1IE Bit................................................................ 16 Interrupt-on-Change (RB7:RB4) Enable TMR2IE Bit................................................................ 16 (RBIE Bit)..................................................... 15, 62 Pin Functions Peripheral Interrupt Enable (PEIE Bit)....................... 15 MCLR/VPP................................................................... 6 RB0/INT Enable (INTE Bit)........................................ 15 RA0/AN0...................................................................... 6 TMR0 Overflow Enable (T0IE Bit).............................. 15 RA1/AN1...................................................................... 6 TMR1 Overflow Enable (TMR1IE Bit) ........................16 RA2/AN2...................................................................... 6 TMR2 to PR2 Match Enable (TMR2IE Bit)................ 16 RA3/AN3/VREF............................................................. 6 Interrupts, Flag Bits RA4/T0CKI.................................................................. 6 A/D Converter Flag (ADIF Bit)............................. 17, 47 RB0/INT....................................................................... 7 CCP1 Flag (CCP1IF Bit)................................ 17, 40, 41 RB1.............................................................................. 7 Interrupt-on-Change (RB7:RB4) Flag RB2.............................................................................. 7 (RBIF Bit)............................................... 15, 24, 62 RB3.............................................................................. 7 RB0/INT Flag (INTF Bit)............................................. 15 RB4.............................................................................. 7 TMR0 Overflow Flag (T0IF Bit)............................ 15, 62 RB5.............................................................................. 7 TMR1 Overflow Flag (TMR1IF Bit)............................ 17 RB6.............................................................................. 7 TMR2 to PR2 Match Flag (TMR2IF Bit)..................... 17 RB7.............................................................................. 7 VDD.............................................................................. 7 M VSS.............................................................................. 7 Master Clear (MCLR) Pinout Descriptions MCLR Reset, Normal Operation.................... 54, 58, 59 PIC16C712/716 Pinout Description............................. 6 MCLR Reset, Sleep................................................... 59 PIR1 Register.............................................................. 11, 17 MCLR Reset, Sleep............................................. 54, 58 ADIF Bit..................................................................... 17 Memory Organization CCP1IF Bit................................................................. 17 Data Memory............................................................. 10 TMR1IF Bit................................................................. 17 Program Memory......................................................... 9 TMR2IF Bit .................................................................17 Microchip Internet Web Site............................................. 101 Pointer, FSR...................................................................... 20 MPLAB ASM30 Assembler, Linker, Librarian.................... 70 POR. See Power-on Reset MPLAB ICD 2 In-Circuit Debugger..................................... 71 PORTA MPLAB ICE 2000 High-Performance Universal Initialization................................................................ 21 In-Circuit Emulator..................................................... 71 PORTA Register.................................................. 11, 21 MPLAB ICE 4000 High-Performance Universal RA3:RA0 Port Pins.................................................... 21 In-Circuit Emulator..................................................... 71 RA4/T0CKI Pin.......................................................... 22 MPLAB Integrated Development Environment Software... 69 TRISA Register.................................................... 12, 21 MPLAB PM3 Device Programmer...................................... 71 PORTB MPLINK Object Linker/MPLIB Object Librarian................. 70 Block Diagram of RB1/T1OSO/T1CKI Pin................. 24 Block Diagram of RB2/T10SI Pin............................... 25 O Block Diagram of RB3/CCP1 Pin ...............................25 OPCODE Field Descriptions.............................................. 67 Initialization................................................................ 23 OPTION_REG Register............................................... 12, 14 PORTB Register.................................................. 11, 23 INTEDG Bit................................................................ 14 Pull-up Enable (RBPU Bit)......................................... 14 PS2:PS0 Bits....................................................... 14, 29 RB0/INT Edge Select (INTEDG Bit).......................... 14 PSA Bit................................................................. 14, 29 RB0/INT Pin, External................................................ 62 RBPU Bit.................................................................... 14 RB3:RB0 Port Pins.................................................... 23 T0CS Bit............................................................... 14, 29 RB7:RB4 Interrupt-on-Change.................................. 62 T0SE Bit................................................................14, 29 RB7:RB4 Interrupt-on-Change Enable (RBIE Bit) 15, 62 Oscillator Configuration................................................ 51, 53 RB7:RB4 Interrupt-on-Change Flag HS........................................................................ 53, 58 (RBIF Bit)............................................... 15, 24, 62 LP......................................................................... 53, 58 RB7:RB4 Port Pins.................................................... 26 RC.................................................................. 53, 54, 58 TRISB Register.................................................... 12, 23 Selection (FOSC1:FOSC0 Bits)................................. 52 DS41106C-page 98  1999-2013 Microchip Technology Inc.

PIC16C712/716 PORTC Brown-out Reset (BOR). See Brown-out Reset (BOR) TRISC Register.......................................................... 12 MCLR Reset. See MCLR Postscaler, Timer2 Power-on Reset (POR). See Power-on Reset (POR) Select (TOUTPS3:TOUTPS0 Bits)............................ 36 Reset Conditions for All Registers............................. 59 Postscaler, WDT................................................................ 29 Reset Conditions for PCON Register........................ 58 Assignment (PSA Bit).......................................... 14, 29 Reset Conditions for Program Counter .....................58 Block Diagram............................................................ 30 Reset Conditions for STATUS Register ....................58 Rate Select (PS2:PS0 Bits)................................. 14, 29 Timing Diagram .........................................................83 Switching Between Timer0 and WDT........................ 30 WDT Reset. See Watchdog Timer (WDT) Power-down Mode. See Sleep Revision History .................................................................95 Power-on Reset (POR).............................. 51, 54, 55, 58, 59 S Oscillator Start-up Timer (OST)........................... 51, 55 POR Status (POR Bit)................................................ 18 Sleep................................................................................. 64 Power Control (PCON) Register................................ 58 Sleep........................................................................... 51, 54 Power-down (PD Bit)........................................... 13, 54 Software Simulator (MPLAB SIM)..................................... 70 Power-on Reset Circuit, External............................... 55 Special Event Trigger. See Compare Power-up Timer (PWRT)..................................... 51, 55 Special Features of the CPU............................................. 51 PWRT Enable (PWRTE Bit)....................................... 52 Special Function Registers................................................ 11 Time-out (TO Bit)................................................. 13, 54 Speed, Operating................................................................ 1 Time-out Sequence.................................................... 57 Stack.................................................................................. 19 Time-out Sequence on Power-up.............................. 60 STATUS Register.................................................. 11, 13, 62 Timing Diagram.......................................................... 83 C Bit ...........................................................................13 Prescaler, Capture............................................................. 40 DC Bit........................................................................ 13 Prescaler, Timer0............................................................... 29 IRP Bit....................................................................... 13 Assignment (PSA Bit).......................................... 14, 29 PD Bit.................................................................. 13, 54 Block Diagram............................................................ 30 RP1:RP0 Bits............................................................. 13 Rate Select (PS2:PS0 Bits)................................. 14, 29 TO Bit.................................................................. 13, 54 Switching Between Timer0 and WDT........................ 30 Z Bit........................................................................... 13 Prescaler, Timer1............................................................... 32 T Select (T1CKPS1:T1CKPS0 Bits).............................. 31 Prescaler, Timer2............................................................... 42 T1CON Register.......................................................... 11, 31 Select (T2CKPS1:T2CKPS0 Bits).............................. 36 T1CKPS1:T1CKPS0 Bits........................................... 31 Product Identification System.......................................... 103 T1OSCEN Bit............................................................ 31 Program Counter T1SYNC Bit............................................................... 31 PCL Register........................................................ 11, 19 TMR1CS Bit............................................................... 31 PCLATH Register.......................................... 11, 19, 62 TMR1ON Bit.............................................................. 31 Reset Conditions........................................................ 58 T2CON Register.......................................................... 11, 36 Program Memory................................................................. 9 T2CKPS1:T2CKPS0 Bits........................................... 36 Interrupt Vector ............................................................9 TMR2ON Bit ..............................................................36 Paging.................................................................... 9, 19 TOUTPS3:TOUTPS0 Bits......................................... 36 Program Memory Map................................................. 9 Timer0............................................................................... 29 Reset Vector................................................................ 9 Block Diagram ...........................................................29 Program Verification.......................................................... 65 Clock Source Edge Select (T0SE Bit)................. 14, 29 Programming, Device Instructions..................................... 67 Clock Source Select (T0CS Bit).......................... 14, 29 PWM (CCP Module).......................................................... 42 Overflow Enable (T0IE Bit)........................................ 15 Block Diagram............................................................ 42 Overflow Flag (T0IF Bit)...................................... 15, 62 CCPR1H:CCPR1L Registers..................................... 42 Overflow Interrupt ................................................30, 62 Duty Cycle.................................................................. 42 Prescaler. See Prescaler, Timer0 Example Frequencies/Resolutions............................ 43 Timing Diagram......................................................... 84 Output Diagram.......................................................... 42 TMR0 Register.......................................................... 11 Period......................................................................... 42 Timer1............................................................................... 31 Set-Up for PWM Operation........................................ 43 Block Diagram........................................................... 32 TMR2 to PR2 Match ............................................36, 42 Capacitor Selection................................................... 34 TMR2 to PR2 Match Enable (TMR2IE Bit)................ 16 Clock Source Select (TMR1CS Bit)........................... 31 TMR2 to PR2 Match Flag (TMR2IF Bit) .....................17 External Clock Input Sync (T1SYNC Bit) ...................31 Module On/Off (TMR1ON Bit)................................... 31 Q Oscillator.............................................................. 31, 34 Q-Clock.............................................................................. 42 Oscillator Enable (T1OSCEN Bit) ..............................31 Overflow Enable (TMR1IE Bit).................................. 16 R Overflow Flag (TMR1IF Bit)....................................... 17 RAM. See Data Memory Overflow Interrupt................................................ 31, 34 Reader Response............................................................ 104 Prescaler. See Prescaler, Timer1 Register File....................................................................... 10 Special Event Trigger (CCP)............................... 34, 41 Register File Map............................................................... 10 T1CON Register.................................................. 11, 31 Reset ............................................................................51, 54 Timing Diagram......................................................... 84 Block Diagram............................................................ 56 TMR1H Register.................................................. 11, 31  1999-2013 Microchip Technology Inc. DS41106C-page 99

PIC16C712/716 TMR1L Register................................................... 11, 31 W Timer2 W Register......................................................................... 62 Block Diagram............................................................ 36 Wake-up from Sleep.......................................................... 51 Postscaler. See Postscaler, Timer2 Wake-up from Sleep.......................................................... 64 PR2 Register ..................................................12, 36, 42 Interrupts............................................................. 58, 59 Prescaler. See Prescaler, Timer2 MCLR Reset.............................................................. 59 T2CON Register.................................................. 11, 36 Timing Diagram......................................................... 65 TMR2 Register..................................................... 11, 36 WDT Reset ................................................................59 TMR2 to PR2 Match Enable (TMR2IE Bit)................ 16 Watchdog Timer (WDT)............................................... 51, 63 TMR2 to PR2 Match Flag (TMR2IF Bit) .....................17 Block Diagram........................................................... 63 TMR2 to PR2 Match Interrupt........................ 36, 37, 42 Enable (WDTE Bit).............................................. 52, 63 Timing Diagrams Postscaler. See Postscaler, WDT Time-out Sequence on Power-up ..............................60 Programming Considerations.................................... 63 Wake-up from Sleep via Interrupt...............................65 RC Oscillator.............................................................. 63 Timing Diagrams and Specifications.................................. 81 Time-out Period......................................................... 63 A/D Conversion.......................................................... 87 Timing Diagram......................................................... 83 Brown-out Reset (BOR)............................................. 83 WDT Reset, Normal Operation ......................54, 58, 59 Capture/Compare/PWM (CCP).................................. 85 WDT Reset, Sleep......................................... 54, 58, 59 CLKOUT and I/O ........................................................82 WWW Address................................................................ 101 External Clock ............................................................81 WWW, On-Line Support...................................................... 3 Oscillator Start-up Timer (OST)................................. 83 Power-up Timer (PWRT)........................................... 83 Reset.......................................................................... 83 Timer0 and Timer1..................................................... 84 Watchdog Timer (WDT)............................................. 83 DS41106C-page 100  1999-2013 Microchip Technology Inc.

PIC16C712/716 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  1999-2013 Microchip Technology Inc. DS41106C-page 101

PIC16C712/716 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16C712/716 Literature Number: DS41106C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41106C-page 102  1999-2013 Microchip Technology Inc.

PIC16C712/716 PIC16C712/716 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XX X /XX XXX Examples: Device Frequency Temperature Package Pattern a) PIC16C716 – 04/P 301 = Commercial temp., Range Range PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. b) PIC16LC712 – 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. Device: PIC16C712(1), PIC16C712T(2);VDD range 4.0V to 5.5V c) PIC16C712 – 20I/P = Industrial temp., PDIP PPIICC1166LCC771162(1()1,) ,P PICIC161C6L7C176T12(2T);(V2)D;VDD rDa nragneg 4e. 02V.5 tVo t5o. 55V.5V package, 20MHz, normal VDD limits. PIC16LC716(1), PIC16LC716T(2);VDD range 2.5V to 5.5V Frequency Range: 04 = 4 MHz Note1: C = CMOS 20 = 20 MHz LC = Low Power CMOS 2: T = in tape and reel – SOIC, SSOP packages only. Temperature blank = 0C to 70C (Commercial) 3: LC extended temperature device is not Range: I = -40C to +85C (Industrial) offered. E = -40C to +125C (Extended) 4: LC is not offered at 20 MHz Package: JW = Windowed CERDIP SO = SOIC P = PDIP SS = SSOP Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com)  1999-2013 Microchip Technology Inc. DS41106C-page 103

PIC16C712/716 NOTES:  1999-2013 Microchip Technology Inc. DS41106C-page 104

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1999-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769751 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  1999-2013 Microchip Technology Inc. DS41106C-page 105

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 www.microchip.com Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 Atlanta Fax: 61-2-9868-6755 Japan - Osaka Germany - Munich Duluth, GA China - Beijing Tel: 81-6-6152-7160 Tel: 49-89-627-144-0 Tel: 86-10-8569-7000 Fax: 49-89-627-144-44 Tel: 678-957-9614 Fax: 81-6-6152-9310 Fax: 678-957-1455 Fax: 86-10-8528-2104 Japan - Tokyo Italy - Milan China - Chengdu Tel: 39-0331-742611 Boston Tel: 81-3-6880- 3770 Tel: 86-28-8665-5511 Fax: 39-0331-466781 Westborough, MA Fax: 81-3-6880-3771 Tel: 774-760-0087 Fax: 86-28-8665-7889 Korea - Daegu Netherlands - Drunen Fax: 774-760-0088 China - Chongqing Tel: 82-53-744-4301 Tel: 31-416-690399 Chicago Tel: 86-23-8980-9588 Fax: 82-53-744-4302 Fax: 31-416-690340 Itasca, IL Fax: 86-23-8980-9500 Korea - Seoul Spain - Madrid Tel: 630-285-0071 China - Hangzhou Tel: 82-2-554-7200 Tel: 34-91-708-08-90 Fax: 630-285-0075 Tel: 86-571-2819-3187 Fax: 82-2-558-5932 or Fax: 34-91-708-08-91 Cleveland Fax: 86-571-2819-3189 82-2-558-5934 UK - Wokingham Independence, OH China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 44-118-921-5869 Tel: 216-447-0464 Tel: 852-2943-5100 Tel: 60-3-6201-9857 Fax: 44-118-921-5820 Fax: 216-447-0643 Fax: 852-2401-3431 Fax: 60-3-6201-9859 Dallas China - Nanjing Malaysia - Penang Addison, TX Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 60-4-227-4068 Fax: 972-818-2924 China - Qingdao Philippines - Manila Detroit Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Farmington Hills, MI Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Tel: 248-538-2250 Fax: 248-538-2260 China - Shanghai Singapore Tel: 86-21-5407-5533 Tel: 65-6334-8870 Indianapolis Fax: 86-21-5407-5066 Fax: 65-6334-8850 Noblesville, IN Tel: 317-773-8323 China - Shenyang Taiwan - Hsin Chu Fax: 317-773-5453 Tel: 86-24-2334-2829 Tel: 886-3-5778-366 Fax: 86-24-2334-2393 Fax: 886-3-5770-955 Los Angeles Mission Viejo, CA China - Shenzhen Taiwan - Kaohsiung Tel: 949-462-9523 Tel: 86-755-8864-2200 Tel: 886-7-213-7828 Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-7-330-9305 Santa Clara China - Wuhan Taiwan - Taipei Santa Clara, CA Tel: 86-27-5980-5300 Tel: 886-2-2508-8600 Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Fax: 408-961-6445 China - Xian Thailand - Bangkok Toronto Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Mississauga, Ontario, Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Canada China - Xiamen Tel: 905-673-0699 Tel: 86-592-2388138 Fax: 905-673-6509 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 11/29/12 Fax: 86-756-3210049 DS41106C-page 106  1999-2013 Microchip Technology Inc.