PIC16C71X 8-Bit CMOS Microcontrollers with A/D Converter Devices included in this data sheet: PIC16C71X Peripheral Features: • PIC16C710 • Timer0: 8-bit timer/counter with 8-bit prescaler • PIC16C71 • 8-bit multichannel analog-to-digital converter • PIC16C711 • Brown-out detection circuitry for • PIC16C715 Brown-out Reset (BOR) • 13 I/O Pins with Individual Direction Control PIC16C71X Microcontroller Core Features: • High-performance RISC CPU PIC16C7X Features 710 71 711 715 • Only 35 single word instructions to learn Program Memory (EPROM) 512 1K 1K 2K • All single cycle instructions except for program x 14 branches which are two cycle Data Memory (Bytes) x 8 36 36 68 128 • Operating speed: DC - 20 MHz clock input I/O Pins 13 13 13 13 DC - 200 ns instruction cycle • Up to 2K x 14 words of Program Memory, Timer Modules 1 1 1 1 up to 128 x 8 bytes of Data Memory (RAM) A/D Channels 4 4 4 4 • Interrupt capability In-Circuit Serial Programming Yes Yes Yes Yes • Eight level deep hardware stack Brown-out Reset Yes — Yes Yes • Direct, indirect, and relative addressing modes Interrupt Sources 4 4 4 4 • Power-on Reset (POR) • Power-up Timer (PWRT) and Pin Diagrams Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC PDIP, SOIC, Windowed CERDIP oscillator for reliable operation • Programmable code-protection RA2/AN2 • 1 18 RA1/AN1 • Power saving SLEEP mode RA3/AN3/VREF 2 17 RA0/AN0 • Selectable oscillator options RA4/T0CKI 3 PPPP16 OSC1/CLKIN MCLR/VPP 4 ICICICIC15 OSC2/CLKOUT • Low-power, high-speed CMOS EPROM VSS 5 1616161614 VDD technology RB0/INT 6 C7C7C7C713 RB7 RB1 7 111112 RB6 • Fully static design RB2 8 51 011 RB5 RB3 9 10 RB4 • Wide operating voltage range: 2.5V to 6.0V • High Sink/Source Current 25/25 mA • Commercial, Industrial and Extended temperature SSOP ranges • Program Memory Parity Error Checking Circuitry RA2/AN2 • 1 20 RA1/AN1 with Parity Error Reset (PER) (PIC16C715) RA3/AN3/VREF 2 19 RA0/AN0 • Low-power consumption: RA4/T0CKI 3 PPP 18 OSC1/CLKIN - < 2 mA @ 5V, 4 MHz MCLR/VVPSPS 45 IC1IC1IC1 1176 VODSDC2/CLKOUT - 15 m A typical @ 3V, 32 kHz VSS 6 6C6C6C 15 VDD - < 1 m A typical standby current RB0/INT 7 717171 14 RB7 RB1 8 510 13 RB6 RB2 9 12 RB5 RB3 10 11 RB4 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 1

PIC16C71X Table of Contents 1.0 General Description....................................................................................................................................................................3 2.0 PIC16C71X Device Varieties......................................................................................................................................................5 3.0 Architectural Overview................................................................................................................................................................7 4.0 Memory Organization...............................................................................................................................................................11 5.0 I/O Ports....................................................................................................................................................................................25 6.0 Timer0 Module..........................................................................................................................................................................31 7.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................37 8.0 Special Features of the CPU....................................................................................................................................................47 9.0 Instruction Set Summary..........................................................................................................................................................69 10.0 Development Support...............................................................................................................................................................85 11.0 Electrical Characteristics for PIC16C710 and PIC16C711.......................................................................................................89 12.0 DC and AC Characteristics Graphs and Tables for PIC16C710 and PIC16C711..................................................................101 13.0 Electrical Characteristics for PIC16C715................................................................................................................................111 14.0 DC and AC Characteristics Graphs and Tables for PIC16C715............................................................................................125 15.0 Electrical Characteristics for PIC16C71..................................................................................................................................135 16.0 DC and AC Characteristics Graphs and Tables for PIC16C71..............................................................................................147 17.0 Packaging Information............................................................................................................................................................155 Appendix A: ......................................................................................................................................................................................161 Appendix B: Compatibility.................................................................................................................................................................161 Appendix C: What’s New..................................................................................................................................................................162 Appendix D: What’s Changed..........................................................................................................................................................162 Index..................................................................................................................................................................................................163 PIC16C71X Product Identification System.........................................................................................................................................173 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS30272A-page 2 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 1.0 GENERAL DESCRIPTION A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock- The PIC16C71X is a family of low-cost, high-perfor- up. mance, CMOS, fully-static, 8-bit microcontrollers with A UV erasable CERDIP packaged version is ideal for integrated analog-to-digital (A/D) converters, in the code development while the cost-effective One-Time- PIC16CXX mid-range family. Programmable (OTP) version is suitable for production All PIC16/17 microcontrollers employ an advanced in any volume. RISC architecture. The PIC16CXX microcontroller fam- The PIC16C71X family fits perfectly in applications ily has enhanced core features, eight-level deep stack, ranging from security and remote sensors to appliance and multiple internal and external interrupt sources. control and automotive. The EPROM technology The separate instruction and data buses of the Harvard makes customization of application programs (trans- architecture allow a 14-bit wide instruction word with mitter codes, motor speeds, receiver frequencies, etc.) the separate 8-bit wide data. The two stage instruction extremely fast and convenient. The small footprint pipeline allows all instructions to execute in a single packages make this microcontroller series perfect for cycle, except for program branches which require two all applications with space limitations. Low cost, low cycles. A total of 35 instructions (reduced instruction power, high performance, ease of use and I/O flexibility set) are available. Additionally, a large register set gives make the PIC16C71X very versatile even in areas some of the architectural innovations used to achieve a where no microcontroller use has been considered very high performance. before (e.g. timer functions, serial communication, cap- PIC16CXX microcontrollers typically achieve a 2:1 ture and compare, PWM functions and coprocessor code compression and a 4:1 speed improvement over applications). other 8-bit microcontrollers in their class. 1.1 Family and Upward Compatibility The PIC16C710/71 devices have 36 bytes of RAM, the PIC16C711 has 68 bytes of RAM and the PIC16C715 Users familiar with the PIC16C5X microcontroller fam- has 128 bytes of RAM. Each device has 13 I/O pins. In ily will realize that this is an enhanced version of the addition a timer/counter is available. Also a 4-channel PIC16C5X architecture. Please refer to Appendix A for high-speed 8-bit A/D is provided. The 8-bit resolution is a detailed list of enhancements. Code written for the ideally suited for applications requiring low-cost analog PIC16C5X can be easily ported to the PIC16CXX fam- interface, e.g. thermostat control, pressure sensing, ily of devices (Appendix B). etc. 1.2 Development Support The PIC16C71X family has special features to reduce external components, thus reducing cost, enhancing PIC16C71X devices are supported by the complete system reliability and reducing power consumption. line of Microchip Development tools. There are four oscillator options, of which the single pin Please refer to Section 10.0 for more details about RC oscillator provides a low-cost solution, the LP oscil- Microchip’s development tools. lator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 3

PIC16C71X TABLE 1-1: PIC16C71X FAMILY OF DEVICES PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72(1) Maximum Frequency 20 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 512 1K 1K 2K 2K — (x14 words) Memory ROM Program Memory — — — — — 2K (14K words) Data Memory (bytes) 36 36 68 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0, TMR0, TMR1, TMR1, TMR2 TMR2 Capture/Compare/PWM — — — — 1 1 Peripherals Module(s) Serial Port(s) — — — — SPI/I2C SPI/I2C (SPI/I2C, USART) Parallel Slave Port — — — — — — A/D Converter (8-bit) Channels 4 4 4 4 5 5 Interrupt Sources 4 4 4 4 8 8 I/O Pins 13 13 13 13 22 22 Voltage Range (Volts) 2.5-6.0 3.0-6.0 2.5-6.0 2.5-5.5 2.5-6.0 3.0-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Features Brown-out Reset Yes — Yes Yes Yes Yes Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP PIC16C73A PIC16C74A PIC16C76 PIC16C77 Maximum Frequency 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 4K 4K 8K 8K Memory (x14 words) Data Memory (bytes) 192 192 376 376 Timer Module(s) TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR2 TMR2 TMR2 TMR2 Capture/Compare/PWM 2 2 2 2 Peripherals Module(s) Serial Port(s) SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART (SPI/I2C, USART) Parallel Slave Port — Yes — Yes A/D Converter (8-bit) Channels 5 8 5 8 Interrupt Sources 11 12 11 12 I/O Pins 22 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Features Brown-out Reset Yes Yes Yes Yes Packages 28-pin SDIP, 40-pin DIP; 28-pin SDIP, 40-pin DIP; SOIC 44-pin PLCC, SOIC 44-pin PLCC, MQFP, TQFP MQFP, TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capabil- ity. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. DS30272A-page 4 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 2.0 PIC16C71X DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP) Devices A variety of frequency ranges and packaging options are available. Depending on application and production Microchip offers a QTP Programming Service for fac- requirements, the proper device option can be selected tory production orders. This service is made available using the information in the PIC16C71X Product Iden- for users who choose not to program a medium to high tification System section at the end of this data sheet. quantity of units and whose code patterns have stabi- When placing orders, please use that page of the data lized. The devices are identical to the OTP devices but sheet to specify the correct part number. with all EPROM locations and configuration options For the PIC16C71X family, there are two device “types” already programmed by the factory. Certain code and as indicated in the device number: prototype verification procedures apply before produc- tion shipments are available. Please contact your local 1. C, as in PIC16C71. These devices have Microchip Technology sales office for more details. EPROM type memory and operate over the standard voltage range. 2.4 Serialized Quick-Turnaround 2. LC, as in PIC16LC71. These devices have Production (SQTPSM) Devices EPROM type memory and operate over an extended voltage range. Microchip offers a unique programming service where a few user-defined locations in each device are pro- 2.1 UV Erasable Devices grammed with different serial numbers. The serial num- bers may be random, pseudo-random, or sequential. The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot Serial programming allows each device to have a programs. This version can be erased and unique number which can serve as an entry-code, reprogrammed to any of the oscillator modes. password, or ID number. (cid:210) (cid:210) Microchip's PICSTART Plus and PRO MATE II programmers both support programming of the PIC16C71X. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 5

PIC16C71X NOTES: DS30272A-page 6 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 3.0 ARCHITECTURAL OVERVIEW PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. The high performance of the PIC16CXX family can be It performs arithmetic and Boolean functions between attributed to a number of architectural features com- the data in the working register and any register file. monly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, The ALU is 8-bits wide and capable of addition, sub- program and data are accessed from separate memo- traction, shift and logical operations. Unless otherwise ries using separate buses. This improves bandwidth mentioned, arithmetic operations are two's comple- over traditional von Neumann architecture in which pro- ment in nature. In two-operand instructions, typically gram and data are fetched from the same memory one operand is the working register (W register). The using the same bus. Separating program and data other operand is a file register or an immediate con- buses further allows instructions to be sized differently stant. In single operand instructions, the operand is than the 8-bit wide data word. Instruction opcodes are either the W register or a file register. 14-bits wide making it possible to have all single word The W register is an 8-bit working register used for ALU instructions. A 14-bit wide program memory access operations. It is not an addressable register. bus fetches a 14-bit instruction in a single cycle. A two- Depending on the instruction executed, the ALU may stage pipeline overlaps fetch and execution of instruc- affect the values of the Carry (C), Digit Carry (DC), and tions (Example 3-1). Consequently, all instructions (35) Zero (Z) bits in the STATUS register. The C and DC bits execute in a single cycle (200 ns @ 20 MHz) except for operate as a borrow bit and a digit borrow out bit, program branches. respectively, in subtraction. See the SUBLW and SUBWF The table below lists program memory (EPROM) and instructions for examples. data memory (RAM) for each PIC16C71X device. Program Device Data Memory Memory PIC16C710 512 x 14 36 x 8 PIC16C71 1K x 14 36 x 8 PIC16C711 1K x 14 68 x 8 PIC16C715 2K x 14 128 x 8 The PIC16CXX can directly or indirectly address its register files or data memory. All special function regis- ters, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (sym- metrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 7

PIC16C71X FIGURE 3-1: PIC16C71X BLOCK DIAGRAM Device Program Memory Data Memory (RAM) PIC16C710 512 x 14 36 x 8 PIC16C71 1K x 14 36 x 8 PIC16C711 1K x 14 68 x 8 PIC16C715 2K x 14 128 x 8 13 8 PORTA Data Bus Program Counter EPROM RA0/AN0 RA1/AN1 Program 8 Level Stack RAM RA2/AN2 Memory (13-bit) File RA3/AN3/VREF Registers RA4/T0CKI Program Bus 14 RAM Addr (1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 Indirect 8 Addr FSR reg RB7:RB1 STATUS reg 8 3 MUX Power-up Timer Instruction Decode & Oscillator Control Start-up Timer ALU 8 Power-on Timing Reset Generation W reg Watchdog OSC1/CLKIN Timer OSC2/CLKOUT Brown-out Reset(2) Timer0 MCLR VDD, VSS A/D Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C71. DS30272A-page 8 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X TABLE 3-1: PIC16C710/71/711/715 PINOUT DESCRIPTION DIP SSOP SOIC I/O/P Buffer Pin Name Description Pin# Pin#(4) Pin# Type Type OSC1/CLKIN 16 18 16 I ST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 17 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 4 4 4 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0/AN0 17 19 17 I/O TTL RA0 can also be analog input0 RA1/AN1 18 20 18 I/O TTL RA1 can also be analog input1 RA2/AN2 1 1 1 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 2 2 2 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 3 3 3 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software pro- grammed for internal weak pull-up on all inputs. RB0/INT 6 7 6 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 7 8 7 I/O TTL RB2 8 9 8 I/O TTL RB3 9 10 9 I/O TTL RB4 10 11 10 I/O TTL Interrupt on change pin. RB5 11 12 11 I/O TTL Interrupt on change pin. RB6 12 13 12 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock. RB7 13 14 13 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. VSS 5 4, 6 5 P — Ground reference for logic and I/O pins. VDD 14 15, 16 14 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: The PIC16C71 is not available in SSOP package. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 9

PIC16C71X 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining The clock input (from OSC1) is internally divided by An “Instruction Cycle” consists of four Q cycles (Q1, four to generate four non-overlapping quadrature Q2, Q3 and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3 and Q4. Internally, the pro- pipelined such that fetch takes one instruction cycle gram counter (PC) is incremented every Q1, the while decode and execute takes another instruction instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction latched into the instruction register in Q4. The instruc- effectively executes in one cycle. If an instruction tion is decoded and executed during the following Q1 causes the program counter to change (e.g. GOTO) then through Q4. The clocks and instruction execution flow two cycles are required to complete the instruction is shown in Figure 3-2. (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 phase clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30272A-page 10 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 4.0 MEMORY ORGANIZATION FIGURE 4-2: PIC16C71/711 PROGRAM MEMORY MAP AND STACK 4.1 Program Memory Organization PC<12:0> The PIC16C71X family has a 13-bit program counter capable of addressing an 8K x 14 program memory CALL, RETURN 13 space. The amount of program memory available to RETFIE, RETLW each device is listed below: Stack Level 1 Program Device Address Range Memory PIC16C710 512 x 14 0000h-01FFh Stack Level 8 PIC16C71 1K x 14 0000h-03FFh PIC16C711 1K x 14 0000h-03FFh Reset Vector 0000h PIC16C715 2K x 14 0000h-07FFh y For those devices with less than 8K program memory, or aacdcderessssin wg iall lcoacuastieo na awbroavpea rtohuen pdh. ysically implemented Mempace Interrupt Vector 0004h er S On-chip Program 0005h The reset vector is at 0000h and the interrupt vector is s U Memory at 0004h. 03FFh FIGURE 4-1: PIC16C710 PROGRAM 0400h MEMORY MAP AND STACK PC<12:0> 1FFFh CALL, RETURN 13 RETFIE, RETLW FIGURE 4-3: PIC16C715 PROGRAM MEMORY MAP AND STACK Stack Level 1 PC<12:0> CALL, RETURN 13 Stack Level 8 RETFIE, RETLW Stack Level 1 Reset Vector 0000h y more Stack Level 8 Meac Interrupt Vector 0004h p ser S On-chip Program 0005h Reset Vector 0000h U Memory 01FFh 0200h Interrupt Vector 0004h 0005h 1FFFh On-chip Program Memory 07FFh 0800h 1FFFh (cid:211) 1997 Microchip Technology Inc. DS30272A-page 11

PIC16C71X 4.2 Data Memory Organization FIGURE 4-4: PIC16C710/71 REGISTER FILE MAP The data memory is partitioned into two Banks which contain the General Purpose Registers and the Special Function Registers. Bit RP0 is the bank select bit. File File RP0 (STATUS<5>) = 1 fi Bank 1 Address Address RP0 (STATUS<5>) = 0 fi Bank 0 00h INDF(1) INDF(1) 80h 01h TMR0 OPTION 81h Each Bank extends up to 7Fh (128 bytes). The lower 02h PCL PCL 82h locations of each Bank are reserved for the Special Function Registers. Above the Special Function Regis- 03h STATUS STATUS 83h ters are General Purpose Registers implemented as 04h FSR FSR 84h static RAM. Both Bank 0 and Bank 1 contain special 05h PORTA TRISA 85h function registers. Some "high use" special function 06h PORTB TRISB 86h registers from Bank 0 are mirrored in Bank 1 for code 07h PCON(2) 87h reduction and quicker access. 08h ADCON0 ADCON1 88h 4.2.1 GENERAL PURPOSE REGISTER FILE 09h ADRES ADRES 89h 0Ah PCLATH PCLATH 8Ah The register file can be accessed either directly, or indi- 0Bh INTCON INTCON 8Bh rectly through the File Select Register FSR 0Ch 8Ch (Section 4.5). General Purpose General Register Purpose Register Mapped in Bank 0(3) 2Fh AFh 30h B0h 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: The PCON register is not implemented on the PIC16C71. 3: These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register. DS30272A-page 12 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X FIGURE 4-5: PIC16C711 REGISTER FILE FIGURE 4-6: PIC16C715 REGISTER FILE MAP MAP File File File File Address Address Address Address 00h INDF(1) INDF(1) 80h 00h INDF(1) INDF(1) 80h 01h TMR0 OPTION 81h 01h TMR0 OPTION 81h 02h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h 07h 87h 07h PCON 87h 08h 88h 08h ADCON0 ADCON1 88h 09h 89h 09h ADRES ADRES 89h 0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Ch 8Ch General 0Dh 8Dh Purpose General Register 0Eh PCON 8Eh Purpose 0Fh 8Fh Register Mapped 10h 90h in Bank 0(2) 11h 91h 4Fh CFh 12h 92h 50h D0h 13h 93h 14h 94h 15h 95h 16h 96h 17h 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 7Fh FFh 1Ch 9Ch Bank 0 Bank 1 1Dh 9Dh 1Eh ADRES 9Eh Unimplemented data memory locations, read 1Fh ADCON0 ADCON1 9Fh as '0'. Note 1: Not a physical register. 20h A0h 2: These locations are unimplemented in Bank 1. General General Purpose Purpose Any access to these locations will access the Register Register corresponding Bank 0 register. BFh C0h 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 13

PIC16C71X 4.2.2 SPECIAL FUNCTION REGISTERS The special function registers can be classified into two sets (core and peripheral). Those registers associated The Special Function Registers are registers used by with the “core” functions are described in this section, the CPU and Peripheral Modules for controlling the and those related to the operation of the peripheral fea- desired operation of the device. These registers are tures are described in the section of that peripheral implemented as static RAM. feature. TABLE 4-1: PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR (1) Bank 0 00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(3) STATUS IRP(5) RP1(5) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(3) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — — PORTA Data Latch when written: PORTA pins when read ---x 0000 ---u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h — Unimplemented — — 08h ADCON0 ADCS1 ADCS0 (6) CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000 09h(3) ADRES A/D Result Register xxxx xxxx uuuu uuuu 0Ah(2,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(3) INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Bank 1 80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(3) STATUS IRP(5) RP1(5) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(3) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111 86h TRISB PORTB Data Direction Control Register 1111 1111 1111 1111 87h(4) PCON — — — — — — POR BOR ---- --qq ---- --uu 88h ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00 89h(3) ADRES A/D Result Register xxxx xxxx uuuu uuuu 8Ah(2,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(3) INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: These registers can be addressed from either bank. 4: The PCON register is not physically implemented in the PIC16C71, read as ’0’. 5: The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear. 6: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented, read as '0'. DS30272A-page 14 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X TABLE 4-2: PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR, PER (3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — — PORTA Data Latch when written: PORTA pins when read ---x 0000 ---u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — — — — -0-- ---- -0-- ---- 0Dh — Unimplemented — — 0Eh — Unimplemented — — 0Fh — Unimplemented — — 10h — Unimplemented — — 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 15

PIC16C71X TABLE 4-2: PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d) Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR, PER (3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 — ADIE — — — — — — -0-- ---- -0-- ---- 8Dh — Unimplemented — — 8Eh PCON MPEEN — — — — PER POR BOR u--- -1qq u--- -1uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear. DS30272A-page 16 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 4.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Applicable Devices 710 71 711 715 STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For The STATUS register, shown in Figure 4-7, contains other instructions, not affecting any status bits, see the the arithmetic status of the ALU, the RESET status and "Instruction Set Summary." the bank select bits for data memory. Note 1: For those devices that do not use bits IRP The STATUS register can be the destination for any and RP1 (STATUS<7:6>), maintain these instruction, as with any other register. If the STATUS bits clear to ensure upward compatibility register is the destination for an instruction that affects with future products. the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the Note 2: The C and DC bits operate as a borrow device logic. Furthermore, the TO and PD bits are not and digit borrow bit, respectively, in sub- writable. Therefore, the result of an instruction with the traction. See the SUBLW and SUBWF STATUS register as destination may be different than instructions for examples. intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 17

PIC16C71X 4.2.2.2 OPTION REGISTER Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to Applicable Devices 710 71 711 715 the Watchdog Timer by setting bit PSA (OPTION<3>). The OPTION register is a readable and writable regis- ter which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-8: OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS30272A-page 18 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 4.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of Applicable Devices 710 71 711 715 its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The INTCON Register is a readable and writable regis- ter which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. FIGURE 4-9: INTCON REGISTER (ADDRESS 0Bh, 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE ADIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: GIE:(1) Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables A/D interrupt 0 = Disables A/D interrupt bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note1: For the PIC16C71, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be uninten- tionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 8.5 for a detailed description. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 19

PIC16C71X 4.2.2.4 PIE1 REGISTER Note: Bit PEIE (INTCON<6>) must be set to Applicable Devices 710 71 711 715 enable any peripheral interrupt. This register contains the individual enable bits for the Peripheral interrupts. FIGURE 4-10: PIE1 REGISTER (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — ADIE — — — — — — R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5-0: Unimplemented: Read as '0' DS30272A-page 20 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 4.2.2.5 PIR1 REGISTER Note: Interrupt flag bits get set when an interrupt Applicable Devices 710 71 711 715 condition occurs regardless of the state of its corresponding enable bit or the global This register contains the individual flag bits for the enable bit, GIE (INTCON<7>). User soft- Peripheral interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 4-11: PIR1 REGISTER (ADDRESS 0Ch) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — ADIF — — — — — — R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed 0 = The A/D conversion is not complete bit 5-0: Unimplemented: Read as '0' (cid:211) 1997 Microchip Technology Inc. DS30272A-page 21

PIC16C71X 4.2.2.6 PCON REGISTER Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked Applicable Devices 710 71 711 715 on subsequent resets to see if BOR is The Power Control (PCON) register contains a flag bit clear, indicating a brown-out has occurred. to allow differentiation between a Power-on Reset The BOR status bit is a don't care and is (POR) to an external MCLR Reset or WDT Reset. not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN Those devices with brown-out detection circuitry con- bit in the Configuration word). tain an additional bit to differentiate a Brown-out Reset (BOR) condition from a Power-on Reset condition. For the PIC16C715 the PCON register also contains status bits MPEEN and PER. MPEEN reflects the value of the MPEEN bit in the configuration word. PER indicates a parity error reset has occurred. FIGURE 4-12: PCON REGISTER (ADDRESS 8Eh), PIC16C710/711 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) FIGURE 4-13: PCON REGISTER (ADDRESS 8Eh), PIC16C715 R-U U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-q MPEEN — — — — PER POR BOR(1) R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: MPEEN: Memory Parity Error Circuitry Status bit Reflects the value of configuration word bit, MPEEN bit 6-3: Unimplemented: Read as '0' bit 2: PER: Memory Parity Error Reset Status bit 1 = No Error occurred 0 = Program Memory Fetch Parity Error occurred (must be set in software after a Parity Error Reset) bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) DS30272A-page 22 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 4.3 PCL and PCLATH 4.3.2 STACK The program counter (PC) is 13-bits wide. The low byte The PIC16CXX family has an 8 level deep x 13-bit wide comes from the PCL register, which is a readable and hardware stack. The stack space is not part of either writable register. The upper bits (PC<12:8>) are not program or data space and the stack pointer is not readable, but are indirectly writable through the readable or writable. The PC is PUSHed onto the stack PCLATH register. On any reset, the upper bits of the when a CALL instruction is executed or an interrupt PC will be cleared. Figure 4-14 shows the two situa- causes a branch. The stack is POPed in the event of a tions for the loading of the PC. The upper example in RETURN, RETLW or a RETFIE instruction execution. the figure shows how the PC is loaded on a write to PCLATH is not affected by a PUSH or POP operation. PCL (PCLATH<4:0> fi PCH). The lower example in the The stack operates as a circular buffer. This means that figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> fi PCH). after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first FIGURE 4-14: LOADING OF PC IN push. The tenth push overwrites the second push (and DIFFERENT SITUATIONS so on). Note 1: There are no status bits to indicate stack PCH PCL overflow or stack underflow conditions. 12 8 7 0 Instruction with Note 2: There are no instructions/mnemonics PC PCL as Destination called PUSH or POP. These are actions PCLATH<4:0> 8 that occur from the execution of the CALL, 5 ALU RETURN, RETLW, and RETFIE instruc- tions, or the vectoring to an interrupt PCLATH address. PCH PCL 4.4 Program Memory Paging 12 11 10 8 7 0 The PIC16C71X devices ignore both paging bits PC GOTO, CALL (PCLATH<4:3>, which are used to access program PCLATH<4:3> 11 memory when more than one page is available. The 2 Opcode <10:0> use of PCLATH<4:3> as general purpose read/write bits for the PIC16C71X is not recommended since this PCLATH may affect upward compatibility with future products. 4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an off- set to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note “Implementing a Table Read" (AN556). (cid:211) 1997 Microchip Technology Inc. DS30272A-page 23

PIC16C71X Example 4-1 shows the calling of a subroutine in 4.5 Indirect Addressing, INDF and FSR page 1 of the program memory. This example assumes Registers that PCLATH is saved and restored by the interrupt ser- The INDF register is not a physical register. Addressing vice routine (if interrupts are used). the INDF register will cause indirect addressing. EXAMPLE 4-1: CALL OF A SUBROUTINE IN Indirect addressing is possible by using the INDF reg- PAGE 1 FROM PAGE 0 ister. Any instruction using the INDF register actually accesses the register pointed to by the File Select Reg- ORG 0x500 ister, FSR. Reading the INDF register itself indirectly BSF PCLATH,3 ;Select page 1 (800h-FFFh) BCF PCLATH,4 ;Only on >4K devices (FSR = '0') will read 00h. Writing to the INDF register CALL SUB1_P1 ;Call subroutine in indirectly results in a no-operation (although status bits : ;page 1 (800h-FFFh) may be affected). An effective 9-bit address is obtained : by concatenating the 8-bit FSR register and the IRP bit : (STATUS<7>), as shown in Figure 4-15. However, IRP ORG 0x900 is not used in the PIC16C71X devices. SUB1_P1: ;called subroutine : ;page 1 (800h-FFFh) A simple program to clear RAM locations 20h-2Fh : using indirect addressing is shown in Example 4-2. RETURN ;return to Call subroutine ;in page 0 (000h-7FFh) EXAMPLE 4-2: INDIRECT ADDRESSING movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next CONTINUE : ;yes continue FIGURE 4-15: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 from opcode 0 IRP(1) 7 FSR register 0 bank select location select bank select location select 00 01 10 11 00h 80h 100h 180h Not Data Used Memory 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For register file map detail see Figure 4-4. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear. DS30272A-page 24 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 5.0 I/O PORTS FIGURE 5-1: BLOCK DIAGRAM OF RA3:RA0 PINS Applicable Devices 710 71 711 715 Data Some pins for these I/O ports are multiplexed with an bus alternate function for the peripheral features on the D Q device. In general, when a peripheral is enabled, that VDD WR pin may not be used as a general purpose I/O pin. Port CK Q P 5.1 PORTA and TRISA Registers Data Latch PORTA is a 5-bit latch. D Q N I/O pin(1) The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL WR input levels and full CMOS output drivers. All pins have TRIS CK Q VSS data direction bits (TRIS registers) which can configure Analog these pins as output or input. input TRIS Latch mode Setting a TRISA register bit puts the corresponding out- put driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on RD TRIS TTL the selected pin(s). input buffer Reading the PORTA register reads the status of the Q D pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are EN read, this value is modified, and then written to the port data latch. RD PORT Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. To A/D Converter Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is Note 1: I/O pins have protection diodes to VDD and selected by clearing/setting the control bits in the VSS. ADCON1 register (A/D Control Register1). FIGURE 5-2: BLOCK DIAGRAM OF RA4/ Note: On a Power-on Reset, these pins are con- figured as analog inputs and read as '0'. T0CKI PIN The TRISA register controls the direction of the RA Data bus pins, even when they are being used as analog inputs. D Q The user must ensure the bits in the TRISA register are WR PORT maintained set when using them as analog inputs. CK Q I/O pin(1) N Data Latch EXAMPLE 5-1: INITIALIZING PORTA D Q VSS BCF STATUS, RP0 ; WR CLRF PORTA ; Initialize PORTA by TRIS CK Q Schmitt ; clearing output Trigger input ; data latches TRIS Latch buffer BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data RD TRIS ; direction MOVWF TRISA ; Set RA<3:0> as inputs Q D ; RA<4> as outputs ; TRISA<7:5> are always ENEN ; read as '0'. RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 25

PIC16C71X TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input RA1/AN1 bit1 TTL Input/output or analog input RA2/AN2 bit2 TTL Input/output or analog input RA3/AN3/VREF bit3 TTL Input/output or analog input/VREF RA4/T0CKI bit4 ST Input/output or external clock input for Timer0 Output is open drain type Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111 9Fh ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS30272A-page 26 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 5.2 PORTB and TRISB Registers Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can PORTB is an 8-bit wide bi-directional port. The corre- cause this interrupt to occur (i.e. any RB7:RB4 pin con- sponding data direction register is TRISB. Setting a bit figured as an output is excluded from the interrupt on in the TRISB register puts the corresponding output change comparison). The input pins (of RB7:RB4) are driver in a hi-impedance input mode. Clearing a bit in compared with the old value latched on the last read of the TRISB register puts the contents of the output latch PORTB. The “mismatch” outputs of RB7:RB4 are on the selected pin(s). OR’ed together to generate the RB Port Change Inter- EXAMPLE 5-2: INITIALIZING PORTB rupt with flag bit RBIF (INTCON<0>). BCF STATUS, RP0 ; This interrupt can wake the device from SLEEP. The CLRF PORTB ; Initialize PORTB by user, in the interrupt service routine, can clear the inter- ; clearing output rupt in the following manner: ; data latches a) Any read or write of PORTB. This will end the BSF STATUS, RP0 ; Select Bank 1 mismatch condition. MOVLW 0xCF ; Value used to ; initialize data b) Clear flag bit RBIF. ; direction A mismatch condition will continue to set flag bit RBIF. MOVWF TRISB ; Set RB<3:0> as inputs Reading PORTB will end the mismatch condition, and ; RB<5:4> as outputs allow flag bit RBIF to be cleared. ; RB<7:6> as inputs Each of the PORTB pins has a weak internal pull-up. A This interrupt on mismatch feature, together with soft- single control bit can turn on all the pull-ups. This is ware configurable pull-ups on these four pins allow performed by clearing bit RBPU (OPTION<7>). The easy interface to a keypad and make it possible for weak pull-up is automatically turned off when the port wake-up on key-depression. Refer to the Embedded pin is configured as an output. The pull-ups are dis- Control Handbook, "Implementing Wake-Up on Key abled on a Power-on Reset. Stroke" (AN552). FIGURE 5-3: BLOCK DIAGRAM OF Note: For the PIC16C71 RB3:RB0 PINS if a change on the I/O pin should occur when the read operation is being executed VDD RBPU(2) weak (start of the Q2 cycle), then interrupt flag bit P pull-up RBIF may not get set. Data Latch Data bus The interrupt on change feature is recommended for D Q wake-up on key depression operation and operations WR Port I/O where PORTB is only used for the interrupt on change CK pin(1) feature. Polling of PORTB is not recommended while TRIS Latch using the interrupt on change feature. D Q TTL Input WR TRIS CK Buffer RD TRIS Q D RD Port EN RB0/INT Schmitt Trigger RD Port Buffer Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = ’1’ enables weak pull-up if RBPU = ’0’ (OPTION<7>). (cid:211) 1997 Microchip Technology Inc. DS30272A-page 27

PIC16C71X FIGURE 5-4: BLOCK DIAGRAM OF FIGURE 5-5: BLOCK DIAGRAM OF RB7:RB4 PINS RB7:RB4 PINS (PIC16C71) (PIC16C710/711/715) VDD VDD RBPU(2) weak RBPU(2) weak P P pull-up pull-up Data Latch Data Latch Data bus Data bus D Q D Q I/O I/O WR Port WR Port CK pin(1) CK pin(1) TRIS Latch TRIS Latch D Q D Q WR TRIS TTL WR TRIS TTL CK CK Input Input Buffer ST Buffer ST Buffer Buffer RD TRIS Latch RD TRIS Latch Q D Q D RD Port EN RD Port EN Q1 Set RBIF Set RBIF FRrBo7m:R oBth4e prins Q D From other Q D RB7:RB4 pins RD Port EN EN RD Port Q3 RB7:RB6 in serial programming mode RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. Note 1: I/O pins have diode protection to VDD and VSS. 2: TRISB = ’1’ enables weak pull-up if 2: TRISB = ’1’ enables weak pull-up if RBPU = ’0’ (OPTION<7>). RBPU = ’0’ (OPTION<7>). TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. DS30272A-page 28 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 29

PIC16C71X 5.3 I/O Programming Considerations EXAMPLE 5-3: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O 5.3.1 BI-DIRECTIONAL I/O PORTS PORT Any instruction which writes, operates internally as a ;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs read followed by a write operation. The BCF and BSF ;PORTB<7:6> have external pull-ups and are instructions, for example, read the register into the ;not connected to other circuitry CPU, execute the bit operation and write the result ; back to the register. Caution must be used when these ; PORT latch PORT pins instructions are applied to a port with both inputs and ; ---------- --------- outputs defined. For example, a BSF operation on bit5 BCF PORTB, 7 ; 01pp pppp 11pp pppp of PORTB will cause all eight bits of PORTB to be read BCF PORTB, 6 ; 10pp pppp 11pp pppp into the CPU. Then the BSF operation takes place on BSF STATUS, RP0 ; bit5 and PORTB is written to the output latches. If BCF TRISB, 7 ; 10pp pppp 11pp pppp another bit of PORTB is used as a bi-directional I/O pin BCF TRISB, 6 ; 10pp pppp 10pp pppp ; (e.g., bit0) and it is defined as an input at this time, the ;Note that the user may have expected the input signal present on the pin itself would be read into ;pin values to be 00pp ppp. The 2nd BCF the CPU and rewritten to the data latch of this particular ;caused RB7 to be latched as the pin value pin, overwriting the previous content. As long as the pin ;(high). stays in the input mode, no problem occurs. However, A pin actively outputting a Low or High should not be if bit0 is switched to an output, the content of the data driven from external devices at the same time in order latch may now be unknown. to change the level on this pin (“wired-or”, “wired-and”). Reading the port register, reads the values of the port The resulting high output currents may damage the pins. Writing to the port register writes the value to the chip. port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins 5.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS is read, the desired operation is done to this value, and The actual write to an I/O port happens at the end of an this value is then written to the port latch. instruction cycle, whereas for reading, the data must be Example 5-3 shows the effect of two sequential read- valid at the beginning of the instruction cycle modify-write instructions on an I/O port. (Figure 5-6). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load depen- dent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-6: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note: PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB Instruction followed by a read from PORTB. fetched MOVWF PORTB MOVF PORTB,W write to NOP NOP Note that: PORTB RB7:RB0 data setup time = (0.25TCY - TPD) where TCY = instruction cycle Port pin sampled here TPD = propagation delay Instruction TPD Therefore, at higher clock frequencies, executed NOP a write followed by a read may be MOVWF PORTB MOVF PORTB,W problematic. write to PORTB DS30272A-page 30 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 6.0 TIMER0 MODULE bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Applicable Devices 710 71 711 715 Section 6.2. The Timer0 module timer/counter has the following fea- The prescaler is mutually exclusively shared between tures: the Timer0 module and the Watchdog Timer. The pres- • 8-bit timer/counter caler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the • Readable and writable prescaler to the Timer0 module. The prescaler is not • 8-bit software programmable prescaler readable or writable. When the prescaler is assigned to • Internal or external clock select the Timer0 module, prescale values of 1:2, 1:4, ..., • Interrupt on overflow from FFh to 00h 1:256 are selectable. Section 6.3 details the operation • Edge select for external clock of the prescaler. Figure 6-1 is a simplified block diagram of the Timer0 6.1 Timer0 Interrupt module. The TMR0 interrupt is generated when the TMR0 reg- Timer mode is selected by clearing bit T0CS ister overflows from FFh to 00h. This overflow sets bit (OPTION<5>). In timer mode, the Timer0 module will T0IF (INTCON<2>). The interrupt can be masked by increment every instruction cycle (without prescaler). If clearing bit T0IE (INTCON<5>). Bit T0IF must be the TMR0 register is written, the increment is inhibited cleared in software by the Timer0 module interrupt ser- for the following two instruction cycles (Figure 6-2 and vice routine before re-enabling this interrupt. The Figure 6-3). The user can work around this by writing TMR0 interrupt cannot awaken the processor from an adjusted value to the TMR0 register. SLEEP since the timer is shut off during SLEEP. See Counter mode is selected by setting bit T0CS Figure 6-4 for Timer0 interrupt timing. (OPTION<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clearing FIGURE 6-1: TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 8 1 Sync with 1 Internal TMR0 clocks RA4/T0CKI Programmable 0 PSout pin Prescaler T0SE (2 cycle delay) 3 Set interrupt PS2, PS1, PS0 PSA flag bit T0IF T0CS on overflow Note1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram). FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch TMR0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T0 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 31

PIC16C71X FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch TMR0 T0 T0+1 NT0 NT0+1 PC+6 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 FIGURE 6-4: TIMER0 INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) Timer0 FEh FFh 00h 01h 02h 1 1 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC +1 PC +1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h) Instruction executed Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h) Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. DS30272A-page 32 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 6.2 Using Timer0 with an External Clock caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, When an external clock input is used for Timer0, it must the ripple-counter must be taken into account. There- meet certain requirements. The requirements ensure fore, it is necessary for T0CKI to have a period of at the external clock can be synchronized with the internal least 4Tosc (and a small RC delay of 40 ns) divided by phase clock (TOSC). Also, there is a delay in the actual the prescaler value. The only requirement on T0CKI incrementing of Timer0 after synchronization. high and low time is that they do not violate the mini- 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION mum pulse width requirement of 10 ns. Refer to param- eters 40, 41 and 42 in the electrical specification of the When no prescaler is used, the external clock input is desired device. the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accom- 6.2.2 TMR0 INCREMENT DELAY plished by sampling the prescaler output on the Q2 and Since the prescaler output is synchronized with the Q4 cycles of the internal phase clocks (Figure 6-5). internal clocks, there is a small delay from the time the Therefore, it is necessary for T0CKI to be high for at external clock edge occurs to the time the Timer0 mod- least 2Tosc (and a small RC delay of 20 ns) and low for ule is actually incremented. Figure 6-5 shows the delay at least 2Tosc (and a small RC delay of 20 ns). Refer to from the external clock edge to the timer incrementing. the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse External Clock Input or Prescaler output (2) misses sampling (1) (3) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = – 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 33

PIC16C71X 6.3 Prescaler When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, An 8-bit counter is available as a prescaler for the BSF 1,x....etc.) will clear the prescaler. When Timer0 module, or as a postscaler for the Watchdog assigned to WDT, a CLRWDT instruction will clear the Timer, respectively (Figure 6-6). For simplicity, this prescaler along with the Watchdog Timer. The pres- counter is being referred to as “prescaler” throughout caler is not readable or writable. this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between Note: Writing to TMR0 when the prescaler is the Timer0 module and the Watchdog Timer. Thus, a assigned to Timer0 will clear the prescaler prescaler assignment for the Timer0 module means count, but will not change the prescaler that there is no prescaler for the Watchdog Timer, and assignment. vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (=Fosc/4) Data Bus 8 M 0 1 RA4/T0CKI U M SYNC pin 1 X 0 U 2 TMR0 reg X Cycles T0SE T0CS PSA Set flag bit T0IF on Overflow 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8 - to - 1MUX PS2:PS0 PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>). DS30272A-page 34 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 6.3.1 SWITCHING PRESCALER ASSIGNMENT Note: To avoid an unintended device RESET, the following instruction sequence (shown in The prescaler assignment is fully under software con- Example 6-1) must be executed when trol, i.e., it can be changed “on the fly” during program changing the prescaler assignment from execution. Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. EXAMPLE 6-1: CHANGING PRESCALER (TIMER0fi WDT) BCF STATUS, RP0 ;Bank 0 CLRF TMR0 ;Clear TMR0 & Prescaler BSF STATUS, RP0 ;Bank 1 CLRWDT ;Clears WDT MOVLW b'xxxx1xxx' ;Selects new prescale value MOVWF OPTION_REG ;and assigns the prescaler to the WDT BCF STATUS, RP0 ;Bank 0 To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2. EXAMPLE 6-2: CHANGING PRESCALER (WDTfi TIMER0) CLRWDT ;Clear WDT and prescaler BSF STATUS, RP0 ;Bank 1 MOVLW b'xxxx0xxx' ;Select TMR0, new prescale value and MOVWF OPTION_REG ;clock source BCF STATUS, RP0 ;Bank 0 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 35

PIC16C71X NOTES: DS30272A-page 36 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 7.0 ANALOG-TO-DIGITAL The A/D converter has a unique feature of being able CONVERTER (A/D) MODULE to operate while the device is in SLEEP mode. To oper- ate in sleep, the A/D conversion clock must be derived Applicable Devices 710 71 711 715 from the A/D’s internal RC oscillator. The analog-to-digital (A/D) converter module has four The A/D module has three registers. These registers analog inputs. are: The A/D allows conversion of an analog input signal to • A/D Result Register (ADRES) a corresponding 8-bit digital number (refer to Applica- • A/D Control Register 0 (ADCON0) tion Note AN546 for use of A/D Converter). The output • A/D Control Register 1 (ADCON1) of the sample and hold is the input into the converter, The ADCON0 register, shown in Figure 7-1 and which generates the result via successive approxima- Figure 7-2, controls the operation of the A/D module. tion. The analog reference voltage is software select- The ADCON1 register, shown in Figure 7-3 configures able to either the device’s positive supply voltage (VDD) the functions of the port pins. The port pins can be con- or the voltage level on the RA3/AN3/VREF pin. figured as analog inputs (RA3 can also be a voltage ref- erence) or as digital I/O. FIGURE 7-1: ADCON0 REGISTER (ADDRESS 08h), PIC16C710/71/711 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 — (1) CHS1 CHS0 GO/DONE ADIF ADON R =Readable bit W =Writable bit bit7 bit0 U =Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an RC oscillation) bit 5: Unimplemented: Read as '0'. bit 4-3: CHS1:CHS0: Analog Channel Select bits 00 = channel 0, (RA0/AN0) 01 = channel 1, (RA1/AN1) 10 = channel 2, (RA2/AN2) 11 = channel 3, (RA3/AN3) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver- sion is complete) bit 1: ADIF: A/D Conversion Complete Interrupt Flag bit 1 = conversion is complete (must be cleared in software) 0 = conversion is not complete bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented, read as '0'. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 37

PIC16C71X FIGURE 7-2: ADCON0 REGISTER (ADDRESS 1Fh), PIC16C715 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 — CHS1 CHS0 GO/DONE — ADON R =Readable bit bit7 bit0 W =Writable bit U =Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an RC oscillation) bit 5: Unused bit 6-3: CHS1:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 0, (RA0/AN0) 101 = channel 1, (RA1/AN1) 110 = channel 2, (RA2/AN2) 111 = channel 3, (RA3/AN3) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver- sion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current FIGURE 7-3: ADCON1 REGISTER, PIC16C710/71/711 (ADDRESS 88h), PIC16C715 (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — PCFG1 PCFG0 R =Readable bit bit7 bit0 W =Writable bit U =Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1-0: PCFG1:PCFG0: A/D Port Configuration Control bits PCFG1:PCFG0 RA1 & RA0 RA2 RA3 VREF 00 A A A VDD 01 A A VREF RA3 10 A D D VDD 11 D D D VDD A = Analog input D = Digital I/O DS30272A-page 38 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X The ADRES register contains the result of the A/D con- 2. Configure A/D interrupt (if desired): version. When the A/D conversion is complete, the • Clear ADIF bit result is loaded into the ADRES register, the GO/DONE • Set ADIE bit bit (ADCON0<2>) is cleared, and A/D interrupt flag bit • Set GIE bit ADIF is set. The block diagram of the A/D module is 3. Wait the required acquisition time. shown in Figure 7-4. 4. Start conversion: After the A/D module has been configured as desired, the selected channel must be acquired before the con- • Set GO/DONE bit (ADCON0) version is started. The analog input channels must 5. Wait for A/D conversion to complete, by either: have their corresponding TRIS bits selected as an • Polling for the GO/DONE bit to be cleared input. To determine acquisition time, see Section 7.1. OR After this acquisition time has elapsed the A/D conver- sion can be started. The following steps should be fol- • Waiting for the A/D interrupt lowed for doing an A/D conversion: 6. Read A/D Result register (ADRES), clear bit ADIF if required. 1. Configure the A/D module: 7. For next conversion, go to step 1 or step 2 as • Configure analog pins / voltage reference / required. The A/D conversion time per bit is and digital I/O (ADCON1) defined as TAD. A minimum wait of 2TAD is • Select A/D input channel (ADCON0) required before next acquisition starts. • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) FIGURE 7-4: A/D BLOCK DIAGRAM CHS1:CHS0 11 VIN RA3/AN3/VREF (Input voltage) 10 RA2/AN2 01 A/D RA1/AN1 Converter 00 RA0/AN0 VDD 00 or VREF 10 or 11 (Reference voltage) 01 PCFG1:PCFG0 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 39

PIC16C71X 7.1 A/D Acquisition Requirements Note 1: The reference voltage (VREF) has no For the A/D converter to meet its specified accuracy, effect on the equation, since it cancels the charge holding capacitor (CHOLD) must be allowed itself out. to fully charge to the input channel voltage level. The Note 2: The charge holding capacitor (CHOLD) is analog input model is shown in Figure 7-5. The source not discharged after each conversion. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge Note 3: The maximum recommended impedance the capacitor CHOLD. The sampling switch (RSS) for analog sources is 10 kW . This is impedance varies over the device voltage (VDD), required to meet the pin leakage specifi- Figure 7-5. The source impedance affects the offset cation. voltage at the analog input (due to pin leakage current). Note 4: After a conversion has completed, a The maximum recommended impedance for ana- 2.0TAD delay must complete before acqui- log sources is 10 kW . After the analog input channel is sition can begin again. During this time the selected (changed) this acquisition must be done holding capacitor is not connected to the before the conversion can be started. selected A/D input channel. To calculate the minimum acquisition time, Equation 7- 1 may be used. This equation calculates the acquisition EXAMPLE 7-1: CALCULATING THE time to within 1/2 LSb error is used (512 steps for the MINIMUM REQUIRED A/D). The 1/2 LSb error is the maximum error allowed AQUISITION TIME for the A/D to meet its specified accuracy. TACQ = Amplifier Settling Time + EQUATION 7-1: A/D MINIMUM CHARGING Holding Capacitor Charging Time + TIME Temperature Coefficient VHOLD = (VREF - (VREF/512)) • (1 - e(-TCAP/CHOLD(RIC + RSS + RS))) TACQ = 5 m s + TCAP + [(Temp - 25(cid:176) C)(0.05 m s/(cid:176) C)] Given: VHOLD = (VREF/512), for 1/2 LSb resolution TCAP = -CHOLD (RIC + RSS + RS) ln(1/511) The above equation reduces to: -51.2 pF (1 kW + 7 kW + 10 kW ) ln(0.0020) TCAP = -(51.2 pF)(1 kW + RSS + RS) ln(1/511) -51.2 pF (18 kW ) ln(0.0020) Example 7-1 shows the calculation of the minimum -0.921 m s (-6.2364) required acquisition time TACQ. This calculation is 5.747 m s based on the following system assumptions. CHOLD = 51.2 pF TACQ = 5 m s + 5.747 m s + [(50(cid:176) C - 25(cid:176) C)(0.05 m s/(cid:176) C)] 10.747 m s + 1.25 m s Rs = 10 kW 11.997 m s 1/2 LSb error VDD = 5V fi Rss = 7 kW Temp (application system max.) = 50(cid:176) C VHOLD = 0 @ t = 0 FIGURE 7-5: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC £ 1k SS RSS CHOLD VA CPIN I leakage = DAC capacitance 5 pF VT = 0.6V – 500 nA = 51.2 pF VSS LegendCPIN = input capacitance 6V VT = threshold voltage 5V I leakage = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch ( kW ) DS30272A-page 40 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 7.2 Selecting the A/D Conversion Clock 7.3 Configuring Analog Port Pins The A/D conversion time per bit is defined as TAD. The The ADCON1 and TRISA registers control the opera- A/D conversion requires 9.5TAD per 8-bit conversion. tion of the A/D port pins. The port pins that are desired The source of the A/D conversion clock is software as analog inputs must have their corresponding TRIS selectable. The four possible options for TAD are: bits set (input). If the TRIS bit is cleared (output), the • 2TOSC digital output level (VOH or VOL) will be converted. • 8TOSC The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. • 32TOSC • Internal RC oscillator Note 1: When reading the port register, all pins configured as analog input channels will For correct A/D conversions, the A/D conversion clock read as cleared (a low level). Pins config- (TAD) must be selected to ensure a minimum TAD time ured as digital inputs, will convert an ana- of: log input. Analog levels on a digitally 2.0 m s for the PIC16C71 configured input will not affect the conver- 1.6 m s for all other PIC16C71X devices sion accuracy. Table 7-1 and Table 7-2 and show the resultant TAD Note 2: Analog levels on any pin that is defined as times derived from the device operating frequencies a digital input (including the AN7:AN0 and the A/D clock source selected. pins), may cause the input buffer to con- sume current that is out of the devices specification. TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C71 AD Clock Source (TAD) Device Frequency Operation ADCS1:ADCS0 20 MHz 16 MHz 4 MHz 1 MHz 333.33 kHz 2TOSC 00 100 ns(2) 125 ns(2) 500 ns(2) 2.0 m s 6 m s 8TOSC 01 400 ns(2) 500 ns(2) 2.0 m s 8.0 m s 24 m s(3) 32TOSC 10 1.6 m s(2) 2.0 m s 8.0 m s 32.0 m s(3) 96 m s(3) RC(5) 11 2 - 6 m s(1,4) 2 - 6 m s(1,4) 2 - 6 m s(1,4) 2 - 6 m s(1) 2 - 6 m s(1) Legend: Shaded cells are outside of recommended range. Note1: The RC source has a typical TAD time of 4 m s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. TABLE 7-2: TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C710/711, PIC16C715 AD Clock Source (TAD) Device Frequency Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz 2TOSC 00 100 ns(2) 400 ns(2) 1.6 m s 6 m s 8TOSC 01 400 ns(2) 1.6 m s 6.4 m s 24 m s(3) 32TOSC 10 1.6 m s 6.4 m s 25.6 m s(3) 96 m s(3) RC(5) 11 2 - 6 m s(1,4) 2 - 6 m s(1,4) 2 - 6 m s(1,4) 2 - 6 m s(1) Legend: Shaded cells are outside of recommended range. Note1: The RC source has a typical TAD time of 4 m s. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 41

PIC16C71X 7.4 A/D Conversions Example 7-2 shows how to perform an A/D conversion. Note: The GO/DONE bit should NOT be set in The RA pins are configured as analog inputs. The ana- the same instruction that turns on the A/D. log reference (VREF) is the device VDD. The A/D inter- Clearing the GO/DONE bit during a conversion will rupt is enabled, and the A/D conversion clock is FRC. abort the current conversion. The ADRES register will The conversion is performed on the RA0 pin (channel NOT be updated with the partially completed A/D con- 0). version sample. That is, the ADRES register will con- tinue to contain the value of the last completed conversion (or the last value written to the ADRES reg- ister). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, an acquisition is automatically started on the selected channel. EXAMPLE 7-2: A/D CONVERSION BSF STATUS, RP0 ; Select Bank 1 CLRF ADCON1 ; Configure A/D inputs BCF STATUS, RP0 ; Select Bank 0 MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected MOVWF ADCON0 ; BSF INTCON, ADIE ; Enable A/D Interrupt BSF INTCON, GIE ; Enable all interrupts ; ; Ensure that the required sampling time for the selected input channel has elapsed. ; Then the conversion may be started. ; BSF ADCON0, GO ; Start A/D Conversion : ; The ADIF bit will be set and the GO/DONE bit : ; is cleared upon completion of the A/D Conversion. DS30272A-page 42 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 7.4.1 FASTER CONVERSION - LOWER Since the TAD is based from the device oscillator, the RESOLUTION TRADE-OFF user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be Not all applications require a result with 8-bits of reso- changed. Example 7-3 shows a comparison of time lution, but may instead require a faster conversion time. required for a conversion with 4-bits of resolution, ver- The A/D module allows users to make the trade-off of sus the 8-bit resolution conversion. The example is for conversion speed to resolution. Regardless of the res- devices operating at 20 MHz and 16 MHz (The A/D olution required, the acquisition time is the same. To clock is programmed for 32TOSC), and assumes that speed up the conversion, the clock source of the A/D immediately after 6TAD, the A/D clock is programmed module may be switched so that the TAD time violates for 2TOSC. the minimum specified time (see the applicable electri- cal specification). Once the TAD time violates the mini- The 2TOSC violates the minimum TAD time since the last 4-bits will not be converted to correct values. mum specified time, all the following A/D result bits are not valid (see A/D Conversion Timing in the Electrical Specifications section.) The clock sources may only be switched between the three oscillator versions (cannot be switched from/to RC). The equation to determine the time before the oscillator can be switched is as follows: Conversion time = 2TAD + N • TAD + (8 - N)(2TOSC) Where: N = number of bits of resolution required. EXAMPLE 7-3: 4-BIT vs. 8-BIT CONVERSION TIMES Resolution Freq. (MHz)(1) 4-bit 8-bit TAD 20 1.6 m s 1.6 m s 16 2.0 m s 2.0 m s TOSC 20 50 ns 50 ns 16 62.5 ns 62.5 ns 2TAD + N • TAD + (8 - N)(2TOSC) 20 10 m s 16 m s 16 12.5 m s 20 m s Note1: The PIC16C71 has a minimum TAD time of 2.0 m s. All other PIC16C71X devices have a minimum TAD time of 1.6 m s. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 43

PIC16C71X 7.5 A/D Operation During Sleep full scale error is that full scale does not take offset error into account. Gain error can be calibrated out in soft- The A/D module can operate during SLEEP mode. This ware. requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is Linearity error refers to the uniformity of the code selected, the A/D module waits one instruction cycle changes. Linearity errors cannot be calibrated out of before starting the conversion. This allows the SLEEP the system. Integral non-linearity error measures the instruction to be executed, which eliminates all digital actual code transition versus the ideal code transition switching noise from the conversion. When the conver- adjusted by the gain error for each code. sion is completed the GO/DONE bit will be cleared, and Differential non-linearity measures the maximum the result loaded into the ADRES register. If the A/D actual code width versus the ideal code width. This interrupt is enabled, the device will wake-up from measure is unadjusted. SLEEP. If the A/D interrupt is not enabled, the A/D mod- In systems where the device frequency is low, use of ule will then be turned off, although the ADON bit will the A/D RC clock is preferred. At moderate to high fre- remain set. quencies, TAD should be derived from the device oscil- When the A/D clock source is another clock option (not lator. TAD must not violate the minimum and should be RC), a SLEEP instruction will cause the present conver- £ 8 m s for preferred operation. This is because TAD, sion to be aborted and the A/D module to be turned off, when derived from TOSC, is kept away from on-chip though the ADON bit will remain set. phase clock transitions. This reduces, to a large extent, Turning off the A/D places the A/D module in its lowest the effects of digital switching noise. This is not possible current consumption state. with the RC derived clock. The loss of accuracy due to digital switching noise can be significant if many I/O Note: For the A/D module to operate in SLEEP, pins are active. the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D In systems where the device will enter SLEEP mode conversion in SLEEP, ensure the SLEEP after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital instruction immediately follows the instruc- noise from the modules in SLEEP are stopped. This tion that sets the GO/DONE bit. method gives high accuracy. 7.6 A/D Accuracy/Error 7.7 Effects of a RESET The absolute accuracy specified for the A/D converter includes the sum of all contributions for quantization A device reset forces all registers to their reset state. error, integral error, differential error, full scale error, off- This forces the A/D module to be turned off, and any set error, and monotonicity. It is defined as the maxi- conversion is aborted. mum deviation from an actual transition versus an ideal The value that is in the ADRES register is not modified transition for any code. The absolute error of the A/D for a Power-on Reset. The ADRES register will contain converter is specified at < – 1 LSb for VDD = VREF (over unknown data after a Power-on Reset. the device’s specified operating range). However, the accuracy of the A/D converter will degrade as VDD 7.8 Connection Considerations diverges from VREF. If the input voltage exceeds the rail values (VSS or VDD) For a given range of analog inputs, the output digital by greater than 0.2V, then the accuracy of the conver- code will be the same. This is due to the quantization of sion is out of specification. the analog input to a digital code. Quantization error is Note: Care must be taken when using the RA0 typically – 1/2 LSb and is inherent in the analog to dig- pin in A/D conversions due to its proximity ital conversion process. The only way to reduce quanti- to the OSC1 pin. zation error is to increase the resolution of the A/D converter. An external RC filter is sometimes added for anti-alias- ing of the input signal. The R component should be Offset error measures the first actual transition of a selected to ensure that the total source impedance is code versus the first ideal transition of a code. Offset kept under the 10 kW recommended specification. Any error shifts the entire transfer function. Offset error can external components connected (via hi-impedance) to be calibrated out of a system or introduced into a sys- an analog input pin (capacitor, zener diode, etc.) should tem through the interaction of the total leakage current have very little leakage current at the pin. and source impedance at the analog input. Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. This error appears as a change in slope of the transfer function. The difference in gain error to DS30272A-page 44 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 7.9 Transfer Function FIGURE 7-6: A/D TRANSFER FUNCTION The ideal transfer function of the A/D converter is as fol- lows: the first transition occurs when the analog input voltage (VAIN) is Analog VREF/256 (Figure 7-6). 7.10 References FFh ut p FEh A very good reference for understanding A/D convert- ut o ers is the "Analog-Digital Conversion Handbook" third e d edition, published by Prentice Hall (ISBN 0-13-03- o c 2848-0). al Digit 04h 03h 02h 01h 00h bb b b b b be) SS S S S S Sal LL L L L L Lc 0.5 1 2 3 4 255 256 ull s (f Analog input voltage FIGURE 7-7: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes GO = 0? No A/=D R CClo?ck Yes C1o InnvSsettrrasuricto toniof DnA eC/Dlayyceled InsStLruEcEtiPon?Yes FinisAhG DCOIoF =n =v 0 e1rsion No No DSLeEviEceP ?in Yes AborAtG DCOIoF n= =v 0e 0rsion FinisAhG DCOIoF =n =v 0 e1rsion FrWoma kSel-euepp?Yes Wait 2 TAD No No FinishG COo =nv 0ersion PoweSrL-dEoEwPn A/D Wait 2 TAD PoSwtaeyr -idno Swlne eAp/D ADIF = 1 Wait 2 TAD (cid:211) 1997 Microchip Technology Inc. DS30272A-page 45

PIC16C71X TABLE 7-3: REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C710/71/711 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 89h ADRES A/D Result Register xxxx xxxx uuuu uuuu 08h ADCON0 ADCS1 ADCS0 — CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000 88h ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00 05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. TABLE 7-4: REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C715 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — — — — -0-- ---- -0-- ---- 8Ch PIE1 — ADIE — — — — — — -0-- ---- -0-- ---- 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON ADCS ADCS CHS2 CHS1 CHS0 GO/ — ADON 0000 00-0 0000 00-0 0 1 0 DONE 9Fh ADCON — — — — — — PCFG1 PCFG0 ---- --00 ---- --00 1 05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 85h TRISA — — — TRISA4 TRISA TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 3 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. DS30272A-page 46 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 8.0 SPECIAL FEATURES OF THE fixed delay of 72 ms (nominal) on power-up only, CPU designed to keep the part in reset while the power sup- ply stabilizes. With these two timers on-chip, most Applicable Devices 710 71 711 715 applications need no external reset circuitry. What sets a microcontroller apart from other proces- SLEEP mode is designed to offer a very low current sors are special circuits to deal with the needs of real- power-down mode. The user can wake-up from SLEEP time applications. The PIC16CXX family has a host of through external reset, Watchdog Timer Wake-up, or such features intended to maximize system reliability, through an interrupt. Several oscillator options are also minimize cost through elimination of external compo- made available to allow the part to fit the application. nents, provide power saving operating modes and offer The RC oscillator option saves system cost while the code protection. These are: LP crystal option saves power. A set of configuration bits are used to select various options. • Oscillator selection • Reset 8.1 Configuration Bits - Power-on Reset (POR) The configuration bits can be programmed (read as '0') - Power-up Timer (PWRT) or left unprogrammed (read as '1') to select various - Oscillator Start-up Timer (OST) device configurations. These bits are mapped in pro- - Brown-out Reset (BOR) gram memory location 2007h. (PIC16C710/711/715) The user will note that address 2007h is beyond the - Parity Error Reset (PER) (PIC16C715) user program memory space. In fact, it belongs to the • Interrupts special test/configuration memory space (2000h - 3FFFh), which can be accessed only during program- • Watchdog Timer (WDT) ming. • SLEEP • Code protection • ID locations • In-circuit serial programming The PIC16CXX has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a FIGURE 8-1: CONFIGURATION WORD FOR PIC16C71 — — — — — — — — — CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG Address 2007h bit13 bit0 bit 13-5: Unimplemented: Read as '1' bit 4: CP0: Code protection bit 1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable bit 3: PWRTE: Power-up Timer Enable bit 1 = Power-up Timer enabled 0 = Power-up Timer disabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator (cid:211) 1997 Microchip Technology Inc. DS30272A-page 47

PIC16C71X FIGURE 8-2: CONFIGURATION WORD, PIC16C710/711 CP0 CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG Address 2007h bit13 bit0 bit 13-7 CP0: Code protection bits (2) 5-4: 1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed. FIGURE 8-3: CONFIGURATION WORD, PIC16C715 CP1 CP0 CP1 CP0 CP1 CP0 MPEEN BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG Address 2007h bit13 bit0 bit 13-8 CP1:CP0: Code Protection bits (2) 5-4: 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 7: MPEEN: Memory Parity Error Enable 1 = Memory Parity Checking is enabled 0 = Memory Parity Checking is disabled bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. DS30272A-page 48 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 8.2 Oscillator Configurations TABLE 8-1: CERAMIC RESONATORS, PIC16C71 8.2.1 OSCILLATOR TYPES Ranges Tested: The PIC16CXX can be operated in four different oscil- lator modes. The user can program two configuration Mode Freq OSC1 OSC2 bits (FOSC1 and FOSC0) to select one of these four XT 455 kHz 47 - 100 pF 47 - 100 pF modes: 2.0 MHz 15 - 68 pF 15 - 68 pF • LP Low Power Crystal 4.0 MHz 15 - 68 pF 15 - 68 pF • XT Crystal/Resonator HS 8.0 MHz 15 - 68 pF 15 - 68 pF • HS High Speed Crystal/Resonator 16.0 MHz 10 - 47 pF 10 - 47 pF • RC Resistor/Capacitor These values are for design guidance only. See notes at bottom of page. 8.2.2 CRYSTAL OSCILLATOR/CERAMIC Resonators Used: RESONATORS 455 kHz Panasonic EFO-A455K04B – 0.3% In XT, LP or HS modes a crystal or ceramic resonator 2.0 MHz Murata Erie CSA2.00MG – 0.5% is connected to the OSC1/CLKIN and OSC2/CLKOUT 4.0 MHz Murata Erie CSA4.00MG – 0.5% pins to establish oscillation (Figure 8-4). The 8.0 MHz Murata Erie CSA8.00MT – 0.5% PIC16CXX Oscillator design requires the use of a par- allel cut crystal. Use of a series cut crystal may give a 16.0 MHz Murata Erie CSA16.00MX – 0.5% frequency out of the crystal manufacturers specifica- All resonators used did not have built-in capacitors. tions. When in XT, LP or HS modes, the device can TABLE 8-2: CAPACITOR SELECTION have an external clock source to drive the OSC1/ FOR CRYSTAL OSCILLATOR, CLKIN pin (Figure 8-5). PIC16C71 FIGURE 8-4: CRYSTAL/CERAMIC RESONATOR OPERATION Mode Freq OSC1 OSC2 (HS, XT OR LP LP 32 kHz 33 - 68 pF 33 - 68 pF OSC CONFIGURATION) 200 kHz 15 - 47 pF 15 - 47 pF XT 100 kHz 47 - 100 pF 47 - 100 pF OSC1 500 kHz 20 - 68 pF 20 - 68 pF C1 1 MHz 15 - 68 pF 15 - 68 pF 2 MHz 15 - 47 pF 15 - 47 pF XTAL SLEEP RF PIC16CXXX 4 MHz 15 - 33 pF 15 - 33 pF OSC2 HS 8 MHz 15 - 47 pF 15 - 47 pF RS (2) Tloog iincternal 20 MHz 15 - 47 pF 15 - 47 pF C2 Note1 These values are for design guidance only. See notes at bottom of page. See Table 8-1 and Table 8-1 for recommended values of C1 and C2. Note 1: A series resistor may be required for AT strip cut crystals. 2: The buffer is on the OSC2 pin. FIGURE 8-5: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock from OSC1 ext. system PIC16CXXX Open OSC2 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 49

PIC16C71X TABLE 8-3: CERAMIC RESONATORS, TABLE 8-4: CAPACITOR SELECTION PIC16C710/711/715 FOR CRYSTAL OSCILLATOR, PIC16C710/711/715 Ranges Tested: Crystal Cap. Range Cap. Range Mode Freq OSC1 OSC2 Osc Type Freq C1 C2 XT 455 kHz 68 - 100 pF 68 - 100 pF LP 32 kHz 33 pF 33 pF 2.0 MHz 15 - 68 pF 15 - 68 pF 200 kHz 15 pF 15 pF 4.0 MHz 15 - 68 pF 15 - 68 pF XT 200 kHz 47-68 pF 47-68 pF HS 8.0 MHz 10 - 68 pF 10 - 68 pF 16.0 MHz 10 - 22 pF 10 - 22 pF 1 MHz 15 pF 15 pF These values are for design guidance only. See 4 MHz 15 pF 15 pF notes at bottom of page. HS 4 MHz 15 pF 15 pF Resonators Used: 8 MHz 15-33 pF 15-33 pF 455 kHz Panasonic EFO-A455K04B – 0.3% 20 MHz 15-33 pF 15-33 pF 2.0 MHz Murata Erie CSA2.00MG – 0.5% These values are for design guidance only. See notes at bottom of page. 4.0 MHz Murata Erie CSA4.00MG – 0.5% Crystals Used 8.0 MHz Murata Erie CSA8.00MT – 0.5% 32 kHz Epson C-001R32.768K-A – 20 PPM 16.0 MHz Murata Erie CSA16.00MX – 0.5% 200 kHz STD XTL 200.000KHz – 20 PPM All resonators used did not have built-in capacitors. 1 MHz ECS ECS-10-13-1 – 50 PPM 4 MHz ECS ECS-40-20-1 – 50 PPM 8 MHz EPSON CA-301 8.000M-C – 30 PPM 20 MHz EPSON CA-301 20.000M-C – 30 PPM Note1: Recommended values of C1 and C2 are identical to the ranges tested table. 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal man- ufacturer for appropriate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level speci- fication. DS30272A-page 50 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 8.2.3 EXTERNAL CRYSTAL OSCILLATOR 8.2.4 RC OSCILLATOR CIRCUIT For timing insensitive applications the “RC” device Either a prepackaged oscillator can be used or a simple option offers additional cost savings. The RC oscillator oscillator circuit with TTL gates can be built. Prepack- frequency is a function of the supply voltage, the resis- aged oscillators provide a wide operating range and tor (Rext) and capacitor (Cext) values, and the operat- better stability. A well-designed crystal oscillator will ing temperature. In addition to this, the oscillator provide good performance with TTL gates. Two types of frequency will vary from unit to unit due to normal pro- crystal oscillator circuits can be used; one with series cess parameter variation. Furthermore, the difference resonance, or one with parallel resonance. in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Figure 8-6 shows implementation of a parallel resonant Cext values. The user also needs to take into account oscillator circuit. The circuit is designed to use the fun- variation due to tolerance of external R and C compo- damental frequency of the crystal. The 74AS04 inverter nents used. Figure 8-8 shows how the R/C combina- performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kW resistor provides the tion is connected to the PIC16CXX. For Rext values negative feedback for stability. The 10 kW potentiome- below 2.2 kW , the oscillator operation may become unstable, or stop completely. For very high Rext values ter biases the 74AS04 in the linear region. This could (e.g. 1 MW ), the oscillator becomes sensitive to noise, be used for external oscillator designs. humidity and leakage. Thus, we recommend to keep FIGURE 8-6: EXTERNAL PARALLEL Rext between 3 kW and 100 kW . RESONANT CRYSTAL Although the oscillator will operate with no external OSCILLATOR CIRCUIT capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or +5V To Other small external capacitance, the oscillation frequency Devices can vary dramatically due to changes in external 10k capacitances, such as PCB trace capacitance or pack- 4.7k 74AS04 PIC16CXXX age lead frame capacitance. 74AS04 CLKIN See characterization data for desired device for RC fre- quency variation from part to part due to normal pro- cess variation. The variation is larger for larger R (since 10k leakage current variation will affect RC frequency more XTAL for large R) and for smaller C (since variation of input 10k capacitance will affect RC frequency more). See characterization data for desired device for varia- 20 pF 20 pF tion of oscillator frequency due to VDD for given Rext/ Cext values as well as frequency variation due to oper- Figure 8-7 shows a series resonant oscillator circuit. ating temperature for given R, C, and VDD values. This circuit is also designed to use the fundamental fre- The oscillator frequency, divided by 4, is available on quency of the crystal. The inverter performs a 180- the OSC2/CLKOUT pin, and can be used for test pur- degree phase shift in a series resonant oscillator cir- poses or to synchronize other logic (see Figure 3-2 for cuit. The 330 kW resistors provide the negative feed- waveform). back to bias the inverters in their linear region. FIGURE 8-8: RC OSCILLATOR MODE FIGURE 8-7: EXTERNAL SERIES RESONANT CRYSTAL VDD OSCILLATOR CIRCUIT Rext Internal To Other OSC1 330 kW 330 kW Devices clock 74AS04 74AS04 74AS04 PIC16CXXX Cext PIC16CXXX CLKIN VSS 0.1 m F OSC2/CLKOUT Fosc/4 XTAL (cid:211) 1997 Microchip Technology Inc. DS30272A-page 51

PIC16C71X 8.3 Reset WDT Reset, on MCLR reset during SLEEP, and Brown- out Reset (BOR). They are not affected by a WDT Applicable Devices 710 71 711 715 Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differ- The PIC16CXX differentiates between various kinds of ently in different reset situations as indicated in Table 8- reset: 7, Table 8-8 and Table 8-9. These bits are used in soft- • Power-on Reset (POR) ware to determine the nature of the reset. See Table 8- 10 and Table 8-11 for a full description of reset states • MCLR reset during normal operation of all registers. • MCLR reset during SLEEP A simplified block diagram of the on-chip reset circuit is • WDT Reset (normal operation) shown in Figure 8-9. • Brown-out Reset (BOR) (PIC16C710/711/715) • Parity Error Reset (PIC16C715) The PIC16C710/711/715 have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore Some registers are not affected in any reset condition; small pulses. their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset It should be noted that a WDT Reset does not drive state” on Power-on Reset (POR), on the MCLR and MCLR pin low. FIGURE 8-9: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/VPP Pin Program MPEEN Memory Parity(3) WDT SLEEP Module WDT Time-out VDD rise detect Power-on Reset VDD Brown-out Reset(2) BODEN S OST/PWRT OST Chip_Reset 10-bit Ripple-counter R Q OSC1/ CLKIN Pin PWRT On-chip(1) 10-bit Ripple-counter RC OSC Enable PWRT See Table 8-6 for time-out situations. Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: Brown-out Reset is implemented on the PIC16C710/711/715. 3: Parity Error Reset is implemented on the PIC16C715. DS30272A-page 52 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 8.4 Power-on Reset (POR), Power-up The power-up time delay will vary from chip to chip due Timer (PWRT) and Oscillator Start-up to VDD, temperature, and process variation. See DC Timer (OST), and Brown-out Reset parameters for details. (BOR) 8.4.3 OSCILLATOR START-UP TIMER (OST) 8.4.1 POWER-ON RESET (POR) Applicable Devices 710 71 711 715 Applicable Devices 710 71 711 715 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the A Power-on Reset pulse is generated on-chip when PWRT delay is over. This ensures that the crystal oscil- VDD rise is detected (in the range of 1.5V - 2.1V). To lator or resonator has started and stabilized. take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate The OST time-out is invoked only for XT, LP and HS external RC components usually needed to create a modes and only on Power-on Reset or wake-up from Power-on Reset. A maximum rise time for VDD is spec- SLEEP. ified. See Electrical Specifications for details. 8.4.4 BROWN-OUT RESET (BOR) When the device starts normal operation (exits the reset condition), device operating parameters (voltage, Applicable Devices 710 71 711 715 frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device A configuration bit, BODEN, can disable (if clear/pro- must be held in reset until the operating conditions are grammed) or enable (if set) the Brown-out Reset cir- met. Brown-out Reset may be used to meet the startup cuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for conditions. greater than parameter #35, the brown-out situation will For additional information, refer to Application Note reset the chip. A reset may not occur if VDD falls below 4.0V for less than parameter #35. The chip will remain AN607, "Power-up Trouble Shooting." in Brown-out Reset until VDD rises above BVDD. The 8.4.2 POWER-UP TIMER (PWRT) Power-up Timer will now be invoked and will keep the chip in RESET an additional 72 ms. If VDD drops below Applicable Devices 710 71 711 715 BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up The Power-up Timer provides a fixed 72 ms nominal Timer will be initialized. Once VDD rises above BVDD, time-out on power-up only, from the POR. The Power- the Power-up Timer will execute a 72 ms time delay. up Timer operates on an internal RC oscillator. The The Power-up Timer should always be enabled when chip is kept in reset as long as the PWRT is active. The Brown-out Reset is enabled. Figure 8-10 shows typical PWRT’s time delay allows VDD to rise to an acceptable brown-out situations. level. A configuration bit is provided to enable/disable the PWRT. FIGURE 8-10: BROWN-OUT SITUATIONS VDD BVDD Internal 72 ms Reset VDD BVDD Internal <72 ms 72 ms Reset VDD BVDD Internal 72 ms Reset (cid:211) 1997 Microchip Technology Inc. DS30272A-page 53

PIC16C71X 8.4.5 TIME-OUT SEQUENCE Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The Applicable Devices 710 71 711 715 user must set this bit following a Power-on Reset. On power-up the time-out sequence is as follows: First For the PIC16C715, bit2 is PER (Parity Error Reset). It PWRT time-out is invoked after the POR time delay has is cleared on a Parity Error Reset and must be set by expired. Then OST is activated. The total time-out will user software. It will also be set on a Power-on Reset. vary based on oscillator configuration and the status of For the PIC16C715, bit7 is MPEEN (Memory Parity the PWRT. For example, in RC mode with the PWRT Error Enable). This bit reflects the status of the MPEEN disabled, there will be no time-out at all. Figure 8-11, bit in configuration word. It is unaffected by any reset of Figure 8-12, and Figure 8-13 depict time-out interrupt. sequences on power-up. 8.4.7 PARITY ERROR RESET (PER) Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then Applicable Devices 710 71 711 715 bringing MCLR high will begin execution immediately (Figure 8-12). This is useful for testing purposes or to The PIC16C715 has on-chip parity bits that can be synchronize more than one PIC16CXX device operat- used to verify the contents of program memory. Parity ing in parallel. bits may be useful in applications in order to increase overall reliability of a system. Table 8-10 and Table 8-11 show the reset conditions for some special function registers, while Table 8-12 and There are two parity bits for each word of Program Table 8-13 show the reset conditions for all the Memory. The parity bits are computed on alternating registers. bits of the program word. One computation is per- formed using even parity, the other using odd parity. As 8.4.6 POWER CONTROL/STATUS REGISTER a program executes, the parity is verified. The even par- (PCON) ity bit is XOR’d with the even bits in the program mem- ory word. The odd parity bit is negated and XOR’d with Applicable Devices 710 71 711 715 the odd bits in the program memory word. When an The Power Control/Status Register, PCON has up to error is detected, a reset is generated and the PER flag two bits, depending upon the device. bit 2 in the PCON register is cleared (logic ‘0’). This indi- cation can allow software to act on a failure. However, Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is there is no indication of the program memory location unknown on a Power-on Reset. It must then be set by of the failure in Program Memory. This flag can only be the user and checked on subsequent resets to see if bit set (logic ‘1’) by software. BOR cleared, indicating a BOR occurred. The BOR bit The parity array is user selectable during programming. is a "Don’t Care" bit and is not necessarily predictable Bit 7 of the configuration word located at address if the Brown-out Reset circuitry is disabled (by clearing 2007h can be programmed (read as ‘0’) to disable par- bit BODEN in the Configuration Word). ity. If left unprogrammed (read as ‘1’), parity is enabled. TABLE 8-5: TIME-OUT IN VARIOUS SITUATIONS, PIC16C71 Oscillator Configuration Power-up Wake-up from SLEEP PWRTE = 1 PWRTE = 0 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 1024 TOSC RC 72 ms — — TABLE 8-6: TIME-OUT IN VARIOUS SITUATIONS, PIC16C710/711/715 Oscillator Configuration Power-up Wake-up from SLEEP Brown-out PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — DS30272A-page 54 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X TABLE 8-7: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C71 TO PD 1 1 Power-on Reset 0 x Illegal, TO is set on POR x 0 Illegal, PD is set on POR 0 1 WDT Reset 0 0 WDT Wake-up u u MCLR Reset during normal operation 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 8-8: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C710/711 POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 x x Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 8-9: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C715 PER POR BOR TO PD 1 0 x 1 1 Power-on Reset x 0 x 0 x Illegal, TO is set on POR x 0 x x 0 Illegal, PD is set on POR 1 1 0 x x Brown-out Reset 1 1 1 0 1 WDT Reset 1 1 1 0 0 WDT Wake-up 1 1 1 u u MCLR Reset during normal operation 1 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP 0 1 1 1 1 Parity Error Reset 0 0 x x x Illegal, PER is set on POR 0 x 0 x x Illegal, PER is set on BOR (cid:211) 1997 Microchip Technology Inc. DS30272A-page 55

PIC16C71X TABLE 8-10: RESET CONDITION FOR SPECIAL REGISTERS, PIC16C710/71/711 Program STATUS PCON Condition Counter Register Register PIC16C710/711 Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset (PIC16C710/711) 000h 0001 1uuu ---- --u0 Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). TABLE 8-11: RESET CONDITION FOR SPECIAL REGISTERS, PIC16C715 Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx u--- -10x MCLR Reset during normal operation 000h 000u uuuu u--- -uuu MCLR Reset during SLEEP 000h 0001 0uuu u--- -uuu WDT Reset 000h 0000 1uuu u--- -uuu WDT Wake-up PC + 1 uuu0 0uuu u--- -uuu Brown-out Reset 000h 0001 1uuu u--- -uu0 Parity Error Reset 000h uuu1 0uuu u--- -0uu Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu u--- -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). DS30272A-page 56 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X TABLE 8-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C710/71/711 Register Power-on Reset, MCLR Resets Wake-up via Brown-out Reset(5) WDT Reset WDT or Interrupt W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000h 0000h PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA ---x 0000 ---u 0000 ---u uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuuu(1) ADRES xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 00-0 0000 00-0 0000 uu-u uuuu OPTION 1111 1111 1111 1111 uuuu uuuu TRISA ---1 1111 ---1 1111 ---u uuuu TRISB 1111 1111 1111 1111 uuuu uuuu PCON(4) ---- --0u ---- --uu ---- --uu ADCON1 ---- --00 ---- --00 ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note1: One or more bits in INTCON will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 8-10 for reset value for specific condition. 4: The PCON register is not implemented on the PIC16C71. 5: Brown-out reset is not implemented on the PIC16C71. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 57

PIC16C71X TABLE 8-13: INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C715 Register Power-on Reset, MCLR Resets Wake-up via Brown-out Reset WDT Reset WDT or Parity Error Reset Interrupt W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 PC + 1(2) STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA ---x 0000 ---u 0000 ---u uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u uuuu uuuu(1) PIR1 -0-- ---- -0-- ---- -u-- ----(1) ADCON0 0000 00-0 0000 00-0 uuuu uu-u OPTION 1111 1111 1111 1111 uuuu uuuu TRISA ---1 1111 ---1 1111 ---u uuuu TRISB 1111 1111 1111 1111 uuuu uuuu PIE1 -0-- ---- -0-- ---- -u-- ---- PCON ---- -qqq ---- -1uu ---- -1uu ADCON1 ---- --00 ---- --00 ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 8-11 for reset value for specific condition. DS30272A-page 58 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET (cid:211) 1997 Microchip Technology Inc. DS30272A-page 59

PIC16C71X FIGURE 8-14: EXTERNAL POWER-ON FIGURE 8-15: EXTERNAL BROWN-OUT RESET CIRCUIT (FOR SLOW PROTECTION CIRCUIT 1 VDD POWER-UP) VDD VDD 33k VDD 10k D R MCLR R1 40k MCLR PIC16CXX C PIC16CXX Note1: This circuit will activate reset when VDD Note1: External Power-on Reset circuit is goes below (Vz + 0.7V) where Vz = Zener required only if VDD power-up slope is too voltage. slow. The diode D helps discharge the 2: Internal brown-out detection on the capacitor quickly when VDD powers down. PIC16C710/711/715 should be disabled 2: R < 40 kW is recommended to make sure when using this circuit. that voltage drop across R does not violate 3: Resistors should be adjusted for the char- the device’s electrical specification. acteristics of the transistor. 3: R1 = 100W to 1 kW will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin break- FIGURE 8-16: EXTERNAL BROWN-OUT down due to Electrostatic Discharge PROTECTION CIRCUIT 2 (ESD) or Electrical Overstress (EOS). VDD VDD R1 Q1 MCLR R2 40k PIC16CXX Note1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 VDD • = 0.7V R1 + R2 2: Internal brown-out detection on the PIC16C710/711/715 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. DS30272A-page 60 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 8.5 Interrupts For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be Applicable Devices 710 71 711 715 three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 8-19). The PIC16C71X family has 4 sources of interrupt. The latency is the same for one or two cycle instruc- tions. Individual interrupt flag bits are set regardless of Interrupt Sources the status of their corresponding mask bit or the GIE External interrupt RB0/INT bit. TMR0 overflow interrupt Note: For the PIC16C71 PORTB change interrupts (pins RB7:RB4) If an interrupt occurs while the Global Inter- A/D Interrupt rupt Enable (GIE) bit is being cleared, the The interrupt control register (INTCON) records indi- GIE bit may unintentionally be re-enabled vidual interrupt requests in flag bits. It also has individ- by the user’s Interrupt Service Routine (the ual and global interrupt enable bits. RETFIE instruction). The events that would cause this to occur are: Note: Individual interrupt flag bits are set regard- 1. An instruction clears the GIE bit while less of the status of their corresponding an interrupt is acknowledged. mask bit or the GIE bit. 2. The program branches to the Interrupt A global interrupt enable bit, GIE (INTCON<7>) vector and executes the Interrupt Ser- enables (if set) all un-masked interrupts or disables (if vice Routine. cleared) all interrupts. When bit GIE is enabled, and an interrupt’s flag bit and mask bit are set, the interrupt will 3. The Interrupt Service Routine com- vector immediately. Individual interrupts can be dis- pletes with the execution of the RET- abled through their corresponding enable bits in vari- FIE instruction. This causes the GIE ous registers. Individual interrupt bits are set bit to be set (enables interrupts), and regardless of the status of the GIE bit. The GIE bit is the program returns to the instruction cleared on reset. after the one which was meant to dis- able interrupts. The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which Perform the following to ensure that inter- re-enables interrupts. rupts are globally disabled: The RB0/INT pin interrupt, the RB port change inter- LOOP BCF INTCON, GIE ; Disable global rupt and the TMR0 overflow interrupt flags are con- ; interrupt bit tained in the INTCON register. BTFSC INTCON, GIE ; Global interrupt ; disabled? The peripheral interrupt flags are contained in the spe- GOTO LOOP ; NO, try again cial function registers PIR1 and PIR2. The correspond- : ; Yes, continue ing interrupt enable bits are contained in special ; with program function registers PIE1 and PIE2, and the peripheral ; flow interrupt enable bit is contained in special function reg- ister INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 61

PIC16C71X FIGURE 8-17: INTERRUPT LOGIC, PIC16C710, 71, 711 Wakeup T0IF (If in SLEEP mode) T0IE INTF INTE Interrupt to CPU RBIF RBIE ADIF ADIE GIE FIGURE 8-18: INTERRUPT LOGIC, PIC16C715 Wakeup T0IF (If in SLEEP mode) T0IE INTF INTE Interrupt to CPU RBIF RBIE ADIF ADIF ADIE GIE DS30272A-page 62 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 8.5.1 INT INTERRUPT 8.5.2 TMR0 INTERRUPT External interrupt on RB0/INT pin is edge triggered: An overflow (FFh fi 00h) in the TMR0 register will set either rising if bit INTEDG (OPTION<6>) is set, or fall- flag bit T0IF (INTCON<2>). The interrupt can be ing, if the INTEDG bit is clear. When a valid edge enabled/disabled by setting/clearing enable bit T0IE appears on the RB0/INT pin, flag bit INTF (INTCON<5>). (Section 6.0) (INTCON<1>) is set. This interrupt can be disabled by 8.5.3 PORTB INTCON CHANGE clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service rou- An input change on PORTB<7:4> sets flag bit RBIF tine before re-enabling this interrupt. The INT interrupt (INTCON<0>). The interrupt can be enabled/disabled can wake-up the processor from SLEEP, if bit INTE was by setting/clearing enable bit RBIE (INTCON<4>). set prior to going into SLEEP. The status of global inter- (Section 5.2) rupt enable bit GIE decides whether or not the proces- sor branches to the interrupt vector following wake-up. Note: For the PIC16C71 See Section 8.8 for details on SLEEP mode. if a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF inter- rupt flag may not get set. FIGURE 8-19: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag 5 Interrupt Latency 2 (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 PC+1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h) Instruction Inst (PC-1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) executed Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 63

PIC16C71X 8.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key reg- isters during an interrupt i.e., W register and STATUS register. This will have to be implemented in software. Example 8-1 stores and restores the STATUS and W registers. The user register, STATUS_TEMP, must be defined in bank 0. The example: a) Stores the W register. b) Stores the STATUS register in bank 0. c) Executes the ISR code. d) Restores the STATUS register (and bank select bit). e) Restores the W register. EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W DS30272A-page 64 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 8.7 Watchdog Timer (WDT) assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to Applicable Devices 710 71 711 715 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and The Watchdog Timer is as a free running on-chip RC the postscaler, if assigned to the WDT, and prevent it oscillator which does not require any external compo- from timing out and generating a device RESET condi- nents. This RC oscillator is separate from the RC oscil- tion. lator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and The TO bit in the STATUS register will be cleared upon OSC2/CLKOUT pins of the device has been stopped, a Watchdog Timer time-out. for example, by execution of a SLEEP instruction. Dur- ing normal operation, a WDT time-out generates a 8.7.2 WDT PROGRAMMING CONSIDERATIONS device RESET (Watchdog Timer Reset). If the device is It should also be taken into account that under worst in SLEEP mode, a WDT time-out causes the device to case conditions (VDD = Min., Temperature = Max., and wake-up and continue with normal operation (Watch- max. WDT prescaler) it may take several seconds dog Timer Wake-up). The WDT can be permanently before a WDT time-out occurs. disabled by clearing configuration bit WDTE (Section 8.1). Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, 8.7.1 WDT PERIOD the prescaler count will be cleared, but the prescaler assignment is not changed. The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with tempera- ture, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be FIGURE 8-20: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 6-6) 0 M Postscaler 1 WDT Timer U X 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure 6-6) 0 1 MUX PSA WDT Note: PSA and PS2:PS0 are bits in the OPTION register. Time-out FIGURE 8-21: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note1: See Figure 8-1, Figure 8-2 and Figure 8-3 for operation of these bits. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 65

PIC16C71X 8.8 Power-down Mode (SLEEP) Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip Q clocks are present. Power-down mode is entered by executing a SLEEP instruction. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to If enabled, the Watchdog Timer will be cleared but wake-up through an interrupt event, the corresponding keeps running, the PD bit (STATUS<3>) is cleared, the interrupt enable bit must be set (enabled). Wake-up is TO (STATUS<4>) bit is set, and the oscillator driver is regardless of the state of the GIE bit. If the GIE bit is turned off. The I/O ports maintain the status they had, clear (disabled), the device continues execution at the before the SLEEP instruction was executed (driving instruction after the SLEEP instruction. If the GIE bit is high, low, or hi-impedance). set (enabled), the device executes the instruction after For lowest current consumption in this mode, place all the SLEEP instruction and then branches to the inter- I/O pins at either VDD, or VSS, ensure no external cir- rupt address (0004h). In cases where the execution of cuitry is drawing current from the I/O pin, power-down the instruction following SLEEP is not desirable, the the A/D, disable external clocks. Pull all I/O pins, that user should have a NOP after the SLEEP instruction. are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The 8.8.2 WAKE-UP USING INTERRUPTS T0CKI input should also be at VDD or VSS for lowest When global interrupts are disabled (GIE cleared) and current consumption. The contribution from on-chip any interrupt source has both its interrupt enable bit pull-ups on PORTB should be considered. and interrupt flag bit set, one of the following will occur: The MCLR pin must be at a logic high level (VIHMC). • If the interrupt occurs before the the execution of 8.8.1 WAKE-UP FROM SLEEP a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT The device can wake up from SLEEP through one of postscaler will not be cleared, the TO bit will not the following events: be set and PD bits will not be cleared. 1. External reset input on MCLR pin. • If the interrupt occurs during or after the execu- 2. Watchdog Timer Wake-up (if WDT was tion of a SLEEP instruction, the device will immedi- enabled). ately wake up from sleep . The SLEEP instruction will be completely executed before the wake-up. 3. Interrupt from INT pin, RB port change, or some Therefore, the WDT and WDT postscaler will be Peripheral Interrupts. cleared, the TO bit will be set and the PD bit will External MCLR Reset will cause a device reset. All be cleared. other events are considered a continuation of program Even if the flag bits were checked before executing a execution and cause a "wake-up". The TO and PD bits SLEEP instruction, it may be possible for flag bits to in the STATUS register can be used to determine the become set before the SLEEP instruction completes. To cause of device reset. The PD bit, which is set on determine whether a SLEEP instruction executed, test power-up, is cleared when SLEEP is invoked. The TO bit the PD bit. If the PD bit is set, the SLEEP instruction was is cleared if a WDT time-out occurred (and caused executed as a NOP. wake-up). To ensure that the WDT is cleared, a CLRWDT instruc- The following peripheral interrupts can wake the device tion should be executed before a SLEEP instruction. from SLEEP: 1. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 2. A/D conversion (when A/D clock source is RC). DS30272A-page 66 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X FIGURE 8-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit Processor in (INTCON<7>) SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Instruction fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Ienxsetcruuctetidon Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 8.9 Program Verification/Code Protection The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the If the code protection bit(s) have not been pro- MCLR (VPP) pin from VIL to VIHH (see programming grammed, the on-chip program memory can be read specification). RB6 becomes the programming clock out for verification purposes. and RB7 becomes the programming data. Both RB6 Note: Microchip does not recommend code pro- and RB7 are Schmitt Trigger inputs in this mode. tecting windowed devices. After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6- 8.10 ID Locations bit command is then supplied to the device. Depending Four memory locations (2000h - 2003h) are designated on the command, 14-bits of program data are then sup- as ID locations where the user can store checksum or plied to or from the device, depending if the command other code-identification numbers. These locations are was a load or a read. For complete details of serial pro- not accessible during normal execution but are read- gramming, please refer to the PIC16C6X/7X Program- able and writable during program/verify. It is recom- ming Specifications (Literature #DS30228). mended that only the 4 least significant bits of the ID FIGURE 8-23: TYPICAL IN-CIRCUIT SERIAL location are used. PROGRAMMING 8.11 In-Circuit Serial Programming CONNECTION PIC16CXX microcontrollers can be serially pro- grammed while in the end application circuit. This is To Normal simply done with two lines for clock and data, and three Connections External other lines for power, ground, and the programming Connector PIC16CXX voltage. This allows customers to manufacture boards Signals with unprogrammed devices, and then program the +5V VDD microcontroller just before shipping the product. This 0V VSS also allows the most recent firmware or a custom firm- ware to be programmed. VPP MCLR/VPP CLK RB6 Data I/O RB7 VDD To Normal Connections (cid:211) 1997 Microchip Technology Inc. DS30272A-page 67

PIC16C71X NOTES: DS30272A-page 68 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 9.0 INSTRUCTION SET SUMMARY • Byte-oriented operations • Bit-oriented operations Each PIC16CXX instruction is a 14-bit word divided • Literal and control operations into an OPCODE which specifies the instruction type and one or more operands which further specify the All instructions are executed within one single instruc- operation of the instruction. The PIC16CXX instruction tion cycle, unless a conditional test is true or the pro- set summary in Table 9-2 lists byte-oriented, bit-ori- gram counter is changed as a result of an instruction. ented, and literal and control operations. Table 9-1 In this case, the execution takes two instruction cycles shows the opcode field descriptions. with the second cycle executed as a NOP. One instruc- tion cycle consists of four oscillator periods. Thus, for For byte-oriented instructions, 'f' represents a file reg- an oscillator frequency of 4 MHz, the normal instruction ister designator and 'd' represents a destination desig- execution time is 1 m s. If a conditional test is true or the nator. The file register designator specifies which file program counter is changed as a result of an instruc- register is to be used by the instruction. tion, the instruction execution time is 2 m s. The destination designator specifies where the result of Table 9-2 lists the instructions recognized by the the operation is to be placed. If 'd' is zero, the result is MPASM assembler. placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. Figure 9-1 shows the general formats that the instruc- tions can have. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected Note: To maintain upward compatibility with by the operation, while 'f' represents the number of the future PIC16CXX products, do not use the file in which the bit is located. OPTION and TRIS instructions. For literal and control operations, 'k' represents an All examples use the following format to represent a eight or eleven bit constant or literal value. hexadecimal number: TABLE 9-1: OPCODE FIELD 0xhh DESCRIPTIONS where h signifies a hexadecimal digit. Field Description FIGURE 9-1: GENERAL FORMAT FOR INSTRUCTIONS f Register file address (0x00 to 0x7F) W Working register (accumulator) Byte-oriented file register operations b Bit address within an 8-bit file register 13 8 7 6 0 k Literal field, constant data or label OPCODE d f (FILE #) x Don't care location (= 0 or 1) d = 0 for destination W The assembler will generate code with x = 0. It is the d = 1 for destination f recommended form of use for compatibility with all f = 7-bit file register address Microchip software tools. d Destination select; d = 0: store result in W, Bit-oriented file register operations d = 1: store result in file register f. 13 10 9 7 6 0 Default is d = 1 OPCODE b (BIT #) f (FILE #) label Label name TOS Top of Stack b = 3-bit bit address f = 7-bit file register address PC Program Counter PCLATH Program Counter High Latch Literal and control operations GIE Global Interrupt Enable bit WDT Watchdog Timer/Counter General TO Time-out bit 13 8 7 0 PD Power-down bit OPCODE k (literal) dest Destination either the W register or the specified register file location k = 8-bit immediate value [ ] Options ( ) Contents CALL and GOTO instructions only fi Assigned to 13 11 10 0 < > Register bit field OPCODE k (literal) ˛ In the set of k = 11-bit immediate value italics User defined term (font is courier) The instruction set is highly orthogonal and is grouped into three basic categories: (cid:211) 1997 Microchip Technology Inc. DS30272A-page 69

PIC16C71X TABLE 9-2: PIC16CXX INSTRUCTION SET Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS30272A-page 70 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 9.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [label] ADDLW k Syntax: [label] ANDLW k Operands: 0 £ k £ 255 Operands: 0 £ k £ 255 Operation: (W) + k fi (W) Operation: (W) .AND. (k) fi (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk Description: The contents of the W register are Description: The contents of W register are added to the eight bit literal 'k' and the AND’ed with the eight bit literal 'k'. The result is placed in the W register. result is placed in the W register. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to literal 'k' data W literal "k" data W Example: ADDLW 0x15 Example ANDLW 0x5F Before Instruction Before Instruction W = 0x10 W = 0xA3 After Instruction After Instruction W = 0x25 W = 0x03 ADDWF Add W and f ANDWF AND W with f Syntax: [label] ADDWF f,d Syntax: [label] ANDWF f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] d ˛ [0,1] Operation: (W) + (f) fi (dest) Operation: (W) .AND. (f) fi (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 00 0111 dfff ffff Encoding: 00 0101 dfff ffff Description: Add the contents of the W register Description: AND the W register with register 'f'. If with register 'f'. If 'd' is 0 the result is 'd' is 0 the result is stored in the W stored in the W register. If 'd' is 1 the register. If 'd' is 1 the result is stored result is stored back in register 'f'. back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register data Dest register data Dest 'f' 'f' Example ADDWF FSR, 0 Example ANDWF FSR, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 FSR= 0xC2 FSR= 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 FSR= 0xC2 FSR= 0x02 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 71

PIC16C71X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [label] BCF f,b Syntax: [label] BTFSC f,b Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 0 £ b £ 7 0 £ b £ 7 Operation: 0 fi (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff Description: Bit 'b' in register 'f' is cleared. Description: If bit 'b' in register 'f' is '1' then the next instruction is executed. Words: 1 If bit 'b', in register 'f', is '0' then the next Cycles: 1 instruction is discarded, and a NOP is executed instead, making this a 2TCY Q Cycle Activity: Q1 Q2 Q3 Q4 instruction. Decode Read Process Write Words: 1 register data register 'f' 'f' Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Example BCF FLAG_REG, 7 Decode Read Process NOP Before Instruction register 'f' data FLAG_REG = 0xC7 After Instruction If Skip: (2nd Cycle) FLAG_REG = 0x47 Q1 Q2 Q3 Q4 NOP NOP NOP NOP Example HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address TRUE BSF Bit Set f if FLAG<1>=1, Syntax: [label] BSF f,b PC = address FALSE Operands: 0 £ f £ 127 0 £ b £ 7 Operation: 1 fi (f<b>) Status Affected: None Encoding: 01 01bb bfff ffff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register data register 'f' 'f' Example BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A DS30272A-page 72 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 £ f £ 127 Operands: 0 £ k £ 2047 0 £ b < 7 Operation: (PC)+ 1fi TOS, Operation: skip if (f<b>) = 1 k fi PC<10:0>, (PCLATH<4:3>) fi PC<12:11> Status Affected: None Status Affected: None Encoding: 01 11bb bfff ffff Description: If bit 'b' in register 'f' is '0' then the next Encoding: 10 0kkk kkkk kkkk instruction is executed. Description: Call Subroutine. First, return address If bit 'b' is '1', then the next instruction is (PC+1) is pushed onto the stack. The discarded and a NOP is executed eleven bit immediate address is loaded instead, making this a 2TCY instruction. into PC bits <10:0>. The upper bits of Words: 1 the PC are loaded from PCLATH. CALL is a two cycle instruction. Cycles: 1(2) Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 2 Decode Read Process NOP Q Cycle Activity: Q1 Q2 Q3 Q4 register 'f' data 1st Cycle Decode Read Process Write to If Skip: (2nd Cycle) literal 'k', data PC Q1 Q2 Q3 Q4 Push PC to Stack NOP NOP NOP NOP 2nd Cycle NOP NOP NOP NOP Example HERE BTFSC FLAG,1 Example HERE CALL THERE FALSE GOTO PROCESS_CODE TRUE • Before Instruction • PC = Address HERE • After Instruction Before Instruction PC = Address THERE TOS= Address HERE+1 PC = address HERE After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE (cid:211) 1997 Microchip Technology Inc. DS30272A-page 73

PIC16C71X CLRF Clear f CLRW Clear W Syntax: [label] CLRF f Syntax: [ label ] CLRW Operands: 0 £ f £ 127 Operands: None Operation: 00h fi (f) Operation: 00h fi (W) 1 fi Z 1 fi Z Status Affected: Z Status Affected: Z Encoding: 00 0001 1fff ffff Encoding: 00 0001 0xxx xxxx Description: The contents of register 'f' are cleared Description: W register is cleared. Zero bit (Z) is and the Z bit is set. set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write Decode NOP Process Write to register data register 'f' data W 'f' Example CLRW Example CLRF FLAG_REG Before Instruction Before Instruction W = 0x5A FLAG_REG = 0x5A After Instruction After Instruction W = 0x00 FLAG_REG = 0x00 Z = 1 Z = 1 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h fi WDT 0 fi WDT prescaler, 1 fi TO 1 fi PD Status Affected: TO, PD Encoding: 00 0000 0110 0100 Description: CLRWDT instruction resets the Watch- dog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode NOP Process Clear data WDT Counter Example CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler= 0 TO = 1 PD = 1 DS30272A-page 74 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] d ˛ [0,1] Operation: (f) fi (dest) Operation: (f) - 1 fi (dest); skip if result = 0 Status Affected: Z Status Affected: None Encoding: 00 1001 dfff ffff Encoding: 00 1011 dfff ffff Description: The contents of register 'f' are comple- Description: The contents of register 'f' are decre- mented. If 'd' is 0 the result is stored in mented. If 'd' is 0 the result is placed in W. If 'd' is 1 the result is stored back in the W register. If 'd' is 1 the result is register 'f'. placed back in register 'f'. If the result is 1, the next instruction, is Words: 1 executed. If the result is 0, then a NOP is Cycles: 1 executed instead making it a 2TCY instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to Cycles: 1(2) register data dest 'f' Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Example COMF REG1,0 register data dest 'f' Before Instruction REG1 = 0x13 If Skip: (2nd Cycle) After Instruction Q1 Q2 Q3 Q4 REG1 = 0x13 W = 0xEC NOP NOP NOP NOP DECF Decrement f Example HERE DECFSZ CNT, 1 GOTO LOOP Syntax: [label] DECF f,d CONTINUE • Operands: 0 £ f £ 127 • d ˛ [0,1] • Operation: (f) - 1 fi (dest) Before Instruction PC = address HERE Status Affected: Z After Instruction CNT = CNT - 1 Encoding: 00 0011 dfff ffff if CNT= 0, Description: Decrement register 'f'. If 'd' is 0 the PC = address CONTINUE rise s1u tlht eis r estsourlet dis isnt othreed W b areckg iisnt erer. gIfis 'tde' r if CNT„ 0, 'f'. PC = address HERE+1 Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register data dest 'f' Example DECF CNT, 1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 75

PIC16C71X GOTO Unconditional Branch INCF Increment f Syntax: [ label ] GOTO k Syntax: [ label ] INCF f,d Operands: 0 £ k £ 2047 Operands: 0 £ f £ 127 d ˛ [0,1] Operation: k fi PC<10:0> PCLATH<4:3> fi PC<12:11> Operation: (f) + 1 fi (dest) Status Affected: None Status Affected: Z Encoding: 10 1kkk kkkk kkkk Encoding: 00 1010 dfff ffff Description: GOTO is an unconditional branch. The Description: The contents of register 'f' are incre- eleven bit immediate value is loaded mented. If 'd' is 0 the result is placed into PC bits <10:0>. The upper bits of in the W register. If 'd' is 1 the result is PC are loaded from PCLATH<4:3>. placed back in register 'f'. GOTO is a two cycle instruction. Words: 1 Words: 1 Cycles: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to 1st Cycle Decode Read Process Write to register data dest literal 'k' data PC 'f' 2nd Cycle NOP NOP NOP NOP Example INCF CNT, 1 Example GOTO THERE Before Instruction After Instruction CNT = 0xFF PC = Address THERE Z = 0 After Instruction CNT = 0x00 Z = 1 DS30272A-page 76 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X INCFSZ Increment f, Skip if 0 IORLW Inclusive OR Literal with W Syntax: [ label ] INCFSZ f,d Syntax: [ label ] IORLW k Operands: 0 £ f £ 127 Operands: 0 £ k £ 255 d ˛ [0,1] Operation: (W) .OR. k fi (W) Operation: (f) + 1 fi (dest), skip if result = 0 Status Affected: Z Status Affected: None Encoding: 11 1000 kkkk kkkk Encoding: 00 1111 dfff ffff Description: The contents of the W register is Description: The contents of register 'f' are incre- OR’ed with the eight bit literal 'k'. The mented. If 'd' is 0 the result is placed result is placed in the W register. in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 If the result is 1, the next instruction is executed. If the result is 0, a NOP is Cycles: 1 executed instead making it a 2TCY instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Words: 1 Decode Read Process Write to literal 'k' data W Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Example IORLW 0x35 Decode Read Process Write to Before Instruction register data dest 'f' W = 0x9A After Instruction If Skip: (2nd Cycle) W = 0xBF Q1 Q2 Q3 Q4 Z = 1 NOP NOP NOP NOP Example HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE • • • Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT„ 0, PC = address HERE +1 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 77

PIC16C71X IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVLW k Operands: 0 £ f £ 127 Operands: 0 £ k £ 255 d ˛ [0,1] Operation: k fi (W) Operation: (W) .OR. (f) fi (dest) Status Affected: None Status Affected: Z Encoding: 11 00xx kkkk kkkk Encoding: 00 0100 dfff ffff Description: The eight bit literal 'k' is loaded into W Description: Inclusive OR the W register with regis- register. The don’t cares will assemble ter 'f'. If 'd' is 0 the result is placed in as 0’s. the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to literal 'k' data W Decode Read Process Write to register data dest 'f' Example MOVLW 0x5A After Instruction Example IORWF RESULT, 0 W = 0x5A Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 Z = 1 MOVWF Move W to f MOVF Move f Syntax: [ label ] MOVWF f Syntax: [ label ] MOVF f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (W) fi (f) Operation: (f) fi (dest) Status Affected: None Status Affected: Z Encoding: 00 0000 1fff ffff Encoding: 00 1000 dfff ffff Description: Move data from W register to register 'f'. Description: The contents of register f is moved to a destination dependant upon the sta- Words: 1 tus of d. If d = 0, destination is W reg- Cycles: 1 ister. If d = 1, the destination is file register f itself. d = 1 is useful to test a Q Cycle Activity: Q1 Q2 Q3 Q4 file register since status flag Z is Decode Read Process Write affected. register data register 'f' 'f' Words: 1 Cycles: 1 Example MOVWF OPTION_REG Q Cycle Activity: Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write to OPTION = 0xFF register data dest W = 0x4F 'f' After Instruction OPTION = 0x4F Example MOVF FSR, 0 W = 0x4F After Instruction W = value in FSR register Z = 1 DS30272A-page 78 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] NOP Syntax: [ label ] RETFIE Operands: None Operands: None Operation: No operation Operation: TOS fi PC, 1 fi GIE Status Affected: None Status Affected: None Encoding: 00 0000 0xx0 0000 Encoding: 00 0000 0000 1001 Description: No operation. Description: Return from Interrupt. Stack is POPed Words: 1 and Top of Stack (TOS) is loaded in Cycles: 1 the PC. Interrupts are enabled by set- ting Global Interrupt Enable bit, GIE Q Cycle Activity: Q1 Q2 Q3 Q4 (INTCON<7>). This is a two cycle Decode NOP NOP NOP instruction. Words: 1 Example NOP Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 1st Cycle Decode NOP Set the Pop from GIE bit the Stack 2nd Cycle NOP NOP NOP NOP Example RETFIE After Interrupt PC = TOS GIE = 1 OPTION Load Option Register Syntax: [ label ] OPTION Operands: None Operation: (W) fi OPTION Status Affected: None Encoding: 00 0000 0110 0010 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code com- patibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 79

PIC16C71X RETLW Return with Literal in W RETURN Return from Subroutine Syntax: [ label ] RETLW k Syntax: [ label ] RETURN Operands: 0 £ k £ 255 Operands: None Operation: k fi (W); Operation: TOS fi PC TOS fi PC Status Affected: None Status Affected: None Encoding: 00 0000 0000 1000 Encoding: 11 01xx kkkk kkkk Description: Return from subroutine. The stack is Description: The W register is loaded with the eight POPed and the top of the stack (TOS) bit literal 'k'. The program counter is is loaded into the program counter. loaded from the top of the stack (the This is a two cycle instruction. return address). This is a two cycle Words: 1 instruction. Cycles: 2 Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 2 1st Cycle Decode NOP NOP Pop from Q Cycle Activity: Q1 Q2 Q3 Q4 the Stack 1st Cycle Decode Read NOP Write to 2nd Cycle NOP NOP NOP NOP literal 'k' W, Pop from the Stack Example RETURN 2nd Cycle NOP NOP NOP NOP After Interrupt PC = TOS Example CALL TABLE ;W contains table ;offset value • ;W now has table value • • TABLE ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 DS30272A-page 80 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] d ˛ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: 00 1101 dfff ffff Encoding: 00 1100 dfff ffff Description: The contents of register 'f' are rotated Description: The contents of register 'f' are rotated one bit to the left through the Carry one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is the W register. If 'd' is 1 the result is stored back in register 'f'. placed back in register 'f'. C Register f C Register f Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register data dest register data dest 'f' 'f' Example RLF REG1,0 Example RRF REG1,0 Before Instruction Before Instruction REG1 = 1110 0110 REG1 = 1110 0110 C = 0 C = 0 After Instruction After Instruction REG1 = 1110 0110 REG1 = 1110 0110 W = 1100 1100 W = 0111 0011 C = 1 C = 0 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 81

PIC16C71X SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SLEEP Syntax: [ label ] SUBLW k Operands: None Operands: 0 £ k £ 255 Operation: 00h fi WDT, Operation: k - (W) fi ( W) 0 fi WDT prescaler, Status Affected: C, DC, Z 1 fi TO, Encoding: 11 110x kkkk kkkk 0 fi PD Description: The W register is subtracted (2’s comple- Status Affected: TO, PD ment method) from the eight bit literal 'k'. Encoding: 00 0000 0110 0011 The result is placed in the W register. Description: The power-down status bit, PD is Words: 1 cleared. Time-out status bit, TO is Cycles: 1 set. Watchdog Timer and its pres- caler are cleared. Q Cycle Activity: Q1 Q2 Q3 Q4 The processor is put into SLEEP Decode Read Process Write to W mode with the oscillator stopped. literal 'k' data See Section 8.8 for more details. Words: 1 Example 1: SUBLW 0x02 Cycles: 1 Before Instruction Q Cycle Activity: Q1 Q2 Q3 Q4 W = 1 C = ? Decode NOP NOP Go to Sleep Z = ? After Instruction Example: SLEEP W = 1 C = 1; result is positive Z = 0 Example 2: Before Instruction W = 2 C = ? Z = ? After Instruction W = 0 C = 1; result is zero Z = 1 Example 3: Before Instruction W = 3 C = ? Z = ? After Instruction W = 0xFF C = 0; result is nega- tive Z = 0 DS30272A-page 82 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] SUBWF f,d Syntax: [ label ] SWAPF f,d Operands: 0 £ f £ 127 Operands: 0 £ f £ 127 d ˛ [0,1] d ˛ [0,1] Operation: (f) - (W) fi ( dest) Operation: (f<3:0>) fi (dest<7:4>), (f<7:4>) fi (dest<3:0>) Status Affected: C, DC, Z Status Affected: None Encoding: 00 0010 dfff ffff Encoding: 00 1110 dfff ffff Description: Subtract (2’s complement method) W reg- ister from register 'f'. If 'd' is 0 the result is Description: The upper and lower nibbles of regis- stored in the W register. If 'd' is 1 the ter 'f' are exchanged. If 'd' is 0 the result is stored back in register 'f'. result is placed in W register. If 'd' is 1 the result is placed in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register 'f' data dest Decode Read Process Write to register 'f' data dest Example 1: SUBWF REG1,1 Example SWAPF REG, 0 Before Instruction Before Instruction REG1 = 3 W = 2 REG1 = 0xA5 C = ? After Instruction Z = ? REG1 = 0xA5 After Instruction W = 0x5A REG1 = 1 W = 2 C = 1; result is positive Z = 0 Example 2: Before Instruction TRIS Load TRIS Register REG1 = 2 Syntax: [label] TRIS f W = 2 Operands: 5 £ f £ 7 C = ? Z = ? Operation: (W) fi TRIS register f; After Instruction Status Affected: None Encoding: 00 0000 0110 0fff REG1 = 0 W = 2 Description: The instruction is supported for code C = 1; result is zero compatibility with the PIC16C5X prod- Z = 1 ucts. Since TRIS registers are read- Example 3: Before Instruction able and writable, the user can directly address them. REG1 = 1 Words: 1 W = 2 C = ? Cycles: 1 Z = ? Example After Instruction To maintain upward compatibility REG1 = 0xFF with future PIC16CXX products, do W = 2 not use this instruction. C = 0; result is negative Z = 0 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 83

PIC16C71X XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] XORLW k Syntax: [label] XORWF f,d Operands: 0 £ k £ 255 Operands: 0 £ f £ 127 d ˛ [0,1] Operation: (W) .XOR. k fi ( W) Operation: (W) .XOR. (f) fi ( dest) Status Affected: Z Status Affected: Z Encoding: 11 1010 kkkk kkkk Encoding: 00 0110 dfff ffff Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. Description: Exclusive OR the contents of the W The result is placed in the W regis- register with register 'f'. If 'd' is 0 the ter. result is stored in the W register. If 'd' is 1 the result is stored back in register Words: 1 'f'. Cycles: 1 Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 1 Decode Read Process Write to Q Cycle Activity: Q1 Q2 Q3 Q4 literal 'k' data W Decode Read Process Write to register data dest Example: XORLW 0xAF 'f' Before Instruction Example XORWF REG 1 W = 0xB5 Before Instruction After Instruction REG = 0xAF W = 0x1A W = 0xB5 After Instruction REG = 0x1A W = 0xB5 DS30272A-page 84 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 10.0 DEVELOPMENT SUPPORT 10.3 ICEPIC: Low-Cost PIC16CXXX In-Circuit Emulator 10.1 Development Tools ICEPIC is a low-cost in-circuit emulator solution for the The PICmicro(cid:228) microcontrollers are supported with a Microchip PIC16C5X and PIC16CXXX families of 8-bit full range of hardware and software development tools: OTP microcontrollers. • PICMASTER/PICMASTER CE Real-Time ICEPIC is designed to operate on PC-compatible In-Circuit Emulator machines ranging from 286-AT(cid:226) through Pentium(cid:228) • ICEPIC Low-Cost PIC16C5X and PIC16CXXX based machines under Windows 3.x environment. In-Circuit Emulator ICEPIC features real time, non-intrusive emulation. (cid:226) • PRO MATE II Universal Programmer 10.4 PRO MATE II: Universal Programmer (cid:226) • PICSTART Plus Entry-Level Prototype Programmer The PRO MATE II Universal Programmer is a full-fea- • PICDEM-1 Low-Cost Demonstration Board tured programmer capable of operating in stand-alone • PICDEM-2 Low-Cost Demonstration Board mode as well as PC-hosted mode. • PICDEM-3 Low-Cost Demonstration Board The PRO MATE II has programmable VDD and VPP • MPASM Assembler supplies which allows it to verify programmed memory • MPLAB(cid:228) SIM Software Simulator at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to • MPLAB-C (C Compiler) enter commands and a modular detachable socket • Fuzzy Logic Development System assembly to support various package types. In stand- (fuzzyTECH(cid:226) - MP) alone mode the PRO MATE II can read, verify or pro- gram PIC12CXXX, PIC14C000, PIC16C5X, 10.2 PICMASTER: High Performance PIC16CXXX and PIC17CXX devices. It can also set Universal In-Circuit Emulator with configuration and code-protect bits in this mode. MPLAB IDE 10.5 PICSTART Plus Entry Level The PICMASTER Universal In-Circuit Emulator is Development System intended to provide the product development engineer with a complete microcontroller design tool set for all The PICSTART programmer is an easy-to-use, low- microcontrollers in the PIC12CXXX, PIC14C000, cost prototype programmer. It connects to the PC via PIC16C5X, PIC16CXXX and PIC17CXX families. one of the COM (RS-232) ports. MPLAB Integrated PICMASTER is supplied with the MPLAB(cid:228) Integrated Development Environment software makes using the Development Environment (IDE), which allows editing, programmer simple and efficient. PICSTART Plus is “make” and download, and source debugging from a not recommended for production programming. single environment. PICSTART Plus supports all PIC12CXXX, PIC14C000, Interchangeable target probes allow the system to be PIC16C5X, PIC16CXXX and PIC17CXX devices with easily reconfigured for emulation of different proces- up to 40 pins. Larger pin count devices such as the sors. The universal architecture of the PICMASTER PIC16C923 and PIC16C924 may be supported with an allows expansion to support all new Microchip micro- adapter socket. controllers. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (cid:226) (and higher) machine platform and Microsoft Windows 3.x environment were chosen to best make these fea- tures available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 85

PIC16C71X 10.6 PICDEM-1 Low-Cost PIC16/17 an RS-232 interface, push-button switches, a potenti- Demonstration Board ometer for simulated analog input, a thermistor and separate headers for connection to an external LCD The PICDEM-1 is a simple board which demonstrates module and a keypad. Also provided on the PICDEM-3 the capabilities of several of Microchip’s microcontrol- board is an LCD panel, with 4 commons and 12 seg- lers. The microcontrollers supported are: PIC16C5X ments, that is capable of displaying time, temperature (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, and day of the week. The PICDEM-3 provides an addi- PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and tional RS-232 interface and Windows 3.1 software for PIC17C44. All necessary hardware and software is showing the demultiplexed LCD signals on a PC. A sim- included to run basic demo programs. The users can ple serial interface allows the user to construct a hard- program the sample microcontrollers provided with ware demultiplexer for the LCD signals. the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firm- 10.9 MPLAB Integrated Development ware. The user can also connect the PICDEM-1 Environment Software board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional pro- The MPLAB IDE Software brings an ease of software totype area is available for the user to build some addi- development previously unseen in the 8-bit microcon- tional hardware and connect it to the microcontroller troller market. MPLAB is a windows based application socket(s). Some of the features include an RS-232 which contains: interface, a potentiometer for simulated analog input, • A full featured editor push-button switches and eight LEDs connected to • Three operating modes PORTB. - editor - emulator 10.7 PICDEM-2 Low-Cost PIC16CXX - simulator Demonstration Board • A project manager • Customizable tool bar and key mapping The PICDEM-2 is a simple demonstration board that • A status bar with project information supports the PIC16C62, PIC16C64, PIC16C65, • Extensive on-line help PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to MPLAB allows you to: run the basic demonstration programs. The user • Edit your source files (either assembly or ‘C’) can program the sample microcontrollers provided • One touch assemble (or compile) and download with the PICDEM-2 board, on a PRO MATE II pro- to PIC16/17 tools (automatically updates all grammer or PICSTART-Plus, and easily test firmware. project information) The PICMASTER emulator may also be used with the • Debug using: PICDEM-2 board to test firmware. Additional prototype - source files area has been provided to the user for adding addi- - absolute listing file tional hardware and connecting it to the microcontroller • Transfer data dynamically via DDE (soon to be socket(s). Some of the features include a RS-232 inter- replaced by OLE) face, push-button switches, a potentiometer for simu- • Run up to four emulators on the same PC lated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connec- The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily tion to an LCD module and a keypad. switch from the low cost simulator to the full featured 10.8 PICDEM-3 Low-Cost PIC16CXXX emulator with minimal retraining due to development Demonstration Board tools. 10.10 Assembler (MPASM) The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC The MPASM Universal Macro Assembler is a PC- package. It will also support future 44-pin PLCC hosted symbolic assembler. It supports all microcon- microcontrollers with a LCD Module. All the neces- troller series including the PIC12C5XX, PIC14000, sary hardware and software is included to run the PIC16C5X, PIC16CXXX, and PIC17CXX families. basic demonstration programs. The user can pro- gram the sample microcontrollers provided with MPASM offers full featured Macro capabilities, condi- the PICDEM-3 board, on a PRO MATE II program- tional assembly, and several source and listing formats. mer or PICSTART Plus with an adapter socket, and It generates various object code formats to support easily test firmware. The PICMASTER emulator may Microchip's development tools as well as third party also be used with the PICDEM-3 board to test firm- programmers. ware. Additional prototype area has been provided to MPASM allows full symbolic debugging from the user for adding hardware and connecting it to the PICMASTER, Microchip’s Universal Emulator microcontroller socket(s). Some of the features include System. DS30272A-page 86 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X MPASM has the following features to assist in develop- 10.14 MP-DriveWay(cid:228) – Application Code ing software for specific use applications. Generator • Provides translation of Assembler source code to MP-DriveWay is an easy-to-use Windows-based Appli- object code for all Microchip microcontrollers. cation Code Generator. With MP-DriveWay you can • Macro assembly capability. visually configure all the peripherals in a PIC16/17 • Produces all the files (Object, Listing, Symbol, device and, with a click of the mouse, generate all the and special) required for symbolic debug with initialization and many functional code modules in C Microchip’s emulator systems. language. The output is fully compatible with Micro- • Supports Hex (default), Decimal and Octal source chip’s MPLAB-C C compiler. The code produced is and listing formats. highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain MPASM provides a rich directive language to support your code through subsequent code generation. programming of the PIC16/17. Directives are helpful in making the development of your assemble source code 10.15 SEEVAL(cid:226) Evaluation and shorter and more maintainable. Programming System 10.11 Software Simulator (MPLAB-SIM) The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit The MPLAB-SIM Software Simulator allows code includes everything necessary to read, write, erase or development in a PC host environment. It allows the program special features of any Microchip SEEPROM user to simulate the PIC16/17 series microcontrollers product including Smart Serials(cid:212) and secure serials. on an instruction level. On any given instruction, the The Total Endurance(cid:212) Disk is included to aid in trade- user may examine or modify any of the data areas or off analysis and reliability calculations. The total kit can provide external stimulus to any of the pins. The input/ significantly reduce time-to-market and result in an output radix can be set by the user and the execution optimized system. can be performed in; single step, execute until break, or in a trace mode. 10.16 KEELOQ(cid:226) Evaluation and MPLAB-SIM fully supports symbolic debugging using Programming Tools MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code out- KEELOQ evaluation and programming tools support side of the laboratory environment making it an excel- Microchips HCS Secure Data Products. The HCS eval- lent multi-project software development tool. uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- 10.12 C Compiler (MPLAB-C) gramming interface to program test transmitters. The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC16/17 family of micro- controllers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler pro- vides symbol information that is compatible with the MPLAB IDE memory display. 10.13 Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is avail- able in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for imple- menting more complex systems. Both versions include Microchip’s fuzzyLAB(cid:228) demon- stration board for hands-on experience with fuzzy logic systems implementation. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 87

PIC16C71X TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP 001 000 S2S3S3 4 4 4 CCC HHH XXX CXCXCX 4 4 4 453 229 X 5 e C7 abl97 4 4 4 4 C17 Avail3Q PI X 4 C 7 4 4 4 4 4 4 4 4 1 C PI X X 9 C 4 4 4 4 4 4 4 6 1 C PI X 8 C 6 4 4 4 4 4 4 4 4 4 4 1 C PI X X 7 C 4 4 4 4 4 4 4 4 4 4 6 1 C PI X 6 C 6 4 4 4 4 4 4 4 4 4 4 1 C PI X X X C 4 4 4 4 4 4 4 4 4 6 1 C PI X 5 C 6 4 4 4 4 4 4 4 4 4 4 1 C PI 0 0 0 4 4 4 4 4 4 4 1 C PI X X 5 C 4 4 4 4 4 4 4 2 1 C PI (cid:226)PICMASTER/PICMASTER-CEIn-Circuit Emulator ICEPIC Low-CostIn-Circuit Emulator (cid:228)MPLABIntegratedDevelopmentEnvironment(cid:228)MPLAB CCompiler(cid:226)fuzzyTECH-MPExplorer/EditionFuzzy LogicDev. Tool(cid:228)MP-DriveWayApplicationsCode Generator(cid:228)Total EnduranceSoftware Model(cid:226)PICSTARTLite Ultra Low-CostDev. Kit(cid:226)PICSTARTPlus Low-CostUniversal Dev. Kit(cid:226)PRO MATE IIUniversalProgrammer(cid:226)KEELOQProgrammer(cid:226)SEEVALDesigners Kit PICDEM-1 PICDEM-2 PICDEM-3 (cid:226)KEELOQEvaluation Kit stcudorP rotalumE slooT erawtfoS sremmargorP sdraoB omeD DS30272A-page 88 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 11.0 ELECTRICAL CHARACTERISTICS FOR PIC16C710 AND PIC16C711 Absolute Maximum Ratings † Ambient temperature under bias.................................................................................................................-55 to +125˚C Storage temperature.............................................................................................................................. -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ........................................................................................................... -0.3 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on RA4 with respect to Vss...................................................................................................................0 to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................– 20 mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................– 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by PORTA........................................................................................................................200 mA Maximum current sourced by PORTA...................................................................................................................200 mA Maximum current sunk by PORTB........................................................................................................................200 mA Maximum current sourced by PORTB...................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD - VOH) x IOH} + (cid:229) (VOl x IOL) † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 11-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C710-04 PIC16C710-10 PIC16C710-20 PIC16LC710-04 PIC16C710/JW OSC PIC16C711-04 PIC16C711-10 PIC16C711-20 PIC16LC711-04 PIC16C711/JW VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA typ. at 3.0V IDD: 5 mA max. at 5.5V RC IPD: 21 m A max. at 4V IPD: 1.5 m A typ. at 4V IPD: 1.5 m A typ. at 4V IPD: 5.0 m A typ. at 3V IPD: 21 m A max. at 4V Freq:4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq:4 MHz max. VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA typ. at 3.0V IDD: 5 mA max. at 5.5V XT IPD: 21 m A max. at 4V IPD: 1.5 m A typ. at 4V IPD: 1.5 m A typ. at 4V IPD: 5.0 m A typ. at 3V IPD: 21 m A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD:4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at IDD: 30 mA max. at IDD: 30 mA max. at IDD: 30 mA max. at Not recommended for HS 5.5V 5.5V 5.5V 5.5V use in HS mode IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq:20 MHz max. Freq: 10 MHz max. VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 52.5 m A typ. at IDD: 48 m A max. at IDD: 48 m A max. at 32 kHz, 4.0V Not recommended for Not recommended for 32 kHz, 3.0V 32 kHz, 3.0V LP IPD: 0.9 m A typ. at 4.0V use in LP mode use in LP mode IPD: 5.0 m A max. at 3.0V IPD: 5.0 m A max. at Freq: 200 kHz max. Freq: 200 kHz max. 3.0V Freq: 200 kHz max. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 89

PIC16C71X Applicable Devices 710 71 711 715 11.1 DC Characteristics: PIC16C710-04 (Commercial, Industrial, Extended) PIC16C711-04 (Commercial, Industrial, Extended) PIC16C710-10 (Commercial, Industrial, Extended) PIC16C711-10 (Commercial, Industrial, Extended) PIC16C710-20 (Commercial, Industrial, Extended) PIC16C711-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C £ TA £ +70˚C (commercial) DC CHARACTERISTICS -40˚C £ TA £ +85˚C (industrial) -40˚C £ TA £ +125˚C (extended) Param. Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power- on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled 3.7 4.0 4.4 V Extended Range Only D010 Supply Current (Note 2) IDD - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D015 Brown-out Reset Current D IBOR - 300* 500 m A BOR enabled VDD = 5.0V (Note 5) D020 Power-down Current IPD - 10.5 42 m A VDD = 4.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3) - 1.5 21 m A VDD = 4.0V, WDT disabled, -0(cid:176) C to +70(cid:176) C D021A - 1.5 24 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D021B - 1.5 30 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +125(cid:176) C D023 Brown-out Reset Current D IBOR - 300* 500 m A BOR enabled VDD = 5.0V (Note 5) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30272A-page 90 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 11.2 DC Characteristics: PIC16LC710-04 (Commercial, Industrial, Extended) PIC16LC711-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C £ TA £ +70˚C (commercial) DC CHARACTERISTICS -40˚C £ TA £ +85˚C (industrial) -40˚C £ TA £ +125˚C (extended) Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage Commercial/Industrial VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) Extended VDD 3.0 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power- on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled Voltage D010 Supply Current IDD - 2.0 3.8 mA XT, RC osc configuration (Note 2) FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 m A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015 Brown-out Reset D IBOR - 300* 500 m A BOR enabled VDD = 5.0V Current (Note 5) D020 Power-down Current IPD - 7.5 30 m A VDD = 3.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3) - 0.9 5 m A VDD = 3.0V, WDT disabled, 0(cid:176) C to +70(cid:176) C D021A - 0.9 5 m A VDD = 3.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D021B - 0.9 10 m A VDD = 3.0V, WDT disabled, -40(cid:176) C to +125(cid:176) C D023 Brown-out Reset D IBOR - 300* 500 m A BOR enabled VDD = 5.0V Current (Note 5) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 91

PIC16C71X Applicable Devices 710 71 711 715 11.3 DC Characteristics: PIC16C710-04 (Commercial, Industrial, Extended) PIC16C711-04 (Commercial, Industrial, Extended) PIC16C710-10 (Commercial, Industrial, Extended) PIC16C711-10 (Commercial, Industrial, Extended) PIC16C710-20 (Commercial, Industrial, Extended) PIC16C711-20 (Commercial, Industrial, Extended) PIC16LC710-04 (Commercial, Industrial, Extended) PIC16LC711-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C £ TA £ +70˚C (commercial) -40˚C £ TA £ +85˚C (industrial) DC CHARACTERISTICS -40˚C £ TA £ +125˚C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5 £ VDD £ 5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 VSS - 0.2VDD V (in RC mode) D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5 £ VDD £ 5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR, RB0/INT 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - – 1 m A Vss £ VPIN £ VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - – 5 m A Vss £ VPIN £ VDD D063 OSC1 - - – 5 m A Vss £ VPIN £ VDD, XT, HS and LP osc configuration * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30272A-page 92 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C £ TA £ +70˚C (commercial) -40˚C £ TA £ +85˚C (industrial) DC CHARACTERISTICS -40˚C £ TA £ +125˚C (extended) Operating voltage VDD range as described in DC spec Section 11.1 and Section 11.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D130* Open-Drain High Voltage VOD - - 14 V RA4 pin Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 93

PIC16C71X Applicable Devices 710 71 711 715 11.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 11-1: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464W CL = 50 pF for all pins except OSC2 15 pF for OSC2 output DS30272A-page 94 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 11.5 Timing Diagrams and Specifications FIGURE 11-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — m s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — m s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High 50 — — ns XT oscillator TosH or Low Time 2.5 — — m s LP oscillator 10 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise — — 25 ns XT oscillator TosF or Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC16C710/711. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 95

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 11-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure 11-1 for load conditions. TABLE 11-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1› to CLKOUTfl — 15 30 ns Note 1 11* TosH2ckH OSC1› to CLKOUT› — 15 30 ns Note 1 12* TckR CLKOUT rise time — 5 15 ns Note 1 13* TckF CLKOUT fall time — 5 15 ns Note 1 14* TckL2ioV CLKOUT fl to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT › 0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT › 0 — — ns Note 1 17* TosH2ioV OSC1› (Q1 cycle) to — — 80 - 100 ns Port out valid 18* TosH2ioI OSC1› (Q2 cycle) to TBD — — ns Port input invalid (I/O in hold time) 19* TioV2osH Port input valid to OSC1› (I/O in setup time) TBD — — ns 20* TioR Port output rise time PIC16C710/711 — 10 25 ns PIC16LC710/711 — — 60 ns 21* TioF Port output fall time PIC16C710/711 — 10 25 ns PIC16LC710/711 — — 60 ns 22††* Tinp INT pin high or low time 20 — — ns 23††* Trbp RB7:RB4 change INT high or low time 20 — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30272A-page 96 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 11-1 for load conditions. FIGURE 11-5: BROWN-OUT RESET TIMING VDD BVDD 35 TABLE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 1 — — m s VDD = 5V, -40˚C to +125˚C 31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5V, -40˚C to +125˚C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33 Tpwrt Power up Timer Period 28* 72 132* ms VDD = 5V, -40˚C to +125˚C 34 TIOZ I/O Hi-impedance from MCLR Low — — 1.1 m s or Watchdog Timer Reset 35 TBOR Brown-out Reset pulse width 100 — — m s 3.8V £ VDD £ 4.2V * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 97

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 11-6: TIMER0 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 TMR0 Note: Refer to Figure 11-1 for load conditions. TABLE 11-5: TIMER0 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns Must also meet parameter 42 With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns Must also meet With Prescaler 10* — — ns parameter 42 42 Tt0P T0CKI Period Greater of: — — ns N = prescale value 20 ns or TCY + 40* (2, 4,..., 256) N 48 Tcke2tmrI Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30272A-page 98 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 TABLE 11-6: A/D CONVERTER CHARACTERISTICS: PIC16C710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C710/711-10 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C710/711-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8-bits bit VREF = VDD, VSS £ AIN £ VREF A02 EABS Absolute error — — < – 1 LSb VREF = VDD, VSS £ AIN £ VREF A03 EIL Integral linearity error — — < – 1 LSb VREF = VDD, VSS £ AIN £ VREF A04 EDL Differential linearity error — — < – 1 LSb VREF = VDD, VSS £ AIN £ VREF A05 EFS Full scale error — — < – 1 LSb VREF = VDD, VSS £ AIN £ VREF A06 EOFF Offset error — — < – 1 LSb VREF = VDD, VSS £ AIN £ VREF A10 — Monotonicity — guaranteed — — VSS £ VAIN £ VREF A20 VREF Reference voltage 2.5V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 kW analog voltage source A40 IAD A/D conversion current (VDD) — 180 — m A Average current consumption when A/D is on. (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 m A During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD see Section 7.1. — — 10 m A During A/D Conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 99

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 11-7: A/D CONVERSION TIMING BSF ADCON0, GO 1 Tcy (TOSC/2) (1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 11-7: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period PIC16C710/711 1.6 — — m s TOSC based, VREF ‡ 3.0V PIC16LC710/711 2.0 — — m s TOSC based, VREF full range PIC16C710/711 2.0* 4.0 6.0 m s A/D RC mode PIC16LC710/711 3.0* 6.0 9.0 m s A/D RC mode 131 TCNV Conversion time — 9.5 — TAD (not including S/H time). (Note 1) 132 TACQ Acquisition time Note 2 20 — m s 5* — — m s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 19.5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to AD clock start — TOSC/2§ — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert fi sample time 1.5§ — — TAD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 7.1 for min conditions. DS30272A-page 100 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 12.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C710 AND PIC16C711 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25(cid:176) C, while 'max' or 'min' represents (mean +3s ) and (mean -3s ) respectively where s is standard deviation. FIGURE 12-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE) 35 30 25 20 A) n (D P I 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 12-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE) 10.000 85(cid:176) C 70(cid:176) C 1.000 A) 25(cid:176) C 0.100 m(D P I 0(cid:176) C -40(cid:176) C 0.010 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 101

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-3: TYPICAL IPD vs. VDD @ 25(cid:176) C FIGURE 12-5: TYPICAL RC OSCILLATOR (WDT ENABLED, RC MODE) FREQUENCY vs. VDD Cext = 22 pF, T = 25(cid:176)C 6.0 25 5.5 5.0 20 4.5 R = 5k 4.0 A) 15 MHz) 3.5 mI(PD 10 osc( 3.0 R = 10k F 2.5 2.0 5 1.5 1.0 0 R = 100k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 VDD(Volts) 0.02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 12-4: MAXIMUM IPD vs. VDD (WDT Shaded area is beyond recommended range. ENABLED, RC MODE) FIGURE 12-6: TYPICAL RC OSCILLATOR 35 FREQUENCY vs. VDD -40(cid:176)C 30 0(cid:176)C 2.4 Cext = 100 pF, T = 25(cid:176)C 25 2.2 R = 3.3k 2.0 A) 20 1.8 m(D 70(cid:176)C 1.6 IP 15 z) R = 5k H 1.4 M 10 85(cid:176)C sc( 1.2 o F 1.0 R = 10k 5 0.8 0.6 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.4 R = 100k 0.2 VDD(Volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 12-7: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 300 pF, T = 25(cid:176)C 1000 900 800 R = 3.3k 700 z) kH 600 c( R = 5k s 500 o F 400 R = 10k 300 200 100 R = 100k 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) DS30272A-page 102 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-8: TYPICAL IPD vs. VDD BROWN- FIGURE 12-10:TYPICAL IPD vs. TIMER1 OUT DETECT ENABLED (RC ENABLED (32 kHz, RC0/RC1 = MODE) 33 pF/33 pF, RC MODE) 1400 1200 30 1000 25 A) 800 Device NOT in m(D Brown-out Reset 20 IP 600 A) 400 BDreovwicne-o iunt m(PD15 200 Reset I10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5 VDD(Volts) 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 The shaded region represents the built-in hysteresis of the VDD(Volts) brown-out reset circuitry. FIGURE 12-9: MAXIMUM IPD vs. VDD BROWN-OUT DETECT FIGURE 12-11:MAXIMUM IPD vs. TIMER1 ENABLED ENABLED (85(cid:176) C TO -40(cid:176) C, RC MODE) (32 kHz, RC0/RC1 = 33 pF/33 pF, 85(cid:176) C TO -40(cid:176) C, RC MODE) 1600 1400 1200 45 1000 40 A) Device NOT in 35 m(PD 800 Brown-out Reset 30 I 600 Device in Brown-out A)25 400 Reset m(D20 P 200 I15 4.3 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5 VDD(Volts) 0 The shaded region represents the built-in hysteresis of the 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 brown-out reset circuitry. VDD(Volts) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 103

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-12:TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25(cid:176) C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V 1400 4.0V A) 1200 3.5V m(D ID 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Frequency(MHz) Shaded area is beyond recommended range FIGURE 12-13:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40(cid:176) C TO 85(cid:176) C) 2000 6.0V 1800 5.5V 5.0V 1600 4.5V 1400 4.0V A) 1200 3.5V m(D ID 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Frequency(MHz) Shaded area is beyond recommended range DS30272A-page 104 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-14:TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25(cid:176) C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 3.5V A) 3.0V m(D 800 D I 2.5V 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is Frequency(kHz) beyond recommended range FIGURE 12-15:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40(cid:176) C TO 85(cid:176) C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 3.5V A) 3.0V m(D 800 D I 2.5V 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is Frequency(kHz) beyond recommended range (cid:211) 1997 Microchip Technology Inc. DS30272A-page 105

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-16:TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25(cid:176) C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V 3.0V A) 600 m(D 2.5V D I 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 12-17:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40(cid:176) C TO 85(cid:176) C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V 3.0V A) 600 m(D 2.5V D I 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) DS30272A-page 106 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-18:TYPICAL IDD vs. CAPACITANCE @ 500 kHz FIGURE 12-19:TRANSCONDUCTANCE(gm) (RC MODE) OF HS OSCILLATOR vs. VDD 600 4.0 Max -40(cid:176)C 5.0V 3.5 500 3.0 4.0V 400 A) 3.0V V) 2.5 Typ 25(cid:176)C m(D 300 mA/ 2.0 ID m( g 1.5 Min 85(cid:176)C 200 1.0 100 0.5 0 0.0 20 pF 100 pF 300 pF 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Capacitance(pF) Shaded area is VDD(Volts) beyond recommended range TABLE 12-1: RC OSCILLATOR FIGURE 12-20:TRANSCONDUCTANCE(gm) FREQUENCIES OF LP OSCILLATOR vs. VDD Average Cext Rext 110 Fosc @ 5V, 25(cid:176) C 100 Max -40(cid:176)C 90 22 pF 5k 4.12 MHz – 1.4% 80 10k 2.35 MHz – 1.4% 70 100k 268 kHz – 1.1% A/V) 60 Typ 25(cid:176)C 100 pF 3.3k 1.80 MHz – 1.0% mm( 50 g 40 5k 1.27 MHz – 1.0% 30 10k 688 kHz – 1.2% 20 Min 85(cid:176)C 100k 77.2 kHz – 1.0% 10 0 300 pF 3.3k 707 kHz – 1.4% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 5k 501 kHz – 1.2% Shaded areas are VDD(Volts) beyond recommended range 10k 269 kHz – 1.6% 100k 28.3 kHz – 1.1% FIGURE 12-21:TRANSCONDUCTANCE(gm) OF XT OSCILLATOR vs. VDD The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is – 3 standard deviation from 1000 average value for VDD = 5V. 900 Max -40(cid:176)C 800 700 V) 600 Typ 25(cid:176)C A/ 500 mm( 400 g 300 Min 85(cid:176)C 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Shaded areas are VDD(Volts) beyond recommended range (cid:211) 1997 Microchip Technology Inc. DS30272A-page 107

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-22:TYPICAL XTAL STARTUP FIGURE 12-24:TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25(cid:176) C) TIME vs. VDD (XT MODE, 25(cid:176) C) 3.5 70 3.0 60 2.5 s) 50 d con 2.0 ms) 40 me(Se 1.5 32 kHz, 33 pF/33 pF Time( 30 200 kHz, 68 pF/68 pF up Ti artup 20 200 kHz, 47 pF/47 pF art 1.0 St 1 MHz, 15 pF/15 pF St 10 4 MHz, 15 pF/15 pF 0.5 200 kHz, 15 pF/15 pF 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 VDD(Volts) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 12-23:TYPICAL XTAL STARTUP TABLE 12-2: CAPACITOR SELECTION TIME vs. VDD (HS MODE, FOR CRYSTAL 25(cid:176) C) OSCILLATORS 7 Crystal Cap. Range Cap. Range Osc Type Freq C1 C2 6 LP 32 kHz 33 pF 33 pF ms) 5 20 MHz, 33 pF/33 pF 200 kHz 15 pF 15 pF me( XT 200 kHz 47-68 pF 47-68 pF p Ti 4 1 MHz 15 pF 15 pF u 8 MHz, 33 pF/33 pF art 3 4 MHz 15 pF 15 pF St 20 MHz, 15 pF/15 pF HS 4 MHz 15 pF 15 pF 2 8 MHz, 15 pF/15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF 1 4.0 4.5 5.0 5.5 6.0 VDD(Volts) Crystals Used 32 kHz Epson C-001R32.768K-A – 20 PPM 200 kHz STD XTL 200.000KHz – 20 PPM 1 MHz ECS ECS-10-13-1 – 50 PPM 4 MHz ECS ECS-40-20-1 – 50 PPM 8 MHz EPSON CA-301 8.000M-C – 30 PPM 20 MHz EPSON CA-301 20.000M-C – 30 PPM DS30272A-page 108 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-25:TYPICAL IDD vs. FREQUENCY FIGURE 12-27:TYPICAL IDD vs. FREQUENCY (LP MODE, 25(cid:176) C) (XT MODE, 25(cid:176) C) 1800 1600 6.0V 120 1400 5.5V 100 5.0V 1200 80 4.5V A) 1000 4.0V 60 m(DD 6.0V 800 3.5V I40 55..50VV A) 3.0V 4.5V m(D600 20 43..05VV ID 2.5V 3.0V 400 2.5V 0 0 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 12-26:MAXIMUM IDD vs. FIGURE 12-28:MAXIMUM IDD vs. FREQUENCY FREQUENCY (LP MODE, 85(cid:176) C TO -40(cid:176) C) (XT MODE, -40(cid:176) C TO 85(cid:176) C) 1800 6.0V 140 1600 5.5V 120 1400 5.0V 100 1200 4.5V 80 1000 4.0V A) m(D60 6.0V 800 3.5V ID 5.5V A) 3.0V 5.0V 40 4.5V m(DD600 2.5V 4.0V I 3.5V 20 400 3.0V 2.5V 0 200 0 50 100 150 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 109

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 12-29:TYPICAL IDD vs. FREQUENCY FIGURE 12-30:MAXIMUM IDD vs. (HS MODE, 25(cid:176) C) FREQUENCY (HS MODE, -40(cid:176) C TO 85(cid:176) C) 7.0 7.0 6.0 6.0 5.0 5.0 A)4.0 (mDD3.0 mA)4.0 I (DD3.0 2.0 6.0V I 5.5V 5.0V 2.0 6.0V 1.0 4.5V 5.5V 4.0V 5.0V 1.0 4.5V 0.0 4.0V 1 2 4 6 8 10 12 14 16 18 20 0.0 Frequency(MHz) 1 2 4 6 8 10 12 14 16 18 20 Frequency(MHz) DS30272A-page 110 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 13.0 ELECTRICAL CHARACTERISTICS FOR PIC16C715 Absolute Maximum Ratings † Ambient temperature under bias.................................................................................................................-55 to +125˚C Storage temperature.............................................................................................................................. -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD and MCLR)....................................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on RA4 with respect to Vss...................................................................................................................0 to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................– 20 mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................– 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by PORTA........................................................................................................................200 mA Maximum current sourced by PORTA...................................................................................................................200 mA Maximum current sunk by PORTB........................................................................................................................200 mA Maximum current sourced by PORTB...................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD - VOH) x IOH} + (cid:229) (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 111

D T A P S A 30 B pp I 272 LE lic C A-page 13-1: able D 16 1 e C 12 ANCR vice 7 DO s 1 FS RES R 71 X OSC PIC16C715-04 PIC16C715-10 PIC16C715-20 PIC16LC715-04 PIC16C715/JW QE 0 VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 4.0V to 5.5V UEFE 71 RC IFIDPrDDe::q : 524 1 mM mAHA zm mmaaaxx.x .a .at t5 4.5VV FIIDPrDDe::q : 412 ..M57 mmHAzA m ttyypap.x . a.att 45V.5V IIFDPrDDe::q : 124.. 57M mmHAzA mttyypap.x . a.att 45V.5V FIIDPrDDe::q : 402 ..M90 mmHAzA m ttyypap.x . a.att 33V.0V IFIDPrDDe::q : 524 1 mM mAHA zm mmaaaxx.x .a .at t5 4.5VV NCIERENC 711 S 7 VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 4.0V to 5.5V OE O 15 XT IIDPDD:: 52 1m mAA m maaxx. .a at t5 4.5VV IIDPDD:: 12..57 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 12..57 mmAA ttyypp. . aatt 45V.5V IIDPDD:: 02..90 mmAA ttyypp. . aatt 33V.0V IIDPDD:: 52 1m mAA m maaxx. .a at t5 4.5VV F OF D Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. PEEV VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V RAIC IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V IDD: 30 mA max. at 5.5V TE HS IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V IPD: 1.5 m A typ. at 4.5V Do not use in HS mode IPD: 1.5 m A typ. at 4.5V ION SP E Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 10 MHz max. (CC VDD: 4.0V to 5.5V VDD: 2.5V to 5.5V VDD: 2.5V to 5.5V OS LP IIDPDD:: 502.9.5 m mAA ty tpy.p a. at 4t 3.02V kHz, 4.0V Do not use in LP mode Do not use in LP mode IIDPDD:: 54.80 mmAA mmaaxx. . aatt 332.0 kVHz, 3.0V IIDPDD:: 458.0 m mAA m maaxx. .a at t3 32.0 kVHz, 3.0V MM FOR E Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. R O The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type CS that ensures the specifications required. IALCIL DLA ET VO (cid:211) ICR 1997 ES) CO M N ic F ro IG c h U ip R T A e c T hn IO olo N g S y In c .

PIC16C71X Applicable Devices 710 71 711 715 13.1 DC Characteristics: PIC16C715-04 (Commercial, Industrial, Extended) PIC16C715-10 (Commercial, Industrial, Extended) PIC16C715-20 (Commercial, Industrial, Extended)) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C £ TA £ +70˚C (commercial) DC CHARACTERISTICS -40˚C £ TA £ +85˚C (industrial) -40˚C £ TA £ +125˚C (extended) Param. Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 5.5 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Device in SLEEP mode Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power- on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled D010 Supply Current (Note 2) IDD - 2.7 5 mA XT, RC osc configuration (PIC16C715-04) FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 13.5 30 mA HS osc configuration (PIC16C715-20) FOSC = 20 MHz, VDD = 5.5V D015 Brown-out Reset Current D IBOR - 300* 500 m A BOR enabled VDD = 5.0V (Note 5) D020 Power-down Current IPD - 10.5 42 m A VDD = 4.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3) - 1.5 21 m A VDD = 4.0V, WDT disabled, -0(cid:176) C to +70(cid:176) C D021A - 1.5 24 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D021B - 1.5 30 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +125(cid:176) C D023 Brown-out Reset Current D IBOR - 300* 500 m A BOR enabled VDD = 5.0V (Note 5) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 113

PIC16C71X Applicable Devices 710 71 711 715 13.2 DC Characteristics: PIC16LC715-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature 0˚C £ TA £ +70˚C (commercial) -40˚C £ TA £ +85˚C (industrial) Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 2.5 - 5.5 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Device in SLEEP mode Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to SVDD 0.05 - - V/ms See section on Power-on Reset for details ensure internal Power-on Reset signal D005 Brown-out Reset BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled Voltage D010 Supply Current IDD - 2.0 3.8 mA XT, RC osc configuration (Note 2) FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 m A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015 Brown-out Reset D IBOR - 300* 500 m A BOR enabled VDD = 5.0V Current (Note 5) D020 Power-down Current IPD - 7.5 30 m A VDD = 3.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3) - 0.9 5 m A VDD = 3.0V, WDT disabled, 0(cid:176) C to +70(cid:176) C D021A - 0.9 5 m A VDD = 3.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C D023 Brown-out Reset D IBOR - 300* 500 m A BOR enabled VDD = 5.0V Current (Note 5) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: The D current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30272A-page 114 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 13.3 DC Characteristics: PIC16C715-04 (Commercial, Industrial, Extended) PIC16C715-10 (Commercial, Industrial, Extended) PIC16C715-20 (Commercial, Industrial, Extended) PIC16LC715-04 (Commercial, Industrial)) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C £ TA £ +70˚C (commercial) -40˚C £ TA £ +85˚C (industrial) DC CHARACTERISTICS -40˚C £ TA £ +125˚C (extended) Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.5V V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, RA4/T0CKI,OSC1 VSS - 0.2VDD V (in RC mode) D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5 £ VDD £ 5.5V D040A 0.8VDD - VDD V For VDD > 5.5V or VDD < 4.5V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR, RA4/T0CKI RB0/INT 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - – 1 m A Vss £ VPIN £ VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - – 5 m A Vss £ VPIN £ VDD D063 OSC1 - - – 5 m A Vss £ VPIN £ VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 115

PIC16C71X Applicable Devices 710 71 711 715 Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C £ TA £ +70˚C (commercial) -40˚C £ TA £ +85˚C (industrial) DC CHARACTERISTICS -40˚C £ TA £ +125˚C (extended) Operating voltage VDD range as described in DC spec Section 13.1 and Section 13.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D092A VDD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40(cid:176) C to +125(cid:176) C Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C7X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. DS30272A-page 116 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 13.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 13-1: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464W CL = 50 pF for all pins except OSC2 15 pF for OSC2 output (cid:211) 1997 Microchip Technology Inc. DS30272A-page 117

PIC16C71X Applicable Devices 710 71 711 715 13.5 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 13-2: CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fos External CLKIN Frequency DC — 4 MHz XT osc mode (Note 1) DC — 4 MHz HS osc mode (PIC16C715-04) DC — 20 MHz HS osc mode (PIC16C715-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 4 MHz HS osc mode (PIC16C715-04) 4 — 10 MHz HS osc mode (PIC16C715-10) 4 — 20 MHz HS osc mode (PIC16C715-20) 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT osc mode (Note 1) 250 — — ns HS osc mode (PIC16C715-04) 100 — — ns HS osc mode (PIC16C715-10) 50 — — ns HS osc mode (PIC16C715-20) 5 — — m s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (PIC16C715-04) 100 — 250 ns HS osc mode (PIC16C715-10) 50 — 250 ns HS osc mode (PIC16C715-20) 5 — — m s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High 50 — — ns XT oscillator TosH or Low Time 2.5 — — m s LP oscillator 10 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise — — 25 ns XT oscillator TosF or Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC16C715. DS30272A-page 118 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 13-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure 13-1 for load conditions. TABLE 13-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1› to CLKOUTfl — 15 30 ns Note 1 11* TosH2ckH OSC1› to CLKOUT› — 15 30 ns Note 1 12* TckR CLKOUT rise time — 5 15 ns Note 1 13* TckF CLKOUT fall time — 5 15 ns Note 1 14* TckL2ioV CLKOUT fl to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT › 0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT › 0 — — ns Note 1 17* TosH2ioV OSC1› (Q1 cycle) to — — 80 - 100 ns Port out valid 18* TosH2ioI OSC1› (Q2 cycle) to TBD — — ns Port input invalid (I/O in hold time) 19* TioV2osH Port input valid to OSC1› (I/O in setup time) TBD — — ns 20* TioR Port output rise time PIC16C715 — 10 25 ns PIC16LC715 — — 60 ns 21* TioF Port output fall time PIC16C715 — 10 25 ns PIC16LC715 — — 60 ns 22††* Tinp INT pin high or low time 20 — — ns 23††* Trbp RB7:RB4 change INT high or low time 20 — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 119

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Parity Error Reset 36 Watchdog Timer RESET 34 31 34 I/O Pins FIGURE 13-5: BROWN-OUT RESET TIMING VDD BVDD 35 TABLE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — m s VDD = 5V, -40˚C to +125˚C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +125˚C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 m s or Watchdog Timer Reset 35 TBOR Brown-out Reset pulse width 100 — — m s VDD £ BVDD (D005) 36 TPER Parity Error Reset — TBD — m s * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30272A-page 120 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 13-6: TIMER0 CLOCK TIMINGS RA4/T0CKI 40 41 42 TMR0 Note: Refer to Figure 13-1 for load conditions. TABLE 13-5: TIMER0 CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns With Prescaler 10* — — ns 42 Tt0P T0CKI Period Greater of: — — ns N = prescale value 20m s or TCY + 40* (1, 2, 4,..., 256) N 48 Tcke2tmrI Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 121

PIC16C71X Applicable Devices 710 71 711 715 TABLE 13-6: A/D CONVERTER CHARACTERISTICS: PIC16C715-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C715-10 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C715-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) Parameter Sym Characteristic Min Typ† Max Units Conditions No. NR Resolution — — 8-bits — VREF = VDD, VSS £ AIN £ VREF NINT Integral error — — less than — VREF = VDD, VSS £ AIN £ VREF – 1 LSb NDIF Differential error — — less than — VREF = VDD, VSS £ AIN £ VREF – 1 LSb NFS Full scale error — — less than — VREF = VDD, VSS £ AIN £ VREF – 1 LSb NOFF Offset error — — less than — VREF = VDD, VSS £ AIN £ VREF – 1 LSb — Monotonicity — guaranteed — — VSS £ AIN £ VREF VREF Reference voltage 2.5V — VDD + 0.3 V VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V ZAIN Recommended — — 10.0 kW impedance of analog voltage source IAD A/D conversion cur- — 180 — m A Average current consumption when rent (VDD) A/D is on. (Note 1) IREF VREF input current — — 1 mA During sampling (Note 2) 10 m A All other times * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. DS30272A-page 122 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 TABLE 13-7: A/D CONVERTER CHARACTERISTICS: PIC16LC715-04 (COMMERCIAL, INDUSTRIAL) Parameter Sym Characteristic Min Typ† Max Units Conditions No. NR Resolution — — 8-bits — VREF = VDD, VSS £ AIN £ VREF NINT Integral error — — less than — VREF = VDD, VSS £ AIN £ VREF – 1 LSb NDIF Differential error — — less than — VREF = VDD, VSS £ AIN £ VREF – 1 LSb NFS Full scale error — — less than — VREF = VDD, VSS £ AIN £ VREF – 1 LSb NOFF Offset error — — less than — VREF = VDD, VSS £ AIN £ VREF – 1 LSb — Monotonicity — guaranteed — — VSS £ AIN £ VREF VREF Reference voltage 2.5V — VDD + 0.3 V VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V ZAIN Recommended — — 10.0 kW impedance of ana- log voltage source IAD A/D conversion cur- — 90 — m A Average current consumption when rent (VDD) A/D is on. (Note 1) IREF VREF input current — — 1 mA During sampling (Note 2) 10 m A All other times * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 123

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 13-7: A/D CONVERSION TIMING BSF ADCON0, GO 1 Tcy (TOSC/2) (1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 13-8: A/D CONVERSION REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period 1.6 — m s VREF ‡ 3.0V 2.0 — m s VREF full range 130 TAD A/D Internal RC ADCS1:ADCS0 = 11 Oscillator source (RC oscillator source) 3.0 6.0 9.0 m s PIC16LC715, VDD = 3.0V 2.0 4.0 6.0 m s PIC16C715 131 TCNV Conversion time — 9.5TAD — — (not including S/H time). Note 1 132 TACQ Acquisition time Note 2 20 — m s * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. DS30272A-page 124 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 14.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C715 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25(cid:176) C, while 'max' or 'min' represents (mean +3s ) and (mean -3s ) respectively where s is standard deviation. FIGURE 14-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE) 35 30 25 20 A) n (D P I 15 10 Shaded area is beyond 5 recommended range. 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 14-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE) 10.000 85(cid:176) C 70(cid:176) C 1.000 A) 25(cid:176) C 0.100 m(D P I 0(cid:176) C -40(cid:176) C 0.010 Shaded area is beyond recommended range. 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 125

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-3: TYPICAL IPD vs. VDD @ 25(cid:176) C FIGURE 14-5: TYPICAL RC OSCILLATOR (WDT ENABLED, RC MODE) FREQUENCY vs. VDD Cext = 22 pF, T = 25(cid:176)C 6.0 25 5.5 5.0 20 4.5 R = 5k 4.0 mI(A)PD 1150 osc(MHz) 33..50 R = 10k F 2.5 2.0 5 1.5 1.0 0 R = 100k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 VDD(Volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Shaded area is beyond recommended range. VDD(Volts) FIGURE 14-4: MAXIMUM IPD vs. VDD (WDT Shaded area is beyond recommended range. ENABLED, RC MODE) FIGURE 14-6: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 35 -40(cid:176)C Cext = 100 pF, T = 25(cid:176)C 2.4 30 0(cid:176)C 2.2 R = 3.3k 25 2.0 1.8 A) 20 1.6 m(PD 70(cid:176)C Hz) 1.4 R = 5k I 15 M c( 1.2 10 85(cid:176)C Fos 1.0 R = 10k 0.8 5 0.6 0 0.4 R = 100k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.2 VDD(Volts) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Shaded area is beyond recommended range. VDD(Volts) Shaded area is beyond recommended range. FIGURE 14-7: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 300 pF, T = 25(cid:176)C 1000 900 800 R = 3.3k 700 z) kH 600 c( R = 5k s 500 o F 400 R = 10k 300 200 100 R = 100k 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) Shaded area is beyond recommended range. DS30272A-page 126 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-8: TYPICAL IPD vs. VDD BROWN- FIGURE 14-10:TYPICAL IPD vs. TIMER1 OUT DETECT ENABLED (RC ENABLED (32 kHz, RC0/RC1 = MODE) 33 pF/33 pF, RC MODE) 1400 1200 30 1000 25 A) 800 Device NOT in m(D Brown-out Reset 20 IP 600 A) 400 BDreovwicne-o iunt m(PD15 I 200 Reset 10 0 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 This shaded region represents the built-in hysteresis of VDD(Volts) the brown-out reset circuitry. Shaded area is beyond recommended range. Shaded area is beyond recommended range. FIGURE 14-11:MAXIMUM IPD vs. TIMER1 FIGURE 14-9: MAXIMUM IPD vs. VDD ENABLED BROWN-OUT DETECT (32 kHz, RC0/RC1 = 33 pF/33 ENABLED (85(cid:176) C TO -40(cid:176) C, RC MODE) pF, 85(cid:176) C TO -40(cid:176) C, RC MODE) 1600 45 1400 40 1200 35 1000 30 A) Device NOT in m(D 800 Brown-out Reset A)25 IP 600 Device in m(PD20 Brown-out I15 400 Reset 10 200 5 4.3 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) VDD(Volts) This shaded region represents the built-in hysteresis of Shaded area is beyond recommended range. the brown-out reset circuitry. Shaded area is beyond recommended range. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 127

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-12:TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25(cid:176) C) 2000 1800 5.5V 5.0V 1600 4.5V 1400 4.0V A) 1200 3.5V m(D ID 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Frequency(MHz) Shaded area is beyond recommended range FIGURE 14-13:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40(cid:176) C TO 85(cid:176) C) 2000 1800 5.5V 5.0V 1600 4.5V 1400 4.0V A) 1200 3.5V m(D ID 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Frequency(MHz) Shaded area is beyond recommended range DS30272A-page 128 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-14:TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25(cid:176) C) 1600 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 3.5V A) 3.0V m(D 800 D I 2.5V 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is Frequency(kHz) beyond recommended range FIGURE 14-15:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40(cid:176) C TO 85(cid:176) C) 1600 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 3.5V A) 3.0V m(D 800 D I 2.5V 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is Frequency(kHz) beyond recommended range (cid:211) 1997 Microchip Technology Inc. DS30272A-page 129

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-16:TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25(cid:176) C) 1200 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V 3.0V A) 600 m(D 2.5V D I 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 14-17:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40(cid:176) C TO 85(cid:176) C) 1200 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V 3.0V A) 600 m(D 2.5V D I 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) DS30272A-page 130 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-18:TYPICAL IDD vs. CAPACITANCE @ 500 kHz FIGURE 14-19:TRANSCONDUCTANCE(gm) (RC MODE) OF HS OSCILLATOR vs. VDD 600 4.0 Max -40(cid:176)C 5.0V 3.5 500 3.0 4.0V 400 A) 3.0V V) 2.5 Typ 25(cid:176)C m(D 300 mA/ 2.0 ID m( g 1.5 Min 85(cid:176)C 200 1.0 100 0.5 0 0.0 20 pF 100 pF 300 pF 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Capacitance(pF) VDD(Volts) Shaded area is beyond recommended range. TABLE 14-1: RC OSCILLATOR FREQUENCIES FIGURE 14-20:TRANSCONDUCTANCE(gm) OF LP OSCILLATOR vs. VDD Average Cext Rext 110 Fosc @ 5V, 25(cid:176) C 100 Max -40(cid:176)C 22 pF 5k 4.12 MHz – 1.4% 90 10k 2.35 MHz – 1.4% 80 70 100k 268 kHz – 1.1% V) A/ 60 Typ 25(cid:176)C 100 pF 3.3k 1.80 MHz – 1.0% mm( 50 5k 1.27 MHz – 1.0% g 40 10k 688 kHz – 1.2% 30 100k 77.2 kHz – 1.0% 20 Min 85(cid:176)C 10 300 pF 3.3k 707 kHz – 1.4% 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 5k 501 kHz – 1.2% VDD(Volts) 10k 269 kHz – 1.6% Shaded area is beyond recommended range. 100k 28.3 kHz – 1.1% FIGURE 14-21:TRANSCONDUCTANCE(gm) The percentage variation indicated here is part to part variation due to normal process distribution. The OF XT OSCILLATOR vs. VDD variation indicated is – 3 standard deviation from average value for VDD = 5V. 1000 900 Max -40(cid:176)C 800 700 V) 600 Typ 25(cid:176)C A/ 500 mm( g 400 300 Min 85(cid:176)C 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD(Volts) Shaded area is beyond recommended range. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 131

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-22:TYPICAL XTAL STARTUP FIGURE 14-24:TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25(cid:176) C) TIME vs. VDD (XT MODE, 25(cid:176) C) 3.5 70 3.0 60 2.5 s) 50 d con 2.0 ms) 40 me(Se 1.5 32 kHz, 33 pF/33 pF Time( 30 200 kHz, 68 pF/68 pF up Ti artup 20 200 kHz, 47 pF/47 pF art 1.0 St 1 MHz, 15 pF/15 pF St 10 4 MHz, 15 pF/15 pF 0.5 200 kHz, 15 pF/15 pF 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 VDD(Volts) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Shaded area is beyond recommended range. VDD(Volts) Shaded area is beyond recommended range. TABLE 14-2: CAPACITOR SELECTION FOR CRYSTAL FIGURE 14-23:TYPICAL XTAL STARTUP OSCILLATORS TIME vs. VDD (HS MODE, 25(cid:176) C) Crystal Cap. Range Cap. Range Osc Type Freq C1 C2 7 LP 32 kHz 33 pF 33 pF 6 200 kHz 15 pF 15 pF s) XT 200 kHz 47-68 pF 47-68 pF m 5 20 MHz, 33 pF/33 pF e( 1 MHz 15 pF 15 pF m 4 MHz 15 pF 15 pF Ti 4 p HS 4 MHz 15 pF 15 pF u 8 MHz, 33 pF/33 pF art 3 8 MHz 15-33 pF 15-33 pF St 20 MHz, 15 pF/15 pF 20 MHz 15-33 pF 15-33 pF 2 8 MHz, 15 pF/15 pF 1 Crystals 4.0 4.5 5.0 5.5 6.0 Used VDD(Volts) 32 kHz Epson C-001R32.768K-A – 20 PPM Shaded area is beyond recommended range. 200 kHz STD XTL 200.000KHz – 20 PPM 1 MHz ECS ECS-10-13-1 – 50 PPM 4 MHz ECS ECS-40-20-1 – 50 PPM 8 MHz EPSON CA-301 8.000M-C – 30 PPM 20 MHz EPSON CA-301 20.000M-C – 30 PPM DS30272A-page 132 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-25:TYPICAL IDD vs. FREQUENCY FIGURE 14-27:TYPICAL IDD vs. FREQUENCY (LP MODE, 25(cid:176) C) (XT MODE, 25(cid:176) C) 1800 1600 120 1400 5.5V 100 5.0V 1200 80 4.5V A) 1000 4.0V 60 m(DD 800 3.5V I40 55..50VV A) 3.0V 4.5V m(D600 20 43..05VV ID 2.5V 3.0V 400 2.5V 0 0 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 14-26:MAXIMUM IDD vs. FIGURE 14-28:MAXIMUM IDD vs. FREQUENCY FREQUENCY (LP MODE, 85(cid:176) C TO -40(cid:176) C) (XT MODE, -40(cid:176) C TO 85(cid:176) C) 1800 140 1600 5.5V 120 1400 5.0V 100 1200 4.5V 80 1000 4.0V A) m(D60 800 3.5V ID 5.5V A) 3.0V 5.0V 40 4.5V m(DD600 2.5V 4.0V I 3.5V 20 400 3.0V 2.5V 0 200 0 50 100 150 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 133

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 14-29:TYPICAL IDD vs. FREQUENCY FIGURE 14-30:MAXIMUM IDD vs. (HS MODE, 25(cid:176) C) FREQUENCY (HS MODE, -40(cid:176) C TO 85(cid:176) C) 7.0 7.0 6.0 6.0 5.0 5.0 A)4.0 (mDD3.0 mA)4.0 I (DD3.0 2.0 I 5.5V 5.0V 2.0 1.0 4.5V 5.5V 4.0V 5.0V 1.0 4.5V 0.0 4.0V 1 2 4 6 8 10 12 14 16 18 20 0.0 Frequency(MHz) 1 2 4 6 8 10 12 14 16 18 20 Frequency(MHz) DS30272A-page 134 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 15.0 ELECTRICAL CHARACTERISTICS FOR PIC16C71 Absolute Maximum Ratings † Ambient temperature under bias.................................................................................................................-55 to +125˚C Storage temperature.............................................................................................................................. -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS .......................................................................................................... -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V Voltage on RA4 with respect to Vss...................................................................................................................0 to +14V Total power dissipation (Note 1)...........................................................................................................................800 mW Maximum current out of VSS pin...........................................................................................................................150 mA Maximum current into VDD pin..............................................................................................................................100 mA Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................– 20 mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................– 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................20 mA Maximum current sunk by PORTA..........................................................................................................................80 mA Maximum current sourced by PORTA.....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB...................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD-VOH) x IOH} + (cid:229) (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100W should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 15-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) OSC PIC16C71-04 PIC16C71-20 PIC16LC71-04 JW Devices VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V IDD: 3.3 mA max. at 5.5V IDD: 1.8 mA typ. at 5.5V IDD: 1.4 mA typ. at 3.0V IDD: 3.3 mA max. at 5.5V RC IPD: 14 m A max. at 4V IPD: 1.0 m A typ. at 4V IPD: 0.6 m A typ. at 3V IPD: 14 m A max. at 4V Freq:4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq:4 MHz max. VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V IDD: 3.3 mA max. at 5.5V IDD: 1.8 mA typ. at 5.5V IDD: 1.4 mA typ. at 3.0V IDD: 3.3 mA max. at 5.5V XT IPD: 14 m A max. at 4V IPD: 1.0 m A typ. at 4V IPD: 0.6 m A typ. at 3V IPD: 14 m A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V Not recommended for use in IDD: 30 mA max. at 5.5V HS IPD: 1.0 m A typ. at 4.5V IPD: 1.0 m A typ. at 4.5V HS mode IPD: 1.0 m A typ. at 4.5V Freq: 4 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. VDD: 4.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V IDD: 15 m A typ. at 32 kHz, IDD: 32 m A max. at 32 kHz, IDD: 32 m A max. at 32 kHz, Not recommended for use LP 4.0V 3.0V 3.0V in LP mode IPD: 0.6 m A typ. at 4.0V IPD: 9 m A max. at 3.0V IPD: 9 m A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recom- mended that the user select the device type that ensures the specifications required. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 135

PIC16C71X Applicable Devices 710 71 711 715 15.1 DC Characteristics: PIC16C71-04 (Commercial, Industrial) PIC16C71-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature 0˚C £ TA £ +70˚C (commercial) -40˚C £ TA £ +85˚C (industrial) Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current (Note 2) IDD - 1.8 3.3 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D020 Power-down Current IPD - 7 28 m A VDD = 4.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3) - 1.0 14 m A VDD = 4.0V, WDT disabled, -0(cid:176) C to +70(cid:176) C D021A - 1.0 16 m A VDD = 4.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. DS30272A-page 136 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 15.2 DC Characteristics: PIC16LC71-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS OOperating temperature 0˚C £ TA £ +70˚C (commercial) -40˚C £ TA £ +85˚C (industrial) Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 3.0 - 6.0 V XT, RC, and LP osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current (Note 2) IDD - 1.4 2.5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 15 32 m A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D020 Power-down Current IPD - 5 20 m A VDD = 3.0V, WDT enabled, -40(cid:176) C to +85(cid:176) C D021 (Note 3) - 0.6 9 m A VDD = 3.0V, WDT disabled, 0(cid:176) C to +70(cid:176) C D021A - 0.6 12 m A VDD = 3.0V, WDT disabled, -40(cid:176) C to +85(cid:176) C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 137

PIC16C71X Applicable Devices 710 71 711 715 15.3 DC Characteristics: PIC16C71-04 (Commercial, Industrial) PIC16C71-20 (Commercial, Industrial) PIC16LC71-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) OOperating temperature 0˚C £ TA £ +70˚C (commercial) DC CHARACTERISTICS -40˚C £ TA £ +85˚C (industrial) Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15V V For entire VDD range D031 with Schmitt Trigger buffer VSS - 0.8V V 4.5 £ VDD £ 5.5V D032 MCLR, OSC1 (in RC mode) VSS - 0.2VDD V D033 OSC1 (in XT, HS and LP) VSS - 0.3VDD V Note1 Input High Voltage I/O ports (Note 4) VIH - D040 with TTL buffer 2.0 - VDD V 4.5 £ VDD £ 5.5V D040A 0.25VDD - VDD For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.85VDD - VDD For entire VDD range D042 MCLR, RB0/INT 0.85VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 †400 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - – 1 m A Vss £ VPIN £ VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - – 5 m A Vss £ VPIN £ VDD D063 OSC1 - - – 5 m A Vss £ VPIN £ VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 - - V IOH = -1.3mA, VDD = 4.5V, -40(cid:176) C to +85(cid:176) C D130* Open-Drain High Voltage VOD - - 14 V RA4 pin † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the PIC16C71 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: PIC16C71 Rev. "Ax" INT pin has a TTL input buffer. PIC16C71 Rev. "Bx" INT pin has a Schmitt Trigger input buffer. DS30272A-page 138 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 Standard Operating Conditions (unless otherwise stated) OOperating temperature 0˚C £ TA £ +70˚C (commercial) DC CHARACTERISTICS -40˚C £ TA £ +85˚C (industrial) Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2. Param Characteristic Sym Min Typ Max Units Conditions No. † Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO 50 pF † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the PIC16C71 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: PIC16C71 Rev. "Ax" INT pin has a TTL input buffer. PIC16C71 Rev. "Bx" INT pin has a Schmitt Trigger input buffer. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 139

PIC16C71X Applicable Devices 710 71 711 715 15.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 15-1: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464W CL = 50 pF for all pins except OSC2/CLKOUT 15 pF for OSC2 output DS30272A-page 140 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 15.5 Timing Diagrams and Specifications FIGURE 15-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 1 — 4 MHz HS osc mode 1 — 20 MHz HS osc mode 1 Tosc External CLKIN Period 250 — — ns XT osc mode (Note 1) 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — m s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 1,000 ns HS osc mode (-04) 50 — 1,000 ns HS osc mode (-20) 5 — — m s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 1.0 TCY DC m s TCY = 4/Fosc 3 TosL, External Clock in (OSC1) High or 50 — — ns XT oscillator TosH Low Time 2.5 — — m s LP oscillator 10 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or 25 — — ns XT oscillator TosF Fall Time 50 — — ns LP oscillator 15 — — ns HS oscillator † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC16C71. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 141

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 15-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 11 10 CLKOUT 13 12 19 18 14 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure 15-1 for load conditions. TABLE 15-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1› to CLKOUTfl — 15 30 ns Note 1 11* TosH2ckH OSC1› to CLKOUT› — 15 30 ns Note 1 12* TckR CLKOUT rise time — 5 15 ns Note 1 13* TckF CLKOUT fall time — 5 15 ns Note 1 14* TckL2ioV CLKOUT fl to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT › 0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT › 0 — — ns Note 1 17* TosH2ioV OSC1› (Q1 cycle) to — — 80 - 100 ns Port out valid 18* TosH2ioI OSC1› (Q2 cycle) to PIC16C71 100 — — ns Port input invalid (I/O in PIC16LC71 200 — — ns hold time) 19* TioV2osH Port input valid to OSC1› (I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C71 — 10 25 ns PIC16LC71 — — 60 ns 21* TioF Port output fall time PIC16C71 — 10 25 ns PIC16LC71 — — 60 ns 22††* Tinp INT pin high or low time 20 — — ns 23††* Trbp RB7:RB4 change INT high or low time 20 — — ns * These parameters are characterized but not tested. †Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30272A-page 142 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure 15-1 for load conditions. TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 200 — — ns VDD = 5V, -40˚C to +85˚C 31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5V, -40˚C to +85˚C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33 Tpwrt Power-up Timer Period 28* 72 132* ms VDD = 5V, -40˚C to +85˚C 34 TIOZ I/O High Impedance from MCLR — — 100 ns Low * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 143

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 15-5: TIMER0 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 TMR0 Note: Refer to Figure 15-1 for load conditions. TABLE 15-5: TIMER0 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet parameter 42 With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns N = prescale value (2, 4,..., 256) With Prescaler Greater of: 20 ns or TCY + 40 N * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30272A-page 144 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 TABLE 15-6: A/D CONVERTER CHARACTERISTICS Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8 bits bits VREF = VDD = 5.12V, VSS £ VAIN £ VREF A02 EABS Absolute error — — < – 1 LSb VREF = VDD = 5.12V, PIC16C71 VSS £ VAIN £ VREF PIC16LC71 — — < – 2 LSb VREF = VDD = 3.0V (Note 3) A03 EIL Integral linearity error — — < – 1 LSb VREF = VDD = 5.12V, PIC16C71 VSS £ VAIN £ VREF PIC16LC71 — — < – 2 LSb VREF = VDD = 3.0V (Note 3) A04 EDL Differential linearity error — — < – 1 LSb VREF = VDD = 5.12V, PIC16C71 VSS £ VAIN £ VREF PIC16LC71 — — < – 2 LSb VREF = VDD = 3.0V (Note 3) A05 EFS Full scale error — — < – 1 LSb VREF = VDD = 5.12V, PIC16C71 VSS £ VAIN £ VREF PIC16LC71 — — < – 2 LSb VREF = VDD = 3.0V (Note 3) A06 EOFF Offset error — — < – 1 LSb VREF = VDD = 5.12V, PIC16C71 VSS £ VAIN £ VREF PIC16LC71 — — < – 2 LSb VREF = VDD = 3.0V (Note 3) A10 — Monotonicity — guaranteed — — VSS £ VAIN £ VREF A20 VREF Reference voltage 3.0V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF V A30 ZAIN Recommended impedance of analog — — 10.0 kW voltage source A40 IAD A/D conversion current (VDD) — 180 — m A Average current consump- tion when A/D is on. (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 m A During VAIN acquisition. Based on differential of VHOLD to VAIN. PIC16C71 To charge CHOLD see Section 7.1. — — 40 m A During A/D Conversion cycle — — 1 mA During VAIN acquisition. Based on differential of VHOLD to VAIN. PIC16LC71 To charge CHOLD see Section 7.1. — — 10 m A During A/D Conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: These specifications apply if VREF = 3.0V and if VDD ‡ 3.0V. VAIN must be between VSS and VREF. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 145

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 15-6: A/D CONVERSION TIMING BSF ADCON0, GO 1 Tcy (TOSC/2) (1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-7: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period PIC16C71 2.0 — — m s TOSC based, VREF ‡ 3.0V PIC16LC71 2.0 — — m s TOSC based, VREF full range PIC16C71 2.0 4.0 6.0 m s A/D RC Mode PIC16LC71 3.0 6.0 9.0 m s A/D RC Mode 131 TCNV Conversion time — 9.5 — TAD (not including S/H time) (Note 1) 132 TACQ Acquisition time Note 2 20 — m s 5* — — m s The minimum time is the ampli- fier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 19.5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — Tosc/2§ — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert fi sample time 1.5§ — — TAD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. § These specifications ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 7.1 for min conditions. DS30272A-page 146 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 16.0 DC AND AC FIGURE 16-2: TYPICAL RC OSCILLATOR CHARACTERISTICS GRAPHS FREQUENCY VS. VDD AND TABLES FOR PIC16C71 5.0 The graphs and tables provided in this section are for R = 4.7k 4.5 design guidance and are not tested or guaranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside speci- 4.0 fied VDD range). This is for information only and devices are guaranteed to operate properly only 3.5 within the specified range. 3.0 Note: The data presented in this section is a sta- tistical summary of data collected on units R = 10k from different lots over a period of time and 2.5 matrix samples. 'Typical' represents the z) mean of the distribution while 'max' or 'min' H 2.0 M represents (mean + 3s ) and (mean - 3s ) c ( respectively where s is standard deviation. os 1.5 F Cext = 20 pF, T = 25(cid:176) C FIGURE 16-1: TYPICAL RC OSCILLATOR 1.0 FREQUENCY VS. TEMPERATURE R = 100k 0.5 Fosc Fosc (25(cid:176) C) Frequency Normalized to 25(cid:176) C 0.0 1.050 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) 1.025 Rext = 10k Cext = 100 pF 1.000 FIGURE 16-3: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD 0.975 VDD = 5.5V 2.0 0.950 R = 3.3k 0.925 VDD = 3.5V 1.8 0.900 1.6 0.875 1.4 R = 4.7k 0.850 0 10 20 30 40 50 60 70 1.2 T((cid:176) C) 1.0 z) H M 0.8 sc ( R = 10k o F 0.6 Cext = 100 pF, T = 25(cid:176) C 0.4 0.2 R = 100k 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 147

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-4: TYPICAL RC OSCILLATOR TABLE 16-1: RC OSCILLATOR FREQUENCY VS. VDD FREQUENCIES .8 Average R = 3.3k Cext Rext FOSC @ 5V, 25(cid:176) C .7 20 pF 4.7k 4.52 MHz – 17.35% 10k 2.47 MHz – 10.10% .6 R = 4.7k 100k 290.86 kHz – 11.90% 100 pF 3.3k 1.92 MHz – 9.43% 4.7k 1.49 MHz – 9.83% z) .5 10k 788.77 kHz – 10.92% H M 100k 88.11 kHz – 16.03% sc ( .4 300 pF 3.3k 726.89 kHz – 10.97% o F 4.7k 573.95 kHz – 10.14% R = 10k 10k 307.31 kHz – 10.43% .3 100k 33.82 kHz – 11.24% The percentage variation indicated here is part to part .2 variation due to normal process distribution. The varia- Cext = 300 pF, T = 25(cid:176) C tion indicated is – 3 standard deviation from average value for VDD = 5V. .1 ails. R = 100k FIGURE 16-6: TYPICAL IPD VS. VDD et WATCHDOG TIMER ENABLED or d 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 25(cid:176) C on f VDD (Volts) cti e 14 s FIGURE 16-5: TYPICAL IPD VS. VDD s hi WATCHDOG TIMER of t DISABLED 25(cid:176) C e 12 g a p 0.6 st fir 10 e e S s. 0.5 e pl A) 8 m x sa 0.4 mI (PD atri 6 m n o A) based mI (PD 0.3 4 a at D 0.2 2 0 0.1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30272A-page 148 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-7: MAXIMUM IPD VS. VDD FIGURE 16-8: MAXIMUM IPD VS. VDD WATCHDOG DISABLED WATCHDOG ENABLED 45 25 -55(cid:176) C 40 -40(cid:176) C 125(cid:176) C 35 20 30 125(cid:176) C 25 15 A) A) m (D 20 P m (D I 0(cid:176) C P 15 I 70(cid:176) C 10 85(cid:176) C ails. 85(cid:176) C 10 det or 70(cid:176) C 5 n f 5 o cti 0 e s 0(cid:176) C 3.0 3.5 4.0 4.5 5.0 5.5 6.0 s 0 --4505(cid:176)(cid:176) CC IPD, with Watchdog TiVmDeDr (eVnoaltbsl)ed, has two components: e of thi 3.0 3.5 4.0 4.5 5.0 5.5 6.0 The leakage current which increases with higher tempera- g a VDD (Volts) ture and the operating current of the Watchdog Timer logic p which increases with lower temperature. At -40(cid:176) C, the latter st dominates explaining the apparently anomalous behavior. fir e e S s. FIGURE 16-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS. VDD e pl m a s 2.00 atrix m 1.80 on Max (-40˚C to 85˚C) d e s a 1.60 b a at 25˚C, TYP D 1.40 s) olt V (H 1.20 Min (-40˚C to 85˚C) T V 1.00 0.80 0.60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 149

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-10:VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD 4.50 VIH, Max (-40(cid:176) C to 85(cid:176) C) VIH, Typ (25(cid:176) C) 4.00 VIH, Min (-40(cid:176) C to 85(cid:176) C) 3.50 3.00 s) olt 2.50 V (L 2.00 VI V, IH 1.50 VIL, Max (-40(cid:176) C to 85(cid:176) C) 1.00 VIL, Typ (25(cid:176) C) VIL, Min (-40(cid:176) C to 85(cid:176) C) 0.50 0.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) s. Note: These input pins have a Schmitt Trigger input buffer. ail et d or FIGURE 16-11:VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) n f VS. VDD o ecti Min (-40(cid:176) C to 85(cid:176) C) s s 3.60 hi of t 3.40 Max (-40(cid:176) C to 85(cid:176) C) TYP (25(cid:176) C) ge 3.20 a p st 3.00 e fir 2.80 e S 2.60 Min (-40(cid:176) C to 85(cid:176) C) ples. olts) 2.40 m V sa (H 2.20 atrix VT 2.00 m 1.80 n d o 1.60 e s 1.40 a b a 1.20 at D 1.00 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts) DS30272A-page 150 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-12:TYPICAL IDD VS. FREQ (EXT CLOCK, 25(cid:176) C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1,000 A) m (D D I 100 10 ails. et d or n f o cti 1 e s 10,000 100,000 1,000,000 10,000,000 100,000,000 his Frequency (Hz) of t e g FIGURE 16-13:MAXIMUM, IDD VS. FREQ (EXT CLOCK, -40(cid:176) TO +85(cid:176) C) pa st fir 10,000 e e 6.0 S 5.5 s. 5.0 e 4.5 mpl 4.0 a 3.5 s 3.0 x atri 1,000 m n A) d o mI (DD a base at D 100 10 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency (Hz) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 151

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-14:MAXIMUM IDD VS. FREQ WITH A/D OFF (EXT CLOCK, -55(cid:176) TO +125(cid:176) C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1,000 A) m (D D I 100 s. ail 10 det 10,000 100,000 1,000,000 10,000,000 100,000,000 n for Frequency (Hz) o FIGURE 16-15:WDT TIMER TIME-OUT FIGURE 16-16:TRANSCONDUCTANCE (gm) cti e PERIOD VS. VDD OF HS OSCILLATOR VS. VDD s s hi of t 9000 e g 50 a p 8000 st fir 45 ee 7000 S s. 40 Max, -40(cid:176) C ple 6000 m d on matrix sa eriod (ms) 3350 Max, 70(cid:176) C Max, 85(cid:176) C mgm (A/V) 54000000 Typ, 25(cid:176) C se T P 25 3000 a D b W Data 20 Typ, 25(cid:176) C 2000 Min, 85(cid:176) C Min, 0(cid:176) C 15 1000 10 0 Min, -40(cid:176) C 2 3 4 5 6 7 VDD (Volts) 5 2 3 4 5 6 7 VDD (Volts) DS30272A-page 152 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-17:TRANSCONDUCTANCE (gm) FIGURE 16-19:IOH VS. VOH, VDD = 3V OF LP OSCILLATOR VS. VDD 0 225 200 -5 Max, -40(cid:176) C Min, 85(cid:176) C 175 150 -10 V) 125 Typ, 25(cid:176) C mA) A/ (H Typ, 25(cid:176) C mm ( 100 Min, 85(cid:176) C IO g -15 75 s. 50 Max, -40(cid:176) C etail -20 d or 25 n f o cti 0 e s 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -25 s VDD (Volts) 0.0 0.5 1.0 VOH1 (.5Volts)2.0 2.5 3.0 of thi e g a FIGURE 16-18:TRANSCONDUCTANCE (gm) FIGURE 16-20:IOH VS. VOH, VDD = 5V st p OF XT OSCILLATOR VS. VDD fir e e 0 S 2500 s. e pl Max, -40(cid:176) C -5 m a s 2000 -10 atrix m -15 n o d 1500 Typ, 25(cid:176) C mA)-20 Min @ 85(cid:176) C base A/V) I( OH -25 Typ @ 25(cid:176) C Data mm ( -30 g 1000 -35 -40 Min, 85(cid:176) C Max @ -40(cid:176) C 500 -45 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 VOH (Volts) 2 3 4 5 6 7 VDD (Volts) (cid:211) 1997 Microchip Technology Inc. DS30272A-page 153

PIC16C71X Applicable Devices 710 71 711 715 FIGURE 16-21:IOL VS. VOL, VDD = 3V FIGURE 16-22:IOL VS. VOL, VDD = 5V 35 90 Max @ -40(cid:176) C 30 80 Max @ -40(cid:176) C 70 25 60 Typ @ 25(cid:176) C Typ @ 25(cid:176) C 20 mA) A) 50 (OL (mL Min @ +85(cid:176) C I 15 Min @ +85(cid:176) C IO 40 30 10 20 5 s. ail 10 et n for d 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 00.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 o VOL (Volts) cti e VOL (Volts) s s hi of t e g a p st fir e e S s. e pl m a s x atri m n o d e s a b a at D DS30272A-page 154 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 17.0 PACKAGING INFORMATION 17.1 18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) (JW) N a C E1 E eA Pin No. 1 eB Indicator Area D S S1 Base Plane Seating Plane L B1 e1 A1 A3 A A2 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 10(cid:176) 0(cid:176) 10(cid:176) A — 5.080 — 0.200 A1 0.381 1.7780 0.015 0.070 A2 3.810 4.699 0.150 0.185 A3 3.810 4.445 0.150 0.175 B 0.355 0.585 0.014 0.023 B1 1.270 1.651 Typical 0.050 0.065 Typical C 0.203 0.381 Typical 0.008 0.015 Typical D 22.352 23.622 0.880 0.930 D1 20.320 20.320 Reference 0.800 0.800 Reference E 7.620 8.382 0.300 0.330 E1 5.588 7.874 0.220 0.310 e1 2.540 2.540 Reference 0.100 0.100 Reference eA 7.366 8.128 Typical 0.290 0.320 Typical eB 7.620 10.160 0.300 0.400 L 3.175 3.810 0.125 0.150 N 18 18 18 18 S 0.508 1.397 0.020 0.055 S1 0.381 1.270 0.015 0.050 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 155

PIC16C71X 17.2 18-Lead Plastic Dual In-line (300 mil) (P) N a C E1 E eA Pin No. 1 eB Indicator Area D S S1 Base Plane Seating Plane L B1 e1 A1 A2 A B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 10(cid:176) 0(cid:176) 10(cid:176) A – 4.064 – 0.160 A1 0.381 – 0.015 – A2 3.048 3.810 0.120 0.150 B 0.355 0.559 0.014 0.022 B1 1.524 1.524 Reference 0.060 0.060 Reference C 0.203 0.381 Typical 0.008 0.015 Typical D 22.479 23.495 0.885 0.925 D1 20.320 20.320 Reference 0.800 0.800 Reference E 7.620 8.255 0.300 0.325 E1 6.096 7.112 0.240 0.280 e1 2.489 2.591 Typical 0.098 0.102 Typical eA 7.620 7.620 Reference 0.300 0.300 Reference eB 7.874 9.906 0.310 0.390 L 3.048 3.556 0.120 0.140 N 18 18 18 18 S 0.889 – 0.035 – S1 0.127 – 0.005 – DS30272A-page 156 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 17.3 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)(SO) e B h x 45(cid:176) N Index Area E H a C Chamfer L h x 45(cid:176) 1 2 3 D Base CP Seating Plane Plane A1 A Package Group: Plastic SOIC (SO) Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 8(cid:176) 0(cid:176) 8(cid:176) A 2.362 2.642 0.093 0.104 A1 0.101 0.300 0.004 0.012 B 0.355 0.483 0.014 0.019 C 0.241 0.318 0.009 0.013 D 11.353 11.735 0.447 0.462 E 7.416 7.595 0.292 0.299 e 1.270 1.270 Reference 0.050 0.050 Reference H 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 L 0.406 1.143 0.016 0.045 N 18 18 18 18 CP – 0.102 – 0.004 (cid:211) 1997 Microchip Technology Inc. DS30272A-page 157

PIC16C71X 17.4 20-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS) N Index area E H a C L 1 2 3 e B A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Inches Symbol Min Max Notes Min Max Notes a 0(cid:176) 8(cid:176) 0(cid:176) 8(cid:176) A 1.730 1.990 0.068 0.078 A1 0.050 0.210 0.002 0.008 B 0.250 0.380 0.010 0.015 C 0.130 0.220 0.005 0.009 D 7.070 7.330 0.278 0.289 E 5.200 5.380 0.205 0.212 e 0.650 0.650 Reference 0.026 0.026 Reference H 7.650 7.900 0.301 0.311 L 0.550 0.950 0.022 0.037 N 20 20 20 20 CP - 0.102 - 0.004 Note1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per side. D1 and E1 dimensions including mold mismatch. 2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m (0.003”)max. 3: This outline conforms to JEDEC MS-026. DS30272A-page 158 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X 17.5 Package Marking Information 18-Lead PDIP Example MMMMMMMMMMMMM PIC16C711-04/P XXXXXXXXXXXXXXXX AABBCDE 9452CBA 18-Lead SOIC Example MMMMMMMMMM PIC16C715 XXXXXXXXXXXX -20/50 XXXXXXXXXXXX AABBCDE 9447CBA 18-Lead CERDIP Windowed Example MMMMMM PIC16C71 XXXXXXXX /JW AABBCDE 945/CBT 20-Lead SSOP Example XXXXXXXX PIC16C710 XXXXXXXX 20I/SS025 AABBCAE 9517SBP Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calender year) BB Week code (week of January 1 is week '01’) C Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 159

PIC16C71X NOTES: DS30272A-page 160 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X APPENDIX A: APPENDIX B: COMPATIBILITY The following are the list of modifications over the To convert code written for PIC16C5X to PIC16CXX, PIC16C5X microcontroller family: the user should take the following steps: 1. Instruction word length is increased to 14-bits. 1. Remove any program memory page select This allows larger page sizes both in program operations (PA2, PA1, PA0 bits) for CALL, GOTO. memory (1K now as opposed to 512 before) and 2. Revisit any computed jump operations (write to register file (68 bytes now versus 32 bytes PC or add to PC, etc.) to make sure page bits before). are set properly under the new scheme. 2. A PC high latch register (PCLATH) is added to 3. Eliminate any data memory page switching. handle program memory paging. Bits PA2, PA1, Redefine data variables to reallocate them. PA0 are removed from STATUS register. 4. Verify all writes to STATUS, OPTION, and FSR 3. Data memory paging is redefined slightly. registers since these have changed. STATUS register is modified. 5. Change reset vector to 0000h. 4. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compati- bility with PIC16C5X. 5. OPTION and TRIS registers are made address- able. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8 deep. 8. Reset vector is changed to 0000h. 9. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Reg- isters are reset differently. 10. Wake up from SLEEP through interrupt is added. 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These tim- ers are invoked selectively to avoid unneces- sary delays on power-up and wake-up. 12. PORTB has weak pull-ups and interrupt on change feature. 13. T0CKI pin is also a port pin (RA4) now. 14. FSR is made a full eight bit register. 15. “In-circuit serial programming” is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). 16. PCON status register is added with a Power-on Reset status bit (POR). 17. Code protection scheme is enhanced such that portions of the program memory can be pro- tected, while the remainder is unprotected. 18. Brown-out protection circuitry has been added. Controlled by configuration word bit BODEN. Brown-out reset ensures the device is placed in a reset condition if VDD dips below a fixed set- point. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 161

PIC16C71X APPENDIX C: WHAT’S NEW APPENDIX D: WHAT’S CHANGED 1. Consolidated all pin compatible 18-pin A/D 1. Minor changes, spelling and grammatical based devices into one data sheet. changes. 2. Low voltage operation on the PIC16LC710/711/ 715 has been reduced from 3.0V to 2.5V. 3. Part numbers of the PIC16C70 and PIC16C71A have changed to PIC16C710 and PIC16C711, respectively. DS30272A-page 162 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X INDEX RB7:RB4 Port Pins .....................................................28 Timer0 ........................................................................31 A Timer0/WDT Prescaler ...............................................34 Watchdog Timer .........................................................65 A/D BODEN bit ..........................................................................48 Accuracy/Error ...........................................................44 BOR bit ........................................................................22, 54 ADIF bit ......................................................................39 Brown-out Reset (BOR) ......................................................53 Analog Input Model Block Diagram ............................40 Analog-to-Digital Converter ........................................37 C Configuring Analog Port Pins .....................................41 C bit ....................................................................................17 Configuring the Interrupt ............................................39 C16C71 ..............................................................................47 Configuring the Module ..............................................39 Carry bit ................................................................................7 Connection Considerations ........................................44 CHS0 bit .............................................................................37 Conversion Clock .......................................................41 CHS1 bit .............................................................................37 Conversion Time ........................................................43 Clocking Scheme ................................................................10 Conversions ...............................................................42 Code Examples Converter Characteristics ..........................99, 122, 145 Call of a Subroutine in Page 1 from Page 0 ...............24 Delays ........................................................................40 Changing Prescaler (Timer0 to WDT) ........................35 Effects of a Reset .......................................................44 Changing Prescaler (WDT to Timer0) ........................35 Equations ...................................................................40 Doing an A/D Conversion ...........................................42 Faster Conversion - Lower Resolution Trade-off .......43 I/O Programming ........................................................30 Flowchart of A/D Operation ........................................45 Indirect Addressing .....................................................24 GO/DONE bit .............................................................39 Initializing PORTA ......................................................25 Internal Sampling Switch (Rss) Impedence ...............40 Initializing PORTB ......................................................27 Minimum Charging Time ............................................40 Saving STATUS and W Registers in RAM .................64 Operation During Sleep .............................................44 Code Protection ...........................................................47, 67 Sampling Requirements .............................................40 Computed GOTO ...............................................................23 Source Impedence .....................................................40 Configuration Bits ...............................................................47 Time Delays ...............................................................40 CP0 bit .........................................................................47, 48 Transfer Function .......................................................45 CP1 bit ................................................................................48 Absolute Maximum Ratings ...............................89, 111, 135 AC Characteristics D PIC16C710 ..............................................................101 DC bit ..................................................................................17 PIC16C711 ..............................................................101 DC Characteristics ...........................................................147 PIC16C715 ..............................................................125 PIC16C71 ................................................................136 ADCON0 Register ..............................................................37 PIC16C710 ........................................................90, 101 ADCON1 ............................................................................37 PIC16C711 ........................................................90, 101 ADCON1 Register ........................................................14, 37 PIC16C715 ......................................................113, 125 ADCS0 bit ..........................................................................37 Development Support ....................................................3, 85 ADCS1 bit ..........................................................................37 Development Tools .............................................................85 ADIE bit ........................................................................19, 20 Diagrams - See Block Diagrams ADIF bit ........................................................................21, 37 Digit Carry bit ........................................................................7 ADON bit ............................................................................37 Direct Addressing ...............................................................24 ADRES Register ....................................................15, 37, 39 ALU ......................................................................................7 E Application Notes Electrical Characteristics AN546 ........................................................................37 PIC16C71 ................................................................135 AN552 ........................................................................27 PIC16C710 .................................................................89 AN556 ........................................................................23 PIC16C711 .................................................................89 AN607, Power-up Trouble Shooting ..........................53 PIC16C715 ..............................................................111 Architecture External Brown-out Protection Circuit .................................60 Harvard ........................................................................7 External Power-on Reset Circuit ........................................60 Overview ......................................................................7 F von Neumann ...............................................................7 Assembler Family of Devices MPASM Assembler ....................................................86 PIC16C71X ...................................................................4 FOSC0 bit ....................................................................47, 48 B FOSC1 bit ....................................................................47, 48 Block Diagrams FSR Register .........................................................15, 16, 24 Analog Input Model ....................................................40 Fuzzy Logic Dev. System (fuzzyTECH(cid:210) -MP) .....................87 On-Chip Reset Circuit ................................................52 G PIC16C71X ..................................................................8 RA3/RA0 Port Pins ....................................................25 General Description ..............................................................3 RA4/T0CKI Pin ...........................................................25 GIE bit ..........................................................................19, 61 RB3:RB0 Port Pins ....................................................27 GO/DONE bit ......................................................................37 RB7:RB4 Pins ............................................................28 (cid:211) 1997 Microchip Technology Inc. DS30390D-page 163

PIC16C71X I TMR0 Overflow ..........................................................61 INTF bit ..............................................................................19 I/O Ports IRP bit ................................................................................17 PORTA .......................................................................25 PORTB .......................................................................27 K Section .......................................................................25 (cid:210) KeeLoq Evaluation and Programming Tools ...................87 I/O Programming Considerations .......................................30 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ...........85 L In-Circuit Serial Programming ......................................47, 67 Loading of PC ....................................................................23 INDF Register ........................................................14, 16, 24 LP ......................................................................................54 Indirect Addressing ............................................................24 Instruction Cycle .................................................................10 M Instruction Flow/Pipelining .................................................10 MCLR ...........................................................................52, 56 Instruction Format ..............................................................69 Memory Instruction Set Data Memory .............................................................12 ADDLW ......................................................................71 Program Memory .......................................................11 ADDWF ......................................................................71 Register File Maps ANDLW ......................................................................71 PIC16C71 ..........................................................12 ANDWF ......................................................................71 PIC16C710 ........................................................12 BCF ............................................................................72 PIC16C711 ........................................................13 BSF ............................................................................72 PIC16C715 ........................................................13 BTFSC .......................................................................72 MP-DriveWay(cid:228) - Application Code Generator ..................87 BTFSS .......................................................................73 MPEEN bit ...................................................................22, 48 CALL ..........................................................................73 MPLAB(cid:228) C ........................................................................87 CLRF ..........................................................................74 MPLAB(cid:228) Integrated Development Environment CLRW ........................................................................74 Software .............................................................................86 CLRWDT ....................................................................74 COMF ........................................................................75 O DECF .........................................................................75 OPCODE ...........................................................................69 DECFSZ .....................................................................75 OPTION Register ...............................................................18 GOTO ........................................................................76 Orthogonal ...........................................................................7 INCF ...........................................................................76 OSC selection ....................................................................47 INCFSZ ......................................................................77 Oscillator IORLW .......................................................................77 HS ........................................................................49, 54 IORWF .......................................................................78 LP ........................................................................49, 54 MOVF .........................................................................78 RC .............................................................................49 MOVLW .....................................................................78 XT ........................................................................49, 54 MOVWF .....................................................................78 Oscillator Configurations ....................................................49 NOP ...........................................................................79 Oscillator Start-up Timer (OST) .........................................53 OPTION .....................................................................79 P RETFIE ......................................................................79 RETLW ......................................................................80 Packaging RETURN ....................................................................80 18-Lead CERDIP w/Window ...................................155 RLF ............................................................................81 18-Lead PDIP ..........................................................156 RRF ............................................................................81 18-Lead SOIC ..........................................................157 SLEEP .......................................................................82 20-Lead SSOP ........................................................158 SUBLW ......................................................................82 Paging, Program Memory ..................................................23 SUBWF ......................................................................83 PCL Register ...................................................14, 15, 16, 23 SWAPF ......................................................................83 PCLATH .......................................................................57, 58 TRIS ...........................................................................83 PCLATH Register ............................................14, 15, 16, 23 XORLW ......................................................................84 PCON Register ............................................................22, 54 XORWF ......................................................................84 PD bit .....................................................................17, 52, 55 Section .......................................................................69 PER bit ...............................................................................22 Summary Table ..........................................................70 PIC16C71 ........................................................................147 INT Interrupt .......................................................................63 AC Characteristics ...................................................147 INTCON Register ...............................................................19 PICDEM-1 Low-Cost PIC16/17 Demo Board ....................86 INTE bit ..............................................................................19 PICDEM-2 Low-Cost PIC16CXX Demo Board ..................86 INTEDG bit ...................................................................18, 63 PICDEM-3 Low-Cost PIC16CXXX Demo Board ...............86 Internal Sampling Switch (Rss) Impedence .......................40 PICMASTER(cid:210) In-Circuit Emulator .....................................85 Interrupts ............................................................................47 PICSTART(cid:210) Plus Entry Level Development System .........85 A/D .............................................................................61 PIE1 Register .....................................................................20 External ......................................................................61 Pin Functions PORTB Change .........................................................61 MCLR/VPP ...................................................................9 PortB Change ............................................................63 OSC1/CLKIN ...............................................................9 RB7:RB4 Port Change ...............................................27 OSC2/CLKOUT ...........................................................9 Section .......................................................................61 RA0/AN0 ......................................................................9 TMR0 .........................................................................63 RA1/AN1 ......................................................................9 DS30390D-page 164 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X RA2/AN2 ......................................................................9 PIC16C711 .........................................................13 RA3/AN3/VREF .............................................................9 PIC16C715 .........................................................13 RA4/T0CKI ...................................................................9 Reset Conditions ........................................................56 RB0/INT .......................................................................9 Summary .............................................................14–?? RB1 ..............................................................................9 Reset ...........................................................................47, 52 RB2 ..............................................................................9 Reset Conditions for Special Registers ..............................56 RB3 ..............................................................................9 RP0 bit .........................................................................12, 17 RB4 ..............................................................................9 RP1 bit ................................................................................17 RB5 ..............................................................................9 S RB6 ..............................................................................9 (cid:210) RB7 ..............................................................................9 SEEVAL Evaluation and Programming System ...............87 VDD ..............................................................................9 Services VSS ...............................................................................9 One-Time-Programmable (OTP) Devices ....................5 Pinout Descriptions Quick-Turnaround-Production (QTP) Devices ..............5 PIC16C71 ....................................................................9 Serialized Quick-Turnaround Production (SQTP) PIC16C710 ..................................................................9 Devices .........................................................................5 PIC16C711 ..................................................................9 SLEEP .........................................................................47, 52 PIC16C715 ..................................................................9 Software Simulator (MPLAB(cid:228) SIM) ...................................87 PIR1 Register .....................................................................21 Special Features of the CPU ..............................................47 POP ...................................................................................23 Special Function Registers POR .............................................................................53, 54 PIC16C71 ...................................................................14 Oscillator Start-up Timer (OST) ...........................47, 53 PIC16C710 .................................................................14 Power Control Register (PCON) ................................54 PIC16C711 .................................................................14 Power-on Reset (POR) ............................47, 53, 57, 58 Special Function Registers, Section ...................................14 Power-up Timer (PWRT) .....................................47, 53 Stack ...................................................................................23 Time-out Sequence ....................................................54 Overflows ....................................................................23 Time-out Sequence on Power-up ..............................59 Underflow ...................................................................23 TO ........................................................................52, 55 STATUS Register ...............................................................17 POR bit ........................................................................22, 54 T Port RB Interrupt ................................................................63 PORTA .........................................................................57, 58 T0CS bit ..............................................................................18 PORTA Register ....................................................14, 15, 25 T0IE bit ...............................................................................19 PORTB .........................................................................57, 58 T0IF bit ...............................................................................19 PORTB Register ....................................................14, 15, 27 TAD .....................................................................................41 Power-down Mode (SLEEP) ..............................................66 Timer0 Prescaler, Switching Between Timer0 and WDT ...............35 RTCC ...................................................................57, 58 PRO MATE(cid:210) II Universal Programmer ..............................85 Timers Program Branches ...............................................................7 Timer0 Program Memory Block Diagram ....................................................31 Paging ........................................................................23 External Clock ....................................................33 Program Memory Maps External Clock Timing ........................................33 PIC16C71 ..................................................................11 Increment Delay .................................................33 PIC16C710 ................................................................11 Interrupt ..............................................................31 PIC16C711 ................................................................11 Interrupt Timing ..................................................32 PIC16C715 ................................................................11 Prescaler ............................................................34 Program Verification ..........................................................67 Prescaler Block Diagram ....................................34 PS0 bit ...............................................................................18 Section ...............................................................31 PS1 bit ...............................................................................18 Switching Prescaler Assignment ........................35 PS2 bit ...............................................................................18 Synchronization ..................................................33 PSA bit ...............................................................................18 T0CKI .................................................................33 PUSH .................................................................................23 T0IF ....................................................................63 PWRT Timing .................................................................31 Power-up Timer (PWRT) ...........................................53 TMR0 Interrupt ...................................................63 PWRTE bit ...................................................................47, 48 Timing Diagrams A/D Conversion .......................................100, 124, 146 R Brown-out Reset ..................................................53, 97 RBIE bit ..............................................................................19 CLKOUT and I/O .......................................96, 119, 142 RBIF bit ..................................................................19, 27, 63 External Clock Timing ................................95, 118, 141 RBPU bit ............................................................................18 Power-up Timer .................................................97, 143 RC ......................................................................................54 Reset .................................................................97, 143 RC Oscillator ................................................................51, 54 Start-up Timer ....................................................97, 143 Read-Modify-Write .............................................................30 Time-out Sequence ....................................................59 Register File .......................................................................12 Timer0 .................................................31, 98, 121, 144 Registers Timer0 Interrupt Timing ..............................................32 Maps Timer0 with External Clock .........................................33 PIC16C71 ..........................................................12 Wake-up from SLEEP through Interrupt .....................67 PIC16C710 ........................................................12 Watchdog Timer ................................................97, 143 (cid:211) 1997 Microchip Technology Inc. DS30390D-page 165

PIC16C71X TO bit .................................................................................17 LIST OF EXAMPLES TOSE bit .............................................................................18 TRISA Register ......................................................14, 16, 25 Example 3-1: Instruction Pipeline Flow...........................10 TRISB Register ......................................................14, 16, 27 Example 4-1: Call of a Subroutine in Page 1 from Two’s Complement ..............................................................7 Page 0......................................................24 Example 4-2: Indirect Addressing...................................24 U Example 5-1: Initializing PORTA.....................................25 Upward Compatibility ...........................................................3 Example 5-2: Initializing PORTB.....................................27 UV Erasable Devices ...........................................................5 Example 5-3: Read-Modify-Write Instructions W on an I/O Port...........................................30 Example 6-1: Changing Prescaler (Timer0fi WDT)........35 W Register Example 6-2: Changing Prescaler (WDTfi Timer0)........35 ALU ..............................................................................7 Equation 7-1: A/D Minimum Charging Time....................40 Wake-up from SLEEP ........................................................66 Example 7-1: Calculating the Minimum Required Watchdog Timer (WDT) ...................................47, 52, 56, 65 Aquisition Time.........................................40 WDT ...................................................................................56 Example 7-2: A/D Conversion.........................................42 Block Diagram ............................................................65 Example 7-3: 4-bit vs. 8-bit Conversion Times...............43 Programming Considerations ....................................65 Example 8-1: Saving STATUS and W Registers Timeout ................................................................57, 58 in RAM......................................................64 WDT Period ........................................................................65 WDTE bit ......................................................................47, 48 LIST OF FIGURES Z Figure 3-1: PIC16C71X Block Diagram........................8 Z bit ....................................................................................17 Figure 3-2: Clock/Instruction Cycle.............................10 Zero bit .................................................................................7 Figure 4-1: PIC16C710 Program Memory Map and Stack..................................................11 Figure 4-2: PIC16C71/711 Program Memory Map and Stack..................................................11 Figure 4-3: PIC16C715 Program Memory Map and Stack..................................................11 Figure 4-4: PIC16C710/71 Register File Map.............12 Figure 4-5: PIC16C711 Register File Map..................13 Figure 4-6: PIC16C715 Register File Map..................13 Figure 4-7: Status Register (Address 03h, 83h)..........17 Figure 4-8: OPTION Register (Address 81h, 181h)....18 Figure 4-9: INTCON Register (Address 0Bh, 8Bh).....19 Figure 4-10: PIE1 Register (Address 8Ch)...................20 Figure 4-11: PIR1 Register (Address 0Ch)...................21 Figure 4-12: PCON Register (Address 8Eh), PIC16C710/711........................................22 Figure 4-13: PCON Register (Address 8Eh), PIC16C715...............................................22 Figure 4-14: Loading of PC In Different Situations........23 Figure 4-15: Direct/Indirect Addressing.........................24 Figure 5-1: Block Diagram of RA3:RA0 Pins..............25 Figure 5-2: Block Diagram of RA4/T0CKI Pin.............25 Figure 5-3: Block Diagram of RB3:RB0 Pins..............27 Figure 5-4: Block Diagram of RB7:RB4 Pins (PIC16C71)...............................................28 Figure 5-5: Block Diagram of RB7:RB4 Pins (PIC16C710/711/715)...............................28 Figure 5-6: Successive I/O Operation.........................30 Figure 6-1: Timer0 Block Diagram..............................31 Figure 6-2: Timer0 Timing: Internal Clock/ No Prescale..............................................31 Figure 6-3: Timer0 Timing: Internal Clock/ Prescale 1:2..............................................32 Figure 6-4: Timer0 Interrupt Timing............................32 Figure 6-5: Timer0 Timing with External Clock...........33 Figure 6-6: Block Diagram of the Timer0/ WDT Prescaler.........................................34 Figure 7-1: ADCON0 Register (Address 08h), PIC16C710/71/711...................................37 Figure 7-2: ADCON0 Register (Address 1Fh), PIC16C715...............................................38 DS30390D-page 166 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X Figure 7-3: ADCON1 Register, PIC16C710/71/711 Figure 12-9: Maximum IPD vs. VDD Brown-out Detect (Address 88h), Enabled (85(cid:176) C to -40(cid:176) C, RC Mode)........103 PIC16C715 (Address 9Fh)........................38 Figure 12-10: Typical IPD vs. Timer1 Enabled Figure 7-4: A/D Block Diagram....................................39 (32 kHz, RC0/RC1 = 33 pF/33 pF, Figure 7-5: Analog Input Model...................................40 RC Mode)...............................................103 Figure 7-6: A/D Transfer Function...............................45 Figure 12-11: Maximum IPD vs. Timer1 Enabled Figure 7-7: Flowchart of A/D Operation.......................45 (32 kHz, RC0/RC1 = 33 pF/33 pF, Figure 8-1: Configuration Word for PIC16C71............47 85(cid:176) C to -40(cid:176) C, RC Mode).......................103 Figure 8-2: Configuration Word, PIC16C710/711........48 Figure 12-12: Typical IDD vs. Frequency Figure 8-3: Configuration Word, PIC16C715...............48 (RC Mode @ 22 pF, 25(cid:176) C).....................104 Figure 8-4: Crystal/Ceramic Resonator Operation Figure 12-13: Maximum IDD vs. Frequency (HS, XT or LP OSC Configuration)...........49 (RC Mode @ 22 pF, -40(cid:176) C to 85(cid:176) C).......104 Figure 8-5: External Clock Input Operation Figure 12-14: Typical IDD vs. Frequency (HS, XT or LP OSC Configuration)...........49 (RC Mode @ 100 pF, 25(cid:176) C)...................105 Figure 8-6: External Parallel Resonant Crystal Figure 12-15: Maximum IDD vs. Frequency Oscillator Circuit........................................51 (RC Mode @ 100 pF, -40(cid:176) C to 85(cid:176) C).....105 Figure 8-7: External Series Resonant Crystal Figure 12-16: Typical IDD vs. Frequency Oscillator Circuit........................................51 (RC Mode @ 300 pF, 25(cid:176) C)...................106 Figure 8-8: RC Oscillator Mode...................................51 Figure 12-17: Maximum IDD vs. Frequency Figure 8-9: Simplified Block Diagram of On-chip (RC Mode @ 300 pF, -40(cid:176) C to 85(cid:176) C).....106 Reset Circuit..............................................52 Figure 12-18: Typical IDD vs. Capacitance Figure 8-10: Brown-out Situations.................................53 @ 500 kHz (RC Mode)...........................107 Figure 8-11: Time-out Sequence on Power-up Figure 12-19: Transconductance(gm) of (MCLR not Tied to VDD): Case 1...............59 HS Oscillator vs. VDD..............................107 Figure 8-12: Time-out Sequence on Power-up Figure 12-20: Transconductance(gm) of (MCLR Not Tied To VDD): Case 2.............59 LP Oscillator vs. VDD..............................107 Figure 8-13: Time-out Sequence on Power-up Figure 12-21: Transconductance(gm) of (MCLR Tied to VDD)..................................59 XT Oscillator vs. VDD..............................107 Figure 8-14: External Power-on Reset Circuit Figure 12-22: Typical XTAL Startup Time vs. (for Slow VDD Power-up)...........................60 VDD (LP Mode, 25(cid:176) C).............................108 Figure 8-15: External Brown-out Protection Circuit 1....60 Figure 12-23: Typical XTAL Startup Time vs. Figure 8-16: External Brown-out Protection Circuit 2....60 VDD (HS Mode, 25(cid:176) C).............................108 Figure 8-17: Interrupt Logic, PIC16C710, 71, 711.........62 Figure 12-24: Typical XTAL Startup Time vs. Figure 8-18: Interrupt Logic, PIC16C715.......................62 VDD (XT Mode, 25(cid:176) C).............................108 Figure 8-19: INT Pin Interrupt Timing............................63 Figure 12-25: Typical IDD vs. Frequency Figure 8-20: Watchdog Timer Block Diagram...............65 (LP Mode, 25(cid:176) C).....................................109 Figure 8-21: Summary of Watchdog Timer Registers...65 Figure 12-26: Maximum IDD vs. Frequency Figure 8-22: Wake-up from Sleep Through Interrupt.....67 (LP Mode, 85(cid:176) C to -40(cid:176) C).......................109 Figure 8-23: Typical In-Circuit Serial Programming Figure 12-27: Typical IDD vs. Frequency Connection................................................67 (XT Mode, 25(cid:176) C).....................................109 Figure 9-1: General Format for Instructions................69 Figure 12-28: Maximum IDD vs. Frequency Figure 11-1: Load Conditions........................................94 (XT Mode, -40(cid:176) C to 85(cid:176) C)......................109 Figure 11-2: External Clock Timing...............................95 Figure 12-29: Typical IDD vs. Frequency Figure 11-3: CLKOUT and I/O Timing...........................96 (HS Mode, 25(cid:176) C)....................................110 Figure 11-4: Reset, Watchdog Timer, Oscillator Figure 12-30: Maximum IDD vs. Frequency Start-up Timer and Power-up Timer (HS Mode, -40(cid:176) C to 85(cid:176) C)......................110 Timing.......................................................97 Figure 13-1: Load Conditions......................................117 Figure 11-5: Brown-out Reset Timing............................97 Figure 13-2: External Clock Timing.............................118 Figure 11-6: Timer0 External Clock Timings.................98 Figure 13-3: CLKOUT and I/O Timing.........................119 Figure 11-7: A/D Conversion Timing...........................100 Figure 13-4: Reset, Watchdog Timer, Oscillator Figure 12-1: Typical IPD vs. VDD Start-Up Timer, and Power-Up Timer (WDT Disabled, RC Mode).....................101 Timing.....................................................120 Figure 12-2: Maximum IPD vs. VDD Figure 13-5: Brown-out Reset Timing.........................120 (WDT Disabled, RC Mode).....................101 Figure 13-6: Timer0 Clock Timings.............................121 Figure 12-3: Typical IPD vs. VDD @ 25(cid:176) C Figure 13-7: A/D Conversion Timing...........................124 (WDT Enabled, RC Mode)......................102 Figure 14-1: Typical IPD vs. VDD Figure 12-4: Maximum IPD vs. VDD (WDT Disabled, RC Mode).....................125 (WDT Enabled, RC Mode)......................102 Figure 14-2: Maximum IPD vs. VDD Figure 12-5: Typical RC Oscillator Frequency (WDT Disabled, RC Mode).....................125 vs. VDD....................................................102 Figure 14-3: Typical IPD vs. VDD @ 25(cid:176) C Figure 12-6: Typical RC Oscillator Frequency (WDT Enabled, RC Mode)......................126 vs. VDD....................................................102 Figure 14-4: Maximum IPD vs. VDD Figure 12-7: Typical RC Oscillator Frequency (WDT Enabled, RC Mode)......................126 vs. VDD....................................................102 Figure 14-5: Typical RC Oscillator Frequency vs. Figure 12-8: Typical IPD vs. VDD Brown-out Detect VDD.........................................................126 Enabled (RC Mode)................................103 (cid:211) 1997 Microchip Technology Inc. DS30390D-page 167

PIC16C71X Figure 14-6: Typical RC Oscillator Frequency vs. Figure 16-4: Typical RC Oscillator Frequency vs. VDD..........................................................126 VDD.........................................................148 Figure 14-7: Typical RC Oscillator Frequency vs. Figure 16-5: Typical Ipd vs. VDD Watchdog Timer VDD..........................................................126 Disabled 25(cid:176) C.........................................148 Figure 14-8: Typical IPD vs. VDD Brown-out Detect Figure 16-6: Typical Ipd vs. VDD Watchdog Timer Enabled (RC Mode)................................127 Enabled 25(cid:176) C..........................................148 Figure 14-9: Maximum IPD vs. VDD Brown-out Detect Figure 16-7: Maximum Ipd vs. VDD Watchdog Enabled Disabled..................................................149 (85(cid:176) C to -40(cid:176) C, RC Mode)......................127 Figure 16-8: Maximum Ipd vs. VDD Watchdog Figure 14-10: Typical IPD vs. Timer1 Enabled (32 kHz, Enabled...................................................149 RC0/RC1 = 33 pF/33 pF, RC Mode).......127 Figure 16-9: Vth (Input Threshold Voltage) of Figure 14-11: Maximum IPD vs. Timer1 Enabled I/O Pins vs. VDD......................................149 (32 kHz, RC0/RC1 = 33 pF/33 pF, Figure 16-10: VIH, VIL of MCLR, T0CKI and OSC1 85(cid:176) C to -40(cid:176) C, RC Mode)........................127 (in RC Mode) vs. VDD.............................150 Figure 14-12: Typical IDD vs. Frequency Figure 16-11: VTH (Input Threshold Voltage) (RC Mode @ 22 pF, 25(cid:176) C)......................128 of OSC1 Input (in XT, HS, and Figure 14-13: Maximum IDD vs. Frequency LP Modes) vs. VDD.................................150 (RC Mode @ 22 pF, -40(cid:176) C to 85(cid:176) C)........128 Figure 16-12: Typical IDD vs. Freq (Ext Clock, 25(cid:176) C)....151 Figure 14-14: Typical IDD vs. Frequency Figure 16-13: Maximum, IDD vs. Freq (Ext Clock, (RC Mode @ 100 pF, 25(cid:176) C)....................129 -40(cid:176) to +85(cid:176) C).........................................151 Figure 14-15: Maximum IDD vs. Frequency Figure 16-14: Maximum IDD vs. Freq with A/D Off (RC Mode @ 100 pF, -40(cid:176) C to 85(cid:176) C)......129 (Ext Clock, -55(cid:176) to +125(cid:176) C)....................152 Figure 14-16: Typical IDD vs. Frequency Figure 16-15: WDT Timer Time-out Period vs. VDD......152 (RC Mode @ 300 pF, 25(cid:176) C)....................130 Figure 16-16: Transconductance (gm) of Figure 14-17: Maximum IDD vs. Frequency HS Oscillator vs. VDD..............................152 (RC Mode @ 300 pF, -40(cid:176) C to 85(cid:176) C)......130 Figure 16-17: Transconductance (gm) of Figure 14-18: Typical IDD vs. Capacitance @ 500 kHz LP Oscillator vs. VDD..............................153 (RC Mode)...............................................131 Figure 16-18: Transconductance (gm) of Figure 14-19: Transconductance(gm) of XT Oscillator vs. VDD..............................153 HS Oscillator vs. VDD..............................131 Figure 16-19: IOH vs. VOH, VDD = 3V..........................153 Figure 14-20: Transconductance(gm) of Figure 16-20: IOH vs. VOH, VDD = 5V..........................153 LP Oscillator vs. VDD...............................131 Figure 16-21: IOL vs. VOL, VDD = 3V...........................154 Figure 14-21: Transconductance(gm) of Figure 16-22: IOL vs. VOL, VDD = 5V...........................154 XT Oscillator vs. VDD..............................131 Figure 14-22: Typical XTAL Startup Time vs. VDD (LP Mode, 25(cid:176) C)..............................132 Figure 14-23: Typical XTAL Startup Time vs. VDD (HS Mode, 25(cid:176) C).............................132 Figure 14-24: Typical XTAL Startup Time vs. VDD (XT Mode, 25(cid:176) C)..............................132 Figure 14-25: Typical IDD vs. Frequency (LP Mode, 25(cid:176) C).....................................133 Figure 14-26: Maximum IDD vs. Frequency (LP Mode, 85(cid:176) C to -40(cid:176) C).......................133 Figure 14-27: Typical IDD vs. Frequency (XT Mode, 25(cid:176) C).....................................133 Figure 14-28: Maximum IDD vs. Frequency (XT Mode, -40(cid:176) C to 85(cid:176) C).......................133 Figure 14-29: Typical IDD vs. Frequency (HS Mode, 25(cid:176) C).....................................134 Figure 14-30: Maximum IDD vs. Frequency (HS Mode, -40(cid:176) C to 85(cid:176) C).......................134 Figure 15-1: Load Conditions......................................140 Figure 15-2: External Clock Timing.............................141 Figure 15-3: CLKOUT and I/O Timing.........................142 Figure 15-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing.....................................................143 Figure 15-5: Timer0 External Clock Timings...............144 Figure 15-6: A/D Conversion Timing...........................146 Figure 16-1: Typical RC Oscillator Frequency vs. Temperature............................................147 Figure 16-2: Typical RC Oscillator Frequency vs. VDD..........................................................147 Figure 16-3: Typical RC Oscillator Frequency vs. VDD..........................................................147 DS30390D-page 168 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X LIST OF TABLES Table 11-6: A/D Converter Characteristics: PIC16C710/711-04 Table 1-1: PIC16C71X Family of Devices....................4 (Commercial, Industrial, Extended) Table 3-1: PIC16C710/71/711/715 Pinout PIC16C710/711-10 Description..................................................9 (Commercial, Industrial, Extended) Table 4-1: PIC16C710/71/711 Special Function PIC16C710/711-20 Register Summary....................................14 (Commercial, Industrial, Extended) Table 4-2: PIC16C715 Special Function Register PIC16LC710/711-04 Summary...................................................15 (Commercial, Industrial, Extended)...........99 Table 5-1: PORTA Functions.....................................26 Table 11-7: A/D Conversion Requirements...............100 Table 5-2: Summary of Registers Associated with Table 12-1: RC Oscillator Frequencies......................107 PORTA......................................................26 Table 12-2: Capacitor Selection for Crystal Table 5-3: PORTB Functions.....................................28 Oscillators...............................................108 Table 5-4: Summary of Registers Associated with Table 13-1: Cross Reference of Device Specs for PORTB......................................................29 Oscillator Configurations and Table 6-1: Registers Associated with Timer0.............35 Frequencies of Operation Table 7-1: TAD vs. Device Operating Frequencies, (Commercial Devices)............................112 PIC16C71..................................................41 Table 13-2: Clock Timing Requirements....................118 Table 7-2: TAD vs. Device Operating Frequencies, Table 13-3: CLKOUT and I/O Timing Requirements.119 PIC16C710/711, PIC16C715....................41 Table 13-4: Reset, Watchdog Timer, Oscillator Table 7-3: Registers/Bits Associated with A/D, Start-up Timer, Power-up Timer, PIC16C710/71/711....................................46 and Brown-out Reset Requirements.......120 Table 7-4: Registers/Bits Associated with A/D, Table 13-5: Timer0 Clock Requirements...................121 PIC16C715................................................46 Table 13-6: A/D Converter Characteristics: Table 8-1: Ceramic Resonators, PIC16C71...............49 PIC16C715-04 Table 8-2: Capacitor Selection For Crystal (Commercial, Industrial, Extended) Oscillator, PIC16C71.................................49 PIC16C715-10 Table 8-3: Ceramic Resonators, (Commercial, Industrial, Extended) PIC16C710/711/715..................................50 PIC16C715-20 Table 8-4: Capacitor Selection for Crystal (Commercial, Industrial, Extended)........122 Oscillator, PIC16C710/711/715.................50 Table 13-7: A/D Converter Characteristics: Table 8-5: Time-out in Various Situations, PIC16LC715-04 (Commercial, PIC16C71..................................................54 Industrial)................................................123 Table 8-6: Time-out in Various Situations, Table 13-8: A/D Conversion Requirements...............124 PIC16C710/711/715..................................54 Table 14-1: RC Oscillator Frequencies......................131 Table 8-7: Status Bits and Their Significance, Table 14-2: Capacitor Selection for Crystal PIC16C71..................................................55 Oscillators...............................................132 Table 8-8: Status Bits and Their Significance, Table 15-1: Cross Reference of Device Specs PIC16C710/711.........................................55 for Oscillator Configurations and Table 8-9: Status Bits and Their Significance, Frequencies of Operation PIC16C715................................................55 (Commercial Devices)............................135 Table 8-10: Reset Condition for Special Registers, Table 15-2: External Clock Timing Requirements.....141 PIC16C710/71/711....................................56 Table 15-3: CLKOUT and I/O Timing Requirements.142 Table 8-11: Reset Condition for Special Registers, Table 15-4: Reset, Watchdog Timer, Oscillator PIC16C715................................................56 Start-up Timer and Power-up Timer Table 8-12: Initialization Conditions For All Registers, Requirements.........................................143 PIC16C710/71/711....................................57 Table 15-5: Timer0 External Clock Requirements.....144 Table 8-13: Initialization Conditions for All Registers, Table 15-6: A/D Converter Characteristics................145 PIC16C715................................................58 Table 15-7: A/D Conversion Requirements...............146 Table 9-1: Opcode Field Descriptions........................69 Table 16-1: RC Oscillator Frequencies......................148 Table 9-2: PIC16CXX Instruction Set.........................70 Table 10-1: Development Tools From Microchip.........88 Table 11-1: Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices)...............................89 Table 11-2: External Clock Timing Requirements........95 Table 11-3: CLKOUT and I/O Timing Requirements....96 Table 11-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements.........97 Table 11-5: Timer0 External Clock Requirements.......98 (cid:211) 1997 Microchip Technology Inc. DS30390D-page 169

PIC16C71X NOTES: DS30390D-page 170 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X ON-LINE SUPPORT The procedure to connect will vary slightly from country to country. Please check with your local CompuServe Microchip provides two methods of on-line support. agent for details if you have a problem. CompuServe These are the Microchip BBS and the Microchip World service allow multiple users various baud rates Wide Web (WWW) site. depending on the local point of access. Use Microchip's Bulletin Board Service (BBS) to get The following connect procedure applies in most loca- current information and help about Microchip products. tions. Microchip provides the BBS communication channel for you to use in extending your technical staff with 1. Set your modem to 8-bit, No parity, and One stop microcontroller and memory experts. (8N1). This is not the normal CompuServe setting which is 7E1. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts 2. Dial your local CompuServe access number. the latest component data and software tool updates, 3. Depress the <Enter> key and a garbage string will provides technical help and embedded systems appear because CompuServe is expecting a 7E1 insights, and discusses how Microchip products pro- setting. vide project solutions. 4. Type +, depress the <Enter> key and “Host Name:” The web site, like the BBS, is used by Microchip as a will appear. means to make files and information easily available to 5. Type MCHIPBBS, depress the <Enter> key and you customers. To view the site, the user must have access will be connected to the Microchip BBS. to the Internet and a web browser, such as Netscape or In the United States, to find the CompuServe phone Microsoft Explorer. Files are also available for FTP number closest to you, set your modem to 7E1 and dial download from our FTP site. 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For each SIG, a Development Tools, Data Sheets, Application Notes, moderator monitors, scans, and approves or disap- User's Guides, Articles and Sample Programs. A vari- proves files submitted to the SIG. No executable files ety of Microchip specific business information is also are accepted from the user community in general to available, including listings of Microchip sales offices, limit the spread of computer viruses. distributors and factory representatives. Other data Systems Information and Upgrade Hot Line available for consideration is: The Systems Information and Upgrade Line provides • Latest Microchip Press Releases system users a listing of the latest versions of all of • Technical Support Section with Frequently Asked Microchip's development systems software products. Questions Plus, this line provides information on how customers • Design Tips can receive any currently available upgrade kits.The • Device Errata Hot Line Numbers are: • Job Postings 1-800-755-2345 for U.S. and most of Canada, and • Microchip Consultant Program Member Listing 1-602-786-7302 for the rest of the world. • Links to other useful web sites related to Microchip Products 970301 Connecting to the Microchip BBS Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks Connect worldwide to the Microchip BBS using either (cid:210) of Microchip Technology Incorporated in the U.S.A. and the Internet or the CompuServe communications net- other countries. FlexROM, MPLAB and fuzzyLAB, are work. trademarks and SQTP is a service mark of Microchip in Internet: the U.S.A. You can telnet or ftp to the Microchip BBS at the fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks address: mchipbbs.microchip.com of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark CompuServe Communications Network: and MS-DOS, Microsoft Windows are registered trade- When using the BBS via the Compuserve Network, marks of Microsoft Corporation. CompuServe is a regis- in most cases, a local call is your only expense. The tered trademark of CompuServe Incorporated. Microchip BBS connection does not use CompuServe All other trademarks mentioned herein are the property of membership services, therefore you do not need their respective companies. CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 171

PIC16C71X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16C71X Literature Number: DS30272A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30272A-page 172 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X PIC16C71X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. PART NO. -XX X /XX XXX Examples Pattern: QTP, SQTP, Code or Special Requirements a) PIC16C71 - 04/P 301 Package: JW = Windowed CERDIP Commercial Temp., SO = SOIC PDIP Package, 4 MHz, SP = Skinny plastic dip normal VDD limits, QTP P = PDIP pattern #301 SS = SSOP b) Temperature - = 0(cid:176) C to +70(cid:176) C Range: I = -40(cid:176) C to +85(cid:176) C E = -40(cid:176) C to +125(cid:176) C Frequency 04 = 200 kHz (PIC16C7X-04) Range: 04 = 4 MHz 10 = 10 MHz 20 = 20 MHz Device PIC16C7X :VDD range 4.0V to 6.0V PIC16C7XT :VDD range 4.0V to 6.0V (Tape/Reel) PIC16LC7X :VDD range 2.5V to 6.0V PIC16LC7XT :VDD range 2.5V to 6.0V (Tape/Reel) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1.Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. (cid:211) 1997 Microchip Technology Inc. DS30272A-page 173

PIC16C71X NOTES: DS30272A-page 174 (cid:211) 1997 Microchip Technology Inc.

PIC16C71X NOTES: (cid:211) 1997 Microchip Technology Inc. DS30272A-page 175

Note the following details of the code protection feature on PICmicro® MCUs. (cid:127) The PICmicro family meets the specifications contained in the Microchip Data Sheet. (cid:127) Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl- edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”. (cid:127) Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab, ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech- to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries. patents or other intellectual property rights arising from such dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, use or otherwise. Use of Microchip’s products as critical com- In-Circuit Serial Programming, ICSP, ICEPIC, microPort, ponents in life support systems is not authorized except with Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, express written approval by Microchip. No licenses are con- MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode veyed, implicitly or otherwise, under any intellectual property and Total Endurance are trademarks of Microchip Technology rights. Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc.

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