PIC16C63A/65B/73B/74B 8-Bit CMOS Microcontrollers with A/D Converter Devices included in this data sheet: PIC16C7X Peripheral Features: • PIC16C63A • PIC16C73B • Timer0: 8-bit timer/counter with 8-bit prescaler • PIC16C65B • PIC16C74B • Timer1: 16-bit timer/counter with prescaler can be incremented during SLEEP via external PIC16CXX Microcontroller Core Features: crystal/clock • Timer2: 8-bit timer/counter with 8-bit period • High performance RISC CPU register, prescaler and postscaler • Only 35 single word instructions to learn • Capture, Compare, PWM modules • All single cycle instructions except for program - Capture is 16-bit, max. resolution is 200 ns branches which are two cycle - Compare is 16-bit, max. resolution is 200 ns • Operating speed: DC - 20 MHz clock input - PWM max. resolution is 10-bit DC - 200 ns instruction cycle • 8-bit multichannel Analog-to-Digital converter • 4K x 14 words of Program Memory, • Synchronous Serial Port (SSP) with SPITM 192 x 8 bytes of Data Memory (RAM) andI2CTM • Interrupt capability • Universal Synchronous Asynchronous Receiver • Eight-level deep hardware stack Transmitter (USART/SCI) • Direct, indirect and relative addressing modes • Parallel Slave Port (PSP), 8-bits wide with • Power-on Reset (POR) external RD, WR and CS controls • Power-up Timer (PWRT) and Oscillator Start-up • Brown-out detection circuitry for Brown-out Reset Timer (OST) (BOR) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Pin Diagram: • Programmable code protection PDIP, Windowed CERDIP • Power-saving SLEEP mode • Selectable oscillator options MCLR/VPP 1 40 RB7 • Low power, high speed CMOS EPROM RA0/AN0 2 39 RB6 RA1/AN1 3 38 RB5 technology RA2/AN2 4 37 RB4 • Wide operating voltage range: 2.5V to 5.5V RA3/AN3/VREF 5 36 RB3 RA4/T0CKI 6 35 RB2 • High Sink/Source Current 25/25 mA RA5/SS/AN4 7 BB 34 RB1 RE0/RD/AN5 8 6574 33 RB0/INT • Commercial, Industrial and Automotive RE1/WR/AN6 9 CC 32 VDD RE2/CS/AN7 10 66 31 VSS temperature ranges VDD 11 C1C1 30 RD7/PSP7 • Low power consumption: OSC1/CLVKSINS 1123 PIPI 2298 RRDD65//PPSSPP65 - < 5 mA @ 5V, 4 MHz OSC2/CLKOUT 14 27 RD4/PSP4 RC0/T1OSO/T1CKI 15 26 RC7/RX/DT - 23 A typical @ 3V, 32 kHz RC1/T1OSI/CCP2 16 25 RC6/TX/CK RC2/CCP1 17 24 RC5/SDO - < 1.2 A typical standby current RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 I/O A/D RD1/PSP1 20 21 RD2/PSP2 Devices PSP Interrupts Pins Chan. PIC16C63A 22 - No 10 PIC16C65B 33 - Yes 11 PIC16C73B 22 5 No 11 PIC16C74B 33 8 Yes 12  1998-2013 Microchip Technology Inc. DS30605D-page 1

PIC16C63A/65B/73B/74B SDIP, SOIC, Windowed CERDIP MCLR/VPP • 1 28 RB7 RA0/AN0 2 27 RB6 RA1/AN1 3 26 RB5 RA2/AN2 4 AB 25 RB4 RA3/AN3/VREF 5 33 24 RB3 RA4/T0CKI 6 C6C7 23 RB2 RA5/SS/AN4 7 66 22 RB1 VSS 8 C1C1 21 RB0/INT OSOCS2C/C1L/CKLOKUINT 910 PIPI 2109 VVDSSD RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA 2 F P PLCC AN3/VREAN2AN1AN0R/VPP X/CKDODI/SDASP3SP2SP1SP0CK/SCLCP11OSI/CC RA3/RA2/RA1/RA0/MCLNCRB7RB6RB5RB4NC MTQQFFPP RC6/TRC5/SRC4/SRD3/PRD2/PRD1/PRD0/PRC3/SRC2/CRC1/TNC RC0O/TSRO1RRRCEOSEERA21S0C25/A/C//OW/1R4CSL///RDCSSTTK///L10/OAAAAVVKCCNUNNNNDSIKKNCTD756S4II 7891111111110234567186195PP204II21CC32211266231CC24446725544326BB42274128403333333333298765432109 RRRRVVRRRRRDSCBDDDDBBBSD032177654//////IRPPPPNSSSSXTPPPP/D7654T RRRRRCDDDDR74567/BR////PPPP0XRRR/SSSSVVI/NDPPPPBBBDSTTD4567123S 123456789111044124313PP4214II4115CC401611639176CC1838761937452036BB213522343333222222232109876543 NROOVVRRRRRSDCCEEEAASSSD021450CC//////12RCWTST//01SDSCCRCO///LLA/AAKASKKNNNINOION4756/UTT1CKI 1/T1OSI/CCP2RC2/CCP1RC3/SCK/SCLRD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP3RC4/SDI/SDARC5/SDORC6/TX/CKNC NCNCRB4RB5RB6RB7MCLR/VPPRA0/AN0RA1/AN1RA2/AN2RA3/AN3/VREF C R Key Features PIC® Mid-Range MCU Family Reference PIC16C63A PIC16C65B PIC16C73B PIC16C74B Manual (DS33023) Program Memory (EPROM) x 14 4K 4K 4K 4K Data Memory (Bytes) x 8 192 192 192 192 Pins 28 40 28 40 Parallel Slave Port — Yes — Yes Capture/Compare/PWM Modules 2 2 2 2 Timer Modules 3 3 3 3 A/D Channels — — 5 8 Serial Communication SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART In-Circuit Serial Programming Yes Yes Yes Yes Brown-out Reset Yes Yes Yes Yes Interrupt Sources 10 11 11 12 Packages 28-pin SDIP, SOIC, 40-pin PDIP; 28-pin SDIP, SOIC, 40-pin PDIP; SSOP, 44-pin PLCC, SSOP, 44-pin PLCC, Windowed CERDIP MQFP, TQFP, Windowed CERDIP MQFP, TQFP, Windowed CERDIP Windowed CERDIP DS30605D-page 2  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B Table of Contents 1.0 General Description......................................................................................................................................................................5 2.0 PIC16C63A/65B/73B/74B Device Varieties.................................................................................................................................7 3.0 Architectural Overview.................................................................................................................................................................9 4.0 Memory Organization.................................................................................................................................................................15 5.0 I/O Ports.....................................................................................................................................................................................29 6.0 Timer0 Module...........................................................................................................................................................................39 7.0 Timer1 Module...........................................................................................................................................................................43 8.0 Timer2 Module...........................................................................................................................................................................47 9.0 Capture/Compare/PWM Modules..............................................................................................................................................49 10.0 Synchronous Serial Port (SSP) Module.....................................................................................................................................55 11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................................65 12.0 Analog-to-Digital Converter (A/D) Module .................................................................................................................................79 13.0 Special Features of the CPU......................................................................................................................................................85 14.0 Instruction Set Summary............................................................................................................................................................99 15.0 Development Support...............................................................................................................................................................107 16.0 Electrical Characteristics..........................................................................................................................................................113 17.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................139 18.0 Packaging Information..............................................................................................................................................................153 Appendix A: Revision History ........................................................................................................................................................165 Appendix B: Device Differences.....................................................................................................................................................165 Appendix C: Device Migrations - PIC16C63/65A/73A/74APIC16C63A/65B/73B/74B.............................................................166 Appendix D: Migration from Baseline to Mid-Range Devices.........................................................................................................168 On-Line Support.................................................................................................................................................................................175 Reader Response..............................................................................................................................................................................176 Product Identification System............................................................................................................................................................177 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.  1998-2013 Microchip Technology Inc. DS30605D-page 3

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 4  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 1.0 GENERAL DESCRIPTION A highly reliable Watchdog Timer (WDT), with its own on-chip RC oscillator, provides protection against soft- The PIC16C63A/65B/73B/74B devices are low cost, ware lockup, and also provides one way of waking the high performance, CMOS, fully-static, 8-bit micro- device from SLEEP. controllers in the PIC16CXX mid-range family. A UV erasable CERDIP packaged version is ideal for All PIC® microcontrollers employ an advanced RISC code development, while the cost effective One-Time- architecture. The PIC16CXX microcontroller family has Programmable (OTP) version is suitable for production enhanced core features, eight-level deep stack and in any volume. multiple internal and external interrupt sources. The The PIC16C63A/65B/73B/74B devices fit nicely in separate instruction and data buses of the Harvard many applications ranging from security and remote architecture allow a 14-bit wide instruction word with sensors to appliance control and automotive. The the separate 8-bit wide data. The two stage instruction EPROM technology makes customization of applica- pipeline allows all instructions to execute in a single tion programs (transmitter codes, motor speeds, cycle, except for program branches, which require two receiver frequencies, etc.) extremely fast and con- cycles. A total of 35 instructions (reduced instruction venient. The small footprint packages make this micro- set) are available. Additionally, a large register set controller series perfect for all applications with space gives some of the architectural innovations used to limitations. Low cost, low power, high performance, achieve a very high performance. ease of use and I/O flexibility make the PIC16C63A/ The PIC16C63A/73B devices have 22 I/O pins. The 65B/73B/74B devices very versatile, even in areas PIC16C65B/74B devices have 33 I/O pins. Each where no microcontroller use has been considered device has 192 bytes of RAM. In addition, several before (e.g., timer functions, serial communication, peripheral features are available, including: three timer/ capture and compare, PWM functions and coprocessor counters, two Capture/Compare/PWM modules, and applications). two serial ports. The Synchronous Serial Port (SSP) can be configured as either a 3-wire Serial Peripheral 1.1 Family and Upward Compatibility Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Universal Synchronous Asynchronous Users familiar with the PIC16C5X microcontroller fam- Receiver Transmitter (USART) is also known as the ily will realize that this is an enhanced version of the Serial Communications Interface or SCI. Also, a 5- PIC16C5X architecture. Please refer to Appendix A for channel high speed 8-bit A/D is provided on the a detailed list of enhancements. Code written for the PIC16C73B, while the PIC16C74B offers 8 channels. PIC16C5X can be easily ported to the PIC16CXX fam- The 8-bit resolution is ideally suited for applications ily of devices (Appendix B). requiring low cost analog interface, e.g., thermostat 1.2 Development Support control, pressure sensing, etc. The PIC16C63A/65B/73B/74B devices have special PIC® devices are supported by the complete line of features to reduce external components, thus reducing Microchip Development tools. cost, enhancing system reliability and reducing power Please refer to Section15.0 for more details about consumption. There are four oscillator options, of which Microchip’s development tools. the single pin RC oscillator provides a low cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for high speed crys- tals. The SLEEP (power-down) feature provides a power-saving mode. The user can wake-up the chip from SLEEP through several external and internal interrupts and RESETS.  1998-2013 Microchip Technology Inc. DS30605D-page 5

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 6  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 2.0 PIC16C63A/65B/73B/74B DEVICE 2.3 Quick-Turnaround-Production VARIETIES (QTP) Devices A variety of frequency ranges and packaging options Microchip offers a QTP Programming Service for fac- are available. Depending on application and production tory production orders. This service is made available requirements, the proper device option can be selected for users who choose not to program a medium to high using the information in the PIC16C63A/65B/73B/74B quantity of units and whose code patterns have stabi- Product Identification System section at the end of this lized. The devices are identical to the OTP devices but data sheet. When placing orders, please use that page with all EPROM locations and configuration options of the data sheet to specify the correct part number. already programmed by the factory. Certain code and prototype verification procedures apply before produc- For the PIC16C7X family, there are two device “types” tion shipments are available. Please contact your local as indicated in the device number: Microchip Technology sales office for more details. 1. C, as in PIC16C74. These devices have EPROM type memory and operate over the 2.4 Serialized Quick-Turnaround standard voltage range. Production (SQTPSM) Devices 2. LC, as in PIC16LC74. These devices have Microchip offers a unique programming service where EPROM type memory and operate over an a few user-defined locations in each device are pro- extended voltage range. grammed with different serial numbers. The serial num- 2.1 UV Erasable Devices bers may be random, pseudo-random or sequential. Serial programming allows each device to have a The UV erasable version, offered in windowed CERDIP unique number, which can serve as an entry code, packages, is optimal for prototype development and password or ID number. pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. Microchip's PICSTART Plus and PROMATEII programmers both support programming of the PIC16C63A/65B/73B/74B. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.  1998-2013 Microchip Technology Inc. DS30605D-page 7

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 8  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 3.0 ARCHITECTURAL OVERVIEW PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. The high performance of the PIC16CXX family can be It performs arithmetic and Boolean functions between attributed to a number of architectural features com- the data in the working register and any register file. monly found in RISC microprocessors. To begin with, The ALU is 8-bits wide and capable of addition, sub- the PIC16CXX uses a Harvard architecture, in which traction, shift and logical operations. Unless otherwise program and data are accessed from separate memo- mentioned, arithmetic operations are two's comple- ries using separate buses. This improves bandwidth ment in nature. In two-operand instructions, typically over traditional von Neumann architecture, in which one operand is the working register (W register). The program and data are fetched from the same memory other operand is a file register or an immediate con- using the same bus. Separating program and data stant. In single operand instructions, the operand is buses further allows instructions to be sized differently either the W register or a file register. than the 8-bit wide data word. Instruction opcodes are 14-bits wide, making it possible to have all single word The W register is an 8-bit working register used for ALU instructions. A 14-bit wide program memory access operations. It is not an addressable register. bus fetches a 14-bit instruction in a single cycle. A Depending on the instruction executed, the ALU may two-stage pipeline overlaps fetch and execution of affect the values of the Carry (C), Digit Carry (DC), and instructions (Example3-1). Consequently, most Zero (Z) bits in the STATUS register. The C and DC bits instructions execute in a single cycle (200 ns@ operate as a borrow bit and a digit borrow out bit, 20 MHz) except for program branches. respectively, in subtraction. See the SUBLW and SUBWF All devices covered by this data sheet contain instructions for examples. 4Kx14-bit program memory and 192 x 8-bit data memory. The PIC16CXX can directly, or indirectly, address its register files or data memory. All Special Function Reg- isters, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXX simple yet efficient. In addition, the learning curve is reduced significantly.  1998-2013 Microchip Technology Inc. DS30605D-page 9

PIC16C63A/65B/73B/74B FIGURE 3-1: PIC16C63A/65B/73B/74B BLOCK DIAGRAM 13 Data Bus 8 PORTA Program Counter RA0/AN0(2) EPROM RA1/AN1(2) Program RA2/AN2(2) Memory 8 Level Stack RAM RA3/AN3/VREF(2) (13-bit) File RA4/T0CKI Registers RA5/SS/AN4(2) Program Bus 14 RAM Addr(1) 9 PORTB Instruction reg Addr MUX RB0/INT Direct Addr 7 Indirect 8 Addr RB7:RB1 FSR reg STATUS reg PORTC 8 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 Power-up 3 MUX RC3/SCK/SCL Timer RC4/SDI/SDA Instruction Oscillator RC5/SDO Decode & Start-up Timer RC6/TX/CK ALU Control RC7/RX/DT Power-on Reset 8 PORTD(3) Timing Watchdog RD0/PSP0 Generation Timer W reg RD1/PSP1 OSC1/CLKIN Brown-out RD2/PSP2 OSC2/CLKOUT Reset RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 Parallel Slave Port RD7/PSP7 MCLR VDD, VSS (3) PORTE(3) RE0/RD/AN5(2,3) Timer0 Timer1 Timer2 A/D(2) RE1/WR/AN6(2,3) RE2/CS/AN7(2,3) Synchronous CCP1 CCP2 USART Serial Port Note 1: Higher order bits are from the STATUS register. 2: A/D is not available on the PIC16C63A/65B. 3: PSP and Ports D and E are not available on PIC16C63A/73B. DS30605D-page 10  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 3-1: PIC16C63A/73B PINOUT DESCRIPTION DIP SOIC I/O/P Buffer Pin Name Description Pin# Pin# Type Type OSC1/CLKIN 9 9 I ST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 I/P ST Master clear (RESET) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0/AN0(4) 2 2 I/O TTL RA0 can also be analog input 0(4). RA1/AN1(4) 3 3 I/O TTL RA1 can also be analog input 1(4). RA2/AN2(4) 4 4 I/O TTL RA2 can also be analog input 2(4). RA3/AN3/VREF(4) 5 5 I/O TTL RA3 can also be analog input 3 or analog reference voltage(4). RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/SS/AN4(4) 7 7 I/O TTL RA5 can also be analog input 4(4) or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3 24 24 I/O TTL RB4 25 25 I/O TTL Interrupt-on-change pin. RB5 26 26 I/O TTL Interrupt-on-change pin. RB6 27 27 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming clock. RB7 28 28 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: A/D module is not available in the PIC16C63A.  1998-2013 Microchip Technology Inc. DS30605D-page 11

PIC16C63A/65B/73B/74B TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION TQFP DIP PLCC I/O/P Buffer Pin Name MQFP Description Pin# Pin# Type Type Pin# OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input. OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master clear (RESET) input or programming voltage input. This pin is an active low RESET to the device. PORTA is a bi-directional I/O port. RA0/AN0(5) 2 3 19 I/O TTL RA0 can also be analog input 0(5). RA1/AN1(5) 3 4 20 I/O TTL RA1 can also be analog input 1(5). RA2/AN2(5) 4 5 21 I/O TTL RA2 can also be analog input 2(5). RA3/AN3/VREF(5) 5 6 22 I/O TTL RA3 can also be analog input 3 or analog reference voltage(5). RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5/SS/AN4(5) 7 8 24 I/O TTL RA5 can also be analog input 4(5) or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3 36 39 11 I/O TTL RB4 37 41 14 I/O TTL Interrupt-on-change pin. RB5 38 42 15 I/O TTL Interrupt-on-change pin. RB6 39 43 16 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming clock. RB7 40 44 17 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming data. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 5: A/D is not available on the PIC16C65B. DS30605D-page 12  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION (CONTINUED) TQFP DIP PLCC I/O/P Buffer Pin Name MQFP Description Pin# Pin# Type Type Pin# PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus. RD0/PSP0 19 21 38 I/O ST/TTL(3) RD1/PSP1 20 22 39 I/O ST/TTL(3) RD2/PSP2 21 23 40 I/O ST/TTL(3) RD3/PSP3 22 24 41 I/O ST/TTL(3) RD4/PSP4 27 30 2 I/O ST/TTL(3) RD5/PSP5 28 31 3 I/O ST/TTL(3) RD6/PSP6 29 32 4 I/O ST/TTL(3) RD7/PSP7 30 33 5 I/O ST/TTL(3) PORTE is a bi-directional I/O port. RE0/RD/AN5(5) 8 9 25 I/O ST/TTL(3) RE0 can also be read control for the parallel slave port, or analog input 5(5). RE1/WR/AN6(5) 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave port, or analog input 6(5). RE2/CS/AN7(5) 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave port, or analog input 7(5). VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins. VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins. NC — 1,17,28, 12,13, — These pins are not internally connected. These pins should 40 33,34 be left unconnected. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 5: A/D is not available on the PIC16C65B.  1998-2013 Microchip Technology Inc. DS30605D-page 13

PIC16C63A/65B/73B/74B 3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining Cycle An “Instruction Cycle” consists of four Q cycles (Q1, The clock input (from OSC1) is internally divided by Q2, Q3 and Q4). The instruction fetch and execute are four to generate four non-overlapping quadrature pipelined such that fetch takes one instruction cycle, clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro- while decode and execute takes another instruction gram counter (PC) is incremented every Q1, the cycle. However, due to the pipelining, each instruction instruction is fetched from the program memory and effectively executes in one cycle. If an instruction latched into the instruction register in Q4. The instruc- causes the program counter to change (e.g., GOTO), tion is decoded and executed during the following Q1 then two cycles are required to complete the instruction through Q4. The clocks and instruction execution flow (Example3-1). is shown in Figure3-2. A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW TCY0 TCY1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS30605D-page 14  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 4.0 MEMORY ORGANIZATION 4.2 Data Memory Organization The data memory is partitioned into multiple banks 4.1 Program Memory Organization which contain the General Purpose Registers (GPR) The PIC16C63A/65B/73B/74B has a 13-bit program and the Special Function Registers (SFR). Bits RP1 counter capable of addressing an 8K x 14 program and RP0 are the bank select bits. memory space. All devices covered by this data sheet RP1:RP0 (STATUS<6:5>) have 4K x 14 bits of program memory. The address = 00  Bank0 range is 0000h - 0FFFh for all devices. = 01  Bank1 Accessing a location above 0FFFh will cause a wrap- = 10  Bank2 around. = 11  Bank3 The RESET vector is at 0000h and the interrupt vector Each bank extends up to 7Fh (128 bytes). The lower is at 0004h. locations of each bank are reserved for the SFRs. Above the SFRs are GPRs, implemented as static FIGURE 4-1: PIC16C63A/65B/73B/74B RAM. PROGRAM MEMORY MAP All implemented banks contain SFRs. Frequently used AND STACK SFRs from one bank may be mirrored in another bank for code reduction and quicker access. PC<12:0> Note: Maintain the IRP and RP1 bits clear in CALL,RETURN these devices. 13 RETFIE,RETLW 4.2.1 GENERAL PURPOSE REGISTER Stack Level 1 FILE The register file can be accessed either directly, or indi- rectly, through the File Select Register (FSR) Stack Level 8 (Section4.5). RESET Vector 0000h y Interrupt Vector 0004h r o me On-chip Program 0005h ec Ma Memory (Page 0) p r S e 07FFh s U On-chip Program 0800h Memory (Page 1) 0FFFh 1000h 1FFFh  1998-2013 Microchip Technology Inc. DS30605D-page 15

PIC16C63A/65B/73B/74B FIGURE 4-2: REGISTER FILE MAP 4.2.2 SPECIAL FUNCTION REGISTERS File File The Special Function Registers are registers used by Address Address the CPU and Peripheral Modules for controlling the 00h INDF(1) INDF(1) 80h desired operation of the device. These registers are implemented as static RAM. 01h TMR0 OPTION_REG 81h 02h PCL PCL 82h The Special Function Registers can be classified into two sets (core and peripheral). Those registers associ- 03h STATUS STATUS 83h ated with the “core” functions are described in this sec- 04h FSR FSR 84h tion, and those related to the operation of the peripheral 05h PORTA TRISA 85h features are described in the section of that peripheral 06h PORTB TRISB 86h feature. 07h PORTC TRISC 87h 08h PORTD(2) TRISD(2) 88h 09h PORTE(2) TRISE(2) 89h 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Dh PIR2 PIE2 8Dh 0Eh TMR1L PCON 8Eh 0Fh TMR1H 8Fh 10h T1CON 90h 11h TMR2 91h 12h T2CON PR2 92h 13h SSPBUF SSPADD 93h 14h SSPCON SSPSTAT 94h 15h CCPR1L 95h 16h CCPR1H 96h 17h CCP1CON 97h 18h RCSTA TXSTA 98h 19h TXREG SPBRG 99h 1Ah RCREG 9Ah 1Bh CCPR2L 9Bh 1Ch CCPR2H 9Ch 1Dh CCP2CON 9Dh 1Eh ADRES(3) 9Eh 1Fh ADCON0(3) ADCON1(3) 9Fh 20h A0h General General Purpose Purpose Register Register 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as ’0’. Note 1: Not a physical register. 2: These registers are not implemented on the PIC16C63A/73B, read as '0'. 3: These registers are not implemented on the PIC16C63A/65B, read as '0'. DS30605D-page 16  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS(3) Bank 0 00h INDF(4) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h PCL(4) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS(4) IRP(2) RP1(2) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h FSR(4) Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h PORTD(5) PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h PORTE(5) — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Ah PCLATH(1,4) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh INTCON(4) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(5) ADIF(6) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Data register 0000 0000 0000 0000 1Ah RCREG USART Receive Data register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 1Eh ADRES(6) A/D Result register xxxx xxxx uuuu uuuu 1Fh ADCON0(6) ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>. 2: The IRP and RP1 bits are reserved; always maintain these bits clear. 3: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 4: These registers can be addressed from either bank. 5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and registers clear. 6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear.  1998-2013 Microchip Technology Inc. DS30605D-page 17

PIC16C63A/65B/73B/74B TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR RESETS(3) Bank 1 80h INDF(4) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL(4) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h STATUS(4) IRP(2) RP1(2) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h FSR(4) Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction register 1111 1111 1111 1111 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 88h TRISD(5) PORTD Data Direction register 1111 1111 1111 1111 89h TRISE(5) IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 8Ah PCLATH(1,4) — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh INTCON(4) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(5) ADIE(6) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1(6) — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>. 2: The IRP and RP1 bits are reserved; always maintain these bits clear. 3: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 4: These registers can be addressed from either bank. 5: PORTD, PORTE and the parallel slave port are not implemented on the PIC16C63A/73B; always maintain these bits and registers clear. 6: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits and registers clear. DS30605D-page 18  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 4.2.2.1 STATUS Register It is recommended that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS regis- The STATUS register, shown in Register4-1, contains ter. These instructions do not affect the Z, C or DC bits the arithmetic status of the ALU, the RESET status and in the STATUS register. For other instructions which do the bank select bits for data memory. not affect status bits, see the "Instruction Set Sum- The STATUS register can be the destination for any mary." instruction, as with any other register. If the STATUS reg- Note 1: These devices do not use bits IRP and ister is the destination for an instruction that affects the Z, RP1 (STATUS<7:6>), maintain these bits DC or C bits, then the write to these three bits is disabled. clear to ensure upward compatibility with These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. future products. Therefore, the result of an instruction with the STATUS 2: The C and DC bits operate as borrow and register as destination may be different than intended. digit borrow bits, respectively, in subtrac- For example, CLRF STATUS will clear the upper three tion. See the SUBLW and SUBWF instruc- bits and set the Z bit. This leaves the STATUS register tions for examples. as 000u u1uu (where u = unchanged). REGISTER 4-1: STATUS REGISTER (ADDRESS 03h, 83h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP(1) RP1(1) RP0 TO PD Z DC C(2) bit 7 bit 0 bit 7 IRP(1): Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5 RP1(1):RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C(2): Carry/borrow bit (ADDWF,ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note 1: Maintain the IRP and RP1 bits clear. 2: For borrow and digit borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF,RLF) instruc- tions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 19

PIC16C63A/65B/73B/74B 4.2.2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for The OPTION_REG register is a readable and writable the TMR0 register, assign the prescaler to register, which contains various control bits to configure the watchdog timer. the TMR0/WDT prescaler, the external INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: OPTION_REG REGISTER (ADDRESS 81h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30605D-page 20  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 4.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON register is a readable and writable regis- condition occurs, regardless of the state of ter, which contains various enable and flag bits for the its corresponding enable bit, or the global TMR0 register overflow, RB Port change and external enable bit, GIE (INTCON<7>). User soft- RB0/INT pin interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 4-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state(1) 0 = None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will exist until PORTB is read. After reading PORTB, the RBIF flag bit can be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 21

PIC16C63A/65B/73B/74B 4.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to This register contains the individual enable bits for the enable any peripheral interrupt. peripheral interrupts. REGISTER 4-4: PIE1 REGISTER (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE(2): A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented; always maintain this bit clear. 2: PIC16C63A/65B devices do not have an A/D implemented; always maintain this bit clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30605D-page 22  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 4.2.2.5 PIR1 Register Note: Interrupt flag bits are set when an interrupt This register contains the individual flag bits for the condition occurs, regardless of the state of peripheral interrupts. its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 4-5: PIR1 REGISTER (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF(2): A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (clear by reading RCREG) 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (clear by writing to TXREG) 0 = The USART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PIC16C63A/73B devices do not have a parallel slave port implemented. This bit loca- tion is reserved on these devices. 2: PIC16C63A/65B devices do not have an A/D implemented. This bit location is reserved on these devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 23

PIC16C63A/65B/73B/74B 4.2.2.6 PIE2 Register This register contains the individual enable bit for the CCP2 peripheral interrupt. REGISTER 4-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IE bit 7 bit 0 bit 7-1 Unimplemented: Read as '0' bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown 4.2.2.7 PIR2 Register Note: Interrupt flag bits are set when an interrupt This register contains the CCP2 interrupt flag bit. condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. REGISTER 4-7: PIR2 REGISTER (ADDRESS 0Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IF bit 7 bit 0 bit 7-1 Unimplemented: Read as '0' bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30605D-page 24  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 4.2.2.8 PCON Register Note: BOR is unknown on POR. It must be set by The Power Control (PCON) register contains flag bits the user and checked on subsequent to allow differentiation between a Power-on Reset RESETS to see if BOR is clear, indicating (POR), a Brown-out Reset (BOR), a Watchdog Reset a brown-out has occurred. The BOR status (WDT) and an external MCLR Reset. bit is a “don't care” and is not predictable if the brown-out circuit is disabled (by clear- ing the BODEN bit in the configuration word). REGISTER 4-8: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR bit 7 bit 0 bit 7-2 Unimplemented: Read as '0' bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 25

PIC16C63A/65B/73B/74B 4.3 PCL and PCLATH Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and 2: There are no instructions/mnemonics writable register. The upper bits (PC<12:8>) are not called PUSH or POP. These are actions readable, but are indirectly writable through the that occur from the execution of the PCLATH register. On any RESET, the upper bits of the CALL, RETURN, RETLW, and RETFIE PC will be cleared. Figure4-3 shows the two situations instructions, or the vectoring to an inter- for the loading of the PC. The upper example in the fig- rupt address. ure shows how the PC is loaded on a write to PCL 4.4 Program Memory Paging (PCLATH<4:0>  PCH). The lower example in the fig- ure shows how the PC is loaded during a CALL or GOTO PIC16CXX devices are capable of addressing a contin- instruction (PCLATH<4:3>  PCH). uous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to FIGURE 4-3: LOADING OF PC IN allow branching within any 2K program memory page. DIFFERENT SITUATIONS When executing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must PCH PCL ensure that the page select bits are programmed, so 12 8 7 0 Instruction with that the desired program memory page is addressed. If PC PCL as Destination a return from a CALL instruction (or interrupt) is exe- PCLATH<4:0> 8 cuted, the entire 13-bit PC is popped from the stack. 5 ALU Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the PCLATH address from the stack). PCH PCL Note 1: The contents of PCLATH are unchanged 12 11 10 8 7 0 after a return or RETFIE instruction is PC GOTO,CALL executed. The user must set up PCLATH for any subsequent CALL’s or GOTO’s PCLATH<4:3> 11 2 Opcode <10:0> 2: PCLATH<4> is not used in these PIC® devices. The use of PCLATH<4> as a PCLATH general purpose read/write bit is not rec- ommended, since this may affect upward compatibility with future products. 4.3.1 COMPUTED GOTO Example4-1 shows the calling of a subroutine in A computed GOTO is accomplished by adding an offset page1 of the program memory. This example assumes to the program counter (ADDWF PCL). When doing a that PCLATH is saved and restored by the Interrupt table read using a computed GOTO method, care Service Routine (if interrupts are used). should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the EXAMPLE 4-1: CALL OF A SUBROUTINE application note “Implementing a Table Read" (AN556). IN PAGE 1 FROM PAGE 0 4.3.2 STACK ORG 0x500 BSF PCLATH,3 ;Select page 1 (800h-FFFh) The PIC16CXX family has an 8-level deep x 13-bit wide CALL SUB1_P1 ;Call subroutine in hardware stack. The stack space is not part of either : ;page 1 (800h-FFFh) program or data space and the stack pointer is not : ORG 0x900 ;page 1 (800h-FFFh) readable or writable. The PC is PUSHed onto the stack SUB1_P1 when a CALL instruction is executed, or an interrupt : ;called subroutine causes a branch. The stack is POPed in the event of a : ;page 1 (800h-FFFh) RETURN,RETLW or a RETFIE instruction execution. : PCLATH is not affected by a PUSH or POP operation. RETURN ;return to Call subroutine The stack operates as a circular buffer. This means that ;in page 0 (000h-7FFh) after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS30605D-page 26  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 4.5 Indirect Addressing, INDF and EXAMPLE 4-2: INDIRECT ADDRESSING FSR Registers movlw 0x20 ;initialize pointer movwf FSR ;to RAM The INDF register is not a physical register. Addressing NEXT clrf INDF ;clear INDF register the INDF register will cause indirect addressing. incf FSR,F ;inc pointer Indirect addressing is possible by using the INDF reg- btfss FSR,4 ;all done? ister. Any instruction using the INDF register actually goto NEXT ;no clear next accesses the register pointed to by the File Select Reg- CONTINUE : ;yes continue ister, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits Note: Maintain the IRP and RP1 bits clear. may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure4-4. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example4-2. FIGURE 4-4: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 from opcode 0 IRP 7 FSR register 0 0 0 bank select location select bank select location select 00 01 10 11 00h 80h 100h 180h not used Data Memory 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register file map detail, see Figure4-2. 2: Shaded portions are not implemented; maintain the IRP and RP1 bits clear.  1998-2013 Microchip Technology Inc. DS30605D-page 27

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 28  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 5.0 I/O PORTS FIGURE 5-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the Data Bus device. In general, when a peripheral is enabled, that D Q pin may not be used as a general purpose I/O pin. VDD WR 5.1 PORTA and TRISA Registers Port CK Q P PORTA is a 6-bit latch. Data Latch The RA4/T0CKI pin is a Schmitt Trigger input and an N I/O pin(1) D Q open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have WR data direction bits (TRIS registers), which can config- TRIS CK Q VSS ure these pins as output or input. Analog TRIS Latch Input Setting a TRISA register bit puts the corresponding out- mode put driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin(s). RD TRIS TTL Input Reading the PORTA register reads the status of the Buffer pins, whereas writing to it will write to the port latch. All Q D write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port EN data latch. Pin RA4 is multiplexed with the Timer0 module clock RD Port input to become the RA4/T0CKI pin. On the PIC16C73B/74B, PORTA pins are multiplexed To A/D Converter with analog inputs and analog VREF input. The opera- tion of each pin is selected by clearing/setting the con- trol bits in the ADCON1 register (A/D Control Note 1: I/O pins have protection diodes to VDD and VSS. Register1). Note: On all RESETS, pins with analog functions FIGURE 5-2: BLOCK DIAGRAM OF are configured as analog and digital inputs. RA4/T0CKI PIN The TRISA register controls the direction of the RA Data pins, even when they are being used as analog inputs. Bus D Q The user must ensure the bits in the TRISA register are WR maintained set when using them as analog inputs. Port CK Q I/O pin(1) N Data Latch EXAMPLE 5-1: INITIALIZING PORTA (PIC16C73B/74B) D Q VSS WR BCF STATUS, RP0 ; TRIS CK Q Schmitt CLRF PORTA ; Initialize PORTA by Trigger ; clearing output TRIS Latch Input ; data latches Buffer BSF STATUS, RP0 ; Select Bank 1 MOVLW 0x06 ; Configure all pins RD TRIS MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data Q D ; direction MOVWF TRISA ; Set RA<3:0> as inputs ENEN ; RA<5:4> as outputs RD Port ; TRISA<7:6> are always ; read as '0'. TMR0 Clock Input Note 1: I/O pins have protection diodes to VDD and VSS.  1998-2013 Microchip Technology Inc. DS30605D-page 29

PIC16C63A/65B/73B/74B TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0(1) bit0 TTL Digital input/output or analog input. RA1/AN1(1) bit1 TTL Digital input/output or analog input. RA2/AN2(1) bit2 TTL Digital input/output or analog input. RA3/AN3/VREF(1) bit3 TTL Digital input/output or analog input or VREF. Digital input/output or external clock input for Timer0. RA4/T0CKI bit4 ST Output is open drain type. RA5/SS/AN4(1) bit5 TTL Input/output or slave select input for synchronous serial port or analog input. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented; maintain this register clear. TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 9Fh ADCON1(1) — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: The A/D is not implemented on the PIC16C63A/65B. Pins will operate as digital I/O only. ADCON1 is not implemented; maintain this register clear. DS30605D-page 30  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 5.2 PORTB and TRISB Registers This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the PORTB is an 8-bit wide, bi-directional port. The corre- interrupt in the following manner: sponding data direction register is TRISB. Setting a bit a) Any read or write of PORTB. This will end the in the TRISB register puts the corresponding output mismatch condition. driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch b) Clear flag bit RBIF. on the selected pin(s). A mismatch condition will continue to set flag bit RBIF. Each of the PORTB pins has a weak internal pull-up. A Reading PORTB will end the mismatch condition, and single control bit can turn on all the pull-ups. This is per- allow flag bit RBIF to be cleared. formed by clearing bit RBPU (OPTION_REG<7>). The This interrupt-on-mismatch feature, together with soft- weak pull-up is automatically turned off when the port ware configurable pull-ups on these four pins, allow pin is configured as an output. The pull-ups are dis- easy interface to a keypad and make it possible for abled on a Power-on Reset. wake-up on key depression. Refer to the Embedded Control Handbook, “Implementing Wake-up on Key FIGURE 5-3: BLOCK DIAGRAM OF Stroke” (AN552). RB3:RB0 PINS The interrupt-on-change feature is recommended for wake-up on key depression operation and operations VDD RBPU(2) where PORTB is only used for the interrupt-on-change Weak P Pull-up feature. Polling of PORTB is not recommended while Data Latch using the interrupt-on-change feature. Data Bus D Q RB0/INT is an external interrupt input pin and is config- WR Port CK I/O pin(1) ured using the INTEDG bit (OPTION_REG<6>). RB0/INT is discussed in detail in Section13.5.1. TRIS Latch D Q TTL WR TRIS Input FIGURE 5-4: BLOCK DIAGRAM OF CK Buffer RB7:RB4 PINS VDD RBPU(2) Weak RD TRIS P Pull-up Data Latch Q D Data Bus D Q RD Port EN WR Port I/O pin(1) CK TRIS Latch RB0/INT D Q Schmitt Trigger RD Port Buffer WR TRIS CK TInTpLut Buffer ST Note 1: I/O pins have diode protection to VDD and VSS. Buffer 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). RD TRIS Latch Q D Four of PORTB’s pins, RB7:RB4, have an interrupt-on-change feature. Only pins configured as RD Port EN Q1 inputs can cause this interrupt to occur (i.e., any Set RBIF RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the value latched on the From other Q D RB7:RB4 pins RD Port last read of PORTB. The “mismatch” outputs of EN RB7:RB4 are OR’d together to generate the RB Port Q3 Change Interrupt with flag bit RBIF (INTCON<0>). RB7:RB6 in Serial Programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).  1998-2013 Microchip Technology Inc. DS30605D-page 31

PIC16C63A/65B/73B/74B TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB PORTB Data Direction register 1111 1111 1111 1111 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30605D-page 32  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 5.3 PORTC and TRISC Registers FIGURE 5-5: PORTC BLOCK DIAGRAM PORTC is an 8-bit bi-directional port. Each pin is indi- PORT/PERIPHERAL Select(2) vidually configurable as an input or output through the TRISC register. PORTC is multiplexed with several Peripheral Data Out peripheral functions (Table5-5). PORTC pins have Data Bus 0 VDD D Q Schmitt Trigger input buffers. WR P Port CK Q 1 When enabling peripheral functions, care should be Data Latch taken in defining TRIS bits for each PORTC pin. Some I/O pin(1) peripherals override the TRIS bit to make a pin an out- D Q WR put, while other peripherals override the TRIS bit to TRIS make a pin an input. Since the TRIS bit override is in CK Q N effect while the peripheral is enabled, read-modify-write TRIS Latch instructions (BSF, BCF, XORWF) with TRISC as des- VSS tination should be avoided. The user should refer to the Schmitt corresponding peripheral section for the correct TRIS RD TRIS Trigger bit settings. Peripheral OE(3) Q D EN RD Port Peripheral Input Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. TABLE 5-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL bit3 ST RC3 can also be the Synchronous Serial Clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port Data output. RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART Synchronous Clock. RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive, or USART Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged  1998-2013 Microchip Technology Inc. DS30605D-page 33

PIC16C63A/65B/73B/74B 5.4 PORTD and TRISD Registers FIGURE 5-6: PORTD BLOCK DIAGRAM Note: The PIC16C63A and PIC16C73B do not Data Bus provide PORTD. The PORTD and TRISD D Q registers are not implemented. WR I/O pin(1) Port CK PORTD is an 8-bit port with Schmitt Trigger input buff- Data Latch ers. Each pin is individually configured as an input or output. D Q PORTD can be configured as an 8-bit wide micropro- WR TRIS cessor port (parallel slave port) by setting control bit CK Schmitt Trigger PSPMODE (TRISE<4>). In this mode, the input buffers TRIS Latch Input are TTL. Buffer RD TRIS Q D ENEN RD Port Note 1:I/O pins have protection diodes to VDD and VSS. TABLE 5-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0 RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1 RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2 RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3 RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4 RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5 RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6 RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7 Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode. TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD. DS30605D-page 34  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 5.5 PORTE and TRISE Register FIGURE 5-7: PORTE BLOCK DIAGRAM Data Note 1: The PIC16C63A and PIC16C73B do not Bus D Q provide PORTE. The PORTE and TRISE WR I/O pin(1) registers are not implemented. Port CK 2: The PIC16C63A/65B does not provide an Data Latch A/D module. A/D functions are not imple- mented. D Q WR PORTE has three pins: RE0/RD/AN5, RE1/WR/AN6 TRIS Schmitt CK and RE2/CS/AN7, which are individually configured as Trigger inputs or outputs. These pins have Schmitt Trigger TRIS Latch Input Buffer input buffers. I/O PORTE becomes control inputs for the micropro- RD TRIS cessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital Q D inputs) and that register ADCON1 is configured for dig- ital I/O. In this mode, the input buffers are TTL. ENEN RD Port Register5-1 shows the TRISE register, which also con- trols the parallel slave port operation. PORTE pins may be multiplexed with analog inputs Note 1:I/O pins have protection diodes to VDD and VSS. (PIC16C74B only). The operation of these pins is selected by control bits in the ADCON1 register. When selected as an analog input, these pins will read as '0's. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, these pins are con- figured as analog inputs and read as ‘0’s. TABLE 5-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD/AN5 bit0 ST/TTL(1) Input/output port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Idle 0 = Read operation. Contents of PORTD register is output to PORTD I/O pins (if chip selected). RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Idle 0 = Write operation. Value of PORTD I/O pins is latched into PORTD register (if chip selected). RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in Parallel Slave Port mode or analog input: CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.  1998-2013 Microchip Technology Inc. DS30605D-page 35

PIC16C63A/65B/73B/74B REGISTER 5-1: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode bit 3 Unimplemented: Read as '0' bit 2 TRISE2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output bit 1 TRISE1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0 TRISE0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE. DS30605D-page 36  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 5.6 Parallel Slave Port (PSP) When not in PSP mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previously set, it Note: The PIC16C63A and PIC16C73B do not must be cleared in firmware. provide a parallel slave port. The PORTD, An interrupt is generated and latched into flag bit PORTE, TRISD and TRISE registers are PSPIF when a read or write operation is completed. not implemented. PSPIF must be cleared by the user in firmware and the PORTD operates as an 8-bit wide Parallel Slave Port interrupt can be disabled by clearing the interrupt (PSP), or microprocessor port when control bit PSP- enable bit PSPIE (PIE1<7>). MODE (TRISE<4>) is set. In Slave mode, it is asyn- chronously readable and writable by the external world, FIGURE 5-8: PORTD AND PORTE through RD control input pin RE0/RD/AN5 and WR BLOCK DIAGRAM control input pin RE1/WR/AN6. (PARALLEL SLAVE It can directly interface to an 8-bit microprocessor data PORT) bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD/AN5 to be the RD input, Data Bus D Q RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to WR RDx be the CS (chip select) input. For this functionality, the Port pin CK corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set) and TTL the A/D port configuration bits PCFG2:PCFG0 Q D (ADCON1<2:0>) must be set, which will configure pins RE2:RE0 as digital I/O. RD ENEN Port There are actually two 8-bit latches, one for data out (from the PIC® MCU) and one for data input. The user One bit of PORTD writes 8-bit data to PORTD data latch and reads data from the port pin latch (note that they have the same Set Interrupt Flag address). In this mode, the TRISD register is ignored PSPIF (PIR1<7>) since the external device is controlling the direction of data flow. A write to the PSP occurs when both the CS and WR lines are first detected low. When either the CS or WR Read TTL RD lines become high (level triggered), then the Input Chip Select Buffer Full (IBF) status flag bit (TRISE<7>) is set on the TTL CS Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure5-9). The interrupt flag bit Write PSPIF (PIR1<7>) is also set on the same Q4 clock TTL WR cycle. IBF can only be cleared by reading the PORTD input latch. The Input Buffer Overflow (IBOV) status Note 1:I/O pins have protection diodes to VDD and VSS. flag bit (TRISE<5>) is set if a second write to the PSP is attempted when the previous byte has not been read out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immedi- ately (Figure5-10), indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the inter- rupt flag bit PSPIF is set on the Q4 clock cycle, follow- ing the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware.  1998-2013 Microchip Technology Inc. DS30605D-page 37

PIC16C63A/65B/73B/74B FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 08h PORTD Port data latch when written, Port pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. DS30605D-page 38  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 6.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will The Timer0 module timer/counter has the following fea- increment, either on every rising, or falling edge of pin tures: RA4/T0CKI. The incrementing edge is determined by • 8-bit timer/counter the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the ris- • Readable and writable ing edge. Restrictions on the external clock input are • 8-bit software programmable prescaler discussed in detail in Section6.2. • Internal or external clock select The prescaler is mutually exclusively shared between • Interrupt on overflow from FFh to 00h the Timer0 module and the watchdog timer. The • Edge select for external clock prescaler is not readable or writable. Section6.3 Figure6-1 is a block diagram of the Timer0 module and details the operation of the prescaler. the prescaler shared with the WDT. 6.1 Timer0 Interrupt Additional information on the Timer0 module is available in the PIC® Mid-Range MCU Family Refer- The TMR0 interrupt is generated when the TMR0 reg- ence Manual (DS33023). ister overflows from FFh to 00h. This overflow sets bit Timer mode is selected by clearing bit T0CS T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without cleared in software by the Timer0 module Interrupt Ser- vice Routine before re-enabling this interrupt. The prescaler). If the TMR0 register is written, the incre- TMR0 interrupt cannot awaken the processor from ment is inhibited for the following two instruction cycles. SLEEP, since the timer is shut-off during SLEEP. The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (= FOSC/4) Data Bus 8 M 0 1 RA4/T0CKI U M SYNC pin 1 X 0 U 2 TMR0 reg X Cycles T0SE T0CS PSA Set Flag bit T0IF on Overflow PRESCALER 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8 - to - 1MUX PS2:PS0 PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).  1998-2013 Microchip Technology Inc. DS30605D-page 39

PIC16C63A/65B/73B/74B 6.2 Using Timer0 with an External module means that there is no prescaler for the Watch- Clock dog Timer, and vice-versa. This prescaler is not read- able or writable (see Figure6-1). The synchronization of T0CKI with the internal phase The PSA and PS2:PS0 bits (OPTION_REG<3:0>) clocks is accomplished by sampling the synchronized determine the prescaler assignment and prescale ratio. input on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high When assigned to the Timer0 module, all instructions for at least 2TOSC (and a small RC delay of 20ns) and writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, low for at least 2TOSC (and a small RC delay of 20ns). BSF 1,x....etc.) will clear the prescaler. When assigned Refer to the electrical specification for the desired to WDT, a CLRWDT instruction will clear the prescaler device. along with the Watchdog Timer. The prescaler is not readable or writable. 6.3 Prescaler Note: Writing to TMR0, when the prescaler is There is only one prescaler available which is mutually assigned to Timer0, will clear the prescaler exclusively shared between the Timer0 module and the count, but will not change the prescaler watchdog timer. A prescaler assignment for the Timer0 assignment. REGISTER 6-1: OPTION_REG REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU bit 6 INTEDG bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown Note: To avoid an unintended device RESET, the instruction sequence shown in the PIC® Mid-Range MCU Family Reference Manual (DS33023, Section 11.6) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled. DS30605D-page 40  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 01h TMR0 Timer0 Module’s register xxxx xxxx uuuu uuuu 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.  1998-2013 Microchip Technology Inc. DS30605D-page 41

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 42  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 7.0 TIMER1 MODULE In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising The Timer1 module is a 16-bit timer/counter consisting edge of the external clock input. of two 8-bit registers (TMR1H and TMR1L), which are Timer1 can be enabled/disabled by setting/clearing readable and writable. The TMR1 Register pair control bit TMR1ON (T1CON<0>). (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, Timer1 also has an internal “RESET input”. This is generated on overflow, which is latched in interrupt RESET can be generated by either of the two CCP flag bit TMR1IF (PIR1<0>). This interrupt can be modules (Section9.0) using the special event trigger. enabled/disabled by setting/clearing TMR1 interrupt Register7-1 shows the Timer1 control register. enable bit TMR1IE (PIE1<0>). When the Timer1 oscillator is enabled (T1OSCEN is Timer1 can operate in one of two modes: set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is • As a timer ignored, and these pins read as ‘0’. • As a counter Additional information on timer modules is available in The operating mode is determined by the clock select the PIC® Mid-range MCU Family Reference Manual bit, TMR1CS (T1CON<1>). (DS33023). REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (The oscillator inverter is turned off to eliminate power drain) bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 43

PIC16C63A/65B/73B/74B 7.1 Timer1 Operation in Timer Mode 7.2 Timer1 Operation in Synchronized Counter Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the Counter mode is selected by setting bit TMR1CS. In timer is FOSC/4. The synchronize control bit T1SYNC this mode, the timer increments on every rising edge of (T1CON<2>) has no effect since the internal clock is clock input on pin RC1/T1OSI/CCP2, when bit always in sync. T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN is cleared. If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchro- nization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. In this configuration during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. The prescaler, however, will continue to increment. FIGURE 7-1: TIMER1 BLOCK DIAGRAM Set Flag bit TMR1IF on Overflow Synchronized TMR1 0 Clock Input TMR1H TMR1L 1 TMR1ON On/Off T1SYNC T1OSC (2) RC0/T1OSO/T1CKI 1 Synchronize Prescaler T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 RC1/T1OSI/CCP2(2) Oscillator(1) Clock 2 SLEEP Input T1CKPS1:T1CKPS0 TMR1CS Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. 2: For the PIC16C65B/73B/74B, the Schmitt Trigger is not implemented in External Clock mode. DS30605D-page 44  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 7.3 Timer1 Operation in TABLE 7-1: CAPACITOR SELECTION FOR Asynchronous Counter Mode THE TIMER1 OSCILLATOR If control bit T1SYNC (T1CON<2>) is set, the external Osc Type Freq C1 C2 clock input is not synchronized. The timer continues to LP 32 kHz 33 pF 33 pF increment asynchronous to the internal phase clocks. 100 kHz 15 pF 15 pF The timer will continue to run during SLEEP and can 200 kHz 15 pF 15 pF generate an interrupt-on-overflow, which will wake-up These values are for design guidance only. the processor. However, special precautions in soft- ware are needed to read/write the timer (Section7.3.1). Crystals Tested: 32.768 kHz Epson C-001R32.768K-A ± 20 PPM In Asynchronous Counter mode, Timer1 can not be used as a time-base for capture or compare opera- 100 kHz Epson C-2 100.00 KC-P ± 20 PPM tions. 200 kHz STD XTL 200.000 kHz ± 20 PPM Note 1: Higher capacitance increases the stability 7.3.1 READING AND WRITING TIMER1 IN of oscillator, but also increases the start-up ASYNCHRONOUS COUNTER time. MODE 2: Since each resonator/crystal has its own characteristics, the user should consult the Reading TMR1H or TMR1L while the timer is running resonator/crystal manufacturer for appro- from an external asynchronous clock will guarantee a priate values of external components. valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since 7.5 Resetting Timer1 using a CCP the timer may overflow between the reads. Trigger Output For writes, it is recommended that the user simply stop If the CCP1 or CCP2 module is configured in Compare the timer and write the desired values. A write conten- mode to generate a “special event trigger” tion may occur by writing to the timer registers, while (CCP1M3:CCP1M0 = 1011), this signal will reset the register is incrementing. This may produce an Timer1. unpredictable value in the timer register. Reading the 16-bit value requires some care. Exam- Note: The special event triggers from the CCP1 ples 12-2 and 12-3 in the PIC® Mid-Range MCU Family and CCP2 modules will not set interrupt Reference Manual (DS33023) show how to read and flag bit TMR1IF (PIR1<0>). write Timer1 when it is running in Asynchronous mode. Timer1 must be configured for either timer or Synchro- nized Counter mode to take advantage of this feature. 7.4 Timer1 Oscillator If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by In the event that a write to Timer1 coincides with a spe- setting control bit T1OSCEN (T1CON<3>). The oscilla- cial event trigger from CCP1 or CCP2, the write will tor is a low power oscillator rated up to 200 kHz. It will take precedence. continue to run during SLEEP. It is primarily intended In this mode of operation, the CCPRxH:CCPRxL regis- for use with a 32 kHz crystal. Table7-1 shows the ter pair effectively becomes the period register for capacitor selection for the Timer1 oscillator. Timer1. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure 7.6 Resetting of Timer1 Register Pair proper oscillator start-up. (TMR1H, TMR1L) TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other resets, the register is unaffected. 7.7 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.  1998-2013 Microchip Technology Inc. DS30605D-page 45

PIC16C63A/65B/73B/74B TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. DS30605D-page 46  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 8.0 TIMER2 MODULE 8.1 Timer2 Prescaler and Postscaler Timer2 is an 8-bit timer with a prescaler and a The prescaler and postscaler counters are cleared postscaler. It can be used as the PWM time-base for when any of the following occurs: the PWM mode of the CCP module(s). The TMR2 reg- • a write to the TMR2 register ister is readable and writable, and is cleared on any • a write to the T2CON register device RESET. • any device RESET (POR, BOR, MCLR Reset, or The input clock (FOSC/4) has a prescale option of 1:1, WDT Reset) 1:4, or 1:16, selected by control bits TMR2 is not cleared when T2CON is written. T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. 8.2 Output of TMR2 Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is The output of TMR2 (before the postscaler) is fed to the a readable and writable register. The PR2 register is SSP module, which optionally uses it to generate the initialized to FFh upon RESET. shift clock. The match output of TMR2 goes through a 4-bit FIGURE 8-1: TIMER2 BLOCK DIAGRAM postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit Sets Flag TMR2 TMR2IF, (PIR1<1>)). bit TMR2IF Output(1) Timer2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. RESET TMR2 reg Prescaler FOSC/4 1:1, 1:4, 1:16 Register8-1 shows the Timer2 control register. Postscaler Comparator 2 Additional information on timer modules is available in 1:1 to 1:16 EQ the PIC® Mid-Range MCU Family Reference Manual T2CKPS1: (DS33023). 4 PR2 reg T2CKPS0 T2OUTPS3: T2OUTPS0 Note 1:TMR2 register output can be software selected by the SSP module as a baud clock. REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 47

PIC16C63A/65B/73B/74B TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 11h TMR2 Timer2 Module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. DS30605D-page 48  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 9.0 CAPTURE/COMPARE/PWM CCP2 Module: MODULES Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and Each Capture/Compare/PWM (CCP) module contains CCPR2H (high byte). The CCP2CON register controls a 16-bit register which can operate as a: the operation of CCP2. The special event trigger is • 16-bit Capture register generated by a compare match and will reset Timer1 • 16-bit Compare register and start an A/D conversion (if the A/D module is enabled). • PWM Master/Slave Duty Cycle register Additional information on CCP modules is available in Both the CCP1 and CCP2 modules are identical in the PIC® Mid-Range MCU Family Reference Manual operation, with the exception being the operation of the (DS33023) and in “Using the CCP Modules” (AN594). special event trigger. Table9-1 and Table9-2 show the resources and interactions of the CCP module(s). In TABLE 9-1: CCP MODE - TIMER the following sections, the operation of a CCP module RESOURCES REQUIRED is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted. CCP Mode Timer Resource CCP1 Module: Capture Timer1 Capture/Compare/PWM Register1 (CCPR1) is com- Compare Timer1 prised of two 8-bit registers: CCPR1L (low byte) and PWM Timer2 CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1. TABLE 9-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time-base. Capture Compare The compare should be configured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None. PWM Compare None.  1998-2013 Microchip Technology Inc. DS30605D-page 49

PIC16C63A/65B/73B/74B REGISTER 9-1: CCP1CON REGISTER/CCP2CON REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30605D-page 50  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 9.1 Capture Mode 9.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode or Synchro- 16-bit value of the TMR1 register when an event occurs nized Counter mode for the CCP module to use the on pin RC2/CCP1. An event is defined as one of the fol- capture feature. In Asynchronous Counter mode, the lowing and is configured using CCPxCON<3:0>: capture operation may not work. • Every falling edge 9.1.3 SOFTWARE INTERRUPT • Every rising edge When the Capture mode is changed, a false capture • Every 4th rising edge interrupt may be generated. The user should keep bit • Every 16th rising edge CCP1IE (PIE1<2>) clear to avoid false interrupts and An event is selected by control bits CCP1M3:CCP1M0 should clear the flag bit CCP1IF following any such (CCP1CON<3:0>). When a capture is made, the inter- change in operating mode. rupt request flag bit CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in software. If another 9.1.4 CCP PRESCALER capture occurs before the value in register CCPR1 is There are four prescaler settings, specified by bits read, the previous captured value is overwritten by the CCP1M3:CCP1M0. Whenever the CCP module is new captured value. turned off, or the CCP module is not in Capture mode, 9.1.1 CCP PIN CONFIGURATION the prescaler counter is cleared. Any RESET will clear the prescaler counter. In Capture mode, the RC2/CCP1 pin should be config- Switching from one capture prescaler to another may ured as an input by setting the TRISC<2> bit. generate an interrupt. Also, the prescaler counter will Note: If the RC2/CCP1 pin is configured as an not be cleared, therefore, the first capture may be from output, a write to the port can cause a a non-zero prescaler. Example9-1 shows the recom- capture condition. mended method for switching between capture pres- calers. This example also clears the prescaler counter FIGURE 9-1: CAPTURE MODE and will not generate the “false” interrupt. OPERATION BLOCK DIAGRAM EXAMPLE 9-1: CHANGING BETWEEN CAPTURE PRESCALERS Set Flag bit CCP1IF Prescaler (PIR1<2>) CLRF CCP1CON ; Turn CCP module off  1, 4, 16 MOVLW NEW_CAPT_PS ; Load the W reg with RC2/CCP1 ; the new prescaler CCPR1H CCPR1L pin ; move value and CCP ON MOVWF CCP1CON ; Load CCP1CON with this and Capture Edge Detect Enable ; value TMR1H TMR1L CCP1CON<3:0> Q’s  1998-2013 Microchip Technology Inc. DS30605D-page 51

PIC16C63A/65B/73B/74B 9.2 Compare Mode 9.2.4 SPECIAL EVENT TRIGGER In Compare mode, the 16-bit CCPR1 register value is In this mode, an internal hardware trigger is generated, constantly compared against the TMR1 register pair which may be used to initiate an action. value. When a match occurs, the RC2/CCP1 pin is: The special event trigger output of CCP1 resets the • Driven high TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for • Driven low Timer1. • Remains unchanged The special event trigger output of CCP2 resets the The action on the pin is based on the value of control TMR1 register pair and starts an A/D conversion (if the bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the A/D module is enabled). same time, interrupt flag bit CCP1IF is set. Note: The special event trigger from the FIGURE 9-2: COMPARE MODE CCP1and CCP2 modules will not set inter- OPERATION BLOCK rupt flag bit TMR1IF (PIR1<0>). DIAGRAM 9.3 PWM Mode (PWM) Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), In Pulse Width Modulation mode, the CCPx pin pro- and set bit GO/DONE (ADCON0<2>). duces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the Special Event Trigger TRISC<2> bit must be cleared to make the CCP1 pin an output. Set Flag bit CCP1IF (PIR1<2>) Note: Clearing the CCP1CON register will force CCPR1H CCPR1L the CCP1 PWM output latch to the default Q S Output low level. This is not the PORTC I/O data RC2/pCinCP1 R Logic Match Comparator latch. TRISC<2> TMR1H TMR1L Figure9-3 shows a simplified block diagram of the Output Enable CCP1CON<3:0> CCP module in PWM mode. Mode Select For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section9.3.3. 9.2.1 CCP PIN CONFIGURATION FIGURE 9-3: SIMPLIFIED PWM BLOCK The user must configure the RC2/CCP1 pin as an out- DIAGRAM put by clearing the TRISC<2> bit. CCP1CON<5:4> Duty Cycle Registers Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the CCPR1L default low level. This is not the PORTC I/O data latch. 9.2.2 TIMER1 MODE SELECTION CCPR1H (Slave) Timer1 must be running in Timer mode or Synchro- nized Counter mode if the CCP module is using the Comparator R Q compare feature. In Asynchronous Counter mode, the RC2/CCP1 compare operation may not work. TMR2 (Note 1) S 9.2.3 SOFTWARE INTERRUPT MODE Comparator TRISC<2> When Generate Software Interrupt mode is chosen, the Clear Timer, CCP1 pin is not affected. The CCPIF bit is set, causing CCP1 pin and latch D.C. a CCP interrupt (if enabled). PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescale, to create 10-bit time-base. DS30605D-page 52  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B A PWM output (Figure9-4) has a time-base (period) 9.3.2 PWM DUTY CYCLE and a time that the output stays high (duty cycle). The The PWM duty cycle is specified by writing to the frequency of the PWM is the inverse of the period CCPR1L register and to the CCP1CON<5:4> bits. Up (1/period). to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the FIGURE 9-4: PWM OUTPUT two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is Period used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 prescale value) Duty Cycle CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into TMR2 = PR2(Timer2 RESET) CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, TMR2 = Duty Cycle CCPR1H is a read-only register. TMR2 = PR2(Timer2 RESET) The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double 9.3.1 PWM PERIOD buffering is essential for glitchless PWM operation. The PWM period is specified by writing to the PR2 When the CCPR1H and 2-bit latch match TMR2, con- register. The PWM period can be calculated using the catenated with an internal 2-bit Q clock, or 2 bits of the following formula: TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM PWM period = [(PR2) + 1] • 4 • TOSC • frequency: (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. (FOSC ) log When TMR2 is equal to PR2, the following three events Resolution = FPWM bits occur on the next increment cycle: log(2) • TMR2 is cleared Note: If the PWM duty cycle value is longer than • The CCP1 pin is set (exception: if PWM duty the PWM period, the CCP1 pin will not be cycle=0%, the CCP1 pin will not be set) cleared. • The PWM duty cycle is latched from CCPR1L into CCPR1H 9.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring Note: The Timer2 postscaler (see Section8.1) is the CCP module for PWM operation: not used in the determination of the PWM frequency. The postscaler could be used to 1. Set the PWM period by writing to the PR2 register. have a servo update rate at a different fre- 2. Set the PWM duty cycle by writing to the quency than the PWM output. CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. TABLE 9-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5  1998-2013 Microchip Technology Inc. DS30605D-page 53

PIC16C63A/65B/73B/74B TABLE 9-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: The PSP is not implemented on the PIC16C63A/73B; always maintain these bits clear. 2: The A/D is not implemented on the PIC16C63A/65B; always maintain these bits clear. TABLE 9-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 11h TMR2 Timer2 Module’s register 0000 0000 0000 0000 92h PR2 Timer2 Module’s Period register 1111 1111 1111 1111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. DS30605D-page 54  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 10.0 SYNCHRONOUS SERIAL PORT FIGURE 10-1: SSP BLOCK DIAGRAM (SSP) MODULE (SPIMODE) Internal 10.1 SSP Module Overview Data Bus Read Write The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other periph- SSPBUF reg eral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The SSP module can operate in one of two modes: SSPSR reg • Serial Peripheral Interface (SPI) RC4/SDI/SDA bit0 Shift • Inter-Integrated Circuit (I2C) Clock An overview of I2C operations and additional informa- RC5/SDO tion on the SSP module can be found in the PIC® Mid-Range MCU Family Reference Manual (DS33023). SS Control Enable Refer to Application Note AN578, “Use of the SSP Module in the I2C Multi-Master Environment.” RA5/SS/AN4 Edge Select 10.2 SPI Mode 2 This section contains register definitions and opera- Clock Select tional characteristics of the SPI module. SPI mode allows 8 bits of data to be synchronously SSPM3:SSPM0 TMR2 Output transmitted and received simultaneously. To accom- 4 2 plish communication, typically three pins are used: Edge • Serial Data Out (SDO) RC5/SDO Select Prescaler TCY RC3/SCK/ • Serial Data In (SDI) RC4/SDI/SDA SCL 4, 16, 64 TRISC<3> • Serial Clock (SCK) RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave To enable the serial port, SSP enable bit, SSPEN mode of operation: (SSPCON<5>) must be set. To reset or reconfigure SPI • Slave Select (SS) RA5/SS/AN4 mode, clear bit SSPEN, re-initialize the SSPCON reg- When initializing the SPI, several options need to be ister, and then set bit SSPEN. This configures the SDI, specified. This is done by programming the appropriate SDO, SCK, and SS pins as serial port pins. For the pins control bits in the SSPCON register (SSPCON<5:0>) to behave as the serial port function, they must have and SSPSTAT<7:6>. These control bits allow the fol- their data direction bits (in the TRISC register) appro- lowing to be specified: priately programmed. That is: • Master mode (SCK is the clock output) • SDI must have TRISC<4> set • Slave mode (SCK is the clock input) • SDO must have TRISC<5> cleared • Clock Polarity (Idle state of SCK) • SCK (Master mode) must have TRISC<3> cleared • Clock edge (output data on rising/falling edge of • SCK (Slave mode) must have TRISC<3> set SCK) • SS must have TRISA<5> set • Clock Rate (Master mode only) • ADCON1 must configure RA5 as a digital I/O pin. • Slave Select mode (Slave mode only) . Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE='1', then the SS pin control must be enabled.  1998-2013 Microchip Technology Inc. DS30605D-page 55

PIC16C63A/65B/73B/74B REGISTER 10-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: SPI Data Input Sample Phase SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire®) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I 2 C mode: This bit must be maintained clear bit 6 CKE: SPI Clock Edge Select (see Figure10-2, Figure10-3, and Figure10-4) SPI mode: CKP = 0: 1 =Data transmitted on rising edge of SCK (Microwire alternate) 0 =Data transmitted on falling edge of SCK CKP = 1: 1 =Data transmitted on falling edge of SCK (Microwire default) 0 =Data transmitted on rising edge of SCK I 2 C mode: This bit must be maintained clear bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: STOP bit (I2C mode only). This bit is cleared when the SSP module is disabled, or when the START bit is detected last. SSPEN is cleared. 1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET) 0 = STOP bit was not detected last bit 3 S: START bit (I2C mode only). This bit is cleared when the SSP module is disabled, or when the STOP bit is detected last. SSPEN is cleared. 1 = Indicates that a START bit has been detected last (this bit is '0' on RESET) 0 = START bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only). This bit holds the R/W bit information follow- ing the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or ACK bit. 1 = Read 0 = Write bit 1 UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 =Receive complete, SSPBUF is full 0 =Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30605D-page 56  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B REGISTER 10-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Flag bit 1 = The SSPBUF register was written while still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Synchronous Serial Port Overflow Flag bit In SPI mode: 1 = A new byte was received while the SSPBUF register is still holding the previous unread data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and trans- mission) is initiated by writing to the SSPBUF register. 0 = No overflow In I 2 C mode: 1 = A byte was received while the SSPBUF register is still holding the previous unread byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit. When enabled, the SSP pins must be properly configured as input or output. In SPI mode: 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level (Microwire default) 0 = Idle state for clock is a low level (Microwire alternate) In I 2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1011 = I2C firmware controlled Master mode (Slave idle) 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 57

PIC16C63A/65B/73B/74B FIGURE 10-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE=0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF DS30605D-page 58  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE=1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 10-1: REGISTERS ASSOCIATED WITH SPI OPERATION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction register --11 1111 --11 1111 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30605D-page 59

PIC16C63A/65B/73B/74B 10.3 SSP I2C Operation The SSPCON register allows control of the I2C opera- tion. Four mode selection bits (SSPCON<3:0>) allow The SSP module in I2C mode fully implements all slave one of the following I2C modes to be selected: functions, except general call support, and provides • I2C Slave mode (7-bit address) interrupts on START and STOP bits in hardware to facilitate firmware implementation of the master func- • I2C Slave mode (10-bit address) tions. The SSP module implements the standard mode • I2C Slave mode (7-bit address), with START and specifications as well as 7-bit and 10-bit addressing. STOP bit interrupts enabled to support firmware Master mode Two pins are used for data transfer, the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA • I2C Slave mode (10-bit address), with START and pin, which is the data (SDA). The user must configure STOP bit interrupts enabled to support firmware these pins as inputs or outputs through the Master mode TRISC<4:3> bits. External pull-up resistors for the SCL • I2C START and STOP bit interrupts enabled to and SDA pins must be provided in the application cir- support firmware Master mode, Slave is idle cuit for proper operation of the I2C module. Selection of any I2C mode with the SSPEN bit set, The SSP module functions are enabled by setting SSP forces the SCL and SDA pins to be open drain, pro- enable bit SSPEN (SSPCON<5>). vided these pins are programmed to inputs by setting the appropriate TRISC bits. FIGURE 10-5: SSP BLOCK DIAGRAM Additional information on SSP I2C operation can be (I2C MODE) found in the PIC® Mid-Range MCU Family Reference Manual (DS33023). Internal Data Bus 10.3.1 SLAVE MODE Read Write In Slave mode, the SCL and SDA pins must be config- ured as inputs (TRISC<4:3> set). The SSP module will SSPBUF reg override the input state with the output data when RC3/SCK/SCL required (slave-transmitter). Shift When an address is matched or the data transfer after Clock an address match is received, the hardware automati- SSPSR reg cally generates the acknowledge (ACK) pulse, and RCS4D/SADI/ MSb LSb then loads the SSPBUF register with the received value currently in the SSPSR register. Match Detect Addr Match There are certain conditions that will cause the SSP module not to give this ACK pulse. They include (either or both): SSPADD reg a) The buffer full bit BF (SSPSTAT<0>) was set START and Set, Reset before the transfer was received. STOP bit Detect S, P bits b) The overflow bit SSPOV (SSPCON<6>) was set (SSPSTAT reg) before the transfer was received. In this case, the SSPSR register value is not loaded The SSP module has five registers for I2C operation. into the SSPBUF, but bit SSPIF (PIR1<3>) is set. These are the: Table10-2 shows what happens when a data transfer • SSP Control Register (SSPCON) byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where • SSP Status Register (SSPSTAT) user software did not properly clear the overflow condi- • Serial Receive/Transmit Buffer (SSPBUF) tion. Flag bit BF is cleared by reading the SSPBUF • SSP Shift Register (SSPSR) - not directly accessible register while bit SSPOV is cleared through software. • SSP Address Register (SSPADD) The SCL clock input must have minimum high and low times for proper operation. The high and low times of the I2C specification, as well as the requirement of the SSP module, is shown in timing parameter #100 and parameter #101. DS30605D-page 60  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 10.3.1.1 Addressing 1. Receive first (high) byte of address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condi- 2. Update the SSPADD register with second (low) tion, 8-bits are shifted into the SSPSR register. All byte of Address (clears bit UA and releases the incoming bits are sampled with the rising edge of the SCL line). clock (SCL) line. The value of register SSPSR<7:1> is 3. Read the SSPBUF register (clears bit BF) and compared to the value of the SSPADD register. The clear flag bit SSPIF. address is compared on the falling edge of the eighth 4. Receive second (low) byte of address (bits clock (SCL) pulse. If the addresses match, and the BF SSPIF, BF, and UA are set). and SSPOV bits are clear, the following events occur: 5. Update the SSPADD register with the first (high) a) The SSPSR register value is loaded into the byte of address, if match releases SCL line, this SSPBUF register. will clear bit UA. b) The buffer full bit, BF is set. 6. Read the SSPBUF register (clears bit BF) and c) An ACK pulse is generated. clear flag bit SSPIF. d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set 7. Receive Repeated START condition. (interrupt is generated if enabled) - on the falling 8. Receive first (high) byte of address (bits SSPIF edge of the ninth SCL pulse. and BF are set). 9. Read the SSPBUF register (clears bit BF) and In 10-bit address mode, two address bytes need to be clear flag bit SSPIF. received by the slave (Figure10-7). The five Most Sig- nificant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the sec- ond address byte. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 - 9 for slave-transmitter: TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Set bit SSPIF Transfer is Received SSPSR  SSPBUF Generate ACK (SSP Interrupt occurs Pulse BF SSPOV if enabled) 0 0 Yes Yes Yes 1 0 No No Yes, SSPOV is set 1 1 No No Yes 0 1 No No Yes Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.  1998-2013 Microchip Technology Inc. DS30605D-page 61

PIC16C63A/65B/73B/74B 10.3.1.2 Reception a) The Buffer Full flag bit, BF(SSPSTAT<0>) was set, indicating that the byte in SSPBUF was When the R/W bit of the address byte is clear and an waiting to be read when another byte was address match occurs, the R/W bit of the SSPSTAT received. This sets the SSPOV flag. register is cleared. The received address is loaded into the SSPBUF register. b) The overflow flag, SSPOV (SSPCON1<6>) was set. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow con- An SSP interrupt is generated for each data transfer dition is defined as any situation where a received byte byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- in SSPBUF is overwritten by the next received byte ware. The SSPSTAT register is used to determine the before it has been read. An overflow has occurred status of the byte. when: FIGURE 10-6: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W=0 Receiving Data ACK Receiving Data ACK ACK SDA A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF (PIR1<3>) Cleared in software Bus Master terminates transfer BF (SSPSTAT<0>) SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full ACK is not sent DS30605D-page 62  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 10.3.1.3 Transmission An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and When the R/W bit of the incoming address byte is set the SSPSTAT register is used to determine the status and an address match occurs, the R/W bit of the of the byte. Flag bit SSPIF is set on the falling edge of SSPSTAT register is set. The received address is the ninth clock pulse. loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held As a slave-transmitter, the ACK pulse from the low. The transmit data must be loaded into the master-receiver is latched on the rising edge of the SSPBUF register, which also loads the SSPSR regis- ninth SCL input pulse. If the SDA line was high (not ter. Then pin RC3/SCK/SCL should be enabled by set- ACK), then the data transfer is complete. When the ting bit CKP (SSPCON<4>). The master must monitor ACK is latched by the slave, the slave logic is reset the SCL pin prior to asserting another clock pulse. The (resets SSPSTAT register) and the slave then monitors slave devices may be holding off the master by stretch- for another occurrence of the START bit. If the SDA line ing the clock. The eight data bits are shifted out on the was low (ACK), the transmit data must be loaded into falling edge of the SCL input. This ensures that the the SSPBUF register, which also loads the SSPSR reg- SDA signal is valid during the SCL high time ister. Then pin RC3/SCK/SCL should be enabled by (Figure10-7). setting bit CKP. FIGURE 10-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address R/W = 1 Transmitting Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low sampled while CPU responds to SSPIF SSPIF (PIR1<3>) Cleared in software BF (SSPSTAT<0>) From SSP Interrupt SSPBUF is written in software Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)  1998-2013 Microchip Technology Inc. DS30605D-page 63

PIC16C63A/65B/73B/74B 10.3.2 MASTER MODE 10.3.3 MULTI-MASTER MODE Master mode of operation is supported in firmware In Multi-Master mode, the interrupt generation on the using interrupt generation on the detection of the detection of the START and STOP conditions allows START and STOP conditions. The STOP (P) and the determination of when the bus is free. The STOP START (S) bits are cleared from a RESET, or when the (P) and START (S) bits are cleared from a RESET or SSP module is disabled. The STOP (P) and START (S) when the SSP module is disabled. The STOP (P) and bits will toggle based on the START and STOP condi- START (S) bits will toggle based on the START and tions. Control of the I2C bus may be taken when the P STOP conditions. Control of the I2C bus may be taken bit is set, or the bus is idle and both the S and P bits are when bit P (SSPSTAT<4>) is set, or the bus is idle and clear. both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt In Master mode, the SCL and SDA lines are manipu- when the STOP condition occurs. lated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the In Multi-Master operation, the SDA line must be moni- value(s) in PORTC<4:3>. So when transmitting data, a tored to see if the signal level is the expected output '1' data bit must have the TRISC<4> bit set (input) and level. This check only needs to be done when a high a '0' data bit must have the TRISC<4> bit cleared (out- level is output. If a high level is expected and a low level put). The same scenario is true for the SCL line with the is present, the device needs to release the SDA and TRISC<3> bit. SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are: The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (an SSP Interrupt will occur, if • Address Transfer enabled): • Data Transfer • START condition When the slave logic is enabled, the slave continues to • STOP condition receive. If arbitration was lost during the address trans- • Data transfer byte transmitted/received fer stage, communication to the device may be in progress. If addressed, an ACK pulse will be gener- Master mode of operation can be done with either the ated. If arbitration was lost during the data transfer Slave mode idle (SSPM3:SSPM0 = 1011), or with the stage, the device will need to re-transfer the data at a slave active. When both Master and Slave modes are later time. enabled, the software needs to differentiate the source(s) of the interrupt. TABLE 10-3: REGISTERS ASSOCIATED WITH I2C OPERATION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit register xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port (I2C mode) Address register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP(3) CKE(3) D/A P S R/W UA BF 0000 0000 0000 0000 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in I2C mode. Note 1: PSPIF and PSPIE are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: ADIF and ADIE are reserved on the PIC16C63A/65B; always maintain these bits clear. 3: Maintain these bits clear in I2C mode. DS30605D-page 64  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 11.0 ADDRESSABLE UNIVERSAL as a half duplex synchronous system that can commu- SYNCHRONOUS nicate with peripheral devices, such as A/D or D/A inte- grated circuits, Serial EEPROMs etc. ASYNCHRONOUS RECEIVER The USART can be configured in the following modes: TRANSMITTER (USART) • Asynchronous (full duplex) The Universal Synchronous Asynchronous Receiver • Synchronous - Master (half duplex) Transmitter (USART) module is one of the two serial • Synchronous - Slave (half duplex) I/O modules. (USART is also known as a Serial Com- munications Interface or SCI.) The USART can be con- Bits SPEN (RCSTA<7>) and TRISC<7:6> have to be figured as a full duplex asynchronous system that can set in order to configure pins RC6/TX/CK and communicate with peripheral devices, such as CRT ter- RC7/RX/DT as the universal synchronous asynchro- minals and personal computers, or it can be configured nous receiver transmitter. REGISTER 11-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 =Master mode (Clock generated internally from BRG) 0 =Slave mode (Clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4 SYNC: USART Mode Select bit 1 =Synchronous mode 0 =Asynchronous mode bit 3 Unimplemented: Read as '0' bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 =High speed 0 =Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 =TSR empty 0 =TSR full bit 0 TX9D: 9th bit of Transmit Data. Can be parity bit. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 65

PIC16C63A/65B/73B/74B REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x SPEN RX9 SREN CREN — FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 Unimplemented: Read as '0' bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data. (Can be parity bit. Calculated by firmware.) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30605D-page 66  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 11.1 USART Baud Rate Generator It may be advantageous to use the high baud rate (BRG) (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the The BRG supports both the Asynchronous and Syn- baud rate error in some cases. chronous modes of the USART. It is a dedicated 8-bit Writing a new value to the SPBRG register causes the baud rate generator. The SPBRG register controls the BRG timer to be reset (or cleared). This ensures the period of a free running 8-bit timer. In Asynchronous BRG does not wait for a timer overflow before output- mode, bit BRGH (TXSTA<2>) also controls the baud ting the new baud rate. rate. In Synchronous mode, bit BRGH is ignored. Table11-1 shows the formula for computation of the 11.1.1 SAMPLING baud rate for different USART modes, which only apply in Master mode (internal clock). The data on the RC7/RX/DT pin is sampled three times near the center of each bit time by a majority detect cir- Given the desired baud rate and Fosc, the nearest inte- cuit to determine if a high or a low level is present at the ger value for the SPBRG register can be calculated RX pin. using the formula in Table11-1. From this, the error in baud rate can be determined. TABLE 11-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(SPBRG+1)) Baud Rate = FOSC/(16(SPBRG+1)) 1 (Synchronous) Baud Rate = FOSC/(4(SPBRG+1)) N/A TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 99h SPBRG Baud Rate Generator register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.  1998-2013 Microchip Technology Inc. DS30605D-page 67

PIC16C63A/65B/73B/74B 11.2 USART Asynchronous Mode This interrupt can be enabled/disabled by setting/clear- ing the USART Transmit Enable bit TXIE (PIE1<4>). In this mode, the USART uses standard non- The flag bit TXIF will be set, regardless of the state of return-to-zero (NRZ) format (one START bit, eight or enable bit TXIE and cannot be cleared in software. It nine data bits, and one STOP bit). The most common will reset only when new data is loaded into the TXREG data format is 8 bits. An on-chip, dedicated, 8-bit baud register. While flag bit TXIF indicates the status of the rate generator can be used to derive standard baud TXREG register, another bit TRMT (TXSTA<1>) shows rate frequencies from the oscillator. The USART trans- the status of the TSR register. Status bit TRMT is a read mits and receives the LSb first. The USART’s transmit- only bit, which is set when the TSR register is empty. No ter and receiver are functionally independent, but use interrupt logic is tied to this bit, so the user has to poll this the same data format and baud rate. The baud rate bit in order to determine if the TSR register is empty. generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity Note 1: The TSR register is not mapped in data is not supported by the hardware, but can be imple- memory, so it is not available to the user. mented in software (and stored as the ninth data bit). 2: Flag bit TXIF is set when enable bit TXEN Asynchronous mode is stopped during SLEEP. is set. TXIF is cleared by loading TXREG. Asynchronous mode is selected by clearing bit SYNC Transmission is enabled by setting enable bit TXEN (TXSTA<4>). (TXSTA<5>). The actual transmission will not occur The USART Asynchronous module consists of the fol- until the TXREG register has been loaded with data lowing important elements: and the baud rate generator (BRG) has produced a shift clock (Figure11-2). The transmission can also be • Baud Rate Generator started by first loading the TXREG register and then • Sampling Circuit setting enable bit TXEN. Normally, when transmission • Asynchronous Transmitter is first started, the TSR register is empty. At that point, • Asynchronous Receiver transfer to the TXREG register will result in an immedi- ate transfer to TSR, resulting in an empty TXREG. A 11.2.1 USART ASYNCHRONOUS back-to-back transfer is thus possible (Figure11-3). TRANSMITTER Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the The USART transmitter block diagram is shown in transmitter. As a result, the RC6/TX/CK pin will revert Figure11-1. The heart of the transmitter is the transmit to hi-impedance. (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The In order to select 9-bit transmission, transmit bit TX9 TXREG register is loaded with data in software. The (TXSTA<6>) should be set and the ninth bit should be TSR register is not loaded until the STOP bit has been written to TX9D (TXSTA<0>). The ninth bit must be transmitted from the previous load. As soon as the written before writing the 8-bit data to the TXREG reg- STOP bit is transmitted, the TSR is loaded with new ister. This is because a data write to the TXREG regis- data from the TXREG register (if available). Once the ter can result in an immediate transfer of the data to the TXREG register transfers the data to the TSR register TSR register (if the TSR is empty). In such a case, an (occurs in one TCY), the TXREG register is empty and incorrect ninth data bit may be loaded in the TSR the USART Transmit Flag bit TXIF (PIR1<4>) is set. register. FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb LSb (8)  0 Pin Buffer and Control TSR register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D DS30605D-page 68  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B Steps to follow when setting up an Asynchronous 4. If 9-bit transmission is desired, then set transmit Transmission: bit TX9. 1. Initialize the SPBRG register for the appropriate 5. Enable the transmission by setting bit TXEN, baud rate. If a high speed baud rate is desired, which will also set flag bit TXIF. set bit BRGH. (Section11.1) 6. If 9-bit transmission is selected, the ninth bit 2. Enable the asynchronous serial port by clearing should be loaded in bit TX9D. bit SYNC and setting bit SPEN. 7. Load data to the TXREG register (starts trans- 3. If interrupts are desired, set interrupt enable bits mission). TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE (INTCON<7>), as required. FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit Word 1 TXIF bit (Transmit buffer reg. empty flag) Word 1 TRMT bit Transmit Shift Reg (Transmit shift reg. empty flag) FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 Word 2 BRG output (shift clock) RC6/TX/CK (pin) START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit START Bit Bit 0 TXIF bit Word 1 Word 2 (interrupt reg. flag) TRMT bit Word 1 (Transmit shift Transmit Shift Reg. Word 2 reg. empty flag) Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 11-3: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30605D-page 69

PIC16C63A/65B/73B/74B 11.2.2 USART ASYNCHRONOUS ered register, i.e., it is a two-deep FIFO. It is possible RECEIVER for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to The receiver block diagram is shown in Figure11-4. the RSR register. On the detection of the STOP bit of The data is received on the RC7/RX/DT pin and drives the third byte, if the RCREG register is still full, then the data recovery block. The data recovery block is overrun error bit OERR (RCSTA<1>) will be set. The actually a high speed shifter operating at x16 times the word in the RSR will be lost. The RCREG register can baud rate, whereas the main receive serial shifter oper- be read twice to retrieve the two bytes in the FIFO. ates at the bit rate or at FOSC. Overrun bit OERR has to be cleared in software. This Once Asynchronous mode is selected, reception is is done by resetting the receive logic (CREN is cleared enabled by setting bit CREN (RCSTA<4>). and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited, and The heart of the receiver is the receive (serial) shift reg- no further data will be received; therefore, it is essential ister (RSR). After sampling the STOP bit, the received to clear error bit OERR if it is set. Framing error bit data in the RSR is transferred to the RCREG register (if FERR (RCSTA<2>) is set if a STOP bit is detected as it is empty). If the transfer is complete, USART Receive clear. Bit FERR and the 9th receive bit are buffered the Flag bit RCIF (PIR1<5>) is set. This interrupt can be same way as the receive data. Reading the RCREG enabled/disabled by setting/clearing the USART will load bits RX9D and FERR with new values, there- Receive Enable bit RCIE (PIE1<5>). fore, it is essential for the user to read the RCSTA reg- Flag bit RCIF is a read only bit, which is cleared by the ister before reading the RCREG register, in order not to hardware. It is cleared when the RCREG register has lose the old FERR and RX9D information. been read and is empty. The RCREG is a double buff- FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN FOSC SPBRG  64 MSb RSR Register LSb or Baud Rate Generator  16 STOP (8) 7  1 0 START RC7/RX/DT Pin Buffer Data and Control Recovery RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF Data Bus RCIE DS30605D-page 70  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B Steps to follow when setting up an Asynchronous 5. Enable the reception by setting bit CREN. Reception: 6. Flag bit RCIF will be set when reception is com- 1. Initialize the SPBRG register for the appropriate plete and an interrupt will be generated if enable baud rate. If a high speed baud rate is desired, bit RCIE was set. set bit BRGH. (Section11.1). 7. Read the RCSTA register to get the ninth bit (if 2. Enable the asynchronous serial port by clearing enabled) and determine if any error occurred bit SYNC, and setting bit SPEN. during reception. 3. If interrupts are desired, set interrupt enable bits 8. Read the 8-bit received data by reading the RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE RCREG register. (INTCON<7>), as required. 9. If any error occurred, clear the error by clearing 4. If 9-bit reception is desired, then set bit RX9. enable bit CREN. FIGURE 11-5: ASYNCHRONOUS RECEPTION RX (pin) START START START bit bit0 bit1 bit7/8 STOP bit bit0 bit7/8 STOP bit bit7/8 STOP bit bit bit Rcv shift reg Rcv buffer reg Word 1 Word 2 Read Rcv RCREG RCREG buffer reg RCREG RCIF (interrupt flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user’s firmware. TABLE 11-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator register 0000 0000 0000 0000 Legend: u = unchanged, x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30605D-page 71

PIC16C63A/65B/73B/74B 11.2.3 USART SYNCHRONOUS MASTER Clearing enable bit TXEN, during a transmission, will MODE cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to In Synchronous Master mode, the data is transmitted in hi-impedance. If either bit CREN, or bit SREN is set a half-duplex manner, i.e., transmission and reception during a transmission, the transmission is aborted and do not occur at the same time. When transmitting data, the DT pin reverts to a hi-impedance state (for a recep- the reception is inhibited and vice versa. Synchronous tion). The CK pin will remain an output if bit CSRC is set mode is entered by setting bit SYNC (TXSTA<4>). In (internal clock). The transmitter logic, however, is not addition, enable bit SPEN (RCSTA<7>) is set in order reset, although it is disconnected from the pins. In order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to reset the transmitter, the user has to clear bit TXEN. to CK (clock) and DT (data) lines, respectively. The If bit SREN is set (to interrupt an on-going transmission Master mode indicates that the processor transmits the and receive a single word), then after the single word is master clock on the CK line. The Master mode is received, bit SREN will be cleared and the serial port entered by setting bit CSRC (TXSTA<7>). will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from 11.2.4 USART SYNCHRONOUS MASTER Hi-impedance Receive mode to transmit and start driv- TRANSMISSION ing. To avoid this, bit TXEN should be cleared. The USART transmitter block diagram is shown in In order to select 9-bit transmission, the TX9 Figure11-1. The heart of the transmitter is the transmit (TXSTA<6>) bit should be set and the ninth bit should (serial) shift register (TSR). The shift register obtains its be written to bit TX9D (TXSTA<0>). The ninth bit must data from the read/write transmit buffer register, be written before writing the 8-bit data to the TXREG TXREG. The TXREG register is loaded with data in register. This is because a data write to the TXREG can software. The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR bit has been transmitted from the previous load. As register (if the TSR is empty). If the TSR was empty and soon as the last bit is transmitted, the TSR is loaded the TXREG was written before writing the “new” TX9D, with new data from the TXREG (if available). Once the the “present” value of bit TX9D is loaded. TXREG register transfers the data to the TSR register Steps to follow when setting up a Synchronous Master (occurs in one TCYCLE), the TXREG is empty and inter- Transmission: rupt flag bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE 1. Initialize the SPBRG register for the appropriate (PIE1<4>). Flag bit TXIF will be set, regardless of the baud rate (Section11.1). state of enable bit TXIE and cannot be cleared in soft- 2. Enable the synchronous master serial port by ware. It will reset only when new data is loaded into the setting bits SYNC, SPEN and CSRC. TXREG register. While flag bit TXIF indicates the status 3. If interrupts are desired, set interrupt enable bits of the TXREG register, another bit TRMT (TXSTA<1>) TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE shows the status of the TSR register. TRMT is a read (INTCON<7>), as required. only bit which is set when the TSR is empty. No inter- 4. If 9-bit transmission is desired, set bit TX9. rupt logic is tied to this bit, so the user has to poll this 5. Enable the transmission by setting bit TXEN. bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not 6. If 9-bit transmission is selected, the ninth bit available to the user. should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG Transmission is enabled by setting enable bit TXEN register. (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is sta- ble around the falling edge of the synchronous clock (Figure11-6). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure11-7). This is advantageous when slow baud rates are selected, since the BRG is kept in RESET when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible. DS30605D-page 72  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 11-5: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. FIGURE 11-6: SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 RC6/TX/CK pin Write to TXREG reg Write word1 Write word2 TXIF bit (Interrupt Flag) TRMT biTtRMT '1' '1' TXEN bit Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words. FIGURE 11-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit  1998-2013 Microchip Technology Inc. DS30605D-page 73

PIC16C63A/65B/73B/74B 11.2.5 USART SYNCHRONOUS MASTER Steps to follow when setting up a Synchronous Master RECEPTION Reception: 1. Initialize the SPBRG register for the appropriate Once Synchronous mode is selected, reception is baud rate. (Section11.1) enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is 2. Enable the synchronous master serial port by sampled on the RC7/RX/DT pin on the falling edge of setting bits SYNC, SPEN, and CSRC. the clock. If enable bit SREN is set, then only a single 3. Ensure bits CREN and SREN are clear. word is received. If enable bit CREN is set, the recep- 4. If interrupts are desired, set interrupt enable bits tion is continuous until CREN is cleared. If both bits are RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE set, CREN takes precedence. After clocking the last bit, (INTCON<7>), as required. the received data in the Receive Shift Register (RSR) 5. If 9-bit reception is desired, then set bit RX9. is transferred to the RCREG register (if it is empty). 6. If a single reception is required, set bit SREN. When the transfer is complete, interrupt flag bit RCIF For continuous reception set bit CREN. (PIR1<5>) is set. The interrupt from the USART can be enabled/disabled by setting/clearing enable bit RCIE 7. Interrupt flag bit RCIF will be set when reception (PIE1<5>). Flag bit RCIF is a read only bit, which is is complete and an interrupt will be generated if reset by the hardware. In this case, it is reset when the enable bit RCIE was set. RCREG register has been read and is empty. The 8. Read the RCSTA register to get the ninth bit (if RCREG is a double buffered register, i.e., it is a enabled) and determine if any error occurred two-deep FIFO. It is possible for two bytes of data to be during reception. received and transferred to the RCREG FIFO and a 9. Read the 8-bit received data by reading the third byte to begin shifting into the RSR register. On the RCREG register. clocking of the last bit of the third byte, if the RCREG 10. If any error occurred, clear the error by clearing register is still full, then overrun error bit OERR bit CREN. (RCSTA<1>) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, and no further data will be received; therefore, it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the receive data. Read- ing the RCREG register will load bit RX9D with a new value, therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. DS30605D-page 74  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 11-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator register 0000 0000 0000 0000 Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. FIGURE 11-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'.  1998-2013 Microchip Technology Inc. DS30605D-page 75

PIC16C63A/65B/73B/74B 11.3 USART Synchronous Slave Mode 11.3.2 USART SYNCHRONOUS SLAVE RECEPTION Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at The operation of the synchronous Master and Slave the RC6/TX/CK pin (instead of being supplied internally modes is identical, except in the case of the SLEEP in Master mode). This allows the device to transfer or mode. Also, bit SREN is a “don't care” in Slave mode. receive data while in SLEEP mode. Slave mode is If receive is enabled by setting bit CREN prior to the entered by clearing bit CSRC (TXSTA<7>). SLEEP instruction, a word may be received during SLEEP. On completely receiving the word, the RSR 11.3.1 USART SYNCHRONOUS SLAVE register will transfer the data to the RCREG register. If TRANSMIT interrupt enable bits RCIE and PEIE are set, the inter- The operation of the Synchronous Master and Slave rupt generated will wake the chip from SLEEP. If the modes are identical, except in the case of the SLEEP global interrupt is enabled, the program will branch to mode. the interrupt vector (0004h), otherwise execution will resume from the instruction following the SLEEP If two words are written to the TXREG and then the instruction. SLEEP instruction is executed, the following will occur: Steps to follow when setting up a Synchronous Slave a) The first word will immediately transfer to the Reception: TSR register and transmit. 1. Enable the synchronous master serial port by b) The second word will remain in TXREG register. setting bits SYNC and SPEN and clearing bit c) Flag bit TXIF will not be set. CSRC. d) When the first word has been shifted out of TSR, 2. If interrupts are desired, set interrupt enable bits the TXREG register will transfer the second RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE word to the TSR and flag bit TXIF will now be (INTCON<7>), as required. set. 3. If 9-bit reception is desired, set bit RX9. e) If interrupt enable bits TXIE and PEIE are set, 4. To enable reception, set enable bit CREN. the interrupt will wake the chip from SLEEP. If GIE is set, the program will branch to the inter- 5. Flag bit RCIF will be set when reception is com- rupt vector (0004h), otherwise execution will plete and an interrupt will be generated, if resume from the instruction following the SLEEP enable bit RCIE was set. instruction. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred Steps to follow when setting up a Synchronous Slave during reception. Transmission: 7. Read the 8-bit received data by reading the 1. Enable the synchronous slave serial port by set- RCREG register. ting bits SYNC and SPEN and clearing bit 8. If any error occurred, clear the error by clearing CSRC. bit CREN. 2. Clear bits CREN and SREN. 3. If interrupts are desired, set interrupt enable bits TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE (INTCON<7>), as required. 4. If 9-bit transmission is desired, set bit TX9. 5. Enable the transmission by setting enable bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. DS30605D-page 76  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 11-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator register 0000 0000 0000 0000 Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear. TABLE 11-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator register 0000 0000 0000 0000 Legend: u = unchanged, x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B; always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B; always maintain these bits clear.  1998-2013 Microchip Technology Inc. DS30605D-page 77

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 78  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 12.0 ANALOG-TO-DIGITAL The A/D converter has a unique feature of being able CONVERTER (A/D) MODULE to operate while the device is in SLEEP mode. To oper- ate in SLEEP, the A/D conversion clock must be Note: The PIC16C63A and PIC16C65B do not derived from the A/D’s internal RC oscillator. include A/D modules. ADCON0, ADCON1 The A/D module has three registers. These registers and ADRES registers are not imple- are: mented. ADIF and ADIE bits are reserved • A/D Result Register (ADRES) and should be maintained clear. • A/D Control Register 0 (ADCON0) The 8-bit Analog-to-Digital (A/D) converter module has • A/D Control Register 1 (ADCON1) five inputs for the PIC16C73B and eight for the The ADCON0 register, shown in Register12-1, con- PIC16C74B. trols the operation of the A/D module. The ADCON1 The A/D allows conversion of an analog input signal to register, shown in Register12-2, configures the func- a corresponding 8-bit digital number. The output of the tions of the port pins. The port pins can be configured sample and hold is the input into the converter, which as analog inputs (RA3 can also be a voltage reference), generates the result via successive approximation. The or as digital I/O. analog reference voltage is software selectable to Additional information on using the A/D module can be either the device’s positive supply voltage (VDD), or the found in the PIC® Mid-Range MCU Family Reference voltage level on the RA3/AN3/VREF pin. Manual (DS33023) and in Application Note, AN546. REGISTER 12-1: ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) bit 5-3 CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) 101 = channel 5, (RE0/AN5)(1) 110 = channel 6, (RE1/AN6)(1) 111 = channel 7, (RE2/AN7)(1) bit 2 GO/DONE: A/D Conversion Status bit If ADON = 1: 1 =A/D conversion in progress (setting this bit starts the A/D conversion) 0 =A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) bit 1 Unimplemented: Read as '0' bit 0 ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C74B only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  1998-2013 Microchip Technology Inc. DS30605D-page 79

PIC16C63A/65B/73B/74B REGISTER 12-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-3 Unimplemented: Read as '0' bit 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF 000 A A A A A A A A VDD 001 A A A A VREF A A A RA3 010 A A A A A D D D VDD 011 A A A A VREF D D D RA3 100 A A D D A D D D VDD 101 A A D D VREF D D D RA3 11x D D D D D D D D VDD A = Analog input D = Digital I/O Note 1: RE0, RE1 and RE2 are implemented on the PIC16C74B only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30605D-page 80  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B The following steps should be followed for doing an A/D 3. Wait the required acquisition time. conversion: 4. Set GO/DONE bit (ADCON0) to start conversion. 1. Configure the A/D module: 5. Wait for A/D conversion to complete, by either: • Configure analog pins, voltage reference, Polling for the GO/DONE bit to be cleared (if and digital I/O (ADCON1) interrupts are disabled); • Select A/D input channel (ADCON0) OR • Select A/D conversion clock (ADCON0) Waiting for the A/D interrupt. • Turn on A/D module (ADCON0) 6. Read A/D result register (ADRES), clear bit 2. Configure A/D interrupt (if desired): ADIF if required. • Clear ADIF bit (PIR1<6>) 7. For next conversion, go to step 1 or step 2 as • Set ADIE bit (PIE1<6>) required. The A/D conversion time per bit is • Set PEIE bit (INTCON<6>) defined as TAD. A minimum wait of 2TAD is required before next acquisition starts. • Set GIE bit (INTCON<7>) FIGURE 12-1: A/D BLOCK DIAGRAM CHS2:CHS0 111 RE2/AN7(1) 110 RE1/AN6(1) 101 RE0/AN5(1) 100 RA5/AN4 VIN 011 (Input Voltage) RA3/AN3/VREF 010 A/D RA2/AN2 Converter 001 RA1/AN1 000 VDD RA0/AN0 000 or 010 or VREF 100 or 11x (Reference Voltage) 001 or 011 or 101 PCFG2:PCFG0 Note 1: Not available on PIC16C73B.  1998-2013 Microchip Technology Inc. DS30605D-page 81

PIC16C63A/65B/73B/74B 12.1 A/D Acquisition Requirements The maximum recommended impedance for ana- log sources is 10k. After the analog input channel is For the A/D converter to meet its specified accuracy, selected (changed), the acquisition time (TACQ) must the charge holding capacitor (CHOLD) must be allowed pass before the conversion can be started. to fully charge to the input channel voltage level. The To calculate the minimum acquisition time, analog input model is shown in Figure12-2. The Equation12-1 may be used. This equation assumes source impedance (RS) and the internal sampling that 1/2 LSb error is used (512 steps for the A/D). The switch (RSS) impedance directly affect the time 1/2 LSb error is the maximum error allowed for the A/D required to charge the capacitor CHOLD. The sampling to meet its specified resolution. switch (RSS) impedance varies over the device voltage (VDD), Figure12-2. The source impedance affects the For more information, see the PIC® Mid-Range MCU offset voltage at the analog input (due to pin leakage Family Reference Manual (DS33023). In general, how- current). ever, given a maximum source impedance of 10k and a worst case temperature of 100°C, TACQ will be no more than 16 sec. FIGURE 12-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6 V Rs ANx RIC £ 1k SS RSS CHOLD VA CPIN I leakage = DAC capacitance 5 pF VT = 0.6 V ± 500 nA = 51.2 pF VSS Legend: CPIN = input capacitance 6V VT = threshold voltage 5V I leakage = leakage current at the pin due to VDD 4V various junctions 3V 2V RIC = interconnect resistance SS = sampling switch 5 6 7 891011 CHOLD = sample/hold capacitance (from DAC) Sampling Switch (k) EQUATION 12-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF TAMP = 5S TC = - (51.2pF)(1k + RSS + RS) In(1/511) TCOFF = (Temp -25C)(0.05S/C) DS30605D-page 82  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 12.2 Selecting the A/D Conversion 12.5 A/D Operation During SLEEP Clock The A/D module can operate during SLEEP mode. This The A/D conversion time per bit is defined as TAD. The requires that the A/D clock source be set to RC A/D conversion requires 9.5 TAD per 8-bit conversion. (ADCS1:ADCS0 = 11). When the RC clock source is The source of the A/D conversion clock is software selected, the A/D module waits one instruction cycle selectable. The four possible options for TAD are: before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital • 2 TOSC switching noise from the conversion. When the conver- • 8 TOSC sion is completed, the GO/DONE bit will be cleared, • 32 TOSC and the result loaded into the ADRES register. If the • Internal RC oscillator (2 - 6 S) A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D mod- For correct A/D conversions, the A/D conversion clock ule will then be turned off, although the ADON bit will (TAD) must be selected to ensure a minimum TAD time remain set. (parameter #130). When the A/D clock source is another clock option (not 12.3 Configuring Analog Port Pins RC), a SLEEP instruction will cause the present conver- sion to be aborted and the A/D module to be turned off, The ADCON1, TRISA and TRISE registers control the though the ADON bit will remain set. operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- Turning off the A/D places the A/D module in its lowest ing TRIS bits set (input). If the TRIS bit is cleared (out- current consumption state. put), the digital output level (VOH or VOL) will be Note: For the A/D module to operate in SLEEP, converted. the A/D clock source must be set to RC The A/D operation is independent of the state of the (ADCS1:ADCS0 = 11). To perform an A/D CHS2:CHS0 bits and the TRIS bits. conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruc- Note 1: When reading the port register, all pins tion that sets the GO/DONE bit. configured as analog input channels will read as cleared (a low level). Pins config- 12.6 Effects of a RESET ured as digital inputs will convert an ana- log input. Analog levels on a digitally A device RESET forces all registers to their RESET configured input will not affect the conver- state. The A/D module is disabled and any conversion sion accuracy. in progress is aborted. All pins with analog functions are configured as analog inputs. 2: Analog levels on any pin that is defined as a digital input, but not as an analog input, The ADRES register will contain unknown data after a may cause the input buffer to consume Power-on Reset. current that is out of the devices specifi- 12.7 Use of the CCP Trigger cation. 3: The TRISE register is not provided on the An A/D conversion can be started by the “special event PIC16C73B. trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- 12.4 A/D Conversions grammed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the Note: The GO/DONE bit should NOT be set in GO/DONE bit will be set, starting the A/D conversion, the same instruction that turns on the A/D. and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period Clearing the GO/DONE bit during a conversion will with minimal software overhead (moving the ADRES to abort the current conversion. The ADRES register will the desired location). The appropriate analog input NOT be updated with the partially completed A/D con- channel must be selected and the minimum acquisition version sample. That is, the ADRES register will con- done before the “special event trigger” sets the tinue to contain the value of the last completed GO/DONE bit (starts a conversion). conversion (or the last value written to the ADRES reg- ister). After the A/D conversion is aborted, a 2TAD wait If the A/D module is not enabled (ADON is cleared), is required before the next acquisition is started. After then the “special event trigger” will be ignored by the this 2TAD wait, an acquisition is automatically started A/D module, but will still reset the Timer1 counter. on the selected channel. The GO/DONE bit can then be set to start another conversion.  1998-2013 Microchip Technology Inc. DS30605D-page 83

PIC16C63A/65B/73B/74B TABLE 12-1: SUMMARY OF A/D REGISTERS (PIC16C73B/74B ONLY) Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP1IF ---- ---0 ---- ---0 8Dh PIE2 — — — — — — — CCP1IE ---- ---0 ---- ---0 1Eh ADRES A/D Result register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction register --11 1111 --11 1111 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C63A/73B; always maintain these bits clear. DS30605D-page 84  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 13.0 SPECIAL FEATURES OF THE timers that offer necessary delays on power-up. One is CPU the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The What sets a microcontroller apart from other proces- other is the Power-up Timer (PWRT), which provides a sors are special circuits to deal with the needs of real- fixed delay of 72ms (nominal) on power-up only and is time applications. The PIC16CXX family has a host of designed to keep the part in RESET, while the power such features intended to maximize system reliability, supply stabilizes. With these two timers on-chip, most minimize cost through elimination of external compo- applications need no external RESET circuitry. nents, provide power saving operating modes and offer SLEEP mode is designed to offer a very low current code protection. These are: power-down mode. The user can wake-up from SLEEP • Oscillator selection through external RESET, WDT wake-up or through an • RESET interrupt. - Power-on Reset (POR) Several oscillator options are also made available to - Power-up Timer (PWRT) allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option - Oscillator Start-up Timer (OST) saves power. A set of configuration bits are used to - Brown-out Reset (BOR) select various options. • Interrupts • Watchdog Timer (WDT) 13.1 Configuration Bits • SLEEP The configuration bits can be programmed (read as '0') • Code protection or left unprogrammed (read as '1') to select various • ID locations device configurations. These bits are mapped in pro- • In-Circuit Serial Programming (ICSP) gram memory location 2007h. The PIC16CXX has a Watchdog Timer which can be The user will note that address 2007h is beyond the shut off only through configuration bits. It runs off its user program memory space, and can be accessed own RC oscillator for added reliability. There are two only during programming. REGISTER 13-1: CONFIGURATION WORD (CONFIG 2007h) CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 bit 13 bit 0 bits 13-8, CP1:CP0: Code Protection bits(2) 5-4 11 =Code protection off 10 =Upper half of program memory code protected 01 =Upper 3/4th of program memory code protected 00 =All memory is code protected bit 7 Unimplemented: Read as '1' bit 6 BODEN: Brown-out Reset Enable bit(1) 1 = BOR enabled 0 = BOR disabled bit 3 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 =RC oscillator 10 =HS oscillator 01 =XT oscillator 00 =LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of PWRTE. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.  1998-2013 Microchip Technology Inc. DS30605D-page 85

PIC16C63A/65B/73B/74B 13.2 Oscillator Configurations FIGURE 13-1: CRYSTAL/CERAMIC RESONATOR OPERATION 13.2.1 OSCILLATOR TYPES (HS, XT OR LP OSC CONFIGURATION) The PIC16CXX can be operated in four different oscil- lator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four OSC1 To internal modes: logic C1 • LP Low Power Crystal XTAL SLEEP • XT Crystal/Resonator RF PIC16CXX OSC2 • HS High Speed Crystal/Resonator RS • RC Resistor/Capacitor C2 (Note 1) 13.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS See Table13-1 and Table13-2 for recommended values of C1 and C2. In XT, LP, or HS modes, a crystal or ceramic resonator Note 1: A series resistor may be required for AT strip cut crystals. is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure13-1). The PIC16CXX oscillator design requires the use of a par- FIGURE 13-2: EXTERNAL CLOCK INPUT allel cut crystal. Use of a series cut crystal may give a OPERATION (HS, XT OR frequency out of the crystal manufacturers specifica- LP OSC CONFIGURATION) tions. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure13-2). See the PIC® Mid-Range Clock from OSC1 MCU Reference Manual (DS33023) for details on ext. system PIC16CXX building an external oscillator. Open OSC2 DS30605D-page 86  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 13-1: CERAMIC RESONATORS Note 1: Higher capacitance increases the stability Ranges Tested: of the oscillator, but also increases the Mode Freq OSC1 OSC2 start-up time. XT 455 kHz 68 - 100 pF 68 - 100 pF 2: Since each resonator/crystal has its own 2.0 MHz 15 - 68 pF 15 - 68 pF characteristics, the user should consult 4.0 MHz 15 - 68 pF 15 - 68 pF the resonator/crystal manufacturer for HS 8.0 MHz 10 - 68 pF 10 - 68 pF appropriate values of external compo- 16.0 MHz 10 - 22 pF 10 - 22 pF nents. Note: These values are for design guidance only. 3: Rs may be required in HS mode, as well See notes following Table13-1 and Table13-2. as XT mode, to avoid overdriving crystals Resonators Used: with low drive level specification. 455 kHz Panasonic EFO-A455K04B ± 0.3% 4: Oscillator performance should be verified 2.0 MHz Murata Erie CSA2.00MG ± 0.5% at the expected voltage and temperature extremes in which the application is 4.0 MHz Murata Erie CSA4.00MG ± 0.5% expected to operate. 8.0 MHz Murata Erie CSA8.00MT ± 0.5% 13.2.3 RC OSCILLATOR 16.0 MHz Murata Erie CSA16.00MX ± 0.5% Note: Resonators used did not have built-in capacitors. For timing insensitive applications, the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resis- TABLE 13-2: CAPACITOR SELECTION FOR tor (REXT) and capacitor (CEXT) values, and the operat- CRYSTAL OSCILLATOR ing temperature. The oscillator frequency will vary from unit to unit due to normal process variation. The differ- Osc Type Crystal Cap. Range Cap. Range ence in lead frame capacitance between package Freq C1 C2 types will also affect the oscillation frequency, espe- LP 32 kHz 33 pF 33 pF cially for low CEXT values. The user also needs to take into account variation due to tolerance of external R 200 kHz 15 pF 15 pF and C components used. Figure13-3 shows how the XT 200 kHz 47-68 pF 47-68 pF R/C combination is connected to the PIC16CXX. 1 MHz 15 pF 15 pF The oscillator frequency, divided by 4, is available on 4 MHz 15 pF 15 pF the OSC2/CLKOUT pin, and can be used for test pur- poses or to synchronize other logic (see Figure3-2 for HS 4 MHz 15 pF 15 pF waveform). 8 MHz 15-33 pF 15-33 pF FIGURE 13-3: RC OSCILLATOR MODE 20 MHz 15-33 pF 15-33 pF Note: These values are for design guidance only. VDD See notes following Table13-1 and Table13-2. Crystals Used: REXT Internal OSC1 32 kHz Epson C-001R32.768K-A ± 20 PPM Clock 200 kHz STD XTL 200.000KHz ± 20 PPM CEXT PIC16CXX 1 MHz ECS ECS-10-13-1 ± 50 PPM VSS OSC2/CLKOUT 4 MHz ECS ECS-40-20-1 ± 50 PPM FOSC/4 8 MHz EPSON CA-301 8.000M-C ± 30 PPM Recommended Values:REXT = 3 kW to 100 kW 20 MHz EPSON CA-301 20.000M-C ± 30 PPM CEXT = 20 pf to 30 pF  1998-2013 Microchip Technology Inc. DS30605D-page 87

PIC16C63A/65B/73B/74B 13.3 RESET on MCLR Reset during SLEEP, and on BOR. The TO and PD bits are set or cleared differently in different The PIC16CXX differentiates between various kinds of RESET situations, as indicated in Table13-4. These RESET: bits are used in software to determine the nature of the • Power-on Reset (POR) RESET. See Table13-6 for a full description of RESET • MCLR Reset during normal operation states of all registers. • MCLR Reset during SLEEP A simplified block diagram of the on-chip RESET circuit • WDT Reset (normal operation) is shown in Figure13-4. • Brown-out Reset (BOR) The PIC devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small Some registers are not affected in any RESET condi- pulses. tion; their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a It should be noted that internal RESET sources do not “RESET state” on POR, on the MCLR and WDT Reset, drive MCLR pin low. FIGURE 13-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External RESET MCLR SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Reset S BODEN OST/PWRT OST Chip Reset 10-bit Ripple Counter R Q OSC1 (Note 1) PWRT On-chip RC OSC 10-bit Ripple Counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. DS30605D-page 88  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 13.4 RESETS 13.4.4 BROWN-OUT RESET (BOR) The configuration bit, BODEN, can enable or disable 13.4.1 POWER-ON RESET (POR) the Brown-out Reset circuit. If VDD falls below VBOR A Power-on Reset pulse is generated on-chip when (parameter D005, about 4V) for longer than TBOR VDD rise is detected (parameters D003 and D004, in (parameter #35, about 100S), the brown-out situation the range of 1.5V - 2.1V). To take advantage of the will reset the device. If VDD falls below VBOR for less POR, just tie the MCLR pin directly (or through a resis- than TBOR, a RESET may not occur. tor) to VDD. This will eliminate external RC components Once the brown-out occurs, the device will remain in usually needed to create a POR. Brown-out Reset until VDD rises above VBOR. The When the device starts normal operation (exits the Power-up Timer then keeps the device in RESET for RESET condition), device operating parameters (volt- TPWRT (parameter #33, about 72mS). If VDD should fall age, frequency, temperature) must be met to ensure below VBOR during TPWRT, the Brown-out Reset pro- operation. If these conditions are not met, the device cess will restart when VDD rises above VBOR with the must be held in RESET until the operating conditions Power-up Timer Reset. The Power-up Timer is always are met. The device may be held in RESET by keeping enabled when the Brown-out Reset circuit is enabled, MCLR at Vss. regardless of the state of the PWRT configuration bit. For additional information, refer to Application Note 13.4.5 TIME-OUT SEQUENCE AN607, “Power-up Trouble Shooting.” On power-up, the time-out sequence is as follows: the 13.4.2 POWER-UP TIMER (PWRT) PWRT delay starts (if enabled) when a POR occurs. Then, OST starts counting 1024 oscillator cycles when The Power-up Timer provides a fixed 72 ms nominal PWRT ends (LP, XT, HS). When the OST ends, the time-out on power-up from the POR. The PWRT oper- device comes out of RESET. ates on an internal RC oscillator. The device is kept in RESET as long as the PWRT is active. The PWRT’s If MCLR is kept low long enough, the time-outs will time delay allows VDD to rise to an acceptable level. A expire. Bringing MCLR high will begin execution imme- configuration bit is provided to enable/disable the diately. This is useful for testing purposes or to synchro- PWRT. nize more than one PIC16CXX device operating in parallel. The power-up time delay will vary from chip to chip, due to VDD, temperature and process variation. See DC Table13-5 shows the RESET conditions for the parameters for details (TPWRT, parameter #33). STATUS, PCON and PC registers, while Table13-6 shows the RESET conditions for all the registers. 13.4.3 OSCILLATOR START-UP TIMER (OST) 13.4.6 POWER CONTROL/STATUS REGISTER (PCON) The Oscillator Start-up Timer provides a delay of 1024 oscillator cycles (from OSC1 input) after the PWRT The Brown-out Reset Status bit, BOR, is unknown on a delay, if enabled. This helps to ensure that the crystal POR. It must be set by the user and checked on sub- oscillator or resonator has started and stabilized. sequent RESETS to see if bit BOR was cleared, indi- cating a BOR occurred. The BOR bit is not predictable The OST time-out is invoked only for XT, LP and HS if the Brown-out Reset circuitry is disabled. modes and only on Power-on Reset or wake-up from SLEEP. The Power-on Reset Status bit, POR, is cleared on a POR and unaffected otherwise. The user must set this bit following a POR and check it on subsequent RESETS to see if it has been cleared.  1998-2013 Microchip Technology Inc. DS30605D-page 89

PIC16C63A/65B/73B/74B TABLE 13-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Oscillator Configuration Brown-out Wake-up from SLEEP PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — TABLE 13-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP Legend: x = don’t care, u = unchanged TABLE 13-5: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 000x xuuu ---- --u0 Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). REGISTER 13-2: STATUS REGISTER IRP RP1 RP0 TO PD Z DC C REGISTER 13-3: PCON REGISTER — — — — — — POR BOR DS30605D-page 90  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset MCLR Resets Wake-up via WDT or Register Applicable Devices Brown-out Reset WDT Reset Interrupt W 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu INDF 63A 65B 73B 74B N/A N/A N/A TMR0 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PCL 63A 65B 73B 74B 0000h 0000h PC + 1(2) STATUS 63A 65B 73B 74B 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTA 63A 65B 73B 74B --0x 0000 --0u 0000 --uu uuuu PORTB 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTC 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTD 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTE 63A 65B 73B 74B ---- -xxx ---- -uuu ---- -uuu PCLATH 63A 65B 73B 74B ---0 0000 ---0 0000 ---u uuuu INTCON 63A 65B 73B 74B 0000 000x 0000 000u uuuu uuuu(1) 63A 65B 73B 74B -0-- 0000 -0-- 0000 -u-- uuuu(1) 63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu(1) PIR1 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu(1) 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu(1) PIR2 63A 65B 73B 74B ---- ---0 ---- ---0 ---- ---u(1) TMR1L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu T1CON 63A 65B 73B 74B --00 0000 --uu uuuu --uu uuuu TMR2 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu T2CON 63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu SSPBUF 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu CCPR1L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu RCSTA 63A 65B 73B 74B 0000 -00x 0000 -00x uuuu -uuu TXREG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu RCREG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu CCPR2L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu ADRES 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table13-5 for RESET value for specific condition.  1998-2013 Microchip Technology Inc. DS30605D-page 91

PIC16C63A/65B/73B/74B TABLE 13-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset MCLR Resets Wake-up via WDT or Register Applicable Devices Brown-out Reset WDT Reset Interrupt ADCON0 63A 65B 73B 74B 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISA 63A 65B 73B 74B --11 1111 --11 1111 --uu uuuu TRISB 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISC 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISD 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISE 63A 65B 73B 74B 0000 -111 0000 -111 uuuu -uuu 63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu 63A 65B 73B 74B 0-00 0000 0-00 0000 u-uu uuuu PIE1 63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu PIE2 63A 65B 73B 74B ---- ---0 ---- ---0 ---- ---u PCON 63A 65B 73B 74B ---- --0q(3) ---- --uu ---- --uu PR2 63A 65B 73B 74B 1111 1111 1111 1111 1111 1111 SSPADD 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu SSPSTAT 63A 65B 73B 74B --00 0000 --00 0000 --uu uuuu TXSTA 63A 65B 73B 74B 0000 -010 0000 -010 uuuu -uuu SPBRG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu ADCON1 63A 65B 73B 74B ---- -000 ---- -000 ---- -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table13-5 for RESET value for specific condition. DS30605D-page 92  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 13.5 Interrupts Note: If an interrupt occurs while the Global Inter- rupt Enable (GIE) bit is being cleared, the The Interrupt Control register (INTCON) records indi- GIE bit may unintentionally be re-enabled vidual interrupt requests in flag bits. It also has individ- by the user’s Interrupt Service Routine (the ual and global interrupt enable bits. RETFIE instruction). The events that Note: Individual interrupt flag bits are set, regard- would cause this to occur are: less of the status of their corresponding 1. An instruction clears the GIE bit while an mask bit, or the GIE bit. interrupt is acknowledged. A global interrupt enable bit, GIE (INTCON<7>), 2. The program branches to the interrupt enables (if set) all unmasked interrupts, or disables (if vector and executes the Interrupt cleared) all interrupts. When bit GIE is enabled, and an Service Routine. interrupt’s flag bit and mask bit are set, the interrupt will 3. The Interrupt Service Routine completes vector immediately. Individual interrupts can be dis- the execution of the RETFIE instruction. abled through their corresponding enable bits in vari- This causes the GIE bit to be set ous registers. Individual interrupt bits are set, (enables interrupts), and the program regardless of the status of the GIE bit. The GIE bit is returns to the instruction after the one cleared on RESET. which was meant to disable interrupts. The “return from interrupt” instruction, RETFIE, exits Perform the following to ensure that inter- the interrupt routine, as well as sets the GIE bit, which rupts are globally disabled: re-enables interrupts. LOOP BCF INTCON, GIE ; Disable global The RB0/INT pin interrupt, the RB port change interrupt ; interrupt bit and the TMR0 overflow interrupt flags are contained in BTFSC INTCON, GIE ; Global interrupt the INTCON register. ; disabled? GOTO LOOP ; NO, try again The peripheral interrupt flags are contained in the spe- : ; Yes, continue cial function registers PIR1 and PIR2. The correspond- ; with program ing interrupt enable bits are contained in special ; flow function registers PIE1 and PIE2 and the peripheral interrupt enable bit is contained in special function reg- ister INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack, and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or the GIE bit.  1998-2013 Microchip Technology Inc. DS30605D-page 93

PIC16C63A/65B/73B/74B FIGURE 13-5: INTERRUPT LOGIC PSPIF PSPIE ADIF T0IF Wake-up (If in SLEEP mode) ADIE T0IE RCIF INTF RCIE INTE Interrupt to CPU TXIF RBIF TXIE RBIE SSPIF SSPIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF PIC16C63A Yes Yes Yes – – Yes Yes Yes Yes Yes Yes Yes PIC16C65B Yes Yes Yes Yes – Yes Yes Yes Yes Yes Yes Yes PIC16C73B Yes Yes Yes – Yes Yes Yes Yes Yes Yes Yes Yes PIC16C74B Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 13.5.1 INT INTERRUPT 13.5.3 PORTB INTERRUPT-ON-CHANGE The external interrupt on RB0/INT pin is edge trig- An input change on PORTB<7:4> sets flag bit RBIF gered: either rising if bit INTEDG (OPTION_REG<6>) (INTCON<0>). The interrupt can be enabled/disabled is set, or falling if the INTEDG bit is clear. When a valid by setting/clearing enable bit RBIE (INTCON<4>). edge appears on the RB0/INT pin, flag bit INTF (Section5.2) (INTCON<1>) is set. This interrupt can be disabled by Note: If a change on the I/O pin should occur clearing enable bit INTE (INTCON<4>). Flag bit INTF when the read operation is being executed must be cleared in software in the Interrupt Service (start of the Q2 cycle), then the RBIF inter- Routine before re-enabling this interrupt. The INT inter- rupt flag may not get set. rupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the pro- cessor branches to the interrupt vector following wake- up. See Section13.8 for details on SLEEP mode. 13.5.2 TMR0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (see Section6.0). DS30605D-page 94  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 13.6 Context Saving During Interrupts The example: a) Stores the W register. During an interrupt, only the return PC value is saved on the stack. Users may wish to save key registers dur- b) Stores the STATUS register in bank 0. ing an interrupt i.e., W register and STATUS register. c) Stores the PCLATH register. This will have to be implemented in software. d) Executes the ISR code. Example13-1 stores and restores the STATUS, W, and e) Restores the STATUS register PCLATH registers. The register W_TEMP must be (and bank select bit). defined in each bank and must be defined at the same f) Restores the W and PCLATH registers. offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). EXAMPLE 13-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W : (ISR) ;User ISR code goes here : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP, W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W 13.7 Watchdog Timer (WDT) 13.7.1 WDT PERIOD The Watchdog Timer is a free running on-chip RC oscil- The WDT has a nominal time-out period of 18 ms lator, which does not require any external components. (parameter #31, TWDT). The time-out periods vary with This RC oscillator is separate from the RC oscillator of temperature, VDD, and process variations. If longer the OSC1/CLKIN pin. The WDT will run, even if the time-out periods are desired, a prescaler with a division clock on the OSC1/CLKIN and OSC2/CLKOUT pins of ratio of up to 1:128 can be assigned to the WDT under the device has been stopped, for example, by execu- software control, by writing to the OPTION register. tion of a SLEEP instruction. Time-out periods up to 128 TWDT can be realized. During normal operation, a WDT time-out generates a The CLRWDT and SLEEP instructions clear the WDT device RESET (Watchdog Timer Reset). If the device is and the postscaler, if assigned to the WDT. In addition, in SLEEP mode, a WDT time-out causes the device to the SLEEP instruction prevents the WDT from generat- wake-up and resume normal operation (Watchdog ing a RESET, but will allow the WDT to wake the device Timer Wake-up). from SLEEP mode. The WDT can be permanently disabled by clearing The TO bit in the STATUS register will be cleared upon configuration bit WDTE (Section13.1). a WDT time-out.  1998-2013 Microchip Technology Inc. DS30605D-page 95

PIC16C63A/65B/73B/74B 13.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., and max. WDT prescaler), it may take several seconds before a WDT time-out occurs. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. FIGURE 13-6: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure6-1) 0 M Postscaler 1 WDT Timer U X 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 MUX (Figure6-1) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION register. TABLE 13-7: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits – BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register13-1 for operation of these bits. DS30605D-page 96  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 13.8 Power-down Mode (SLEEP) Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip Q clocks are present. Power-down mode is entered by executing a SLEEP When the SLEEP instruction is being executed, the next instruction. instruction (PC + 1) is pre-fetched. For the device to If enabled, the WDT will be cleared but keeps running, wake-up through an interrupt event, the corresponding the PD bit (STATUS<3>) is cleared, the TO (STA- interrupt enable bit must be set (enabled). Wake-up is TUS<4>) bit is set, and the oscillator driver is turned off. regardless of the state of the GIE bit. If the GIE bit is The I/O ports maintain the status they had, before the clear (disabled), the device continues execution at the SLEEP instruction was executed (driving high, low, or instruction after the SLEEP instruction. If the GIE bit is hi-impedance). set (enabled), the device executes the instruction after For lowest current consumption in this mode, place all the SLEEP instruction and then branches to the inter- I/O pins at either VDD or VSS, ensure no external cir- rupt address (0004h). In cases where the execution of cuitry is drawing current from the I/O pin, power-down the instruction following SLEEP is not desirable, the the A/D, and disable external clocks. Pull all I/O pins user should have a NOP after the SLEEP instruction. that are hi-impedance inputs, high or low externally, to 13.8.2 WAKE-UP USING INTERRUPTS avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest When global interrupts are disabled (GIE cleared) and current consumption. The contribution from on-chip any interrupt source has both its interrupt enable bit pull-ups on PORTB should also be considered. and interrupt flag bit set, one of the following will occur: The MCLR pin must be at a logic high level (VIHMC). • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will com- 13.8.1 WAKE-UP FROM SLEEP plete as a NOP. Therefore, the WDT and WDT The device can wake up from SLEEP through one of postscaler will not be cleared, the TO bit will not the following events: be set and PD bit will not be cleared. 1. External RESET input on MCLR pin. • If the interrupt occurs during or after the execu- tion of a SLEEP instruction, the device will imme- 2. Watchdog Timer Wake-up (if WDT was diately wake up from sleep. The SLEEP enabled). instruction will be completely executed before the 3. Interrupt from INT pin, RB port change or a wake-up. Therefore, the WDT and WDT Peripheral Interrupt. postscaler will be cleared, the TO bit will be set External MCLR Reset will cause a device RESET. All and the PD bit will be cleared. other events are considered a continuation of program Even if the flag bits were checked before executing a execution and cause a “wake-up”. The TO and PD bits SLEEP instruction, it may be possible for flag bits to in the STATUS register can be used to determine the become set before the SLEEP instruction completes. To cause of device RESET. The PD bit, which is set on determine whether a SLEEP instruction executed, test power-up, is cleared when SLEEP is invoked. The TO the PD bit. If the PD bit is set, the SLEEP instruction bit is cleared if a WDT time-out occurred (and caused was executed as a NOP. wake-up). To ensure that the WDT is cleared, a CLRWDT instruc- The following peripheral interrupts can wake the device tion should be executed before a SLEEP instruction. from SLEEP: 1. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 2. SSP (START/STOP) bit detect interrupt. 3. SSP transmit or receive in Slave mode (SPI/I2C). 4. CCP Capture mode interrupt. 5. Parallel Slave port read or write (PIC16C65B/74B only). 6. A/D conversion (when A/D clock source is RC). 7. USART TX or RX (Synchronous Slave mode).  1998-2013 Microchip Technology Inc. DS30605D-page 97

PIC16C63A/65B/73B/74B FIGURE 13-7: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin I(NINTTFC FOlaNg<1>) Interrupt Latency(2) GIE bit Processor in (INTCON<7>) SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h IFnesttcruhcetdion Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024Tosc (drawing not to scale). This delay is not present in RC osc mode. 3: GIE = '1' assumed. After wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 13.9 Program Verification/Code The device is placed into a Program/Verify mode by Protection holding the RB6 and RB7 pins low, while raising the MCLR (VPP) pin from VIL to VIHH (see programming If the code protection bit(s) have not been pro- specification). RB6 becomes the programming clock grammed, the on-chip program memory can be read and RB7 becomes the programming data. Both RB6 out for verification purposes. and RB7 are Schmitt Trigger inputs in this mode. Note: Microchip does not recommend code pro- After RESET, to place the device into Programming/ tecting windowed devices. Devices that Verify mode, the program counter (PC) is at location are code protected may be erased, but not 00h. A 6-bit command is then supplied to the device. programmed again. Depending on the command, 14 bits of program data are then supplied to or from the device, depending if the 13.10 ID Locations command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Four memory locations (2000h - 2003h) are designated Programming Specifications (Literature #DS30228). as ID locations where the user can store checksum or other code identification numbers. These locations are FIGURE 13-8: TYPICAL IN-CIRCUIT not accessible during normal execution, but are read- SERIAL PROGRAMMING able and writable during program/verify. It is recom- CONNECTION mended that only the four least significant bits of the ID location are used. To Normal Connections 13.11 In-Circuit Serial Programming External Connector PIC16CXX Signals PIC16CXX microcontrollers can be serially pro- grammed while in the end application circuit. This is +5V VDD simply done with two lines for clock and data, and three 0V VSS other lines for power, ground and the programming VPP MCLR/VPP voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the CLK RB6 microcontroller just before shipping the product. This also allows the most recent firmware or a custom firm- Data I/O RB7 ware to be programmed. VDD To Normal Connections DS30605D-page 98  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 14.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped into three basic categories: Each PIC16CXX instruction is a 14-bit word divided • Byte-oriented operations into an OPCODE, which specifies the instruction type and one or more operands, which further specify the • Bit-oriented operations operation of the instruction. The PIC16CXX instruction • Literal and control operations set summary in Table14-2 lists byte-oriented, bit-ori- All instructions are executed within one single instruc- ented, and literal and control operations. Table14-1 tion cycle, unless a conditional test is true or the pro- shows the opcode field descriptions. gram counter is changed as a result of an instruction. For byte-oriented instructions, 'f' represents a file reg- In this case, the execution takes two instruction cycles ister designator and 'd' represents a destination desig- with the second cycle executed as a NOP. One instruc- nator. The file register designator specifies which file tion cycle consists of four oscillator periods. Thus, for register is to be used by the instruction. an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the The destination designator specifies where the result of program counter is changed as a result of an instruc- the operation is to be placed. If 'd' is zero, the result is tion, the instruction execution time is 2 s. placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. Table14-2 lists the instructions recognized by the MPASMTM assembler. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected Figure14-1 shows the general formats that the instruc- by the operation, while 'f' represents the address of the tions can have. file in which the bit is located. Note: To maintain upward compatibility with For literal and control operations, 'k' represents an future PIC16CXX products, do not use the eight or eleven bit constant or literal value. OPTION and TRIS instructions. TABLE 14-1: OPCODE FIELD All examples use the following format to represent a DESCRIPTIONS hexadecimal number: Field Description 0xhh f Register file address (0x00 to 0x7F) where h signifies a hexadecimal digit. W Working register (accumulator) FIGURE 14-1: GENERAL FORMAT FOR b Bit address within an 8-bit file register INSTRUCTIONS k Literal field, constant data or label Byte-oriented file register operations 13 8 7 6 0 Don't care location (= 0 or 1) OPCODE d f (FILE #) The assembler will generate code with x = 0. It is the x recommended form of use for compatibility with all d = 0 for destination W Microchip software tools. d = 1 for destination f Destination select; d = 0: store result in W, f = 7-bit file register address d d = 1: store result in file register f. Default is d = 1 Bit-oriented file register operations label Label name 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) TOS Top-of-Stack PC Program Counter b = 3-bit bit address f = 7-bit file register address PCLATH Program Counter High Latch GIE Global Interrupt Enable bit Literal and control operations WDT Watchdog Timer/Counter TO Time-out bit General 13 8 7 0 PD Power-down bit OPCODE k (literal) Destination either the W register or the specified dest register file location k = 8-bit immediate value [ ] Options ( ) Contents CALL and GOTO instructions only 13 11 10 0  Assigned to OPCODE k (literal) < > Register bit field k = 11-bit immediate value  In the set of italics User defined term (font is courier)  1998-2013 Microchip Technology Inc. DS30605D-page 99

PIC16C63A/65B/73B/74B TABLE 14-2: PIC16CXX INSTRUCTION SET Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0000 0011 Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Note: Additional information on the mid-range instruction set is available in the PICmicroTM Mid-Range MCU Family Reference Manual (DS33023). DS30605D-page 100  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 14.1 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [label] ADDLW k Syntax: [label] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 Operation: (W) + k  (W) d  Status Affected: C, DC, Z Operation: (W) .AND. (f)  (destination) Description: The contents of the W register are Status Affected: Z added to the eight bit literal 'k' and the Description: AND the W register with register 'f'. If result is placed in the W register. 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. ADDWF Add W and f BCF Bit Clear f Syntax: [label] ADDWF f,d Syntax: [label] BCF f,b Operands: 0  f  127 Operands: 0  f  127 d  0  b  7 Operation: (W) + (f)  (destination) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit 'b' in register 'f' is cleared. with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. ANDLW AND Literal with W BSF Bit Set f Syntax: [label] ANDLW k Syntax: [label] BSF f,b Operands: 0  k  255 Operands: 0  f  127 Operation: (W) .AND. (k)  (W) 0  b  7 Status Affected: Z Operation: 1  (f<b>) Description: The contents of W register are Status Affected: None AND’ed with the eight bit literal 'k'. Description: Bit 'b' in register 'f' is set. The result is placed in the W register.  1998-2013 Microchip Technology Inc. DS30605D-page 101

PIC16C63A/65B/73B/74B BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [label] BTFSS f,b Syntax: [label] CLRF f Operands: 0  f  127 Operands: 0  f  127 0  b < 7 Operation: 00h  (f) Operation: skip if (f<b>) = 1 1  Z Status Affected: None Status Affected: Z Description: If bit 'b' in register 'f' is '0', the next Description: The contents of register 'f' are cleared instruction is executed. and the Z bit is set. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead making this a 2TCY instruction. BTFSC Bit Test, Skip if Clear CLRW Clear W Syntax: [label] BTFSC f,b Syntax: [ label ] CLRW Operands: 0  f  127 Operands: None 0  b  7 Operation: 00h  (W) Operation: skip if (f<b>) = 0 1  Z Status Affected: None Status Affected: Z Description: If bit 'b' in register 'f' is '1', the next Description: W register is cleared. Zero bit (Z) is instruction is executed. set. If bit 'b', in register 'f', is '0', the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction. CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<4:3>)  PC<12:11> 1  TO Status Affected: None 1  PD Description: Call Subroutine. First, return address Status Affected: TO, PD (PC+1) is pushed onto the stack. The Description: CLRWDT instruction resets the Watch- eleven bit immediate address is dog Timer. It also resets the prescaler loaded into PC bits <10:0>. The upper of the WDT. Status bits TO and PD bits of the PC are loaded from are set. PCLATH. CALL is a two-cycle instruction. DS30605D-page 102  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B COMF Complement f GOTO Unconditional Branch Syntax: [ label ] COMF f,d Syntax: [ label ] GOTO k Operands: 0  f  127 Operands: 0  k  2047 d  [0,1] Operation: k  PC<10:0> Operation: (f)  (destination) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register 'f' are comple- Description: GOTO is an unconditional branch. The mented. If 'd' is 0, the result is stored eleven bit immediate value is loaded in W. If 'd' is 1, the result is stored into PC bits <10:0>. The upper bits of back in register 'f'. PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. DECF Decrement f INCF Increment f Syntax: [label] DECF f,d Syntax: [ label ] INCF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination) Operation: (f) + 1  (destination) Status Affected: Z Status Affected: Z Description: Decrement register 'f'. If 'd' is 0, the Description: The contents of register 'f' are incre- result is stored in the W register. If 'd' mented. If 'd' is 0, the result is placed is 1, the result is stored back in in the W register. If 'd' is 1, the result is register 'f'. placed back in register 'f'. DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register 'f' are decre- Description: The contents of register 'f' are incre- mented. If 'd' is 0, the result is placed mented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is in the W register. If 'd' is 1, the result is placed back in register 'f'. placed back in register 'f'. If the result is 1, the next instruction is If the result is 1, the next instruction is executed. If the result is 0, then a NOP executed. If the result is 0, a NOP is is executed instead making it a 2TCY executed instead making it a 2TCY instruction. instruction.  1998-2013 Microchip Technology Inc. DS30605D-page 103

PIC16C63A/65B/73B/74B IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] IORLW k Syntax: [ label ] MOVLW k Operands: 0  k  255 Operands: 0  k  255 Operation: (W) .OR. k  (W) Operation: k  (W) Status Affected: Z Status Affected: None Description: The contents of the W register are Description: The eight bit literal 'k' is loaded into OR’ed with the eight bit literal 'k'. The W register. The don’t cares will result is placed in the W register. assemble as 0’s. IORWF Inclusive OR W with f MOVWF Move W to f Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: (W)  (f) Operation: (W) .OR. (f)  (destination) Status Affected: None Status Affected: Z Description: Move data from W register to Description: Inclusive OR the W register with regis- register'f'. ter 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0  f  127 Operands: None d  [0,1] Operation: No operation Operation: (f)  (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. DS30605D-page 104  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] RETFIE Syntax: [ label ] RLF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: TOS  PC, 1  GIE Operation: See description below Status Affected: None Status Affected: C Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'. C Register f RETLW Return with Literal in W RRF Rotate Right f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RRF f,d Operands: 0  k  255 Operands: 0  f  127 d  [0,1] Operation: k  (W); TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the eight Description: The contents of register 'f' are rotated bit literal 'k'. The program counter is one bit to the right through the Carry loaded from the top of the stack (the Flag. If 'd' is 0, the result is placed in return address). This is a two-cycle the W register. If 'd' is 1, the result is instruction. placed back in register 'f'. C Register f RETURN Return from Subroutine SLEEP Syntax: [ label ] RETURN Syntax: [ label ] SLEEP Operands: None Operands: None Operation: TOS  PC Operation: 00h  WDT, 0  WDT prescaler, Status Affected: None 1  TO, Description: Return from subroutine. The stack is 0  PD POPed and the top of the stack (TOS) is loaded into the program counter. Status Affected: TO, PD This is a two-cycle instruction. Description: The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section13.8 for more details.  1998-2013 Microchip Technology Inc. DS30605D-page 105

PIC16C63A/65B/73B/74B SUBLW Subtract W from Literal XORLW Exclusive OR Literal with W Syntax: [ label ] SUBLW k Syntax: [label] XORLW k Operands: 0 k 255 Operands: 0 k 255 Operation: k - (W) W) Operation: (W) .XOR. k W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (2’s com- Description: The contents of the W register are plement method) from the eight bit lit- XOR’ed with the eight bit literal 'k'. eral 'k'. The result is placed in the W The result is placed in the W register. register. SUBWF Subtract W from f XORWF Exclusive OR W with f Syntax: [ label ] SUBWF f,d Syntax: [label] XORWF f,d Operands: 0 f 127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - (W) destination) Operation: (W) .XOR. (f) destination) Status Affected: C, DC, Z Status Affected: Z Description: Subtract (2’s complement method) W Description: Exclusive OR the contents of the W register from register 'f'. If 'd' is 0, the register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is result is stored in the W register. If 'd' 1, the result is stored back in register 'f'. is 1, the result is stored back in register 'f'. SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0  f  127 d  [0,1] Operation: (f<3:0>)  (destination<7:4>), (f<7:4>)  (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of regis- ter 'f' are exchanged. If 'd' is 0, the result is placed in W register. If 'd' is 1, the result is placed in register 'f'. DS30605D-page 106  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 15.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) The PIC® microcontrollers are supported with a full range of hardware and software development tools: • One touch assemble (or compile) and download to PIC emulator and simulator tools (automatically • Integrated Development Environment updates all project information) - MPLAB® IDE Software • Debug using: • Assemblers/Compilers/Linkers - source files - MPASMTM Assembler - absolute listing file - MPLAB C17 and MPLAB C18 C Compilers - machine code - MPLINKTM Object Linker/ The ability to use MPLAB IDE with multiple debugging MPLIBTM Object Librarian tools allows users to easily switch from the cost- • Simulators effective simulator to a full-featured emulator with - MPLAB SIM Software Simulator minimal retraining. • Emulators 15.2 MPASM Assembler - MPLAB ICE 2000 In-Circuit Emulator - ICEPIC™ In-Circuit Emulator The MPASM assembler is a full-featured universal • In-Circuit Debugger macro assembler for all PIC MCUs. - MPLAB ICD for PIC16F87X The MPASM assembler has a command line interface • Device Programmers and a Windows shell. It can be used as a stand-alone - PRO MATE® II Universal Device Programmer application on a Windows 3.x or greater system, or it - PICSTART® Plus Entry-Level Development can be used through MPLAB IDE. The MPASM assem- bler generates relocatable object files for the MPLINK Programmer object linker, Intel® standard HEX files, MAP files to • Low Cost Demonstration Boards detail memory usage and symbol reference, an abso- - PICDEMTM 1 Demonstration Board lute LST file that contains source lines and generated - PICDEM 2 Demonstration Board machine code, and a COD file for debugging. - PICDEM 3 Demonstration Board The MPASM assembler features include: - PICDEM 17 Demonstration Board • Integration into MPLAB IDE projects. - KEELOQ® Demonstration Board • User-defined macros to streamline assembly code. 15.1 MPLAB Integrated Development • Conditional assembly for multi-purpose source Environment Software files. The MPLAB IDE software brings an ease of software • Directives that allow complete control over the development previously unseen in the 8-bit microcon- assembly process. troller market. The MPLAB IDE is a Windows®-based application that contains: 15.3 MPLAB C17 and MPLAB C18 C Compilers • An interface to debugging tools - simulator The MPLAB C17 and MPLAB C18 Code Development - programmer (sold separately) Systems are complete ANSI ‘C’ compilers for - emulator (sold separately) Microchip’s PIC17CXXX and PIC18CXXX family of - in-circuit debugger (sold separately) microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not • A full-featured editor found with other compilers. • A project manager For easier source level debugging, the compilers pro- • Customizable toolbar and key mapping vide symbol information that is compatible with the • A status bar MPLAB IDE memory display. • On-line help  1998-2013 Microchip Technology Inc. DS30605D-page 107

PIC16C63A/65B/73B/74B 15.4 MPLINK Object Linker/ 15.6 MPLAB ICE High Performance MPLIB Object Librarian Universal In-Circuit Emulator with MPLAB IDE The MPLINK object linker combines relocatable objects created by the MPASM assembler and the The MPLAB ICE universal in-circuit emulator is intended MPLAB C17 and MPLAB C18 C compilers. It can also to provide the product development engineer with a link relocatable objects from pre-compiled libraries, complete microcontroller design tool set for PIC micro- using directives from a linker script. controllers (MCUs). Software control of the MPLAB ICE The MPLIB object librarian is a librarian for pre- in-circuit emulator is provided by the MPLAB Integrated compiled code to be used with the MPLINK object Development Environment (IDE), which allows editing, linker. When a routine from a library is called from building, downloading and source debugging from a another source file, only the modules that contain that single environment. routine will be linked in with the application. This allows The MPLAB ICE 2000 is a full-featured emulator sys- large libraries to be used efficiently in many different tem with enhanced trace, trigger and data monitoring applications. The MPLIB object librarian manages the features. Interchangeable processor modules allow the creation and modification of library files. system to be easily reconfigured for emulation of differ- The MPLINK object linker features include: ent processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to • Integration with MPASM assembler and MPLAB support new PIC microcontrollers. C17 and MPLAB C18 C compilers. The MPLAB ICE in-circuit emulator system has been • Allows all memory areas to be defined as sections designed as a real-time emulation system, with to provide link-time flexibility. advanced features that are generally found on more The MPLIB object librarian features include: expensive development tools. The PC platform and • Easier linking because single libraries can be Microsoft® Windows environment were chosen to best included instead of many smaller files. make these features available to you, the end user. • Helps keep code maintainable by grouping 15.7 ICEPIC In-Circuit Emulator related modules together. • Allows libraries to be created and modules to be The ICEPIC low cost, in-circuit emulator is a solution added, listed, replaced, deleted or extracted. for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- 15.5 MPLAB SIM Software Simulator Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X The MPLAB SIM software simulator allows code devel- or PIC16CXXX products through the use of inter- opment in a PC-hosted environment by simulating the changeable personality modules, or daughter boards. PIC series microcontrollers on an instruction level. On The emulator is capable of emulating without target any given instruction, the data areas can be examined application circuitry being present. or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execu- tion can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debug- ging using the MPLAB C17 and the MPLAB C18 C com- pilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. DS30605D-page 108  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 15.8 MPLAB ICD In-Circuit Debugger 15.11 PICDEM 1 Low Cost PIC MCU Demonstration Board Microchip's In-Circuit Debugger, MPLAB ICD, is a pow- erful, low cost, run-time development tool. This tool is The PICDEM 1 demonstration board is a simple board based on the FLASH PIC16F87X and can be used to which demonstrates the capabilities of several of develop for this and other PIC microcontrollers from the Microchip’s microcontrollers. The microcontrollers sup- PIC16CXXX family. The MPLAB ICD utilizes the in-cir- ported are: PIC16C5X (PIC16C54 to PIC16C58A), cuit debugging capability built into the PIC16F87X. This PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, feature, along with Microchip's In-Circuit Serial PIC17C42, PIC17C43 and PIC17C44. All necessary ProgrammingTM protocol, offers cost-effective in-circuit hardware and software is included to run basic demo FLASH debugging from the graphical user interface of programs. The user can program the sample microcon- the MPLAB Integrated Development Environment. This trollers provided with the PICDEM 1 demonstration enables a designer to develop and debug source code board on a PROMATE II device programmer, or a by watching variables, single-stepping and setting PICSTART Plus development programmer, and easily break points. Running at full speed enables testing test firmware. The user can also connect the hardware in real-time. PICDEM1 demonstration board to the MPLAB ICE in- circuit emulator and download the firmware to the emu- 15.9 PRO MATE II Universal Device lator for testing. A prototype area is available for the Programmer user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features The PRO MATE II universal device programmer is a include an RS-232 interface, a potentiometer for simu- full-featured programmer, capable of operating in lated analog input, push button switches and eight stand-alone mode, as well as PC-hosted mode. The LEDs connected to PORTB. PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has program- 15.12 PICDEM 2 Low Cost PIC16CXX mable VDD and VPP supplies, which allow it to verify Demonstration Board programmed memory at VDD min and VDD max for max- imum reliability. It has an LCD display for instructions The PICDEM 2 demonstration board is a simple dem- and error messages, keys to enter commands and a onstration board that supports the PIC16C62, modular detachable socket assembly to support various PIC16C64, PIC16C65, PIC16C73 and PIC16C74 package types. In stand-alone mode, the PRO MATE II microcontrollers. All the necessary hardware and soft- device programmer can read, verify, or program PIC ware is included to run the basic demonstration pro- devices. It can also set code protection in this mode. grams. The user can program the sample microcontrollers provided with the PICDEM2 demon- 15.10 PICSTART Plus Entry Level stration board on a PRO MATE II device programmer, Development Programmer or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emula- The PICSTART Plus development programmer is an tor may also be used with the PICDEM 2 demonstration easy-to-use, low cost, prototype programmer. It con- board to test firmware. A prototype area has been pro- nects to the PC via a COM (RS-232) port. MPLAB vided to the user for adding additional hardware and Integrated Development Environment software makes connecting it to the microcontroller socket(s). Some of using the programmer simple and efficient. the features include a RS-232 interface, push button The PICSTART Plus development programmer sup- switches, a potentiometer for simulated analog input, a ports all PIC devices with up to 40 pins. Larger pin serial EEPROM to demonstrate usage of the I2CTM bus count devices, such as the PIC16C92X and and separate headers for connection to an LCD PIC17C76X, may be supported with an adapter socket. module and a keypad. The PICSTART Plus development programmer is CE compliant.  1998-2013 Microchip Technology Inc. DS30605D-page 109

PIC16C63A/65B/73B/74B 15.13 PICDEM 3 Low Cost PIC16CXXX 15.14 PICDEM 17 Demonstration Board Demonstration Board The PICDEM 17 demonstration board is an evaluation The PICDEM 3 demonstration board is a simple dem- board that demonstrates the capabilities of several onstration board that supports the PIC16C923 and Microchip microcontrollers, including PIC17C752, PIC16C924 in the PLCC package. It will also support PIC17C756A, PIC17C762 and PIC17C766. All neces- future 44-pin PLCC microcontrollers with an LCD Mod- sary hardware is included to run basic demo programs, ule. All the necessary hardware and software is which are supplied on a 3.5-inch disk. A programmed included to run the basic demonstration programs. The sample is included and the user may erase it and user can program the sample microcontrollers pro- program it with the other sample programs using the vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or the PICSTART PRO MATE II device programmer, or a PICSTART Plus Plus development programmer, and easily debug and development programmer with an adapter socket, and test the sample code. In addition, the PICDEM17 dem- easily test firmware. The MPLAB ICE in-circuit emula- onstration board supports downloading of programs to tor may also be used with the PICDEM 3 demonstration and executing out of external FLASH memory on board. board to test firmware. A prototype area has been pro- The PICDEM 17 demonstration board is also usable vided to the user for adding hardware and connecting it with the MPLAB ICE in-circuit emulator, or the to the microcontroller socket(s). Some of the features PICMASTER emulator and all of the sample programs include a RS-232 interface, push button switches, a can be run and modified using either emulator. Addition- potentiometer for simulated analog input, a thermistor ally, a generous prototype area is available for user and separate headers for connection to an external hardware. LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 15.15 KEELOQ Evaluation and commons and 12 segments, that is capable of display- Programming Tools ing time, temperature and day of the week. The KEELOQ evaluation and programming tools support PICDEM 3 demonstration board provides an additional Microchip’s HCS Secure Data Products. The HCS eval- RS-232 interface and Windows software for showing uation kit includes a LCD display to show changing the demultiplexed LCD signals on a PC. A simple serial codes, a decoder to decode transmissions and a pro- interface allows the user to construct a hardware gramming interface to program test transmitters. demultiplexer for the LCD signals. DS30605D-page 110  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 15-1: DEVELOPMENT TOOLS FROM MICROCHIP 0152PCM  7. 7 6, XXXFRCM     4, 7 7 3, 7 XXXSCH     72, 5, 6 XXC39 4, //XXXXCC4522   3, 6 6 2, 6 C 2XXC81CIP        6 1 C PI h XX7C71CIP        wit 1) 0 0 4 X4C71CIP        16 V D er ( XX9C61CIP        gg u b e D XX8F61CIP       cuit Cir n- D I X8C61CIP        C ® I B A L XX7C61CIP       MP e h e t s X7C61CIP     *   † † o u w t o h X26F61CIP   ** ** ** on n o ati m XXXC61CIP        or nf or i X6C61CIP     *   † om f c p. hi c X5C61CIP        cro mi ww.e. X0X0X0C4211CCIPIP ®MPLAB IntegratedDevelopment Environment ®MPLAB C17 C Compiler ®MPLAB C18 C Compiler TMMPASM Assembler/ TMMPLINKObject Linker ®MPLAB ICE In-Circuit Emulator TMICEPIC In-Circuit Emulator ®MPLAB ICD In-Circuit Debugger ®PICSTART Plus Entry LevelDevelopment Programmer ®PRO MATE II Universal Device Programmer TMPICDEM 1 Demonstration Board TMPICDEM 2 Demonstration Board TMPICDEM 3 Demonstration Board TMPICDEM 14A Demonstration Board TMPICDEM 17 Demonstration Board ® KLEvaluation KitEEOQ ®KL Transponder KitEEOQ TMmicroID Programmer’s Kit TM125 kHz microID Developer’s Kit TM125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision TMmicroID Developer’s Kit MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site at wContact Microchip Technology Inc. for availability datDevelopment tool is available on select devices. slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***†  1998-2013 Microchip Technology Inc. DS30605D-page 111

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 112  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 16.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2).........................................................................................0V to +13.25V Voltage on RA4 with respect to VSS...............................................................................................................0V to +8.5V Total power dissipation (Note 1)...............................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)...................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. 3: PORTD and PORTE not available on the PIC16C63A/73B. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  1998-2013 Microchip Technology Inc. DS30605D-page 113

PIC16C63A/65B/73B/74B FIGURE 16-1: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V PIC16CXXX-20 4.5 V e g a 4.0 V t l o 3.5 V V 3.0 V 2.5 V 2.0 V 20 MHz Frequency FIGURE 16-2: PIC16LC63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V e PIC16LCXXX-04 g 4.0 V a t l o 3.5 V V 3.0 V 2.5 V 2.0 V 4 MHz 10 MHz Frequency FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application. Note 2: FMAX has a maximum frequency of 10MHz. DS30605D-page 114  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 16-3: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V PIC16CXXX-04 4.5 V e g a 4.0 V t l o 3.5 V V 3.0 V 2.5 V 2.0 V 4 MHz Frequency  1998-2013 Microchip Technology Inc. DS30605D-page 115

PIC16C63A/65B/73B/74B 16.1 DC Characteristics PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial ‡PIC16C63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) ‡PIC16C6A/65B/73B/74B-20 Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. VDD Supply Voltage D001 PIC16LCXXX 2.5 – 5.5 V LP, XT, RC osc modes (DC - 4 MHz) VBOR* – 5.5 V BOR enabled (Note 7) D001 PIC16CXXX 4.0 – 5.5 V XT, RC and LP osc mode D001A 4.5 – 5.5 V HS osc mode VBOR* – 5.5 V BOR enabled (Note 7) D002* VDR RAM Data Retention – 1.5 – V Voltage (Note 1) D003 VPOR VDD Start Voltage to – VSS – V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* SVDD VDD Rise Rate to 0.05 – – V/mS PWRT enabled (PWRTE bit clear) D004A* ensure internal TBD – – V/mS PWRT disabled (PWRTE bit set) Power-on Reset signal See section on Power-on Reset for details D005 VBOR Brown-out Reset 3.65 – 4.35 V BODEN bit set voltage trip point * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. 8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with external clock in RC mode. 9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10:Negative current is defined as current sourced by the pin. DS30605D-page 116  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial ‡PIC16C63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) ‡PIC16C6A/65B/73B/74B-20 Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. IDD Supply Current (Notes 2, 5) D010 PIC16LCXXX – 0.6 2.0 mA XT, RC osc modes: FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A – 22.5 48 A LP osc mode: FOSC = 32 kHz, VDD = 3.0V, WDT disabled D010 PIC16CXXX – 2.7 5 mA XT, RC osc modes: FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 – 7 10 mA HS osc mode: FOSC = 20 MHz, VDD = 5.5V IPD Power-down Current (Notes 3, 5) D020 PIC16LCXXX – 7.5 20 A VDD = 3.0V, WDT enabled, -40°C to +85°C D021 – 0.9 3 A VDD = 3.0V, WDT disabled, 0°C to +70°C D021A – 0.9 3 A VDD = 3.0V, WDT disabled, -40°C to +85°C D020 PIC16CXXX – 10.5 42 A VDD = 4.0V, WDT enabled, -40°C to +85°C D021 – 1.5 16 A VDD = 4.0V, WDT disabled, 0°C to +70°C D021A – 1.5 19 A VDD = 4.0V, WDT disabled, -40°C to +85°C D021B – 2.5 19 A VDD = 4.0V, WDT disabled, -40°C to +125°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. 8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with external clock in RC mode. 9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10:Negative current is defined as current sourced by the pin.  1998-2013 Microchip Technology Inc. DS30605D-page 117

PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial ‡PIC16C63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) ‡PIC16C6A/65B/73B/74B-20 Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Module Differential Current (Note 6) D022* IWDT Watchdog Timer – 6.0 20 A WDTE bit set, VDD = 4.0V D022A* IBOR Brown-out Reset – 100 150 A BODEN bit set, VDD = 5.0 Input Low Voltage VIL I/O ports D030 with TTL buffer VSS – 0.15VDD V For entire VDD range D030A VSS – 0.8V V 4.5V  VDD  5.5V D031 with Schmitt VSS – 0.2VDD V Trigger buffer D032 MCLR, OSC1 Vss – 0.2VDD V (in RC mode) D033 OSC1 (in XT, HS, and Vss – 0.3VDD V (Note 8) LP modes) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. 8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with external clock in RC mode. 9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10:Negative current is defined as current sourced by the pin. DS30605D-page 118  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial ‡PIC16C63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) ‡PIC16C6A/65B/73B/74B-20 Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Input High Voltage VIH I/O ports D040 with TTL buffer 2.0 – VDD V 4.5V  VDD  5.5V D040A 0.25VDD + – VDD V For entire VDD range 0.8V D041 with Schmitt 0.8VDD – VDD V For entire VDD range Trigger buffer D042 MCLR 0.8VDD – VDD V D042A OSC1 (in XT, HS, and 0.7VDD – VDD V (Note 8) LP modes) D043 OSC1 (in RC mode) 0.9VDD – VDD V Input Leakage Current (Notes 9, 10) D060 IIL I/O ports – – ±1 A Vss  VPIN  VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI – – ±5 A Vss  VPIN  VDD D063 OSC1 – – ±5 A Vss  VPIN  VDD, XT, HS and LP osc modes D070 IPURB PORTB Weak Pull-up 50 250 400 A VDD = 5V, VPIN = VSS Current * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. 8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with external clock in RC mode. 9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10:Negative current is defined as current sourced by the pin.  1998-2013 Microchip Technology Inc. DS30605D-page 119

PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial ‡PIC16C63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) ‡PIC16C6A/65B/73B/74B-20 Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Output Low Voltage D080 VOL I/O ports – – 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C – – 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C D083 OSC2/CLKOUT – – 0.6 V IOL = 1.6 mA, VDD = 4.5V, (RC osc mode) -40°C to +85°C – – 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C Output High Voltage D090 VOH I/O ports (Note 10) VDD-0.7 – – V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C VDD-0.7 – – V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C D092 OSC2/CLKOUT VDD-0.7 – – V IOH = -1.3 mA, VDD = 4.5V, (RC osc mode) -40°C to +85°C VDD-0.7 – – V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C D150* VOD Open-Drain – – 8.5 V RA4 pin High Voltage * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. 8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with external clock in RC mode. 9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10:Negative current is defined as current sourced by the pin. DS30605D-page 120  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial ‡PIC16C63A/65B/73B/74B-04 Standard Operating Conditions (unless otherwise stated) ‡PIC16C6A/65B/73B/74B-20 Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin – – 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 – – 50 pF (in RC mode) D102 Cb SCL, SDA – – 400 pF (in I2C mode) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ‡ When specification values of standard devices differ from those of extended voltage devices, they are shown in gray. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. 8: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC device be driven with external clock in RC mode. 9: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 10:Negative current is defined as current sourced by the pin.  1998-2013 Microchip Technology Inc. DS30605D-page 121

PIC16C63A/65B/73B/74B 16.2 AC (Timing) Characteristics 16.2.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition DS30605D-page 122  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 16.2.2 TIMING CONDITIONS The temperature and voltages specified in Table16-1 apply to all timing specifications unless otherwise noted. Figure16-4 specifies the load conditions for the timing specifications. TABLE 16-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C  TA  +70°C for commercial -40°C  TA  +85°C for industrial AC CHARACTERISTICS -40°C  TA  +125°C for extended Operating voltage VDD range as described in DC spec Section16.1. LC parts operate for commercial/industrial temperatures only. FIGURE 16-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSC2/CLKOUT VSS but including D and E outputs as ports CL = 15 pF for OSC2 output Note 1: PORTD and PORTE are not implemented on the PIC16C63A/73B.  1998-2013 Microchip Technology Inc. DS30605D-page 123

PIC16C63A/65B/73B/74B 16.2.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 16-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 1A FOSC External CLKIN Frequency DC — 4 MHz RC and XT osc modes (Note 1) DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 TOSC External CLKIN Period 250 — — ns RC and XT osc modes (Note 1) 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3* TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4* TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. DS30605D-page 124  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 16-6: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure16-4 for load conditions. TABLE 16-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns (Note 1) 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns (Note 1) 12* TckR CLKOUT rise time — 35 100 ns (Note 1) 13* TckF CLKOUT fall time — 35 100 ns (Note 1) 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns (Note 1) 15* TioV2ckH Port in valid before CLKOUT  TOSC + 200 — — ns (Note 1) 16* TckH2ioI Port in hold after CLKOUT  0 — — ns (Note 1) 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* OSC1 (Q2 cycle) to Port PIC16CXX 100 — — ns TosH2ioI input invalid (I/O in hold 18A* PIC16LCXX 200 — — ns time) Port input valid to OSC1(I/O in setup 19* TioV2osH 0 — — ns time) 20* PIC16CXX — 10 40 ns TioR Port output rise time 20A* PIC16LCXX — — 80 ns 21* PIC16CXX — 10 40 ns TioF Port output fall time 21A* PIC16LCXX — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ††These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.  1998-2013 Microchip Technology Inc. DS30605D-page 125

PIC16C63A/65B/73B/74B FIGURE 16-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure16-4 for load conditions. FIGURE 16-8: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Param No. Sym Characteristic Min Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C Watchdog Timer Time-out 31* TWDT 7 18 33 ms VDD = 5V, -40°C to +125°C Period (No Prescaler) Oscillation Start-up Timer 32 TOST — 1024 TOSC — — TOSC = OSC1 period Period 33* TPWRT Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C I/O Hi-impedance from MCLR 34 TIOZ — — 2.1 s Low or WDT Reset 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  BVDD (D005) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30605D-page 126  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 16-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure16-4 for load conditions. TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4,..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16CXX 15 — — ns parameter 47 Prescaler = 2,4,8 PIC16LCXX 25 — — ns Asynchronous PIC16CXX 30 — — ns PIC16LCXX 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16CXX 15 — — ns parameter 47 Prescaler = 2,4,8 PIC16LCXX 25 — — ns Asynchronous PIC16CXX 30 — — ns PIC16LCXX 50 — — ns 47* Tt1P T1CKI input Synchronous PIC16CXX Greater of: — — ns N = prescale value period 30 or TCY + 40 (1, 2, 4, 8) N PIC16LCXX Greater of: N = prescale value 50 or TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16CXX 60 — — ns PIC16LCXX 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1 Delay from external clock edge to timer increment 2TOSC — 7TOSC — * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. DS30605D-page 127

PIC16C63A/65B/73B/74B FIGURE 16-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture mode) 50 51 52 CCPx (Compare or PWM mode) 53 54 Note: Refer to Figure16-4 for load conditions. TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and No Prescaler 0.5TCY + 20 — — ns CCP2 With Prescaler PIC16CXX 10 — — ns input low time PIC16LCXX 20 — — ns 51* TccH CCP1 and No Prescaler 0.5TCY + 20 — — ns CCP2 With Prescaler PIC16CXX 10 — — ns input high time PIC16LCXX 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale N value (1,4, or 16) 53* TccR CCP1 and CCP2 output rise time PIC16CXX — 10 25 ns PIC16LCXX — 25 45 ns 54* TccF CCP1 and CCP2 output fall time PIC16CXX — 10 25 ns PIC16LCXX — 25 45 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30605D-page 128  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 16-11: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure16-4 for load conditions. TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B) Param No. Sym Characteristic Min Typ† Max Units Conditions 62* TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 63* TwrH2dtI WR or CS to data in PIC16CXX 20 — — ns invalid (hold time) PIC16LCXX 35 — — ns 64 TrdL2dtV RD and CS to data out valid — — 80 ns 65* TrdH2dtI RD or CS to data out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1998-2013 Microchip Technology Inc. DS30605D-page 129

PIC16C63A/65B/73B/74B FIGURE 16-12: EXAMPLE SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure16-4 for load conditions. TABLE 16-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=0) Param Symbol Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71 TscH SCK input high time Continuous 1.25TCY + 30 — — ns 71A (Slave mode) Single Byte 40 — — ns (Note 1) 72 TscL SCK input low time Continuous 1.25TCY + 30 — — ns 72A (Slave mode) Single Byte 40 — — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns (Note 1) edge of Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns TscL2diL 75 TdoR SDO data output rise time PIC16CXX — 10 25 ns PIC16LCXX — 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 78 TscR SCK output rise time PIC16CXX — 10 25 ns (Master mode) PIC16LCXX — 20 45 ns 79 TscF SCK output fall time (Master mode) — 10 25 ns 80 TscH2doV, SDO data output valid PIC16CXX — — 50 ns TscL2doV after SCK edge PIC16LCXX — — 100 ns † Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. DS30605D-page 130  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 16-13: EXAMPLE SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure16-4 for load conditions. TABLE 16-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE=1) Param Symbol Characteristic Min Typ† Max Units Conditions No. 71 TscH SCK input high time Continuous 1.25TCY + 30 — — ns 71A (Slave mode) Single Byte 40 — — ns (Note 1) 72 TscL SCK input low time Continuous 1.25TCY + 30 — — ns 72A (Slave mode) Single Byte 40 — — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns (Note 1) edge of Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns TscL2diL 75 TdoR SDO data output rise PIC16CXX — 10 25 ns time PIC16LCXX 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 78 TscR SCK output rise time PIC16CXX — 10 25 ns (Master mode) PIC16LCXX 20 45 ns 79 TscF SCK output fall time (Master mode) — 10 25 ns 80 TscH2doV, SDO data output valid PIC16CXX — — 50 ns TscL2doV after SCK edge PIC16LCXX — 100 ns 81 TdoV2scH, SDO data output setup to SCK edge TCY — — ns TdoV2scL † Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used.  1998-2013 Microchip Technology Inc. DS30605D-page 131

PIC16C63A/65B/73B/74B FIGURE 16-14: EXAMPLE SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 SSDDII MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure16-4 for load conditions. TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE=0) Param Symbol Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71 TscH SCK input high time Continuous 1.25TCY + 30 — — ns 71A (Slave mode) Single Byte 40 — — ns (Note 1) 72 TscL SCK input low time Continuous 1.25TCY + 30 — — ns 72A (Slave mode) Single Byte 40 — — ns (Note 1) 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns (Note 1) edge of Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns TscL2diL 75 TdoR SDO data output rise time PIC16CXX — 10 25 ns PIC16LCXX 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time PIC16CXX — 10 25 ns (Master mode) PIC16LCXX 20 45 ns 79 TscF SCK output fall time (Master mode) — 10 25 ns 80 TscH2doV, SDO data output valid PIC16CXX — — 50 ns TscL2doV after SCK edge PIC16LCXX — 100 ns 83 TscH2ssH, SS  after SCK edge 1.5TCY + 40 — — ns TscL2ssH † Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used. DS30605D-page 132  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 16-15: EXAMPLE SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 SSDDII MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure16-4 for load conditions. TABLE 16-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE=1) Param Symbol Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71 SCK input high time Continuous 1.25TCY + 30 — — ns TscH 71A (Slave mode) Single Byte 40 — — ns (Note 1) 72 SCK input low time Continuous 1.25TCY + 30 — — ns TscL 72A (Slave mode) Single Byte 40 — — ns (Note 1) Last clock edge of Byte1 to the 1st clock 73A TB2B 1.5TCY + 40 — — ns (Note 1) edge of Byte2 TscH2diL, 74 Hold time of SDI data input to SCK edge 100 — — ns TscL2diL SDO data output rise PIC16CXX — 10 25 ns 75 TdoR time PIC16LCXX 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns SCK output rise time PIC16CXX — 10 25 ns 78 TscR (Master mode) PIC16LCXX — 20 45 ns 79 TscF SCK output fall time (Master mode) — 10 25 ns TscH2doV, SDO data output valid PIC16CXX — — 50 ns 80 TscL2doV after SCK edge PIC16LCXX — — 100 ns SDO data output valid PIC16CXX — — 50 ns 82 TssL2doV after SS edge PIC16LCXX — — 100 ns TscH2ssH, 83 SS  after SCK edge 1.5TCY + 40 — — ns TscL2ssH † Data in “Typ” column is at 5 V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Specification 73A is only required if specifications 71A and 72A are used.  1998-2013 Microchip Technology Inc. DS30605D-page 133

PIC16C63A/65B/73B/74B FIGURE 16-16: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure16-4 for load conditions. TABLE 16-12: I2C BUS START/STOP BITS REQUIREMENTS Param Sym Characteristic Min Typ Max Units Conditions No. 90* TSU:STA START condition 100 kHz mode 4700 — — ns Only relevant for Repeated Setup time 400 kHz mode 600 — — START condition 91* THD:STA START condition 100 kHz mode 4000 — — ns After this period the first clock Hold time 400 kHz mode 600 — — pulse is generated 92* TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. FIGURE 16-17: I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure16-4 for load conditions. DS30605D-page 134  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 16-13: I2C BUS DATA REQUIREMENTS Param. Sym Characteristic Min Max Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 103* TF SDA and SCL fall 100 kHz mode — 300 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 90* TSU:STA START condition 100 kHz mode 4.7 — s Only relevant for Repeated setup time START condition 400 kHz mode 0.6 — s 91* THD:STA START condition 100 kHz mode 4.0 — s After this period the first hold time clock pulse is generated 400 kHz mode 0.6 — s 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns 92* TSU:STO STOP condition 100 kHz mode 4.7 — s setup time 400 kHz mode 0.6 — s 109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free before a new transmission 400 kHz mode 1.3 — s can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT=1000 + 250 = 1250 ns (according to the stan- dard mode I2C bus specification) before the SCL line is released.  1998-2013 Microchip Technology Inc. DS30605D-page 135

PIC16C63A/65B/73B/74B FIGURE 16-18: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure16-4 for load conditions. TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 120* TckH2dtV SYNC XMIT (MASTER & PIC16CXX — — 80 ns SLAVE) PIC16LCXX — — 100 ns Clock high to data out valid 121* Tckrf Clock out rise time and fall PIC16CXX — — 45 ns time (Master mode) PIC16LCXX — — 50 ns 122* Tdtrf Data out rise time and fall time PIC16CXX — — 45 ns PIC16LCXX — — 50 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 16-19: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure16-4 for load conditions. TABLE 16-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup 15 — — ns time) 126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30605D-page 136  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE 16-16: A/D CONVERTER CHARACTERISTICS: PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution PIC16CXX — — 8 bits bit VREF = VDD = 5.12 V, VSS  VAIN  VREF PIC16LCXX — — 8 bits bit VREF = VDD = 2.5 V A02 EABS Total Absolute error — — < ± 1 LSb VREF = VDD = 5.12 V, Vss  VAIN  VREF A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12 V, Vss  VAIN  VREF A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12 V, Vss  VAIN  VREF A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12 V, Vss  VAIN  VREF A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12 V, Vss  VAIN  VREF A10 — Monotonicity (Note 3) — guaranteed — — Vss  VAIN  VREF A20 VREF Reference voltage 2.5V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 k analog voltage source A40 IAD A/D conversion PIC16CXX — 180 — A Average current current (VDD) consumption when A/D PIC16LCXX — 90 — A is on (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 A During VAIN acquisition Based on differential of VHOLD to VAIN to charge CHOLD, see Section12.1 During A/D Conversion — — 10 A cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5 V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.  1998-2013 Microchip Technology Inc. DS30605D-page 137

PIC16C63A/65B/73B/74B FIGURE 16-20: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY 134 (TOSC/2)(1) 131 Q4 130 A/D CLK 132 A/D DATA 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1:If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 16-17: A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period PIC16CXX 1.6 — — s TOSC based, VREF  3.0 V PIC16LCXX 2.0 — — s TOSC based, 2.5V  VREF  5.5 V PIC16CXX 2.0 4.0 6.0 s A/D RC mode PIC16LCXX 3.0 6.0 9.0 s A/D RC mode 131 TCNV Conversion time (not including S/H 11 — 11 TAD time) (Note 1) 132 TACQ Acquisition time 5* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 20.0mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert  sample time 1.5 — — TAD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section12.1 for minimum conditions. DS30605D-page 138  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 17.0 DC AND AC The data presented in this section is a statistical sum- CHARACTERISTICS GRAPHS mary of data collected on units from different lots over a period of time. AND TABLES Note: Standard deviation is denoted by sigma (). The graphs and tables provided in this section are for • Typ or Typical represents the mean of the design guidance and are not tested nor guaranteed. In distribution at 25°C. some graphs or tables the data presented is outside • Max or Maximum represents the mean + 3 over specified operating range (e.g., outside specified VDD the temperature range of -40°C to 85°C. range). This is for information only and devices are ensured to operate properly only within the specified • Min or Minimum represents the mean - 3 over range. the temperature range of -40°C to 85°C.  1998-2013 Microchip Technology Inc. DS30605D-page 139

PIC16C63A/65B/73B/74B FIGURE 17-1: TYPICAL IDD vs. FOSC OVER VDD – HS MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 7 6 5 4 A) m 5.5 V (D D 5.0 V I 3 4.5 V 4.0 V 2 3.5 V 3.0 V 1 2.5 V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) FIGURE 17-2: MAXIMUM IDD vs. FOSC OVER VDD – HS MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 7 6 5 5.5 V 4 A) m 5.0 V (D 4.5 V D I 3 4.0 V 2 3.5 V 3.0 V 1 2.5 V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) DS30605D-page 140  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 17-3: TYPICAL IDD vs. FOSC OVER VDD – LP MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 100 90 5.5 V 80 70 5.0 V 60 4.5 V A) (µD 50 D 4.0 V I 40 3.5 V 30 3.0 V 20 2.5 V 10 0 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 17-4: MAXIMUM IDD vs. FOSC OVER VDD – LP MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 160 140 5.5 V 120 100 5.0 V A) (µD 80 4.5 V D I 60 4.0 V 3.5 V 40 3.0 V 2.5 V 20 0 30 40 50 60 70 80 90 100 FOSC (kHz)  1998-2013 Microchip Technology Inc. DS30605D-page 141

PIC16C63A/65B/73B/74B FIGURE 17-5: TYPICAL IDD vs. FOSC OVER VDD – XT MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.4 1.2 5.5 V 1.0 5.0 V 0.8 A) 4.5 V m (D D I 0.6 4.0 V 3.5 V 0.4 3.0 V 2.5 V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 17-6: MAXIMUM IDD vs. FOSC OVER VDD – XT MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.8 1.6 5.5 V 1.4 5.0 V 1.2 4.5 V A) 1.0 m (D 4.0 V D 0.8 I 3.5 V 0.6 3.0 V 2.5 V 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) DS30605D-page 142  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 17-7: AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 20 PF Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 4.5 Not recommended for operation over 4 MHz 4.0 3.3 k 3.5 3.0 Hz) 2.5 5.1 k M (C OS 2.0 F 1.5 10 k 1.0 0.5 100 k 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-8: AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 100 PF Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.5 2.0 3.3 k 1.5 z) H M 5.1 k (C S O F 1.0 10 k 0.5 100 k 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  1998-2013 Microchip Technology Inc. DS30605D-page 143

PIC16C63A/65B/73B/74B FIGURE 17-9: AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 300 PF Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1,000 900 800 700 3.3 k 600 z) H k (SC 500 5.1 k O F 400 300 10 k 200 100 100 k 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-10: VTH vs. VDD OVER TEMPERATURE – TTL INPUT Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 1.8 1.6 1.4 Max (-40°C) 1.2 V) Typ (25°C) (H 1.0 T V Min (125°C) 0.8 0.6 0.4 0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30605D-page 144  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 17-11: VIL, VIH vs. VDD OVER TEMPERATURE – SCHMITT TRIGGER INPUT (I2C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 4.0 3.5 VIH Max (125°C) VIH Typ (25°C) 3.0 VIH Min (-40°C) 2.5 V) (N 2.0 VI VIL Max (125°C) 1.5 VIL Typ (25°C) VIL Min (-40°C) 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-12: VIL, VIH vs. VDD OVER TEMPERATURE – SCHMITT TRIGGER INPUT Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 4.0 3.5 VIH Max (125°C) 3.0 VIH Typ (25°C) 2.5 VIH Min (-40°C) V) VIL Max (125°C) (N 2.0 VI VIL Typ (25°C) VIL Min (-40°C) 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  1998-2013 Microchip Technology Inc. DS30605D-page 145

PIC16C63A/65B/73B/74B FIGURE 17-13: VOH vs. IOH AT VDD = 3.0 V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 3.5 3.0 2.5 Max (-40°C) 2.0 V) (H Typical (25°C) O V 1.5 1.0 Min (125°C) 0.5 0.0 0 5 10 15 20 25 IOH (mA) FIGURE 17-14: VOH vs. IOH AT VDD = 5.0 V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 5.5 5.0 4.5 Max (-40°C) 4.0 Typical (25°C) 3.5 V) 3.0 (H O V 2.5 Min (125°C) 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (mA) DS30605D-page 146  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 17-15: VOL vs. IOL AT VDD = 3.0 V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.4 2.2 2.0 1.8 1.6 Max (125°C) 1.4 V) (L 1.2 O V 1.0 Typ (25°C) 0.8 0.6 0.4 Min (-40°C) 0.2 0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 IOL (-mA) FIGURE 17-16: VOL vs. IOL AT VDD = 5.0 V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 1.8 1.6 1.4 1.2 Max (125°C) V) (L 1.0 O V 0.8 Typ (25°C) 0.6 0.4 Min (-40°C) 0.2 0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 IOL (-mA)  1998-2013 Microchip Technology Inc. DS30605D-page 147

PIC16C63A/65B/73B/74B FIGURE 17-17: IPD vs. VDD (85°C) – SLEEP MODE, ALL PERIPHERALS DISABLED Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 140 Max 85°C 120 100 80 A) n (D P I 60 Typ 85°C 40 20 Max 25°CMax -40°C 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-18: IPD vs. VDD (125°C) – SLEEP MODE, ALL PERIPHERALS DISABLED Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1,400 1,200 Max (125°C) 1,000 800 A) n (D P I 600 Typ (125°C) 400 200 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30605D-page 148  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 17-19: IBOR vs. VDD OVER TEMPERATURE (-40°C TO +125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 200 180 160 140 Max (125°C) 120 A) u Device (R 100 in BO Typ (25°C) Indeterminant SLEEP I Device State 80 in Max (125°C) RESET Typ (25°C) 60 RESET current depends on oscillator mode, frequency, and 40 circuit. 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-20: ITIMER1 vs. VDD (-10°C TO +70°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 120 100 Max (-10°C to 70°C) 80 A) u (1 R 60 E M Typical (25°C) TI I 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  1998-2013 Microchip Technology Inc. DS30605D-page 149

PIC16C63A/65B/73B/74B FIGURE 17-21: IWDT vs. VDD (-40°C TO +125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 20 18 16 14 12 A) Max (-40°C to 125°C) µ (T 10 D W I 8 Typical (25°C) 6 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-22: WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 40 35 Maximum (125°C) 30 s) 25 m d ( o eri 20 P T D Typical (25°C) W 15 10 Minimum (-40°C) 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS30605D-page 150  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B FIGURE 17-23: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 40 35 30 125°C s) 25 m d ( 85°C o eri 20 P T 25°C D W 15 -40°C 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  1998-2013 Microchip Technology Inc. DS30605D-page 151

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 152  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 18.0 PACKAGING INFORMATION 18.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX PIC16C73B-04/SP XXXXXXXXXXXXXXXXX YYWWNNN 0017HAT 28-Lead CERDIP Windowed Example XXXXXXXXXXXXXX PIC16C73B/JW XXXXXXXXXXXXXX YYWWNNN 0017CAT 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC16C73B-20/SO XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 0017SAA 28-Lead SSOP Example XXXXXXXXXXXX PIC16C73B- XXXXXXXXXXXX 20I/SS025 YYWWNNN 0017SBP Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  1998-2013 Microchip Technology Inc. DS30605D-page 153

PIC16C63A/65B/73B/74B Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX PIC16C74B-04/P XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 0017SAA 40-Lead CERDIP Windowed Example XXXXXXXXXXX PIC16C74B/JW XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 0017HAT 44-Lead TQFP Example XXXXXXXXXX PIC16C74B XXXXXXXXXX -20/PT XXXXXXXXXX YYWWNNN 0017HAT 44-Lead MQFP Example XXXXXXXXXX PIC16C74B XXXXXXXXXX -20/PQ XXXXXXXXXX YYWWNNN 0017SAT 44-Lead PLCC Example XXXXXXXXXX PIC16C74B XXXXXXXXXX -20/L XXXXXXXXXX YYWWNNN 0017SAT DS30605D-page 154  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 18.2 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A L c  A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 8.26 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .040 .053 .065 1.02 1.33 1.65 Lower Lead Width B .016 .019 .022 0.41 0.48 0.56 Overall Row Spacing § eB .320 .350 .430 8.13 8.89 10.92 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070  1998-2013 Microchip Technology Inc. DS30605D-page 155

PIC16C63A/65B/73B/74B 18.3 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 W2 D 2 n 1 W1 E A A2 c L B1 eB A1 B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .170 .183 .195 4.32 4.64 4.95 Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19 Standoff A1 .015 .023 .030 0.38 0.57 0.76 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Ceramic Pkg. Width E1 .285 .290 .295 7.24 7.37 7.49 Overall Length D 1.430 1.458 1.485 36.32 37.02 37.72 Tip to Seating Plane L .135 .140 .145 3.43 3.56 3.68 Lead Thickness c .008 .010 .012 0.20 0.25 0.30 Upper Lead Width B1 .050 .058 .065 1.27 1.46 1.65 Lower Lead Width B .016 .019 .021 0.41 0.47 0.53 Overall Row Spacing § eB .345 .385 .425 8.76 9.78 10.80 Window Width W1 .130 .140 .150 3.30 3.56 3.81 Window Length W2 .290 .300 .310 7.37 7.62 7.87 * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-058 Drawing No. C04-080 DS30605D-page 156  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 18.4 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1 h  45 c A A2   L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .288 .295 .299 7.32 7.49 7.59 Overall Length D .695 .704 .712 17.65 17.87 18.08 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle Top  0 4 8 0 4 8 Lead Thickness c .009 .011 .013 0.23 0.28 0.33 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top  0 12 15 0 12 15 Mold Draft Angle Bottom  0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052  1998-2013 Microchip Technology Inc. DS30605D-page 157

PIC16C63A/65B/73B/74B 18.5 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1  A c A2  A1 L  Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .026 0.65 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .319 7.59 7.85 8.10 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .396 .402 .407 10.06 10.20 10.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle  0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073 DS30605D-page 158  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 18.6 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2  n 1 E A A2 L c B1  A1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 40 40 Pitch p .100 2.54 Top to Seating Plane A .160 .175 .190 4.06 4.45 4.83 Molded Package Thickness A2 .140 .150 .160 3.56 3.81 4.06 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88 Molded Package Width E1 .530 .545 .560 13.46 13.84 14.22 Overall Length D 2.045 2.058 2.065 51.94 52.26 52.45 Tip to Seating Plane L .120 .130 .135 3.05 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .030 .050 .070 0.76 1.27 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .620 .650 .680 15.75 16.51 17.27 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016  1998-2013 Microchip Technology Inc. DS30605D-page 159

PIC16C63A/65B/73B/74B 18.7 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D 2 n 1 E A2 c L B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 40 40 Pitch p .100 2.54 Top to Seating Plane A .185 .205 .225 4.70 5.21 5.72 Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19 Standoff A1 .030 .045 .060 0.76 1.14 1.52 Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88 Ceramic Pkg. Width E1 .514 .520 .526 13.06 13.21 13.36 Overall Length D 2.040 2.050 2.060 51.82 52.07 52.32 Tip to Seating Plane L .135 .140 .145 3.43 3.56 3.68 Lead Thickness c .008 .011 .014 0.20 0.28 0.36 Upper Lead Width B .050 .053 .055 1.27 1.33 1.40 Lower Lead Width B1 .016 .020 .023 0.41 0.51 0.58 Overall Row Spacing § eB .610 .660 .710 15.49 16.76 18.03 Window Diameter W .340 .350 .360 8.64 8.89 9.14 * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-103 Drawing No. C04-014 DS30605D-page 160  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 18.8 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45  A c   A1 A2 L (F) Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .031 0.80 Pins per Side n1 11 11 Overall Height A .039 .043 .047 1.00 1.10 1.20 Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05 Standoff § A1 .002 .004 .006 0.05 0.10 0.15 Foot Length L .018 .024 .030 0.45 0.60 0.75 Footprint (Reference) (F) .039 1.00 Foot Angle  0 3.5 7 0 3.5 7 Overall Width E .463 .472 .482 11.75 12.00 12.25 Overall Length D .463 .472 .482 11.75 12.00 12.25 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B .012 .015 .017 0.30 0.38 0.44 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076  1998-2013 Microchip Technology Inc. DS30605D-page 161

PIC16C63A/65B/73B/74B 18.9 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form (MQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45  A1 c A  L  (F) A2 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .031 0.80 Pins per Side n1 11 11 Overall Height A .079 .086 .093 2.00 2.18 2.35 Molded Package Thickness A2 .077 .080 .083 1.95 2.03 2.10 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Foot Length L .029 .035 .041 0.73 0.88 1.03 Footprint (Reference) (F) .063 1.60 Foot Angle  0 3.5 7 0 3.5 7 Overall Width E .510 .520 .530 12.95 13.20 13.45 Overall Length D .510 .520 .530 12.95 13.20 13.45 Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10 Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10 Lead Thickness c .005 .007 .009 0.13 0.18 0.23 Lead Width B .012 .015 .018 0.30 0.38 0.45 Pin 1 Corner Chamfer CH .025 .035 .045 0.64 0.89 1.14 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-022 Drawing No. C04-071 DS30605D-page 162  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B 18.10 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3  A2 A 35 B1 c B A1  p E2 D2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p .050 1.27 Pins per Side n1 11 11 Overall Height A .165 .173 .180 4.19 4.39 4.57 Molded Package Thickness A2 .145 .153 .160 3.68 3.87 4.06 Standoff § A1 .020 .028 .035 0.51 0.71 0.89 Side 1 Chamfer Height A3 .024 .029 .034 0.61 0.74 0.86 Corner Chamfer 1 CH1 .040 .045 .050 1.02 1.14 1.27 Corner Chamfer (others) CH2 .000 .005 .010 0.00 0.13 0.25 Overall Width E .685 .690 .695 17.40 17.53 17.65 Overall Length D .685 .690 .695 17.40 17.53 17.65 Molded Package Width E1 .650 .653 .656 16.51 16.59 16.66 Molded Package Length D1 .650 .653 .656 16.51 16.59 16.66 Footprint Width E2 .590 .620 .630 14.99 15.75 16.00 Footprint Length D2 .590 .620 .630 14.99 15.75 16.00 Lead Thickness c .008 .011 .013 0.20 0.27 0.33 Upper Lead Width B1 .026 .029 .032 0.66 0.74 0.81 Lower Lead Width B .013 .020 .021 0.33 0.51 0.53 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-048  1998-2013 Microchip Technology Inc. DS30605D-page 163

PIC16C63A/65B/73B/74B NOTES: DS30605D-page 164  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B APPENDIX A: REVISION HISTORY Version Date Revision Description A 7/98 This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234, and the PIC16C7X Data Sheet, DS30390. B 1/99 Corrections to Version A data sheet for technical accuracy. Added data: • Operation of the SMP and CKE bits of the SSPSTAT register in I2C mode have been specified • Frequency vs. VDD graphs for device operating area (in Electrical Specifications) • Formula for calculating A/D acquisition time, TACQ (in the A/D section) • Brief description of instructions Removed data (see PICmicroTM Mid-Range MCU Family Reference Manual, DS33023, for additional data): • USART Baud Rate Tables (formulas for calculating baud rate remain) C 12/00 • Minor changes to text to clarify content • Revised some DC specifications • Included characteristic charts and graphs D 01/13 • Added a note to every package drawing. APPENDIX B: DEVICE DIFFERENCES The differences between the devices in this data sheet are listed in TableB-1. TABLE B-1: DEVICE DIFFERENCES Difference PIC16C63A PIC16C65B PIC16C73B PIC16C74B A/D no no 5 channels, 8 bits 8 channels, 8 bits Parallel Slave Port no yes no yes Packages 28-pin PDIP, 28-pin 40-pin PDIP, 40-pin 28-pin PDIP, 28-pin 40-pin PDIP, 40-pin windowed CERDIP, windowed CERDIP, windowed CERDIP, windowed CERDIP, 28-pin SOIC, 28-pin 44-pin TQFP, 44-pin 28-pin SOIC, 28-pin 44-pin TQFP, 44-pin SSOP MQFP, 44-pin PLCC SSOP MQFP, 44-pin PLCC  1998-2013 Microchip Technology Inc. DS30605D-page 165

PIC16C63A/65B/73B/74B APPENDIX C: DEVICE MIGRATIONS - PIC16C63/65A/73A/74A  PIC16C63A/65B/73B/74B This document is intended to describe the functional differences and the electrical specification differences that are present when migrating from one device to the next. TableC-1 shows functional differences, while TableC-2 shows electrical and timing differences. Note: Even though compatible devices are specified to be tested to the same electrical specification, the device characteristics may be different from each other (due to process differences). For systems that were designed to the device specifications, these process differences should not cause any issues in the appli- cation. For systems that did not tightly meet the electrical specifications, the process differences may cause the device to behave differently in the application. Note: While there are no functional or electrical changes to the device oscillator specifications, the user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the oscillator mode may be required. TABLE C-1: FUNCTIONAL DIFFERENCES No. Module Differences from PIC16C63/65A/73A/74A H/W S/W Prog. 1 CCP CCP Special Event Trigger clears Timer1. — ✔ — 2 Compare mode drives pin correctly. — ✔ — 3 Timers Writing to TMR1L does not affect TMR1H. — ✔ — 4 WDT/TMR0 prescaler assignment changes do not affect TMR0 count. — ✔ — 5 SSP TMR2 SPI clock synchronized to start of SPI Transmission. — ✔ — 6 Can now transmit multiple words in SPI mode. — ✔ — 7 Supports all four SPI modes. (Now uses SSP vs. BSSP module.) — ✔ — See SSP module in the PIC® Mid-Range MCU Family Reference Manual (DS33023). 8 I2C no longer generates ACK pulses when module is enabled. — ✔ — 9 USART Async receive errors due to BRGH setting corrected. — ✔ — 10 A/D VREF = VDD when all inputs are configured as digital. — ✔ — This allows conversion of digital inputs. (A/D on PIC16C73X/74X only.) H/W - Issues may exist with regard to the application circuits. S/W - Issues may exist with regard to the user program. Prog. - Issues may exist when writing the program to the controller. DS30605D-page 166  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TABLE C-2: SPECIFICATION DIFFERENCES Param PIC16C63/65A/73A/74A PIC16C63A/65B/73B/74B Symbol Characteristic Unit No. Min Typ† Max Min Typ† Max Core D001 VDD Supply Voltage 4.0 — 6.0 4.0 — 5.5 V D001A — — — VBOR(1) — 5.5 V D005 BVDD Brown-out Reset Voltage 3.7 4.0 4.3 3.65 — 4.35 V D150* VOD Open-Drain High Voltage on — — 14.0 - — 8.5 V RA4 A/D Converter A20 VREF Reference voltage 3.0 — VDD + 0.3 2.5 — VDD + 0.3 V 131 TCNV Conversion time (Note 2) — 9.5 — 11 — 11 TAD (not including S/H time) (Note 3) (Note 4) (Note 4) SSP in SPI mode 71 TscH SCK input high Continuous TCY+20 — — 1.25TCY + 30 — — ns 71A time (Slave mode) Single Byte 40 — — ns 72 TscL SCK input low Continuous TCY+20 — — 1.25TCY + 30 — — ns 72A time Single Byte 40 — — ns (Slave mode) 73 TdiV2scH Setup time of SDI data input to 50 — — 100 — — ns TdiV2scL SCK edge 73A TB2B Last clock edge of Byte1 to the — — — 1.5TCY + 40 — — ns (Note 5) 1st clock edge of Byte2 74 TscH2diL Hold time of SDI data input to 50 — — 100 — — ns TscL2diL SCK edge 75 TdoR SDO data output PIC16CXX — 10 25 — 10 25 ns rise time PIC16LCXX — 20 45 ns 78 TscR SCK output rise PIC16CXX — 10 25 — 10 25 ns time (Master PIC16LCXX — 20 45 ns mode) 80 TscH2doV SDO data output PIC16CXX — — 50 — — 50 ns TscL2doV valid after SCK PIC16LCXX — — 100 ns edge 83 TscH2ssH SS  after SCK edge — — 50 1.5TCY + 40 — — ns TscL2ssH †Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When BOR is enabled, the device will operate until VDD drops below VBOR. 2: ADRES register may be read on the following TCY cycle. 3: This is the time that the actual conversion requires. 4: This is the time from when the GO/DONE bit is set, to when the conversion result appears in ADRES. 5: Specification 73A is only required if specifications 71A and 72A are used.  1998-2013 Microchip Technology Inc. DS30605D-page 167

PIC16C63A/65B/73B/74B APPENDIX D: MIGRATION FROM BASELINE TO MID-RANGE DEVICES This section discusses how to migrate from a baseline To convert code written for PIC16C5X to PIC16CXX, device (i.e., PIC16C5X) to a mid-range device (i.e., the user should take the following steps: PIC16CXXX). 1. Remove any program memory page select The following are the list of modifications over the operations (PA2, PA1, PA0 bits) for CALL, GOTO. PIC16C5X microcontroller family: 2. Revisit any computed jump operations (write to 1. Instruction word length is increased to 14-bits. PC or add to PC, etc.) to make sure page bits This allows larger page sizes, both in program are set properly under the new scheme. memory (2K now as opposed to 512 before) 3. Eliminate any data memory page switching. and register file (128 bytes now versus 32 bytes Redefine data variables to reallocate them. before). 4. Verify all writes to STATUS, OPTION and FSR 2. A PC high latch register (PCLATH) is added to registers since these have changed. handle program memory paging. Bits PA2, PA1 5. Change RESET vector to 0000h. and PA0 are removed from STATUS register. 3. Data memory paging is redefined slightly. STATUS register is modified. 4. Four new instructions have been added: RETURN, RETFIE, ADDLW and SUBLW. Two instructions, TRIS and OPTION, are being phased out, although they are kept for compati- bility with PIC16C5X. 5. OPTION and TRIS registers are made address- able. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8-deep. 8. RESET vector is changed to 0000h. 9. RESET of all registers is revisited. Five different RESET (and wake-up) types are recognized. Registers are reset differently. 10. Wake up from SLEEP through interrupt is added. 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These tim- ers are invoked selectively to avoid unneces- sary delays on power-up and wake-up. 12. PORTB has weak pull-ups and interrupt-on-change feature. 13. T0CKI pin is also a port pin (RA4) now. 14. FSR is made a full 8-bit register. 15. “In-Circuit Serial Programming” (ICSP) is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). 16. PCON status register is added with a Power-on Reset status bit (POR). 17. Code protection scheme is enhanced, such that portions of the program memory can be pro- tected, while the remainder is unprotected. 18. Brown-out protection circuitry has been added. Controlled by configuration word bit BODEN. Brown-out Reset ensures the device is placed in a RESET condition if VDD dips below a fixed setpoint. DS30605D-page 168  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B INDEX A BOR bit.........................................................................25, 89 BRGH bit............................................................................67 A/D Brown-out Reset (BOR) ADCON0 Register.......................................................79 Timing Diagram........................................................126 ADCON1 Register.......................................................80 Buffer Full Status bit, BF.....................................................56 Analog Input Model Block Diagram.............................82 Analog-to-Digital Converter.........................................79 C Block Diagram.............................................................81 C bit....................................................................................19 Configuring Analog Port Pins......................................83 Capture/Compare/PWM Configuring the Interrupt.............................................81 Capture Configuring the Module...............................................81 Block Diagram....................................................51 Conversion Clock........................................................83 CCP1CON Register............................................50 Conversions................................................................83 CCP1IF...............................................................51 Converter Characteristics.........................................137 Mode..................................................................51 Effects of a RESET.....................................................83 Prescaler............................................................51 Faster Conversion - Lower Resolution Trade-off........83 CCP Timer Resources................................................49 Internal Sampling Switch (Rss) Impedance................82 Compare Operation During SLEEP............................................83 Block Diagram....................................................52 Sampling Requirements..............................................82 Mode..................................................................52 Source Impedance......................................................82 Software Interrupt Mode.....................................52 Timing Diagram.........................................................138 Special Event Trigger.........................................52 Using the CCP Trigger................................................83 Special Trigger Output of CCP1.........................52 Absolute Maximum Ratings..............................................113 Special Trigger Output of CCP2.........................52 ACK...............................................................................60, 62 Interaction of Two CCP Modules................................49 ADRES Register...........................................................17, 79 Section........................................................................49 Application Notes Special Event Trigger and A/D Conversions...............52 AN552 (Implementing Wake-up on Key Strokes Capture/Compare/PWM (CCP) Using PIC16CXXX).....................................................31 PWM Block Diagram..................................................52 AN556 (Table Reading Using PIC16CXX)..................26 PWM Mode.................................................................52 AN578 (Use of the SSP Module in the I2C PWM, Example Frequencies/Resolutions..................53 Multi-Master Environment)..........................................55 Timing Diagram........................................................128 AN607, (Power-up Trouble Shooting).........................89 CCP2IE bit..........................................................................24 Architecture CCP2IF bit..........................................................................24 Overview.......................................................................9 CCPR1H Register.........................................................17, 49 Assembler CCPR1L Register...............................................................49 MPASM® Assembler.................................................107 CCPR2H Register...............................................................17 B CCPR2L Register...............................................................17 CCPxM0 bit.........................................................................50 Baud Rate Formula.............................................................67 CCPxM1 bit.........................................................................50 BF.................................................................................56, 60 CCPxM2 bit.........................................................................50 Block Diagrams CCPxM3 bit.........................................................................50 A/D..............................................................................81 CCPxX bit...........................................................................50 Analog Input Model.....................................................82 CCPxY bit...........................................................................50 Capture.......................................................................51 CKE....................................................................................56 Compare.....................................................................52 CKP....................................................................................57 I2C Mode.....................................................................60 Clock Polarity Select bit, CKP.............................................57 On-Chip Reset Circuit.................................................88 Clocking Scheme................................................................14 PIC16C74...................................................................10 Code Examples PIC16C74A.................................................................10 Call of a Subroutine in Page 1 from Page 0...............26 PIC16C77...................................................................10 Indirect Addressing.....................................................27 PORTC.......................................................................33 Initializing PORTA.......................................................29 PORTD (In I/O Port Mode)..........................................34 Code Protection............................................................85, 98 PORTD and PORTE as a Parallel Slave Port.............37 Computed GOTO................................................................26 PORTE (In I/O Port Mode)..........................................35 Configuration Bits...............................................................85 PWM...........................................................................52 CREN bit.............................................................................66 RA4/T0CKI Pin............................................................29 CS pin.................................................................................37 RB3:RB0 Port Pins.....................................................31 RB7:RB4 Port Pins.....................................................31 SSP in I2C Mode.........................................................60 SSP in SPI Mode........................................................55 Timer0/WDT Prescaler................................................39 Timer2.........................................................................47 USART Receive..........................................................70 USART Transmit.........................................................68 Watchdog Timer..........................................................96  1998-2013 Microchip Technology Inc. DS30605D-page 169

PIC16C63A/65B/73B/74B D COMF.......................................................................103 DECF........................................................................103 D/A......................................................................................56 DECFSZ...................................................................103 Data Memory GOTO.......................................................................103 Register File Map........................................................16 INCF.........................................................................103 Data/Address bit, D/A..........................................................56 INCFSZ.....................................................................103 DC bit..................................................................................19 IORLW......................................................................104 Development Support...........................................................5 IORWF......................................................................104 Device Differences............................................................165 MOVF.......................................................................104 Direct Addressing................................................................27 MOVLW....................................................................104 E MOVWF....................................................................104 NOP..........................................................................104 Electrical Characteristics...................................................113 RETFIE.....................................................................105 Errata....................................................................................3 RETLW.....................................................................105 F RETURN...................................................................105 RLF...........................................................................105 FERR bit..............................................................................66 RRF..........................................................................105 FSR Register...........................................................17, 18, 27 SLEEP......................................................................105 G SUBLW.....................................................................106 SUBWF.....................................................................106 General Description..............................................................5 SWAPF.....................................................................106 GIE bit.................................................................................93 XORLW.....................................................................106 I XORWF....................................................................106 Section........................................................................99 I/O Ports Summary Table.........................................................100 PORTA........................................................................29 INT Interrupt........................................................................94 PORTB........................................................................31 INTCON Register................................................................21 PORTC........................................................................33 INTEDG bit...................................................................20, 94 PORTD..................................................................34, 37 Internal Sampling Switch (Rss) Impedance........................82 PORTE........................................................................35 Interrupts.............................................................................85 Section........................................................................29 I2C PORTB Change..........................................................94 RB7:RB4 Port Change................................................31 Addressing..................................................................61 Section........................................................................93 Block Diagram.............................................................60 I2C Operation..............................................................60 TMR0..........................................................................94 IRP bit.................................................................................19 Master Mode...............................................................64 Mode...........................................................................60 K Mode Selection...........................................................60 Multi-Master Mode......................................................64 KEELOQ Evaluation and Programming Tools....................110 Reception....................................................................62 L Reception Timing Diagram..........................................62 Loading of PC.....................................................................26 SCL and SDA pins......................................................60 Slave Mode.................................................................60 M Transmission...............................................................63 I2C (SSP Module) MCLR............................................................................87, 90 Memory Timing Diagram, Data...............................................134 Data Memory..............................................................15 Timing Diagram, START/STOP Bits..........................134 Program Memory........................................................15 In-Circuit Serial Programming.......................................85, 98 Program Memory Maps INDF Register.........................................................17, 18, 27 PIC16C73...........................................................15 Indirect Addressing.............................................................27 PIC16C73A.........................................................15 Instruction Cycle..................................................................14 PIC16C74...........................................................15 Instruction Flow/Pipelining..................................................14 PIC16C74A.........................................................15 Instruction Format...............................................................99 Register File Maps Instruction Set PIC16C73...........................................................16 ADDLW.....................................................................101 PIC16C73A.........................................................16 ADDWF.....................................................................101 PIC16C74...........................................................16 ANDLW.....................................................................101 PIC16C74A.........................................................16 ANDWF.....................................................................101 PIC16C76...........................................................16 BCF...........................................................................101 PIC16C77...........................................................16 BSF...........................................................................101 MPLAB® Integrated Development BTFSC......................................................................102 Environment Software......................................................107 BTFSS......................................................................102 CALL.........................................................................102 CLRF.........................................................................102 CLRW........................................................................102 CLRWDT...................................................................102 DS30605D-page 170  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B O RD1/PSP1..................................................................13 RD2/PSP2..................................................................13 OERR bit.............................................................................66 RD3/PSP3..................................................................13 OPCODE............................................................................99 RD4/PSP4..................................................................13 OPTION Register................................................................20 RD5/PSP5..................................................................13 OSC Selection....................................................................85 RD6/PSP6..................................................................13 Oscillator RD7/PSP7..................................................................13 HS.........................................................................86, 90 RE0/RD/AN5..............................................................13 LP..........................................................................86, 90 RE1/WR/AN6..............................................................13 RC...............................................................................86 RE2/CS/AN7...............................................................13 XT.........................................................................86, 90 Oscillator Configurations.....................................................86 VDD........................................................................11, 13 Output of TMR2..................................................................47 VSS........................................................................11, 13 Pinout Descriptions P PIC16C73...................................................................11 PIC16C73A.................................................................11 P..........................................................................................56 PIC16C74...................................................................12 Packaging.........................................................................153 PIC16C74A.................................................................12 Paging, Program Memory...................................................26 PIC16C76...................................................................11 Parallel Slave Port........................................................34, 37 PIC16C77...................................................................12 Parallel Slave Port (PSP) PIR1 Register.....................................................................23 Timing Diagram.........................................................129 PIR2 Register.....................................................................24 PCFG0 bit...........................................................................80 POP....................................................................................26 PCFG1 bit...........................................................................80 POR....................................................................................89 PCFG2 bit...........................................................................80 Oscillator Start-up Timer (OST)............................85, 89 PCL Register...........................................................17, 18, 26 Power Control Register (PCON).................................89 PCLATH..............................................................................91 Power-on Reset (POR)...................................85, 89, 91 PCLATH Register...................................................17, 18, 26 Power-up Timer (PWRT)............................................85 PCON Register.............................................................25, 89 Power-Up-Timer (PWRT)...........................................89 PD bit............................................................................19, 87 TO...............................................................................87 PICDEMTM 1 Low Cost PIC MCU POR bit.........................................................................25, 89 Demonstration Board........................................................109 Port RB Interrupt.................................................................94 PICDEMTM 2 Low Cost PIC16CXX PORTA...............................................................................91 Demonstration Board........................................................109 PORTA Register...........................................................17, 29 PICDEMTM 3 Low Cost PIC16CXXX PORTB...............................................................................91 Demonstration Board........................................................110 PICSTART® Plus Entry Level PORTB Register...........................................................17, 31 PORTC...............................................................................91 Development System........................................................109 PORTC Register...........................................................17, 33 PIE1 Register......................................................................22 PORTD...............................................................................91 PIE2 Register......................................................................24 PORTD Register...........................................................17, 34 Pin Functions PORTE...............................................................................91 MCLR/VPP.............................................................11, 12 PORTE Register...........................................................17, 35 OSC1/CLKIN.........................................................11, 12 Power-down Mode (SLEEP)...............................................97 OSC2/CLKOUT.....................................................11, 12 Power-on Reset (POR) RA0/AN0...............................................................11, 12 Timing Diagram........................................................126 RA1/AN1...............................................................11, 12 PR2 Register................................................................18, 47 RA2/AN2...............................................................11, 12 PRO MATE® II Universal Programmer.............................109 RA3/AN3/VREF......................................................11, 12 Product Identification System...........................................177 RA4/T0CKI............................................................11, 12 Program Memory RA5/AN4/SS.........................................................11, 12 Paging........................................................................26 RB0/INT................................................................11, 12 Program Memory Maps RB1.......................................................................11, 12 PIC16C73...................................................................15 RB2.......................................................................11, 12 PIC16C73A.................................................................15 RB3.......................................................................11, 12 PIC16C74...................................................................15 RB4.......................................................................11, 12 PIC16C74A.................................................................15 RB5.......................................................................11, 12 Program Verification...........................................................98 RB6.......................................................................11, 12 PS0 bit................................................................................20 RB7.......................................................................11, 12 PS1 bit................................................................................20 RC0/T1OSO/T1CKI..............................................11, 13 PS2 bit................................................................................20 RC1/T1OSI/CCP2.................................................11, 13 PSA bit................................................................................20 RC2/CCP1............................................................11, 13 PSPMODE bit.........................................................34, 35, 37 RC3/SCK/SCL......................................................11, 13 PUSH..................................................................................26 RC4/SDI/SDA.......................................................11, 13 RC5/SDO..............................................................11, 13 RC6/TX/CK...............................................11, 13, 65–76 RC7/RX/DT...............................................11, 13, 65–76 RD0/PSP0...................................................................13  1998-2013 Microchip Technology Inc. DS30605D-page 171

PIC16C63A/65B/73B/74B R SSPSTAT....................................................................56 SPI Clock Edge Select bit, CKE.........................................56 R/W.....................................................................................56 SPI Data Input Sample Phase Select bit, SMP..................56 R/W bit....................................................................61, 62, 63 SREN bit.............................................................................66 RBIF bit.........................................................................31, 94 SSP RBPU bit.............................................................................20 Module Overview........................................................55 RC Oscillator.................................................................87, 90 Section........................................................................55 RCSTA Register..................................................................66 SSPCON....................................................................57 RD pin.................................................................................37 SSPSTAT....................................................................56 Read/Write bit Information, R/W.........................................56 SSPADD Register...............................................................18 Receive Overflow Indicator bit, SSPOV..............................57 SSPBUF Register...............................................................17 Register File........................................................................15 SSPCON.............................................................................57 Register File Map................................................................16 SSPCON Register..............................................................17 Registers SSPEN................................................................................57 Maps SSPM3:SSPM0..................................................................57 PIC16C73...........................................................16 SSPOV.........................................................................57, 60 PIC16C73A.........................................................16 SSPSTAT Register.......................................................18, 56 PIC16C74...........................................................16 Stack...................................................................................26 PIC16C74A.........................................................16 Overflows....................................................................26 RESET Conditions......................................................90 Underflow...................................................................26 SSPSTAT....................................................................56 START bit, S.......................................................................56 Summary.....................................................................17 STATUS Register...............................................................19 RESET..........................................................................85, 87 STOP bit, P.........................................................................56 Timing Diagram.........................................................126 Synchronous Serial Port Enable bit, SSPEN......................57 RESET Conditions for Special Registers............................90 Synchronous Serial Port Mode Select bits, Revision History................................................................165 SSPM3:SSPM0..................................................................57 RP0 bit..........................................................................15, 19 Synchronous Serial Port Module........................................55 RP1 bit................................................................................19 Synchronous Serial Port Status Register...........................56 RX9 bit................................................................................66 RX9D bit..............................................................................66 T S T0CS bit..............................................................................20 T1CKPS0 bit.......................................................................43 S..........................................................................................56 T1CKPS1 bit.......................................................................43 SCL.....................................................................................60 T1CON Register.................................................................43 Serial Communication Interface (SCI) Module, T1OSCEN bit......................................................................43 See USART T1SYNC bit.........................................................................43 Services T2CKPS0 bit.......................................................................47 One-Time-Programmable (OTP)...................................7 T2CKPS1 bit.......................................................................47 Quick-Turnaround-Production (QTP)............................7 T2CON Register.................................................................47 Serialized Quick-Turnaround Production (SQTP)..........................................................................7 TAD......................................................................................83 Timer0 Slave Mode RTCC..........................................................................91 SCL.............................................................................60 Timing Diagram........................................................127 SDA.............................................................................60 Timer1 SLEEP...........................................................................85, 87 Timing Diagram........................................................127 SMP....................................................................................56 Timers Software Simulator (MPLAB-SIM).....................................108 Timer0 SPBRG Register.................................................................18 External Clock....................................................40 Special Features of the CPU...............................................85 Interrupt..............................................................39 Special Function Registers Prescaler............................................................40 PIC16C73...................................................................17 Prescaler Block Diagram....................................39 PIC16C73A.................................................................17 Section................................................................39 PIC16C74...................................................................17 T0CKI.................................................................40 PIC16C74A.................................................................17 T0IF....................................................................94 Special Function Registers, Section...................................16 TMR0 Interrupt...................................................94 SPEN bit..............................................................................66 Timer1 SPI Asynchronous Counter Mode.............................45 Block Diagram.............................................................55 Capacitor Selection............................................45 Master Mode Timing...................................................58 Operation in Timer Mode....................................44 Serial Clock.................................................................55 Oscillator.............................................................45 Serial Data In..............................................................55 Prescaler............................................................45 Serial Data Out............................................................55 Resetting of Timer1 Registers............................45 Slave Mode Timing.....................................................59 Resetting Timer1 using a CCP Slave Mode Timing Diagram.......................................58 Trigger Output....................................................45 Slave Select................................................................55 Synchronized Counter Mode..............................44 SSPCON.....................................................................57 T1CON...............................................................43 DS30605D-page 172  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B TMR1H...............................................................45 U TMR1L................................................................45 UA.......................................................................................56 Timer2 Universal Synchronous Asynchronous Receiver Block Diagram....................................................47 Transmitter (USART)..........................................................65 Module................................................................47 Update Address bit, UA......................................................56 Postscaler...........................................................47 USART Prescaler.............................................................47 Asynchronous Mode...................................................68 T2CON................................................................47 Asynchronous Receiver..............................................70 Timing Diagrams Asynchronous Reception............................................71 I2C Reception (7-bit Address).....................................62 Asynchronous Transmitter..........................................68 SPI Master Mode........................................................58 Baud Rate Generator (BRG)......................................67 SPI Slave Mode (CKE = 1).........................................59 Receive Block Diagram..............................................70 SPI Slave Mode Timing (CKE = 0)..............................58 Sampling.....................................................................67 USART Asynchronous Master Transmission..............69 Synchronous Master Mode.........................................72 USART Asynchronous Reception...............................71 Timing Diagram, Synchronous Receive...........136 USART Synchronous Reception.................................75 Timing Diagram, Synchronous Transmission...136 USART Synchronous Transmission............................73 Synchronous Master Reception.................................74 Wake-up from SLEEP via Interrupt.............................98 Synchronous Master Transmission............................72 Timing Diagrams and Specifications.................................124 Synchronous Slave Mode...........................................76 A/D Conversion.........................................................138 Synchronous Slave Reception...................................76 Brown-out Reset (BOR)............................................126 Synchronous Slave Transmit......................................76 Capture/Compare/PWM (CCP).................................128 Transmit Block Diagram.............................................68 CLKOUT and I/O.......................................................125 UV Erasable Devices............................................................7 External Clock...........................................................124 I2C Bus Data.............................................................134 W I2C Bus START/STOP Bits.......................................134 Wake-up from SLEEP.........................................................97 Oscillator Start-up Timer (OST).................................126 Watchdog Timer (WDT)....................................85, 87, 90, 95 Parallel Slave Port (PSP)..........................................129 Timing Diagram........................................................126 Power-up Timer (PWRT)...........................................126 WCOL.................................................................................57 RESET......................................................................126 WDT...................................................................................90 Timer0 and Timer1....................................................127 Block Diagram............................................................96 USART Synchronous Receive (Master/Slave).........136 Period.........................................................................95 USART SynchronousTransmission (Master/Slave)..136 Programming Considerations.....................................96 Watchdog Timer (WDT)............................................126 Time-out......................................................................91 TMR0 Register....................................................................17 WR pin................................................................................37 TMR1CS bit........................................................................43 Write Collision Detect bit, WCOL........................................57 TMR1H Register.................................................................17 WWW, On-Line Support.......................................................3 TMR1L Register..................................................................17 TMR1ON bit........................................................................43 Z TMR2 Register....................................................................17 Z bit.....................................................................................19 TMR2ON bit........................................................................47 TO bit..................................................................................19 TOUTPS0 bit.......................................................................47 TOUTPS1 bit.......................................................................47 TOUTPS2 bit.......................................................................47 TOUTPS3 bit.......................................................................47 TRISA Register.............................................................18, 29 TRISB Register.............................................................18, 31 TRISC Register.............................................................18, 33 TRISD Register.............................................................18, 34 TRISE Register.......................................................18, 35, 36 TXSTA Register..................................................................65  1998-2013 Microchip Technology Inc. DS30605D-page 173

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THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or field application engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  1998-2013 Microchip Technology Inc. DS30605D-page 175

READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: Literature Number: DS30605D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS30605D-page 176  1998-2013 Microchip Technology Inc.

PIC16C63A/65B/73B/74B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XX X /XX XXX Examples: Device Frequency Temperature Package Pattern a) PIC16C74B -04/P 301 = Commercial temp., Range Range PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. b) PIC16LC63A - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. Device PIC16C6X(1), PIC16C6XT(2); VDD range 4.0V to 5.5V c) PIC16C65B - 20I/P = Industrial temp., PDIP PPIICC1166CLC7X6X(1()1, )P, PICIC161C6L7CX6TX(2T);( 2V);D VDD rDa nrgaen g4e.0 2V.5 tVo 5to.5 5V.5V package, 20 MHz, normal VDD limits. PIC16LC7X(1), PIC16LC7XT(2); VDD range 2.5V to 5.5V Frequency Range 04 = 4 MHz Note1: C = CMOS 20 = 20 MHz LC = Low Power CMOS 2: T = in tape and reel - SOIC, SSOP, PLCC, QFP, TQ and FP Temperature Range blank = 0°C to 70°C (Commercial) packages only. I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package JW = Windowed CERDIP PQ = MQFP (Metric PQFP) PT = TQFP (Thin Quad Flatpack) SO = SOIC SP = Skinny plastic dip P = PDIP L = PLCC SS = SSOP Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com)  1998-2013 Microchip Technology Inc. DS30605D-page 177

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PIC16C63A/65B/73B/74B DS30605D-page 184  1998-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1998-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769324 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  1998-2013 Microchip Technology Inc. DS30605D-page 185

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16C74BT-20E/PT PIC16C74BT-04/PQ PIC16C74BT-04/PT PIC16C73B-20E/SS PIC16C73B-20E/SO PIC16C63A-04I/SS PIC16C74BT-20E/L PIC16C65BT-04/L PIC16LC65BT-04/PQ PIC16C73B-20I/ML PIC16C73B- 20I/SS PIC16LC65BT-04/PT PIC16LC73B-04/SO PIC16LC73B-04/SP PIC16LC73B-04/SS PIC16LC65BT-04/L PIC16C63AT-04I/SO PIC16C63AT-04I/SS PIC16C65B-20I/P PIC16C65B-20I/L PIC16C74B-04E/PT PIC16C65BT- 20I/L PIC16C74B-04E/PQ PIC16C73B-04E/SO PIC16C73B-04E/SS PIC16C73B-04E/SP PIC16C74B-20I/P PIC16C74B-20I/L PIC16C65B-20I/PQ PIC16C65B-20I/PT PIC16C63AT-04E/SS PIC16C63AT-04E/SO PIC16C74B- 20/PQ PIC16C74B-20/PT PIC16C74BT-04I/PQ PIC16C65BT-04E/L PIC16C63AT-20E/SS PIC16C63AT-20E/SO PIC16C73B/JW PIC16C74BT-04I/PT PIC16C74BT-20I/PT PIC16C74BT-20I/PQ PIC16LC74B-04I/PQ PIC16LC74B- 04I/PT PIC16C65B-04I/PQ PIC16C65B-04I/PT PIC16C65B-20E/PT PIC16C65B-20E/PQ PIC16LC74B-04/PT PIC16LC74B-04/PQ PIC16LC65BT-04I/L PIC16C73B-20/SP PIC16C73B-20/SO PIC16C63A-04I/SP PIC16C73B- 04/SS PIC16C63A-04I/SO PIC16C73B-04/SO PIC16C73B-04/SP PIC16C63A-20I/SS PIC16C63A-20I/SO PIC16C63A-20I/SP PIC16LC63A-04I/SS PIC16LC63A-04I/SO PIC16LC63A-04I/SP PIC16LC73B-04I/ML PIC16LC73B-04I/SP PIC16LC73B-04I/SS PIC16LC73B-04I/SO PIC16C73BT-20/SO PIC16C74B-20I/PT PIC16C73BT-20/SS PIC16C74B-20I/PQ PIC16C65B-04E/P PIC16LC65B-04I/L PIC16LC65B-04I/P PIC16C65B- 04E/L PIC16C74BT-20E/PQ PIC16LC63A-04I/ML PIC16C65B-04/PQ PIC16C65B-20E/P PIC16C65B-04/PT PIC16C65B-20E/L PIC16LC74BT-04I/L PIC16C74B-20E/PT PIC16LC74BT-04/PT PIC16C74B-20E/PQ PIC16C74BT-04I/L PIC16LC74BT-04/PQ PIC16C73BT-04/SO PIC16C73BT-04/SS PIC16C65BT-04/PQ PIC16C65BT-04/PT PIC16C65B/JW PIC16C63A-20E/SS PIC16C63A-20E/SO PIC16C63A-20E/SP PIC16LC63A- 04/SP PIC16C65BT-20E/L PIC16C63A-04/SP PIC16LC65B-04/PQ