PIC16C6X 8-Bit CMOS Microcontrollers Devices included in this data sheet: (cid:129) Low-power, high-speed CMOS EPROM/ROM technology (cid:129) PIC16C61 (cid:129) PIC16C64A (cid:129) Fully static design (cid:129) PIC16C62 (cid:129) PIC16CR64 (cid:129) Wide operating voltage range: 2.5V to 6.0V (cid:129) PIC16C62A (cid:129) PIC16C65 (cid:129) Commercial, Industrial, and Extended (cid:129) PIC16CR62 (cid:129) PIC16C65A temperature ranges (cid:129) PIC16C63 (cid:129) PIC16CR65 (cid:129) Low-power consumption:  < 2 mA @ 5V, 4 MHz (cid:129) PIC16CR63 (cid:129) PIC16C66  15 A typical @ 3V, 32 kHz (cid:129) PIC16C64 (cid:129) PIC16C67  < 1 A typical standby current PIC16C6X Microcontroller Core Features: PIC16C6X Peripheral Features: • High performance RISC CPU (cid:129) Timer0: 8-bit timer/counter with 8-bit prescaler (cid:129) Only 35 single word instructions to learn (cid:129) Timer1: 16-bit timer/counter with prescaler, (cid:129) All single cycle instructions except for program can be incremented during sleep via branches which are two-cycle external crystal/clock (cid:129) Operating speed:DC - 20MHz clock input (cid:129) Timer2: 8-bit timer/counter with 8-bit period DC - 200ns instruction cycle register, prescaler and postscaler (cid:129) Interrupt capability (cid:129) Capture/Compare/PWM (CCP) module(s) (cid:129) Eight level deep hardware stack (cid:129) Capture is 16-bit, max resolution is 12.5 ns, (cid:129) Direct, indirect, and relative addressing modes Compare is 16-bit, max resolution is 200 ns, (cid:129) Power-on Reset (POR) PWM max resolution is 10-bit. (cid:129) Power-up Timer (PWRT) and (cid:129) Synchronous Serial Port (SSP) with SPI and I2C Oscillator Start-up Timer (OST) (cid:129) Universal Synchronous Asynchronous Receiver (cid:129) Watchdog Timer (WDT) with its own on-chip RC Transmitter (USART/SCI) oscillator for reliable operation (cid:129) Parallel Slave Port (PSP) 8-bits wide, with (cid:129) Programmable code-protection external RD, WR and CS controls (cid:129) Power saving SLEEP mode (cid:129) Brown-out detection circuitry for Brown-out Reset (BOR) (cid:129) Selectable oscillator options PIC16C6X Features 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Program Memory 1K 2K 2K — 4K — 2K 2K — 4K 4K — 8K 8K (EPROM) x 14 (ROM) x 14 — — — 2K — 4K — — 2K — — 4K — — Data Memory (Bytes) x 8 36 128 128 128 192 192 128 128 128 192 192 192 368 368 I/O Pins 13 22 22 22 22 22 33 33 33 33 33 33 22 33 Parallel Slave Port — — — — — — Yes Yes Yes Yes Yes Yes — Yes Capture/Compare/PWM — 1 1 1 2 2 1 1 1 2 2 2 2 2 Module(s) Timer Modules 1 3 3 3 3 3 3 3 3 3 3 3 3 3 Serial Communication — SPI/ SPI/ SPI/ SPI/I2C,SPI/I2C, SPI/ SPI/ SPI/ SPI/I2C,SPI/I2C,SPI/I2C,SPI/I2C,SPI/I2C, I2C I2C I2C USART USART I2C I2C I2C USART USART USART USART USART In-Circuit Serial Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Programming Brown-out Reset — — Yes Yes Yes Yes — Yes Yes — Yes Yes Yes Yes Interrupt Sources 3 7 7 7 10 10 8 8 8 11 11 11 10 11 Sink/Source Current (mA) 25/2025/2525/2525/25 25/25 25/25 25/2525/2525/25 25/25 25/25 25/25 25/25 25/25  1997-2013 Microchip Technology Inc. DS30234E-page 1

PIC16C6X Pin Diagrams PDIP, SOIC, Windowed CERDIP SDIP, SOIC, SSOP, Windowed CERDIP (300 mil) RA2 1 18 RA1 MCLR/VPP 1 28 RB7 RA3 2 17 RA0 RA0 2 27 RB6 RA4/T0CKI 3 16 OSC1/CLKIN RRAA12 34 2265 RRBB54 MCLR/VPP 4 15 OSC2/CLKOUT RA3 5 24 RB3 VSS 5 14 VDD RA4/T0CKI 6 23 RB2 RB0/INT 6 13 RB7 RA5/SS 7 22 RB1 RB1 7 12 RB6 VSS 8 21 RB0/INT RB2 8 11 RB5 OSOCS2C/C1L/CKLOKUINT 910 2109 VVDSSD RB3 9 10 RB4 RC0/T1OSI/T1CKI 11 18 RC7 RC1/T1OSO 12 17 RC6 PIC16C61 RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA PIC16C62 SDIP, SOIC, SSOP, Windowed CERDIP (300 mil) SDIP, SOIC, Windowed CERDIP (300 mil) MCLR/VPP 1 28 RB7 MCLR/VPP 1 28 RB7 RA0 2 27 RB6 RA0 2 27 RB6 RA1 3 26 RB5 RA1 3 26 RB5 RA2 4 25 RB4 RA2 4 25 RB4 RA3 5 24 RB3 RA3 5 24 RB3 RA4/T0CKI 6 23 RB2 RA4/T0CKI 6 23 RB2 RA5/SS 7 22 RB1 RA5/SS 7 22 RB1 VSS 8 21 RB0/INT VSS 8 21 RB0/INT OSC1/CLKIN 9 20 VDD OSC1/CLKIN 9 20 VDD OSC2/CLKOUT 10 19 VSS OSC2/CLKOUT 10 19 VSS RC0/T1OSO/T1CKI 11 18 RC7 RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI 12 17 RC6 RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA RC3/SCK/SCL 14 15 RC4/SDI/SDA PIC16C62A PIC16C63 PIC16CR62 PIC16CR63 PIC16C66 PDIP, Windowed CERDIP MCLR/VPP 1 40 RB7 MCLR/VPP 1 40 RB7 MCLR/VPP 1 40 RB7 RA0 2 39 RB6 RA0 2 39 RB6 RA0 2 39 RB6 RA1 3 38 RB5 RA1 3 38 RB5 RA1 3 38 RB5 RA2 4 37 RB4 RA2 4 37 RB4 RA2 4 37 RB4 RA3 5 36 RB3 RA3 5 36 RB3 RA3 5 36 RB3 RA4/T0CKI 6 35 RB2 RA4/T0CKI 6 35 RB2 RA4/T0CKI 6 35 RB2 RA5/SS 7 34 RB1 RA5/SS 7 34 RB1 RA5/SS 7 34 RB1 RE0/RD 8 33 RB0/INT RE0/RD 8 33 RB0/INT RE0/RD 8 33 RB0/INT RE1/WR 9 32 VDD RE1/WR 9 32 VDD RE1/WR 9 32 VDD RE2/CS 10 31 VSS RE2/CS 10 31 VSS RE2/CS 10 31 VSS VDD 11 30 RD7/PSP7 VDD 11 30 RD7/PSP7 VDD 11 30 RD7/PSP7 VSS 12 29 RD6/PSP6 VSS 12 29 RD6/PSP6 VSS 12 29 RD6/PSP6 OSC1/CLKIN 13 28 RD5/PSP5 OSC1/CLKIN 13 28 RD5/PSP5 OSC1/CLKIN 13 28 RD5/PSP5 OSC2/CLKOUT 14 27 RD4/PSP4 OSC2/CLKOUT 14 27 RD4/PSP4 OSC2/CLKOUT 14 27 RD4/PSP4 RC0/T1OSI/T1CKI 15 26 RC7 RC0/T1OSO/T1CKI 15 26 RC7 RC0/T1OSO/T1CKI 15 26 RC7/RX/DT RC1/T1OSO 16 25 RC6 RC1/T1OSI 16 25 RC6 RC1/T1OSI/CCP2 16 25 RC6/TX/CK RC2/CCP1 17 24 RC5/SDO RC2/CCP1 17 24 RC5/SDO RC2/CCP1 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RC3/SCK/SCL 18 23 RC4/SDI/SDA RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 RD0/PSP0 19 22 RD3/PSP3 RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2 RD1/PSP1 20 21 RD2/PSP2 RD1/PSP1 20 21 RD2/PSP2 PIC16C64 PIC16C64A PIC16C65 PIC16CR64 PIC16C65A PIC16CR65 PIC16C67 DS30234E-page 2  1997-2013 Microchip Technology Inc.

PIC16C6X Pin Diagrams (Cont.’d) MQFP RC6RC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSONC PLCC RA3RA2RA1RA0MCLR/VPPNCRB7RB6RB5RB4NC 6543214443424140 RC7 1444342414039383736353433 NC RA4R/TA05C/SKSI 78 3398 RRBB32 RD4/PSP4 2 32 RC0/T1OSI/T1CKI RE0/RD 9 37 RB1 RD5/PSP5 3 31 OSC2/CLKOUT RE1/WR 10 36 RB0/INT RRDDR67B//PP0RRRSS/VVINPPBBBDSTD67123S 4567891101 PIC16C64 3222222209876543 OVRRRRRVSAEEEASDSD5C2104/////1SCWRT/0SCSDRCLKKIIN RCO0/STOC1SO2C/SC1RI/L/ECTK12LOVVC/KNCUDSIKNSCDSTI 11111111234567 PIC16C64 33333325432109 VVRRRRRDSDDDDCSD76547////PPPPSSSSPPPP7654 1213141516171819202122 1819202122232425262728 NCNCRB4RB5RB6RB7MCLR/VPPRA0RA1RA2RA3 RC1/T1OSORC2/CCP1RC3/SCK/SCLRD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP3RC4/SDI/SDARC5/SDORC6NC MQFP, TQFP (PIC16C64A only) PLCC RC6RC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSINC RA3RA2RA1RA0MCLR/VPPNCRB7RB6RB5RB4NC 6543214443424140 RA4/T0CKI 7 39 RB3 RC7 1444342414039383736353433 NC RREA05//RSDS 89 3387 RRBB21 RD4/PSP4 2 32 RC0/T1OSO/T1CKI RE1/WR 10 36 RB0/INT RRRDDDR567B///PPP0RRSSS/VVINBBPPPDSTDS12567 345678910 PPIICC1166CCR646A4 3322222210987654 OOVVRRRRSDAEEESSSD5120CC////21SWCR//SSDCCRLLKKOINUT RC0O/TSO1COS2SC/CO1RL//CETK21LOVV/CKNCUDSIKCNSTDSI 11111111234567 PPIICC1166CCR646A4 33333325432109 VVRRRRRDSDDDDCSD76547////PPPPSSSSPPPP7654 RB3 11121314151617181920212223 RA4/T0CKI 1819202122232425262728 NCNCRB4RB5RB6RB7/VMCLRPPRA0RA1RA2RA3 RC1/T1OSIRC2/CCP1RC3/SCK/SCLRD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP3RC4/SDI/SDARC5/SDORC6NC MQFP, TQFP (Not on PIC16C65) PLCC RC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSI/CCP2NC RA3RA2RA1RA0MCLR/VPPNCRB7RB6RB5RB4NC 6543214443424140 RA4/T0CKI 7 39 RB3 RC7/RX/DT 1444342414039383736353433 NC RREA05//RSDS 89 3387 RRBB21 RD4/PSP4 2 32 RC0/T1OSO/T1CKI RE1/WR 10 36 RB0/INT RRRDDDR567B///PPP0RRSSS/VVINBBPPPDSTD12S567 345678910 PPPPIICCIICC11116666CCCCR6665657A5 3322222210987654 OOVVRRRRSDAEEESSSD5120CC////12SWCR//SSDCCRLLKKOINUT RC0O/TSO1COS2SC/CO1RL//CETKL12OVVKC/NCUDSIKNCSTDSI 11111111234567 PPPPIICCIICC11116666CCCC6R665657A5 33333325432109 VVRRRRRDSDDDDCSD76547/////PPPPRSSSSXPPPP/D7654T RB3 11121314151617181920212223 RA4/T0CKI 1819202122232425262728 NCNCRB4RB5RB6RB7MCLR/VPPRA0RA1RA2RA3 /CCP2RC1/T1OSIRC2/CCP1RC3/SCK/SCLRD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP3RC4/SDI/SDARC5/SDORC6/TX/CKNC  1997-2013 Microchip Technology Inc. DS30234E-page 3

PIC16C6X Table Of Contents 1.0 General Description.......................................................................................................................................................................5 2.0 PIC16C6X Device Varieties...........................................................................................................................................................7 3.0 Architectural Overview...................................................................................................................................................................9 4.0 Memory Organization...................................................................................................................................................................19 5.0 I/O Ports.......................................................................................................................................................................................51 6.0 Overview of Timer Modules.........................................................................................................................................................63 7.0 Timer0 Module.............................................................................................................................................................................65 8.0 Timer1 Module.............................................................................................................................................................................71 9.0 Timer2 Module.............................................................................................................................................................................75 10.0Capture/Compare/PWM (CCP) Module(s)...................................................................................................................................77 11.0Synchronous Serial Port (SSP) Module.......................................................................................................................................83 12.0Universal Synchronous Asynchronous Receiver Transmitter (USART) Module........................................................................105 13.0Special Features of the CPU.....................................................................................................................................................123 14.0Instruction Set Summary............................................................................................................................................................143 15.0Development Support................................................................................................................................................................159 16.0Electrical Characteristics for PIC16C61.....................................................................................................................................163 17.0DC and AC Characteristics Graphs and Tables for PIC16C61..................................................................................................173 18.0Electrical Characteristics for PIC16C62/64................................................................................................................................183 19.0Electrical Characteristics for PIC16C62A/R62/64A/R64............................................................................................................199 20.0Electrical Characteristics for PIC16C65.....................................................................................................................................215 21.0Electrical Characteristics for PIC16C63/65A.............................................................................................................................231 22.0Electrical Characteristics for PIC16CR63/R65...........................................................................................................................247 23.0Electrical Characteristics for PIC16C66/67................................................................................................................................263 24.0DC and AC Characteristics Graphs and Tables for: PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A, PIC16CR64, PIC16C65A, PIC16C66, PIC16C67...........................................................................................................................................281 25.0Packaging Information...............................................................................................................................................................291 Appendix A: Modifications..............................................................................................................................................................307 Appendix B: Compatibility..............................................................................................................................................................307 Appendix C: What’s New................................................................................................................................................................308 Appendix D: What’s Changed........................................................................................................................................................308 Appendix E: PIC16/17 Microcontrollers.......................................................................................................................................309 Pin Compatibility................................................................................................................................................................................315 Index..................................................................................................................................................................................................317 List of Equation and Examples...........................................................................................................................................................326 List of Figures.....................................................................................................................................................................................326 List of Tables......................................................................................................................................................................................330 Reader Response..............................................................................................................................................................................334 PIC16C6X Product Identification System...........................................................................................................................................335 For register and module descriptions in this data sheet, device legends show which devices apply to those sections. For example, the legend below shows that some features of only the PIC16C62A, PIC16CR62, PIC16C63, PIC16C64A, PIC16CR64, and PIC16C65A are described in this section. Applicable Devices 616262AR6263R636464AR646565AR656667 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS30234E-page 4  1997-2013 Microchip Technology Inc.

PIC16C6X 1.0 GENERAL DESCRIPTION ter (USART) is also known as a Serial Communications Interface or SCI. An 8-bit Parallel Slave Port is also pro- The PIC16CXX is a family of low-cost, high-perfor- vided. mance, CMOS, fully-static, 8-bit microcontrollers. The PIC16C6X device family has special features to All PIC16/17 microcontrollers employ an advanced reduce external components, thus reducing cost, RISC architecture. The PIC16CXX microcontroller fam- enhancing system reliability and reducing power con- ily has enhanced core features, eight-level deep stack, sumption. There are four oscillator options, of which the and multiple internal and external interrupt sources. single pin RC oscillator provides a low-cost solution, The separate instruction and data buses of the Harvard the LP oscillator minimizes power consumption, XT is a architecture allow a 14-bit wide instruction word with standard crystal, and the HS is for High Speed crystals. separate 8-bit wide data. The two stage instruction The SLEEP (power-down) mode offers a power saving pipeline allows all instructions to execute in a single mode. The user can wake the chip from SLEEP cycle, except for program branches (which require two through several external and internal interrupts, and cycles). A total of 35 instructions (reduced instruction resets. set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a A highly reliable Watchdog Timer with its own on-chip very high performance. RC oscillator provides protection against software lock- up. PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over A UV erasable CERDIP packaged version is ideal for other 8-bit microcontrollers in their class. code development, while the cost-effective One-Time-Programmable (OTP) version is suitable for The PIC16C61 device has 36 bytes of RAM and 13 I/O production in any volume. pins. In addition a timer/counter is available. The PIC16C6X family fits perfectly in applications rang- The PIC16C62/62A/R62 devices have 128 bytes of ing from high-speed automotive and appliance control RAM and 22 I/O pins. In addition, several peripheral to low-power remote sensors, keyboards and telecom features are available, including: three timer/counters, processors. The EPROM technology makes custom- one Capture/Compare/PWM module and one serial ization of application programs (transmitter codes, port. The Synchronous Serial Port can be configured motor speeds, receiver frequencies, etc.) extremely as either a 3-wire Serial Peripheral Interface (SPI) or fast and convenient. The small footprint packages the two-wire Inter-Integrated Circuit (I2C) bus. make this microcontroller series perfect for all applica- The PIC16C63/R63 devices have 192 bytes of RAM, tions with space limitations. Low-cost, low-power, high while the PIC16C66 has 368 bytes. All three devices performance, ease-of-use, and I/O flexibility make the have 22 I/O pins. In addition, several peripheral fea- PIC16C6X very versatile even in areas where no micro- tures are available, including: three timer/counters, two controller use has been considered before (e.g. timer Capture/Compare/PWM modules and two serial ports. functions, serial communication, capture and compare, The Synchronous Serial Port can be configured as PWM functions, and co-processor applications). either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Univer- 1.1 Family and Upward Compatibility sal Synchronous Asynchronous Receiver Transmitter Those users familiar with the PIC16C5X family of (USART) is also know as a Serial Communications microcontrollers will realize that this is an enhanced Interface or SCI. version of the PIC16C5X architecture. Please refer to The PIC16C64/64A/R64 devices have 128 bytes of Appendix A for a detailed list of enhancements. Code RAM and 33I/O pins. In addition, several peripheral written for PIC16C5X can be easily ported to features are available, including: three timer/counters, PIC16CXX family of devices (Appendix B). one Capture/Compare/PWM module and one serial 1.2 Development Support port. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or PIC16C6X devices are supported by the complete line the two-wire Inter-Integrated Circuit (I2C) bus. An 8-bit of Microchip Development tools. Parallel Slave Port is also provided. Please refer to Section15.0 for more details about The PIC16C65/65A/R65 devices have 192 bytes of Microchip’s development tools. RAM, while the PIC16C67 has 368 bytes. All four devices have 33I/O pins. In addition, several peripheral features are available, including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I2C) bus. The Uni- versal Synchronous Asynchronous Receiver Transmit-  1997-2013 Microchip Technology Inc. DS30234E-page 5

PIC16C6X TABLE 1-1: PIC16C6X FAMILY OF DEVICES PIC16C61 PIC16C62A PIC16CR62 PIC16C63 PIC16CR63 Maximum Frequency 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 1K 2K — 4K — (x14 words) Memory ROM Program Memory — — 2K — 4K (x14 words) Data Memory (bytes) 36 128 128 192 192 Timer Module(s) TMR0 TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR2 TMR2 TMR2 TMR2 Capture/Compare/ — 1 1 2 2 Peripherals PWM Module(s) Serial Port(s) — SPI/I2C SPI/I2C SPI/I2C, SPI/I2C (SPI/I2C, USART) USART USART Parallel Slave Port — — — — — Interrupt Sources 3 7 7 10 10 I/O Pins 13 22 22 22 22 Voltage Range (Volts) 3.0-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 Features In-Circuit Serial Programming Yes Yes Yes Yes Yes Brown-out Reset — Yes Yes Yes Yes Packages 18-pin DIP, SO28-pin SDIP, 28-pin SDIP, 28-pin SDIP, 28-pin SDIP, SOIC, SSOP SOIC, SSOP SOIC SOIC PIC16C64A PIC16CR64 PIC16C65A PIC16CR65 PIC16C66 PIC16C67 Maximum Frequency 20 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 2K — 4K — 8K 8K (x14 words) Memory ROM Program Memory (x14 — 2K — 4K — — words) Data Memory (bytes) 128 128 192 192 368 368 Timer Module(s) TMR0, TMR0, TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR1, TMR1, TMR2 TMR2 TMR2 TMR2 TMR2 TMR2 Capture/Compare/PWM Mod- 1 1 2 2 2 2 Peripherals ule(s) Serial Port(s) (SPI/I2C, USART) SPI/I2C SPI/I2C SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, USART USART USART USART Parallel Slave Port Yes Yes Yes Yes — Yes Interrupt Sources 8 8 11 11 10 11 I/O Pins 33 33 33 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Features Brown-out Reset Yes Yes Yes Yes Yes Yes Packages 40-pin DIP; 40-pin DIP; 40-pin DIP; 40-pin DIP; 28-pin SDIP,40-pin DIP; 44-pin PLCC,44-pin PLCC, 44-pin PLCC, 44-pin SOIC 44-pin MQFP, TQFPMQFP, TQFPMQFP, TQFP PLCC, PLCC, MQFP, MQFP, TQFP TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7. DS30234E-page 6  1997-2013 Microchip Technology Inc.

PIC16C6X 2.0 PIC16C6X DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP) Devices A variety of frequency ranges and packaging options are available. Depending on application and production Microchip offers a QTP Programming Service for fac- requirements, the proper device option can be selected tory production orders. This service is made available using the information in the PIC16C6X Product Identi- for users who choose not to program a medium to high fication System section at the end of this data sheet. quantity of units and whose code patterns have stabi- When placing orders, please use that page of the data lized. The devices are identical to the OTP devices but sheet to specify the correct part number. with all EPROM locations and configuration options For the PIC16C6X family of devices, there are four already programmed by the factory. Certain code and device “types” as indicated in the device number: prototype verification procedures apply before produc- tion shipments are available. Please contact your local 1. C, as in PIC16C64. These devices have Microchip Technology sales office for more details. EPROM type memory and operate over the standard voltage range. 2.4 Serialized Quick-Turnaround 2. LC, as in PIC16LC64. These devices have Production (SQTPSM) Devices EPROM type memory and operate over an extended voltage range. Microchip offers a unique programming service where 3. CR, as in PIC16CR64. These devices have a few user-defined locations in each device are pro- ROM program memory and operate over the grammed with different serial numbers. The serial num- standard voltage range. bers may be random, pseudo-random, or sequential. 4. LCR, as in PIC16LCR64. These devices have Serial programming allows each device to have a ROM program memory and operate over an unique number which can serve as an entry-code, extended voltage range. password, or ID number. ROM devices do not allow serialization information in 2.1 UV Erasable Devices the program memory space. The user may have this The UV erasable version, offered in CERDIP package information programmed in the data memory space. is optimal for prototype development and pilot For information on submitting ROM code, please con- programs. This version can be erased and tact your regional sales office. reprogrammed to any of the oscillator modes. Microchip's PICSTART Plus and PROMATEII 2.5 Read Only Memory (ROM) Devices programmers both support programming of the Microchip offers masked ROM versions of several of PIC16C6X. the highest volume parts, thus giving customers a low cost option for high volume, mature products. 2.2 One-Time-Programmable (OTP) Devices For information on submitting ROM code, please con- tact your regional sales office. The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must also be programmed.  1997-2013 Microchip Technology Inc. DS30234E-page 7

PIC16C6X NOTES: DS30234E-page 8  1997-2013 Microchip Technology Inc.

PIC16C6X 3.0 ARCHITECTURAL OVERVIEW The PIC16CXX device contains an 8-bit ALU and work- ing register (W). The ALU is a general purpose arithme- The high performance of the PIC16CXX family can be tic unit. It performs arithmetic and Boolean functions attributed to a number of architectural features com- between data in the working register and any register monly found in RISC microprocessors. To begin with, file. the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memo- The ALU is 8-bits wide and capable of addition, sub- ries using separate buses. This improves bandwidth traction, shift, and logical operations. Unless otherwise over traditional von Neumann architecture where pro- mentioned, arithmetic operations are two's comple- gram and data may be fetched from the same memory ment in nature. In two-operand instructions, typically using the same bus. Separating program and data bus- one operand is the working register (W register), the ses further allows instructions to be sized differently other operand is a file register or an immediate con- than 8-bit wide data words. Instruction opcodes are stant. In single operand instructions, the operand is 14-bits wide making it possible to have all single word either the W register or a file register. instructions. A 14-bit wide program memory access The W register is an 8-bit working register used for ALU bus fetches a 14-bit instruction in a single cycle. A two- operations. It is not an addressable register. stage pipeline overlaps fetch and execution of instruc- Depending upon the instruction executed, the ALU may tions (Example3-1). Consequently, all instructions exe- affect the values of the Carry (C), Digit Carry (DC), and cute in a single cycle (200ns @ 20MHz) except for Zero (Z) bits in the STATUS register. Bits C and DC program branches. operate as a borrow and digit borrow out bit, respec- The PIC16C61 addresses 1K x 14 of program memory. tively, in subtraction. See the SUBLW and SUBWF The PIC16C62/62A/R62/64/64A/R64 address 2K x 14 instructions for examples. of program memory, and the PIC16C63/R63/65/65A/R65 devices address 4K x 14 of program memory. The PIC16C66/67 address 8Kx14 program memory. All program memory is internal. The PIC16CXX can directly or indirectly address its register files or data memory. All special function reg- isters including the program counter are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of “special optimal situations” makes programming with the PIC16CXX simple yet efficient, thus significantly reducing the learning curve.  1997-2013 Microchip Technology Inc. DS30234E-page 9

PIC16C6X FIGURE 3-1: PIC16C61 BLOCK DIAGRAM 13 Data Bus 8 PORTA EPROM Program Counter RA0 Program RA1 Memory RAM RA2 1K x 14 8 L(e1v3e-lb Sitt)ack RegFiisleters RA3 36 x 8 RA4/T0CKI Program 14 Bus RAM Addr(1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 Indirect 8 Addr FSR reg RB7:RB1 STATUS reg 8 3 Power-up MUX Timer Instruction Oscillator Decode & Start-up Timer ALU Control Power-on Reset 8 Timing Watchdog Generation Timer W reg OSC1/CLKIN OSC2/CLKOUT Timer0 MCLR VDD, VSS Note 1: Higher order bits are from the STATUS register. DS30234E-page 10  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 3-2: PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM 13 Data Bus 8 PORTA EPROM/ Program Counter RA0 ROM RA1 Program M2Ke mx o1r4y 8 L(e1v3e-lb Sitt)ack ReRgFAiisleMters RRRAAA423/T0CKI 128 x 8 RA5/SS ProBgursam 14 RAM Addr(1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 Indirect 8 Addr FSR reg RB7:RB1 STATUS reg 8 PORTC RC0/T1OSO/T1CKI(4) 3 RC1/T1OSI(4) Power-up MUX RC2/CCP1 Timer RC3/SCK/SCL Instruction Oscillator RC4/SDI/SDA Decode & Start-up Timer ALU RC5/SDO Control RC6 Power-on Reset 8 RC7 Timing Watchdog Generation Timer W reg OSC1/CLKIN Brown-out PORTD OSC2/CLKOUT Reset(3) RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 MCLR VDD, VSS RD6/PSP6 RD7/PSP7 Parallel Slave PORTE Port RE0/RD RE1/WR Timer1 Timer2 CCP1 RE2/CS (Note 2) Synchronous Timer0 Serial Port Note 1: Higher order bits are from the STATUS register. 2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C62/62A/R62. 3: Brown-out Reset is not available on the PIC16C62/64. 4: Pin functions T1OSI and T1OSO are swapped on the PIC16C62/64.  1997-2013 Microchip Technology Inc. DS30234E-page 11

PIC16C6X FIGURE 3-3: PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM 13 Data Bus 8 PORTA EPROM Program Counter RA0 RA1 Program M4Ke mx o1r4y 8 L(e1v3e-lb Sitt)ack ReRgFAiisleMters RRRAAA234/T0CKI 192 x 8 RA5/SS ProBgursam 14 RAM Addr(1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 Indirect 8 Addr FSR reg RB7:RB1 STATUS reg 8 PORTC RC0/T1OSO/T1CKI 3 RC1/T1OSI/CCP2 Power-up MUX RC2/CCP1 Timer RC3/SCK/SCL Instruction Oscillator RC4/SDI/SDA Decode & Start-up Timer ALU RC5/SDO Control RC6/TX/CK Power-on Reset 8 RC7/RX/DT Timing Watchdog Generation Timer W reg OOSSCC21//CCLLKKOINUT BRroewsne-t(o3u)t PORTD RRDD01//PPSSPP01 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 MCLR VDD, VSS RD6/PSP6 RD7/PSP7 Parallel Slave Port PORTE RE0/RD RE1/WR Timer0 Timer1 Timer2 RE2/CS (Note 2) Synchronous USART Serial Port CCP1 CCP2 Note 1: Higher order bits are from the STATUS register. 2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C63/R63. 3: Brown-out Reset is not available on the PIC16C65. DS30234E-page 12  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 3-4: PIC16C66/67 BLOCK DIAGRAM 13 Data Bus 8 PORTA EPROM Program Counter RA0 RA1 Program M8Ke mx o1r4y 8 L(e1v3e-lb Sitt)ack ReRgFAiisleMters RRRAAA234/T0CKI 368 x 8 RA5/SS ProBgursam 14 RAM Addr(1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 Indirect 8 Addr FSR reg RB7:RB1 STATUS reg 8 PORTC RC0/T1OSO/T1CKI 3 RC1/T1OSI/CCP2 Power-up MUX RC2/CCP1 Timer RC3/SCK/SCL Instruction Oscillator RC4/SDI/SDA Decode & Start-up Timer ALU RC5/SDO Control RC6/TX/CK Power-on Reset 8 RC7/RX/DT Timing Watchdog Generation Timer W reg OSC1/CLKIN Brown-out PORTD RD0/PSP0 OSC2/CLKOUT Reset RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 MCLR VDD, VSS RD6/PSP6 RD7/PSP7 Parallel Slave Port PORTE RE0/RD RE1/WR Timer0 Timer1 Timer2 RE2/CS (Note 2) Synchronous USART Serial Port CCP1 CCP2 Note 1: Higher order bits are from the STATUS register. 2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C66.  1997-2013 Microchip Technology Inc. DS30234E-page 13

PIC16C6X TABLE 3-1: PIC16C61 PINOUT DESCRIPTION DIP SOIC Buffer Pin Name Pin Type Description Pin# Pin# Type OSC1/CLKIN 16 16 I ST/CMOS(1) Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 4 4 I/P ST Master clear reset input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 17 17 I/O TTL RA1 18 18 I/O TTL RA2 1 1 I/O TTL RA3 2 2 I/O TTL RA4/T0CKI 3 3 I/O ST RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software pro- grammed for internal weak pull-up on all inputs. RB0/INT 6 6 I/O TTL/ST(2) RB0 can also be the external interrupt pin. RB1 7 7 I/O TTL RB2 8 8 I/O TTL RB3 9 9 I/O TTL RB4 10 10 I/O TTL Interrupt on change pin. RB5 11 11 I/O TTL Interrupt on change pin. RB6 12 12 I/O TTL/ST(3) Interrupt on change pin. Serial programming clock. RB7 13 13 I/O TTL/ST(3) Interrupt on change pin. Serial programming data. VSS 5 5 P — Ground reference for logic and I/O pins. VDD 14 14 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 2: This buffer is a Schmitt Trigger input when configured as the external interrupt. 3: This buffer is a Schmitt Trigger input when used in serial programming mode. DS30234E-page 14  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 3-2: PIC16C62/62A/R62/63/R63/66 PINOUT DESCRIPTION Buffer Pin Name Pin# Pin Type Description Type OSC1/CLKIN 9 I ST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crys- tal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 I/P ST Master clear reset input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 2 I/O TTL RA1 3 I/O TTL RA2 4 I/O TTL RA3 5 I/O TTL RA4/T0CKI 6 I/O ST RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. RA5/SS 7 I/O TTL RA5 can also be the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software pro- grammed for internal weak pull-up on all inputs. RB0/INT 21 I/O TTL/ST(4) RB0 can also be the external interrupt pin. RB1 22 I/O TTL RB2 23 I/O TTL RB3 24 I/O TTL RB4 25 I/O TTL Interrupt on change pin. RB5 26 I/O TTL Interrupt on change pin. RB6 27 I/O TTL/ST(5) Interrupt on change pin. Serial programming clock. RB7 28 I/O TTL/ST(5) Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO(1)/T1CKI 11 I/O ST RC0 can also be the Timer1 oscillator output(1) or Timer1 clock input. RC1/T1OSI(1)/CCP2(2) 12 I/O ST RC1 can also be the Timer1 oscillator input(1) or Capture2 input/Compare2 output/PWM2 output(2). RC2/CCP1 13 I/O ST RC2 can also be the Capture1 input/Compare1 out- put/PWM1 output. RC3/SCK/SCL 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK(2) 17 I/O ST RC6 can also be the USART Asynchronous Transmit(2) or Synchronous Clock(2). RC7/RX/DT(2) 18 I/O ST RC7 can also be the USART Asynchronous Receive(2) or Synchronous Data(2). VSS 8,19 P — Ground reference for logic and I/O pins. VDD 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: Pin functions T1OSO and T1OSI are reversed on the PIC16C62. 2: The USART and CCP2 are not available on the PIC16C62/62A/R62. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: This buffer is a Schmitt Trigger input when configured as the external interrupt. 5: This buffer is a Schmitt Trigger input when used in serial programming mode.  1997-2013 Microchip Technology Inc. DS30234E-page 15

PIC16C6X TABLE 3-3: PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION TQFP DIP PLCC Pin Buffer Pin Name MQFP Description Pin# Pin# Type Type Pin# OSC1/CLKIN 13 14 30 I ST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLK- OUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master clear reset input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0 2 3 19 I/O TTL RA1 3 4 20 I/O TTL RA2 4 5 21 I/O TTL RA3 5 6 22 I/O TTL RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. RA5/SS 7 8 24 I/O TTL RA5 can also be the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(4) RB0 can also be the external interrupt pin. RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3 36 39 11 I/O TTL RB4 37 41 14 I/O TTL Interrupt on change pin. RB5 38 42 15 I/O TTL Interrupt on change pin. RB6 39 43 16 I/O TTL/ST(5) Interrupt on change pin. Serial programming clock. RB7 40 44 17 I/O TTL/ST(5) Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO(1)/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output(1) or Timer1 clock input. RC1/T1OSI(1)/CCP2(2) 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input(1) or Capture2 input/Compare2 output/PWM2 output(2). RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 out- put/PWM1 output. RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/out- put for both SPI and I2C modes. RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK(2) 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit(2) or Synchronous Clock(2). RC7/RX/DT(2) 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive(2) or Synchronous Data(2). Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: Pin functions T1OSO and T1OSI are reversed on the PIC16C64. 2: CCP2 and the USART are not available on the PIC16C64/64A/R64. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: This buffer is a Schmitt Trigger input when configured as the external interrupt. 5: This buffer is a Schmitt Trigger input when used in serial programming mode. 6: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). DS30234E-page 16  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 3-3: PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION (Cont.’d) TQFP DIP PLCC Pin Buffer Pin Name MQFP Description Pin# Pin# Type Type Pin# PORTD can be a bi-directional I/O port or parallel slave port for interfacing to a microprocessor bus. RD0/PSP0 19 21 38 I/O ST/TTL(6) RD1/PSP1 20 22 39 I/O ST/TTL(6) RD2/PSP2 21 23 40 I/O ST/TTL(6) RD3/PSP3 22 24 41 I/O ST/TTL(6) RD4/PSP4 27 30 2 I/O ST/TTL(6) RD5/PSP5 28 31 3 I/O ST/TTL(6) RD6/PSP6 29 32 4 I/O ST/TTL(6) RD7/PSP7 30 33 5 I/O ST/TTL(6) PORTE is a bi-directional I/O port. RE0/RD 8 9 25 I/O ST/TTL(6) RE0 can also be read control for the parallel slave port. RE1/WR 9 10 26 I/O ST/TTL(6) RE1 can also be write control for the parallel slave port. RE2/CS 10 11 27 I/O ST/TTL(6) RE2 can also be select control for the parallel slave port. VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins. VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins. NC — 1,17, 12,13, — — These pins are not internally connected. These pins should 28,40 33,34 be left unconnected. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: Pin functions T1OSO and T1OSI are reversed on the PIC16C64. 2: CCP2 and the USART are not available on the PIC16C64/64A/R64. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: This buffer is a Schmitt Trigger input when configured as the external interrupt. 5: This buffer is a Schmitt Trigger input when used in serial programming mode. 6: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus).  1997-2013 Microchip Technology Inc. DS30234E-page 17

PIC16C6X 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining The clock input (from OSC1) is internally divided by An “Instruction Cycle” consists of four Q cycles (Q1, four to generate four non-overlapping quadrature Q2, Q3, and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3, and Q4. Internally, the pro- pipelined such that fetch takes one instruction cycle gram counter (PC) is incremented every Q1, the while decode and execute takes another instruction instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction latched into the instruction register in Q4. The instruc- effectively executes in one cycle. If an instruction tion is decoded and executed during the following Q1 causes the program counter to change (e.g. GOTO) through Q4. The clock and instruction execution flow is then two cycles are required to complete the instruction shown in Figure3-5. (Example3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-5: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC+1 PC+2 (Program counter) OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush 5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30234E-page 18  1997-2013 Microchip Technology Inc.

PIC16C6X 4.0 MEMORY ORGANIZATION FIGURE 4-2: PIC16C62/62A/R62/64/64A/ R64 PROGRAM MEMORY Applicable Devices 616262AR6263R636464AR646565AR656667 MAP AND STACK 4.1 Program Memory Organization PC<12:0> CALL, RETURN 13 The PIC16C6X family has a 13-bit program counter RETFIE, RETLW capable of addressing an 8K x14 program memory Stack Level 1  space. The amount of program memory available to   each device is listed below: Stack Level 8 Device Program Address Range Reset Vector 0000h Memory ory Peripheral Interrupt Vector 0004h PIC16C61 1K x 14 0000h-03FFh me 0005h PPIICC1166CC6622A 22KK xx 1144 00000000hh--0077FFFFhh User MeSpac On-cMhiepm Pororygram PIC16CR62 2K x 14 0000h-07FFh 07FFh PIC16C63 4K x 14 0000h-0FFFh 0800h PIC16CR63 4K x 14 0000h-0FFFh PIC16C64 2K x 14 0000h-07FFh PIC16C64A 2K x 14 0000h-07FFh PIC16CR64 2K x 14 0000h-07FFh 1FFFh PIC16C65 4K x 14 0000h-0FFFh PIC16C65A 4K x 14 0000h-0FFFh FIGURE 4-3: PIC16C63/R63/65/65A/R65 PIC16CR65 4K x 14 0000h-0FFFh PROGRAM MEMORY MAP PIC16C66 8K x 14 0000h-1FFFh AND STACK PIC16C67 8K x 14 0000h-1FFFh PC<12:0> For those devices with less than 8K program memory, CALL, RETURN 13 accessing a location above the physically implemented RETFIE, RETLW address will cause a wraparound. Stack Level 1   The reset vector is at 0000h and the interrupt vector is  at 0004h. Stack Level 8 FIGURE 4-1: PIC16C61 PROGRAM Reset Vector 0000h MEMORY MAP AND STACK Peripheral Interrupt Vector 0004h 0005h PC<12:0> CALL, RETURN 13 RETFIE, RETLW y On-chip Program SSttaacckk LLeevveell 81 ser MemorSpace Memory (Page 0) 0078F00Fhh U Reset Vector 0000h On-chip Program ory Peripheral Interrupt Vector 0004h Memory (Page 1) me 0005h er MeSpac On-chip Program 0FFFh Us Memory 1000h 03FFh 0400h 1FFFh 1FFFh  1997-2013 Microchip Technology Inc. DS30234E-page 19

PIC16C6X FIGURE 4-4: PIC16C66/67 PROGRAM For the PIC16C61, general purpose register locations MEMORY MAP AND STACK 8Ch-AFh of Bank 1 are not physically implemented. These locations are mapped into 0Ch-2Fh of Bank 0. PC<12:0> FIGURE 4-5: PIC16C61 REGISTER FILE CALL, RETURN 13 RETFIE, RETLW MAP Stack Level 1  File Address File Address   00h INDF(1) INDF(1) 80h Stack Level 8 01h TMR0 OPTION 81h Reset Vector 0000h 02h PCL PCL 82h Peripheral Interrupt Vector 0004h 03h STATUS STATUS 83h 0005h 04h FSR FSR 84h On-chip Program y Memory (Page 0) 05h PORTA TRISA 85h more 07FFh 06h PORTB TRISB 86h User MeSpac OMne-mchoirpy P(Proaggrea m1) 0800h 0078hh 8878hh 0FFFh 1000h 09h 89h On-chip Program 0Ah PCLATH PCLATH 8Ah Memory (Page 2) 0Bh INTCON INTCON 8Bh 17FFh 0Ch 8Ch 1800h On-chip Program Memory (Page 3) PGuernpeorsael inM Baapnpke 0d(2) Register 1FFFh 2Fh AFh 4.2 Data Memory Organization 30h B0h Applicable Devices 616262AR6263R636464AR646565AR656667 The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. RP1:RP0 (STATUS<6:5>) = 00  Bank0 = 01  Bank1 = 10  Bank2 = 11  Bank3 7Fh FFh Each bank extends up to 7Fh (128 bytes). The lower Bank 0 Bank 1 locations of each bank are reserved for the Special Unimplemented data memory location; read as '0'. Function Registers. Above the Special Function Regis- Note 1: Not a physical register. ters are General Purpose Registers, implemented as 2: These locations are unimplemented in static RAM. All implemented banks contain special Bank1. Any access to these locations will function registers. Some “high use” special function access the corresponding Bank0 register. registers from one bank may be mirrored in another bank for code reduction and quicker access. 4.2.1 GENERAL PURPOSE REGISTERS These registers are accessed either directly or indi- rectly through the File Select Register (FSR) (Section4.5). DS30234E-page 20  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 4-6: PIC16C62/62A/R62/64/64A/ FIGURE 4-7: PIC16C63/R63/65/65A/R65 R64 REGISTER FILE MAP REGISTER FILE MAP File Address File Address File Address File Address 00h INDF(1) INDF(1) 80h 00h INDF(1) INDF(1) 80h 01h TMR0 OPTION 81h 01h TMR0 OPTION 81h 02h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h 07h PORTC TRISC 87h 07h PORTC TRISC 87h 08h PORTD(2) TRISD(2) 88h 08h PORTD(2) TRISD(2) 88h 09h PORTE(2) TRISE(2) 89h 09h PORTE(2) TRISE(2) 89h 0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Ch PIR1 PIE1 8Ch 0Dh 8Dh 0Dh PIR2 PIE2 8Dh 0Eh TMR1L PCON 8Eh 0Eh TMR1L PCON 8Eh 0Fh TMR1H 8Fh 0Fh TMR1H 8Fh 10h T1CON 90h 10h T1CON 90h 11h TMR2 91h 11h TMR2 91h 12h T2CON PR2 92h 12h T2CON PR2 92h 13h SSPBUF SSPADD 93h 13h SSPBUF SSPADD 93h 14h SSPCON SSPSTAT 94h 14h SSPCON SSPSTAT 94h 15h CCPR1L 95h 15h CCPR1L 95h 16h CCPR1H 96h 16h CCPR1H 96h 17h CCP1CON 97h 17h CCP1CON 97h 18h 98h 18h RCSTA TXSTA 98h 19h TXREG SPBRG 99h 1Ah RCREG 9Ah 1Bh CCPR2L 9Bh 1Fh 9Fh 1Ch CCPR2H 9Ch 20h A0h 1Dh CCP2CON 9Dh General Purpose 1Eh 9Eh General Register Purpose BFh 1Fh 9Fh Register C0h 20h A0h General General Purpose Purpose 7Fh FFh 7Fh Register Register FFh Bank 0 Bank 1 Bank 0 Bank 1 Unimplemented data memory location; read as '0'. Unimplemented data memory location; read as '0'. Note 1: Not a physical register. Note 1: Not a physical register 2: PORTD and PORTE are not available on 2: PORTD and PORTE are not available on the PIC16C62/62A/R62. the PIC16C63/R63.  1997-2013 Microchip Technology Inc. DS30234E-page 21

PIC16C6X FIGURE 4-8: PIC16C66/67 DATA MEMORY MAP File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 01h OPTION 81h TMR0 101h OPTION 181h PCL 02h PCL 82h PCL 102h PCL 182h STATUS 03h STATUS 83h STATUS 103h STATUS 183h FSR 04h FSR 84h FSR 104h FSR 184h PORTA 05h TRISA 85h 105h 185h PORTB 06h TRISB 86h PORTB 106h TRISB 186h PORTC 07h TRISC 87h 107h 187h PORTD(1) 08h TRISD(1) 88h 108h 188h PORTE(1) 09h TRISE(1) 89h 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh PIR1 0Ch PIE1 8Ch 10Ch 18Ch PIR2 0Dh PIE2 8Dh 10Dh 18Dh TMR1L 0Eh PCON 8Eh 10Eh 18Eh TMR1H 0Fh 8Fh 10Fh 18Fh T1CON 10h 90h 110h 190h TMR2 11h 91h 111h 191h T2CON 12h PR2 92h 112h 192h SSPBUF 13h SSPADD 93h 113h 193h SSPCON 14h SSPSTAT 94h 114h 194h CCPR1L 15h 95h 115h 195h CCPR1H 16h 96h 116h 196h CCP1CON 17h 97h General 117h General 197h Purpose Purpose RCSTA 18h TXSTA 98h Register 118h Register 198h TXREG 19h SPBRG 99h 16 Bytes 119h 16 Bytes 199h RCREG 1Ah 9Ah 11Ah 19Ah CCPR2L 1Bh 9Bh 11Bh 19Bh CCPR2H 1Ch 9Ch 11Ch 19Ch CCP2CON 1Dh 9Dh 11Dh 19Dh 1Eh 9Eh 11Eh 19Eh 1Fh 9Fh 11Fh 19Fh 20h A0h 120h 1A0h General General General General Purpose Purpose Purpose Purpose Register Register Register Register 80 Bytes 80 Bytes 80 Bytes 96 Bytes EFh 16Fh 1EFh accesses F0h accesses 170h accesses 1F0h 70h-7Fh 70h-7Fh 70h-7Fh in Bank 0 in Bank 0 in Bank 0 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Unimplemented data memory locations, read as '0'. * Not a physical register. These registers are not implemented on the PIC16C66. Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require relocation of data memory usage in the user application code if upgrading to the PIC16C66/67. DS30234E-page 22  1997-2013 Microchip Technology Inc.

PIC16C6X 4.2.2 SPECIAL FUNCTION REGISTERS: The special function registers can be classified into two sets (core and peripheral). The registers associated The Special Function Registers are registers used by with the “core” functions are described in this section the CPU and peripheral modules for controlling the and those related to the operation of the peripheral fea- desired operation of the device. These registers are tures are described in the section of that peripheral fea- implemented as static RAM. ture. TABLE 4-1: SPECIAL FUNCTION REGISTERS FOR THE PIC16C61 Value on Value on: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — — PORTA Data Latch when written: PORTA pins when read ---x xxxx ---u uuuu 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(1) INTCON GIE — T0IE INTE RBIE T0IF INTF RBIF 0-00 000x 0-00 000u Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111 86h TRISB PORTB Data Direction Control Register 1111 1111 1111 1111 87h – Unimplemented — — 88h – Unimplemented — — 89h – Unimplemented — — 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(1) INTCON GIE — T0IE INTE RBIE T0IF INTF RBIF 0-00 000x 0-00 000u Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'. Shaded locations are unimplemented and read as ‘0’ Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose con- tents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 23

PIC16C6X TABLE 4-2: SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS IRP(5) RP1(5) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (6) (6) — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 0Dh — Unimplemented — — 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h-1Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C62, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear. 6: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear. DS30234E-page 24  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 4-2: SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62 (Cont.’d) Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(1) STATUS IRP(5) RP1(5) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h — Unimplemented — — 89h — Unimplemented — — 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 (6) (6) — — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR(4) ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h-9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C62, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear. 6: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 25

PIC16C6X TABLE 4-3: SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h — Unimplemented — — 09h — Unimplemented — — 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (5) (5) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — —– — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 1Eh-1Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear. 5: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 26

PIC16C6X TABLE 4-3: SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 (Cont.’d) Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(1) STATUS IRP(4) RP1(4) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h — Unimplemented — — 89h — Unimplemented — — 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 (5) (5) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h(2) TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h(2) SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear. 5: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 27

PIC16C6X TABLE 4-4: SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS IRP(5) RP1(5) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF (6) — — SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 0Dh — Unimplemented — — 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h-1Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C64, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear. 6: PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear. DS30234E-page 28  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 4-4: SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64 (Cont.’d) Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(1) STATUS IRP(5) RP1(5) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE (6) — — SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR(4) ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h-9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C64, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear. 6: PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 29

PIC16C6X TABLE 4-5: SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS IRP(5) RP1(5) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF (6) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — —– — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 1Eh-1Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C65, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear. 6: PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear. DS30234E-page 30  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 4-5: SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 (Cont.’d) Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(1) STATUS IRP(5) RP1(5) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE (6) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR(4) ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from either bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: The BOR bit is reserved on the PIC16C65, always maintain this bit set. 5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear. 6: PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 31

PIC16C6X TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 0 00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --xx xxxx --uu uuuu 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(6) (4) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — —– — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 1Eh-1Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear. 5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'. 6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear. DS30234E-page 32  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d) Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 1 80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE(6) (4) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear. 5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'. 6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 33

PIC16C6X TABLE 4-6: SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d) Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets(3) Bank 2 100h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 102h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 103h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 104h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 10Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Ch- — Unimplemented — — 10Fh Bank 3 180h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 183h(1) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 184h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 18Bh(1) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 18Ch- — Unimplemented — — 19Fh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>) 3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset. 4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear. 5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'. 6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear. DS30234E-page 34  1997-2013 Microchip Technology Inc.

PIC16C6X 4.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the Applicable Devices STATUS register because these instructions do not 616262AR6263R636464AR646565AR656667 affect the Z, C or DC bits from the STATUS register. For The STATUS register, shown in Figure4-9, contains other instructions, not affecting any status bits, see the the arithmetic status of the ALU, the RESET status and “Instruction Set Summary.” the bank select bits for data memory. Note 1: For those devices that do not use bits IRP The STATUS register can be the destination for any and RP1 (STATUS<7:6>), maintain these instruction, as with any other register. If the STATUS bits clear to ensure upward compatibility register is the destination for an instruction that affects with future products. the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the Note 2: The C and DC bits operate as a borrow device logic. Furthermore, the TO and PD bits are not and digit borrow bit, respectively, in sub- writable. Therefore, the result of an instruction with the traction. See the SUBLW and SUBWF STATUS register as destination may be different than instructions for examples. intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 4-9: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C R = Readable bit bit7 bit0 W = Writable bit - n = Value at POR reset x = unknown bit 7: IRP: RegIster Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF, ADDLW,SUBLW, and SUBWF instructions) (For borrow the polarity is reversed). 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (for ADDWF, ADDLW,SUBLW, and SUBWF instructions)( For borrow the polarity is reversed). 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result Note: a subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.  1997-2013 Microchip Technology Inc. DS30234E-page 35

PIC16C6X 4.2.2.2 OPTION REGISTER Note: To achieve a 1:1 prescaler assignment for Applicable Devices TMR0 register, assign the prescaler to the 616262AR6263R636464AR646565AR656667 Watchdog Timer. The OPTION register is a readable and writable regis- ter which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-10: OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS30234E-page 36  1997-2013 Microchip Technology Inc.

PIC16C6X 4.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt Applicable Devices condition occurs regardless of the state of 616262AR6263R636464AR646565AR656667 its corresponding enable bit or the global The INTCON Register is a readable and writable regis- enable bit, GIE (INTCON<7>). ter which contains the various enable and flag bits for the TMR0 register overflow, RB port change and exter- nal RB0/INT pin interrupts. FIGURE 4-11: INTCON REGISTER (ADDRESS0Bh,8Bh, 10Bh 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset x = unknown bit 7: GIE:(1) Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE:(2) Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (see Section5.2 to clear the interrupt) 0 = None of the RB7:RB4 pins have changed state Note 1: For the PIC16C61/62/64/65, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may unintentionally be re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section13.5 for a detailed description. 2: The PEIE bit (bit6) is unimplemented on the PIC16C61, read as '0'. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  1997-2013 Microchip Technology Inc. DS30234E-page 37

PIC16C6X 4.2.2.4 PIE1 REGISTER Note: Bit PEIE (INTCON<6>) must be set to Applicable Devices enable any peripheral interrupt. 616262AR6263R636464AR646565AR656667 This register contains the individual enable bits for the peripheral interrupts. FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch) RW-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Reserved: Always maintain these bits clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30234E-page 38  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 4-13: PIE1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Reserved: Always maintain these bits clear. bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt FIGURE 4-14: PIE1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 8Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE — — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: Reserved: Always maintain this bit clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt  1997-2013 Microchip Technology Inc. DS30234E-page 39

PIC16C6X FIGURE 4-15: PIE1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 8Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE — RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: Reserved: Always maintain this bit clear. bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30234E-page 40  1997-2013 Microchip Technology Inc.

PIC16C6X 4.2.2.5 PIR1 REGISTER Note: Interrupt flag bits get set when an interrupt Applicable Devices condition occurs regardless of the state of 616262AR6263R636464AR646565AR656667 its corresponding enable bit or the global This register contains the individual flag bits for the enable bit, GIE (INTCON<7>). User soft- peripheral interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 4-16: PIR1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Reserved: Always maintain these bits clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflow occurred (must be cleared in software) 0 = No TMR1 register overflow occurred Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  1997-2013 Microchip Technology Inc. DS30234E-page 41

PIC16C6X FIGURE 4-17: PIR1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Reserved: Always maintain these bits clear. bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflow occurred (must be cleared in software) 0 = No TMR1 register overflow occurred Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30234E-page 42  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 4-18: PIR1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF — — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIF: Parallel Slave Port Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write operation has taken place bit 6: Reserved: Always maintain this bit clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflow occurred (must be cleared in software) 0 = No TMR1 register occurred Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  1997-2013 Microchip Technology Inc. DS30234E-page 43

PIC16C6X FIGURE 4-19: PIR1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 0Ch) R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF — RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIF: Parallel Slave Port Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write operation has taken place bit 6: Reserved: Always maintain this bit clear. bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflow occurred (must be cleared in software) 0 = No TMR1 register overflow occurred Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30234E-page 44  1997-2013 Microchip Technology Inc.

PIC16C6X 4.2.2.6 PIE2 REGISTER Applicable Devices 616262AR6263R636464AR646565AR656667 This register contains the CCP2 interrupt enable bit. FIGURE 4-20: PIE2 REGISTER (ADDRESS 8Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt  1997-2013 Microchip Technology Inc. DS30234E-page 45

PIC16C6X 4.2.2.7 PIR2 REGISTER . Note: Interrupt flag bits get set when an interrupt Applicable Devices condition occurs regardless of the state of 616262AR6263R636464AR646565AR656667 its corresponding enable bit or the global This register contains the CCP2 interrupt flag bit. enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 4-21: PIR2 REGISTER (ADDRESS 0Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS30234E-page 46  1997-2013 Microchip Technology Inc.

PIC16C6X 4.2.2.8 PCON REGISTER Note: BOR is unknown on Power-on Reset. It Applicable Devices must then be set by the user and checked 616262AR6263R636464AR646565AR656667 on subsequent resets to see if BOR is The Power Control register (PCON) contains a flag bit clear, indicating a brown-out has occurred. to allow differentiation between a Power-on Reset to an The BOR status bit is a “don't care” and is external MCLR reset or WDT reset. Those devices with not necessarily predictable if the brown-out brown-out detection circuitry contain an additional bit to circuit is disabled (by clearing the BODEN differentiate a Brown-out Reset condition from a Power- bit in the Configuration word). on Reset condition. FIGURE 4-22: PCON REGISTER FOR PIC16C62/64/65 (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR — R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset q = value depends on conditions bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: Reserved This bit should be set upon a Power-on Reset by user software and maintained as set. Use of this bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. FIGURE 4-23: PCON REGISTER FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67 (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset q = value depends on conditions bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)  1997-2013 Microchip Technology Inc. DS30234E-page 47

PIC16C6X 4.3 PCL and PCLATH Note 1: There are no status bits to indicate stack Applicable Devices overflows or stack underflow conditions. 616262AR6263R636464AR646565AR656667 Note 2: There are no instructions mnemonics The program counter (PC) is 13-bits wide. The low byte called PUSH or POP. These are actions comes from the PCL register, which is a readable and that occur from the execution of the writable register. The upper bits (PC<12:8>) are not CALL, RETURN, RETLW, and RETFIE readable, but are indirectly writable through the instructions, or the vectoring to an inter- PCLATH register. On any reset, the upper bits of the PC rupt address will be cleared. Figure4-24 shows the two situations for 4.4 Program Memory Paging the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL Applicable Devices (PCLATH<4:0>  PCH). The lower example in the fig- 616262AR6263R636464AR646565AR656667 ure shows how the PC is loaded during a CALL or GOTO PIC16C6X devices are capable of addressing a contin- instruction (PCLATH<4:3>  PCH). uous 8K word block of program memory. The CALL and FIGURE 4-24: LOADING OF PC IN GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. DIFFERENT SITUATIONS When doing a CALL or GOTO instruction the upper two PCH PCL bits of the address are provided by PCLATH<4:3>. 12 8 7 0 Instruction with When doing a CALL or GOTO instruction, the user must PC PCL as ensure that the page select bits are programmed so destination that the desired program memory page is addressed. If 5 PCLATH<4:0> 8 ALU a return from a CALL instruction (or interrupt) is exe- cuted, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are PCLATH not required for the return instructions (which POPs the address from the stack). PCH PCL 12 11 10 8 7 0 Note: PIC16C6X devices with 4K or less of pro- PC GOTO, CALL gram memory ignore paging bit PCLATH<4:3> 11 PCLATH<4>. The use of PCLATH<4> as a 2 Opcode <10:0> general purpose read/write bit is not rec- ommended since this may affect upward PCLATH compatibility with future products. 4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 word block). Refer to the application note “Implementing a Table Read” (AN556). 4.3.2 STACK The PIC16CXX family has an 8 deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or a POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS30234E-page 48  1997-2013 Microchip Technology Inc.

PIC16C6X Example4-1 shows the calling of a subroutine in 4.5 Indirect Addressing, INDF and FSR page1 of the program memory. This example assumes Registers that the PCLATH is saved and restored by the interrupt Applicable Devices service routine (if interrupts are used). 616262AR6263R636464AR646565AR656667 The INDF register is not a physical register. Address- EXAMPLE 4-1: CALL OF A SUBROUTINE IN ing the INDF register will cause indirect addressing. PAGE 1 FROM PAGE 0 ORG 0x500 Indirect addressing is possible by using the INDF reg- BSF PCLATH,3 ;Select page 1 (800h-FFFh) ister. Any instruction using the INDF register actually BCF PCLATH,4 ;Only on >4K devices accesses the register pointed to by the File Select Reg- CALL SUB1_P1 ;Call subroutine in ister, FSR. Reading the INDF register itself indirectly : ;page 1 (800h-FFFh) (FSR = '0') will produce 00h. Writing to the INDF regis- : ter indirectly results in a no-operation (although status : bits may be affected). An effective 9-bit address is ORG 0x900 obtained by concatenating the 8-bit FSR register and SUB1_P1: ;called subroutine the IRP bit (STATUS<7>), as shown in Figure4-25. : ;page 1 (800h-FFFh) : A simple program to clear RAM location 20h-2Fh using RETURN ;return to Call subroutine indirect addressing is shown in Example4-2. ;in page 0 (000h-7FFh) EXAMPLE 4-2: INDIRECT ADDRESSING movlw 0x20 ;initialize pointer movwf FSR ; to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;NO, clear next CONTINUE : ;YES, continue FIGURE 4-25: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 from opcode 0 IRP 7 FSR 0 bank select location select bank select location select 00 01 10 11 00h 80h 100h 180h Data Memory 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figure4-5, Figure4-6, Figure4-7, and Figure4-8.  1997-2013 Microchip Technology Inc. DS30234E-page 49

PIC16C6X NOTES: DS30234E-page 50  1997-2013 Microchip Technology Inc.

PIC16C6X 5.0 I/O PORTS FIGURE 5-1: BLOCK DIAGRAM OF THE RA3:RA0 PINS AND THE RA5 Applicable Devices 616262AR6263R636464AR646565AR656667 PIN Some pins for these I/O ports are multiplexed with an Data alternate function(s) for the peripheral features on the bus device. In general, when a peripheral is enabled, that D Q pin may not be used as a general purpose I/O pin. WR VDD Port 5.1 PORTA and TRISA Register CK Q P Applicable Devices Data Latch 616262AR6263R636464AR646565AR656667 All devices have a 6-bit wide PORTA, except for the D Q N I/O pin(1) PIC16C61 which has a 5-bit wide PORTA. WR Pin RA4/T0CKI is a Schmitt Trigger input and an open TRIS CK Q VSS drain output. All other RA port pins have TTL input lev- els and full CMOS output drivers. All pins have data TRIS Latch TTL input direction bits (TRIS registers) which can configure buffer these pins as output or input. Setting a bit in the TRISA register puts the correspond- RD TRIS ing output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output Q D latch on the selected pin. Reading PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write EN operations are read-modify-write operations. There- fore, a write to a port implies that the port pins are read, RD PORT this value is modified, and then written to the port data latch. Note 1: I/O pins have protection diodes to VDD and Pin RA4 is multiplexed with Timer0 module clock input VSS. to become the RA4/T0CKI pin. 2: The PIC16C61 does not have an RA5 pin. EXAMPLE 5-1: INITIALIZING PORTA FIGURE 5-2: BLOCK DIAGRAM OF THE RA4/T0CKI PIN BCF STATUS, RP0 ; BCF STATUS, RP1 ; PIC16C66/67 only Data CLRF PORTA ; Initialize PORTA by bus D Q ; clearing output WR ; data latches PORT BSF STATUS, RP0 ; Select Bank 1 CK Q N I/O pin(1) MOVLW 0xCF ; Value used to Data Latch ; initialize data ; direction D Q VSS WR MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs TRIS CK Q STrcighgmeirtt ; TRISA<7:6> are always input TRIS Latch ; read as '0'. buffer RD TRIS Q D ENEN RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only.  1997-2013 Microchip Technology Inc. DS30234E-page 51

PIC16C6X TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Type Function RA0 bit0 TTL Input/output RA1 bit1 TTL Input/output RA2 bit2 TTL Input/output RA3 bit3 TTL Input/output RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/SS (1) bit5 TTL Input/output or slave select input for synchronous serial port. Legend:TTL = TTL input, ST = Schmitt Trigger input Note1: The PIC16C61 does not have PORTA<5> or TRISA<5>, read as ‘0’. TABLE 5-2: REGISTERS/BITS ASSOCIATED WITH PORTA Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 05h PORTA — — RA5(1) RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu 85h TRISA — — PORTA Data Direction Register(1) --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: PORTA<5> and TRISA<5> are not implemented on the PIC16C61, read as '0'. DS30234E-page 52  1997-2013 Microchip Technology Inc.

PIC16C6X 5.2 PORTB and TRISB Register This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the inter- Applicable Devices rupt in the following manner: 616262AR6263R636464AR646565AR656667 PORTB is an 8-bit wide bi-directional port. The corre- a) Any read or write of PORTB. This will end the sponding data direction register is TRISB. Setting a bit mismatch condition. in the TRISB register puts the corresponding output b) Clear flag bit RBIF. driver in a hi-impedance mode. Clearing a bit in the A mismatch condition will continue to set flag bit RBIF. TRISB register puts the contents of the output latch on Reading PORTB will end the mismatch condition, and the selected pin(s). allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with soft- EXAMPLE 5-2: INITIALIZING PORTB ware configurable pull-ups on these four pins allow BCF STATUS, RP0 ; easy interface to a keypad and make it possible for CLRF PORTB ; Initialize PORTB by wake-up on key-depression. Refer to the Embedded ; clearing output Control Handbook, Application Note, “Implementing ; data latches Wake-up on Key Stroke” (AN552). BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to Note: For PIC16C61/62/64/65, if a change on the ; initialize data I/O pin should occur when a read operation ; direction MOVWF TRISB ; Set RB<3:0> as inputs is being executed (start of the Q2 cycle), ; RB<5:4> as outputs then interrupt flag bit RBIF may not get set. ; RB<7:6> as inputs The interrupt on change feature is recommended for Each of the PORTB pins has a weak internal pull-up. A wake-up on key depression operation and operations single control bit can turn on all the pull-ups. This is where PORTB is only used for the interrupt on change performed by clearing bit RBPU (OPTION<7>). The feature. Polling of PORTB is not recommended while weak pull-up is automatically turned off when the port using the interrupt on change feature. pin is configured as an output. The pull-ups are also FIGURE 5-3: BLOCK DIAGRAM OF THE disabled on a Power-on Reset. RB7:RB4 PINS FOR Four of PORTB’s pins, RB7:RB4, have an interrupt on PIC16C61/62/64/65 change feature. Only pins configured as inputs can VDD cause this interrupt to occur (i.e., any RB7:RB4 pin RBPU(2) weak configured as an output is excluded from the interrupt P pull-up on change comparison). The input pins (of RB7:RB4) Data Latch Data bus are compared with the old value latched on the last D Q read of PORTB. The “mismatch” outputs of RB7:RB4 I/O are OR’ed together to generate the RB port change WR Port CK pin(1) interrupt with flag bit RBIF (INTCON<0>). TRIS Latch D Q WR TRIS CK TInTpLut Buffer ST Buffer RD TRIS Latch Q D RD Port EN Set RBIF From other Q D RB7:RB4 pins EN RD Port RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RPBU bit (OPTION<7>).  1997-2013 Microchip Technology Inc. DS30234E-page 53

PIC16C6X FIGURE 5-4: BLOCK DIAGRAM OF THE FIGURE 5-5: BLOCK DIAGRAM OF THE RB7:RB4 PINS FOR RB3:RB0 PINS PIC16C62A/63/R63/64A/65A/ VDD R65/66/67 RBPU(2) weak P pull-up VDD Data Latch RBPU(2) P wpuelal-kup Data bus D Q Data Latch WR Port I/O Data bus D Q CK pin(1) I/O TRIS Latch WR Port CK pin(1) D Q TTL TRIS Latch WR TRIS CK IBnupfufetr D Q WR TRIS CK TInTpLut Buffer ST RD TRIS Buffer Q D RD TRIS Latch RD Port EN Q D RD Port EN Q1 RB0/INT Set RBIF Schmitt Trigger RD Port Buffer From other Q D RB7:RB4 pins RD Port EN Note 1: I/O pins have diode protection to VDD and VSS. Q3 2: To enable weak pull-ups, set the appropriate TRIS bit(s) RB7:RB6 in serial programming mode and clear the RPBU bit (OPTION<7>). Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RPBU bit (OPTION<7>). TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Type Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30234E-page 54  1997-2013 Microchip Technology Inc.

PIC16C6X 5.3 PORTC and TRISC Register FIGURE 5-6: PORTC BLOCK DIAGRAM Applicable Devices PORT/PERIPHERAL Select(2) 616262AR6263R636464AR646565AR656667 PORTC is an 8-bit wide bi-directional port. Each pin is Peripheral Data Out 0 VDD Data bus individually configurable as an input or output through WR D Q 1 P the TRISC register. PORTC is multiplexed with several PORT CK Q peripheral functions (Table5-5). PORTC pins have Data Latch Schmitt Trigger input buffers. D Q I/O When enabling peripheral functions, care should be WR pin(1) taken in defining TRIS bits for each PORTC pin. Some TRIS CK Q N peripherals override the TRIS bit to make a pin an out- TRIS Latch put, while other peripherals override the TRIS bit to VSS make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify- RD TRIS STrcighgmeirtt write instructions (BSF, BCF, XORWF) with TRISC as Peripheral destination should be avoided. The user should refer to OE(3) Q D the corresponding peripheral section for the correct TRIS bit settings. RD EN PORT EXAMPLE 5-3: INITIALIZING PORTC Peripheral input BCF STATUS, RP0 ; BCF STATUS, RP1 ; PIC16C66/67 only Note 1: I/O pins have diode protection to VDD and VSS. 2: Port/Peripheral select signal selects between port CLRF PORTC ; Initialize PORTC by data and peripheral output. ; clearing output 3: Peripheral OE (output enable) is only activated if ; data latches peripheral select is active. BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs TABLE 5-5: PORTC FUNCTIONS FOR PIC16C62/64 Name Bit# Buffer Type Function RC0/T1OSI/T1CKI bit0 ST Input/output port pin or Timer1 oscillator input or Timer1 clock input RC1/T1OSO bit1 ST Input/output port pin or Timer1 oscillator output RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or synchronous serial port data output RC6 bit6 ST Input/output port pin RC7 bit7 ST Input/output port pin Legend:ST = Schmitt Trigger input  1997-2013 Microchip Technology Inc. DS30234E-page 55

PIC16C6X TABLE 5-6: PORTC FUNCTIONS FOR PIC16C62A/R62/64A/R64 Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output or Timer1 clock input RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture input/Compare output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or synchronous serial port data output RC6 bit6 ST Input/output port pin RC7 bit7 ST Input/output port pin Legend:ST = Schmitt Trigger input TABLE 5-7: PORTC FUNCTIONS FOR PIC16C63/R63/65/65A/R65/66/67 Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output or Timer1 clock input RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or synchronous serial port data output RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART Syn- chronous Clock RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive, or USART Syn- chronous Data Legend:ST = Schmitt Trigger input TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. DS30234E-page 56  1997-2013 Microchip Technology Inc.

PIC16C6X 5.4 PORTD and TRISD Register FIGURE 5-7: PORTD BLOCK DIAGRAM (IN I/O PORT MODE) Applicable Devices 616262AR6263R636464AR646565AR656667 Data PORTD is an 8-bit port with Schmitt Trigger input buf- bus D Q fers. Each pin is individually configurable as input or WR output. PORT I/O pin(1) CK PORTD can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit Data Latch PSPMODE (TRISE<4>). In this mode, the input buffers D Q are TTL. WR TRIS CK Schmitt Trigger input TRIS Latch buffer RD TRIS Q D ENEN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. TABLE 5-9: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0 RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1 RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2 RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3 RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4 RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5 RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6 RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7 Legend: ST = Schmitt Trigger input, TTL = TTL input Note1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port mode. TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTD.  1997-2013 Microchip Technology Inc. DS30234E-page 57

PIC16C6X 5.5 PORTE and TRISE Register FIGURE 5-8: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) Applicable Devices 616262AR6263R636464AR646565AR656667 Data PORTE has three pins, RE2/CS, RE1/WR, and bus D Q RE0/RD which are individually configurable as inputs WR or outputs. These pins have Schmitt Trigger input buf- PORT CK I/O pin(1) fers. Data Latch I/O PORTE becomes control inputs for the micropro- D Q cessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the WR TRISE<2:0> bits are set (pins are configured as digital TRIS CK STrcighgmeirtt inputs). In this mode the input buffers are TTL. input TRIS Latch buffer Figure5-9 shows the TRISE register, which controls the parallel slave port operation and also controls the direction of the PORTE pins. RD TRIS Q D ENEN RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 5-9: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — bit2 bit1 bit0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7 : IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6: OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4: PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode bit 3: Unimplemented: Read as '0' PORTE Data Direction Bits bit 2: Bit2: Direction Control bit for pin RE2/CS 1 = Input 0 = Output bit 1: Bit1: Direction Control bit for pin RE1/WR 1 = Input 0 = Output bit 0: Bit0: Direction Control bit for pin RE0/RD 1 = Input 0 = Output DS30234E-page 58  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 5-11: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD bit0 ST/TTL(1) Input/output port pin or Read control input in parallel slave port mode. RD 1 = Not a read operation 0 = Read operation. The system reads the PORTD register (if chip selected) RE1/WR bit1 ST/TTL(1) Input/output port pin or Write control input in parallel slave port mode. WR 1 = Not a write operation 0 = Write operation. The system writes to the PORTD register (if chip selected) RE2/CS bit2 ST/TTL(1) Input/output port pin or Chip select control input in parallel slave port mode. CS 1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input, TTL = TTL input Note1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port (PSP) mode. TABLE 5-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells not used by PORTE.  1997-2013 Microchip Technology Inc. DS30234E-page 59

PIC16C6X 5.6 I/O Programming Considerations EXAMPLE 5-4: READ-MODIFY-WRITE INSTRUCTIONS ON AN Applicable Devices 616262AR6263R636464AR646565AR656667 I/O PORT 5.6.1 BI-DIRECTIONAL I/O PORTS ;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs Any instruction which writes, operates internally as a ;PORTB<7:6> have external pull-ups and are read followed by a write operation. The BCF and BSF ;not connected to other circuitry instructions, for example, read the register into the ; ; PORT latch PORT pins CPU, execute the bit operation and write the result back ; ---------- --------- to the register. Caution must be used when these BCF PORTB, 7 ; 01pp pppp 11pp pppp instructions are applied to a port with both inputs and BCF PORTB, 6 ; 10pp pppp 11pp pppp outputs defined. For example, a BSF operation on bit5 BSF STATUS, RP0 ; of PORTB will cause all eight bits of PORTB to be read BCF TRISB, 7 ; 10pp pppp 11pp pppp into the CPU. Then the BSF operation takes place on BCF TRISB, 6 ; 10pp pppp 10pp pppp bit5 and PORTB is written to the output latches. If ; another bit of PORTB is used as a bi-directional I/O pin ;Note that the user may have expected the (e.g., bit0) and it is defined as an input at this time, the ;pin values to be 00pp pppp. The 2nd BCF input signal present on the pin itself would be read into ;caused RB7 to be latched as the pin value ;(high). the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin A pin actively outputting a Low or High should not be stays in the input mode, no problem occurs. However, if driven from external devices at the same time in order bit0 is switched into output mode later on, the content to change the level on this pin (“wired-or”, “wired-and”). of the data latch may now be unknown. The resulting high output currents may damage the chip. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the 5.6.2 SUCCESSIVE OPERATIONS ON I/O PORTS port latch. When using read-modify-write instructions (ex. BCF, BSF, etc.) on a port, the value of the port pins The actual write to an I/O port happens at the end of an is read, the desired operation is done to this value, and instruction cycle, whereas for reading, the data must be this value is then written to the port latch. valid at the beginning of the instruction cycle (Figure5-10). Therefore, care must be exercised if a Example5-4 shows the effect of two sequential write followed by a read operation is carried out on the read-modify-write instructions on an I/O port. same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load depen- dent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-10: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note: PC PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB Insfterutcchtieodn MOVWF PORTB MOVF PORTB,W followed by a read from PORTB. wPOritRe TtoB NOP NOP Note that: RB7:RB0 data setup time = (0.25TCY - TPD) where TCY = instruction cycle Port pin sampled here TPD = propagation delay Instruction TPD Therefore, at higher clock frequencies, executed NOP a write followed by a read may be prob- MOVwWritFe PtoORTB MOVF PORTB,W lematic. PORTB DS30234E-page 60  1997-2013 Microchip Technology Inc.

PIC16C6X 5.7 Parallel Slave Port FIGURE 5-11: PORTD AND PORTE AS A PARALLEL SLAVE PORT Applicable Devices 616262AR6263R636464AR646565AR656667 PORTD operates as an 8-bit wide parallel slave port Data bus (microprocessor port) when control bit PSPMODE D Q (TRISE<4>) is set. In slave mode it is asynchronously WR RDx PORT readable and writable by the external world through CK pin RD control input (RE0/RD) and WR control input pin TTL (RE1/WR). Q D It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the RD ENEN PORTD latch as an 8-bit latch. Setting PSPMODE PORT enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip One bit of PORTD select) input. For this functionality, the corresponding Set interrupt flag data direction bits of the TRISE register (TRISE<2:0>) PSPIF (PIR1<7>) must be configured as inputs (set). There are actually two 8-bit latches, one for data-out (from the PIC16/17) and one for data input. The user writes 8-bit data to PORTD data latch and reads data Read from the port pin latch (note that they have the same TTL RD address). In this mode, the TRISD register is ignored Chip Select since the microprocessor is controlling the direction of TTL CS data flow. Write A write to the PSP occurs when both the CS and WR TTL WR lines are first detected low. When either the CS or WR lines become high (level triggered), then the Input Buf- Note: I/O pin has protection diodes to VDD and VSS. fer Full status flag bit IBF (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure5-12). The interrupt flag bit PSPIF (PIR1<7>) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The input Buffer Overflow status flag bit IBOV (TRISE<5>) is set if a second write to the Parallel Slave Port is attempted when the previous byte has not been read out of the buffer. A read from the PSP occurs when both the CS and RD lines are first detected low. The Output Buffer Full sta- tus flag bit OBF (TRISE<6>) is cleared immediately (Figure5-13) indicating that the PORTD latch is waiting to be read by the external bus. When either the CS or RD pin becomes high (level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware. When not in Parallel Slave Port mode, the IBF and OBF bits are held clear. However, if flag bit IBOV was previ- ously set, it must be cleared in firmware. An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in firmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).  1997-2013 Microchip Technology Inc. DS30234E-page 61

PIC16C6X FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0 xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 0Ch PIR1 PSPIF (1) RCIF(2) TXIF(2) SSPIF CCP1IF TMR2IF TRM1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE (1) RCIE(2) TXIE(2) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP. Note 1: These bits are reserved, always maintain these bits clear. 2: These bits are implemented on the PIC16C65/65A/R65/67 only. DS30234E-page 62  1997-2013 Microchip Technology Inc.

PIC16C6X 6.0 OVERVIEW OF TIMER 6.3 Timer2 Overview MODULES Applicable Devices 616262AR6263R636464AR646565AR656667 Applicable Devices 616262AR6263R636464AR646565AR656667 Timer2 is an 8-bit timer with a programmable prescaler and a programmable postscaler, as well as an 8-bit All PIC16C6X devices have three timer modules except Period Register (PR2). Timer2 can be used with the for the PIC16C61, which has one timer module. Each CCP module (in PWM mode) as well as the Baud Rate module can generate an interrupt to indicate that an Generator for the Synchronous Serial Port (SSP). The event has occurred (i.e., timer overflow). Each of these prescaler option allows Timer2 to increment at the fol- modules are detailed in the following sections. The lowing rates: 1:1, 1:4, and 1:16. timer modules are: The postscaler allows TMR2 register to match the (cid:129) Timer0 module (Section7.0) period register (PR2) a programmable number of times (cid:129) Timer1 module (Section8.0) before generating an interrupt. The postscaler can be (cid:129) Timer2 module (Section9.0) programmed from 1:1 to 1:16 (inclusive). 6.1 Timer0 Overview 6.4 CCP Overview Applicable Devices Applicable Devices 616262AR6263R636464AR646565AR656667 616262AR6263R636464AR646565AR656667 The Timer0 module is a simple 8-bit overflow counter. The CCP module(s) can operate in one of three modes: The clock source can be either the internal system 16-bit capture, 16-bit compare, or up to 10-bit Pulse clock (Fosc/4) or an external clock. When the clock Width Modulation (PWM). source is an external clock, the Timer0 module can be Capture mode captures the 16-bit value of TMR1 into selected to increment on either the rising or falling the CCPRxH:CCPRxL register pair. The capture event edge. can be programmed for either the falling edge, rising The Timer0 module also has a programmable pres- edge, fourth rising edge, or sixteenth rising edge of the caler option. This prescaler can be assigned to either CCPx pin. the Timer0 module or the Watchdog Timer. Bit PSA Compare mode compares the TMR1H:TMR1L register (OPTION<3>) assigns the prescaler, and bits PS2:PS0 pair to the CCPRxH:CCPRxL register pair. When a (OPTION<2:0>) determine the prescaler value. TMR0 match occurs, an interrupt can be generated and the can increment at the following rates: 1:1 when the pres- output pin CCPx can be forced to a given state (High or caler is assigned to Watchdog Timer, 1:2, 1:4, 1:8, Low) and Timer1 can be reset. This depends on control 1:16, 1:32, 1:64, 1:128, and 1:256. bits CCPxM3:CCPxM0. Synchronization of the external clock occurs after the PWM mode compares the TMR2 register to a 10-bit prescaler. When the prescaler is used, the external duty cycle register (CCPRxH:CCPRxL<5:4>) as well as clock frequency may be higher then the device’s fre- to an 8-bit period register (PR2). When the TMR2 reg- quency. The maximum frequency is 50 MHz, given the ister = Duty Cycle register, the CCPx pin will be forced high and low time requirements of the clock. low. When TMR2 = PR2, TMR2 is cleared to 00h, an 6.2 Timer1 Overview interrupt can be generated, and the CCPx pin (if an out- put) will be forced high. Applicable Devices 616262AR6263R636464AR646565AR656667 Timer1 is a 16-bit timer/counter. The clock source can be either the internal system clock (Fosc/4), an external clock, or an external crystal. Timer1 can operate as either a timer or a counter. When operating as a coun- ter (external clock source), the counter can either oper- ate synchronized to the device or asynchronously to the device. Asynchronous operation allows Timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power sav- ings of SLEEP mode. TImer1 also has a prescaler option which allows TMR1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. TMR1 can be used in conjunction with the Capture/ Compare/PWM module. When used with a CCP mod- ule, Timer1 is the time-base for 16-bit capture or 16-bit compare and must be synchronized to the device.  1997-2013 Microchip Technology Inc. DS30234E-page 63

PIC16C6X NOTES: DS30234E-page 64  1997-2013 Microchip Technology Inc.

PIC16C6X 7.0 TIMER0 MODULE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are dis- Applicable Devices cussed in detail in Section7.2. 616262AR6263R636464AR646565AR656667 The Timer0 module has the following features: The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The pres- (cid:129) 8-bit timer/counter register, TMR0 caler assignment is controlled in software by control bit - Read and write capability PSA (OPTION<3>). Clearing bit PSA will assign the - Interrupt on overflow from FFh to 00h prescaler to the Timer0 module. The prescaler is not (cid:129) 8-bit software programmable prescaler readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., (cid:129) Internal or external clock select 1:256 are selectable. Section7.3 details the operation - Edge select for external clock of the prescaler. Figure7-1 is a simplified block diagram of the Timer0 module. 7.1 TMR0 Interrupt Timer mode is selected by clearing bit T0CS Applicable Devices (OPTION<5>). In timer mode, the Timer0 module will 616262AR6263R636464AR646565AR656667 increment every instruction cycle (without prescaler). If The TMR0 interrupt is generated when the register TMR0 register is written, the increment is inhibited for (TMR0) overflows from FFh to 00h. This overflow sets the following two instruction cycles (Figure7-2 and interrupt flag bit T0IF (INTCON<2>). The interrupt can Figure7-3). The user can work around this by writing be masked by clearing enable bit T0IE (INTCON<5>). an adjusted value to the TMR0 register. Flag bit T0IF must be cleared in software by the TImer0 Counter mode is selected by setting bit T0CS. In this interrupt service routine before re-enabling this inter- mode, Timer0 will increment either on every rising or rupt. The TMR0 interrupt cannot wake the processor falling edge of pin RA4/T0CKI. The incrementing edge from SLEEP since the timer is shut off during SLEEP. is determined by the source edge select bit T0SE Figure7-4 displays the Timer0 interrupt timing. FIGURE 7-1: TIMER0 BLOCK DIAGRAM Data bus RA4/T0CKI FOSC/4 0 pin PSout 8 1 Sync with 1 Internal TMR0 reg clocks Programmable 0 PSout Prescaler T0SE (2 cycle delay) 3 Set bit T0IF PS2, PS1, PS0 PSA on overflow T0CS Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0). 2: The prescaler is shared with Watchdog Timer (refer to Figure7-6 for detailed diagram). FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch TMR0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2  1997-2013 Microchip Technology Inc. DS30234E-page 65

PIC16C6X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch TMR0 T0 T0+1 NT0 NT0+1 T0 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 FIGURE 7-4: TMR0 INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) Timer0 FEh FFh 00h 01h 02h 1 1 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC +1 PC +1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h) Ienxsetcruuctetidon Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h) Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. DS30234E-page 66  1997-2013 Microchip Technology Inc.

PIC16C6X 7.2 Using Timer0 with External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- Applicable Devices caler so that the prescaler output is symmetrical. For 616262AR6263R636464AR646565AR656667 the external clock to meet the sampling requirement, When an external clock input is used for Timer0, it must the ripple-counter must be taken into account. There- meet certain requirements. The requirements ensure fore, it is necessary for T0CKI to have a period of at the external clock can be synchronized with the internal least 4Tosc (and a small RC delay of 40 ns) divided by phase clock (TOSC). Also, there is a delay in the actual the prescaler value. The only requirement on T0CKI incrementing of Timer0 after synchronization. high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. Refer to param- 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION eters 40, 41 and 42 in the electrical specification of the When no prescaler is used, the external clock input is desired device. the same as the prescaler output. The synchronization 7.2.2 TIMER0 INCREMENT DELAY of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Since the prescaler output is synchronized with the Q4 cycles of the internal phase clocks (Figure7-5). internal clocks, there is a small delay from the time the Therefore, it is necessary for T0CKI to be high for at external clock edge occurs to the time the Timer0 mod- least 2Tosc (and a small RC delay of 20 ns) and low for ule is actually incremented. Figure7-5 shows the delay at least 2Tosc (and a small RC delay of 20 ns). Refer to from the external clock edge to the timer incrementing. the electrical specification of the desired device. FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse EPxretesrcnaalel rC olouctpk uInt (p2u)t or misses sampling (1) (3) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.  1997-2013 Microchip Technology Inc. DS30234E-page 67

PIC16C6X 7.3 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. Applicable Devices 616262AR6263R636464AR646565AR656667 When assigned to the Timer0 module, all instructions An 8-bit counter is available as a prescaler for the writing to the TMR0 register (e.g. CLRF TMR0, Timer0 module or as a postscaler for the Watchdog MOVWF TMR0, BSF TMR0,bitx) will clear the pres- Timer (WDT), respectively (Figure7-6). For simplicity, caler count. When assigned to the Watchdog Timer, a this counter is being referred to as “prescaler” through- CLRWDT instruction will clear the Watchdog Timer and out this data sheet. Note that the prescaler may be the prescaler count. The prescaler is not readable or used by either the Timer0 module or the Watchdog writable. Timer, but not both. Thus, a prescaler assignment for Note: Writing to TMR0 when the prescaler is the Timer0 module means that there is no prescaler for assigned to Timer0 will clear the prescaler the Watchdog Timer, and vice-versa. count, but will not change the prescaler assignment. FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (=Fosc/4) Data Bus 8 0 M 1 RA4p/Tin0CKI 1 UX 0 MU SY2NC TMR0 reg X Cycles T0SE T0CS PSA Set flag bit T0IF on Overflow 0 M 8-bit Prescaler U Watchdog 1 X 8 Timer 8 - to - 1MUX PS2:PS0 PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>). DS30234E-page 68  1997-2013 Microchip Technology Inc.

PIC16C6X 7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol, i.e., it can be changed “on the fly” during program execution. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This precaution must be followed even if the WDT is disabled. EXAMPLE 7-1: CHANGING PRESCALER (TIMER0WDT) 1) BSF STATUS, RP0 ;Bank 1 Lines 2 and 3 do NOT have to 2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of be included if the final desired 3) MOVWF OPTION_REG ;other than 1:1 prescale value is other than 1:1. 4) BCF STATUS, RP0 ;Bank 0 If 1:1 is final desired value, then 5) CLRF TMR0 ;Clear TMR0 and prescaler a temporary prescale value is set in lines 2 and 3 and the final 6) BSF STATUS, RP1 ;Bank 1 prescale value will be set in lines 7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value 10 and 11. 8) MOVWF OPTION_REG ; 9) CLRWDT ;Clears WDT and prescaler 10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT 11) MOVWF OPTION_REG ; 12) BCF STATUS, RP0 ;Bank 0 To change prescaler from the WDT to the Timer0 mod- ule, use the sequence shown in Example7-2. EXAMPLE 7-2: CHANGING PRESCALER (WDTTIMER0) CLRWDT ;Clear WDT and prescaler BSF STATUS, RP0 ;Bank 1 MOVLW b'xxxx0xxx' ;Select TMR0, new prescale value and clock source MOVWF OPTION_REG ; BCF STATUS, RP0 ;Bank 0 TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0 Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 01h, 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE PEIE(1) T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — PORTA Data Direction Register(1) --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. Note 1: TRISA<5> and bit PEIE are not implemented on the PIC16C61, read as '0'.  1997-2013 Microchip Technology Inc. DS30234E-page 69

PIC16C6X NOTES: DS30234E-page 70  1997-2013 Microchip Technology Inc.

PIC16C6X 8.0 TIMER1 MODULE Timer1 also has an internal “reset input”. This reset can be generated by CCP1 or CCP2 (Capture/Compare/ Applicable Devices PWM) module. See Section10.0 for details. Figure8-1 616262AR6263R636464AR646565AR656667 shows the Timer1 control register. Timer1 is a 16-bit timer/counter consisting of two 8-bit For the PIC16C62A/R62/63/R63/64A/R64/65A/R65/ registers (TMR1H and TMR1L) which are readable and R66/67, when the Timer1 oscillator is enabled writable. Register TMR1 (TMR1H:TMR1L) increments (T1OSCEN is set), the RC1 and RC0 pins become from 0000h to FFFFh and rolls over to 0000h. The inputs. That is, the TRISC<1:0> value is ignored. TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). For the PIC16C62/64/65, when the Timer1 oscillator is This interrupt can be enabled/disabled by setting/clear- enabled (T1OSCEN is set), RC1 pin becomes an input, ing the TMR1 interrupt enable bit TMR1IE (PIE1<0>). however the RC0 pin will have to be configured as an input by setting the TRISC<0> bit. Timer1 can operate in one of two modes: The Timer1 module also has a software programmable (cid:129) As a timer prescaler. (cid:129) As a counter The operating mode is determined by clock select bit, TMR1CS (T1CON<1>) (Figure8-2). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). FIGURE 8-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1T1CKPS0T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1OSI (on the rising edge) (See pinouts for pin with T1OSI function) 0 = Internal clock (Fosc/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1  1997-2013 Microchip Technology Inc. DS30234E-page 71

PIC16C6X 8.1 Timer1 Operation in Timer Mode 8.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE Applicable Devices 616262AR6263R636464AR646565AR656667 When an external clock input is used for Timer1 in syn- Timer mode is selected by clearing bit TMR1CS chronized counter mode, it must meet certain require- (T1CON<1>). In this mode, the input clock to the timer ments. The external clock requirement is due to is Fosc/4. The synchronize control bit T1SYNC internal phase clock (Tosc) synchronization. Also, there (T1CON<2>) has no effect since the internal clock is is a delay in the actual incrementing of TMR1 after syn- always in sync. chronization. When the prescaler is 1:1, the external clock input is 8.2 Timer1 Operation in Synchronized the same as the prescaler output. The synchronization Counter Mode of T1CKI with the internal phase clocks is accom- Applicable Devices plished by sampling the prescaler output on the Q2 and 616262AR6263R636464AR646565AR656667 Q4 cycles of the internal phase clocks. Therefore, it is necessary for T1CKI to be high for at least 2Tosc (and Counter mode is selected by setting bit TMR1CS. In a small RC delay of 20 ns) and low for at least 2Tosc this mode the timer increments on every rising edge of (and a small RC delay of 20 ns). Refer to appropriate clock input on T1OSI when enable bit T1OSCEN is set electrical specification section, parameters 45, 46, and or pin with T1CKI when bit T1OSCEN is cleared. 47. Note: The T1OSI function is multiplexed to differ- When a prescaler other than 1:1 is used, the external ent pins, depending on the device. See the clock input is divided by the asynchronous ripple-coun- pinout descriptions to see which pin has ter type prescaler so that the prescaler output is sym- the T1OSI function. metrical. In order for the external clock to meet the If T1SYNC is cleared, then the external clock input is sampling requirement, the ripple counter must be taken synchronized with internal phase clocks. The synchro- into account. Therefore, it is necessary for T1CKI to nization is done after the prescaler stage. The pres- have a period of at least 4Tosc (and a small RC delay caler stage is an asynchronous ripple counter. of 40 ns) divided by the prescaler value. The only In this configuration, during SLEEP mode, Timer1 will requirement on T1CKI high and low time is that they do not increment even if an external clock is present, since not violate the minimum pulse width requirements of the synchronization circuit is shut off. The prescaler, 10ns). Refer to applicable electrical specification sec- however, will continue to increment. tion, parameters 40, 42, 45, 46, and 47. FIGURE 8-2: TIMER1 BLOCK DIAGRAM TMR1IF Overflow Synchronized Interrupt TMR1 0 clock input flag bit TMR1H TMR1L 1 TMR1ON on/off T1SYNC T1OSC (3) T1OSO(2) 1 Synchronize Prescaler T1OSCEN Fosc/4 1, 2, 4, 8 det Enable Internal 0 T1OSI(2) Oscillator(1) Clock 2 TMR1CS SLEEP input T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2: See pinouts for pins with T1OSO and T1OSI functions. 3: For the PIC16C62/64/65, the Schmitt Trigger is not implemented in external clock mode. DS30234E-page 72  1997-2013 Microchip Technology Inc.

PIC16C6X 8.3 Timer1 Operation in Asynchronous EXAMPLE 8-1: READING A 16-BIT Counter Mode FREE-RUNNING TIMER Applicable Devices ; All Interrupts are disabled 616262AR6263R636464AR646565AR656667 MOVF TMR1H, W ;Read high byte MOVWF TMPH ; If control bit T1SYNC (T1CON<2>) is set, the external MOVF TMR1L, W ;Read low byte clock input is not synchronized. The timer continues to MOVWF TMPL ; increment asynchronous to the internal phase clocks. MOVF TMR1H, W ;Read high byte The timer will continue to run during SLEEP and gener- SUBWF TMPH, W ;Sub 1st read ate an interrupt on overflow which will wake the proces- ;with 2nd read sor. However, special precautions in software are BTFSC STATUS,Z ;is result = 0 needed to read-from or write-to the Timer1 register GOTO CONTINUE ;Good 16-bit read pair, TMR1L and TMR1H (Section8.3.2). ; TMR1L may have rolled over between the read ; of the high and low bytes. Reading the high In asynchronous counter mode, Timer1 cannot be used ; and low bytes now will read a good value. as a time-base for capture or compare operations. MOVF TMR1H, W ;Read high byte MOVWF TMPH ; 8.3.1 EXTERNAL CLOCK INPUT TIMING WITH MOVF TMR1L, W ;Read low byte UNSYNCHRONIZED CLOCK MOVWF TMPL ; If control bit T1SYNC is set, the timer will increment ; Re-enable Interrupt (if required) completely asynchronously. The input clock must meet CONTINUE ;Continue with : ;your code certain minimum high time and low time requirements, as specified in timing parameters (45 - 47). 8.4 Timer1 Oscillator 8.3.2 READING AND WRITING TMR1 IN Applicable Devices ASYNCHRONOUS COUNTER MODE 616262AR6263R636464AR646565AR656667 Reading TMR1H or TMR1L, while the timer is running A crystal oscillator circuit is built in-between pins T1OSI from an external asynchronous clock, will ensure a (input) and T1OSO (amplifier output). It is enabled by valid read (taken care of in hardware). However, the setting control bit T1OSCEN (T1CON<3>). The oscilla- user should keep in mind that reading the 16-bit timer tor is a low power oscillator rated up to 200 kHz. It will in two 8-bit values itself poses certain problems since continue to run during SLEEP. It is primarily intended the timer may overflow between the reads. for a 32 kHz crystal. Table8-1 shows the capacitor selection for the Timer1 oscillator. For writes, it is recommended that the user simply stop the timer and write the desired values. A write conten- The Timer1 oscillator is identical to the LP oscillator. tion may occur by writing to the timer registers while the The user must allow a software time delay to ensure register is incrementing. This may produce an unpre- proper oscillator start-up. dictable value in the timer register. TABLE 8-1: CAPACITOR SELECTION FOR Reading the 16-bit value requires some care. THE TIMER1 OSCILLATOR Example8-1 is an example routine to read the 16-bit timer value. This is useful if the timer cannot be Osc Type Freq C1 C2 stopped. LP 32 kHz 33 pF 33 pF 100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A  20 PPM 100 kHz Epson C-2 100.00 KC-P  20 PPM 200 kHz STD XTL 200.000 kHz  20 PPM Note1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components.  1997-2013 Microchip Technology Inc. DS30234E-page 73

PIC16C6X 8.5 Resetting Timer1 using a CCP Trigger 8.6 Resetting of TMR1 Register Pair Output (TMR1H:TMR1L) Applicable Devices Applicable Devices 616262AR6263R636464AR646565AR656667 616262AR6263R636464AR646565AR656667 CCP2 is implemented on the PIC16C63/R63/65/65A/ The TMR1H and TMR1L registers are not reset to 00h R65/66/67 only. on a POR or any other reset except by the CCP1 or CCP2 special event trigger. If CCP1 or CCP2 module is configured in Compare mode to generate a “special event trigger” The T1CON register is reset to 00h on a Power-on (CCPxM3:CCPxM0 = 1011), this signal will reset Reset or a Brown-out Reset, which shuts off the timer Timer1. and leaves a 1:1 prescaler. In all other resets, the reg- ister is unaffected. Note: The “special event trigger” from the CCP1and CCP2 modules will not set inter- 8.7 Timer1 Prescaler rupt flag bit TMR1IF(PIR1<0>). Applicable Devices Timer1 must be configured for either timer or synchro- 616262AR6263R636464AR646565AR656667 nized counter mode to take advantage of this feature. The prescaler counter is cleared on writes to the If the Timer1 is running in asynchronous counter mode, TMR1H or TMR1L registers. this reset operation may not work. In the event that a write to Timer1 coincides with a spe- cial event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL regis- ters pair effectively becomes the period register for the Timer1 module. TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(2) (3) RCIF(1) TXIF(1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(2) (3) RCIE(1) TXIE(1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: The USART is implemented on the PIC16C63/R63/65/65A/R65/66/67 only. 2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear. 3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. DS30234E-page 74  1997-2013 Microchip Technology Inc.

PIC16C6X 9.0 TIMER2 MODULE 9.1 Timer2 Prescaler and Postscaler Applicable Devices Applicable Devices 616262AR6263R636464AR646565AR656667 616262AR6263R636464AR646565AR656667 Timer2 is an 8-bit timer with a prescaler and a post- The prescaler and postscaler counters are cleared scaler. It is especially suitable as PWM time-base for when any of the following occurs: PWM mode of CCP module(s). TMR2 is a readable and (cid:129) a write to the TMR2 register writable register, and is cleared on any device reset. (cid:129) a write to the T2CON register The input clock (FOSC/4) has a prescale option of 1:1, (cid:129) any device reset (POR, BOR, MCLR Reset, or 1:4 or 1:16, selected by control bits WDT Reset). T2CKPS1:T2CKPS0 (T2CON<1:0>). TMR2 is not cleared when T2CON is written. The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and 9.2 Output of TMR2 then resets to 00h on the next increment cycle. PR2 is Applicable Devices a readable and writable register. The PR2 register is ini- 616262AR6263R636464AR646565AR656667 tialized to FFh upon reset. The output of TMR2 (before the postscaler) is fed to the The match output of the TMR2 register goes through a Synchronous Serial Port module which optionally uses 4-bit postscaler (which gives a 1:1 to 1:16 scaling, it to generate shift clock. inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF (PIR1<1>)). FIGURE 9-1: TIMER2 BLOCK DIAGRAM The Timer2 module can be shut off by clearing control Sets bit TMR2ON (T2CON<2>) to minimize power con- iTnMteRrr2upt ToMutRpu2t(1) sumption. flag bit, TMR2IF Figure9-2 shows the Timer2 control register. T2CON is Reset TMR2 reg Prescaler Fosc/4 1:1, 1:4, 1:16 cleared upon reset which initializes Timer2 as shut off with the prescaler and postscaler at a 1:1 value. Postscaler Comparator 2 1:1 to1:16 EQ 4 PR2 reg Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. FIGURE 9-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3TOUTPS2TOUTPS1TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 postscale 0001 = 1:2 postscale   1111 = 1:16 postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = 1:1 prescale 01 = 1:4 prescale 1x = 1:16 prescale  1997-2013 Microchip Technology Inc. DS30234E-page 75

PIC16C6X TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(2) (3) RCIF(1) TXIF(1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(2) (3) RCIE(1) TXIE(1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer2. Note 1: The USART is implemented on the PIC16C63/R63/65/65A/R65/66/67 only. 2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear. 3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. DS30234E-page 76  1997-2013 Microchip Technology Inc.

PIC16C6X 10.0 CAPTURE/COMPARE/PWM CCP2 module: (CCP) MODULE(s) Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and Applicable Devices CCPR2H (high byte). The CCP2CON register controls 6162 62A R62 63R63 64 64A R6465 65A R65 6667CCP1 the operation of CCP2. All are readable and writable. 6162 62A R62 63R63 64 64A R6465 65A R65 6667CCP2 Each CCP (Capture/Compare/PWM) module contains For use of the CCP modules, refer to the Embedded a 16-bit register which can operate as a 16-bit capture Control Handbook, “Using the CCP Modules” (AN594). register, as a 16-bit compare register, or as a PWM TABLE 10-1: CCP MODE - TIMER master/slave duty cycle register. Both the CCP1 and RESOURCE CCP2 modules are identical in operation, with the exception of the operation of the special event trigger. CCP Mode Timer Resource Table10-1 and Table10-2 show the resources and interactions of the CCP modules(s). In the following Capture Timer1 sections, the operation of a CCP module is described Compare Timer1 with respect to CCP1. CCP2 operates the same as PWM Timer2 CCP1, except where noted. CCP1 module: Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 10-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time-base. Capture Compare The compare should be configured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None  1997-2013 Microchip Technology Inc. DS30234E-page 77

PIC16C6X FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Significant bits Capture Mode Unused Compare Mode Unused PWM Mode These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (bit CCPxIF is set) 1001 = Compare mode, clear output on match (bit CCPxIF is set) 1010 = Compare mode, generate software interrupt on match (bit CCPxIF is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1) 11xx = PWM mode 10.1 Capture Mode FIGURE 10-2: CAPTURE MODE OPERATION BLOCK DIAGRAM Applicable Devices 616262AR6263R636464AR646565AR656667 Set CCP1IF In Capture mode, CCPR1H:CCPR1L captures the Prescaler PIR1<2> 16-bit value of the TMR1 register when an event occurs  1, 4, 16 on pin RC2/CCP1 (Figure10-2). An event is defined RC2/CCP1 CCPR1H CCPR1L pin as: (cid:129) Every falling edge edgaen ddetect CEnaapbtulere (cid:129) Every rising edge TMR1H TMR1L (cid:129) Every 4th rising edge CCP1CON<3:0> (cid:129) Every 16th rising edge Q’s An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the inter- 10.1.2 TIMER1 MODE SELECTION rupt request flag bit CCP1IF (PIR1<2>) is set. It must Timer1 must be running in Timer mode or Synchro- be cleared in software. If another capture occurs before nized Counter mode for the CCP module to use the the value in register CCPR1 is read, the old captured capture feature. In Asynchronous Counter mode, the value will be lost. capture operation may not work consistently. 10.1.1 CCP PIN CONFIGURATION 10.1.3 SOFTWARE INTERRUPT In Capture mode, the RC2/CCP1 pin should be config- When the Capture event is changed, a false capture ured as an input by setting the TRISC<2> bit. interrupt may be generated. The user should clear Note: If the RC2/CCP1 pin is configured as an enable bit CCP1IE (PIE1<2>) to avoid false interrupts output, a write to PORTC can cause a cap- and should clear flag bit CCP1IF following any such ture condition. change in operating mode. DS30234E-page 78  1997-2013 Microchip Technology Inc.

PIC16C6X 10.1.4 CCP PRESCALER 10.2.1 CCP PIN CONFIGURATION There are four prescaler settings, specified by bits The user must configure the RC2/CCP1 pin as an out- CCP1M3:CCP1M0. Whenever the CCP module is put by clearing the TRISC<2> bit. turned off, or the CCP module is not in Capture mode, Note: Clearing the CCP1CON register will force the prescaler counter is cleared. This means that any the RC2/CCP1 compare output latch to the reset will clear the prescaler counter. default low level. This is not the data latch. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will 10.2.1 TIMER1 MODE SELECTION not be cleared, therefore the first capture may be from Timer1 must be running in Timer mode or Synchro- a non-zero prescaler. Example10-1 shows the recom- nized Counter mode if the CCP module is using the mended method for switching between capture pres- compare feature. In Asynchronous Counter mode, the calers. This example also clears the prescaler counter compare operation may not work. and will not generate the “false” interrupt. 10.2.2 SOFTWARE INTERRUPT MODE EXAMPLE 10-1: CHANGING BETWEEN CAPTURE PRESCALERS When Generate Software Interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is gen- CLRF CCP1CON ; Turn CCP module off erated (if enabled). MOVLW NEW_CAPT_PS; Load the W reg with ; the new prescaler 10.2.3 SPECIAL EVENT TRIGGER ; mode value and CCP ON MOVWF CCP1CON ; Load CCP1CON with In this mode, an internal hardware trigger is generated ; this value which may be used to initiate an action. 10.2 Compare Mode The special event trigger output of CCP1 and CCP2 resets the TMR1 register pair. This allows the Applicable Devices CCPR1H:CCPR1L and CCPR2H:CCPR2L registers to 616262AR6263R636464AR646565AR656667 effectively be 16-bit programmable period register(s) In Compare mode, the 16-bit CCPR1 register value is for Timer1. constantly compared against the TMR1 register pair For compatibility issues, the special event trigger out- value. When a match occurs, the RC2/CCP1 pin is: put of CCP1 (PIC16C72) and CCP2 (all other (cid:129) Driven High PIC16C7X devices) also starts an A/D conversion. (cid:129) Driven Low Note: The “special event trigger” from the (cid:129) Remains Unchanged CCP1and CCP2 modules will not set inter- The action on the pin is based on the value of control rupt flag bit TMR1IF (PIR1<0>). bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time interrupt flag bit CCP1IF is set. FIGURE 10-3: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>). Special Event Trigger Set CCP1IF PIR1<2> CCPR1H CCPR1L Q S Output RC2/CCP1 R Logic match Comparator TRISC<2> TMR1H TMR1L Output Enable CCP1CON<3:0> Mode Select  1997-2013 Microchip Technology Inc. DS30234E-page 79

PIC16C6X 10.3 PWM Mode 10.3.1 PWM PERIOD Applicable Devices The PWM period is specified by writing to the PR2 reg- 616262AR6263R636464AR646565AR656667 ister. The PWM period can be calculated using the fol- In Pulse Width Modulation (PWM) mode, the CCP1 pin lowing formula: produces up to a 10-bit resolution PWM output. Since PWM period = [(PR2) + 1] • 4 (cid:129) TOSC (cid:129) the CCP1 pin is multiplexed with the PORTC data latch, (TMR2 prescale value) the TRISC<2> bit must be cleared to make the CCP1 pin an output. PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events Note: Clearing the CCP1CON register will force occur on the next increment cycle: the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data (cid:129) TMR2 is cleared latch. (cid:129) The PWM duty cycle is latched from CCPR1L into Figure10-4 shows a simplified block diagram of the CCPR1H CCP module in PWM mode. (cid:129) The CCP1 pin is set (exception: if PWM duty cycle=0%, the CCP1 pin will not be set) For a step by step procedure on how to set up the CCP module for PWM operation, see Section10.3.3. Note: The Timer2 postscaler (see Section9.1) is FIGURE 10-4: SIMPLIFIED PWM BLOCK not used in the determination of the PWM DIAGRAM frequency. The postscaler could be used to have a servo update rate at a different fre- Duty cycle registers CCP1CON<5:4> quency than the PWM output. CCPR1L 10.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up CCPR1H (Slave) to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the Comparator R Q two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is RC2/CCP1 used to calculate the PWM duty cycle in time: TMR2 (Note 1) S PWM duty cycle = (CCPR1L:CCP1CON<5:4>) (cid:129) Tosc (cid:129) (TMR2 prescale value) Comparator TRISC2 CCPR1L and CCP1CON<5:4> can be written to at any Clear Timer, CCP1 pin and time, but the duty cycle value is not latched into PR2 latch D.C. CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, Note 1: 8-bit timer is concatenated with 2-bit internal Q clock CCPR1H is a read-only register. or 2 bits of the prescaler to create 10-bit time-base. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double A PWM output (Figure10-5) has a time base (period) buffering is essential for glitchless PWM operation. and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period When the CCPR1H and 2-bit latch match TMR2 con- (1/period). catenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. FIGURE 10-5: PWM OUTPUT Maximum PWM resolution (bits) for a given PWM frequency: Period ( FOSC ) log FPWM = bits log(2) Duty Cycle TMR2 = PR2 Note: If the PWM duty cycle value is longer than TMR2 = Duty Cycle the PWM period the CCP1 pin will not be forced to the low level. TMR2 = PR2 DS30234E-page 80  1997-2013 Microchip Technology Inc.

PIC16C6X EXAMPLE 10-2: PWM PERIOD AND DUTY In order to achieve higher resolution, the PWM fre- CYCLE CALCULATION quency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased. Desired PWM frequency is 78.125 kHz, Fosc = 20 MHz Table10-3 lists example PWM frequencies and resolu- TMR2 prescale = 1 tions for Fosc = 20 MHz. The TMR2 prescaler and PR2 values are also shown. 1/78.125 kHz = [(PR2) + 1] (cid:129) 4 (cid:129) 1/20 MHz (cid:129) 1 12.8 s = [(PR2) + 1] (cid:129) 4 (cid:129) 50 ns (cid:129) 1 10.3.3 SET-UP FOR PWM OPERATION PR2 = 63 The following steps should be taken when configuring Find the maximum resolution of the duty cycle that can the CCP module for PWM operation: be used with a 78.125 kHz frequency and 20 MHz 1. Set the PWM period by writing to the PR2 regis- oscillator: ter. 1/78.125 kHz = 2PWM RESOLUTION (cid:129) 1/20 MHz (cid:129) 1 2. Set the PWM duty cycle by writing to the 12.8 s = 2PWM RESOLUTION (cid:129) 50 ns (cid:129) 1 CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the 256 = 2PWM RESOLUTION TRISC<2> bit. log(256) = (PWM Resolution) (cid:129) log(2) 4. Set the TMR2 prescale value and enable Timer2 8.0 = PWM Resolution by writing to T2CON. At most, an 8-bit resolution duty cycle can be obtained 5. Configure the CCP1 module for PWM operation. from a 78.125 kHz frequency and a 20 MHz oscillator, i.e., 0  CCPR1L:CCP1CON<5:4>  255. Any value greater than 255 will result in a 100% duty cycle. TABLE 10-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5 TABLE 10-4: REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE Value on: Value on Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(2) (3) RCIF(1) TXIF(1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh(4) PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(2) (3) RCIE(1) TXIE(1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh(4) PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1T1CKPS0T1OSCEN T1SYNC TMR1CSTMR1ON--00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh(4) CCPR2L Capture/Compare/PWM2 (LSB) xxxx xxxx uuuu uuuu 1Ch(4) CCPR2H Capture/Compare/PWM2 (MSB) xxxx xxxx uuuu uuuu 1Dh(4) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2CCP2M1 CCP2M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in these modes. Note 1: These bits are associated with the USART module, which is implemented on the PIC16C63/R63/65/65A/R65/66/67 only. 2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear. 3: The PIR1<6> and PIE1<6> bits are reserved, always maintain these bits clear. 4: These registers are associated with the CCP2 module, which is only implemented on the PIC16C63/R63/65/65A/R65/66/67.  1997-2013 Microchip Technology Inc. DS30234E-page 81

PIC16C6X TABLE 10-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on: Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 0000 10Bh,18Bh 000x 000u 0Ch PIR1 PSPIF(2) (3) RCIF(1) TXIF(1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh(4) PIR2 — — — — — — — CCP2IF ---- --- ---- --- 0 0 8Ch PIE1 PSPIE(2) (3) RCIE(1) TXIE(1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh(4) PIE2 — — — — — — — CCP2IE ---- --- ---- --- 0 0 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 92h PR2 Timer2 module’s Period register 1111 1111 1111 1111 12h T2CON — TOUTPS3TOUTPS2TOUTPS1TOUTPS0TMR2ONT2CKPS1T2CKPS0 -000 -000 0000 0000 15h CCPR1L Capture/Compare/PWM1 (LSB) xxxx uuuu xxxx uuuu 16h CCPR1H Capture/Compare/PWM1 (MSB) xxxx uuuu xxxx uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 --00 0000 0000 1Bh(4) CCPR2L Capture/Compare/PWM2 (LSB) xxxx uuuu xxxx uuuu 1Ch(4) CCPR2H Capture/Compare/PWM2 (MSB) xxxx uuuu xxxx uuuu 1Dh(4) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 --00 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in this mode. Note 1: These bits are associated with the USART module, which is implemented on the PIC16C63/R63/65/65A/R65/66/67 only. 2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear. 3: The PIR1<6> and PIE1<6> bits are reserved, always maintain these bits clear. 4: These registers are associated with the CCP2 module, which is only implemented on the PIC16C63/R63/65/65A/R65/66/67. DS30234E-page 82  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 11.1 SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The SSP module can operate in one of two modes: (cid:129) Serial Peripheral Interface (SPI) (cid:129) Inter-Integrated Circuit (I2C) The SSP module in I2C mode works the same in all PIC16C6X devices that have an SSP module. However the SSP Module in SPI mode has differences between the PIC16C66/67 and the other PIC16C6X devices. The register definitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C66/67 and the other PIC16C6X devices. The default reset values of both the SPI modules is the same regardless of the device: 11.2 SPI Mode for PIC16C62/62A/R62/63/R63/64/ 64A/R64/65/65A/R65......................................84 11.3 SPI Mode for PIC16C66/67.............................89 11.4 I2C™ Overview................................................95 11.5 SSP I2C Operation..........................................99 Refer to Application Note AN578, “Use of the SSP Module in the I2C Multi-Master Environment.”  1997-2013 Microchip Technology Inc. DS30234E-page 83

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 11.2 SPI Mode for PIC16C62/62A/R62/63/ R63/64/64A/R64/65/65A/R65 This section contains register definitions and opera- tional characteristics of the SPI module for the PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16CR63, PIC16C64, PIC16C64A, PIC16CR64, PIC16C65, PIC16C65A, PIC16CR65. FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — D/A P S R/W UA BF R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS30234E-page 84  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Detect bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the SSP- BUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge. 0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge. In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = Fosc/4 0001 = SPI master mode, clock = Fosc/16 0010 = SPI master mode, clock = Fosc/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled Master Mode (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled  1997-2013 Microchip Technology Inc. DS30234E-page 85

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 11.2.1 OPERATION OF SSP MODULE IN SPI EXAMPLE 11-1: LOADING THE SSPBUF MODE (SSPSR) REGISTER BSF STATUS, RP0 ;Specify Bank 1 Applicable Devices LOOP BTFSS SSPSTAT, BF ;Has data been 616262AR6263R636464AR646565AR656667 ;received The SPI mode allows 8-bits of data to be synchro- ;(transmit nously transmitted and received simultaneously. To ;complete)? accomplish communication, typically three pins are GOTO LOOP ;No used: BCF STATUS, RP0 ;Specify Bank 0 MOVF SSPBUF, W ;W reg = contents (cid:129) Serial Data Out (SDO) ;of SSPBUF (cid:129) Serial Data In (SDI) MOVWF RXDATA ;Save in user RAM (cid:129) Serial Clock (SCK) MOVF TXDATA, W ;W reg = contents Additionally a fourth pin may be used when in a slave ; of TXDATA mode of operation: MOVWF SSPBUF ;New data to xmit (cid:129) Slave Select (SS) The block diagram of the SSP module, when in SPI mode (Figure11-3), shows that the SSPSR register is When initializing the SPI, several options need to be not directly readable or writable, and can only be specified. This is done by programming the appropriate accessed from addressing the SSPBUF register. Addi- control bits in the SSPCON register (SSPCON<5:0>). tionally, the SSP status register (SSPSTAT) indicates These control bits allow the following to be specified: the various status conditions. (cid:129) Master Mode (SCK is the clock output) FIGURE 11-3: SSP BLOCK DIAGRAM (cid:129) Slave Mode (SCK is the clock input) (SPI MODE) (cid:129) Clock Polarity (Output/Input data on the Rising/ Falling edge of SCK) (cid:129) Clock Rate (Master mode only) Internal (cid:129) Slave Select Mode (Slave mode only) data bus The SSP consists of a transmit/receive Shift Register Read Write (SSPSR) and a Buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF reg SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been received, that byte is moved to the SSPBUF register. Then the Buffer Full bit, BF (SSPSTAT<0>) SSPSR reg and flag bit SSPIF are set. This double buffering of the received data (SSPBUF) allows the next byte to start RC4/SDI/SDA bit0 cslohcifkt reception before reading the data that was just received. Any write to the SSPBUF register during RC5/SDO transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON<7>) will be set. User software must clear bit WCOL so that it can SSControl be determined if the following write(s) to the SSPBUF Enable completed successfully. When the application software RA5/SS Edge is expecting to receive valid data, the SSPBUF register Select should be read before the next byte of data to transfer is written to the SSPBUF register. The Buffer Full bit BF 2 (SSPSTAT<0>) indicates when the SSPBUF register Clock Select has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is SSPM3:SSPM0 TMR2 output cleared. This data may be irrelevant if the SPI is only a 4 2 transmitter. Generally the SSP Interrupt is used to determine when the transmission/reception has com- Edge pleted. The SSPBUF register must be read and/or writ- RC3/SCK/ Select P4r, e1s6c,a 6le4r TCY ten. If the interrupt method is not going to be used, then SCL software polling can be done to ensure that a write col- TRISC<3> lision does not occur. Example11-1 shows the loading of the SSPBUF (SSPSR) register for data transmission. The shaded instruction is only required if the received data is meaningful. DS30234E-page 86  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 To enable the serial port, SSP enable bit SSPEN The master can initiate the data transfer at any time (SSPCON<5>) must be set. To reset or reconfigure SPI because it controls the SCK. The master determines mode, clear enable bit SSPEN, re-initialize SSPCON when the slave (Processor 2) is to broadcast data by register, and then set enable bit SSPEN. This config- the software protocol. ures the SDI, SDO, SCK, and SS pins as serial port In master mode the data is transmitted/received as pins. For the pins to behave as the serial port function, soon as the SSPBUF register is written to. If the SPI is they must have their data direction bits (in the TRIS reg- only going to receive, the SCK output could be disabled ister) appropriately programmed. That is: (programmed as an input). The SSPSR register will (cid:129) SDI must have TRISC<4> set continue to shift in the signal present on the SDI pin at (cid:129) SDO must have TRISC<5> cleared the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal (cid:129) SCK (Master mode) must have TRISC<3> received byte (interrupts and status bits appropriately cleared set). This could be useful in receiver applications as a (cid:129) SCK (Slave mode) must have TRISC<3> set “line activity monitor” mode. (cid:129) SS must have TRISA<5> set (if implemented) In slave mode, the data is transmitted and received as Any serial port function that is not desired may be over- the external clock pulses appear on SCK. When the ridden by programming the corresponding data direc- last bit is latched interrupt flag bit SSPIF (PIR1<3>) is tion (TRIS) register to the opposite value. An example set. would be in master mode where you are only sending The clock polarity is selected by appropriately program- data (to a display driver), then both SDI and SS could ming bit CKP (SSPCON<4>). This then would give be used as general purpose outputs by clearing their waveforms for SPI communication as shown in corresponding TRIS register bits. Figure11-5 and Figure11-6 where the MSB is trans- Figure11-4 shows a typical connection between two mitted first. In master mode, the SPI clock rate (bit rate) microcontrollers. The master controller (Processor 1) is user programmable to be one of the following: initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- (cid:129) Fosc/4 (or TCY) grammed clock edge, and latched on the opposite edge (cid:129) Fosc/16 (or 4  TCY) of the clock. Both processors should be programmed to (cid:129) Fosc/64 (or 16  TCY) the same Clock Polarity (CKP), then both controllers (cid:129) Timer2 output/2 would send and receive data at the same time. This allows a maximum bit clock frequency (at 20 MHz) Whether the data is meaningful (or dummy data) of 5 MHz. When in slave mode the external clock must depends on the application software. This leads to meet the minimum high and low times. three scenarios for data transmission: In sleep mode, the slave can transmit and receive data (cid:129) Master sends data—Slave sends dummy data and wake the device from sleep. (cid:129) Master sends data—Slave sends data (cid:129) Master sends dummy data—Slave sends data FIGURE 11-4: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF register) (SSPBUF register) Shift Register SDI SDO Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2  1997-2013 Microchip Technology Inc. DS30234E-page 87

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 The SS pin allows a synchronous slave mode. The point at which it was taken high. External pull-up/ SPI must be in slave mode (SSPCON<3:0> = 04h) pull-down resistors may be desirable, depending on the and the TRISA<5> bit must be set the for synchro- application. nous slave mode to be enabled. When the SS pin is To emulate two-wire communication, the SDO pin can low, transmission and reception are enabled and be connected to the SDI pin. When the SPI needs to the SDO pin is driven. When the SS pin goes high, operate as a receiver the SDO pin can be configured as the SDO pin is no longer driven, even if in the mid- an input. This disables transmissions from the SDO. dle of a transmitted byte, and becomes a floating The SDI can always be left as an input (SDI function) output. If the SS pin is taken low without resetting since it cannot create a bus conflict. SPI mode, the transmission will continue from the FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI bit7 bit0 SSPIF FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI bit7 bit0 SSPIF TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(2) (3) RCIF(1) TXIF(1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(2) (3) RCIE(1) TXIE(1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: These bits are associated with the USART which is implemented on the PIC16C63/R63/65/65A/R65 only. 2: PSPIF and PSPIE are reserved on the PIC16C62/62A/R62/63/R63, always maintain these bits clear. 3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. DS30234E-page 88  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 11.3 SPI Mode for PIC16C66/67 This section contains register definitions and opera- tional characterisitics of the SPI module on the PIC16C66 and PIC16C67 only. FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C66/67) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF R = Readable bit W =Writable bit bit7 bit0 U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SMP: SPI data input sample phase SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode bit 6: CKE: SPI Clock Edge Select (Figure11-11, Figure11-12, and Figure11-13) CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty  1997-2013 Microchip Technology Inc. DS30234E-page 89

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C66/67) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit W =Writable bit bit7 bit0 U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = FOSC/4 0001 = SPI master mode, clock = FOSC/16 0010 = SPI master mode, clock = FOSC/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master mode (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled DS30234E-page 90  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 11.3.1 SSP MODULE IN SPI MODE FOR EXAMPLE 11-2: LOADING THE SSPBUF PIC16C66/67 (SSPSR) REGISTER (PIC16C66/67) The SPI mode allows 8-bits of data to be synchro- nously transmitted and received simultaneously. To BCF STATUS, RP1 ;Specify Bank 1 accomplish communication, typically three pins are BSF STATUS, RP0 ; used: LOOP BTFSS SSPSTAT, BF ;Has data been (cid:129) Serial Data Out (SDO) RC5/SDO ;received ;(transmit (cid:129) Serial Data In (SDI) RC4/SDI/SDA ;complete)? (cid:129) Serial Clock (SCK) RC3/SCK/SCL GOTO LOOP ;No Additionally a fourth pin may be used when in a slave BCF STATUS, RP0 ;Specify Bank 0 MOVF SSPBUF, W ;W reg = contents mode of operation: ; of SSPBUF (cid:129) Slave Select (SS) RA5/SS MOVWF RXDATA ;Save in user RAM When initializing the SPI, several options need to be MOVF TXDATA, W ;W reg = contents specified. This is done by programming the appropriate ; of TXDATA MOVWF SSPBUF ;New data to xmit control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the fol- The block diagram of the SSP module, when in SPI lowing to be specified: mode (Figure11-9), shows that the SSPSR is not (cid:129) Master Mode (SCK is the clock output) directly readable or writable, and can only be accessed (cid:129) Slave Mode (SCK is the clock input) from addressing the SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various (cid:129) Clock Polarity (Idle state of SCK) status conditions. (cid:129) Clock edge (output data on rising/falling edge of SCK) FIGURE 11-9: SSP BLOCK DIAGRAM (cid:129) Clock Rate (Master mode only) (SPIMODE)(PIC16C66/67) (cid:129) Slave Select Mode (Slave mode only) Internal The SSP consists of a transmit/receive Shift Register data bus (SSPSR) and a buffer register (SSPBUF). The SSPSR Read Write shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR SSPBUF reg until the received data is ready. Once the 8-bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit BF (SSPSTAT<0>) and interrupt flag bit SSPIF (PIR1<3>) SSPSR reg are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before RC4/SDI/SDA bit0 cslohcifkt reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data RC5/SDO will be ignored, and the write collision detect bit WCOL (SSPCON<7>) will be set. User software must clear the WCOL bit so that it can be determined if the following SSControl write(s) to the SSPBUF register completed success- Enable fully. When the application software is expecting to RA5/SS Edge receive valid data, the SSPBUF should be read before Select the next byte of data to transfer is written to the SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates 2 when SSPBUF has been loaded with the received data Clock Select (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI SSPM3:SSPM0 TMR2 output is only a transmitter. Generally the SSP Interrupt is 4 2 used to determine when the transmission/reception has completed. The SSPBUF must be read and/or writ- Edge ten. If the interrupt method is not going to be used, then RC3/SCK/ Select P4r,e 1s6c,a 6le4r TCY software polling can be done to ensure that a write col- SCL lision does not occur. Example11-2 shows the loading TRISC<3> of the SSPBUF (SSPSR) for data transmission. The shaded instruction is only required if the received data is meaningful.  1997-2013 Microchip Technology Inc. DS30234E-page 91

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 To enable the serial port, SSP Enable bit, SSPEN The master can initiate the data transfer at any time (SSPCON<5>) must be set. To reset or reconfigure SPI because it controls the SCK. The master determines mode, clear bit SSPEN, re-initialize the SSPCON reg- when the slave (Processor 2) is to broadcast data by ister, and then set bit SSPEN. This configures the SDI, the firmware protocol. SDO, SCK, and SS pins as serial port pins. For the pins In master mode the data is transmitted/received as to behave as the serial port function, they must have soon as the SSPBUF register is written to. If the SPI is their data direction bits (in the TRISC register) appro- only going to receive, the SCK output could be disabled priately programmed. That is: (programmed as an input). The SSPSR register will (cid:129) SDI must have TRISC<4> set continue to shift in the signal present on the SDI pin at (cid:129) SDO must have TRISC<5> cleared the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal (cid:129) SCK (Master mode) must have TRISC<3> received byte (interrupts and status bits appropriately cleared set). This could be useful in receiver applications as a (cid:129) SCK (Slave mode) must have TRISC<3> set “line activity monitor” mode. (cid:129) SS must have TRISA<5> set In slave mode, the data is transmitted and received as Any serial port function that is not desired may be over- the external clock pulses appear on SCK. When the ridden by programming the corresponding data direc- last bit is latched the interrupt flag bit SSPIF (PIR1<3>) tion (TRIS) register to the opposite value. An example is set. would be in master mode where you are only sending The clock polarity is selected by appropriately program- data (to a display driver), then both SDI and SS could ming bit CKP (SSPCON<4>). This then would give be used as general purpose outputs by clearing their waveforms for SPI communication as shown in corresponding TRIS register bits. Figure11-11, Figure11-12, and Figure11-13 where Figure11-10 shows a typical connection between two the MSB is transmitted first. In master mode, the SPI microcontrollers. The master controller (Processor 1) clock rate (bit rate) is user programmable to be one of initiates the data transfer by sending the SCK signal. the following: Data is shifted out of both shift registers on their pro- grammed clock edge, and latched on the opposite edge (cid:129) FOSC/4 (or TCY) of the clock. Both processors should be programmed to (cid:129) FOSC/16 (or 4 (cid:129) TCY) same Clock Polarity (CKP), then both controllers would (cid:129) FOSC/64 (or 16 (cid:129) TCY) send and receive data at the same time. Whether the (cid:129) Timer2 output/2 data is meaningful (or dummy data) depends on the This allows a maximum bit clock frequency (at 20 MHz) application firmware. This leads to three scenarios for of 5 MHz. When in slave mode the external clock must data transmission: meet the minimum high and low times. (cid:129) Master sends data—Slave sends dummy data In sleep mode, the slave can transmit and receive data (cid:129) Master sends data—Slave sends data and wake the device from sleep. (cid:129) Master sends dummy data—Slave sends data FIGURE 11-10:SPI MASTER/SLAVE CONNECTION (PIC16C66/67) SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer Serial Input Buffer (SSPBUF) (SSPBUF) Shift Register SDI SDO Shift Register (SSPSR) (SSPSR) MSb LSb MSb LSb Serial Clock SCK SCK PROCESSOR 1 PROCESSOR 2 DS30234E-page 92  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 The SS pin allows a synchronous slave mode. The Note: When the SPI is in Slave Mode with SS pin SPI must be in slave mode (SSPCON<3:0> = 04h) control enabled, (SSPCON<3:0> = 0100) and the TRISA<5> bit must be set for the synchro- the SPI module will reset if the SS pin is set nous slave mode to be enabled. When the SS pin is to VDD. low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, Note: If the SPI is used in Slave Mode with the SDO pin is no longer driven, even if in the mid- CKE='1', then the SS pin control must be dle of a transmitted byte, and becomes a floating enabled. output. If the SS pin is taken low without resetting To emulate two-wire communication, the SDO pin can SPI mode, the transmission will continue from the be connected to the SDI pin. When the SPI needs to point at which it was taken high. External pull-up/ operate as a receiver the SDO pin can be configured as pull-down resistors may be desirable, depending on the an input. This disables transmissions from the SDO. application. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. FIGURE 11-11:SPI MODE TIMING, MASTER MODE (PIC16C66/67) SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 11-12:SPI MODE TIMING (SLAVE MODE WITH CKE=0) (PIC16C66/67) SS (optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF  1997-2013 Microchip Technology Inc. DS30234E-page 93

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 FIGURE 11-13:SPI MODE TIMING (SLAVE MODE WITH CKE=1) (PIC16C66/67) SS (not optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 11-2: REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C66/67) Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other resets Reset 0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh,18Bh 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction register --11 1111 --11 1111 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: PSPIF and PSPIE are reserved on the PIC16C66, always maintain these bits clear. 2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. DS30234E-page 94  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 11.4 I2C™ Overview In both cases the master generates the clock signal. The output stages of the clock (SCL) and data (SDA) This section provides an overview of the Inter-Inte- grated Circuit (I2C) bus, with Section11.5 discussing lines must have an open-drain or open-collector in the operation of the SSP module in I2C mode. order to perform the wired-AND function of the bus. External pull-up resistors are used to ensure a high The I2C bus is a two-wire serial interface developed by level when no device is pulling the line down. The num- the Philips® Corporation. The original specification, or ber of devices that may be attached to the I2C bus is standard mode, was for data transfers of up to 100 limited only by the maximum bus loading specification Kbps. The enhanced specification (fast mode) is also of 400 pF. supported. This device will communicate with both standard and fast mode devices if attached to the same 11.4.1 INITIATING AND TERMINATING DATA bus. The clock will determine the data rate. TRANSFER The I2C interface employs a comprehensive protocol to During times of no data transfer (idle time), both the ensure reliable transmission and reception of data. clock line (SCL) and the data line (SDA) are pulled high When transmitting data, one device is the “master” through the external pull-up resistors. The START and which initiates transfer on the bus and generates the STOP conditions determine the start and stop of data clock signals to permit that transfer, while the other transmission. The START condition is defined as a high device(s) acts as the “slave.” All portions of the slave to low transition of the SDA when the SCL is high. The protocol are implemented in the SSP module’s hard- STOP condition is defined as a low to high transition of ware, except general call support, while portions of the the SDA when the SCL is high. Figure11-14 shows the master protocol need to be addressed in the START and STOP conditions. The master generates PIC16CXX software. Table11-3 defines some of the these conditions for starting and terminating data trans- I2C bus terminology. For additional information on the fer. Due to the definition of the START and STOP con- I2C interface specification, refer to the Philips docu- ditions, when data is being transmitted, the SDA line ment “The I2C bus and how to use it.” #939839340011, can only change state when the SCL line is low. which can be obtained from the Philips Corporation. In the I2C interface protocol each device has an FIGURE 11-14:START AND STOP address. When a master wishes to initiate a data trans- CONDITIONS fer, it first transmits the address of the device that it wishes to “talk” to. All devices “listen” to see if this is their address. Within this address, a bit specifies if the master wishes to read-from/write-to the slave device. SDA The master and slave are always in opposite modes (transmitter/receiver) of operation during a data trans- SCL S P fer. That is they can be thought of as operating in either of these two relations: Start Change Change Stop Condition of Data of Data Condition (cid:129) Master-transmitter and Slave-receiver Allowed Allowed (cid:129) Slave-transmitter and Master-receiver TABLE 11-3: I2C BUS TERMINOLOGY Term Description Transmitter The device that sends the data to the bus. Receiver The device that receives the data from the bus. Master The device which initiates the transfer, generates the clock and terminates the transfer. Slave The device addressed by a master. Multi-master More than one master device in a system. These masters can attempt to control the bus at the same time without corrupting the message. Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that the transfer data does not get corrupted. Synchronization Procedure where the clock signals of two or more devices are synchronized.  1997-2013 Microchip Technology Inc. DS30234E-page 95

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 11.4.2 ADDRESSING I2C DEVICES FIGURE 11-17:SLAVE-RECEIVER ACKNOWLEDGE There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure11-15). The Data more complex is the 10-bit address with a R/W bit Output by Transmitter (Figure11-16). For 10-bit address format, two bytes must be transmitted with the first five bits specifying this OutpuDta btay not acknowledge to be a 10-bit address. Receiver acknowledge SCL from FIGURE 11-15:7-BIT ADDRESS FORMAT Master 1 2 8 9 S MSb LSb Start Clock Pulse for Condition Acknowledgment S R/W ACK slave address Sent by If the master is receiving the data (master-receiver), it Slave generates an acknowledge signal for each received S Start Condition byte of data, except for the last byte. To signal the end R/W Read/Write pulse of data to the slave-transmitter, the master does not ACK Acknowledge generate an acknowledge (not acknowledge). The slave then releases the SDA line so the master can generate the STOP condition. The master can also FIGURE 11-16:I2C 10-BIT ADDRESS FORMAT generate the STOP condition during the acknowledge pulse for valid termination of data transfer. S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK If the slave needs to delay the transmission of the next sent by slave byte, holding the SCL line low will force the master into = 0 for write a wait state. Data transfer continues when the slave S - Start Condition releases the SCL line. This allows the slave to move the R/W - Read/Write Pulse ACK - Acknowledge received data or fetch the data it needs to transfer before allowing the clock to start. This wait state tech- nique can also be implemented at the bit level, 11.4.3 TRANSFER ACKNOWLEDGE Figure11-18. The slave will inherently stretch the clock, when it is a transmitter, but will not when it is a All data must be transmitted per byte, with no limit to the receiver. The slave will have to clear the SSPCON<4> number of bytes transmitted per data transfer. After bit to enable clock stretching when it is a receiver. each byte, the slave-receiver generates an acknowl- edge bit (ACK) (Figure11-17). When a slave-receiver doesn’t acknowledge the slave address or received data, the master must abort the transfer. The slave must leave SDA high so that the master can generate the STOP condition (Figure11-14). FIGURE 11-18:DATA TRANSFER WAIT STATE SDA MSB acknowledgment acknowledgment signal from receiver byte complete signal from receiver interrupt with receiver clock line held low while interrupts are serviced SCL S 1 2 7 8 9 1 2 3  8 9 P Start Stop Condition Address R/W ACK WStaaitte Data ACK Condition DS30234E-page 96  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 Figure11-19 and Figure11-20 show Master-transmit- SCL is high), but occurs after a data transfer acknowl- ter and Master-receiver data transfer sequences. edge pulse (not the bus-free state). This allows a mas- ter to send “commands” to the slave and then receive When a master does not wish to relinquish the bus (by the requested information or to address a different generating a STOP condition), a repeated START con- slave device. This sequence is shown in Figure11-21. dition (Sr) must be generated. This condition is identi- cal to the start condition (SDA goes high-to-low while FIGURE 11-19:MASTER-TRANSMITTER SEQUENCE For 7-bit address: For 10-bit address: SSlave AddressR/WA Data A Data A/A P SSlave AddressR/WA1Slave AddressA2 First 7 bits Second byte '0' (write) data transferred (n bytes - acknowledge) (write) A master transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed. DataA DataA/AP A = acknowledge (SDA low) From master to slave A = not acknowledge (SDA high) S = Start Condition A master transmitter addresses a slave receiver From slave to master P = Stop Condition with a 10-bit address. FIGURE 11-20:MASTER-RECEIVER SEQUENCE For 7-bit address: For 10-bit address: SSlave AddressR/WA Data A Data A P SSlave AddressR/WA1Slave AddressA2 First 7 bits Second byte '1' (read) data transferred (n bytes - acknowledge) (write) A master reads a slave immediately after the first byte. SrSlave AddressR/WA3DataA DataAP A = acknowledge (SDA low) First 7 bits From master to slave A = not acknowledge (SDA high) (read) S = Start Condition A master transmitter addresses a slave receiver From slave to master P = Stop Condition with a 10-bit address. FIGURE 11-21:COMBINED FORMAT (read or write) (n bytes + acknowledge) SSlave AddressR/WA Data A/A Sr Slave AddressR/WA Data A/A P (read) Sr = repeated (write) Direction of transfer Start Condition may change at this point Transfer direction of data and acknowledgment bits depends on R/W bits. Combined format: SrSlave AddressR/W A Slave AddressA DataA Data A/A Sr Slave AddressR/WADataA DataAP First 7 bits Second byte First 7 bits (write) (read) Combined format - A master addresses a slave with a 10-bit address, then transmits data to this slave and reads data from this slave. A = acknowledge (SDA low) From master to slave A = not acknowledge (SDA high) S = Start Condition From slave to master P = Stop Condition  1997-2013 Microchip Technology Inc. DS30234E-page 97

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 11.4.4 MULTI-MASTER 11.2.4.2 Clock Synchronization The I2C protocol allows a system to have more than Clock synchronization occurs after the devices have started arbitration. This is performed using a wired- one master. This is called multi-master. When two or AND connection to the SCL line. A high to low transition more masters try to transfer data at the same time, arbi- on the SCL line causes the concerned devices to start tration and synchronization occur. counting off their low period. Once a device clock has 11.4.4.1 ARBITRATION gone low, it will hold the SCL line low until its SCL high state is reached. The low to high transition of this clock Arbitration takes place on the SDA line, while the SCL may not change the state of the SCL line, if another line is high. The master which transmits a high when device clock is still within its low period. The SCL line is the other master transmits a low loses arbitration held low by the device with the longest low period. (Figure11-22), and turns off its data output stage. A Devices with shorter low periods enter a high wait- master which lost arbitration can generate clock pulses state, until the SCL line comes high. When the SCL line until the end of the data byte where it lost arbitration. comes high, all devices start counting off their high When the master devices are addressing the same periods. The first device to complete its high period will device, arbitration continues into the data. pull the SCL line low. The SCL line high time is deter- mined by the device with the shortest high period, FIGURE 11-22:MULTI-MASTER Figure11-23. ARBITRATION (TWO MASTERS) FIGURE 11-23:CLOCK SYNCHRONIZATION transmitter 1 loses arbitration DATA 1 SDA wait start counting state HIGH period DATA 1 DATA 2 CLK 1 SDA counter CLK reset 2 SCL SCL Masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. This is because the winning mas- ter-transmitter may be addressing it. Arbitration is not allowed between: (cid:129) A repeated START condition (cid:129) A STOP condition and a data bit (cid:129) A repeated START condition and a STOP condi- tion Care needs to be taken to ensure that these conditions do not occur. DS30234E-page 98  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 11.5 SSP I2C Operation The SSPCON register allows control of the I2C opera- The SSP module in I2C mode fully implements all slave tion. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate (cid:129) I2C Slave mode (7-bit address) firmware implementations of the master functions. The (cid:129) I2C Slave mode (10-bit address) SSP module implements the standard mode specifica- (cid:129) I2C Slave mode (7-bit address), with start and tions as well as 7-bit and 10-bit addressing. Two pins stop bit interrupts enabled are used for data transfer. These are the RC3/SCK/ (cid:129) I2C Slave mode (10-bit address), with start and SCL pin, which is the clock (SCL), and the RC4/SDI/ stop bit interrupts enabled SDA pin, which is the data (SDA). The user must con- (cid:129) I2C Firmware controlled Master Mode, slave is figure these pins as inputs or outputs through the idle TRISC<4:3> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSP- Selection of any I2C mode, with the SSPEN bit set, CON<5>). forces the SCL and SDA pins to be open drain, pro- vided these pins are programmed to inputs by setting FIGURE 11-24:SSP BLOCK DIAGRAM the appropriate TRISC bits. (I2C MODE) The SSPSTAT register gives the status of the data transfer. This information includes detection of a START or STOP bit, specifies if the received byte was Internal data or address if the next byte is the completion of 10- data bus bit address, and if this will be a read or write data trans- Read Write fer. The SSPSTAT register is read only. The SSPBUF is the register to which transfer data is SSPBUF reg RC3/SCK/SCL written to or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the shift SSPBUF and SSPSR create a doubled buffered clock receiver. This allows reception of the next byte to begin SSPSR reg before reading the last byte of received data. When the RC4/ MSb LSb complete byte is received, it is transferred to the SDI/ SSPBUF register and flag bit SSPIF is set. If another SDA Match detect Addr Match complete byte is received before the SSPBUF register is read, a receiver overflow has occurred and bit SSPOV (SSPCON<6>) is set and the byte in the SSPADD reg SSPSR is lost. The SSPADD register holds the slave address. In 10-bit Start and Set, Reset mode, the user first needs to write the high byte of the Stop bit detect S, P bits (SSPSTAT reg) address (1111 0 A9 A8 0). Following the high byte address match, the low byte of the address needs to be The SSP module has five registers for I2C operation. loaded (A7:A0). These are the: (cid:129) SSP Control Register (SSPCON) (cid:129) SSP Status Register (SSPSTAT) (cid:129) Serial Receive/Transmit Buffer (SSPBUF) (cid:129) SSP Shift Register (SSPSR) - Not directly acces- sible (cid:129) SSP Address Register (SSPADD)  1997-2013 Microchip Technology Inc. DS30234E-page 99

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 11.5.1 SLAVE MODE address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF In slave mode, the SCL and SDA pins must be config- and SSPOV bits are clear, the following events occur: ured as inputs (TRISC<4:3> set). The SSP module will a) The SSPSR register value is loaded into the override the input state with the output data when SSPBUF register. required (slave-transmitter). b) The buffer full bit, BF is set. When an address is matched or the data transfer after c) An ACK pulse is generated. an address match is received, the hardware automati- cally will generate the acknowledge (ACK) pulse, and d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set then load the SSPBUF register with the received value (interrupt is generated if enabled) - on the falling currently in the SSPSR register. edge of the ninth SCL pulse. There are certain conditions that will cause the SSP In 10-bit address mode, two address bytes need to be module not to give this ACK pulse. These are if either received by the slave (Figure11-16). The five Most Sig- (or both): nificant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must a) The buffer full bit BF (SSPSTAT<0>) was set specify a write so the slave device will receive the sec- before the transfer was received. ond address byte. For a 10-bit address the first byte b) The overflow bit SSPOV (SSPCON<6>) was set would equal ‘1111 0 A9 A8 0’, where A9 and A8 are before the transfer was received. the two MSbs of the address. The sequence of events In this case, the SSPSR register value is not loaded for 10-bit address is as follows, with steps 7- 9 for slave- into the SSPBUF, but bit SSPIF (PIR1<3>) is set. transmitter: Table11-4 shows what happens when a data transfer 1. Receive first (high) byte of Address (bits SSPIF, byte is received, given the status of bits BF and SSPOV. BF, and bit UA (SSPSTAT<1>) are set). The shaded cells show the condition where user soft- 2. Update the SSPADD register with second (low) ware did not properly clear the overflow condition. Flag byte of Address (clears bit UA and releases the bit BF is cleared by reading the SSPBUF register while SCL line). bit SSPOV is cleared through software. 3. Read the SSPBUF register (clears bit BF) and The SCL clock input must have a minimum high and clear flag bit SSPIF. low for proper operation. The high and low times of the 4. Receive second (low) byte of Address (bits I2C specification as well as the requirement of the SSP SSPIF, BF, and UA are set). module is shown in timing parameter #100 and param- 5. Update the SSPADD register with the first (high) eter #101. byte of Address, if match releases SCL line, this 11.5.1.1 ADDRESSING will clear bit UA. 6. Read the SSPBUF register (clears bit BF) and Once the SSP module has been enabled, it waits for a clear flag bit SSPIF. START condition to occur. Following the START condi- 7. Receive repeated START condition. tion, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the 8. Receive first (high) byte of Address (bits SSPIF clock (SCL) line. The value of register SSPSR<7:1> is and BF are set). compared to the value of the SSPADD register. The 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. TABLE 11-4: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF Generate ACK (SSP Interrupt occurs BF SSPOV SSPSR  SSPBUF Pulse if enabled) 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes DS30234E-page 100  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 11.5.1.2 RECEPTION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- When the R/W bit of the address byte is clear and an ware. The SSPSTAT register is used to determine the address match occurs, the R/W bit of the SSPSTAT status of the byte. register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow con- dition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. FIGURE 11-25: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W=0 Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACKD7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF (PIR1<3>) Cleared in software Bus Master terminates transfer BF (SSPSTAT<0>) SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.  1997-2013 Microchip Technology Inc. DS30234E-page 101

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 11.5.1.3 TRANSMISSION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and When the R/W bit of the incoming address byte is set the SSPSTAT register is used to determine the status and an address match occurs, the R/W bit of the of the byte. Flag bit SSPIF is set on the falling edge of SSPSTAT register is set. The received address is the ninth clock pulse. loaded into the SSPBUF register. The ACK pulse will As a slave-transmitter, the ACK pulse from the master- be sent on the ninth bit, and pin RC3/SCK/SCL is held receiver is latched on the rising edge of the ninth SCL low. The transmit data must be loaded into the SSP- input pulse. If the SDA line was high (not ACK), then the BUF register, which also loads the SSPSR register. data transfer is complete. When the ACK is latched by Then pin RC3/SCK/SCL should be enabled by setting the slave, the slave logic is reset (resets SSPSTAT reg- bit CKP (SSPCON<4>). The master must monitor the ister) and the slave then monitors for another occur- SCL pin prior to asserting another clock pulse. The rence of the START bit. If the SDA line was low (ACK), slave devices may be holding off the master by stretch- the transmit data must be loaded into the SSPBUF reg- ing the clock. The eight data bits are shifted out on the ister, which also loads the SSPSR register. Then pin falling edge of the SCL input. This ensures that the SDA RC3/SCK/SCL should be enabled by setting bit CKP. signal is valid during the SCL high time (Figure11-26). FIGURE 11-26:I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address R/W = 1 Transmitting Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S P Data in SCL held low sampled while CPU responds to SSPIF SSPIF (PIR1<3>) BF (SSPSTAT<0>) cleared in software From SSP interrupt SSPBUF is written in software service routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) DS30234E-page 102  1997-2013 Microchip Technology Inc.

Applicable Devices PIC16C6X 616262AR6263R636464AR646565AR656667 11.5.2 MASTER MODE 11.5.3 MULTI-MASTER MODE Master mode of operation is supported in firmware In multi-master mode, the interrupt generation on the using interrupt generation on the detection of the detection of the START and STOP conditions allows START and STOP conditions. The STOP (P) and the determination of when the bus is free. The STOP START (S) bits are cleared from a reset or when the (P) and START (S) bits are cleared from a reset or SSP module is disabled. The STOP (P) and START (S) when the SSP module is disabled. The STOP (P) and bits will toggle based on the START and STOP condi- START (S) bits will toggle based on the START and tions. Control of the I2C bus may be taken when the P STOP conditions. Control of the I2C bus may be taken bit is set, or the bus is idle and both the S and P bits are when bit P (SSPSTAT<4>) is set, or the bus is idle and clear. both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt In master mode the SCL and SDA lines are manipu- when the STOP condition occurs. lated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the In multi-master operation, the SDA line must be moni- value(s) in PORTC<4:3>. So when transmitting data, a tored to see if the signal level is the expected output '1' data bit must have the TRISC<4> bit set (input) and level. This check only needs to be done when a high a '0' data bit must have the TRISC<4> bit cleared (out- level is output. If a high level is expected and a low level put). The same scenario is true for the SCL line with the is present, the device needs to release the SDA and TRISC<3> bit. SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are: The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): (cid:129) Address Transfer (cid:129) START condition (cid:129) Data Transfer (cid:129) STOP condition When the slave logic is enabled, the slave continues to (cid:129) Data transfer byte transmitted/received receive. If arbitration was lost during the address trans- fer stage, communication to the device may be in prog- Master mode of operation can be done with either the ress. If addressed an ACK pulse will be generated. If slave mode idle (SSPM3:SSPM0 = 1011) or with the arbitration was lost during the data transfer stage, the slave active. When both master and slave modes are device will need to re-transfer the data at a later time. enabled, the software needs to differentiate the source(s) of the interrupt. TABLE 11-5: REGISTERS ASSOCIATED WITH I2C OPERATION Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets BOR 0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Bh, 18Bh 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP(3) CKE(3) D/A P S R/W UA BF 0000 0000 0000 0000 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: PSPIF and PSPIE are reserved on the PIC16C66, always maintain these bits clear. 2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. 3: The SMP and CKE bits are implemented on the PIC16C66/67 only. All other PIC16C6X devices have these two bits unim- plemented, read as '0'.  1997-2013 Microchip Technology Inc. DS30234E-page 103

PIC16C6X Applicable Devices 616262AR6263R636464AR646565AR656667 FIGURE 11-27:OPERATION OF THE I2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE IDLE_MODE (7-bit): if (Addr_match) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { transfer SSPSR  SSPBUF; send ACK = 0; } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( ACK Received = 1) { End of transmission; Go back to IDLE_MODE; } else if ( ACK Received = 0) Go back to XMIT_MODE; IDLE_MODE (10-Bit): If (High_byte_addr_match AND (R/W = 0)) { PRIOR_ADDR_MATCH = FALSE; Set interrupt; if ((SSPBUF = Full) OR ((SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { Set UA = 1; Send ACK = 0; While (SSPADD not updated) Hold SCL low; Clear UA = 0; Receive Low_addr_byte; Set interrupt; Set UA = 1; If (Low_byte_addr_match) { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear UA = 0; Set RCV_MODE; } } } else if (High_byte_addr_match AND (R/W = 1) { if (PRIOR_ADDR_MATCH) { send ACK = 0; set XMIT_MODE; } else PRIOR_ADDR_MATCH = FALSE; } DS30234E-page 104  1997-2013 Microchip Technology Inc.

PIC16C6X 12.0 UNIVERSAL SYNCHRONOUS minals and personal computers, or it can be configured ASYNCHRONOUS RECEIVER as a half duplex synchronous system that can commu- nicate with peripheral devices such as A/D or D/A inte- TRANSMITTER (USART) grated circuits, Serial EEPROMs etc. MODULE The USART can be configured in the following modes: Applicable Devices (cid:129) Asynchronous (full duplex) 616262AR6263R636464AR646565AR656667 (cid:129) Synchronous - Master (half duplex) The Universal Synchronous Asynchronous Receiver (cid:129) Synchronous - Slave (half duplex) Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Com- Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to munications Interface or SCI) The USART can be con- be set in order to configure pins RC6/TX/CK and figured as a full duplex asynchronous system that can RC7/RX/DT as the Universal Synchronous Asynchro- communicate with peripheral devices such as CRT ter- nous Receiver Transmitter. FIGURE 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D R = Readable bit bit7 bit0 W =Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: CSRC: Clock Source Select bit Asynchronous mode Don’t care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) bit 6: TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5: TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4: SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3: Unimplemented: Read as '0' bit 2: BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed Note: For the PIC16C63/R63/65/65A/R65 the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional infor- mation or use the PIC16C66/67. 0 = Low speed Synchronous mode Unused in this mode bit 1: TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit.  1997-2013 Microchip Technology Inc. DS30234E-page 105

PIC16C6X FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x SPEN RX9 SREN CREN — FERR OERR RX9D R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset x = unknown bit 7: SPEN: Serial Port Enable bit (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins when bits TRISC<7:6> are set) 1 = Serial port enabled 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5: SREN: Single Receive Enable bit Asynchronous mode Don’t care Synchronous mode - master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave Unused in this mode bit 4: CREN: Continuous Receive Enable bit Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3: Unimplemented: Read as '0' bit 2: FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1: OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30234E-page 106  1997-2013 Microchip Technology Inc.

PIC16C6X 12.1 USART Baud Rate Generator (BRG) EXAMPLE 12-1: CALCULATING BAUD RATE ERROR Applicable Devices 616262AR6263R636464AR646565AR656667 Desired Baud rate = Fosc / (64 (X + 1)) The BRG supports both the Asynchronous and Syn- 9600 = 16000000 /(64 (X + 1)) chronous modes of the USART. It is a dedicated 8-bit X = 25.042 = 25 baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In asynchronous Calculated Baud Rate=16000000 / (64 (25 + 1)) mode bit BRGH (TXSTA<2>) also controls the baud = 9615 rate. In synchronous mode bit BRGH is ignored. Error = (Calculated Baud Rate - Desired Baud Rate) Table12-1 shows the formula for computation of the Desired Baud Rate baud rate for different USART modes which only apply = (9615 - 9600) / 9600 in master mode (internal clock). = 0.16% Given the desired baud rate and Fosc, the nearest inte- ger value for the SPBRG register can be calculated using the formula in Table12-1. From this, the error in It may be advantageous to use the high baud rate baud rate can be determined. (BRGH = 1) even for slower baud clocks. This is Example12-1 shows the calculation of the baud rate because the FOSC/(16(X + 1)) equation can reduce the error for the following conditions: baud rate error in some cases. FOSC = 16 MHz Note: For the PIC16C63/R63/65/65A/R65 the Desired Baud Rate = 9600 asynchronous high speed mode (BRGH=1) may experience a high rate of BRGH = 0 receive errors. It is recommended that SYNC = 0 BRGH=0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information or use the PIC16C66/67. Writing a new value to the SPBRG register, causes the BRG timer to be reset (or cleared), this ensures that the BRG does not wait for a timer overflow before output- ting the new baud rate. TABLE 12-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate = FOSC/(16(X+1)) 1 (Synchronous) Baud Rate = FOSC/(4(X+1)) N/A X = value in SPBRG (0 to 255) TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.  1997-2013 Microchip Technology Inc. DS30234E-page 107

PIC16C6X TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE FOSC = 20 MHz 16 MHz 10 MHz 7.15909 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value KBAUD KBAUD KBAUD KBAUD (K) ERROR (decimal) ERROR (decimal) ERROR (decimal) ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - 9.766 +1.73 255 9.622 +0.23 185 19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5 500 500 0 9 500 0 7 500 0 4 NA - - HIGH 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0 LOW 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255 FOSC = 5.0688 MHz 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG SPBRG RATE KBAUD % value KBAUD % value KBAUD % value KBAUD % value KBAUD % value (K) ERROR(decimal) ERROR(decimal) ERROR(decimal) ERROR(decimal) ERROR(decimal) 0.3 NA - - NA - - NA - - NA - - 0.303 +1.14 26 1.2 NA - - NA - - NA - - 1.202 +0.16 207 1.170 -2.48 6 2.4 NA - - NA - - NA - - 2.404 +0.16 103 NA - - 9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 NA - - 19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 NA - - 76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 NA - - 96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 NA - - NA - - 300 316.8 +5.60 3 NA - - 298.3 -0.57 2 NA - - NA - - 500 NA - - NA - - NA - - NA - - NA - - HIGH 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0 LOW 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255 TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz 16 MHz 10 MHz 7.15909 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value (K) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92 2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46 9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11 19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 NA - - 96 104.2 +8.51 2 NA - - NA - - NA - - 300 312.5 +4.17 0 NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0 LOW 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255 FOSC = 5.0688 MHz 4 MHz 3.579545 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value % value (K) KBAUD ERROR(decimal) KBAUD ERROR(decimal) KBAUD ERROR(decimal) KBAUD ERROR(decimal) KBAUD ERROR(decimal) 0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 NA - - 2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 NA - - 9.6 9.9 +3.13 7 NA - - 9.322 -2.90 5 NA - - NA - - 19.2 19.8 +3.13 3 NA - - 18.64 -2.90 2 NA - - NA - - 76.8 79.2 +3.13 0 NA - - NA - - NA - - NA - - 96 NA - - NA - - NA - - NA - - NA - - 300 NA - - NA - - NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - NA - - HIGH 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0 LOW 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255 DS30234E-page 108  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 20 MHz 16 MHz 10 MHz 7.16 MHz BAUD SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value (K) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46 19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22 38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11 57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7 115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3 250 250 0 4 250 0 3 NA - - NA - - 625 625 0 1 NA - - 625 0 0 NA - - 1250 1250 0 0 NA - - NA - - NA - - FOSC = 5.068 MHz 4 MHz 3.579 MHz 1 MHz 32.768 kHz BAUD SPBRG SPBRG SPBRG SPBRG SPBRG RATE % value % value % value % value % value (K) KBAUD ERROR (decimal) KBAUD ERROR(decimal) KBAUD ERROR(decimal) KBAUD ERROR(decimal) KBAUD ERROR(decimal) 9.6 9.6 0 32 NA - - 9.727 +1.32 22 8.928 -6.99 6 NA - - 19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 NA - - 38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 NA - - 57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 NA - - 115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 NA - - NA - - 250 NA - - NA - - 223.721 -10.51 0 NA - - NA - - 625 NA - - NA - - NA - - NA - - NA - - 1250 NA - - NA - - NA - - NA - - NA - - Note: For the PIC16C63/R63/65/65A/R65 the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information or use the PIC16C66/67.  1997-2013 Microchip Technology Inc. DS30234E-page 109

PIC16C6X 12.1.1 SAMPLING set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge The data on the RC7/RX/DT pin is sampled three times after the first falling edge of a x4 clock (Figure12-4 and by a majority detect circuit to determine if a high or a Figure12-5). low level is present at the RX pin. If bit BRGH (TXSTA<2>) is clear (i.e., at the low baud rates), the sampling is done on the seventh, eighth and ninth fall- ing edges of a x16 clock (Figure12-3). If bit BRGH is FIGURE 12-3: RX PIN SAMPLING SCHEME (BRGH = 0) PIC16C63/R63/65/65A/R65) RX Start bit Bit0 (RC7/RX/DT pin) Baud CLK for all but start bit baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples FIGURE 12-4: RX PIN SAMPLING SCHEME (BRGH = 1) (PIC16C63/R63/65/65A/R65) RC7/RX/DT pin Start Bit bit0 bit1 baud clk First falling edge after RX pin goes low Second rising edge x4 clk 1 2 3 4 1 2 3 4 1 2 Q2, Q4 clk Samples Samples Samples FIGURE 12-5: RX PIN SAMPLING SCHEME (BRGH = 1) (PIC16C63/R63/65/65A/R65) RC7/RX/DT pin Start Bit bit0 Baud clk for all but start bit baud clk First falling edge after RX pin goes low Second rising edge x4 clk 1 2 3 4 Q2, Q4 clk Samples DS30234E-page 110  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 12-6: RX PIN SAMPLING SCHEME (BRGH = 0 OR = 1) (PIC16C66/67) RX Start bit Bit0 (RC7/RX/DT pin) Baud CLK for all but start bit baud CLK x16 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Samples  1997-2013 Microchip Technology Inc. DS30234E-page 111

PIC16C6X 12.2 USART Asynchronous Mode abled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of Applicable Devices enable bit TXIE and cannot be cleared in software. It 616262AR6263R636464AR646565AR656667 will reset only when new data is loaded into the TXREG In this mode, the USART uses standard nonreturn-to- register. While flag bit TXIF indicates the status of the zero (NRZ) format (one start bit, eight or nine data bits TXREG register, another bit, TRMT (TXSTA<1>) and one stop bit). The most common data format is shows the status of the TSR register. Status bit TRMT 8-bits. An on-chip dedicated 8-bit baud rate generator is a read only bit which is set when the TSR register is can be used to derive standard baud rate frequencies empty. No interrupt logic is tied to this bit, so the user from the oscillator. The USART transmits and receives has to poll this bit in order to determine if the TSR reg- the LSb first. The USART’s transmitter and receiver are ister is empty. functionally independent but use the same data format and baud rate. The baud rate generator produces a Note 1: The TSR register is not mapped in data clock either x16 or x64 of the bit shift rate, depending memory so it is not available to the user. on bit BRGH (TXSTA<2>). Parity is not supported by Note 2: Flag bit TXIF is set when enable bit TXEN the hardware, but can be implemented in software (and is set. stored as the ninth data bit). Asynchronous mode is Transmission is enabled by setting enable bit TXEN stopped during SLEEP. (TXSTA<5>). The actual transmission will not occur Asynchronous mode is selected by clearing bit SYNC until the TXREG register has been loaded with data (TXSTA<4>). and the baud rate generator (BRG) has produced a The USART Asynchronous module consists of the fol- shift clock (Figure12-7). The transmission can also be lowing important elements: started by first loading the TXREG register and then setting enable bit TXEN. Normally when transmission (cid:129) Baud Rate Generator is first started, the TSR register is empty, so a transfer (cid:129) Sampling Circuit to the TXREG register will result in an immediate trans- (cid:129) Asynchronous Transmitter fer to TSR register resulting in an empty TXREG regis- (cid:129) Asynchronous Receiver ter. A back-to-back transfer is thus possible (Figure12- 9). Clearing enable bit TXEN during a transmission will 12.2.1 USART ASYNCHRONOUS TRANSMITTER cause the transmission to be aborted and will reset the transmitter. As a result the RC6/TX/CK pin will revert to The USART transmitter block diagram is shown in hi-impedance. Figure12-7. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its In order to select 9-bit transmission, transmit bit TX9 data from the read/write transmit buffer, TXREG. The (TXSTA<6>) should be set and the ninth bit should be TXREG register is loaded with data in software. The written to bit TX9D (TXSTA<0>). The ninth bit must be TSR register is not loaded until the STOP bit has been written before writing the 8-bit data to the TXREG reg- transmitted from the previous load. As soon as the ister. This is because a data write to the TXREG regis- STOP bit is transmitted, the TSR is loaded with new ter can result in an immediate transfer of the data to the data from the TXREG (if available). Once the TXREG TSR register (if the TSR is empty). In such a case, an register transfers the data to the TSR register (occurs incorrect ninth data bit maybe loaded in the TSR regis- in one TCY) the TXREG register is empty and flag bit ter. TXIF (PIR1<4>) is set. This interrupt is enabled/dis- FIGURE 12-7: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb LSb (8)  0 Panind BCuofnfetrrol TSR register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D DS30234E-page 112  1997-2013 Microchip Technology Inc.

PIC16C6X Steps to follow when setting up an Asynchronous 5. Enable the transmission by setting bit TXEN, Transmission: which will also set bit TXIF. 1. Initialize the SPBRG register for the appropriate 6. If 9-bit transmission is selected, the ninth bit baud rate. If a high speed baud rate is desired, should be loaded in bit TX9D. then set bit BRGH. (Section12.1). 7. Load data to the TXREG register (starts trans- 2. Enable the asynchronous serial port by clearing mission). bit SYNC and setting bit SPEN. 3. If interrupts are desired, then set enable bit TXIE. 4. If 9-bit transmission is desired, then set transmit bit TX9. FIGURE 12-8: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG reg Word 1 BRG output (shift clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit WORD 1 TXIF bit (Transmit buffer reg. empty flag) TRMT bit WTraOnRsDm i1t Shift Reg (Transmit shift reg. empty flag) FIGURE 12-9: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG reg Word 1 Word 2 BRG output (shift clock) RC6/TX/CK (pin) TXIF bit Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Start Bit Bit 0 (interrupt reg. flag) WORD 1 WORD 2 T(reTRrgaM.n eTsmm bpiittt ys hfliaftg) TWraOnRsmD it1 Shift Reg. WTraOnRsDm i2t Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 113

PIC16C6X 12.2.2 USART ASYNCHRONOUS RECEIVER possible for two bytes of data to be received and trans- ferred to the RCREG FIFO and a third byte begin shift- The receiver block diagram is shown in Figure12-10. ing to the RSR register. On the detection of the STOP The data comes in the RC7/RX/DT pin and drives the bit of the third byte, if the RCREG is still full, then the data recovery block. The data recovery block is actually overrun error bit, OERR (RCSTA<1>) will be set. The a high speed shifter operating at x16 times the baud word in the RSR register will be lost. The RCREG reg- rate, whereas the main receive serial shifter operates at ister can be read twice to retrieve the two bytes in the the bit rate or at FOSC. FIFO. Overrun bit OERR has to be cleared in software. Once Asynchronous mode is selected, reception is This is done by resetting the receive logic (CREN is enabled by setting bit CREN (RCSTA<4>). cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited, The heart of the receiver is the receive (serial) shift reg- so it is essential to clear overrun bit OERR if it is set. ister (RSR). After sampling the STOP bit, the received Framing error bit FERR (RCSTA<2>) is set if a stop bit data in the RSR is transferred to the RCREG register (if is detected as clear. Error bit FERR and the 9th receive it is empty). If the transfer is complete, flag bit RCIF bit are buffered the same way as the receive data. (PIR1<5>) is set. The actual interrupt can be Reading the RCREG register will load bits RX9D and enabled/disabled by setting/clearing enable bit RCIE FERR with new values. Therefore it is essential for the (PIE1<5>). Flag bit RCIF is a read only bit which is user to read the RCSTA register before reading cleared by the hardware. It is cleared when the RCREG RCREG in order not to lose the old FERR and RX9D register has been read and is empty. The RCREG is information. double buffered register, i.e., it is a two deep FIFO. It is FIGURE 12-10:USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK OERR FERR CREN SPBRG  o6r4 MSb RSR register LSb Baud Rate Generator  16 Stop (8) 7  1 0 Start RC7/RX/DT Panind BCuofnfetrrol DRaetcaovery RX9 SPEN RX9D RCREG register FIFO 8 Interrupt RCIF Data Bus RCIE FIGURE 12-11:ASYNCHRONOUS RECEPTION RC7/RX/DT (pin) Start Start Start bit bit0 bit1 bit7/8 Stop bit bit0 bit7/8 Stop bit bit7/8 Stop bit bit bit Rcv shift reg Rcv buffer reg WORD 1 WORD 2 Read Rcv RCREG RCREG buffer reg RCREG RCIF (interrupt flag) OERR bit CREN bit Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing overrun error bit OERR to be set. DS30234E-page 114  1997-2013 Microchip Technology Inc.

PIC16C6X Steps to follow when setting up an Asynchronous 6. Flag bit RCIF will be set when reception is com- Reception: plete, and an interrupt will be generated if enable bit RCIE was set. 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, 7. Read the RCSTA register to get the ninth bit (if set bit BRGH (Section12.1). enabled) and determine if any error occurred during reception. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 8. Read the 8-bit received data by reading the RCREG register. 3. If interrupts are desired, then set enable bit RCIE. 9. If any error occurred, clear the error by clearing enable bit CREN. 4. If 9-bit reception is desired, then set bit RX9. 5. Enable the reception by setting enable bit CREN. TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: PSPIE and PSPIF are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIE1<6> and PIR1<6> are reserved, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 115

PIC16C6X 12.3 USART Synchronous Master Mode Clearing enable bit TXEN, during a transmission, will cause the transmission to be aborted and will reset the Applicable Devices transmitter. The DT and CK pins will revert to hi-imped- 616262AR6263R636464AR646565AR656667 ance. If, during a transmission, either bit CREN or bit In Synchronous Master mode the data is transmitted in SREN is set the transmission is aborted and the DT pin a half-duplex manner i.e., transmission and reception reverts to a hi-impedance state (for a reception). The do not occur at the same time. When transmitting data CK pin will remain an output if bit CSRC is set (internal the reception is inhibited and vice versa. Synchronous clock). The transmitter logic however, is not reset mode is entered by setting bit SYNC (TXSTA<4>). In although it is disconnected from the pins. In order to addition enable bit SPEN (RCSTA<7>) is set in order to reset the transmitter, the user has to clear enable bit configure the RC6 and RC7 I/O pins to CK (clock) and TXEN. If enable bit SREN is set (to interrupt an on DT (data) lines respectively. The Master mode indi- going transmission and receive a single word), then cates that the processor transmits the master clock on after the single word is received, enable bit SREN will the CK line. The Master mode is entered by setting bit be cleared, and the serial port will revert back to trans- CSRC (TXSTA<7>). mitting since enable bit TXEN is still set. The DT line will immediately switch from hi-impedance receive 12.3.1 USART SYNCHRONOUS MASTER mode to transmit and start driving. To avoid this, enable TRANSMISSION bit TXEN should be cleared. The USART transmitter block diagram is shown in In order to select 9-bit transmission, bit TX9 Figure12-7. The heart of the transmitter is the transmit (TXSTA<6>) should be set and the ninth bit should be (serial) shift register (TSR). The shift register obtains its written to bit TX9D (TXSTA<0>). The ninth bit must be data from the read/write transmit buffer register, written before writing the 8-bit data to the TXREG reg- TXREG. The TXREG register is loaded with data in ister. This is because a data write to the TXREG regis- software. The TSR register is not loaded until the last ter can result in an immediate transfer of the data to the bit has been transmitted from the previous load. As TSR register (if the TSR is empty). If the TSR register soon as the last bit is transmitted, the TSR register is was empty and the TXREG register was written before loaded with new data from the TXREG register (if avail- writing the “new” TX9D, the “present” value of bit TX9D able). Once the TXREG register transfers the data to is loaded. the TSR register (occurs in one Tcycle), the TXREG Steps to follow when setting up a Synchronous Master register is empty and interrupt flag bit TXIF (PIR1<4>) Transmission: is set. This interrupt can be enabled/disabled by set- ting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF 1. Initialize the SPBRG register for the appropriate will be set regardless of the status of enable bit TXIE baud rate (Section12.1). and cannot be cleared in software. It will clear only 2. Enable the synchronous master serial port by when new data is loaded into the TXREG register. setting bits SYNC, SPEN, and CSRC. While flag bit TXIF indicates the status of the TXREG 3. If interrupts are desired, then set enable bit register, another bit, TRMT (TXSTA<1>), shows the TXIE. status of the TSR register. Status bit TRMT is a read 4. If 9-bit transmission is desired, then set bit TX9. only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll 5. Enable the transmission by setting enable bit this bit in order to determine if the TSR register is TXEN. empty. The TSR register is not mapped in data memory 6. If 9-bit transmission is selected, the ninth bit so it is not available to the user. should be loaded in bit TX9D. Transmission is enabled by setting enable bit TXEN 7. Start transmission by loading data to the (TXSTA<5>). The actual transmission will not occur TXREG register. until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is sta- ble around the falling edge of the synchronous clock (Figure12-12). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN (Figure12-13). This is advantageous when slow baud rates are selected, since the BRG is kept in reset when bits TXEN, CREN, and SREN are clear. Setting enable bit TXEN will start the BRG, cre- ating a shift clock immediately. Normally when trans- mission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immedi- ate transfer to TSR resulting in an empty TXREG reg- ister. Back-to-back transfers are possible. DS30234E-page 116  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: PSPIE and PSPIF are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIE1<6> and PIR1<6> are reserved, always maintain these bits clear. FIGURE 12-12:SYNCHRONOUS TRANSMISSION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin Bit 0 Bit 1 Bit 2 Bit 7 Bit 0 Bit 1 Bit 7 WORD 1 WORD 2 RC6/TX/CK pin Write to TXREG reg Write word1 Write word2 TXIF bit (Interrupt flag) TRMT bTiRtMT '1' '1' TXEN bit Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words FIGURE 12-13:SYNCHRONOUS TRANSMISSION THROUGH TXEN RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit  1997-2013 Microchip Technology Inc. DS30234E-page 117

PIC16C6X 12.3.2 USART SYNCHRONOUS MASTER Steps to follow when setting up Synchronous Master RECEPTION Reception: 1. Initialize the SPBRG register for the appropriate Once Synchronous Mode is selected, reception is baud rate (Section 12.1). enabled by setting either enable bit SREN (RCSTA<5>) bit or enable bit CREN (RCSTA<4>). Data is sampled 2. Enable the synchronous master serial port by on the DT pin on the falling edge of the clock. If enable setting bits SYNC, SPEN, and CSRC. bit SREN is set, then only a single word is received. If 3. Ensure bits CREN and SREN are clear. enable bit CREN is set, the reception is continuous until 4. If interrupts are desired, then set enable bit bit CREN is cleared. If both the bits are set then bit RCIE. CREN takes precedence. After clocking the last bit, the 5. If 9-bit reception is desired, then set bit RX9. received data in the Receive Shift Register (RSR) is 6. If a single reception is required, set enable bit transferred to the RCREG register (if it is empty). When SREN. For continuous reception set enable bit the transfer is complete, interrupt bit RCIF (PIR1<5>) is CREN. set. The actual interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit 7. Flag bit RCIF will be set when reception is com- RCIF is a read only bit which is reset by the hardware. plete and an interrupt will be generated if enable In this case, it is reset when the RCREG register has bit RCIE was set. been read and is empty. The RCREG is a double buff- 8. Read the RCSTA register to get the ninth bit (if ered register, i.e., it is a two deep FIFO. It is possible for enabled) and determine if any error occurred two bytes of data to be received and transferred to the during reception. RCREG FIFO and a third byte to begin shifting into the 9. Read the 8-bit received data by reading the RSR register. On the clocking of the last bit of the third RCREG register. byte, if the RCREG register is still full, then overrun 10. If any error occurred, clear the error by clearing error bit, OERR (RCSTA<1>) is set. The word in the enable bit CREN. RSR register will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Over- run error bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The 9th receive bit is buff- ered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value. Therefore it is essential for the user to read the RCSTA register before reading the RCREG register in order not to lose the old RX9D bit information. TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Master Reception. Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. DS30234E-page 118  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 12-14:SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.  1997-2013 Microchip Technology Inc. DS30234E-page 119

PIC16C6X 12.4 USART Synchronous Slave Mode 12.4.2 USART SYNCHRONOUS SLAVE RECEPTION Applicable Devices 616262AR6263R636464AR646565AR656667 The operation of the synchronous master and slave Synchronous Slave Mode differs from Master Mode in modes is identical except in the case of the SLEEP the fact that the shift clock is supplied externally at the mode. Also, enable bit SREN is a don't care in slave CK pin (instead of being supplied internally in master mode. mode). This allows the device to transfer or receive If receive is enabled by setting bit CREN prior to the data while in SLEEP mode. Slave mode is entered by SLEEP instruction, then a word may be received during clearing bit CSRC (TXSTA<7>). SLEEP. On completely receiving the word, the RSR 12.4.1 USART SYNCHRONOUS SLAVE register will transfer the data to the RCREG register TRANSMIT and if enable bit RCIE is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is The operation of the synchronous master and slave enabled, the program will branch to the interrupt vector modes are identical except in the case of the SLEEP (0004h). mode. Steps to follow when setting up a Synchronous Slave If two words are written to the TXREG and then the Reception: SLEEP instruction is executed, the following will occur: 1. Enable the synchronous master serial port by a) The first word will immediately transfer to the setting bits SYNC and SPEN, and clearing bit TSR register and transmit. CSRC. b) The second word will remain in TXREG register. 2. If interrupts are desired, then set enable bit c) Flag bit TXIF will not be set. RCIE. d) When the first word has been shifted out of TSR, 3. If 9-bit reception is desired, then set bit RX9. the TXREG register will transfer the second 4. To enable reception, set enable bit CREN. word to the TSR and flag bit TXIF will now be 5. Flag bit RCIF will be set when reception is com- set. plete, and an interrupt will be generated if e) If enable bit TXIE is set, the interrupt will wake enable bit RCIE was set. the chip from SLEEP and if the global interrupt 6. Read the RCSTA register to get the ninth bit (if is enabled, the program will branch to the inter- enabled) and determine if any error occurred rupt vector (0004h). during reception. Steps to follow when setting up Synchronous Slave 7. Read the 8-bit received data by reading the Transmission: RCREG register. 1. Enable the synchronous slave serial port by set- 8. If any error occurred, clear the error by clearing ting bits SYNC and SPEN, and clearing bit enable bit CREN. CSRC. 2. Clear bits CREN and SREN. 3. If interrupts are desired, then set enable bit TXIE. 4. If 9-bit transmission is desired, then set bit TX9. 5. Enable the transmission by setting bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. DS30234E-page 120  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear. TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) (2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear. 2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.  1997-2013 Microchip Technology Inc. DS30234E-page 121

PIC16C6X NOTES: DS30234E-page 122  1997-2013 Microchip Technology Inc.

PIC16C6X 13.0 SPECIAL FEATURES OF THE timers that offer necessary delays on power-up. One is CPU the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. Applicable Devices The other is the Power-up Timer (PWRT), which pro- 616262AR6263R636464AR646565AR656667 vides a fixed delay of 72 ms (nominal) on power-up What sets a microcontroller apart from other proces- only, designed to keep the part in reset while the power sors are special circuits to deal with the needs of real- supply stabilizes. With these two timers on-chip, most time applications. The PIC16CXX family has a host of applications need no external reset circuitry. such features intended to maximize system reliability, SLEEP mode is designed to offer a very low current minimize cost through elimination of external compo- power-down mode. The user can wake from SLEEP nents, provide power saving operating modes and offer through external reset, Watchdog Timer Wake-up or code protection. These are: through an interrupt. Several oscillator options are also (cid:129) Oscillator selection made available to allow the part to fit the application. (cid:129) Reset The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration - Power-on Reset (POR) bits are used to select various options. - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) 13.1 Configuration Bits - Brown-out Reset (BOR) Applicable Devices (cid:129) Interrupts 616262AR6263R636464AR646565AR656667 (cid:129) Watchdog Timer (WDT) The configuration bits can be programmed (read as '0') (cid:129) SLEEP mode or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in pro- (cid:129) Code protection gram memory location 2007h. (cid:129) ID locations The user will note that address 2007h is beyond the (cid:129) In-circuit serial programming user program memory space. In fact, it belongs to the The PIC16CXX has a Watchdog Timer which can be special test/configuration memory space (2000h - shut off only through configuration bits. It runs off its 3FFFh), which can be accessed only during program- own RC oscillator for added reliability. There are two ming. FIGURE 13-1: CONFIGURATION WORD FOR PIC16C61 — — — — — — — — — CP0 PWRTEWDTE FOSC1 FOSC0 Register: CONFIG bit13 bit0 Address 2007h bit 13-5: Unimplemented: Read as '1' bit 4: CP0: Code protection bit 1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable bit 3: PWRTE: Power-up Timer Enable bit 1 = Power-up Timer enabled 0 = Power-up Timer disabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator  1997-2013 Microchip Technology Inc. DS30234E-page 123

PIC16C6X FIGURE 13-2: CONFIGURATION WORD FOR PIC16C62/64/65 — — — — — — — — CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG bit13 bit0 Address 2007h bit 13-6: Unimplemented: Read as '1' bit 5-4: CP1:CP0: Code Protection bits 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 3: PWRTE: Power-up Timer Enable bit 1 = Power-up Timer enabled 0 = Power-up Timer disabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator FIGURE 13-3: CONFIGURATION WORD FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67 CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTEWDTEFOSC1FOSC0 Register: CONFIG bit13 bit0 Address 2007h bit 13-8: CP1:CP0: Code Protection bits(2) bit 5:4 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = Power-up Timer disabled 0 = Power-up Timer enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to implement the code protection scheme listed. DS30234E-page 124  1997-2013 Microchip Technology Inc.

PIC16C6X 13.2 Oscillator Configurations FIGURE 13-4: CRYSTAL/CERAMIC RESONATOR OPERATION Applicable Devices 616262AR6263R636464AR646565AR656667 (HS, XT OR LP OSC CONFIGURATION) 13.2.1 OSCILLATOR TYPES Tlahtoer PmICo1d6eCs.X TXh eca uns beer coapne rpartoegdr ainm f otuwro d cifofenrfeignut roasticoinl- OSC1 (2) Tloog iincternal bits (FOSC1 and FOSC0) to select one of these four C1 m(cid:129) oLdPes: Low Power Crystal XTALOSC2 RF SLPEICE1P6CXX (cid:129) XT Crystal/Resonator RS (2) To internal logic (cid:129) HS High Speed Crystal/Resonator C2 Note1 (cid:129) RC Resistor/Capacitor See Table13-1, Table13-3, Table13-2 and Table13-4 for 13.2.2 CRYSTAL OSCILLATOR/CERAMIC recommended values of C1 and C2. RESONATORS Note 1: A series resistor may be required for AT strip cut crystals. In LP, XT, or HS modes a crystal or ceramic resonator 2: For the PIC16C61 the buffer is on the OSC2 is connected to the OSC1/CLKIN and OSC2/CLKOUT pin, all other devices have the buffer on the pins to establish oscillation (Figure13-4). The OSC1 pin. PIC16CXX oscillator design requires the use of a par- allel cut crystal. Use of a series cut crystal may give a FIGURE 13-5: EXTERNAL CLOCK INPUT frequency out of the crystal manufacturers specifica- OPERATION (HS, XT OR LP tions. When in LP, XT, or HS modes, the device can OSC CONFIGURATION) have an external clock source to drive the OSC1/ CLKIN pin (Figure13-5). Clock from OSC1 ext. system PIC16CXX Open OSC2  1997-2013 Microchip Technology Inc. DS30234E-page 125

PIC16C6X TABLE 13-1: CERAMIC RESONATORS TABLE 13-3: CAPACITOR SELECTION FOR PIC16C61 CRYSTAL OSCILLATOR FOR PIC16C61 Ranges Tested: Mode Freq OSC1 OSC2 Mode Freq OSC1 OSC2 XT 455 kHz 47 - 100 pF 47 - 100 pF LP 32 kHz 33 - 68 pF 33 - 68 pF 2.0 MHz 15 - 68 pF 15 - 68 pF 200 kHz 15 - 47 pF 15 - 47 pF 4.0 MHz 15 - 68 pF 15 - 68 pF XT 100 kHz 47 - 100 pF 47 - 100 pF HS 8.0 MHz 15 - 68 pF 15 - 68 pF 500 kHz 20 - 68 pF 20 - 68 pF 16.0 MHz 10 - 47 pF 10 - 47 pF 1 MHz 15 - 68 pF 15 - 68 pF 2 MHz 15 - 47 pF 15 - 47 pF These values are for design guidance only. See 4 MHz 15 - 33 pF 15 - 33 pF notes at bottom of page. HS 8 MHz 15 - 47 pF 15 - 47 pF Resonators Used: 20 MHz 15 - 47 pF 15 - 47 pF 455 kHz Panasonic EFO-A455K04B  0.3% These values are for design guidance only. See 2.0 MHz Murata Erie CSA2.00MG  0.5% notes at bottom of page. 4.0 MHz Murata Erie CSA4.00MG  0.5% 8.0 MHz Murata Erie CSA8.00MT  0.5% TABLE 13-4: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR FOR 16.0 MHz Murata Erie CSA16.00MX  0.5% PIC16C62/62A/R62/63/R63/64/ All resonators used did not have built-in capacitors. 64A/R64/65/65A/R65/66/67 TABLE 13-2: CERAMIC RESONATORS PIC16C62/62A/R62/63/R63/64/ Cap. Crystal Cap. Range 64A/R64/65/65A/R65/66/67 Osc Type Freq C1 Range C2 Ranges Tested: LP 32 kHz 33 pF 33 pF Mode Freq OSC1 OSC2 200 kHz 15 pF 15 pF XT 455 kHz 68 - 100 pF 68 - 100 pF XT 200 kHz 47-68 pF 47-68 pF 2.0 MHz 15 - 68 pF 15 - 68 pF 1 MHz 15 pF 15 pF 4.0 MHz 15 - 68 pF 15 - 68 pF 4 MHz 15 pF 15 pF HS 8.0 MHz 10 - 68 pF 10 - 68 pF HS 4 MHz 15 pF 15 pF 16.0 MHz 10 - 22 pF 10 - 22 pF 8 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes at bottom of page. 20 MHz 15-33 pF 15-33 pF Resonators Used: These values are for design guidance only. See notes at bottom of page. 455 kHz Panasonic EFO-A455K04B  0.3% Crystals Used 2.0 MHz Murata Erie CSA2.00MG  0.5% 32 kHz Epson C-001R32.768K-A ± 20 PPM 4.0 MHz Murata Erie CSA4.00MG  0.5% 200 kHz STD XTL 200.000KHz ± 20 PPM 8.0 MHz Murata Erie CSA8.00MT  0.5% 1 MHz ECS ECS-10-13-1 ± 50 PPM 16.0 MHz Murata Erie CSA16.00MX  0.5% 4 MHz ECS ECS-40-20-1 ± 50 PPM All resonators used did not have built-in capacitors. 8 MHz EPSON CA-301 8.000M-C ± 30 PPM 20 MHz EPSON CA-301 20.000M-C ± 30 PPM Note1: Recommended values of C1 and C2 are identical to the ranges tested Table13-1 and Table13-2. 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal man- ufacturer for appropriate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level speci- fication. DS30234E-page 126  1997-2013 Microchip Technology Inc.

PIC16C6X 13.2.3 EXTERNAL CRYSTAL OSCILLATOR 13.2.4 RC OSCILLATOR CIRCUIT For timing insensitive applications the RC device option Either a prepackaged oscillator can be used or a simple offers additional cost savings. The RC oscillator fre- oscillator circuit with TTL gates can be built. Prepack- quency is a function of the supply voltage, the resistor aged oscillators provide a wide operating range and (Rext) and capacitor (Cext) values, and the operating better stability. A well-designed crystal oscillator will temperature. In addition to this, the oscillator frequency provide good performance with TTL gates. Two types of will vary from unit to unit due to normal process param- crystal oscillator circuits can be used; one with series eter variation. Furthermore, the difference in lead frame resonance, or one with parallel resonance. capacitance between package types will also affect the oscillation frequency, especially for low Cext values. Figure13-6 shows implementation of a parallel reso- The user also needs to take into account variation due nant oscillator circuit. The circuit is designed to use the to tolerance of external R and C components used. fundamental frequency of the crystal. The 74AS04 Figure13-8 shows how the RC combination is con- inverter performs the 180-degree phase shift that a par- nected to the PIC16CXX. For Rext values below allel oscillator requires. The 4.7 k resistor provides 2.2k, the oscillator operation may become unstable the negative feedback for stability. The 10 k potenti- or stop completely. For very high Rext values (e.g. ometer biases the 74AS04 in the linear region. This 1M), the oscillator becomes sensitive to noise, could be used for external oscillator designs. humidity and leakage. Thus, we recommend keeping FIGURE 13-6: EXTERNAL PARALLEL Rext between 3 k and 100 k. RESONANT CRYSTAL Although the oscillator will operate with no external OSCILLATOR CIRCUIT capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or +5V To Other small external capacitance, the oscillation frequency Devices can vary dramatically due to changes in external 10k capacitances, such as PCB trace capacitance or pack- 4.7k 74AS04 PIC16CXX age lead frame capacitance. 74AS04 CLKIN See characterization data for desired device for RC fre- quency variation from part to part due to normal pro- cess variation. The variation is larger for larger R (since 10k leakage current variation will affect RC frequency more XTAL for large R) and for smaller C (since variation of input 10k capacitance will affect RC frequency more). See characterization data for desired device for varia- 20 pF 20 pF tion of oscillator frequency due to VDD for given Rext/ Cext values as well as frequency variation due to oper- Figure13-7 shows a series resonant oscillator circuit. ating temperature for given R, C, and VDD values. This circuit is also designed to use the fundamental fre- The oscillator frequency, divided by 4, is available on quency of the crystal. The inverter performs a 180- the OSC2/CLKOUT pin, and can be used for test pur- degree phase shift in a series resonant oscillator cir- poses or to synchronize other logic (see Figure3-5 for cuit. The 330 k resistors provide the negative feed- waveform). back to bias the inverters in their linear region. FIGURE 13-8: RC OSCILLATOR MODE FIGURE 13-7: EXTERNAL SERIES RESONANT CRYSTAL VDD OSCILLATOR CIRCUIT Rext Internal To Other OSC1 330 k 330 k Devices clock 74AS04 74AS04 74AS04 PIC16CXX Cext PIC16CXX CLKIN VSS 0.1F OSC2/CLKOUT Fosc/4 XTAL  1997-2013 Microchip Technology Inc. DS30234E-page 127

PIC16C6X 13.3 Reset The TO and PD bits are set or cleared differently in dif- ferent reset situations as indicated in Table13-7, Applicable Devices Table13-8, and Table13-9. These bits are used in soft- 616262AR6263R636464AR646565AR656667 ware to determine the nature of the reset. See The PIC16CXX differentiates between various kinds of Table13-12 for a full description of reset states of all reset: registers. (cid:129) Power-on Reset (POR) A simplified block diagram of the on-chip reset circuit is (cid:129) MCLR reset during normal operation shown in Figure13-9. (cid:129) MCLR reset during SLEEP On the PIC16C62A/R62/63/R63/64A/R64/65A/R65/ (cid:129) WDT Reset (normal operation) 66/67, the MCLR reset path has a noise filter to detect (cid:129) Brown-out Reset (BOR) - Not on PIC16C61/62/ and ignore small pulses. See parameter #34 for pulse 64/65 width specifications. Some registers are not affected in any reset condition, It should be noted that a WDT Reset does not drive the their status is unknown on POR and unchanged in any MCLR pin low. other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on MCLR or WDT Reset, on MCLR reset during SLEEP, and on Brown- out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. FIGURE 13-9: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/VPP pin SLEEP WDT Module WDT Time-out VDD rise detect Power-on Reset VDD pin (2) Brown-out Reset BODEN S OST/PWRT OST Chip Reset 10-bit Ripple counter R Q OSC1/ CLKIN pin (1) PWRT On-chip RC OSC 10-bit Ripple counter Enable PWRT (3) Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: Brown-out Reset is NOT implemented on the PIC16C61/62/64/65. 3: See Table13-5 and Table13-6 for time-out situations. DS30234E-page 128  1997-2013 Microchip Technology Inc.

PIC16C6X 13.4 Power-on Reset (POR), Power-up The power-up time delay will vary from chip to chip due Timer (PWRT), Oscillator Start-up to VDD, temperature, and process variation. See DC Timer (OST) and Brown-out Reset parameters for details. (BOR) 13.4.3 OSCILLATOR START-UP TIMER (OST) Applicable Devices 616262AR6263R636464AR646565AR656667 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the 13.4.1 POWER-ON RESET (POR) PWRT delay is over. This ensures the crystal oscillator or resonator has started and stabilized. A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To The OST time-out is invoked only for XT, LP and HS take advantage of the POR, just tie the MCLR/VPP pin modes and only on Power-on Reset or wake-up from directly (or through a resistor) to VDD. This will elimi- SLEEP. nate external RC components usually needed to create 13.4.4 BROWN-OUT RESET (BOR) a Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details. Applicable Devices 616262AR6263R636464AR646565AR656667 When the device starts normal operation (exits the reset condition), device operating parameters (voltage, A configuration bit, BODEN, can disable (if clear/pro- frequency, temperature, ...) must be met to ensure grammed) or enable (if set) the Brown-out Reset cir- operation. If these conditions are not met, the device cuitry. If VDD falls below 4.0V (parameter D005 in must be held in reset until the operating conditions are Electrical Specification section) for greater than param- met. Brown-out Reset may be used to meet the startup eter #34 (see Electrical Specification section), the conditions. brown-out situation will reset the chip. A reset may not occur if VDD falls below 4.0V for less than parameter For additional information, refer to Application Note #34. The chip will remain in Brown-out Reset until VDD AN607, “Power-up Trouble Shooting.” rises above BVDD. The Power-up Timer will now be invoked and will keep the chip in RESET an additional 13.4.2 POWER-UP TIMER (PWRT) 72 ms. If VDD drops below BVDD while the Power-up The Power-up Timer provides a fixed 72 ms nominal Timer is running, the chip will go back into a Brown-out time-out on power-up only, from POR. The Power-up Reset and the Power-up Timer will be initialized. Once Timer operates on an internal RC oscillator. The chip is VDD rises above BVDD, the Power-up Timer will exe- kept in reset as long as PWRT is active. The PWRT’s cute a 72 ms time delay. The Power-up Timer should time delay allows VDD to rise to an acceptable level. A always be enabled when Brown-out Reset is enabled. configuration bit is provided to enable/disable the Figure13-10 shows typical brown-out situations. PWRT. FIGURE 13-10:BROWN-OUT SITUATIONS VDD BVDD Max. BVDD Min. Internal 72 ms Reset VDD BVDD Max. BVDD Min. Internal <72 ms Reset 72 ms VDD BVDD Max. BVDD Min. Internal 72 ms Reset  1997-2013 Microchip Technology Inc. DS30234E-page 129

PIC16C6X 13.4.5 TIME-OUT SEQUENCE 13.4.6 POWER CONTROL/STATUS REGISTER (PCON) On power-up the time-out sequence is as follows: First Applicable Devices a PWRT time-out is invoked after the POR time delay 616262AR6263R636464AR646565AR656667 has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the sta- The Power Control/Status Register, PCON has up to tus of the PWRT. For example, in RC mode, with the two bits, depending upon the device. Bit0 is not imple- PWRT disabled, there will be no time-out at all. mented on the PIC16C62/64/65. Figure13-11, Figure13-12, and Figure13-13 depict Bit0 is BOR (Brown-out Reset Status bit). BOR is time-out sequences on power-up. unknown on Power-on Reset. It must then be set by the Since the time-outs occur from the POR pulse, if the user and checked on subsequent resets to see if BOR MCLR/VPP pin is kept low long enough, the time-outs cleared, indicating that a brown-out has occurred. The will expire. Then bringing the MCLR/VPP pin high will BOR status bit is a “Don’t Care” and is not necessarily begin execution immediately (Figure13-14). This is predictable if the Brown-out Reset circuitry is disabled useful for testing purposes or to synchronize more than (by clearing bit BODEN in the Configuration Word). one PIC16CXX device operating in parallel. Bit1 is POR (Power-on Reset Status bit). It is cleared on Table13-10 and Table13-11 show the reset conditions a Power-on Reset and unaffected otherwise. The user for some special function registers, while Table13-12 must set this bit following a Power-on Reset. shows the reset conditions for all the registers. TABLE 13-5: TIME-OUT IN VARIOUS SITUATIONS, PIC16C61/62/64/65 Oscillator Configuration Power-up Wake-up from SLEEP PWRTE = 1 PWRTE = 0 XT, HS, LP 72 ms + 1024TOSC 1024TOSC 1024 TOSC RC 72 ms — — TABLE 13-6: TIME-OUT IN VARIOUS SITUATIONS, PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67 Power-up Wake up from Oscillator Configuration Brown-out PWRTE = 0 PWRTE = 1 SLEEP XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024 TOSC RC 72 ms — 72 ms — TABLE 13-7: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C61 TO PD 1 1 Power-on Reset or MCLR reset during normal operation 0 1 WDT Reset 0 0 WDT Wake-up 1 0 MCLR reset during SLEEP or interrupt wake-up from SLEEP TABLE 13-8: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C62/64/65 POR TO PD 0 1 1 Power-on Reset 0 0 x Illegal, TO is set on a Power-on Reset 0 x 0 Illegal, PD is set on a Power-on Reset 1 0 1 WDT Reset 1 0 0 WDT Wake-up 1 u u MCLR reset during normal operation 1 1 0 MCLR reset during SLEEP or interrupt wake-up from SLEEP Legend:x = unknown, u = unchanged DS30234E-page 130  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 13-9: STATUS BITS AND THEIR SIGNIFICANCE FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67 POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on a Power-on Reset 0 x x 0 Illegal, PD is set on a Power-on Reset 1 0 x x Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR reset during normal operation 1 1 1 0 MCLR reset during SLEEP or interrupt wake-up from SLEEP Legend:x = unknown, u = unchanged TABLE 13-10: RESET CONDITION FOR SPECIAL REGISTERS ON PIC16C61/62/64/65 Program Counter STATUS PCON(2) Power-on Reset 000h 0001 1xxx ---- --0- MCLR reset during normal operation 000h 000u uuuu ---- --u- MCLR reset during SLEEP 000h 0001 0uuu ---- --u- WDT Reset 000h 0000 1uuu ---- --u- WDT Wake-up PC + 1 uuu0 0uuu ---- --u- Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --u- Legend:u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note1: When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the inter- rupt vector (0004h) after execution of PC+1. 2: The PCON register is not implemented on the PIC16C61. TABLE 13-11: RESET CONDITION FOR SPECIAL REGISTERS ON PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67 Program Counter STATUS PCON Power-on Reset 000h 0001 1xxx ---- --0x MCLR reset during normal operation 000h 000u uuuu ---- --uu MCLR reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu Legend:u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.  1997-2013 Microchip Technology Inc. DS30234E-page 131

PIC16C6X TABLE 13-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset MCLR Reset during: Wake-up via Brown-out – normal operation interrupt or Reset – SLEEP WDT Wake-up WDT Reset W 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu INDF 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 N/A N/A N/A TMR0 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu PCL 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000h 0000h PC + 1(2) STATUS 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---x xxxx ---u uuuu ---u uuuu PORTA 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 --xx xxxx --uu uuuu --uu uuuu PORTB 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu PORTE 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---- -xxx ---- -uuu ---- -uuu PCLATH 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---0 0000 ---0 0000 ---u uuuu INTCON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 000x 0000 000u uuuu uuuu(1) PIR1 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 00-- 0000 00-- 0000 uu-- uuuu(1) 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu(1) PIR2 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---- ---0 ---- ---0 ---- ---u(2) TMR1L 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 --00 0000 --uu uuuu --uu uuuu TMR2 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu T2CON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 -000 0000 -000 0000 -uuu uuuu SSPBUF 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu CCPR1L 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 --00 0000 --00 0000 --uu uuuu RCSTA 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 -00x 0000 -00x uuuu -uuu TXREG 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu RCREG 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu CCPR2L 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu OPTION 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 1111 1111 1111 1111 uuuu uuuu 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---1 1111 ---1 1111 ---u uuuu TRISA 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 --11 1111 --11 1111 --uu uuuu TRISB 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 1111 1111 1111 1111 uuuu uuuu TRISC 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 1111 1111 1111 1111 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 3: See Table13-10 and Table13-11 for reset value for specific conditions. DS30234E-page 132  1997-2013 Microchip Technology Inc.

PIC16C6X TABLE 13-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d) Register Applicable Devices Power-on Reset MCLR Reset during: Wake-up via Brown-out – normal operation interrupt or Reset – SLEEP WDT Wake-up WDT Reset TRISD 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 1111 1111 1111 1111 uuuu uuuu TRISE 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 -111 0000 -111 uuuu -uuu PIE1 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 00-- 0000 00-- 0000 uu-- uuuu 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu PIE2 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---- ---0 ---- ---0 ---- ---u 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---- --0u ---- --uu ---- --uu PCON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 ---- --0- ---- --u- ---- --u- PR2 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 1111 1111 1111 1111 1111 1111 SSPADD 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu SSPSTAT 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 --00 0000 --00 0000 --uu uuuu TXSTA 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 -010 0000 -010 uuuu -uuu SPBRG 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition. Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 3: See Table13-10 and Table13-11 for reset value for specific conditions.  1997-2013 Microchip Technology Inc. DS30234E-page 133

PIC16C6X FIGURE 13-11:TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 13-12:TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 13-13:TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30234E-page 134  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 13-14:EXTERNAL POWER-ON FIGURE 13-15:EXTERNAL BROWN-OUT RESET CIRCUIT (FOR SLOW PROTECTION CIRCUIT 1 VDD POWER-UP) VDD VDD VDD 33k D R 10k MCLR R1 MCLR 40k PIC16CXX C PIC16CXX Note1: External Power-on Reset circuit is required Note1: This circuit will activate reset when VDD only if VDD power-up slope is too slow. The goes below (Vz + 0.7V) where Vz = Zener diode D helps discharge the capacitor voltage. quickly when VDD powers down. 2: Internal brown-out detection on the 2: R < 40 k is recommended to make sure PIC16C62A/R62/63/R63/64A/R64/65A/ that voltage drop across R does not violate R65/66/67 should be disabled when using the devices electrical specifications. this circuit. 3: R1 = 100 to 1 k will limit any current 3: Resistors should be adjusted for the flowing into MCLR from external capacitor characteristics of the transistors. C in the event of MCLR/VPP pin break- down due to Electrostatic Discharge (ESD) or Electrostatic Overstress (EOS). FIGURE 13-16:EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD R1 Q1 MCLR R2 40k PIC16CXX Note1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 VDD (cid:129) = 0.7V R1 + R2 2: Internal brown-out detection on the PIC16C62A/R62/63/R63/64A/R64/65A/ R65/66/67 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistors.  1997-2013 Microchip Technology Inc. DS30234E-page 135

PIC16C6X 13.5 Interrupts avoid infinite interrupt requests. Individual interrupt flag bits are set regardless of the status of their correspond- Applicable Devices ing mask bit or the GIE bit. 616262AR6263R636464AR646565AR656667 The PIC16C6X family has up to 11 sources of interrupt. Note: For the PIC16C61/62/64/65, if an interrupt The interrupt control register (INTCON) records individ- occurs while the Global Interrupt Enable ual interrupt requests in flag bits. It also has individual bit, GIE is being cleared, bit GIE may unin- and global interrupt enable bits. tentionally be re-enabled by the user’s Interrupt Service Routine (the RETFIE Note: Individual interrupt flag bits are set regard- instruction). The events that would cause less of the status of their corresponding this to occur are: mask bit or global enable bit, GIE. 1. An instruction clears the GIE bit while Global interrupt enable bit, GIE (INTCON<7>) enables an interrupt is acknowledged (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt 2. The program branches to the Interrupt flag bit and mask bit are set, the interrupt will vector vector and executes the Interrupt Ser- immediately. Individual interrupts can be disabled vice Routine. through their corresponding enable bits in the INTCON 3. The Interrupt Service Routine com- register. GIE is cleared on reset. pletes with the execution of the RET- The “return from interrupt” instruction, RETFIE, exits FIE instruction. This causes the GIE the interrupt routine as well as sets the GIE bit, which bit to be set (enables interrupts), and re-enable interrupts. the program returns to the instruction after the one which was meant to dis- The RB0/INT pin interrupt, the RB port change interrupt able interrupts. and the TMR0 overflow interrupt flag bits are contained in the INTCON register. 4. Perform the following to ensure that interrupts are globally disabled. The peripheral interrupt flag bits are contained in spe- cial function registers PIR1 and PIR2. The correspond- LOOP BCF INTCON,GIE ;Disable Global ;Interrupt bit ing interrupt enable bits are contained in special BTFSC INTCON,GIE ;Global Interrupt function registers PIE1 and PIE2 and the peripheral ;Disabled? interrupt enable bit is contained in special function reg- GOTO LOOP ;NO, try again ister INTCON. : ;Yes, continue When an interrupt is responded to, bit GIE is cleared to ;with program flow disable any further interrupts, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in soft- ware before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the RB0/INT pin or RB port change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure13- 19). The latency is the same for one or two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to DS30234E-page 136  1997-2013 Microchip Technology Inc.

PIC16C6X FIGURE 13-17:INTERRUPT LOGIC FOR PIC16C61 Wake-up T0IF (If in SLEEP mode) T0IE INTF INTE Interrupt to CPU RBIF RBIE GIE FIGURE 13-18:INTERRUPT LOGIC FOR PIC16C6X PSPIF PSPIE RCIF T0IF Wake-up (If in SLEEP mode) RCIE T0IE TXIF INTF TXIE INTE Interrupt to CPU SSPIF RBIF SSPIE RBIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF PIC16C62 Yes Yes Yes - - - Yes Yes Yes Yes - PIC16C62A Yes Yes Yes - - - Yes Yes Yes Yes - PIC16CR62 Yes Yes Yes - - - Yes Yes Yes Yes - PIC16C63 Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes PIC16CR63 Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes PIC16C64 Yes Yes Yes Yes - - Yes Yes Yes Yes - PIC16C64A Yes Yes Yes Yes - - Yes Yes Yes Yes - PIC16C64 Yes Yes Yes Yes - - Yes Yes Yes Yes - PIC16C65 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PIC16C65A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PIC16CR65 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PIC16C66 Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes PIC16C67 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes  1997-2013 Microchip Technology Inc. DS30234E-page 137

PIC16C6X 13.5.1 INT INTERRUPT 13.5.2 TMR0 INTERRUPT External interrupt on RB0/INT pin is edge triggered: An overflow (FFh  00h) in the TMR0 register will set either rising if edge select bit INTEDG (OPTION<6>) is flag bit T0IF (INTCON<2>). The interrupt can be set, or falling, if bit INTEDG is clear. When a valid edge enabled/disabled by setting/clearing enable bit T0IE appears on the RB0/INT pin, flag bit INTF (INTCON<5>) (Section7.0). (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). The INTF bit 13.5.3 PORTB INTERRUPT ON CHANGE must be cleared in software in the interrupt service rou- An input change on PORTB<7:4> sets flag bit RBIF tine before re-enabling this interrupt. The INT interrupt (INTCON<0>). The interrupt can be enabled/disabled can wake the processor from SLEEP, if enable bit INTE by setting/clearing enable bit RBIE (INTCON<4>) was set prior to going into SLEEP. The status of global (Section5.2). enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Note: For the PIC16C61/62/64/65, if a change on Section13.8 for details on SLEEP mode. the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then flag bit RBIF may not get set. FIGURE 13-19:INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) 4 INT pin 1 1 INTF flag 5 Interrupt Latency (2) (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 PC+1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h) Ienxsetcruuctetidon Inst (PC-1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3TCY for synchronous interrupt and 3-4TCY for asynchronous interrupt. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width spec of INT pulse, refer to AC specs. 5: INTF can to be set anytime during the Q4-Q1 cycles. DS30234E-page 138  1997-2013 Microchip Technology Inc.

PIC16C6X 13.6 Context Saving During Interrupts defined in all banks and must be defined at the same offset from the bank base address (i.e., if W_TEMP is Applicable Devices defined at 0x20 in bank 0, it must also be defined at 616262AR6263R636464AR646565AR656667 0xA0 in bank 1, 0x120 in bank 2, and 0x1A0 in bank 3). During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key reg- The examples: isters during an interrupt i.e., W register and STATUS a) Stores the W register register. This will have to be implemented in software. b) Stores the STATUS register in bank 0 Example13-1 stores and restores the STATUS and W c) Stores PCLATH registers. Example13-2 stores and restores the d) Executes ISR code STATUS, W, and PCLATH registers (Devices with e) Restores PCLATH paged program memory). For all PIC16C6X devices f) Restores STATUS register (and bank select bit) with greater than 1K of program memory (all devices except PIC16C61), the register, W_TEMP, must be g) Restores W register EXAMPLE 13-1: SAVING STATUS AND W REGISTERS IN RAM (PIC16C61) MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W EXAMPLE 13-2: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM (ALL OTHER PIC16C6X DEVICES) MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page BCF STATUS, IRP ;Return to Bank 0 MOVF FSR, W ;Copy FSR to W MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP :(ISR) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W  1997-2013 Microchip Technology Inc. DS30234E-page 139

PIC16C6X 13.7 Watchdog Timer (WDT) assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to Applicable Devices 2.3 seconds can be realized. 616262AR6263R636464AR646565AR656667 The Watchdog Timer is a free running on-chip RC oscil- The CLRWDT and SLEEP instructions clear the WDT lator which does not require any external components. and the postscaler, if assigned to the WDT, and prevent This RC oscillator is separate from the RC oscillator of it from timing out and generating a device RESET con- the OSC1/CLKIN pin. That means that the WDT will dition. run, even if the clock on the OSC1/CLKIN and OSC2/ The TO bit in the STATUS register will be cleared upon CLKOUT pins of the device has been stopped, for a WDT time-out. example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device 13.7.2 WDT PROGRAMMING CONSIDERATIONS reset. If the device is in SLEEP mode, a WDT time-out It should also be taken in account that under worst case causes the device to wake-up and continue with normal operation (WDT Wake-up). The WDT can be perma- conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a nently disabled by clearing configuration bit WDTE WDT time-out occurs. (Section13.1). Note: When a CLRWDT instruction is executed 13.7.1 WDT PERIOD and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the The WDT has a nominal time-out period of 18 ms, (with prescaler assignment is not changed. no prescaler). The time-out periods vary with tempera- ture, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be FIGURE 13-20:WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (see Figure7-6) 0 M Postscaler Watchdog U Timer 1 X 8 8- to -1 MUX PS2:PS0 PSA WDT Enable bit To TMR0 (Figure7-6) 0 1 MUX PSA WDT Time-out Note: Bits T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>). FIGURE 13-21:SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend:Shaded cells are not used by the Watchdog Timer. Note1: See Figure13-1, Figure13-2, and Figure13-3 for details of these bits for the specific device. DS30234E-page 140  1997-2013 Microchip Technology Inc.

PIC16C6X 13.8 Power-down Mode (SLEEP) Other peripherals can not generate interrupts since during SLEEP, no on-chip Q clocks are present. Applicable Devices 616262AR6263R636464AR646565AR656667 When the SLEEP instruction is being executed, the next Power-down mode is entered by executing a SLEEP instruction (PC + 1) is pre-fetched. For the device to instruction. wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is If enabled, the Watchdog Timer will be cleared but regardless of the state of the GIE bit. If the GIE bit is keeps running, status bit PD (STATUS<3>) is cleared, clear (disabled), the device continues execution at the status bit TO (STATUS<4>) is set, and the oscillator instruction after the SLEEP instruction. If the GIE bit is driver is turned off. The I/O ports maintain the status set (enabled), the device executes the instruction after they had before the SLEEP instruction was executed the SLEEP instruction and then branches to the inter- (driving high, low, or hi-impedance). rupt address (0004h). In cases where the execution of For lowest current consumption in this mode, place all the instruction following SLEEP is not desirable, the I/O pins at either VDD, or VSS, ensure no external cir- user should have a NOP after the SLEEP instruction. cuitry is drawing current from the I/O pin, and disable external clocks. Pull all I/O pins, that are hi-impedance 13.8.2 WAKE-UP USING INTERRUPTS inputs, high or low externally to avoid switching currents When global interrupts are disabled (GIE cleared) and caused by floating inputs. The T0CKI input should also any interrupt source has both its interrupt enable bit be at VDD or VSS for lowest current consumption. The and interrupt flag bit set, one of the following will occur: contribution from on-chip pull-ups on PORTB should be considered. (cid:129) If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will com- The MCLR/VPP pin must be at a logic high level plete as a NOP. Therefore, the WDT and WDT (VIHMC). postscaler will not be cleared, the TO bit will not 13.8.1 WAKE-UP FROM SLEEP be set and PD bits will not be cleared. (cid:129) If the interrupt occurs during or after the execu- The device can wake from SLEEP through one of the tion of a SLEEP instruction, the device will imme- following events: diately wake up from sleep. The SLEEP instruction 1. External reset input on MCLR/VPP pin. will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be 2. Watchdog Timer Wake-up (if WDT was cleared, the TO bit will be set and the PD bit will enabled). be cleared. 3. Interrupt from RB0/INT pin, RB port change, or some peripheral interrupts. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to External MCLR Reset will cause a device reset. All become set before the SLEEP instruction completes. To other events are considered a continuation of program determine whether a SLEEP instruction executed, test execution and cause a “wake-up”. The TO and PD bits the PD bit. If the PD bit is set, the SLEEP instruction in the STATUS register can be used to determine the was executed as a NOP. cause of device reset. The PD bit, which is set on power-up is cleared when SLEEP is invoked. The TO bit To ensure that the WDT is cleared, a CLRWDT instruc- is cleared if WDT time-out occurred (and caused wake- tion should be executed before a SLEEP instruction. up). The following peripheral interrupts can wake the device from SLEEP: 1. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 2. SSP (Start/Stop) bit detect interrupt. 3. SSP transmit or receive in slave mode (SPI/I2C). 4. CCP capture mode interrupt. 5. Parallel Slave Port read or write. 6. USART TX or RX (synchronous slave mode).  1997-2013 Microchip Technology Inc. DS30234E-page 141

PIC16C6X FIGURE 13-22:WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) G(INIET CbiOtN<7>) Processor in SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Ifentscthruecdtion Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Ienxsetcruuctetidon Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 13.9 Program Verification/Code Protection The device is placed into a program/verify mode by holding pins RB6 and RB7 low while raising the MCLR Applicable Devices (VPP) pin from VIL to VIHH (see programming specifica- 616262AR6263R636464AR646565AR656667 tion). RB6 becomes the programming clock and RB7 If the code protection bit(s) have not been pro- becomes the programming data. Both RB6 and RB7 grammed, the on-chip program memory can be read are Schmitt Trigger inputs in this mode. out for verification purposes. After reset, to place the device in program/verify mode, Note: Microchip does not recommend code pro- the program counter (PC) is at location 00h. A 6-bit tecting windowed devices. command is then supplied to the device. Depending on the command, 14-bits of program data are then sup- 13.10 ID Locations plied to or from the device, depending if the command Applicable Devices was a load or a read. For complete details of serial pro- 616262AR6263R636464AR646565AR656667 gramming, please refer to the PIC16C6X/7X Program- Four memory locations (2000h - 2003h) are designated ming Specifications (Literature #DS30228). as ID locations where the user can store checksum or FIGURE 13-23:TYPICAL IN-CIRCUIT SERIAL other code-identification numbers. These locations are PROGRAMMING not accessible during normal execution but are read- CONNECTION able and writable during program/verify. It is recom- mended that only the 4 least significant bits of the ID location are used. To Normal Connections External For ROM devices, these values are submitted along Connector PIC16CXX with the ROM code. Signals 13.11 In-Circuit Serial Programming +5V VDD 0V VSS Applicable Devices VPP MCLR/VPP 616262AR6263R636464AR646565AR656667 The PIC16CXX microcontrollers can be serially pro- CLK RB6 grammed while in the end application circuit. This is simply done with two lines for clock and data, and three Data I/O RB7 other lines for power, ground, and the programming voltage. This allows customers to manufacture boards VDD with unprogrammed devices, and then program the microcontroller just before shipping the product. This To Normal also allows the most recent firmware or a custom firm- Connections ware to be programmed. DS30234E-page 142  1997-2013 Microchip Technology Inc.

PIC16C6X 14.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped into three basic categories: Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type (cid:129) Byte-oriented operations and one or more operands which further specify the (cid:129) Bit-oriented operations operation of the instruction. The PIC16CXX instruction (cid:129) Literal and control operations set summary in Table14-2 lists byte-oriented, bit-ori- All instructions are executed within one single instruc- ented, and literal and control operations. Table14-1 tion cycle, unless a conditional test is true or the pro- shows the opcode field descriptions. gram counter is changed as a result of an instruction. For byte-oriented instructions, 'f' represents a file reg- In this case, the execution takes two instruction cycles ister designator and 'd' represents a destination desig- with the second cycle executed as a NOP. One instruc- nator. The file register designator specifies which file tion cycle consists of four oscillator periods. Thus, for register is to be used by the instruction. an oscillator frequency of 4 MHz, the normal instruction The destination designator specifies where the result of execution time is 1 s. If a conditional test is true or the the operation is to be placed. If 'd' is zero, the result is program counter is changed as a result of an instruc- placed in the W register. If 'd' is one, the result is placed tion, the instruction execution time is 2 s. in the file register specified in the instruction. Table14-2 lists the instructions recognized by the For bit-oriented instructions, 'b' represents a bit field MPASM assembler. designator which selects the number of the bit affected Figure14-1 shows the general formats that the instruc- by the operation, while 'f' represents the number of the tions can have. file in which the bit is located. Note: To maintain upward compatibility with For literal and control operations, 'k' represents an future PIC16CXX products, do not use the eight or eleven bit constant or literal value. OPTION and TRIS instructions. TABLE 14-1: OPCODE FIELD All examples use the following format to represent a DESCRIPTIONS hexadecimal number: 0xhh Field Description where h signifies a hexadecimal digit. f Register file address (0x00 to 0x7F) W Working register (accumulator) FIGURE 14-1: GENERAL FORMAT FOR b Bit address within an 8-bit file register INSTRUCTIONS k Literal field, constant data or label Byte-oriented file register operations x Don't care location (= 0 or 1) 13 8 7 6 0 The assembler will generate code with x = 0. It is the OPCODE d f (FILE #) recommended form of use for compatibility with all Microchip software tools. d = 0 for destination W d Destination select; d = 0: store result in W, d = 1 for destination f f = 7-bit file register address d = 1: store result in file register f. Default is d = 1 label Label name Bit-oriented file register operations 13 10 9 7 6 0 TOS Top of Stack OPCODE b (BIT #) f (FILE #) PC Program Counter PCLATH Program Counter High Latch b = 3-bit bit address GIE Global Interrupt Enable bit f = 7-bit file register address WDT Watchdog Timer/Counter TO Time-out bit Literal and control operations PD Power-down bit General dest Destination either the W register or the specified register file location 13 8 7 0 [ ] Options OPCODE k (literal) ( ) Contents k = 8-bit immediate value  Assigned to < > Register bit field CALL and GOTO instructions only  In the set of 13 11 10 0 italics User defined term (font is courier) OPCODE k (literal) k = 11-bit immediate value  1997-2013 Microchip Technology Inc. DS30234E-page 143

PIC16C6X TABLE 14-2: PIC16CXX INSTRUCTION SET Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS30234E-page 144  1997-2013 Microchip Technology Inc.

PIC16C6X 14.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [label] ADDLW k Syntax: [label] ANDLW k Operands: 0  k  255 Operands: 0  k  255 Operation: (W) + k  (W) Operation: (W) .AND. (k)  (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk Description: The contents of the W register are Description: The contents of W register are added to the eight bit literal 'k' and the AND’ed with the eight bit literal 'k'. The result is placed in the W register. result is placed in the W register. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to literal 'k' data W literal "k" data W Example: ADDLW 0x15 Example ANDLW 0x5F Before Instruction Before Instruction W = 0x10 W = 0xA3 After Instruction After Instruction W = 0x25 W = 0x03 ADDWF Add W and f ANDWF AND W with f Syntax: [label] ADDWF f,d Syntax: [label] ANDWF f,d Operands: 0  f  127 Operands: 0  f  127 d  d  Operation: (W) + (f)  (destination) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Encoding: 00 0111 dfff ffff Encoding: 00 0101 dfff ffff Description: Add the contents of the W register with Description: AND the W register with register 'f'. If 'd' register 'f'. If 'd' is 0 the result is stored is 0 the result is stored in the W regis- in the W register. If 'd' is 1 the result is ter. If 'd' is 1 the result is stored back in stored back in register 'f'. register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register data destination register data destination 'f' 'f' Example ADDWF FSR, 0 Example ANDWF FSR, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 FSR= 0xC2 FSR= 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 FSR= 0xC2 FSR= 0x02  1997-2013 Microchip Technology Inc. DS30234E-page 145

PIC16C6X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [label] BCF f,b Syntax: [label] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff Description: Bit 'b' in register 'f' is cleared. Description: If bit 'b' in register 'f' is '1' then the next instruction is executed. Words: 1 If bit 'b', in register 'f', is '0' then the next Cycles: 1 instruction is discarded, and a NOP is Q Cycle Activity: Q1 Q2 Q3 Q4 executed instead, making this a 2TCY instruction. Decode Read Process Write register data register 'f' Words: 1 'f' Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Example BCF FLAG_REG, 7 Decode Read Process No- Before Instruction register 'f' data Operation FLAG_REG = 0xC7 After Instruction If Skip: (2nd Cycle) FLAG_REG = 0x47 Q1 Q2 Q3 Q4 No- No- No- No- Operation Operation Operation Operation Example HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE (cid:129) (cid:129) (cid:129) Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, BSF Bit Set f PC = address TRUE Syntax: [label] BSF f,b if FLAG<1>=1, PC = address FALSE Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Encoding: 01 01bb bfff ffff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write register data register 'f' 'f' Example BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A DS30234E-page 146  1997-2013 Microchip Technology Inc.

PIC16C6X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0  f  127 Operands: 0  k  2047 0  b < 7 Operation: (PC)+ 1 TOS, Operation: skip if (f<b>) = 1 k  PC<10:0>, Status Affected: None (PCLATH<4:3>)  PC<12:11> Encoding: 01 11bb bfff ffff Status Affected: None Description: If bit 'b' in register 'f' is '0' then the next Encoding: 10 0kkk kkkk kkkk instruction is executed. Description: Call Subroutine. First, return address If bit 'b' is '1', then the next instruction is (PC+1) is pushed onto the stack. The discarded and a NOP is executed eleven bit immediate address is loaded instead, making this a 2TCY instruction. into PC bits <10:0>. The upper bits of Words: 1 the PC are loaded from PCLATH. CALL is a two cycle instruction. Cycles: 1(2) Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 2 Decode Read Process No- register 'f' data Operation Q Cycle Activity: Q1 Q2 Q3 Q4 1st Cycle Decode Read Process Write to If Skip: (2nd Cycle) literal 'k', data PC Q1 Q2 Q3 Q4 Push PC to Stack No- No- No- No- 2nd Cycle No- No- No- No- Operation Operation Operation Operation Operation Operation Operation Operation Example HERE BTFSC FLAG,1 Example HERE CALL THERE FALSE GOTO PROCESS_CODE TRUE (cid:129) Before Instruction (cid:129) PC = Address HERE (cid:129) After Instruction Before Instruction PC = Address THERE TOS= Address HERE+1 PC = address HERE After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE  1997-2013 Microchip Technology Inc. DS30234E-page 147

PIC16C6X CLRF Clear f CLRW Clear W Syntax: [label] CLRF f Syntax: [ label ] CLRW Operands: 0  f  127 Operands: None Operation: 00h  (f) Operation: 00h  (W) 1  Z 1  Z Status Affected: Z Status Affected: Z Encoding: 00 0001 1fff ffff Encoding: 00 0001 0xxx xxxx Description: The contents of register 'f' are cleared Description: W register is cleared. Zero bit (Z) is and the Z bit is set. set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write Decode No- Process Write to register data register 'f' Operation data W 'f' Example CLRW Example CLRF FLAG_REG Before Instruction Before Instruction W = 0x5A FLAG_REG = 0x5A After Instruction After Instruction W = 0x00 FLAG_REG = 0x00 Z = 1 Z = 1 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h  WDT 0  WDT prescaler, 1  TO 1  PD Status Affected: TO, PD Encoding: 00 0000 0110 0100 Description: CLRWDT instruction resets the Watch- dog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No- Process Clear Operation data WDT Counter Example CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler= 0 TO = 1 PD = 1 DS30234E-page 148  1997-2013 Microchip Technology Inc.

PIC16C6X COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f)  (destination) Operation: (f) - 1  (destination); Status Affected: Z skip if result = 0 Encoding: 00 1001 dfff ffff Status Affected: None Description: The contents of register 'f' are comple- Encoding: 00 1011 dfff ffff mented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in Description: The contents of register 'f' are decre- register 'f'. mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed Words: 1 back in register 'f'. If the result is 1, the next instruction, is Cycles: 1 executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruc- Q Cycle Activity: Q1 Q2 Q3 Q4 tion. Decode Read Process Write to Words: 1 register data destination 'f' Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Example COMF REG1,0 Decode Read Process Write to Before Instruction register 'f' data destination REG1 = 0x13 If Skip: (2nd Cycle) After Instruction Q1 Q2 Q3 Q4 REG1 = 0x13 W = 0xEC No- No- No- No- Operation Operation Operation Operation DECF Decrement f Example HERE DECFSZ CNT, 1 Syntax: [label] DECF f,d GOTO LOOP Operands: 0  f  127 CONTINUE (cid:129) d  [0,1] (cid:129) (cid:129) Operation: (f) - 1  (destination) Before Instruction Status Affected: Z PC = address HERE After Instruction Encoding: 00 0011 dfff ffff CNT = CNT - 1 Description: Decrement register 'f'. If 'd' is 0 the if CNT= 0, r1e tshuelt riess sutolt riesd s itno rtehde bWa crek ginis treerg. iIsft e'dr' 'ifs'. PC = address CONTINUE if CNT 0, Words: 1 PC = address HERE+1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register data destination 'f' Example DECF CNT, 1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1  1997-2013 Microchip Technology Inc. DS30234E-page 149

PIC16C6X GOTO Unconditional Branch INCF Increment f Syntax: [ label ] GOTO k Syntax: [ label ] INCF f,d Operands: 0  k  2047 Operands: 0  f  127 d  [0,1] Operation: k  PC<10:0> PCLATH<4:3>  PC<12:11> Operation: (f) + 1  (destination) Status Affected: None Status Affected: Z Encoding: 10 1kkk kkkk kkkk Encoding: 00 1010 dfff ffff Description: GOTO is an unconditional branch. The Description: The contents of register 'f' are incre- eleven bit immediate value is loaded mented. If 'd' is 0 the result is placed in into PC bits <10:0>. The upper bits of the W register. If 'd' is 1 the result is PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction. placed back in register 'f'. Words: 1 Words: 1 Cycles: 2 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 1st Cycle Decode Read Process Write to Decode Read Process Write to literal 'k' data PC register data destination 'f' 2nd Cycle No- No- No- No- Operation Operation Operation Operation Example INCF CNT, 1 Example GOTO THERE Before Instruction CNT = 0xFF After Instruction Z = 0 PC = Address THERE After Instruction CNT = 0x00 Z = 1 DS30234E-page 150  1997-2013 Microchip Technology Inc.

PIC16C6X INCFSZ Increment f, Skip if 0 IORLW Inclusive OR Literal with W Syntax: [ label ] INCFSZ f,d Syntax: [ label ] IORLW k Operands: 0  f  127 Operands: 0  k  255 d  [0,1] Operation: (W) .OR. k  (W) Operation: (f) + 1  (destination), Status Affected: Z skip if result = 0 Encoding: 11 1000 kkkk kkkk Status Affected: None Description: The contents of the W register is Encoding: 00 1111 dfff ffff OR’ed with the eight bit literal 'k'. The Description: The contents of register 'f' are incre- result is placed in the W register. mented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is Words: 1 placed back in register 'f'. Cycles: 1 If the result is 1, the next instruction is executed. If the result is 0, a NOP is exe- cuted instead making it a 2TCY instruc- Q Cycle Activity: Q1 Q2 Q3 Q4 tion. Decode Read Process Write to Words: 1 literal 'k' data W Cycles: 1(2) Example IORLW 0x35 Q Cycle Activity: Q1 Q2 Q3 Q4 Before Instruction Decode Read Process Write to W = 0x9A register 'f' data destination After Instruction If Skip: (2nd Cycle) W = 0xBF Z = 1 Q1 Q2 Q3 Q4 No- No- No- No- Operation Operation Operation Operation Example HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE (cid:129) (cid:129) (cid:129) Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT 0, PC = address HERE +1  1997-2013 Microchip Technology Inc. DS30234E-page 151

PIC16C6X IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVLW k Operands: 0  f  127 Operands: 0  k  255 d  [0,1] Operation: k  (W) Operation: (W) .OR. (f)  (destination) Status Affected: None Status Affected: Z Encoding: 11 00xx kkkk kkkk Encoding: 00 0100 dfff ffff Description: The eight bit literal 'k' is loaded into W Description: Inclusive OR the W register with regis- register. The don’t cares will assemble ter 'f'. If 'd' is 0 the result is placed in the as 0’s. W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to literal 'k' data W Decode Read Process Write to register data destination 'f' Example MOVLW 0x5A After Instruction Example IORWF RESULT, 0 W = 0x5A Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 Z = 1 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: (W)  (f) Operation: (f)  (destination) Status Affected: None Status Affected: Z Encoding: 00 0000 1fff ffff Encoding: 00 1000 dfff ffff Description: Move data from W register to register Description: The contents of register f is moved to a 'f'. destination dependant upon the status Words: 1 of d. If d = 0, destination is W register. If d = 1, the destination is file register f Cycles: 1 itself. d = 1 is useful to test a file regis- Q Cycle Activity: Q1 Q2 Q3 Q4 ter since status flag Z is affected. Decode Read Process Write Words: 1 register data register 'f' Cycles: 1 'f' Q Cycle Activity: Q1 Q2 Q3 Q4 Example MOVWF OPTION_REG Decode Read Process Write to register data destination Before Instruction 'f' OPTION = 0xFF W = 0x4F After Instruction Example MOVF FSR, 0 OPTION = 0x4F After Instruction W = 0x4F W = value in FSR register Z = 1 DS30234E-page 152  1997-2013 Microchip Technology Inc.

PIC16C6X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] NOP Syntax: [ label ] RETFIE Operands: None Operands: None Operation: No operation Operation: TOS  PC, 1  GIE Status Affected: None Status Affected: None Encoding: 00 0000 0xx0 0000 Encoding: 00 0000 0000 1001 Description: No operation. Description: Return from Interrupt. Stack is POPed Words: 1 and Top of Stack (TOS) is loaded in the Cycles: 1 PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE Q Cycle Activity: Q1 Q2 Q3 Q4 (INTCON<7>). This is a two cycle Decode No- No- No- instruction. Operation Operation Operation Words: 1 Example NOP Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 1st Cycle Decode No- Set the Pop from Operation GIE bit the Stack 2nd Cycle No- No- No- No- Operation Operation Operation Operation Example RETFIE After Interrupt PC = TOS GIE = 1 OPTION Load Option Register Syntax: [ label ] OPTION Operands: None Operation: (W)  OPTION Status Affected: None Encoding: 00 0000 0110 0010 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code com- patibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction.  1997-2013 Microchip Technology Inc. DS30234E-page 153

PIC16C6X RETLW Return with Literal in W RETURN Return from Subroutine Syntax: [ label ] RETLW k Syntax: [ label ] RETURN Operands: 0  k  255 Operands: None Operation: k  (W); Operation: TOS  PC TOS  PC Status Affected: None Status Affected: None Encoding: 00 0000 0000 1000 Encoding: 11 01xx kkkk kkkk Description: Return from subroutine. The stack is Description: The W register is loaded with the eight POPed and the top of the stack (TOS) bit literal 'k'. The program counter is is loaded into the program counter. This loaded from the top of the stack (the is a two cycle instruction. return address). This is a two cycle Words: 1 instruction. Cycles: 2 Words: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Cycles: 2 1st Cycle Decode No- No- Pop from Q Cycle Activity: Q1 Q2 Q3 Q4 Operation Operation the Stack 1st Cycle Decode Read No- Write to 2nd Cycle No- No- No- No- literal 'k' Operation W, Pop Operation Operation Operation Operation from the Stack Example RETURN 2nd Cycle No- No- No- No- Operation Operation Operation Operation After Interrupt PC = TOS Example CALL TABLE ;W contains table ;offset value (cid:129) ;W now has table value (cid:129) (cid:129) TABLE ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; (cid:129) (cid:129) (cid:129) RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 DS30234E-page 154  1997-2013 Microchip Technology Inc.

PIC16C6X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: 00 1101 dfff ffff Encoding: 00 1100 dfff ffff Description: The contents of register 'f' are rotated Description: The contents of register 'f' are rotated one bit to the left through the Carry one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored W register. If 'd' is 1 the result is placed back in register 'f'. back in register 'f'. C Register f C Register f Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to Decode Read Process Write to register data destination register data destination 'f' 'f' Example RLF REG1,0 Example RRF REG1,0 Before Instruction Before Instruction REG1 = 1110 0110 REG1 = 1110 0110 C = 0 C = 0 After Instruction After Instruction REG1 = 1110 0110 REG1 = 1110 0110 W = 1100 1100 W = 0111 0011 C = 1 C = 0  1997-2013 Microchip Technology Inc. DS30234E-page 155

PIC16C6X SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SLEEP Syntax: [ label ] SUBLW k Operands: None Operands: 0 k 255 Operation: 00h  WDT, Operation: k - (W) W) 0  WDT prescaler, Status Affected: C, DC, Z 1  TO, Encoding: 11 110x kkkk kkkk 0  PD Description: The W register is subtracted (2’s comple- Status Affected: TO, PD ment method) from the eight bit literal 'k'. Encoding: 00 0000 0110 0011 The result is placed in the W register. Description: The power-down status bit, PD is Words: 1 cleared. Time-out status bit, TO is Cycles: 1 set. Watchdog Timer and its pres- caler are cleared. Q Cycle Activity: Q1 Q2 Q3 Q4 The processor is put into SLEEP Decode Read Process Write to W mode with the oscillator stopped. See literal 'k' data Section13.8 for more details. Words: 1 Example 1: SUBLW 0x02 Cycles: 1 Before Instruction Q Cycle Activity: Q1 Q2 Q3 Q4 W = 1 Decode No- No- Go to C = ? Operation Operation Sleep Z = ? After Instruction Example: SLEEP W = 1 C = 1; result is positive Z = 0 Example 2: Before Instruction W = 2 C = ? Z = ? After Instruction W = 0 C = 1; result is zero Z = 1 Example 3: Before Instruction W = 3 C = ? Z = ? After Instruction W = 0xFF C = 0; result is negative Z = 0 DS30234E-page 156  1997-2013 Microchip Technology Inc.

PIC16C6X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] SUBWF f,d Syntax: [ label ] SWAPF f,d Operands: 0 f 127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - (W) destination) Operation: (f<3:0>)  (destination<7:4>), (f<7:4>)  (destination<3:0>) Status Affected: C, DC, Z Status Affected: None Encoding: 00 0010 dfff ffff Encoding: 00 1110 dfff ffff Description: Subtract (2’s complement method) W reg- ister from register 'f'. If 'd' is 0 the result is Description: The upper and lower nibbles of register stored in the W register. If 'd' is 1 the 'f' are exchanged. If 'd' is 0 the result is result is stored back in register 'f'. placed in W register. If 'd' is 1 the result is placed in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to register 'f' data destination Decode Read Process Write to register 'f' data destination Example 1: SUBWF REG1,1 Example SWAPF REG, 0 Before Instruction Before Instruction REG1 = 3 W = 2 REG1 = 0xA5 C = ? After Instruction Z = ? REG1 = 0xA5 After Instruction W = 0x5A REG1 = 1 W = 2 C = 1; result is positive Z = 0 Example 2: Before Instruction TRIS Load TRIS Register REG1 = 2 Syntax: [label] TRIS f W = 2 Operands: 5  f  7 C = ? Z = ? Operation: (W)  TRIS register f; After Instruction Status Affected: None REG1 = 0 Encoding: 00 0000 0110 0fff W = 2 Description: The instruction is supported for code C = 1; result is zero compatibility with the PIC16C5X prod- Z = 1 ucts. Since TRIS registers are read- Example 3: Before Instruction able and writable, the user can directly address them. REG1 = 1 Words: 1 W = 2 C = ? Cycles: 1 Z = ? Example After Instruction To maintain upward compatibility REG1 = 0xFF with future PIC16CXX products, do W = 2 not use this instruction. C = 0; result is negative Z = 0  1997-2013 Microchip Technology Inc. DS30234E-page 157

PIC16C6X XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] XORLW k Syntax: [label] XORWF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: (W) .XOR. k W) Operation: (W) .XOR. (f) destination) Status Affected: Z Status Affected: Z Encoding: 11 1010 kkkk kkkk Encoding: 00 0110 dfff ffff Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. Description: Exclusive OR the contents of the W The result is placed in the W regis- register with register 'f'. If 'd' is 0 the ter. result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read Process Write to literal 'k' data W Decode Read Process Write to register data destination 'f' Example: XORLW 0xAF Before Instruction Example XORWF REG 1 W = 0xB5 Before Instruction After Instruction REG = 0xAF W = 0xB5 W = 0x1A After Instruction REG = 0x1A W = 0xB5 DS30234E-page 158  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.0 ELECTRICAL CHARACTERISTICS FOR PIC16C61 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)..............................................................................................0V to +14V Voltage on RA4 pin with respect to Vss..........................................................................................................0V to +14V Total power dissipation (Note 1)...........................................................................................................................800 mW Maximum current out of VSS pin...........................................................................................................................150 mA Maximum current into VDD pin..............................................................................................................................100 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................20 mA Maximum current sunk byPORTA..........................................................................................................................80 mA Maximum current sourced by PORTA.....................................................................................................................50 mA Maximum current sunk by PORTB........................................................................................................................150 mA Maximum current sourced by PORTB...................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 15-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) OSC PIC16C61-04 PIC16C61-20 PIC16LC61-04 JW Devices RC VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V IDD: 3.3 mA max. at 5.5V IDD: 1.8 mA typ. at 5.5V IDD: 1.4 mA typ. at 3.0V IDD: 3.3 mA max. at 5.5V IPD: 14 A max. at 4V IPD: 1.0 A typ. at 4V IPD: 0.6 A typ. at 3V IPD: 14 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. XT VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V IDD: 3.3 mA max. at 5.5V IDD: 1.8 mA typ. at 5.5V IDD: 1.4 mA typ. at 3.0V IDD: 3.3 mA max. at 5.5V IPD: 14 A max. at 4V IPD: 1.0 A typ. at 4V IPD: 0.6 A typ. at 3V IPD: 14 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 30 mA max. at 5.5V Not recommended for use in IDD: 30 mA max. at 5.5V IPD: 1.0 A typ. at 4.5V IPD: 1.0 A typ. at 4.5V HS mode IPD: 1.0 A typ. at 4.5V Freq: 4 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. LP VDD: 4.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V IDD: 15 A typ. at 32 kHz, IDD: 32 A max. at 32 kHz, IDD: 32 A max. at 32 kHz, Not recommended for 4.0V 3.0V 3.0V use in LP mode IPD: 0.6 A typ. at 4.0V IPD: 9 A max. at 3.0V IPD: 9 A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 159

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.1 DC Characteristics: PIC16C61-04 (Commercial, Industrial, Extended) PIC16C61-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, DC CHARACTERISTICS -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power- on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current (Note 2) IDD - 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D020 Power-down Current IPD - 7 28 A VDD = 4.0V, WDT enabled, -40C to +85C D021 (Note 3) - 1.0 14 A VDD = 4.0V, WDT disabled, -0C to +70C D021A - 1.0 16 A VDD = 4.0V, WDT disabled, -40C to +85C D021B - 1.0 20 A VDD = 4.0V, WDT disabled, -40C to +125C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. DS30234E-page 160  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.2 DC Characteristics: PIC16LC61-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 3.0 - 6.0 V XT, RC, and LP osc configuration D002* RAM Data Retention Volt- VDR - 1.5 - V age (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current (Note 2) IDD - 1.4 2.5 mA FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 15 32 A FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP osc configuration D020 Power-down Current IPD - 5 20 A VDD = 3.0V, WDT enabled, -40C to +85C D021 (Note 3) - 0.6 9 A VDD = 3.0V, WDT disabled, 0C to +70C D021A - 0.6 12 A VDD = 3.0V, WDT disabled, -40C to +85C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.  1997-2013 Microchip Technology Inc. DS30234E-page 161

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.3 DC Characteristics: PIC16C61-04 (Commercial, Industrial, Extended) PIC16C61-20 (Commercial, Industrial, Extended) PIC16LC61-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section15.1 and Section15.2. Param Characteristic Sym Min Typ† Max Units Conditions No. Input Low Voltage I/O ports VIL D030 with TTL buffer Vss - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer Vss - 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP) Vss - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V  VDD  5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.85VDD - VDD V For entire VDD range D042 MCLR 0.85VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 † 400 A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - 1 A Vss VPIN VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * The parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 162  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section15.1 and Section15.2. Param Characteristic Sym Min Typ† Max Units Conditions No. Output High Voltage D090 I/O ports (Note 3) VOH VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D090A VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C D092 OSC2/CLKOUT (RC osc config) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D092A VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO 50 pF * The parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 163

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 15-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50 pF for all pins except OSC2/CLKOUT 15 pF for OSC2 output DS30234E-page 164  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 15.5 Timing Diagrams and Specifications FIGURE 15-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 1 — 4 MHz HS osc mode (-04) 1 — 20 MHz HS osc mode (-20) 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 1,000 ns HS osc mode (-04) 50 — 1,000 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 1.0 TCY DC s TCY = 4/Fosc 3 TosL, External Clock in (OSC1) High or 50 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 10 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or 25 — — ns XT oscillator TosF Fall Time 50 — — ns LP oscillator 15 — — ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 165

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 12 13 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure15-1 for load conditions. TABLE 15-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1 to CLKOUT — 15 30 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 15 30 ns Note 1 12* TckR CLKOUT rise time — 5 15 ns Note 1 13* TckF CLKOUT fall time — 5 15 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — — 80 - 100 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19* TioV2osH Port input valid to OSC1(I/O in setup TBD — — ns time) 20* TioR Port output rise time PIC16C61 — 10 25 ns PIC16LC61 — — 60 ns 21* TioF Port output fall time PIC16C61 — 10 25 ns PIC16LC61 — — 60 ns 22††* Tinp RB0/INT pin high or low time 20 — — ns 23††* Trbp RB7:RB4 change int high or low time 20 — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 166  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure15-1 for load conditions. TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30* TmcL MCLR Pulse Width (low) 200 — — ns VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +125°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34* TIOZ I/O Hi-impedance from MCLR Low — — 100 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 167

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 15-5: TIMER0 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 TMR0 Note: Refer to Figure15-1 for load conditions. TABLE 15-5: TIMER0 EXTERNAL CLOCK REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet parameter 42 With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet parameter 42 With Prescaler 10 — — ns 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns N = prescale value (2, 4, ..., 256) With Prescaler Greater of: — — ns 20 ns or TCY + 40 N * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 168  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 16.0 DC AND AC Note: The data presented in this section is a sta- CHARACTERISTICS GRAPHS tistical summary of data collected on units AND TABLES FOR PIC16C61 from different lots over a period of time and matrix samples. 'Typical' represents the The graphs and tables provided in this section are for mean of the distribution while 'max' or 'min' design guidance and are not tested or guaranteed. represents (mean +3) and (mean -3) In some graphs or tables the data presented are respectively where  is standard deviation. outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. FIGURE 16-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FOSC FOSC (25C) Frequency Normalized TO +25C 1.050 REXT  10 k 1.025 CEXT = 100 pF 1.00 VDD = 5.5V 0.975 0.950 0.925 VDD = 3.5V 0.900 0.875 0.850 0 10 20 25 30 40 50 60 70 T (C) TABLE 16-1: RC OSCILLATOR FREQUENCIES Average Cext Rext Fosc @ 5V, 25C 20 pF 4.7k 4.52 MHz  17.35% 10k 2.47 MHz  10.10% 100k 290.86 kHz  11.90% 100 pF 3.3k 1.92 MHz  9.43% 4.7k 1.48 MHz  9.83% 10k 788.77 kHz  10.92% 100k 88.11 kHz  16.03% 300 pF 3.3k 726.89 kHz  10.97% 4.7k 573.95 kHz  10.14% 10k 307.31 kHz  10.43% 100k 33.82 kHz  11.24% The percentage variation indicated here is part to part variation due to normal process distribution. The variation indi- cated is 3 standard deviation from average value for VDD = 5V.  1997-2013 Microchip Technology Inc. DS30234E-page 169

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-2: TYPICAL RC OSCILLATOR FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY VS. VDD FREQUENCY VS. VDD 5.0 8.0 R = 3.3k 4.5 R = 4.7k 7.0 4.0 6.0 R = 4.7k 3.5 5.0 3.0 Fosc (MHz) 2.5 R = 10k Fosc (MHz) 4.0 2.0 R = 10k 3.0 1.5 2.0 1.0 Cext = 300 pF, T = 25C Cext = 20 pF, T = 25C ails. 0.5 1.0 R = 100k det R = 100k n for 0.03.0 3.5 4.0 4.5 5.0 5.5 6.0 0.03.0 3.5 4.0 4.5 5.0 5.5 6.0 o VDD (Volts) VDD (Volts) cti e s s FIGURE 16-3: TYPICAL RC OSCILLATOR FIGURE 16-5: TYPICAL IPD VS. VDD hi FREQUENCY VS. VDD WATCHDOG TIMER of t DISABLED 25C e 2.0 g a p 0.6 st 1.8 R = 3.3k e fir e 1.6 S s. 0.5 e pl 1.4 m R = 4.7k a x s 1.2 0.4 atri Hz) based on m Fosc (M 10..08 R = 10k I (A)PD 0.3 ata 0.6 D 0.2 0.4 Cext = 100 pF, T = 25C 0.2 R = 100k 0.1 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30234E-page 170  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-6: TYPICAL IPD VS. VDD FIGURE 16-7: MAXIMUM IPD VS. VDD WATCHDOG TIMER ENABLED WATCHDOG DISABLED 25C 25 14 125C 12 20 10 15 A) 8 A) I (PD (PD 6 I 10 85C 4 70C 5 s. ail et 2 0C or d -40C n f 0 03.0 3.5 4.0 4.5 5.0 5.5 6.0-55C ectio 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) s s VDD (Volts) of thi e g a p st e fir e S s. e pl m a s x atri m n o d e s a b a at D  1997-2013 Microchip Technology Inc. DS30234E-page 171

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-8: MAXIMUM IPD VS. VDD FIGURE 16-9: VTH (INPUT THRESHOLD WATCHDOG ENABLED* VOLTAGE) OF I/O PINS VS. VDD 45 -55C 40 -40C 2.00 1.80 35 Max (-40C to 85C) s) 1.60 30 olt 1.40 25C, Typ 125C (VH 1.20 A) 25 VT (D 1.00 Min (-40C to 85C) P I 20 0.80 0.60 0C 15 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 7805CC VDD (Volts) 10 5 s. ail et 0 n for d 3.0 3.5 4.0VDD4 (.V5olts)5.0 5.5 6.0 o cti *IPD, with Watchdog Timer enabled, has two compo- e s s nents: The leakage current which increases with higher hi temperature and the operating current of the Watchdog of t Timer logic which increases with lower temperature. At e -40C, the latter dominates explaining the apparently g pa anomalous behavior. st e fir e S s. e pl m a s x atri m n o d e s a b a at D DS30234E-page 172  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-10:VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD 4.5 VIH, Max (-40C to 85C) 4.0 VIH, Typ (25C) VIH, Min (-40C to 85C) 3.5 3.0 s) olt 2.5 V V (IL 2.0 , H VI 1.5 VIL, Max (-40C to 85C) 1.0 VIL, Typ (25C) VIL, Min (-40C to 85C) 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) These pins have Schmitt Trigger input buffers. s. ail et d FIGURE 16-11:VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) or VS. VDD n f o cti e 3.6 Max (-40C to 85C) s s 3.4 Typ (25C) of thi 3.2 e Min (-40C to 85C) ag 3.0 p st 2.8 e fir e 2.6 S Volts) 2.4 ples. (H 2.2 am VT 2.0 x s 1.8 matri 1.6 on d 1.4 se a b 1.2 a at 1.0 D 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts)  1997-2013 Microchip Technology Inc. DS30234E-page 173

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-12:TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1,000 A)  (D D I 100 10 s. ail et 1 d or 10,000 100,000 1,000,000 10,000,000 100,000,000 n f Frequency (Hz) o cti e s s FIGURE 16-13:MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -40 TO +85C) hi of t e 10,000 ag 6.0 p 5.5 st 5.0 e fir 44..50 e 3.5 S s. 3.0 e pl 1,000 m sa A) atrix (DD m I n o d e s a 100 b a at D 10 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency (Hz) DS30234E-page 174  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-14:MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -55 TO +125C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1,000 A)  (D D I 100 s. 10 etail 10,000 100,000 1,000,000 10,000,000 100,000,000 or d Frequency (Hz) n f o cti e FIGURE 16-15:WDT TIMER TIME-OUT FIGURE 16-16:TRANSCONDUCTANCE (gm) s s PERIOD VS. VDD OF HS OSCILLATOR VS. VDD hi of t 50 e g 9000 a p 45 st 8000 e fir e S 40 7000 s. e Max. -40C pl m 35 6000 sa s) x DT period (m 3205 Max. 85C gm (A/V) 54000000 ed on matri W Max. 70C Typ. 25C as b 20 Typ. 25C 3000 MIn. 85C Data 2000 15 Min. 0C 1000 10 Min. -40C 0 5 2 3 4 5 6 7 2 3 4 5 6 7 VDD (Volts) VDD (Volts)  1997-2013 Microchip Technology Inc. DS30234E-page 175

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-17:TRANSCONDUCTANCE (gm) FIGURE 16-19:IOH VS. VOH, VDD = 3V OF LP OSCILLATOR VS. VDD 0 225 200 -5 MIn. 85C Max. -40C 175 150 -10 Typ. 25C A) m (A/V) 125 I (mOH Typ. 25C g 100 -15 MIn. 85C 75 50 -20 ails. 25 Max. -40C et d on for 03.0 3.5 4V.0DD (Volts4).5 5.0 5.5 6.0 -250 0.5 1.0 1.5 2.0 2.5 3.0 cti VOH (Volts) e s s FIGURE 16-18:TRANSCONDUCTANCE (gm) of thi OF XT OSCILLATOR VS. VDD FIGURE 16-20:IOH VS. VOH, VDD = 5V e ag 2500 0 p st e fir -5 e Max. -40C S s. 200 -10 e pl m -15 a s atrix 1500 mA) -20 Min @ 85C d on m m (A/V) Typ. 25C I( OH -25 Typ @ 25C e g as -30 b 100 a at -35 D MIn. 85C -40 Max @ -40C 500 -45 -50 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 3 4 5 6 7 VDD (Volts) VOH (Volts) DS30234E-page 176  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 16-21:IOL VS. VOL, VDD = 3V FIGURE 16-22:IOL VS. VOL, VDD = 5V 35 90 Min @ -40C 80 Min @ -40C 30 70 25 60 Typ @ 25C Typ @ 25C 20 A) 50 A) m I (mOL 15 Min @ +85C I (OL 40 Min @ +85C 30 10 20 5 s. 10 ail et d 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 00.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 on for VOL (Volts) VOL (Volts) ecti s s hi of t e g a p st TABLE 16-2: INPUT CAPACITANCE* e fir e Pin Name Typical Capacitance (pF) S s. 18L PDIP 18L SOIC e pl RA port 5.0 4.3 m a s RB port 5.0 4.3 x MCLR 17.0 17.0 matri OSC1/CLKIN 4.0 3.5 on d OSC2/CLKOUT 4.3 3.5 e s a T0CKI 3.2 2.8 b a *All capacitance values are typical at 25C. A part to part variation of 25% (three standard deviations) should be at D taken into account.  1997-2013 Microchip Technology Inc. DS30234E-page 177

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 178  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.0 ELECTRICAL CHARACTERISTICS FOR PIC16C62/64 Absolute Maximum Ratings † Ambient temperature under bias...............................................................................................................-55°C to +85°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)...............................................................................................0V to +14V Voltage on RA4 with respect to Vss ...............................................................................................................0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE* (combined)................................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE* (combined)...........................................................200 mA Maximum current sunk by PORTC and PORTD* (combined)...............................................................................200 mA Maximum current sourced by PORTC and PORTD* (combined).........................................................................200 mA * PORTD and PORTE not available on the PIC16C62. Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 17-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C62-04 PIC16C62-10 PIC16C62-20 PIC16LC62-04 OSC JW Devices PIC16C64-04 PIC16C64-10 PIC16C64-20 PIC16LC64-04 RC VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V IDD: 3.8 mA max. at 5.5VIDD: 2.0 mA typ. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 3.8 mA max. at 3.0VIDD: 3.8 mA max. at 5.5V IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 13.5 A max. at 3V IPD: 21 A max. at 4V Freq:4 MHz max. Freq:4 MHz max. Freq:4 MHz max. Freq: 4 MHz max. Freq:4 MHz max. XT VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V IDD: 3.8 mA max. at 5.5VIDD: 2.0 mA typ. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 3.8 mA max. at 3.0VIDD: 3.8 mA max. at 5.5V IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 13.5 A max. at 3.0VIPD: 21 A max. at 4V Freq:4 MHz max. Freq:4 MHz max. Freq:4 MHz max. Freq: 4 MHz max. Freq:4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 15 mA max. at 5.5V IDD: 30 mA max. at 5.5V Not recommended for IDD: 30 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V use in HS mode IPD: 1.5 A typ. at 4.5V Freq:4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. LP VDD: 4.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V IDD: 52.5 A typ. IDD: 48 A max. IDD: 48 A max. Not recommended for Not recommended for at 32 kHz, 4.0V at 32 kHz, 3.0V at 32 kHz, 3.0V use in LP mode use in LP mode IPD: 0.9 A typ. at 4.0V IPD: 13.5 A max. at 3.0V IPD:13.5 A max. at 3.0V Freq:200 kHz max. Freq:200 kHz max. Freq:200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 179

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.1 DC Characteristics: PIC16C62/64-04 (Commercial, Industrial) PIC16C62/64-10 (Commercial, Industrial) PIC16C62/64-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power- on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current IDD - 2.7 5.0 mA XT, RC, osc configuration (Note 2, 5) FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D020 Power-down Current IPD - 10.5 42 A VDD = 4.0V, WDT enabled, -40C to +85C D021 (Note 3, 5) - 1.5 21 A VDD = 4.0V, WDT disabled, -0C to +70C D021A - 1.5 24 A VDD = 4.0V, WDT disabled, -40C to +85C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from charac- terization and is for design guidance only. This is not tested. DS30234E-page 180  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.2 DC Characteristics: PIC16LC62/64-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 3.0 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power- on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current IDD - 2.0 3.8 mA XT, RC osc configuration (Note 2, 5) FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D020 Power-down Current IPD - 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D021 (Note 3, 5) - 0.9 13.5 A VDD = 3.0V, WDT disabled, 0C to +70C D021A - 0.9 18 A VDD = 3.0V, WDT disabled, -40C to +85C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from charac- terization and is for design guidance only. This is not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 181

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.3 DC Characteristics: PIC16C62/64-04 (Commercial, Industrial) PIC16C62/64-10 (Commercial, Industrial) PIC16C62/64-20 (Commercial, Industrial) PIC16LC62/64-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section17.1 and Section17.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP) Vss - 0.3VDD V Note1 Input High Voltage I/O ports VIH D040 with TTL buffer 2.0 - VDD V 4.5V  VDD  5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 200 400 A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - 1 A Vss VPIN VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C Output High Voltage D090 I/O ports (Note 3) VOH VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKOUT (RC osc config) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 182  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section17.1 and Section17.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF D102 SCL, SDA in I2C mode Cb - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 183

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 17-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 VDD/2 Load condition 2 RL Pin CL Pin CL VSS VSS RL = 464 Note1: PORTD and PORTE are not imple- mented on the PIC16C62. CL = 50 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports 15 pF for OSC2 output DS30234E-page 184  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 17.5 Timing Diagrams and Specifications FIGURE 17-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 1,000 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High 100 — — ns XT oscillator TosH or Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise — — 25 ns XT oscillator TosF or Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 185

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 14 19 18 12 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure17-1 for load conditions. TABLE 17-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameters Sym Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  TOSC + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port PIC16C62/64 100 — — ns input invalid (I/O in hold time) PIC16LC62/64 200 — — ns 19* TioV2osH Port input valid to OSC1 0 — — ns (I/O in setup time) 20* TioR Port output rise time PIC16C62/64 — 10 40 ns PIC16LC62/64 — — 80 ns 21* TioF Port output fall time PIC16C62/64 — 10 40 ns PIC16LC62/64 — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 186  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure17-1 for load conditions. TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30* TmcL MCLR Pulse Width (low) 100 — — ns VDD = 5V, -40°C to +85°C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C 34* TIOZ I/O Hi-impedance from MCLR Low — — 100 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 187

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSI/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure17-1 for load conditions. TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C6X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC6X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C6X 60 — — ns PIC16LC6X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 188  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure17-1 for load conditions. TABLE 17-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 No Prescaler 0.5TCY + 20 — — ns input low time With PrescalerPIC16C62/64 10 — — ns PIC16LC62/64 20 — — ns 51* TccH CCP1 No Prescaler 0.5TCY + 20 — — ns input high time With PrescalerPIC16C62/64 10 — — ns PIC16LC62/64 20 — — ns 52* TccP CCP1 input period 3TCY + 40 — — ns N = prescale value N (1,4 or 16) 53 TccR CCP1 output rise time PIC16C62/64 — 10 25 ns PIC16LC62/64 — 25 45 ns 54 TccF CCP1 output fall time PIC16C62/64 — 10 25 ns PIC16LC62/64 — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 189

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-7: PARALLEL SLAVE PORT TIMING (PIC16C64) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure17-1 for load conditions TABLE 17-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C64) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62 TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 63* TwrH2dtI WR or CS to data–in invalid PIC16C64 20 — — ns (hold time) PIC16LC64 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns 65 TrdH2dtI RD or CS to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 190  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 80 79 78 SDO 75, 76 77 SDI 74 73 Note: Refer to Figure17-1 for load conditions TABLE 17-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71 TscH SCK input high time (slave mode) TCY + 20 — — ns 72 TscL SCK input low time (slave mode) TCY + 20 — — ns 73 TdiV2scH, Setup time of SDI data input to SCK 50 — — ns TdiV2scL edge 74 TscH2diL, Hold time of SDI data input to SCK 50 — — ns TscL2diL edge 75 TdoR SDO data output rise time — 10 25 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 191

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-9: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure17-1 for load conditions TABLE 17-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns condition Setup time 400 kHz mode 600 — — 91 THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns pulse is generated Hold time 400 kHz mode 600 — — 92 TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — DS30234E-page 192  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 17-10:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure17-1 for load conditions TABLE 17-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102 TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 103 TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10 to 400 pF 90 TSU:STA START condition 100 kHz mode 4.7 — s Only relevant for repeated setup time 400 kHz mode 0.6 — s START condition 91 THD:STA START condition hold 100 kHz mode 4.0 — s After this period the first clock time 400 kHz mode 0.6 — s pulse is generated 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92 TSU:STO STOP condition setup 100 kHz mode 4.7 — s time 400 kHz mode 0.6 — s 109 TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start Cb Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max. + tsu;DAT=1000+250=1250ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 193

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 194  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.0 ELECTRICAL CHARACTERISTICS FOR PIC16C62A/R62/64A/R64 Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)...............................................................................................0V to +14V Voltage on RA4 with respect to Vss................................................................................................................0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (combined)..................................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined)............................................................200 mA Maximum current sunk by PORTC and PORTD (combined)................................................................................200 mA Maximum current sourced by PORTC and PORTD (combined)...........................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 18-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C62A-04 PIC16C62A-10 PIC16C62A-20 PIC16LC62A-04 PIC16CR62-04 PIC16CR62-10 PIC16CR62-20 PIC16LCR62-04 OSC JW Devices PIC16C64A-04 PIC16C64A-10 PIC16C64A-20 PIC16LC64A-04 PIC16CR64-04 PIC16CR64-10 PIC16CR64-20 PIC16LCR64-04 RC VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 3.8 mA max. at 3.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 16 A max. at 4V Freq:4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq:4 MHz max. XT VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 3.8 mA max. at 3.0V IDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3.0V IPD: 16 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5VIDD: 10 mA max. at 5.5VIDD: 20 mA max. at 5.5VNot recommended for use IDD: 20 mA max. at 5.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V in HS mode IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. LP VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 52.5 A typ. Not recommended for Not recommended for IDD: 48 A max. at 32 IDD: 48 A max. at 32 kHz, 4.0V kHz, 3.0V at 32 kHz, 3.0V use in LP mode use in LP mode IPD: 0.9 A typ. at 4.0V IPD: 5 A max. at 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 195

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.1 DC Characteristics: PIC16C62A/R62/64A/R64-04 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-10 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, DC CHARACTERISTICS -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled 3.7 4.0 4.4 V Extended Range Only D010 Supply Current (Note 2, 5) IDD - 2.7 5 mA XT, RC, osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 10 20 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D015* Brown-out Reset Current  IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note6) D020 Power-down Current (Note IPD - 10.5 42 A VDD = 4.0V, WDT enabled, -40C to +85C D021 3, 5) - 1.5 16 A VDD = 4.0V, WDT disabled, -0C to +70C D021A - 1.5 19 A VDD = 4.0V, WDT disabled, -40C to +85C D021B - 2.5 19 A VDD = 4.0V, WDT disabled, -40C to +125C D023* Brown-out Reset Current  IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30234E-page 196  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.2 DC Characteristics: PIC16LC62A/R62/64A/R64-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention Volt- VDR - 1.5 - V age (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN bit in configuration word enabled D010 Supply Current (Note 2, 5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note6) D020 Power-down Current IPD - 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D021 (Note 3, 5) - 0.9 5 A VDD = 3.0V, WDT disabled, 0C to +70C D021A - 0.9 5 A VDD = 3.0V, WDT disabled, -40C to +85C D023* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.  1997-2013 Microchip Technology Inc. DS30234E-page 197

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.3 DC Characteristics: PIC16C62A/R62/64A/R64-04 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-10 (Commercial, Industrial, Extended) PIC16C62A/R62/64A/R64-20 (Commercial, Industrial, Extended) PIC16LC62A/R62/64A/R64-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section18.1 and Section18.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer Vss - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer Vss - 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP) Vss - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V  VDD  5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - 1 A Vss VPIN VDD, Pin at hi-imped- ance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 198  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section18.1 and Section18.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Output High Voltage D090 I/O ports (Note 3) VOH VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D090A VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C D092 OSC2/CLKOUT (RC osc config) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D092A VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin Capacitive Loading Specs on Out- put Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF D102 SCL, SDA in I2C mode Cb - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 199

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 18-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS Pin CL VSS RL = 464 CL = 50 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports Note1: PORTD and PORTE are not 15 pF for OSC2 output implemented on the PIC16C62A/R62. DS30234E-page 200  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 18.5 Timing Diagrams and Specifications FIGURE 18-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 18-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency (Note 1) DC — 4 MHz XT and RC osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 201

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure18-1 for load conditions. TABLE 18-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameters Sym Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input PIC16C62A/ 100 — — ns invalid (I/O in hold time) R62/64A/R64 PIC16LC62A/ 200 — — ns R62/64A/R64 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C62A/ — 10 40 ns R62/64A/R64 PIC16LC62A/ — — 80 ns R62/64A/R64 21* TioF Port output fall time PIC16C62A/ — 10 40 ns R62/64A/R64 PIC16LC62A/ — — 80 ns R62/64A/R64 22††* Tinp RB0/INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change int high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 202  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure18-1 for load conditions. FIGURE 18-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +125°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 s or WDT Reset 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  BVDD (param. D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 203

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure18-1 for load conditions. TABLE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C6X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC6X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C6X 60 — — ns PIC16LC6X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 204  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1) RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure18-1 for load conditions. TABLE 18-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 No Prescaler 0.5TCY + 20 — — ns input low time With Prescaler PIC16C62A/R62/ 10 — — ns 64A/R64 PIC16LC62A/R62/ 20 — — ns 64A/R64 51* TccH CCP1 No Prescaler 0.5TCY + 20 — — ns input high time With Prescaler PIC16C62A/R62/ 10 — — ns 64A/R64 PIC16LC62A/R62/ 20 — — ns 64A/R64 52* TccP CCP1 input period 3TCY + 40 — — ns N = prescale value N (1,4 or 16) 53* TccR CCP1 output rise time PIC16C62A/R62/ — 10 25 ns 64A/R64 PIC16LC62A/R62/ — 25 45 ns 64A/R64 54* TccF CCP1 output fall time PIC16C62A/R62/ — 10 25 ns 64A/R64 PIC16LC62A/R62/ — 25 45 ns 64A/R64 * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 205

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-8: PARALLEL SLAVE PORT TIMING (PIC16C64A/R64) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure18-1 for load conditions TABLE 18-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C64A/R64) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62 TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 25 — — ns Extended Range Only 63* TwrH2dtI WR or CS to data–in invalid (hold PIC16C64A/R64 20 — — ns time) PIC16LC64A.R64 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns — — 90 ns Extended Range Only 65* TrdH2dtI RD or CS to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 206  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO 75, 76 77 SDI 74 73 Note: Refer to Figure18-1 for load conditions TABLE 18-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70* TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, Setup time of SDI data input to SCK 50 — — ns TdiV2scL edge 74* TscH2diL, Hold time of SDI data input to SCK 50 — — ns TscL2diL edge 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 207

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-10:I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure18-1 for load conditions TABLE 18-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90* TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91* THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92* TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93* THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — *These parameters are characterized but not tested. DS30234E-page 208  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 18-11:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure18-1 for load conditions TABLE 18-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 103* TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 90* TSU:STA START condition 100 kHz mode 4.7 — s Only relevant for repeated setup time 400 kHz mode 0.6 — s START condition 91* THD:STA START condition hold 100 kHz mode 4.0 — s After this period the first clock time 400 kHz mode 0.6 — s pulse is generated 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107* TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92* TSU:STO STOP condition setup 100 kHz mode 4.7 — s time 400 kHz mode 0.6 — s 109* TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT=1000+250=1250ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 209

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 NOTES: DS30234E-page 210  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.0 ELECTRICAL CHARACTERISTICS FOR PIC16C65 Absolute Maximum Ratings † Ambient temperature under bias...............................................................................................................-55°C to +85°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)...............................................................................................0V to +14V Voltage on RA4 with respect to Vss................................................................................................................0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (combined)..................................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined)............................................................200 mA Maximum current sunk by PORTC and PORTD (combined)................................................................................200 mA Maximum current sourced by PORTC and PORTD (combined)...........................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 19-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) OSC PIC16C65-04 PIC16C65-10 PIC16C65-20 PIC16LC65-04 JW Devices RC VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 800 A max. at 3V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. XT VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3V IDD: 5 mA max. at 5.5V IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 800 A max. at 3V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. HS VDD:4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at IDD: 15 mA max. at 5.5VIDD: 30 mA max. at IDD: 30 mA max. at 5.5V Not recommended for 5.5V 5.5V use in HS mode IPD: 1.5 A typ. at 4.5V IPD 1.0 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. LP VDD: 4.0V to 6.0V VDD: 3.0V to 6.0V VDD: 3.0V to 6.0V IDD: 52.5 A typ. IDD: 105 A max. IDD: 105 A max. at 32 kHz, 4.0V Not recommended for Not recommended for at 32 kHz, 3.0V at 32 kHz, 3.0V IPD: 0.9 A typ. at 4.0V use in LP mode use in LP mode IPD: 800 A max. at IPD: 800 A max. at Freq: 200 kHz max. 3.0V 3.0V Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recom- mended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 211

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.1 DC Characteristics: PIC16C65-04 (Commercial, Industrial) PIC16C65-10 (Commercial, Industrial) PIC16C65-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current (Note 2, 5) IDD - 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 13.5 30 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V D020 Power-down Current IPD - 10.5 800 A VDD = 4.0V, WDT enabled,-40C to +85C D021 (Note 3, 5) - 1.5 800 A VDD = 4.0V, WDT disabled,-0C to +70C D021A - 1.5 800 A VDD = 4.0V, WDT disabled,-40C to +85C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. DS30234E-page 212  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.2 DC Characteristics: PIC16LC65-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 3.0 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D010 Supply Current (Note 2, 5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 105 A LP osc configuration FOSC = 32 kHz, VDD = 4.0V, WDT disabled D020 Power-down Current IPD - 7.5 800 A VDD = 3.0V, WDT enabled, -40C to +85C D021 (Note 3, 5) - 0.9 800 A VDD = 3.0V, WDT disabled, 0C to +70C D021A - 0.9 800 A VDD = 3.0V, WDT disabled, -40C to +85C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 213

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.3 DC Characteristics: PIC16C65-04 (Commercial, Industrial) PIC16C65-10 (Commercial, Industrial) PIC16C65-20 (Commercial, Industrial) PIC16LC65-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section19.1 and Section19.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1(in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP) Vss - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V  VDD  5.5V D040A 0.25VDD + - VDD V For entire VDD range 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7 VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - 1 A Vss VPIN VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS, and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C Output High Voltage D090 I/O ports (Note 3) VOH VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKOUT (RC osc config) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 214  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section19.1 and Section19.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF D102 SCL, SDA in I2C mode Cb - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 215

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 19-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS Pin CL RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports 15 pF for OSC2 output DS30234E-page 216  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 19.5 Timing Diagrams and Specifications FIGURE 19-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 19-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3 TosL, External Clock in (OSC1) High or 50 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 217

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure19-1 for load conditions. TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port PIC16C65 100 — — ns input invalid (I/O in hold time) PIC16LC65 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C65 — 10 25 ns PIC16LC65 — — 60 ns 21* TioF Port output fall time PIC16C65 — 10 25 ns PIC16LC65 — — 60 ns 22††* Tinp RB0/INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change int high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 218  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure19-1 for load conditions. TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30* TmcL MCLR Pulse Width (low) 100 — — ns VDD = 5V, -40°C to +85°C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +85°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period or WDT 28 72 132 ms VDD = 5V, -40°C to +85°C reset 34 TIOZ I/O Hi-impedance from MCLR Low — — 100 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 219

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure19-1 for load conditions. TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C6X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC6X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C6X 60 — — ns PIC16LC6X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 220  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure19-1 for load conditions. TABLE 19-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time With Prescaler PIC16C65 10 — — ns PIC16LC65 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time With Prescaler PIC16C65 10 — — ns PIC16LC65 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale value N (1,4, or 16) 53 TccR CCP1 and CCP2 output rise time PIC16C65 — 10 25 ns PIC16LC65 — 25 45 ns 54 TccF CCP1 and CCP2 output fall time PIC16C65 — 10 25 ns PIC16LC65 — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 221

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-7: PARALLEL SLAVE PORT TIMING RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure19-1 for load conditions TABLE 19-7: PARALLEL SLAVE PORT REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62 TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 63* TwrH2dtI WR or CS to data–in invalid (hold PIC16C65 20 — — ns time) PIC16LC65 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns 65 TrdH2dtI RD or CS to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 222  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-8: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO 75, 76 77 SDI 74 73 Note: Refer to Figure19-1 for load conditions TABLE 19-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71 TscH SCK input high time (slave mode) TCY + 20 — — ns 72 TscL SCK input low time (slave mode) TCY + 20 — — ns 73 TdiV2scH, Setup time of SDI data input to SCK 50 — — ns TdiV2scL edge 74 TscH2diL, Hold time of SDI data input to SCK 50 — — ns TscL2diL edge 75 TdoR SDO data output rise time — 10 25 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time (master mode) — 10 25 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 223

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-9: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure19-1 for load conditions TABLE 19-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90 TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91 THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92 TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — DS30234E-page 224  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-10:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure19-1 for load conditions TABLE 19-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — s Devce must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101 TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102 TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 103 TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 90 TSU:STA START condition 100 kHz mode 4.7 — s Only relevant for repeated setup time 400 kHz mode 0.6 — s START condition 91 THD:STA START condition hold 100 kHz mode 4.0 — s After this period the first clock time 400 kHz mode 0.6 — s pulse is generated 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92 TSU:STO STOP condition setup 100 kHz mode 4.7 — s time 400 kHz mode 0.6 — s 109 TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110 TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start Cb Bus capacitive loading — 400 pF Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT=1000+250=1250ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 225

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 19-11:USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK 121 pin 121 RC7/RX/DT pin 120 122 Note: Refer to Figure19-1 for load conditions TABLE 19-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) PIC16C65 — — 80 ns Clock high to data out valid PIC16LC65 — — 100 ns 121 Tckrf Clock out rise time and fall time PIC16C65 — — 45 ns (Master Mode) PIC16LC65 — — 50 ns 122 Tdtrf Data out rise time and fall time PIC16C65 — — 45 ns PIC16LC65 — — 50 ns †: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 19-12:USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure19-1 for load conditions TABLE 19-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126 TckL2dtl Data hold after CK  (DT hold time) 15 — — ns †: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 226  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.0 ELECTRICAL CHARACTERISTICS FOR PIC16C63/65A Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)...............................................................................................0V to +14V Voltage on RA4 with respect to Vss................................................................................................................0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE not available on the PIC16C63. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 20-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C63-04 PIC16C63-10 PIC16C63-20 PIC16LC63-04 OSC JW Devices PIC16C65A-04 PIC16C65A-10 PIC16C65A-20 PIC16LC65A-04 RC VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3VIDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 16 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. XT VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3VIDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 16 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at IDD: 10 mA max. at 5.5VIDD: 20 mA max. at 5.5V IDD: 20 mA max. at Not recommended for 5.5V 5.5V use in HS mode IPD: 1.5 A typ. at 4.5V IPD 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. LP VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 52.5 A typ. Not recommended for Not recommended for IDD: 48 A max. at 32 IDD: 48 A max. at 32 kHz, 4.0V kHz, 3.0V at 32 kHz, 3.0V use in LP mode use in LP mode IPD: 0.9 A typ. at 4.0V IPD: 5 A max. at 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recom- mended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 227

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.1 DC Characteristics: PIC16C63/65A-04 (Commercial, Industrial, Extended) PIC16C63/65A-10 (Commercial, Industrial, Extended) PIC16C63/65A-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, DC CHARACTERISTICS -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled 3.7 4.0 4.4 V Extended Range Only D010 Supply Current (Note 2, 5) IDD - 2.7 5 mA XT, RC, osc config FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 10 20 mA HS osc config FOSC = 20 MHz, VDD = 5.5V D015* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) D020 Power-down Current IPD - 10.5 42 A VDD = 4.0V, WDT enabled,-40C to +85C D021 (Note 3, 5) - 1.5 16 A VDD = 4.0V, WDT disabled,-0C to +70C D021A - 1.5 19 A VDD = 4.0V, WDT disabled,-40C to +85C D021B - 2.5 19 A VDD = 4.0V, WDT disabled,-40C to +125C D023* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30234E-page 228  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.2 DC Characteristics: PIC16LC63/65A-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled D010 Supply Current (Note 2, 5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) D020 Power-down Current IPD - 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D021 (Note 3, 5) - 0.9 5 A VDD = 3.0V, WDT disabled, 0C to +70C D021A - 0.9 5 A VDD = 3.0V, WDT disabled, -40C to +85C D023* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.  1997-2013 Microchip Technology Inc. DS30234E-page 229

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.3 DC Characteristics: PIC16C63/65A-04 (Commercial, Industrial, Extended) PIC16C63/65A-10 (Commercial, Industrial, Extended) PIC16C63/65A-20 (Commercial, Industrial, Extended) PIC16LC63/65A-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section20.1 and Section20.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP) Vss - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V  VDD  5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - 1 A Vss VPIN VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 230  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section20.1 and Section20.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Output High Voltage D090 I/O ports (Note 3) VOH VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D090A VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C D092 OSC2/CLKOUT (RC osc config) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D092A VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin Capacitive Loading Specs on Out- put Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF D102 SCL, SDA in I2C mode Cb - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 231

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 20-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS Pin CL RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports Note1: PORTD and PORTE are not imple- mented on the PIC16C63. 15 pF for OSC2 output DS30234E-page 232  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 20.5 Timing Diagrams and Specifications FIGURE 20-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 20-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3* TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4* TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 233

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure20-1 for load conditions. TABLE 20-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input PIC16C63/65A 100 — — ns invalid (I/O in hold time) PIC16LC63/65A 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C63/65A — 10 40 ns PIC16LC63/65A — — 80 ns 21* TioF Port output fall time PIC16C63/65A — 10 40 ns PIC16LC63/65A — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 234  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure20-1 for load conditions. FIGURE 20-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +125°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 s or WDT reset 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  BVDD (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 235

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure20-1 for load conditions. TABLE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C6X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC6X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C6X 60 — — ns PIC16LC6X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 236  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure20-1 for load conditions. TABLE 20-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time With Prescaler PIC16C63/65A 10 — — ns PIC16LC63/65A 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time With Prescaler PIC16C63/65A 10 — — ns PIC16LC63/65A 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale value N (1,4, or 16) 53* TccR CCP1 and CCP2 output rise time PIC16C63/65A — 10 25 ns PIC16LC63/65A — 25 45 ns 54* TccF CCP1 and CCP2 output fall time PIC16C63/65A — 10 25 ns PIC16LC63/65A — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 237

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-8: PARALLEL SLAVE PORT TIMING (PIC16C65A) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure20-1 for load conditions TABLE 20-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65A) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62* TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 25 — — ns Extended Range Only 63* TwrH2dtI WR or CS to data–in invalid (hold PIC16C65A 20 — — ns time) PIC16LC65A 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns — — 90 ns Extended Range Only 65* TrdH2dtI RD or CS to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 238  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO 75, 76 77 SDI 74 73 Note: Refer to Figure20-1 for load conditions TABLE 20-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70* TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, Setup time of SDI data input to SCK 50 — — ns TdiV2scL edge 74* TscH2diL, Hold time of SDI data input to SCK 50 — — ns TscL2diL edge 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 239

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-10:I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure20-1 for load conditions TABLE 20-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90* TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91* THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92* TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. DS30234E-page 240  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-11:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure20-1 for load conditions TABLE 20-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 103* TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 90* TSU:STA START condition 100 kHz mode 4.7 — s Only relevant for repeated setup time 400 kHz mode 0.6 — s START condition 91* THD:STA START condition hold 100 kHz mode 4.0 — s After this period the first clock time 400 kHz mode 0.6 — s pulse is generated 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107* TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92* TSU:STO STOP condition setup 100 kHz mode 4.7 — s time 400 kHz mode 0.6 — s 109* TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT=1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 241

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 20-12:USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure20-1 for load conditions TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 120* TckH2dtV SYNC XMIT (MASTER & SLAVE) PIC16C63/65A — — 80 ns Clock high to data out valid PIC16LC63/65A — — 100 ns 121* Tckrf Clock out rise time and fall time PIC16C63/65A — — 45 ns (Master Mode) PIC16LC63/65A — — 50 ns 122* Tdtrf Data out rise time and fall time PIC16C63/65A — — 45 ns PIC16LC63/65A — — 50 ns * These parameters are characterized but not tested. †: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 20-13:USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure20-1 for load conditions TABLE 20-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns * These parameters are characterized but not tested. †: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 242  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.0 ELECTRICAL CHARACTERISTICS FOR PIC16CR63/R65 Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)...............................................................................................0V to +14V Voltage on RA4 with respect to Vss................................................................................................................0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE not available on the PIC16CR63. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 21-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16CR63-04 PIC16CR63-10 PIC16CR63-20 PIC16LCR63-04 OSC JW Devices PIC16CR65-04 PIC16CR65-10 PIC16CR65-20 PIC16LCR65-04 RC VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 5.5V VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3VIDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 16 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. XT VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 3.0V to 5.5V VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3VIDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 16 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at IDD: 10 mA max. at 5.5VIDD: 20 mA max. at 5.5V IDD: 20 mA max. at Not recomm ended for 5.5V 5.5V use in HS mode IPD: 1.5 A typ. at 4.5V IPD 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. LP VDD: 4.0V to 5.5V VDD: 3.0V to 5.5V VDD: 3.0V to 5.5V IDD: 52.5 A typ. Not recomm ended for Not recomm ended for IDD: 48 A max. at 32 IDD: 48 A max. at 32 kHz, 4.0V kHz, 3.0V at 32 kHz, 3.0V use in LP mode use in LP mode IPD: 0.9 A typ. at 4.0V IPD: 5 A max. at 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recom- mended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 243

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.1 DC Characteristics: PIC16CR63/R65-04 (Commercial, Industrial) PIC16CR63/R65-10 (Commercial, Industrial) PIC16CR63/R65-20 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 5.5 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled D010 Supply Current (Note 2, 5) IDD - 2.7 5 mA XT, RC, osc config FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 10 20 mA HS osc config FOSC = 20 MHz, VDD = 5.5V D015* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) D020 Power-down Current IPD - 10.5 42 A VDD = 4.0V, WDT enabled,-40C to +85C D021 (Note 3, 5) - 1.5 16 A VDD = 4.0V, WDT disabled,-0C to +70C D021A - 1.5 19 A VDD = 4.0V, WDT disabled,-40C to +85C D023* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30234E-page 244  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.2 DC Characteristics: PIC16LCR63/R65-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 3.0 - 5.5 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled D010 Supply Current (Note 2, 5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) D020 Power-down Current IPD - 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D021 (Note 3, 5) - 0.9 5 A VDD = 3.0V, WDT disabled, 0C to +70C D021A - 0.9 5 A VDD = 3.0V, WDT disabled, -40C to +85C D023* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.  1997-2013 Microchip Technology Inc. DS30234E-page 245

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.3 DC Characteristics: PIC16CR63/R65-04 (Commercial, Industrial) PIC16CR63/R65-10 (Commercial, Industrial) PIC16CR63/R65-20 (Commercial, Industrial) PIC16LCR63/R65-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section21.1 and Section21.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP) Vss - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V  VDD  5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - 1 A Vss VPIN VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C Output High Voltage D090 I/O ports (Note 3) VOH VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKOUT (RC osc config) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 246  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section21.1 and Section21.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Capacitive Loading Specs on Out- put Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF D102 SCL, SDA in I2C mode Cb - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 247

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 21-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS Pin CL RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports Note1: PORTD and PORTE are not imple- mented on the PIC16CR63. 15 pF for OSC2 output DS30234E-page 248  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 21.5 Timing Diagrams and Specifications FIGURE 21-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 21-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3* TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4* TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 249

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure21-1 for load conditions. TABLE 21-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input PIC16CR63/R65 100 — — ns invalid (I/O in hold time) PIC16LCR63/R65 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16CR63/R65 — 10 40 ns PIC16LCR63/R65 — — 80 ns 21* TioF Port output fall time PIC16CR63/R65 — 10 40 ns PIC16LCR63/R65 — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 250  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure21-1 for load conditions. FIGURE 21-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +125°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 s or WDT reset 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  BVDD (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 251

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure21-1 for load conditions. TABLE 21-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C6X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC6X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C6X 60 — — ns PIC16LC6X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 252  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure21-1 for load conditions. TABLE 21-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time With Prescaler PIC16CR63/R65 10 — — ns PIC16LCR63/R65 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time With Prescaler PIC16CR63/R65 10 — — ns PIC16LCR63/R65 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale value N (1,4, or 16) 53* TccR CCP1 and CCP2 output rise time PIC16CR63/R65 — 10 25 ns PIC16LCR63/R65 — 25 45 ns 54* TccF CCP1 and CCP2 output fall time PIC16CR63/R65 — 10 25 ns PIC16LCR63/R65 — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 253

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-8: PARALLEL SLAVE PORT TIMING (PIC16CR65) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure21-1 for load conditions TABLE 21-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16CR65) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62* TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 63* TwrH2dtI WR or CS to data–in invalid (hold PIC16CR65 20 — — ns time) PIC16LCR65 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns 65* TrdH2dtI RD or CS to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 254  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-9: SPI MODE TIMING SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO 75, 76 77 SDI 74 73 Note: Refer to Figure21-1 for load conditions TABLE 21-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70* TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, Setup time of SDI data input to SCK 50 — — ns TdiV2scL edge 74* TscH2diL, Hold time of SDI data input to SCK 50 — — ns TscL2diL edge 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 255

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-10:I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure21-1 for load conditions TABLE 21-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90* TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91* THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92* TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. DS30234E-page 256  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-11:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure21-1 for load conditions TABLE 21-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 103* TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 90* TSU:STA START condition 100 kHz mode 4.7 — s Only relevant for repeated setup time 400 kHz mode 0.6 — s START condition 91* THD:STA START condition hold 100 kHz mode 4.0 — s After this period the first clock time 400 kHz mode 0.6 — s pulse is generated 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107* TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92* TSU:STO STOP condition setup 100 kHz mode 4.7 — s time 400 kHz mode 0.6 — s 109* TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT=1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 257

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 21-12:USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure21-1 for load conditions TABLE 21-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 120* TckH2dtV SYNC XMIT (MASTER & SLAVE) PIC16CR63/R65 — — 80 ns Clock high to data out valid PIC16LCR63/R65 — — 100 ns 121* Tckrf Clock out rise time and fall time PIC16CR63/R65 — — 45 ns (Master Mode) PIC16LCR63/R65 — — 50 ns 122* Tdtrf Data out rise time and fall time PIC16CR63/R65 — — 45 ns PIC16LCR63/R65 — — 50 ns * These parameters are characterized but not tested. †: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 21-13:USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure21-1 for load conditions TABLE 21-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns * These parameters are characterized but not tested. †: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 258  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.0 ELECTRICAL CHARACTERISTICS FOR PIC16C66/67 Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)...............................................................................................0V to +14V Voltage on RA4 with respect to Vss................................................................................................................0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk byPORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE not available on the PIC16C66. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 22-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C66-04 PIC16C66-10 PIC16C66-20 PIC16LC66-04 OSC JW Devices PIC16C67-04 PIC16C67-10 PIC16C67-20 PIC16LC67-04 RC VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3VIDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 16 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. XT VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3VIDD: 5 mA max. at 5.5V IPD: 16 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 16 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at IDD: 10 mA max. at 5.5VIDD: 20 mA max. at 5.5V IDD: 20 mA max. at Not recommended for 5.5V 5.5V use in HS mode IPD: 1.5 A typ. at 4.5V IPD 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. LP VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 52.5 A typ. Not recommended for Not recommended for IDD: 48 A max. at 32 IDD: 48 A max. at 32 kHz, 4.0V kHz, 3.0V at 32 kHz, 3.0V use in LP mode use in LP mode IPD: 0.9 A typ. at 4.0V IPD: 5 A max. at 3.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recom- mended that the user select the device type that ensures the specifications required.  1997-2013 Microchip Technology Inc. DS30234E-page 259

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.1 DC Characteristics: PIC16C66/67-04 (Commercial, Industrial, Extended) PIC16C66/67-10 (Commercial, Industrial, Extended) PIC16C66/67-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, DC CHARACTERISTICS -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 4.0 - 6.0 V XT, RC and LP osc configuration D001A 4.5 - 5.5 V HS osc configuration D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled 3.7 4.0 4.4 V Extended Range Only D010 Supply Current (Note 2, 5) IDD - 2.7 5 mA XT, RC, osc config FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 10 20 mA HS osc config FOSC = 20 MHz, VDD = 5.5V D015* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) D020 Power-down Current IPD - 10.5 42 A VDD = 4.0V, WDT enabled,-40C to +85C D021 (Note 3, 5) - 1.5 16 A VDD = 4.0V, WDT disabled,-0C to +70C D021A - 1.5 19 A VDD = 4.0V, WDT disabled,-40C to +85C D021B - 2.5 19 A VDD = 4.0V, WDT disabled,-40C to +125C D023* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30234E-page 260  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.2 DC Characteristics: PIC16LC66/67-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial and 0°C  TA  +70°C for commercial Param Characteristic Sym Min Typ† Max Units Conditions No. D001 Supply Voltage VDD 2.5 - 6.0 V LP, XT, RC osc configuration (DC - 4 MHz) D002* RAM Data Retention VDR - 1.5 - V Voltage (Note 1) D003 VDD start voltage to VPOR - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* VDD rise rate to ensure SVDD 0.05 - - V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 Brown-out Reset Voltage BVDD 3.7 4.0 4.3 V BODEN configuration bit is enabled D010 Supply Current (Note 2, 5) IDD - 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 A LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled D015* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) D020 Power-down Current IPD - 7.5 30 A VDD = 3.0V, WDT enabled, -40C to +85C D021 (Note 3, 5) - 0.9 5 A VDD = 3.0V, WDT disabled, 0C to +70C D021A - 0.9 5 A VDD = 3.0V, WDT disabled, -40C to +85C D023* Brown-out Reset Current IBOR - 350 425 A BOR enabled, VDD = 5.0V (Note 6) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti- mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from character- ization and is for design guidance only. This is not tested. 6: The  current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.  1997-2013 Microchip Technology Inc. DS30234E-page 261

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.3 DC Characteristics: PIC16C66/67-04 (Commercial, Industrial, Extended) PIC16C66/67-10 (Commercial, Industrial, Extended) PIC16C66/67-20 (Commercial, Industrial, Extended) PIC16LC66/67-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section22.1 and Section22.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V  VDD  5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP) Vss - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer 2.0 - VDD V 4.5V  VDD  5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V D070 PORTB weak pull-up current IPURB 50 250 400 A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - 1 A Vss VPIN VDD, Pin at hi- impedance D061 MCLR, RA4/T0CKI - - 5 A Vss VPIN VDD D063 OSC1 - - 5 A Vss VPIN VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C D083 OSC2/CLKOUT (RC osc config) - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C D083A - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40C to +125C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. DS30234E-page 262  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C for extended, -40°C  TA  +85°C for industrial and DC CHARACTERISTICS 0°C  TA  +70°C for commercial Operating voltage VDD range as described in DC spec Section22.1 and Section22.2 Param Characteristic Sym Min Typ Max Units Conditions No. † Output High Voltage D090 I/O ports (Note 3) VOH VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D090A VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C D092 OSC2/CLKOUT (RC osc config) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C D092A VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40C to +125C D150* Open-Drain High Voltage VOD - - 14 V RA4 pin Capacitive Loading Specs on Out- put Pins D100 OSC2 pin COSC2 - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 (in RC mode) CIO - - 50 pF D102 SCL, SDA in I2C mode Cb - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C6X be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin.  1997-2013 Microchip Technology Inc. DS30234E-page 263

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only) CC HD Hold SU Setup ST DAT DATA input hold STO STOP condition STA START condition FIGURE 22-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 Load condition 2 VDD/2 RL Pin CL VSS Pin CL RL = 464 VSS CL = 50 pF for all pins except OSC2/CLKOUT but including D and E outputs as ports Note1: PORTD and PORTE are not imple- mented on the PIC16C66. 15 pF for OSC2 output DS30234E-page 264  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 22.5 Timing Diagrams and Specifications FIGURE 22-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 22-2: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. Fosc External CLKIN Frequency DC — 4 MHz XT and RC osc mode (Note 1) DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns XT and RC osc mode (Note 1) 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10) 50 — — ns HS osc mode (-20) 5 — — s LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 100 — 250 ns HS osc mode (-10) 50 — 250 ns HS osc mode (-20) 5 — — s LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/FOSC 3* TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — s LP oscillator 15 — — ns HS oscillator 4* TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.  1997-2013 Microchip Technology Inc. DS30234E-page 265

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-3: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: Refer to Figure22-1 for load conditions. TABLE 22-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1 to CLKOUT — 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT  to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT  Tosc + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT  0 — — ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input PIC16C66/67 100 — — ns invalid (I/O in hold time) PIC16LC66/67 200 — — ns 19* TioV2osH Port input valid to OSC1(I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C66/67 — 10 40 ns PIC16LC66/67 — — 80 ns 21* TioF Port output fall time PIC16C66/67 — 10 40 ns PIC16LC66/67 — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30234E-page 266  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Note: Refer to Figure22-1 for load conditions. FIGURE 22-5: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +125°C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40°C to +125°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C 34 TIOZ I/O Hi-impedance from MCLR Low — — 2.1 s or WDT reset 35 TBOR Brown-out Reset Pulse Width 100 — — s VDD  BVDD (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 267

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 40 41 42 RC0/T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure22-1 for load conditions. TABLE 22-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, PIC16C6X 15 — — ns parameter 47 Prescaler = PIC16LC6X 25 — — ns 2,4,8 Asynchronous PIC16C6X 30 — — ns PIC16LC6X 50 — — ns 47* Tt1P T1CKI input period Synchronous PIC16C6X Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8) N PIC16LC6X Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8) N Asynchronous PIC16C6X 60 — — ns PIC16LC6X 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 268  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure22-1 for load conditions. TABLE 22-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time With Prescaler PIC16C66/67 10 — — ns PIC16LC66/67 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time With Prescaler PIC16C66/67 10 — — ns PIC16LC66/67 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale value N (1,4, or 16) 53* TccR CCP1 and CCP2 output rise time PIC16C66/67 — 10 25 ns PIC16LC66/67 — 25 45 ns 54* TccF CCP1 and CCP2 output fall time PIC16C66/67 — 10 25 ns PIC16LC66/67 — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 269

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-8: PARALLEL SLAVE PORT TIMING (PIC16C67) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure22-1 for load conditions TABLE 22-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C67) Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62* TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns 25 — — ns Extended Range Only 63* TwrH2dtI WR or CS to data–in invalid (hold PIC16C67 20 — — ns time) PIC16LC67 35 — — ns 64 TrdL2dtV RD and CS to data–out valid — — 80 ns — — 90 ns Extended Range Only 65* TrdH2dtI RD or CS to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 270  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-9: SPI MASTER MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSB BIT6 - - - - - -1 LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure22-1 for load conditions. FIGURE 22-10:SPI MASTER MODE TIMING (CKE=1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSB BIT6 - - - - - -1 LSB 75, 76 SDI MSB IN BIT6 - - - -1 LSB IN 74 Refer to Figure22-1 for load conditions.  1997-2013 Microchip Technology Inc. DS30234E-page 271

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-11:SPI SLAVE MODE TIMING (CKE=0) SS 70 SCK (CKP = 0) 83 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSB BIT6 - - - - - -1 LSB 75, 76 77 SSDDII MSB IN BIT6 - - - -1 LSB IN 74 73 Refer to Figure22-1 for load conditions. FIGURE 22-12:SPI SLAVE MODE TIMING (CKE=1) 82 SS 70 SCK 83 (CKP = 0) 71 72 SCK (CKP = 1) 80 SDO MSB BIT6 - - - - - -1 LSB 75, 76 77 SSDDII MSB IN BIT6 - - - -1 LSB IN 74 Refer to Figure22-1 for load conditions. DS30234E-page 272  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 TABLE 22-8: SPI MODE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 70* TssL2scH, SS to SCK or SCK input TCY — — ns TssL2scL 71* TscH SCK input high time (slave mode) TCY + 20 — — ns 72* TscL SCK input low time (slave mode) TCY + 20 — — ns 73* TdiV2scH, Setup time of SDI data input to SCK 100 — — ns TdiV2scL edge 74* TscH2diL, Hold time of SDI data input to SCK 100 — — ns TscL2diL edge 75* TdoR SDO data output rise time — 10 25 ns 76* TdoF SDO data output fall time — 10 25 ns 77* TssH2doZ SS to SDO output hi-impedance 10 — 50 ns 78* TscR SCK output rise time (master mode) — 10 25 ns 79* TscF SCK output fall time (master mode) — 10 25 ns 80* TscH2doV, SDO data output valid after SCK — — 50 ns TscL2doV edge 81* TdoV2scH, SDO data output setup to SCK TCY — — ns TdoV2scL edge 82* TssL2doV SDO data output valid after SS — — 50 ns edge 83* TscH2ssH, SS after SCK edge 1.5TCY + 40 — — ns TscL2ssH * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  1997-2013 Microchip Technology Inc. DS30234E-page 273

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-13:I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA START STOP Condition Condition Note: Refer to Figure22-1 for load conditions TABLE 22-9: I2C BUS START/STOP BITS REQUIREMENTS Parameter Sym Characteristic Min Typ Max Units Conditions No. 90* TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91* THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92* TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. DS30234E-page 274  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-14:I2C BUS DATA TIMING 103 100 102 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure22-1 for load conditions TABLE 22-10: I2C BUS DATA REQUIREMENTS Parameter Sym Characteristic Min Max Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 103* TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 90* TSU:STA START condition 100 kHz mode 4.7 — s Only relevant for repeated setup time 400 kHz mode 0.6 — s START condition 91* THD:STA START condition hold 100 kHz mode 4.0 — s After this period the first clock time 400 kHz mode 0.6 — s pulse is generated 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107* TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92* TSU:STO STOP condition setup 100 kHz mode 4.7 — s time 400 kHz mode 0.6 — s 109* TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT=1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.  1997-2013 Microchip Technology Inc. DS30234E-page 275

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 22-15:USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure22-1 for load conditions TABLE 22-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 120* TckH2dtV SYNC XMIT (MASTER & SLAVE) PIC16C66/67 — — 80 ns Clock high to data out valid PIC16LC66/67 — — 100 ns 121* Tckrf Clock out rise time and fall time PIC16C66/67 — — 45 ns (Master Mode) PIC16LC66/67 — — 50 ns 122* Tdtrf Data out rise time and fall time PIC16C66/67 — — 45 ns PIC16LC66/67 — — 50 ns * These parameters are characterized but not tested. †: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 22-16:USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure22-1 for load conditions TABLE 22-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK  (DT setup time) 15 — — ns 126* TckL2dtl Data hold after CK  (DT hold time) 15 — — ns * These parameters are characterized but not tested. †: Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30234E-page 276  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR: PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A, PIC16CR64, PIC16C65A, PIC16C66, PIC16C67 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25C, while 'max' or 'min' represents (mean +3) and (mean -3) respectively where  is standard deviation. FIGURE 23-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE) 35 30 25 20 A) n (D P I 15 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 23-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE) 10.000 85C 70C 1.000 (A)D 0.100 25C P I 0C -40C 0.010 0.001 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts)  1997-2013 Microchip Technology Inc. DS30234E-page 277

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-3: TYPICAL IPD vs. VDD @ 25C FIGURE 23-5: TYPICAL RC OSCILLATOR (WDT ENABLED, RC MODE) FREQUENCY vs. VDD Cext = 22 pF, T = 25C 6.0 25 5.5 5.0 20 4.5 R = 5k 4.0 A) 15 MHz) 3.5 I(PD 10 osc( 3.0 R = 10k F 2.5 2.0 5 1.5 1.0 0 R = 100k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 VDD(Volts) 0.02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 23-4: MAXIMUM IPD vs. VDD (WDT Shaded area is beyond recommended range. ENABLED, RC MODE) FIGURE 23-6: TYPICAL RC OSCILLATOR 35 FREQUENCY vs. VDD -40C 30 0C 2.4 Cext = 100 pF, T = 25C 25 2.2 R = 3.3k 2.0 A) 20 1.8  I(PD 15 70C Hz) 11..64 R = 5k M 10 85C sc( 1.2 o F 1.0 ails. 5 0.8 R = 10k et 0.6 d 0 or 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.4 R = 100k on f VDD(Volts) 0.2 cti 0.02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 e s s VDD(Volts) hi of t FIGURE 23-7: TYPICAL RC OSCILLATOR ge FREQUENCY vs. VDD a p st e fir 1000 Cext = 300 pF, T = 25C e S 900 es. 800 R = 3.3k atrix sampl Fosc(kHz) 765400000000 R = 5k m n 300 R = 10k o d 200 se 100 R = 100k a a b 02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 at D VDD(Volts) DS30234E-page 278  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-8: TYPICAL IPD vs. VDD BROWN- FIGURE 23-10:TYPICAL IPD vs. TIMER1 OUT DETECT ENABLED (RC ENABLED (32 kHz, RC0/RC1 = MODE) 33 pF/33 pF, RC MODE) 1400 1200 30 1000 25 A) 800 Device NOT in (D Brown-out Reset 20 IP 600 400 BDreovwicne-o iunt (A)PD15 200 Reset I10 02.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5 VDD(Volts) 0 Tbrhoew ns-hoaudt erde seret gciiorcnu itrreyp.resents the built-in hysteresis of the 2.5 3.0 3.5 V4D.0D(Volts4).5 5.0 5.5 6.0 FIGURE 23-9: MAXIMUM IPD vs. VDD BROWN-OUT DETECT FIGURE 23-11:MAXIMUM IPD vs. TIMER1 ENABLED ENABLED (85C TO -40C, RC MODE) (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C TO -40C, RC MODE) 1600 1400 1200 45 1000 40 A) Device NOT in 35 (PD 800 Brown-out Reset 30 I 600 Device in Brown-out A)25 400 Reset (D20 2000 4.3 IP1150 details. The sh2a.5ded r3e.g0ion re3.p5resen4tVs.0D Dth(eV o4blt.us5i)lt-in 5h.y0steres5i.s5 of th6e.0 502.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 on for brown-out reset circuitry. VDD(Volts) cti e s s hi of t e g a p st e fir e S s. e pl m a s x atri m n o d e s a b a at D  1997-2013 Microchip Technology Inc. DS30234E-page 279

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-12:TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25C) 2000 6.0V 1800 5.5V 1600 5.0V 4.5V 1400 4.0V A) 1200 3.5V  (D ID 1000 3.0V 800 2.5V 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Frequency(MHz) Shaded area is beyond recommended range FIGURE 23-13:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40C TO 85C) 2000 6.0V 1800 5.5V 1600 5.0V 4.5V 1400 4.0V or details. I(A)DD 11200000 33..50VV n f 800 ctio 2.5V se 600 s of thi 400 ge 200 a p st 0 e fir 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 e Frequency(MHz) S Shaded area is s. beyond recommended range e pl m a s x atri m n o d e s a b a at D DS30234E-page 280  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-14:TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25C) 1600 6.0V 1400 5.5V 5.0V 1200 4.5V 4.0V 1000 3.5V A) (D 800 3.0V D I 2.5V 600 400 200 0 0 200 400 600 800 1000 1200 1400 1600 1800 Shaded area is Frequency(kHz) beyond recommended range FIGURE 23-15:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40C TO 85C) 1600 6.0V 1400 5.5V s. 5.0V ail 1200 4.5V det or 4.0V n f 1000 o 3.5V cti e I(A)DD 800 3.0V of this s 2.5V e 600 ag p st 400 e fir e S s. 200 ple m a s 00 200 400 600 800 1000 1200 1400 1600 1800 atrix m Shaded area is Frequency(kHz) n beyond recommended range o d e s a b a at D  1997-2013 Microchip Technology Inc. DS30234E-page 281

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-16:TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25C) 1200 6.0V 5.5V 1000 5.0V 4.5V 4.0V 800 3.5V 3.0V A) 600 (D 2.5V D I 400 200 0 0 100 200 300 400 500 600 700 Frequency(kHz) FIGURE 23-17:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40C TO 85C) 1200 6.0V 5.5V 1000 5.0V s. ail 4.5V et or d 800 4.0V n f 3.5V o cti e 3.0V of this s I(A)DD 600 2.5V e g a 400 p st e fir e S 200 s. e pl m a s 0 atrix 0 100 200 300 400 500 600 700 m Frequency(kHz) n o d e s a b a at D DS30234E-page 282  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-18:TYPICAL IDD vs. CAPACITANCE @ 500 kHz FIGURE 23-19:TRANSCONDUCTANCE(gm) (RC MODE) OF HS OSCILLATOR vs. VDD 600 4.0 Max -40C 500 5.0V 3.5 3.0 4.0V 400 2.5 A) 3.0V V) Typ 25C (D 300 mA/ 2.0 ID m( g 1.5 Min 85C 200 1.0 100 0.5 0 0.0 20 pF 100 pF 300 pF 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Capacitance(pF) Shaded area is VDD(Volts) beyond recommended range TABLE 23-1: RC OSCILLATOR FIGURE 23-20:TRANSCONDUCTANCE(gm) FREQUENCIES OF LP OSCILLATOR vs. VDD Average Cext Rext 110 Fosc @ 5V, 25C 100 Max -40C 90 22 pF 5k 4.12 MHz ± 1.4% 80 10k 2.35 MHz ± 1.4% 70 100k 268 kHz ± 1.1% A/V) 60 Typ 25C 100 pF 3.3k 1.80 MHz ± 1.0% m( 50 g 40 5k 1.27 MHz ± 1.0% 30 10k 688 kHz ± 1.2% 20 Min 85C 100k 77.2 kHz ± 1.0% 10 0 300 pF 3.3k 707 kHz ± 1.4% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 s. 5k 501 kHz ± 1.2% Sbehyaodnedd raerceoams mareen ded range VDD(Volts) detail 11000kk 2286.93 kkHHzz ±± 11..61%% FIGURE 23-21:TRANSCONDUCTANCE(gm) n for The percentage variation indicated here is part to OF XT OSCILLATOR vs. VDD ctio e part variation due to normal process distribution. The s vaaveriraatigoen vinadluicea ftoerd V isD D± 3= s5tVa.ndard deviation from 1098000000 Max -40C e of this 700 g a gm(A/V) 654300000000 TMyipn 2855CC See first p 200 s. e 100 pl m 02.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 sa x Sbehyaodnedd raerceoams mareen ded rangeVDD(Volts) atri m n o d e s a b a at D  1997-2013 Microchip Technology Inc. DS30234E-page 283

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-22:TYPICAL XTAL STARTUP FIGURE 23-24:TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25C) TIME vs. VDD (XT MODE, 25C) 3.5 70 3.0 60 2.5 s) 50 d con 2.0 ms) 40 up Time(Se 1.5 32 kHz, 33 pF/33 pF artup Time( 3200 220000 kkHHzz,, 6487 ppFF//6487 ppFF art 1.0 St 1 MHz, 15 pF/15 pF St 10 4 MHz, 15 pF/15 pF 0.5 200 kHz, 15 pF/15 pF 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.0 VDD(Volts) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(Volts) FIGURE 23-23:TYPICAL XTAL STARTUP TABLE 23-2: CAPACITOR SELECTION FOR TIME vs. VDD (HS MODE, CRYSTAL OSCILLATORS 25C) Crystal Cap. Range Cap. Range Osc Type 7 Freq C1 C2 LP 32 kHz 33 pF 33 pF 6 200 kHz 15 pF 15 pF ms) 5 20 MHz, 33 pF/33 pF XT 200 kHz 47-68 pF 47-68 pF e( m 1 MHz 15 pF 15 pF Ti 4 p 4 MHz 15 pF 15 pF u 8 MHz, 33 pF/33 pF ails. Start 3 20 MHz, 15 pF/15 pF HS 48 MMHHzz 151-53 3p FpF 151-53 3p FpF det 2 8 MHz, 15 pF/15 pF 20 MHz 15-33 pF 15-33 pF on for 14.0 4.5 5.0 5.5 6.0 Crystals cti VDD(Volts) Used e s s 32 kHz Epson C-001R32.768K-A ± 20 PPM e of thi 210 0M kHHzz SETCDS XETCLS 2-1000-.1030-01KHz ±± 2500 PPPPMM ag 4 MHz ECS ECS-40-20-1 ± 50 PPM p st 8 MHz EPSON CA-301 8.000M-C ± 30 PPM e fir 20 MHz EPSON CA-301 20.000M-C ± 30 PPM e S s. e pl m a s x atri m n o d e s a b a at D DS30234E-page 284  1997-2013 Microchip Technology Inc.

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-25:TYPICAL IDD vs. FREQUENCY FIGURE 23-27:TYPICAL IDD vs. FREQUENCY (LP MODE, 25°C) (XT MODE, 25°C) 1800 1600 6.0V 120 1400 5.5V 100 5.0V 1200 80 4.5V A)60 1000 4.0V I(DD40 655...050VVV A)800 33..50VV 4.5V (D600 20 43..05VV ID 2.5V 3.0V 400 2.5V 0 0 50 100 150 200 200 Frequency(kHz) 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Frequency(MHz) FIGURE 23-26:MAXIMUM IDD vs. FIGURE 23-28:MAXIMUM IDD vs. FREQUENCY FREQUENCY (LP MODE, 85°C TO -40°C) (XT MODE, -40°C TO 85°C) 1800 6.0V 140 1600 5.5V 120 1400 5.0V 100 1200 4.5V 80 1000 4.0V A) (D60 6.0V 800 3.5V ID4200 55443.....50505VVVVV I(A)DD640000 32..05VV details. 32..05VV or 0 200 n f 0 50 Freque1n0cy0(kHz) 150 200 0 ectio 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 s s Frequency(MHz) hi of t e g a p st e fir e S s. e pl m a s x atri m n o d e s a b a at D  1997-2013 Microchip Technology Inc. DS30234E-page 285

PIC16C6X Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 FIGURE 23-29:TYPICAL IDD vs. FREQUENCY FIGURE 23-30:MAXIMUM IDD vs. (HS MODE, 25°C) FREQUENCY (HS MODE, -40°C TO 85°C) 7.0 7.0 6.0 6.0 5.0 5.0 A)4.0 (mDD3.0 mA)4.0 I (DD3.0 2.0 6.0V I 5.5V 5.0V 2.0 6.0V 1.0 4.5V 5.5V 4.0V 5.0V 1.0 4.5V 0.0 4.0V 1 2 4 6 8 10 12 14 16 18 20 0.0 Frequency(MHz) 1 2 4 6 8 10 12 14 16 18 20 Frequency(MHz) s. ail et d or n f o cti e s s hi of t e g a p st e fir e S s. e pl m a s x atri m n o d e s a b a at D DS30234E-page 286  1997-2013 Microchip Technology Inc.

PIC16C6X 24.0 PACKAGING INFORMATION 24.1 18-Lead Plastic Dual In-line (300 mil) (P) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N  C E1 E eA Pin No. 1 eB Indicator Area D S S1 Base Plane Seating Plane L B1 e1 A1 A2 A B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 10 0 10 A – 4.064 – 0.160 A1 0.381 – 0.015 – A2 3.048 3.810 0.120 0.150 B 0.355 0.559 0.014 0.022 B1 1.524 1.524 Reference 0.060 0.060 Reference C 0.203 0.381 Typical 0.008 0.015 Typical D 22.479 23.495 0.885 0.925 D1 20.320 20.320 Reference 0.800 0.800 Reference E 7.620 8.255 0.300 0.325 E1 6.096 7.112 0.240 0.280 e1 2.489 2.591 Typical 0.098 0.102 Typical eA 7.620 7.620 Reference 0.300 0.300 Reference eB 7.874 9.906 0.310 0.390 L 3.048 3.556 0.120 0.140 N 18 18 18 18 S 0.889 – 0.035 – S1 0.127 – 0.005 –  1997-2013 Microchip Technology Inc. DS30234E-page 287

PIC16C6X 24.2 28-Lead Plastic Dual In-line (300 mil) (SP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N  E1 E C Pin No. 1 eA Indicator eB Area B2 B1 D S Base Plane Seating Plane L Detail A e1 A1 A2 A B3 B D1 Detail A Package Group: Plastic Dual In-Line (PLA) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 10 0 10 A 3.632 4.572 0.143 0.180 A1 0.381 – 0.015 – A2 3.175 3.556 0.125 0.140 B 0.406 0.559 0.016 0.022 B1 1.016 1.651 Typical 0.040 0.065 Typical B2 0.762 1.016 4 places 0.030 0.040 4 places B3 0.203 0.508 4 places 0.008 0.020 4 places C 0.203 0.331 Typical 0.008 0.013 Typical D 34.163 35.179 1.385 1.395 D1 33.020 33.020 Reference 1.300 1.300 Reference E 7.874 8.382 0.310 0.330 E1 7.112 7.493 0.280 0.295 e1 2.540 2.540 Typical 0.100 0.100 Typical eA 7.874 7.874 Reference 0.310 0.310 Reference eB 8.128 9.652 0.320 0.380 L 3.175 3.683 0.125 0.145 N 28 28 28 28 S 0.584 1.220 0.023 0.048 DS30234E-page 288  1997-2013 Microchip Technology Inc.

PIC16C6X 24.3 40-Lead Plastic Dual In-line (600 mil) (P) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N  E1 E C Pin No. 1 eA Indicator eB Area D S S1 Base Plane Seating Plane L B1 e1 A1 A2 A B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 10 0 10 A – 5.080 – 0.200 A1 0.381 – 0.015 – A2 3.175 4.064 0.125 0.160 B 0.355 0.559 0.014 0.022 B1 1.270 1.778 Typical 0.050 0.070 Typical C 0.203 0.381 Typical 0.008 0.015 Typical D 51.181 52.197 2.015 2.055 D1 48.260 48.260 Reference 1.900 1.900 Reference E 15.240 15.875 0.600 0.625 E1 13.462 13.970 0.530 0.550 e1 2.489 2.591 Typical 0.098 0.102 Typical eA 15.240 15.240 Reference 0.600 0.600 Reference eB 15.240 17.272 0.600 0.680 L 2.921 3.683 0.115 0.145 N 40 40 40 40 S 1.270 – 0.050 – S1 0.508 – 0.020 –  1997-2013 Microchip Technology Inc. DS30234E-page 289

PIC16C6X 24.4 18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e B h x 45 N Index Area E H  C Chamfer L h x 45 1 2 3 D CP Base Seating Plane Plane A1 A Package Group: Plastic SOIC (SO) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 8 0 8 A 2.362 2.642 0.093 0.104 A1 0.101 0.300 0.004 0.012 B 0.355 0.483 0.014 0.019 C 0.241 0.318 0.009 0.013 D 11.353 11.735 0.447 0.462 E 7.416 7.595 0.292 0.299 e 1.270 1.270 Reference 0.050 0.050 Reference H 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 L 0.406 1.143 0.016 0.045 N 18 18 18 18 CP – 0.102 – 0.004 DS30234E-page 290  1997-2013 Microchip Technology Inc.

PIC16C6X 24.5 28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e B h x 45 N Index Area E H  C Chamfer L h x 45 1 2 3 D CP Base Seating Plane Plane A1 A Package Group: Plastic SOIC (SO) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 8 0 8 A 2.362 2.642 0.093 0.104 A1 0.101 0.300 0.004 0.012 B 0.355 0.483 0.014 0.019 C 0.241 0.318 0.009 0.013 D 17.703 18.085 0.697 0.712 E 7.416 7.595 0.292 0.299 e 1.270 1.270 Typical 0.050 0.050 Typical H 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 L 0.406 1.143 0.016 0.045 N 28 28 28 28 CP – 0.102 – 0.004  1997-2013 Microchip Technology Inc. DS30234E-page 291

PIC16C6X 24.6 18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N  C E1 E eA Pin No. 1 eB Indicator Area D S S1 Base Plane Seating Plane L B1 e1 A1 A3 A A2 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 10 0 10 A — 5.080 — 0.200 A1 0.381 1.778 0.015 0.070 A2 3.810 4.699 0.150 0.185 A3 3.810 4.445 0.150 0.175 B 0.355 0.585 0.014 0.023 B1 1.270 1.651 Typical 0.050 0.065 Typical C 0.203 0.381 Typical 0.008 0.015 Typical D 22.352 23.622 0.880 0.930 D1 20.320 20.320 Reference 0.800 0.800 Reference E 7.620 8.382 0.300 0.330 E1 5.588 7.874 0.220 0.310 e1 2.540 2.540 Reference 0.100 0.100 Reference eA 7.366 8.128 Typical 0.290 0.320 Typical eB 7.620 10.160 0.300 0.400 L 3.175 3.810 0.125 0.150 N 18 18 18 18 S 0.508 1.397 0.020 0.055 S1 0.381 1.270 0.015 0.050 DS30234E-page 292  1997-2013 Microchip Technology Inc.

PIC16C6X 24.7 28-Lead Ceramic CERDIP Dual In-line withWindow (300 mil)) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 E  C Pin No. 1 Indicator eA Area eB D D1 Base Plane Seating Plane L B1 e1 A1 A2 A B D2 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 10 0 10 A 3.30 5.84 .130 0.230 A1 0.38 — 0.015 — A2 2.92 4.95 0.115 0.195 B 0.35 0.58 0.014 0.023 B1 1.14 1.78 Typical 0.045 0.070 Typical C 0.20 0.38 Typical 0.008 0.015 Typical D 34.54 37.72 1.360 1.485 D2 32.97 33.07 Reference 1.298 1.302 Reference E 7.62 8.25 0.300 0.325 E1 6.10 7.87 0.240 0.310 e 2.54 2.54 Typical 0.100 0.100 Typical eA 7.62 7.62 Reference 0.300 0.300 Reference eB — 11.43 — 0.450 L 2.92 5.08 0.115 0.200 N 28 28 28 28 D1 0.13 — 0.005 —  1997-2013 Microchip Technology Inc. DS30234E-page 293

PIC16C6X 24.8 40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N E1 E  C Pin No. 1 Indicator eA Area eB D S S1 Base Plane Seating Plane L B1 e1 A1 A3 A A2 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 10 0 10 A 4.318 5.715 0.170 0.225 A1 0.381 1.778 0.015 0.070 A2 3.810 4.699 0.150 0.185 A3 3.810 4.445 0.150 0.175 B 0.355 0.585 0.014 0.023 B1 1.270 1.651 Typical 0.050 0.065 Typical C 0.203 0.381 Typical 0.008 0.015 Typical D 51.435 52.705 2.025 2.075 D1 48.260 48.260 Reference 1.900 1.900 Reference E 15.240 15.875 0.600 0.625 E1 12.954 15.240 0.510 0.600 e1 2.540 2.540 Reference 0.100 0.100 Reference eA 14.986 16.002 Typical 0.590 0.630 Typical eB 15.240 18.034 0.600 0.710 L 3.175 3.810 0.125 0.150 N 40 40 40 40 S 1.016 2.286 0.040 0.090 S1 0.381 1.778 0.015 0.070 DS30234E-page 294  1997-2013 Microchip Technology Inc.

PIC16C6X 24.9 28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil) (JW) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N C E1 E eA Pin #1  eB Indicator Area D S1 S Base Plane Seating A3 A2 Plane L A1 A B1 e1 B D1 Package Group: Ceramic Side Brazed Dual In-Line (CER) Millimeters Inches Symbol Min Max Notes Min Max Notes  0 10 0 10 A 3.937 5.030 0.155 0.198 A1 1.016 1.524 0.040 0.060 A2 2.921 3.506 0.115 0.138 A3 1.930 2.388 0.076 0.094 B 0.406 0.508 0.016 0.020 B1 1.219 1.321 Typical 0.048 0.052 C 0.228 0.305 Typical 0.009 0.012 D 35.204 35.916 1.386 1.414 D1 32.893 33.147 Reference 1.295 1.305 E 7.620 8.128 0.300 0.320 E1 7.366 7.620 0.290 0.300 e1 2.413 2.667 Typical 0.095 0.105 eA 7.366 7.874 Reference 0.290 0.310 eB 7.594 8.179 0.299 0.322 L 3.302 4.064 0.130 0.160 N 28 28 28 28 S 1.143 1.397 0.045 0.055 S1 0.533 0.737 0.021 0.029  1997-2013 Microchip Technology Inc. DS30234E-page 295

PIC16C6X 24.10 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N Index area E H  C L 1 2 3 e B A Base plane CP Seating plane D A1 Package Group: Plastic SSOP Millimeters Inches Symbol Min Max Notes Min Max Notes  0 8 0 8 A 1.730 1.990 0.068 0.078 A1 0.050 0.210 0.002 0.008 B 0.250 0.380 0.010 0.015 C 0.130 0.220 0.005 0.009 D 10.070 10.330 0.396 0.407 E 5.200 5.380 0.205 0.212 e 0.650 0.650 Reference 0.026 0.026 Reference H 7.650 7.900 0.301 0.311 L 0.550 0.950 0.022 0.037 N 28 28 28 28 CP - 0.102 - 0.004 DS30234E-page 296  1997-2013 Microchip Technology Inc.

PIC16C6X 24.11 44-Lead Plastic Leaded Chip Carrier (Square) (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D 0.812/0.661 N Pics 0.177 1.27 .032/.026 .007 S BD-E S .050 -A- 2 Sides -H- 0.0.10777S BAS D1 A A1 2 Sides -D- 3 DD3/2E3 D 0..010041 SPleaanteing 9 3 0.0.3185 F-G S 4 -C- -F3- 8 -G- E2 E1 E 0.38 .015 F-G S 4 -B- 3 -E- 0.177 .007 S AF-G S 10 0.812/0.661 0.254 0.254 .032/.026 3 .010 Max 11 .010 Max 11 2 -H- 0..052008 0..052008 -H- 2 1.0.56204Min 6 6 -C- 5 1.0.66551 1.0.66551 0.0.2645 Min 0..052331//.00.13331 R 1.14/0.64 R1.14/0.64 .045/.025 .045/.025 0.0.10777M A F-G S,D-E S Package Group: Plastic Leaded Chip Carrier (PLCC) Millimeters Inches Symbol Min Max Notes Min Max Notes A 4.191 4.572 0.165 0.180 A1 2.413 2.921 0.095 0.115 D 17.399 17.653 0.685 0.695 D1 16.510 16.663 0.650 0.656 D2 15.494 16.002 0.610 0.630 D3 12.700 12.700 Reference 0.500 0.500 Reference E 17.399 17.653 0.685 0.695 E1 16.510 16.663 0.650 0.656 E2 15.494 16.002 0.610 0.630 E3 12.700 12.700 Reference 0.500 0.500 Reference N 44 44 44 44 CP – 0.102 – 0.004 LT 0.203 0.381 0.008 0.015  1997-2013 Microchip Technology Inc. DS30234E-page 297

PIC16C6X 24.12 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) (PQ) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 M CA-BS D S 4D 0.20 M HA-BS D S D1 5 7 0.05 mm/mm A-B 0.20 min. D3 0.13 R min. Index area 6 PARTING LINE 0.13/0.30 R 9 b  L C E3 E1 E 1.60 Ref. 0.20 M CA-B S D S 4 TYP 4x 10 e B 0.20 M HA-B S D S 5 7 0.05 mm/mm D A2 A Base Plane Seating Plane A1 Package Group: Plastic MQFP Millimeters Inches Symbol Min Max Notes Min Max Notes  0 7 0 7 A 2.000 2.350 0.078 0.093 A1 0.050 0.250 0.002 0.010 A2 1.950 2.100 0.768 0.083 b 0.300 0.450 Typical 0.011 0.018 Typical C 0.150 0.180 0.006 0.007 D 12.950 13.450 0.510 0.530 D1 9.900 10.100 0.390 0.398 D3 8.000 8.000 Reference 0.315 0.315 Reference E 12.950 13.450 0.510 0.530 E1 9.900 10.100 0.390 0.398 E3 8.000 8.000 Reference 0.315 0.315 Reference e 0.800 0.800 0.031 0.032 L 0.730 1.030 0.028 0.041 N 44 44 44 44 CP 0.102 – 0.004 – DS30234E-page 298  1997-2013 Microchip Technology Inc.

PIC16C6X 24.13 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) (TQ) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 1.0ø (0.039ø) Ref. 11/13(4x) Pin#1 Pin#1 2 2 0 Min E E1  11/13(4x) Detail B e 3.0ø (0.118ø) Ref. R1 0.08 Min Option 1 (TOP side) R 0.08/0.20 Option 2 (TOP side) Gage Plane A1 0.250 Base Metal Lead Finish A2 A b S L 0.20 Detail A L c c1 L1 Min Detail B 1.00 Ref. 1.00 Ref b1 Detail A Detail B Package Group: Plastic TQFP Millimeters Inches Symbol Min Max Notes Min Max Notes A 1.00 1.20 0.039 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 D 11.75 12.25 0.463 0.482 D1 9.90 10.10 0.390 0.398 E 11.75 12.25 0.463 0.482 E1 9.90 10.10 0.390 0.398 L 0.45 0.75 0.018 0.030 e 0.80 BSC 0.031 BSC b 0.30 0.45 0.012 0.018 b1 0.30 0.40 0.012 0.016 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 N 44 44 44 44  0 7 0 7 Note1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per side. D1 and E1 dimensions including mold mismatch. 2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m (0.003”)max. 3: This outline conforms to JEDEC MS-026.  1997-2013 Microchip Technology Inc. DS30234E-page 299

PIC16C6X 24.14 Package Marking Information 18-Lead PDIP Example MMMMMMMMMMMMM PIC16C61-04/P XXXXXXXXXXXXXXXX AABBCDE 9450CBA 18-Lead SOIC Example MMMMMMMMMM PIC16C61 XXXXXXXXXXXX -20/SO XXXXXXXXXXXX AABBCDE 9449CBA 18-Lead CERDIP Windowed Example MMMMMM PIC16C61 XXXXXXXX /JW AABBCDE 9440CBT 28-Lead PDIP (.300 MIL) Example XXXXXXXXXXXXXXXXX PIC16C63-04I/SP XXXXXXXXXXXXXXXXX AABBCAE 9452CAN Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calender year) BB Week code (week of January 1 is week '01’) C Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 Mask revision number for microcontroller D2 Mask revision number for EEPROM E Assembly code of the plant or country of origin in which part was assembled. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30234E-page 300  1997-2013 Microchip Technology Inc.

PIC16C6X Package Marking Information (Cont’d) 28-Lead SOIC Example MMMMMMMMMMMMMMMMMMXX PIC16C62-20/S0111 XXXXXXXXXXXXXXXXXXXX AABBCAE 9515SBA 28-Lead CERDIP Skinny Windowed Example XXXXXXXXXXXXXX PIC16C62/JW XXXXXXXXXXXXXX AABBCDE 9517SBT 28-Lead Side Brazed Skinny Windowed Example XXXXXXXXXXX PIC16C66/JW XXXXXXXXXXX AABBCDE 9517CAT 28-Lead SSOP Example XXXXXXXXXXXX PIC16C62 XXXXXXXXXXXX 20I/SS025 AABBCAE 9517SBP 40-Lead PDIP Example MMMMMMMMMMMMMM PIC16C65-04/P XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX AABBCDE 9510CAA Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calender year) BB Week code (week of January 1 is week '01’) C Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  1997-2013 Microchip Technology Inc. DS30234E-page 301

PIC16C6X Package Marking Information (Cont’d) 40-Lead CERDIP Windowed Example MMMMMMMMM PIC16C67/JW XXXXXXXXXXX XXXXXXXXXXX AABBCDE 9450CAT 44-Lead PLCC Example MMMMMMMM PIC16C64 XXXXXXXXXX -20/L XXXXXXXXXX AABBCDE 9442CAN 44-Lead MQFP Example MMMMMMMM PIC16C64 XXXXXXXXXX -04/PQ XXXXXXXXXX AABBCDE 9444CAP 44-Lead TQFP Example MMMMMMMM PIC16C64A XXXXXXXXXX -10/TQ XXXXXXXXXX AABBCDE AABBCDE Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calender year) BB Week code (week of January 1 is week '01’) C Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. D1 Mask revision number for microcontroller E Assembly code of the plant or country of origin in which part was assembled. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30234E-page 302  1997-2013 Microchip Technology Inc.

PIC16C6X APPENDIX A:MODIFICATIONS APPENDIX B:COMPATIBILITY The following are the list of modifications over the To convert code written for PIC16C5X to PIC16CXX, PIC16C5X microcontroller family: the user should take the following steps: 1. Instruction word length is increased to 14-bits. 1. Remove any program memory page select This allows larger page sizes both in program operations (PA2, PA1, PA0 bits) for CALL, memory (2K now as opposed to 512 before) and GOTO. register file (128 bytes now versus 32 bytes 2. Revisit any computed jump operations (write to before). PC or add to PC, etc.) to make sure page bits 2. A PC high latch register (PCLATH) is added to are set properly under the new scheme. handle program memory paging. PA2, PA1, PA0 3. Eliminate any data memory page switching. bits are removed from STATUS register. Redefine data variables to reallocate them. 3. Data memory paging is redefined slightly. STA- 4. Verify all writes to STATUS, OPTION, and FSR TUS register is modified. registers since these have changed. 4. Four new instructions have been added: 5. Change reset vector to 0000h. RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compati- bility with PIC16C5X. 5. OPTION and TRIS registers are made address- able. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8 deep. 8. Reset vector is changed to 0000h. 9. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Reg- isters are reset differently. 10. Wake-up from SLEEP through interrupt is added. 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT), are included for more reliable power-up. These tim- ers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. PORTB has weak pull-ups and interrupt on change feature. 13. Timer0 pin is also a port pin (RA4/T0CKI) now. 14. FSR is made a full 8-bit register. 15. “In-circuit programming” is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out). 16. Power Control register (PCON) is added with a Power-on Reset status bit (POR).(Not on the PIC16C61). 17. Brown-out Reset has been added to the follow- ing devices: PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/ 67.  1997-2013 Microchip Technology Inc. DS30234E-page 303

PIC16C6X APPENDIX C:WHAT’S NEW APPENDIX D:WHAT’S CHANGED Added PIC16CR63 and PIC16CR65 devices. Minor changes, spelling and grammatical changes. Added PIC16C66 and PIC16C67 devices. The Divided SPI section into SPI for the PIC16C66/67 PIC16C66/67 devices have 368 bytes of data memory (Section11.3) and SPI for all other devices distributed in 4 banks and 8K of program memory in 4 (Section11.2). pages. These two devices have an enhanced SPI that Added the following note for the USART. This applies to supports both clock phase and polarity. The USART all devices except the PIC16C66 and PIC16C67. has been enhanced. For the PIC16C63/R63/65/65A/R65 the asynchronous When upgrading to the PIC16C66/67 please note that high speed mode (BRGH = 1) may experience a high the upper 16 bytes of data memory in banks 1,2, and 3 rate of receive errors. It is recommended that BRGH = are mapped into bank 0. This may require relocation of 0. If you desire a higher baud rate than BRGH = 0 can data memory usage in the user application code. support, refer to the device errata for additional infor- Q-cycles for instruction execution were added to Sec- mation or use the PIC16C66/67. tion 14.0 Instruction Set Summary. APPENDIX E:REVISION E January 2013 - Added a note to each package drawing. DS30234E-page 304  1997-2013 Microchip Technology Inc.

PIC16C6X APPENDIX F: PIC16/17 MICROCONTROLLERS F.1 PIC12CXXX Family of Devices PIC12C508 PIC12C509 PIC12C671 PIC12C672 Maximum Frequency 4 4 4 4 Clock of Operation (MHz) EPROM Program Memory 512 x 12 1024 x 12 1024 x 14 2048 x 14 Memory Data Memory (bytes) 25 41 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 Peripherals A/D Converter (8-bit) Channels — — 4 4 Wake-up from SLEEP on Yes Yes Yes Yes pin change I/O Pins 5 5 5 5 Input Pins 1 1 1 1 Features Internal Pull-ups Yes Yes Yes Yes Voltage Range (Volts) 2.5-5.5 2.5-5.5 2.5-5.5 2.5-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Number of Instructions 33 33 35 35 Packages 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC 8-pin DIP, SOIC All PIC12C5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12C5XX devices use serial programming with data pin GP1 and clock pin GP0. F.2 PIC14C000 Family of Devices PIC14C000 Clock Maximum Frequency of Operation (MHz) 20 EPROM Program Memory (x14 words) 4K Data Memory (bytes) 192 Memory Timer Module(s) TMR0 ADTMR Serial Port(s) I2C with SMBus Peripherals (SPI/I2C, USART) Support Slope A/D Converter Channels 8 External; 6 Internal Interrupt Sources 11 I/O Pins 22 Voltage Range (Volts) 2.7-6.0 Features In-Circuit Serial Programming Yes Additional On-chip Features Internal 4MHz Oscillator, Bandgap Reference,Temperature Sensor, Calibration Factors, Low Voltage Detector, SLEEP, HIBERNATE, Comparators with Programmable References (2) Packages 28-pin DIP (.300 mil), SOIC, SSOP  1997-2013 Microchip Technology Inc. DS30234E-page 305

PIC16C6X F.3 PIC16C15X Family of Devices PIC16C154 PIC16CR154 PIC16C156 PIC16CR156 PIC16C158 PIC16CR158 Maximum Frequency 20 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 512 — 1K — 2K — (x12 words) Memory ROM Program Memory — 512 — 1K — 2K (x12 words) RAM Data Memory (bytes) 25 25 25 25 73 73 Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 12 12 12 12 Voltage Range (Volts) 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 3.0-5.5 2.5-5.5 Features Number of Instructions 33 33 33 33 33 33 Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. F.4 PIC16C5X Family of Devices PIC16C52 PIC16C54 PIC16C54A PIC16CR54A PIC16C55 PIC16C56 Maximum Frequency 4 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 384 512 512 — 512 1K (x12 words) Memory ROM Program Memory — — — 512 — — (x12 words) RAM Data Memory (bytes) 25 25 25 25 24 25 Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 12 12 20 12 Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.25 Features Number of Instructions 33 33 33 33 33 33 Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin DIP, 18-pin DIP, SOIC SOIC; SOIC; SOIC; SOIC, SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP SSOP 20-pin SSOP PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A Maximum Frequency 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 2K — 2K — (x12 words) Memory ROM Program Memory — 2K — 2K (x12 words) RAM Data Memory (bytes) 72 72 73 73 Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 I/O Pins 20 20 12 12 Voltage Range (Volts) 2.5-6.25 2.5-6.25 2.0-6.25 2.5-6.25 Features Number of Instructions 33 33 33 33 Packages 28-pin DIP, 28-pin DIP, SOIC, 18-pin DIP, SOIC; 18-pin DIP, SOIC; SOIC, SSOP 20-pin SSOP 20-pin SSOP SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high I/O current capability. DS30234E-page 306  1997-2013 Microchip Technology Inc.

PIC16C6X F.5 PIC16C55X Family of Devices PIC16C554 PIC16C556(1) PIC16C558 Clock Maximum Frequency of Operation (MHz) 20 20 20 EPROM Program Memory (x14 words) 512 1K 2K Memory Data Memory (bytes) 80 80 128 Timer Module(s) TMR0 TMR0 TMR0 Peripherals Comparators(s) — — — Internal Reference Voltage — — — Interrupt Sources 3 3 3 I/O Pins 13 13 13 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 Features Brown-out Reset — — — Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. F.6 PIC16C62X and PIC16C64X Family of Devices PIC16C620 PIC16C621 PIC16C622 PIC16C642 PIC16C662 Maximum Frequency 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 512 1K 2K 4K 4K Memory (x14 words) Data Memory (bytes) 80 80 128 176 176 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 Peripherals Comparators(s) 2 2 2 2 2 Internal Reference Voltage Yes Yes Yes Yes Yes Interrupt Sources 4 4 4 4 5 I/O Pins 13 13 13 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 3.0-6.0 3.0-6.0 Brown-out Reset Yes Yes Yes Yes Yes Features Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin PDIP, 40-pin PDIP, SOIC; SOIC; SOIC; SOIC, Windowed 20-pin SSOP 20-pin SSOP 20-pin SSOP Windowed CDIP; CDIP 44-pin PLCC, MQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C62X and PIC16C64X Family devices use serial programming with clock pin RB6 and data pin RB7.  1997-2013 Microchip Technology Inc. DS30234E-page 307

PIC16C6X F.7 PIC16C7XX Family of Devces PIC16C710 PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72(1) Maximum Frequency 20 20 20 20 20 20 Clock of Operation (MHz) EPROM Program Memory 512 1K 1K 2K 2K — (x14 words) Memory ROM Program Memory — — — — — 2K (14K words) Data Memory (bytes) 36 36 68 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0, TMR0, TMR1, TMR1, TMR2 TMR2 Capture/Compare/ — — — — 1 1 Peripherals PWM Module(s) Serial Port(s) — — — — SPI/I2C SPI/I2C (SPI/I2C, USART) Parallel Slave Port — — — — — — A/D Converter (8-bit) Channels 4 4 4 4 5 5 Interrupt Sources 4 4 4 4 8 8 I/O Pins 13 13 13 13 22 22 Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5 Features In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown-out Reset Yes — Yes Yes Yes Yes Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP, SOIC; SOIC SOIC; SOIC; SOIC, SSOP SOIC, SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP PIC16C73A PIC16C74A PIC16C76 PIC16C77 Maximum Frequency of Oper- 20 20 20 20 Clock ation (MHz) EPROM Program Memory 4K 4K 8K 8K Memory (x14 words) Data Memory (bytes) 192 192 368 368 Timer Module(s) TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR2 TMR2 TMR2 TMR2 Capture/Compare/PWM Mod- 2 2 2 2 Peripherals ule(s) Serial Port(s) (SPI/I2C, SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART SPI/I2C, USART USART) Parallel Slave Port — Yes — Yes A/D Converter (8-bit) Channels 5 8 5 8 Interrupt Sources 11 12 11 12 I/O Pins 22 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 Features In-Circuit Serial Programming Yes Yes Yes Yes Brown-out Reset Yes Yes Yes Yes Packages 28-pin SDIP, 40-pin DIP; 28-pin SDIP, 40-pin DIP; SOIC 44-pin PLCC, SOIC 44-pin PLCC, MQFP, TQFP MQFP, TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capabil- ity. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales office for availability of these devices. DS30234E-page 308  1997-2013 Microchip Technology Inc.

PIC16C6X F.8 PIC16C8X Family of Devices PIC16F83 PIC16CR83 PIC16F84 PIC16CR84 Maximum Frequency 10 10 10 10 Clock of Operation (MHz) Flash Program Memory 512 — 1K — EEPROM Program Memory — — — — Memory ROM Program Memory — 512 — 1K Data Memory (bytes) 36 36 68 68 Data EEPROM (bytes) 64 64 64 64 Peripher- Timer Module(s) TMR0 TMR0 TMR0 TMR0 als Interrupt Sources 4 4 4 4 I/O Pins 13 13 13 13 Features Voltage Range (Volts) 2.0-6.0 2.0-6.0 2.0-6.0 2.0-6.0 Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC SOIC SOIC SOIC All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capabil- ity. All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7. F.9 PIC16C9XX Family Of Devices PIC16C923 PIC16C924 Clock Maximum Frequency of Operation (MHz) 8 8 EPROM Program Memory 4K 4K Memory Data Memory (bytes) 176 176 Timer Module(s) TMR0, TMR0, TMR1, TMR1, TMR2 TMR2 Capture/Compare/PWM Module(s) 1 1 Serial Port(s) SPI/I2C SPI/I2C Peripherals (SPI/I2C, USART) Parallel Slave Port — — A/D Converter (8-bit) Channels — 5 LCD Module 4 Com, 4 Com, 32 Seg 32 Seg Interrupt Sources 8 9 I/O Pins 25 25 Input Pins 27 27 Voltage Range (Volts) 3.0-6.0 3.0-6.0 Features In-Circuit Serial Programming Yes Yes Brown-out Reset — — Packages 64-pin SDIP(1), 64-pin SDIP(1), TQFP; TQFP; 68-pin PLCC, 68-pin PLCC, Die Die All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa- bility. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7.  1997-2013 Microchip Technology Inc. DS30234E-page 309

PIC16C6X F.10 PIC17CXXX Family of Devices PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44 Maximum Frequency 33 33 33 33 33 Clock of Operation (MHz) EPROM Program Memory 2K — 4K — 8K (words) Memory ROM Program Memory — 2K — 4K — (words) RAM Data Memory (bytes) 232 232 454 454 454 Timer Module(s) TMR0, TMR0, TMR0, TMR0, TMR0, TMR1, TMR1, TMR1, TMR1, TMR1, TMR2, TMR2, TMR2, TMR2, TMR2, Peripherals TMR3 TMR3 TMR3 TMR3 TMR3 Captures/PWM Module(s) 2 2 2 2 2 Serial Port(s) (USART) Yes Yes Yes Yes Yes Hardware Multiply Yes Yes Yes Yes Yes External Interrupts Yes Yes Yes Yes Yes Interrupt Sources 11 11 11 11 11 I/O Pins 33 33 33 33 33 Features Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 Number of Instructions 58 58 58 58 58 Packages 40-pin DIP; 40-pin DIP; 40-pin DIP; 40-pin DIP; 40-pin DIP; 44-pin PLCC, 44-pin PLCC, 44-pin PLCC, 44-pin PLCC, 44-pin PLCC, MQFP, TQFP MQFP, TQFP MQFP, TQFP MQFP, TQFP MQFP, TQFP PIC17C752 PIC17C756 Maximum Frequency 33 33 Clock of Operation (MHz) EPROM Program Memory 8K 16K (words) Memory ROM Program Memory — — (words) RAM Data Memory (bytes) 454 902 Timer Module(s) TMR0, TMR0, TMR1, TMR1, TMR2, TMR2, Peripherals TMR3 TMR3 Captures/PWM Module(s) 4/3 4/3 Serial Port(s) (USART) 2 2 Hardware Multiply Yes Yes External Interrupts Yes Yes Interrupt Sources 18 18 I/O Pins 50 50 Features Voltage Range (Volts) 3.0-6.0 3.0-6.0 Number of Instructions 58 58 Packages 64-pin DIP; 64-pin DIP; 68-pin LCC, 68-pin LCC, 68-pin TQFP 68-pin TQFP All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. DS30234E-page 310  1997-2013 Microchip Technology Inc.

PIC16C6X PIN COMPATIBILITY Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex.,PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55. Pin compatibility does not mean that the devices offer the same features. As an example, the PIC16C54 is pin compatible with the PIC16C71, but does not have an A/D converter, weak pull-ups on PORTB, or interrupts. TABLE F-1: PIN COMPATIBLE DEVICES Pin Compatible Devices Package PIC12C508, PIC12C509, PIC12C671, PIC12C672 8-pin PIC16C154, PIC16CR154, PIC16C156, 18-pin, PIC16CR156, PIC16C158, PIC16CR158, 20-pin PIC16C52, PIC16C54, PIC16C54A, PIC16CR54A, PIC16C56, PIC16C58A, PIC16CR58A, PIC16C61, PIC16C554, PIC16C556, PIC16C558 PIC16C620, PIC16C621, PIC16C622 PIC16C641, PIC16C642, PIC16C661, PIC16C662 PIC16C710, PIC16C71, PIC16C711, PIC16C715 PIC16F83, PIC16CR83, PIC16F84A, PIC16CR84 PIC16C55, PIC16C57, PIC16CR57B 28-pin PIC16CR62, PIC16C62A, PIC16C63, PIC16CR63, 28-pin PIC16C66, PIC16C72, PIC16C73A, PIC16C76 PIC16CR64, PIC16C64A, PIC16C65A, 40-pin PIC16CR65, PIC16C67, PIC16C74A, PIC16C77 PIC17CR42, PIC17C42A, 40-pin PIC17C43, PIC17CR43, PIC17C44 PIC16C923, PIC16C924 64/68-pin PIC17C756, PIC17C752 64/68-pin  1997-2013 Microchip Technology Inc. DS30234E-page 311

PIC16C6X NOTES: DS30234E-page 312  1997-2013 Microchip Technology Inc.

PIC16C6X INDEX SPI Master/Slave Connection.....................................87 SSP in I2C Mode........................................................99 Numerics SSP in SPI Mode..................................................86, 91 Timer0........................................................................65 9-bit Receive Enable bit, RX9...........................................106 Timer0/WDT Prescaler...............................................68 9-bit Transmit Enable bit, TX9..........................................105 Timer1........................................................................72 9th bit of received data, RX9D..........................................106 Timer2........................................................................75 9th bit of transmit data, TX9D...........................................105 USART Receive.......................................................114 A USART Transmit......................................................112 Watchdog Timer.......................................................140 Absolute Maximum BOR..................................................................................129 Ratings..............................163, 183, 199, 215, 231, 247, 263 BOR............................................................................47, 131 ACK.....................................................................96, 100, 101 BRGH...............................................................................105 ALU.......................................................................................9 Brown-out Reset (BOR)....................................................129 Application Notes Brown-out Reset Status bit, BOR.......................................47 AN552 (Implementing Wake-up on Key Stroke).........53 Buffer Full Status bit, BF...............................................84, 89 AN556 (Implementing a Table Read).........................48 AN594 (Using the CCP Modules)...............................77 C Architectural Overview..........................................................9 C.........................................................................................35 B C Compiler........................................................................161 Capture Baud Rate Formula...........................................................107 Block Diagram............................................................78 Baud Rate Generator........................................................107 Mode...........................................................................78 Baud Rates Pin Configuration........................................................78 Asynchronous Mode.................................................108 Prescaler....................................................................79 Error, Calculating......................................................107 Software Interrupt.......................................................78 RX Pin Sampling, Timing Diagrams..................110, 111 Capture Interrupt................................................................78 Sampling...................................................................110 Capture/Compare/PWM (CCP) Synchronous Mode...................................................108 Capture Mode.............................................................78 BF.........................................................................84, 89, 100 Capture Mode Block Diagram....................................78 Block Diagrams CCP1..........................................................................77 Capture Mode Operation............................................78 CCP2..........................................................................77 Compare Mode...........................................................79 Compare Mode...........................................................79 Crystal Oscillator, Ceramic Resonator......................125 Compare Mode Block Diagram..................................79 External Brown-out Protection..................................135 Overview.....................................................................63 External Parallel Resonant Crystal Circuit................127 Prescaler....................................................................79 External Power-on Reset..........................................135 PWM Block Diagram..................................................80 External Series Resonant Crystal Circuit..................127 I2C Mode.....................................................................99 PWM Mode.................................................................80 PWM, Example Frequencies/Resolutions..................81 In-circuit Programming Connections.........................142 Section........................................................................77 Interrupt Logic...........................................................137 Carry.....................................................................................9 On-chip Reset Circuit................................................128 Carry bit..............................................................................35 Parallel Slave Port, PORTD-PORTE..........................61 CCP Module Interaction......................................................77 PIC16C61...................................................................10 CCP pin Configuration........................................................78 PIC16C62...................................................................11 CCP to Timer Resource Use..............................................77 PIC16C62A.................................................................11 CCP1 Interrupt Enable bit, CCP1IE....................................38 PIC16C63...................................................................12 CCP1 Interrupt Flag bit, CCP1IF........................................41 PIC16C64...................................................................11 CCP1 Mode Select bits.......................................................78 PIC16C64A.................................................................11 CCP1CON............................................24, 26, 28, 30, 32, 34 PIC16C65...................................................................12 CCP1IE...............................................................................38 PIC16C65A.................................................................12 CCP1IF...............................................................................41 PIC16C66...................................................................13 CCP1M3:CCM1M0.............................................................78 PIC16C67...................................................................13 CCP1X:CCP1Y...................................................................78 PIC16CR62.................................................................11 PIC16CR63.................................................................12 CCP2 Interrupt Enable bit, CCP2IE....................................45 PIC16CR64.................................................................11 CCP2 Interrupt Flag bit, CCP2IF........................................46 PIC16CR65.................................................................12 CCP2 Mode Select bits.......................................................78 PORTC.......................................................................55 CCP2CON............................................24, 26, 28, 30, 32, 34 PORTD (I/O Mode).....................................................57 CCP2IE...............................................................................45 PORTE (I/O Mode).....................................................58 CCP2IF...............................................................................46 PWM...........................................................................80 CCP2M3:CCP2M0..............................................................78 RA3:RA0 pins.............................................................51 CCP2X:CCP2Y...................................................................78 RA4/T0CKI pin............................................................51 CCPR1H...............................................24, 26, 28, 30, 32, 34 RA5 pin.......................................................................51 CCPR1L...............................................24, 26, 28, 30, 32, 34 RB3:RB0 pins.............................................................54 CCPR2H...............................................24, 26, 28, 30, 32, 34 RB7:RB4 pins.......................................................53, 54 CCPR2L...............................................24, 26, 28, 30, 32, 34 RC Oscillator Mode...................................................127 CKE....................................................................................89 CKP..............................................................................85, 90  1997-2013 Microchip Technology Inc. DS30234E-page 313

PIC16C6X Clearing Interrupts...............................................................53 44-Lead Plastic Surface Mount (MQFP Clock Polarity Select bit, CKP.......................................85, 90 10x10mmBody1.6/0.15mmLeadForm).......302, 303 Clock Polarity, SPI Mode....................................................87 Device Varieties....................................................................7 Clock Source Select bit, CSRC.........................................105 Digit Carry.............................................................................9 Clocking Scheme................................................................18 Digit Carry bit......................................................................35 Code Examples Direct Addressing...............................................................49 Changing Between Capture Prescalers......................79 E Ensuring Interrupts are Globally Disabled................136 Indirect Addressing.....................................................49 Electrical Characteristics..163, 183, 199, 215, 231, 247, 263 Initializing PORTA.......................................................51 External Clock Synchronization, TMR0..............................67 Initializing PORTB.......................................................53 F Initializing PORTC.......................................................55 Loading the SSPBUF Register...................................86 Family of Devices Loading the SSPBUF register.....................................91 PIC12CXXX..............................................................309 Reading a 16-bit Free-running Timer..........................73 PIC14C000...............................................................309 Read-Modify-Write on an I/O Port...............................60 PIC16C15X...............................................................310 Saving Status, W, and PCLATH Registers...............139 PIC16C55X...............................................................311 Subroutine Call, Page0 to Page1................................49 PIC16C5X.................................................................310 Code Protection................................................................142 PIC16C62X and PIC16C64X....................................311 Compare PIC16C6X.....................................................................6 Block Diagram.............................................................79 PIC16C7XX..............................................................312 Mode...........................................................................79 PIC16C8X.................................................................313 Pin Configuration........................................................79 PIC16C9XX..............................................................313 Software Interrupt.......................................................79 PIC17CXX................................................................314 Special Event Trigger..................................................79 FERR................................................................................106 Computed GOTO................................................................48 Framing Error bit, FERR...................................................106 Configuration Bits..............................................................123 FSR.........................24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 Configuration Word, Diagram............................................124 Fuzzy Logic Dev. System (fuzzyTECH-MP)...........159, 161 Connecting Two Microcontrollers........................................87 G Continuous Receive Enable bit, CREN.............................106 CREN................................................................................106 General Description..............................................................5 CSRC................................................................................105 General Purpose Registers................................................20 GIE......................................................................................37 D Global Interrupt Enable bit, GIE..........................................37 D/A................................................................................84, 89 Graphs Data/Address bit, D/A....................................................84, 89 PIC16C6X.................................................................281 Data Memory PIC16C61.................................................................173 Organization................................................................20 H Section........................................................................20 Data Sheet High Baud Rate Select bit, BRGH....................................105 Compatibility.............................................................307 I Modifications.............................................................307 What’s New...............................................................308 I/O Ports, Section................................................................51 DC.......................................................................................35 I2C DC CHARACTERISTICS..164, 184, 200, 216, 232, 248, 264 Addressing................................................................100 Development Support.......................................................159 Addressing I2C Devices..............................................96 Development Tools...........................................................159 Arbitration...................................................................98 Block Diagram............................................................99 Device Drawings Clock Synchronization................................................98 18-Lead Ceramic CERDIP Dual In-line Combined Format.......................................................97 withWindow(300mil)...............................................296 I2C Operation..............................................................99 18-Lead Plastic Dual In-line (300 mil).......................291 I2C Overview...............................................................95 18-Lead Plastic Surface Mount Initiating and Terminating Data Transfer....................95 (SOIC-Wide, 300milBody)....................................294 Master Mode.............................................................103 28-Lead Ceramic CERDIP Dual In-line with Master-Receiver Sequence........................................97 Window (300 mil)).....................................................297 Master-Transmitter Sequence....................................97 28-Lead Ceramic Side Brazed Dual In-Line Mode...........................................................................99 withWindow(300mil)...............................................299 Mode Selection...........................................................99 28-Lead Plastic Dual In-line (300 mil).......................292 28-Lead Plastic Surface Mount Multi-master................................................................98 Multi-Master Mode....................................................103 (SOIC-Wide,300milBody).....................................295 Reception.................................................................101 28-Lead Plastic Surface Mount Reception Timing Diagram.......................................101 (SSOP-209milBody5.30mm)...............................300 SCL and SDA pins....................................................100 40-Lead Ceramic CERDIP Dual In-line Slave Mode...............................................................100 withWindow(600mil)...............................................298 START........................................................................95 40-Lead Plastic Dual In-line (600 mil).......................293 STOP....................................................................95, 96 44-Lead Plastic Leaded Chip Carrier (Square).........301 DS30234E-page 314  1997-2013 Microchip Technology Inc.

PIC16C6X Transfer Acknowledge................................................96 RB0/INT Timing Diagram.........................................138 Transmission.............................................................102 Receive Flag bit..........................................................42 ID Locations......................................................................142 Timer0........................................................................65 IDLE_MODE.....................................................................104 Timer0, Timing............................................................66 In-circuit Serial Programming............................................142 Timing Diagram, Wake-up from SLEEP...................142 INDF......................................................24, 26, 28, 30, 32, 34 TMR0........................................................................138 Indirect Addressing.............................................................49 USART Receive Enable bit........................................39 Instruction Cycle.................................................................18 USART Transmit Enable bit.......................................39 Instruction Flow/Pipelining..................................................18 USART Transmit Flag bit............................................42 Instruction Format.............................................................143 Wake-up...................................................................141 Instruction Set Wake-up from SLEEP..............................................141 ADDLW.....................................................................145 INTF....................................................................................37 ADDWF.....................................................................145 IRP......................................................................................35 ANDLW.....................................................................145 L ANDWF.....................................................................145 BCF...........................................................................146 Loading the Program Counter............................................48 BSF...........................................................................146 M BTFSC......................................................................146 BTFSS......................................................................147 MPASM Assembler...................................................159, 160 CALL.........................................................................147 MPLAB-C..........................................................................161 CLRF.........................................................................148 MPSIM Software Simulator.......................................159, 161 CLRW.......................................................................148 O CLRWDT...................................................................148 COMF.......................................................................149 OERR...............................................................................106 DECF........................................................................149 One-Time-Programmable Devices.......................................7 DECFSZ....................................................................149 OPCODE..........................................................................143 GOTO.......................................................................150 Open-Drain.........................................................................51 INCF..........................................................................150 OPTION................................................25, 27, 29, 31, 33, 34 INCFSZ.....................................................................151 Oscillator Start-up Timer (OST)................................123, 129 IORLW......................................................................151 Oscillators IORWF......................................................................152 Block Diagram, External Parallel Resonant Crystal.127 MOVF........................................................................152 Capacitor Selection....................................................73 MOVLW....................................................................152 Configuration............................................................125 MOVWF....................................................................152 External Crystal Circuit.............................................127 NOP..........................................................................153 HS.....................................................................125, 130 OPTION....................................................................153 LP.....................................................................125, 130 RETFIE.....................................................................153 RC, Block Diagram...................................................127 RETLW.....................................................................154 RC, Section..............................................................127 RETURN...................................................................154 XT.............................................................................125 RLF...........................................................................155 Overrun Error bit, OERR...................................................106 RRF...........................................................................155 P SLEEP......................................................................156 SUBLW.....................................................................156 P...................................................................................84, 89 SUBWF.....................................................................157 Packaging Information......................................................291 SWAPF.....................................................................157 Parallel Slave Port TRIS..........................................................................157 PORTD.......................................................................57 XORLW.....................................................................158 Section........................................................................61 XORWF.....................................................................158 Parallel Slave Port Interrupt Flag bit, PSPIF.......................43 Section......................................................................143 Parallel Slave Port Read/Write Interrupt Enable bit, PSPIE39 Summary Table.........................................................144 PCL.........................24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 INTCON..................24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 PCLATH...........24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 48 INTE....................................................................................37 PCON...........................................25, 27, 29, 31, 33, 34, 130 INTEDG..............................................................................36 PD...............................................................................35, 131 Interrupt Edge Select bit, INTEDG......................................36 PEIE...................................................................................37 Interrupt on Change Feature...............................................53 Peripheral Interrupt Enable bit, PEIE..................................37 Interrupts PICDEM-1 Low-Cost PIC16/17 Demo Board...........159, 160 Section......................................................................136 PICDEM-2 Low-Cost PIC16CXX Demo Board.........159, 160 CCP............................................................................78 PICDEM-3 Low-Cost PIC16C9XXX Demo Board............160 CCP1..........................................................................38 PICMASTER In-Circuit Emulator......................................159 CCP1 Flag bit..............................................................41 PICSTART Low-Cost Development System.....................159 CCP2 Enable bit.........................................................45 PIE1......................................................25, 27, 29, 31, 33, 34 CCP2 Flag bit..............................................................46 PIE2......................................................25, 27, 29, 31, 33, 34 Context Saving..........................................................139 Pin Compatible Devices....................................................315 Parallel Slave Port Flag bit..........................................43 Pin Functions Parallel Slave Prot Read/Write Enable bit..................39 MCLR/VPP..................................................................16 Port RB.......................................................................53 RB0/INT..............................................................54, 138  1997-2013 Microchip Technology Inc. DS30234E-page 315

PIC16C6X OSC1/CLKIN...............................................................16 Map.......................................................................19, 20 OSC2/CLKOUT...........................................................16 Organization...............................................................19 PORTA........................................................................52 Paging........................................................................48 PORTB........................................................................54 Section........................................................................19 PORTC.......................................................................55 Programming While In-circuit............................................142 PORTD.......................................................................57 PS2:PS0.............................................................................36 PORTE........................................................................59 PSA.....................................................................................36 RA4/T0CKI............................................................16, 52 PSPIE.................................................................................39 RA5/SS.................................................................16, 52 PSPIF.................................................................................43 RB0/INT................................................................16, 54 Pull-ups...............................................................................53 RB6...........................................................................142 PUSH..................................................................................48 RB7...........................................................................142 PWM RC0/T1OSI/T1CKI......................................................55 Block Diagram............................................................80 RC0/T1OSO/T1CKI..............................................16, 55 Calculations................................................................81 RC1/T1OSI.................................................................55 Mode...........................................................................80 RC1/T1OSI/CCP2.................................................16, 55 Output Timing.............................................................80 RC1/T1OSO................................................................55 PWM Least Significant bits.................................................78 RC2/CCP1......................................................16, 55, 56 Q RC3/SCK/SCL................................................16, 55, 56 RC4/SDI/SDA.................................................16, 55, 56 Quadrature Clocks..............................................................18 RC5/SDO........................................................16, 55, 56 Quick-Turnaround-Production..............................................7 RC6/TX/CK.....................................16, 55, 56, 105–120 R RC7/RX/DT.....................................16, 55, 56, 105–120 RD7/PSP7:RD0/PSP0..........................................17, 57 R/W bit............................................84, 89, 96, 100, 101, 102 RE0/RD...........................................................17, 59, 61 RA0 pin...............................................................................51 RE1/WR..........................................................17, 59, 61 RA1 pin...............................................................................51 RE2/CS...........................................................17, 59, 61 RA2 pin...............................................................................51 SCK.......................................................................86–88 RA3 pin...............................................................................51 SDI........................................................................86–88 RA4/T0CKI pin....................................................................51 SDO......................................................................86–88 RA5 pin...............................................................................51 SS.........................................................................86–88 RB Port Change Interrupt Enable bit, RBIE........................37 VDD..............................................................................17 RB Port Change Interrupt Flag bit, RBIF............................37 VSS..............................................................................17 RB0.....................................................................................54 PIR1......................................................24, 26, 28, 30, 32, 34 RB0/INT............................................................................138 PIR2......................................................24, 26, 28, 30, 32, 34 RB0/INT External Interrupt Enable bit, INTE......................37 POP.....................................................................................48 RB0/INT External Interrupt Flag bit, INTF...........................37 POR............................................................................47, 131 RB1.....................................................................................54 POR Time-Out Sequence on Power-Up...........................134 RB2.....................................................................................54 Port RB Interrupt.................................................................53 RB3.....................................................................................54 PORTA............................................24, 26, 28, 30, 32, 34, 51 RB4.....................................................................................53 PORTB............................................24, 26, 28, 30, 32, 34, 53 RB5.....................................................................................53 PORTB Interrupt on Change.............................................138 RB6.....................................................................................53 PORTB Pull-up Enable bit, RBPU.......................................36 RB7.....................................................................................53 PORTC............................................24, 26, 28, 30, 32, 34, 55 RBIE...................................................................................37 PORTD............................................24, 26, 28, 30, 32, 34, 57 RBIF....................................................................................37 PORTE............................................24, 26, 28, 30, 32, 34, 58 RBPU............................................................................36, 53 Ports RC Oscillator.....................................................................130 Bi-directional...............................................................60 RCIE...................................................................................39 I/O Programming Considerations................................60 RCIF...................................................................................42 PORTA........................................................................16 RCREG.................................................24, 26, 28, 30, 32, 34 PORTB........................................................................16 RCSTA..........................................24, 26, 28, 30, 32, 34, 106 PORTC.......................................................................16 RCV_MODE.....................................................................104 PORTD.......................................................................17 Read Only Memory...............................................................7 PORTE........................................................................17 Read/Write bit Information, R/W...................................84, 89 Successive Operations on an I/O Port........................60 Receive and Control Register...........................................106 Power/Control Status Register, PCON.............................130 Receive Overflow Detect bit, SSPOV.................................85 Power-down bit...................................................................35 Receive Overflow Indicator bit, SSPOV..............................90 Power-down Mode............................................................141 Register Bank Select bit, Indirect........................................35 Power-on Reset (POR).....................................................129 Register Bank Select bits. Direct........................................35 Power-on Reset Status bit, POR.........................................47 Power-up Timer (PWRT)...........................................123, 129 PR2.......................................................25, 27, 29, 31, 33, 34 Prescaler.............................................................................68 Prescaler Assignment bit, PSA...........................................36 Prescaler Rate Select bits, PS2:PS0..................................36 PRO MATE Universal Programmer..................................159 Program Memory DS30234E-page 316  1997-2013 Microchip Technology Inc.

PIC16C6X Registers PORTD CCP1CON Section...............................................................57 Diagram..............................................................78 Summary................................................28, 30, 32 Section................................................................78 PORTE Summary....................................24, 26, 28, 30, 32 Section...............................................................58 CCP2CON Summary................................................28, 30, 32 Diagram..............................................................78 PR2 Section................................................................78 Summary....................................25, 27, 29, 31, 33 Summary................................................26, 30, 32 RCREG CCPR1H Summary................................................26, 30, 32 Summary....................................24, 26, 28, 30, 32 RCSTA CCPR1L Diagram............................................................106 Summary....................................24, 26, 28, 30, 32 Summary................................................26, 30, 32 CCPR2H SPBRG Summary................................................26, 30, 32 Summary................................................27, 31, 33 CCPR2L SSPBUF Summary................................................26, 30, 32 Section...............................................................86 FSR Summary....................................24, 26, 28, 30, 32 Indirect Addressing.............................................49 SSPCON Summary..............................24, 26, 28, 30, 32, 34 Diagram..............................................................85 INDF Summary....................................24, 26, 28, 30, 32 Indirect Addressing.............................................49 SSPSR Summary..............................24, 26, 28, 30, 32, 34 Section...............................................................86 INTCON SSPSTAT...................................................................89 Diagram..............................................................37 Diagram..............................................................84 Section................................................................37 Section...............................................................84 Summary..............................24, 26, 28, 30, 32, 34 Summary....................................25, 27, 29, 31, 33 OPTION STATUS Diagram..............................................................36 Diagram..............................................................35 Section................................................................36 Section...............................................................35 Summary..............................25, 27, 29, 31, 33, 34 Summary..............................24, 26, 28, 30, 32, 34 PCL T1CON Section................................................................48 Diagram..............................................................71 Summary..............................24, 26, 28, 30, 32, 34 Section...............................................................71 PCLATH Summary....................................24, 26, 28, 30, 32 Section................................................................48 T2CON Summary..............................24, 26, 28, 30, 32, 34 Diagram..............................................................75 PCON Section...............................................................75 Diagram..............................................................47 Summary....................................24, 26, 28, 30, 32 Section................................................................47 TMR0 Summary....................................25, 27, 29, 31, 33 Summary..............................24, 26, 28, 30, 32, 34 PIE1 TMR1H Diagram..............................................................40 Summary....................................24, 26, 28, 30, 32 Section................................................................38 TMR1L Summary....................................25, 27, 29, 31, 33 Summary....................................24, 26, 28, 30, 32 PIE2 TMR2..........................................................................75 Diagram..............................................................45 Summary....................................24, 26, 28, 30, 32 Section................................................................45 TRISA Summary................................................27, 31, 33 Section...............................................................51 PIR1 Summary....................................25, 27, 29, 31, 33 Diagram..............................................................44 TRISB Section................................................................41 Section...............................................................53 Summary....................................24, 26, 28, 30, 32 Summary..............................25, 27, 29, 31, 33, 34 PIR2 TRISC Diagram..............................................................46 Section...............................................................55 Section................................................................46 Summary....................................25, 27, 29, 31, 33 Summary................................................26, 30, 32 TRISD PORTA Section...............................................................57 Section................................................................51 Summary................................................29, 31, 33 Summary....................................24, 26, 28, 30, 32 TRISE PORTB Diagram..............................................................58 Section................................................................53 Section...............................................................58 Summary..............................24, 26, 28, 30, 32, 34 Summary................................................29, 31, 33 PORTC TXREG Section................................................................55 Summary................................................26, 30, 32 Summary....................................24, 26, 28, 30, 32  1997-2013 Microchip Technology Inc. DS30234E-page 317

PIC16C6X TXSTA SSP in I2C Mode - See I2C Diagram............................................................105 SSPADD.........................................25, 27, 29, 31, 33, 34, 99 Section..............................................................105 SSPBUF.........................................24, 26, 28, 30, 32, 34, 99 Summary.......................................................31, 33 SSPCON...................................24, 26, 28, 30, 32, 34, 85, 90 W...................................................................................9 SSPEN..........................................................................85, 90 Special Function Registers, Initialization SSPIE.................................................................................38 Conditions.................................................................132 SSPIF.................................................................................41 Special Function Registers, Reset Conditions..........131 SSPM3:SSPM0............................................................85, 90 Special Function Register Summary...24, 26, 28, 30, 32 SSPOV.................................................................85, 90, 100 File Maps....................................................................21 SSPSTAT.................................25, 27, 29, 31, 33, 34, 84, 99 Resets...............................................................................128 SSPSTAT Register.............................................................89 ROM......................................................................................7 Stack...................................................................................48 RP0 bit..........................................................................20, 35 Start bit, S.....................................................................84, 89 RP1.....................................................................................35 STATUS..................24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 RX9...................................................................................106 Status bits.................................................................130, 131 RX9D.................................................................................106 Status Bits During Various Resets....................................131 Stop bit, P.....................................................................84, 89 S Switching Prescalers..........................................................69 S....................................................................................84, 89 SYNC,USART Mode Select bit, SYNC.............................105 SCI - See Universal Synchronous Asynchronous Receiver Synchronizing Clocks, TMR0..............................................67 Transmitter (USART) Synchronous Serial Port (SSP) SCK.....................................................................................86 Block Diagram, SPI Mode...........................................86 SCL...................................................................................100 SPI Master/Slave Diagram.........................................87 SDI......................................................................................86 SPI Mode....................................................................86 SDO....................................................................................86 Synchronous Serial Port Enable bit, SSPEN................85, 90 Serial Port Enable bit, SPEN.............................................106 Synchronous Serial Port Interrupt Enable bit, SSPIE.........38 Serial Programming..........................................................142 Synchronous Serial Port Interrupt Flag bit, SSPIF.............41 Serial Programming, Block Diagram.................................142 Synchronous Serial Port Mode Select bits, Serialized Quick-Turnaround-Production..............................7 SSPM3:SSPM0............................................................85, 90 Single Receive Enable bit, SREN.....................................106 Synchronous Serial Port Module........................................83 Slave Mode Synchronous Serial Port Status Register...........................89 SCL...........................................................................100 SDA...........................................................................100 T SLEEP Mode.............................................................123, 141 T0CS...................................................................................36 SMP....................................................................................89 T0IE....................................................................................37 Software Simulator (MPSIM).............................................161 T0IF....................................................................................37 SPBRG..................................................25, 27, 29, 31, 33, 34 T0SE...................................................................................36 Special Features, Section.................................................123 T1CKPS1:T1CKPS0...........................................................71 SPEN................................................................................106 T1CON..................................................24, 26, 28, 30, 32, 34 SPI T1OSCEN...........................................................................71 Block Diagram.......................................................86, 91 T1SYNC..............................................................................71 Master Mode...............................................................92 T2CKPS1:T2CKPS0...........................................................75 Master Mode Timing...................................................93 T2CON............................................24, 26, 28, 30, 32, 34, 75 Mode...........................................................................86 TIme-out...........................................................................130 Serial Clock.................................................................91 Time-out bit.........................................................................35 Serial Data In..............................................................91 Time-out Sequence..........................................................130 Serial Data Out...........................................................91 Timer Modules Slave Mode Timing.....................................................94 Overview, all...............................................................63 Slave Mode Timing Diagram.......................................93 Timer0 Slave Select................................................................91 Block Diagram....................................................65 SPI clock.....................................................................92 Counter Mode.....................................................65 SPI Mode....................................................................91 External Clock....................................................67 SSPCON.....................................................................90 Interrupt..............................................................65 SSPSTAT....................................................................89 Overview.............................................................63 SPI Clock Edge Select bit, CKE..........................................89 Prescaler............................................................68 SPI Data Input Sample Phase Select bit, SMP...................89 Section................................................................65 SPI Mode............................................................................86 Timer Mode........................................................65 SREN................................................................................106 Timing DiagramTiiming Diagrams SS.......................................................................................86 Timer0................................................................65 SSP TMR0 register.....................................................65 Module Overview........................................................83 Timer1 Section........................................................................83 Block Diagram....................................................72 SSPBUF......................................................................92 Capacitor Selection............................................73 SSPCON.....................................................................90 Counter Mode, Asynchronous............................73 SSPSR........................................................................92 Counter Mode, Synchronous..............................72 SSPSTAT....................................................................89 External Clock....................................................73 Oscillator.............................................................73 DS30234E-page 318  1997-2013 Microchip Technology Inc.

PIC16C6X Overview.............................................................63 Watchdog Timer...............................................207 Prescaler.............................................................72 PIC16C63 Read/Write in Asynchronous Counter Mode......73 Brown-out Reset...............................................239 Section................................................................71 Capture/Compare/PWM...................................241 Synchronizing with External Clock......................72 CLKOUT and I/O..............................................238 Timer Mode.........................................................72 External Clock..................................................237 TMR1 Register Pair............................................71 I2C Bus Data.....................................................245 Timer2 I2C Bus Start/Stop Bits.....................................244 Block Diagram....................................................75 Oscillator Start-up Timer...................................239 Overview.............................................................63 Power-up Timer................................................239 Postscaler...........................................................75 Reset................................................................239 Prescaler.............................................................75 SPI Mode..........................................................243 Timer0 Clock Synchronization, Delay.................................67 Timer0..............................................................240 TImer0 Interrupt................................................................138 Timer1..............................................................240 Timer1 Clock Source Select bit, TMR1CS..........................71 USART Synchronous Receive Timer1 External Clock Input Synchronization (Master/Slave).................................................246 Control bit, T1SYNC...........................................................71 Watchdog Timer...............................................239 Timer1 Input Clock Prescale Select bits.............................71 PIC16C64 Timer1 Mode Selection.......................................................78 Capture/Compare/PWM...................................193 Timer1 On bit, TMR1ON.....................................................71 CLKOUT and I/O..............................................190 Timer1 Oscillator Enable Control bit, T1OSCEN................71 External Clock..................................................189 Timer2 Clock Prescale Select bits, I2C Bus Data.....................................................197 T2CKPS1:T2CKPS0...........................................................75 I2C Bus Start/Stop Bits.....................................196 Timer2 Module....................................................................75 Oscillator Start-up Timer...................................191 Timer2 On bit, TMR2ON.....................................................75 Parallel Slave Port............................................194 Timer2 Output Postscale Select bits, Power-up Timer................................................191 TOUTPS3:TOUTPS0..........................................................75 Reset................................................................191 Timing Diagrams SPI Mode..........................................................195 Brown-out Reset.......................................................129 Timer0..............................................................192 I2C Clock Synchronization..........................................98 Timer1..............................................................192 I2C Data Transfer Wait State......................................96 Watchdog Timer...............................................191 I2C Multi-Master Arbitration.........................................98 PIC16C64A I2C Reception (7-bit Address)...................................101 Brown-out Reset...............................................207 PIC16C61 Capture/Compare/PWM...................................209 CLKOUT and I/O..............................................170 CLKOUT and I/O..............................................206 External Clock...................................................169 External Clock..................................................205 Oscillator Start-up Timer...................................171 I2C Bus Data.....................................................213 Power-up Timer................................................171 I2C Bus Start/Stop Bits.....................................212 Reset................................................................171 Oscillator Start-up Timer...................................207 Timer0...............................................................172 Parallel Slave Port............................................210 Watchdog Timer...............................................171 Power-up Timer................................................207 PIC16C62 Reset................................................................207 Capture/Compare/PWM...................................193 SPI Mode..........................................................211 CLKOUT and I/O..............................................190 Timer0..............................................................208 External Clock...................................................189 Timer1..............................................................208 I2C Bus Data.....................................................197 Watchdog Timer...............................................207 I2C Bus Start/Stop Bits.....................................196 PIC16C65 Oscillator Start-up Timer...................................191 Capture/Compare/PWM...................................225 Power-up Timer................................................191 CLKOUT and I/O..............................................222 Reset................................................................191 External Clock..................................................221 SPI Mode..........................................................195 I2C Bus Data.....................................................229 Timer0...............................................................192 I2C Bus Start/Stop Bits.....................................228 Timer1...............................................................192 Oscillator Start-up Timer...................................223 Watchdog Timer...............................................191 Parallel Slave Port............................................226 PIC16C62A Reset................................................................223 Brown-out Reset...............................................207 SPI Mode..........................................................227 Capture/Compare/PWM...................................209 Timer0..............................................................224 CLKOUT and I/O..............................................206 Timer1..............................................................224 External Clock...................................................205 USART Synchronous Receive I2C Bus Data.....................................................213 (Master/Slave)..................................................230 I2C Bus Start/Stop Bits.....................................212 Watchdog Timer...............................................223 Oscillator Start-up Timer...................................207 PIC16C65A Power-up Timer................................................207 Brown-out Reset...............................................239 Reset................................................................207 Capture/Compare/PWM...................................241 SPI Mode..........................................................211 CLKOUT and I/O..............................................238 Timer0...............................................................208 External Clock..................................................237 Timer1...............................................................208 I2C Bus Data.....................................................245  1997-2013 Microchip Technology Inc. DS30234E-page 319

PIC16C6X I2C Bus Start/Stop Bits......................................244 PIC16CR63 Oscillator Start-up Timer...................................239 Brown-out Reset...............................................255 Parallel Slave Port............................................242 Capture/Compare/PWM...................................257 Power-up Timer................................................239 CLKOUT and I/O..............................................254 Reset.................................................................239 External Clock..................................................253 SPI Mode..........................................................243 I2C Bus Data.....................................................261 Timer0...............................................................240 I2C Bus Start/Stop Bits.....................................260 Timer1...............................................................240 Oscillator Start-up Timer...................................255 USART Synchronous Receive Power-up Timer................................................255 (Master/Slave)...................................................246 Reset................................................................255 Watchdog Timer................................................239 SPI Mode..........................................................259 PIC16C66 Timer0..............................................................256 Brown-out Reset...............................................271 Timer1..............................................................256 Capture/Compare/PWM....................................273 USART Synchronous Receive CLKOUT and I/O...............................................270 (Master/Slave).................................................262 External Clock...................................................269 Watchdog Timer...............................................255 I2C Bus Data.....................................................279 PIC16CR64 I2C Bus Start/Stop Bits......................................278 Capture/Compare/PWM...................................209 Oscillator Start-up Timer...................................271 CLKOUT and I/O..............................................206 Power-up Timer................................................271 External Clock..................................................205 Reset.................................................................271 I2C Bus Data.....................................................213 Timer0...............................................................272 I2C Bus Start/Stop Bits.....................................212 Timer1...............................................................272 Oscillator Start-up Timer...................................207 USART Synchronous Receive Parallel Slave Port............................................210 (Master/Slave)...................................................280 Power-up Timer................................................207 Watchdog Timer................................................271 Reset................................................................207 PIC16C67 SPI Mode..........................................................211 Brown-out Reset...............................................271 Timer0..............................................................208 Capture/Compare/PWM....................................273 Timer1..............................................................208 CLKOUT and I/O...............................................270 Watchdog Timer...............................................207 External Clock...................................................269 PIC16CR65 I2C Bus Data.....................................................279 Brown-out Reset...............................................255 I2C Bus Start/Stop Bits......................................278 Capture/Compare/PWM...................................257 Oscillator Start-up Timer...................................271 CLKOUT and I/O..............................................254 Parallel Slave Port............................................274 External Clock..................................................253 Power-up Timer................................................271 I2C Bus Data.....................................................261 Reset.................................................................271 I2C Bus Start/Stop Bits.....................................260 Timer0...............................................................272 Oscillator Start-up Timer...................................255 Timer1...............................................................272 Parallel Slave Port............................................258 USART Synchronous Receive Power-up Timer................................................255 (Master/Slave)...................................................280 Reset................................................................255 Watchdog Timer................................................271 SPI Mode..........................................................259 PIC16CR62 Timer0..............................................................256 Capture/Compare/PWM....................................209 Timer1..............................................................256 CLKOUT and I/O...............................................206 USART Synchronous Receive External Clock...................................................205 (Master/Slave)..................................................262 I2C Bus Data.....................................................213 Watchdog Timer...............................................255 I2C Bus Start/Stop Bits......................................212 Power-up Timer........................................................223 Oscillator Start-up Timer...................................207 PWM Output...............................................................80 Power-up Timer................................................207 RB0/INT Interrupt......................................................138 Reset.................................................................207 RX Pin Sampling...............................................110, 111 SPI Mode..........................................................211 SPI Master Mode........................................................93 Timer0...............................................................208 SPI Mode, Master/Slave Mode, Timer1...............................................................208 No SS Control.............................................................88 Watchdog Timer................................................207 SPI Mode, Slave Mode With SS Control....................88 SPI Slave Mode (CKE = 1).........................................94 SPI Slave Mode Timing (CKE = 0).............................93 Timer0 with External Clock.........................................67 TMR0 Interrupt Timing................................................66 USART Asynchronous Master Transmission...........113 USART Asynchronous Master Transmission (Back to Back)..........................................................113 USART Asynchronous Reception.............................114 USART Synchronous Reception in Master Mode.............................................................119 USART Synchronous Tranmission...........................117 Wake-up from SLEEP Through Interrupts................142 DS30234E-page 320  1997-2013 Microchip Technology Inc.

PIC16C6X TMR0....................................................24, 26, 28, 30, 32, 34 Synchronous Slave Mode TMR0 Clock Source Select bit, T0CS.................................36 Reception.........................................................120 TMR0 Interrupt....................................................................65 Section.............................................................120 TMR0 Overflow Interrupt Enable bit, T0IE..........................37 Setting Up Reception........................................120 TMR0 Overflow Interrupt Flag bit, T0IF..............................37 Setting Up Transmission..................................120 TMR0 Prescale Selection Table.........................................36 Transmit............................................................120 TMR0 Source Edge Select bit, T0SE..................................36 Transmit Block Diagram...........................................112 TMR1 Overflow Interrupt Enable bit, TMR1IE....................38 Update Address bit, UA................................................84, 89 TMR1 Overflow Interrupt Flag bit, TMR1IF.........................41 USART Receive Interrupt Enable bit, RCIE........................39 TMR1CS.............................................................................71 USART Receive Interrupt Flag bit, RCIF............................42 TMR1H..................................................24, 26, 28, 30, 32, 34 USART Transmit Interrupt Enable bit, TXIE.......................39 TMR1IE...............................................................................38 USART Transmit Interrupt Flag bit, TXIF............................42 TMR1IF...............................................................................41 UV Erasable Devices............................................................7 TMR1L..................................................24, 26, 28, 30, 32, 34 W TMR1ON.............................................................................71 TMR2....................................................24, 26, 28, 30, 32, 34 Wake-up from Sleep.........................................................141 TMR2 Register....................................................................75 Wake-up on Key Depression..............................................53 TMR2 to PR2 Match Interrupt Enable bit, TMR2IE.............38 Wake-up Using Interrupts.................................................141 TMR2 to PR2 Match Interrupt Flag bit, TMR2IF.................41 Watchdog Timer (WDT) TMR2IE...............................................................................38 Block Diagram..........................................................140 TMR2IF...............................................................................41 Period.......................................................................140 TMR2ON.............................................................................75 Programming Considerations...................................140 TO...............................................................................35, 131 Section......................................................................140 TOUTPS3:TOUTPS0..........................................................75 WCOL...........................................................................85, 90 Transmit Enable bit, TXEN...............................................105 Weak Internal Pull-ups........................................................53 Transmit Shift Register Status bit, TRMT.........................105 Write Collision Detect bit, WCOL..................................85, 90 Transmit Status and Control Register...............................105 X TRISA.............................................25, 27, 29, 31, 33, 34, 51 TRISB.............................................25, 27, 29, 31, 33, 34, 53 XMIT_MODE....................................................................104 TRISC.......................................25, 27, 29, 31, 33, 34, 55, 94 XT.....................................................................................130 TRISD.............................................25, 27, 29, 31, 33, 34, 57 Z TRISE.............................................25, 27, 29, 31, 33, 34, 58 Z.........................................................................................35 TRMT................................................................................105 Zero bit...........................................................................9, 35 TX9...................................................................................105 TX9D.................................................................................105 TXEN................................................................................105 TXIE....................................................................................39 TXIF....................................................................................42 TXREG..................................................24, 26, 28, 30, 32, 34 TXSTA..........................................25, 27, 29, 31, 33, 34, 105 U UA.................................................................................84, 89 Universal Synchronous Asynchronous Receiver Transmitter (USART) Asynchronous Mode Setting Up Transmission...................................113 Timing Diagram, Master Transmission.............113 Transmitter........................................................112 Asynchronous Receiver Setting Up Reception........................................115 Timing Diagram................................................114 Asynchronous Receiver Mode Block Diagram..................................................114 Section..............................................................114 Section......................................................................105 Synchronous Master Mode Reception..........................................................118 Section..............................................................116 Setting Up Reception........................................118 Setting Up Transmission...................................116 Timing Diagram, Reception..............................119 Timing Diagram, Transmission.........................117 Transmission....................................................116  1997-2013 Microchip Technology Inc. DS30234E-page 321

PIC16C6X LIST OF EQUATION AND EXAMPLES Figure 4-15: PIE1 Register for PIC16C65/65A/R65/67 (Address 8Ch)............................................40 Example 3-1: Instruction Pipeline Flow.............................18 Figure 4-16: PIR1 Register for PIC16C62/62A/R62 Example 4-1: Call of a Subroutine in Page 1 (Address 0Ch)............................................41 from Page 0................................................49 Figure 4-17: PIR1 Register for PIC16C63/R63/66 Example 4-2: Indirect Addressing.....................................49 Address 0Ch)..............................................42 Example 5-1: Initializing PORTA.......................................51 Figure 4-18: PIR1 Register for PIC16C64/64A/R64 Example 5-2: Initializing PORTB.......................................53 (Address 0Ch)............................................43 Example 5-3: Initializing PORTC......................................55 Figure 4-19: PIR1 Register for PIC16C65/65A/R65/67 Example 5-4: Read-Modify-Write Instructions on an (Address 0Ch)............................................44 I/O Port.......................................................60 Figure 4-20: PIE2 Register (Address 8Dh).....................45 Example 7-1: Changing Prescaler (Timer0WDT)..........69 Figure 4-21: PIR2 Register (Address 0Dh).....................46 Example 7-2: Changing Prescaler (WDTTimer0)..........69 Figure 4-22: PCON Register for PIC16C62/64/65 Example 8-1: Reading a 16-bit (Address 8Eh).............................................47 Free-running Timer.....................................73 Figure 4-23: PCON Register for PIC16C62A/R62/63/ Example 10-1:Changing Between R63/64A/R64/65A/R65/66/67 Capture Prescalers.....................................79 (Address 8Eh).............................................47 Example 10-2:PWM Period and Duty Figure 4-24: Loading of PC in Different Situations..........48 Cycle Calculation........................................81 Figure 4-25: Direct/Indirect Addressing..........................49 Example 11-1:Loading the SSPBUF Figure 5-1: Block Diagram of the (SSPSR) Register.......................................86 RA3:RA0 Pins and the RA5 Pin.................51 Example 11-2:Loading the SSPBUF Figure 5-2: Block Diagram of the RA4/T0CKI Pin.........51 (SSPSR) Register (PIC16C66/67)..............91 Figure 5-3: Block Diagram of the Example 12-1:Calculating Baud Rate Error.....................107 RB7:RB4 Pins for PIC16C61/62/64/65.......53 Example 13-1:Saving Status and W Figure 5-4: Block Diagram of the Registers in RAM......................................139 RB7:RB4 Pins for PIC16C62A/63/R63/ Example 13-2:Saving Status, W, and 64A/65A/R65/66/67....................................54 PCLATH Registers in RAM Figure 5-5: Block Diagram of the (All other PIC16C6X devices)...................139 RB3:RB0 Pins.............................................54 Figure 5-6: PORTC Block Diagram...............................55 Figure 5-7: PORTD Block Diagram LIST OF FIGURES (In I/O Port Mode).......................................57 Figure 5-8: PORTE Block Diagram Figure 3-1: PIC16C61 Block Diagram...........................10 (In I/O Port Mode)......................................58 Figure 3-2: PIC16C62/62A/R62/64/64A/R64 Figure 5-9: TRISE Register (Address 89h)...................58 Block Diagram............................................11 Figure 5-10: Successive I/O Operation...........................60 Figure 3-3: PIC16C63/R63/65/65A/R65 Figure 5-11: PORTD and PORTE as a Parallel Block Diagram............................................12 Slave Port...................................................61 Figure 3-4: PIC16C66/67 Block Diagram......................13 Figure 5-12: Parallel Slave Port Write Waveforms.........62 Figure 3-5: Clock/Instruction Cycle...............................18 Figure 5-13: Parallel Slave Port Read Waveforms.........62 Figure 4-1: PIC16C61 Program Memory Map Figure 7-1: Timer0 Block Diagram................................65 and Stack....................................................19 Figure 7-2: Timer0 Timing: Internal Clock/No Figure 4-2: PIC16C62/62A/R62/64/64A/ Prescaler....................................................65 R64 Program Memory Map and Stack.......19 Figure 7-3: Timer0 Timing: Internal Figure 4-3: PIC16C63/R63/65/65A/R65 Program Clock/Prescale 1:2......................................66 Memory Map and Stack..............................19 Figure 7-4: TMR0 Interrupt Timing................................66 Figure 4-4: PIC16C66/67 Program Memory Figure 7-5: Timer0 Timing With External Clock............67 Map and Stack............................................20 Figure 7-6: Block Diagram of the Timer0/WDT Figure 4-5: PIC16C61 Register File Map......................20 Prescaler....................................................68 Figure 4-6: PIC16C62/62A/R62/64/64A/ Figure 8-1: T1CON: Timer1 Control Register R64 Register File Map................................21 (Address 10h).............................................71 Figure 4-7: PIC16C63/R63/65/65A/R65 Figure 8-2: Timer1 Block Diagram................................72 Register File Map........................................21 Figure 9-1: Timer2 Block Diagram................................75 Figure 4-8: PIC16C66/67 Data Memory Map................22 Figure 9-2: T2CON: Timer2 Control Register Figure 4-9: STATUS Register (Address 12h).............................................75 (Address 03h, 83h, 103h, 183h).................35 Figure 10-1: CCP1CON Register (Address 17h) / Figure 4-10: OPTION Register CCP2CON Register (Address 1Dh)...........78 (Address 81h, 181h)...................................36 Figure 10-2: Capture Mode Operation Figure 4-11: INTCON Register Block Diagram............................................78 (Address0Bh,8Bh, 10Bh 18Bh).................37 Figure 10-3: Compare Mode Operation Figure 4-12: PIE1 Register for PIC16C62/62A/R62 Block Diagram............................................79 (Address 8Ch).............................................38 Figure 10-4: Simplified PWM Block Diagram..................80 Figure 4-13: PIE1 Register for PIC16C63/R63/66 Figure 10-5: PWM Output...............................................80 (Address 8Ch).............................................39 Figure 11-1: SSPSTAT: Sync Serial Port Status Figure 4-14: PIE1 Register for PIC16C64/64A/R64 Register (Address 94h)...............................84 (Address 8Ch).............................................39 DS30234E-page 322  1997-2013 Microchip Technology Inc.

PIC16C6X Figure 11-2: SSPCON: Sync Serial Port Figure 13-2: Configuration Word for Control Register (Address 14h)..................85 PIC16C62/64/65.......................................124 Figure 11-3: SSP Block Diagram (SPI Mode).................86 Figure 13-3: Configuration Word for Figure 11-4: SPI Master/Slave Connection.....................87 PIC16C62A/R62/63/R63/64A/R64/ Figure 11-5: SPI Mode Timing, Master Mode or 65A/R65/66/67.........................................124 Slave Mode w/o SS Control........................88 Figure 13-4: Crystal/Ceramic Resonator Operation Figure 11-6: SPI Mode Timing, Slave Mode with (HS, XT or LP OSC Configuration)...........125 SS Control..................................................88 Figure 13-5: External Clock Input Operation Figure 11-7: SSPSTAT: Sync Serial Port Status (HS, XT or LP OSC Configuration)...........125 Register (Address 94h)(PIC16C66/67).......89 Figure 13-6: External Parallel Resonant Figure 11-8: SSPCON: Sync Serial Port Control Crystal Oscillator Circuit...........................127 Register (Address 14h)(PIC16C66/67).......90 Figure 13-7: External Series Resonant Figure 11-9: SSP Block Diagram (SPIMode) Crystal Oscillator Circuit...........................127 (PIC16C66/67)............................................91 Figure 13-8: RC Oscillator Mode..................................127 Figure 11-10: SPI Master/Slave Connection Figure 13-9: Simplified Block Diagram of (PIC16C66/67)............................................92 On-chip Reset Circuit...............................128 Figure 11-11: SPI Mode Timing, Master Mode Figure 13-10: Brown-out Situations................................129 (PIC16C66/67)............................................93 Figure 13-11: Time-out Sequence on Power-up Figure 11-12: SPI Mode Timing (Slave Mode With (MCLR not Tied to VDD): Case 1..............134 CKE=0) (PIC16C66/67)............................93 Figure 13-12: Time-out Sequence on Power-up Figure 11-13: SPI Mode Timing (Slave Mode With (MCLR Not Tied To VDD): Case 2............134 CKE=1) (PIC16C66/67)............................94 Figure 13-13: Time-out Sequence on Power-up Figure 11-14: Start and Stop Conditions...........................95 (MCLR Tied to VDD).................................134 Figure 11-15: 7-bit Address Format..................................96 Figure 13-14: External Power-on Reset Circuit Figure 11-16: I2C 10-bit Address Format..........................96 (For Slow VDD Power-up).........................135 Figure 11-17: Slave-receiver Acknowledge......................96 Figure 13-15: External Brown-out Figure 11-18: Data Transfer Wait State............................96 Protection Circuit 1...................................135 Figure 11-19: Master-transmitter Sequence.....................97 Figure 13-16: External Brown-out Figure 11-20: Master-receiver Sequence..........................97 Protection Circuit 2...................................135 Figure 11-21: Combined Format.......................................97 Figure 13-17: Interrupt Logic for PIC16C61....................137 Figure 11-22: Multi-master Arbitration Figure 13-18: Interrupt Logic for PIC16C6X...................137 (Two Masters).............................................98 Figure 13-19: INT Pin Interrupt Timing...........................138 Figure 11-23: Clock Synchronization................................98 Figure 13-20: Watchdog Timer Block Diagram...............140 Figure 11-24: SSP Block Diagram (I2C Mode)..................99 Figure 13-21: Summary of Watchdog Figure 11-25: I2C Waveforms for Reception Timer Registers........................................140 (7-bit Address)..........................................101 Figure 13-22: Wake-up from Sleep Figure 11-26: I2C Waveforms for Transmission Through Interrupt......................................142 (7-bit Address)..........................................102 Figure 13-23: Typical In-circuit Serial Figure 11-27: Operation of the I2C Module in Programming Connection.........................142 IDLE_MODE, RCV_MODE or Figure 14-1: General Format for Instructions................143 XMIT_MODE............................................104 Figure 16-1: Load Conditions for Device Timing Figure 12-1: TXSTA: Transmit Status and Specifications...........................................168 Control Register (Address 98h)................105 Figure 16-2: External Clock Timing..............................169 Figure 12-2: RCSTA: Receive Status and Figure 16-3: CLKOUT and I/O Timing..........................170 Control Register (Address 18h)................106 Figure 16-4: Reset, Watchdog Timer, Oscillator Figure 12-3: RX Pin Sampling Scheme (BRGH = 0) Start-up Timer and Power-up Timer PIC16C63/R63/65/65A/R65)....................110 Timing.......................................................171 Figure 12-4: RX Pin Sampling Scheme (BRGH = 1) Figure 16-5: Timer0 External Clock Timings................172 (PIC16C63/R63/65/65A/R65)...................110 Figure 17-1: Typical RC Oscillator Figure 12-5: RX Pin Sampling Scheme (BRGH = 1) Frequency vs. Temperature....................173 (PIC16C63/R63/65/65A/R65)...................110 Figure 17-2: Typical RC Oscillator Figure 12-6: RX Pin Sampling Scheme (BRGH = 0 or = 1) Frequency vs. VDD...................................174 (PIC16C66/67)..........................................111 Figure 17-3: Typical RC Oscillator Figure 12-7: USART Transmit Block Diagram..............112 Frequency vs. VDD...................................174 Figure 12-8: Asynchronous Master Transmission.........113 Figure 17-4: Typical RC Oscillator Figure 12-9: Asynchronous Master Transmission Frequency vs. VDD...................................174 (Back to Back)..........................................113 Figure 17-5: Typical IPD vs. VDD Watchdog Timer Figure 12-10: USART Receive Block Diagram...............114 Disabled 25C..........................................174 Figure 12-11: Asynchronous Reception..........................114 Figure 17-6: Typical IPD vs. VDD Watchdog Timer Figure 12-12: Synchronous Transmission......................117 Enabled 25C...........................................175 Figure 12-13: Synchronous Transmission Figure 17-7: Maximum IPD vs. VDD Watchdog through TXEN...........................................117 Disabled...................................................175 Figure 12-14: Synchronous Reception Figure 17-8: Maximum IPD vs. VDD Watchdog (Master Mode, SREN)..............................119 Enabled*...................................................176 Figure 13-1: Configuration Word for PIC16C61............123 Figure 17-9: VTH (Input Threshold Voltage) of I/O Pins vs. VDD.......................................176  1997-2013 Microchip Technology Inc. DS30234E-page 323

PIC16C6X Figure 17-10: VIH, VIL of MCLR, T0CKI and OSC1 Figure 20-7: Parallel Slave Port Timing........................226 (in RC Mode) vs. VDD...............................177 Figure 20-8: SPI Mode Timing......................................227 Figure 17-11: VTH (Input Threshold Voltage) of Figure 20-9: I2C Bus Start/Stop Bits Timing.................228 OSC1 Input (in XT, HS, Figure 20-10: I2C Bus Data Timing.................................229 and LP Modes) vs. VDD............................177 Figure 20-11: USART Synchronous Transmission Figure 17-12: Typical IDD vs. Frequency (Master/Slave) Timing..............................230 (External Clock, 25C)..............................178 Figure 20-12: USART Synchronous Receive Figure 17-13: Maximum IDD vs. Frequency (Master/Slave) Timing..............................230 (External Clock, -40 to +85C).................178 Figure 21-1: Load Conditions for Device Timing Figure 17-14: Maximum IDD vs. Frequency Specifications...........................................236 (External Clock, -55 to +125C)...............179 Figure 21-2: External Clock Timing...............................237 Figure 17-15: WDT Timer Time-out Period vs. VDD........179 Figure 21-3: CLKOUT and I/O Timing..........................238 Figure 17-16: Transconductance (gm) of HS Figure 21-4: Reset, Watchdog Timer, Oscillator Oscillator vs. VDD......................................179 Start-up Timer and Power-up Timer Figure 17-17: Transconductance (gm) of LP Timing.......................................................239 Oscillator vs. VDD......................................180 Figure 21-5: Brown-out Reset Timing...........................239 Figure 17-18: Transconductance (gm) of XT Figure 21-6: Timer0 and Timer1 External Clock Oscillator vs. VDD......................................180 Timings.....................................................240 Figure 17-19: IOH vs. VOH, VDD = 3V..............................180 Figure 21-7: Capture/Compare/PWM Timings Figure 17-20: IOH vs. VOH, VDD = 5V..............................180 (CCP1 and CCP2)...................................241 Figure 17-21: IOL vs. VOL, VDD = 3V...............................181 Figure 21-8: Parallel Slave Port Timing Figure 17-22: IOL vs. VOL, VDD = 5V...............................181 (PIC16C65A)............................................242 Figure 18-1: Load Conditions for Device Figure 21-9: SPI Mode Timing......................................243 Timing Specifications................................188 Figure 21-10: I2C Bus Start/Stop Bits Timing.................244 Figure 18-2: External Clock Timing...............................189 Figure 21-11: I2C Bus Data Timing.................................245 Figure 18-3: CLKOUT and I/O Timing...........................190 Figure 21-12: USART Synchronous Transmission Figure 18-4: Reset, Watchdog Timer, (Master/Slave) Timing..............................246 Oscillator Start-up Timer and Figure 21-13: USART Synchronous Receive Power-up Timer Timing............................191 (Master/Slave) Timing..............................246 Figure 18-5: Timer0 and Timer1 External Figure 22-1: Load Conditions for Device Timing Clock Timings...........................................192 Specifications...........................................252 Figure 18-6: Capture/Compare/PWM Timings Figure 22-2: External Clock Timing...............................253 (CCP1)......................................................193 Figure 22-3: CLKOUT and I/O Timing..........................254 Figure 18-7: Parallel Slave Port Timing Figure 22-4: Reset, Watchdog Timer, Oscillator (PIC16C64)...............................................194 Start-up Timer and Power-up Timer Figure 18-8: SPI Mode Timing......................................195 Timing.......................................................255 Figure 18-9: I2C Bus Start/Stop Bits Timing..................196 Figure 22-5: Brown-out Reset Timing...........................255 Figure 18-10: I2C Bus Data Timing.................................197 Figure 22-6: Timer0 and Timer1 External Clock Figure 19-1: Load Conditions for Device Timings.....................................................256 Timing Specifications................................204 Figure 22-7: Capture/Compare/PWM Timings Figure 19-2: External Clock Timing...............................205 (CCP1 and CCP2)....................................257 Figure 19-3: CLKOUT and I/O Timing...........................206 Figure 22-8: Parallel Slave Port Timing Figure 19-4: Reset, Watchdog Timer, (PIC16CR65)............................................258 Oscillator Start-up Timer and Figure 22-9: SPI Mode Timing......................................259 Power-up Timer Timing............................207 Figure 22-10: I2C Bus Start/Stop Bits Timing.................260 Figure 19-5: Brown-out Reset Timing...........................207 Figure 22-11: I2C Bus Data Timing.................................261 Figure 19-6: Timer0 and Timer1 External Figure 22-12: USART Synchronous Transmission Clock Timings...........................................208 (Master/Slave) Timing..............................262 Figure 19-7: Capture/Compare/PWM Timings Figure 22-13: USART Synchronous Receive (CCP1)......................................................209 (Master/Slave) Timing..............................262 Figure 19-8: Parallel Slave Port Timing Figure 23-1: Load Conditions for Device Timing (PIC16C64A/R64).....................................210 Specifications...........................................268 Figure 19-9: SPI Mode Timing......................................211 Figure 23-2: External Clock Timing...............................269 Figure 19-10: I2C Bus Start/Stop Bits Timing..................212 Figure 23-3: CLKOUT and I/O Timing..........................270 Figure 19-11: I2C Bus Data Timing.................................213 Figure 23-4: Reset, Watchdog Timer, Oscillator Figure 20-1: Load Conditions for Device Timing Start-up Timer and Power-up Timer Specifications............................................220 Timing.......................................................271 Figure 20-2: External Clock Timing...............................221 Figure 23-5: Brown-out Reset Timing...........................271 Figure 20-3: CLKOUT and I/O Timing...........................222 Figure 23-6: Timer0 and Timer1 External Clock Figure 20-4: Reset, Watchdog Timer, Oscillator Timings.....................................................272 Start-up Timer and Power-up Timer Figure 23-7: Capture/Compare/PWM Timings Timing.......................................................223 (CCP1 and CCP2)....................................273 Figure 20-5: Timer0 and Timer1 External Clock Figure 23-8: Parallel Slave Port Timing (PIC16C67)....274 Timings.....................................................224 Figure 23-9: SPI Master Mode Timing (CKE=0).........275 Figure 20-6: Capture/Compare/PWM Timings Figure 23-10: SPI Master Mode Timing (CKE=1).........275 (CCP1 and CCP2)....................................225 Figure 23-11: SPI Slave Mode Timing (CKE=0)...........276 DS30234E-page 324  1997-2013 Microchip Technology Inc.

PIC16C6X Figure 23-12: SPI Slave Mode Timing (CKE=1)...........276 Figure 24-29: Typical IDD vs. Frequency Figure 23-13: I2C Bus Start/Stop Bits Timing..................278 (HS Mode, 25°C)......................................290 Figure 23-14: I2C Bus Data Timing.................................279 Figure 24-30: Maximum IDD vs. Frequency Figure 23-15: USART Synchronous Transmission (HS Mode, -40°C to 85°C)........................290 (Master/Slave) Timing...............................280 Figure 23-16: USART Synchronous Receive (Master/Slave) Timing...............................280 Figure 24-1: Typical IPD vs. VDD (WDT Disabled, RC Mode).......................281 Figure 24-2: Maximum IPD vs. VDD (WDT Disabled, RC Mode).......................281 Figure 24-3: Typical IPD vs. VDD @ 25C (WDT Enabled, RC Mode)........................282 Figure 24-4: Maximum IPD vs. VDD (WDT Enabled, RC Mode)........................282 Figure 24-5: Typical RC Oscillator Frequency vs. VDD....................................282 Figure 24-6: Typical RC Oscillator Frequency vs. VDD....................................282 Figure 24-7: Typical RC Oscillator Frequency vs. VDD....................................282 Figure 24-8: Typical IPD vs. VDD Brown-out Detect Enabled (RC Mode).......................283 Figure 24-9: Maximum IPD vs. VDD Brown-out Detect Enabled (85C to -40C, RC Mode)........................283 Figure 24-10: Typical IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, RC Mode)................................................283 Figure 24-11: Maximum IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C to -40C, RC Mode).........................283 Figure 24-12: Typical IDD vs. Frequency (RC Mode @ 22 pF, 25°C).......................284 Figure 24-13: Maximum IDD vs. Frequency (RC Mode @ 22 pF, -40°C to 85°C).........284 Figure 24-14: Typical IDD vs. Frequency (RC Mode @ 100 pF, 25°C).....................285 Figure 24-15: Maximum IDD vs. Frequency (RC Mode @ 100 pF, -40°C to 85°C).......285 Figure 24-16: Typical IDD vs. Frequency (RC Mode @ 300 pF, 25°C).....................286 Figure 24-17: Maximum IDD vs. Frequency (RC Mode @ 300 pF, -40°C to 85°C).......286 Figure 24-18: Typical IDD vs. Capacitance @ 500 kHz (RC Mode)................................................287 Figure 24-19: Transconductance(gm) of HS Oscillator vs. VDD......................................287 Figure 24-20: Transconductance(gm) of LP Oscillator vs. VDD......................................287 Figure 24-21: Transconductance(gm) of XT Oscillator vs. VDD......................................287 Figure 24-22: Typical XTAL Startup Time vs. VDD (LP Mode, 25C).......................................288 Figure 24-23: Typical XTAL Startup Time vs. VDD (HS Mode, 25C)......................................288 Figure 24-24: Typical XTAL Startup Time vs. VDD (XT Mode, 25C).......................................288 Figure 24-25: Typical Idd vs. Frequency (LP Mode, 25°C).......................................289 Figure 24-26: Maximum IDD vs. Frequency (LP Mode, 85°C to -40°C).........................289 Figure 24-27: Typical IDD vs. Frequency (XT Mode, 25°C).......................................289 Figure 24-28: Maximum IDD vs. Frequency (XT Mode, -40°C to 85°C).........................289  1997-2013 Microchip Technology Inc. DS30234E-page 325

PIC16C6X LIST OF TABLES Table 12-2: Registers Associated with Baud Rate Generator.........................................107 Table 1-1: PIC16C6X Family of Devices.......................6 Table 12-3: Baud Rates for Synchronous Mode..........108 Table 3-1: PIC16C61 Pinout Description.....................14 Table 12-4: Baud Rates for Asynchronous Mode Table 3-2: PIC16C62/62A/R62/63/R63/66 (BRGH = 0)...............................................108 Pinout Description.......................................15 Table 12-5: Baud Rates for Asynchronous Mode Table 3-3: PIC16C64/64A/R64/65/65A/R65/67 (BRGH = 1)...............................................109 Pinout Description.......................................16 Table 12-6: Registers Associated with Table 4-1: Special Function Registers for the Asynchronous Transmission....................113 PIC16C61...................................................23 Table 12-7: Registers Associated with Table 4-2: Special Function Registers for the Asynchronous Reception..........................115 PIC16C62/62A/R62....................................24 Table 12-8: Registers Associated with Table 4-3: Special Function Registers for the Synchronous Master Transmission..........117 PIC16C63/R63............................................26 Table 12-9: Registers Associated with Table 4-4: Special Function Registers for the Synchronous Master Reception...............118 PIC16C64/64A/R64....................................28 Table 12-10: Registers Associated with Table 4-5: Special Function Registers for the Synchronous Slave Transmission............121 PIC16C65/65A/R65....................................30 Table 12-11: Registers Associated with Table 4-6: Special Function Registers for the Synchronous Slave Reception.................121 PIC16C66/67..............................................32 Table 13-1: Ceramic Resonators PIC16C61...............126 Table 5-1: PORTA Functions.......................................52 Table 13-2: Ceramic Resonators Table 5-2: Registers/Bits Associated with PIC16C62/62A/R62/63/R63/ PORTA.......................................................52 64/64A/R64/65/65A/R65/66/67................126 Table 5-3: PORTB Functions.......................................54 Table 13-3: Capacitor Selection for Crystal Table 5-4: Summary of Registers Associated with Oscillator for PIC16C61............................126 PORTB.......................................................54 Table 13-4: Capacitor Selection for Crystal Table 5-5: PORTC Functions for PIC16C62/64...........55 Oscillator for PIC16C62/62A/R62/63/R63/ Table 5-6: PORTC Functions for 64/64A/R64/65/65A/R65/66/67................126 PIC16C62A/R62/64A/R64..........................56 Table 13-5: Time-out in Various Situations, Table 5-7: PORTC Functions for PIC16C61/62/64/65..................................130 PIC16C63/R63/65/65A/R65/66/67..............56 Table 13-6: Time-out in Various Situations, Table 5-8: Summary of Registers Associated with PIC16C62A/R62/63/R63/ PORTC.......................................................56 64A/R64/65A/R65/66/67..........................130 Table 5-9: PORTD Functions.......................................57 Table 13-7: Status Bits and Their Significance, Table 5-10: Summary of Registers Associated with PIC16C61.................................................130 PORTD.......................................................57 Table 13-8: Status bits and Their Significance, Table 5-11: PORTE Functions.......................................59 PIC16C62/64/65.......................................130 Table 5-12: Summary of Registers Associated with Table 13-9: Status Bits and Their Significance for PORTE.......................................................59 PIC16C62A/R62/63/R63/ Table 5-13: Registers Associated with 64A/R64/65A/R65/66/67..........................131 Parallel Slave Port......................................62 Table 13-10: Reset Condition for Special Table 7-1: Registers Associated with Timer0..............69 Registers on PIC16C61/62/64/65.............131 Table 8-1: Capacitor Selection for the Table 13-11: Reset Condition for Special Timer1 Oscillator.........................................73 Registers on Table 8-2: Registers Associated with PIC16C62A/R62/63/R63/ Timer1 as a Timer/Counter.........................74 64A/R64/65A/R65/66/67..........................131 Table 9-1: Registers Associated with Table 13-12: Initialization Conditions for Timer2 as a Timer/Counter.........................76 all Registers..............................................132 Table 10-1: CCP Mode - Timer Resource.....................77 Table 14-1: Opcode Field Descriptions.......................143 Table 10-2: Interaction of Two CCP Modules................77 Table 14-2: PIC16CXX Instruction Set........................144 Table 10-3: Example PWM Frequencies Table 15-1: Development Tools from Microchip..........162 and Resolutions at 20 MHz.........................81 Table 16-1: Cross Reference of Device Table 10-4: Registers Associated with Timer1, Specs for Oscillator Configurations Capture and Compare................................81 and Frequencies of Operation Table 10-5: Registers Associated with PWM (Commercial Devices)..............................163 and Timer2..................................................82 Table 16-2: External Clock Timing Table 11-1: Registers Associated with SPI Requirements...........................................169 Operation....................................................88 Table 16-3: CLKOUT and I/O Timing Table 11-2: Registers Associated with SPI Requirements...........................................170 Operation (PIC16C66/67)...........................94 Table 16-4: Reset, Watchdog Timer, Table 11-3: I2C Bus Terminology...................................95 Oscillator Start-up Timer and Table 11-4: Data Transfer Received Byte Power-up Timer Requirements.................171 Actions......................................................100 Table 16-5: Timer0 External Clock Requirements.......172 Table 11-5: Registers Associated with I2C Table 17-1: RC Oscillator Frequencies........................173 Operation..................................................103 Table 17-2: Input Capacitance*...................................181 Table 12-1: Baud Rate Formula...................................107 DS30234E-page 326  1997-2013 Microchip Technology Inc.

PIC16C6X Table 18-1: Cross Reference of Device Specs Table 20-12: USART Synchronous Receive for Oscillator Configurations and Requirements...........................................230 Frequencies of Operation Table 21-1: Cross Reference of Device (Commercial Devices)..............................183 Specs for Oscillator Configurations Table 18-2: External Clock Timing and Frequencies of Operation Requirements...........................................189 (Commercial Devices)..............................231 Table 18-3: CLKOUT and I/O Timing Table 21-2: External Clock Timing Requirements...........................................190 Requirements...........................................237 Table 18-4: Reset, Watchdog Timer, Table 21-3: CLKOUT and I/O Timing Oscillator Start-up Timer and Requirements...........................................238 Power-up Timer Requirements.................191 Table 21-4: Reset, Watchdog Timer, Oscillator Table 18-5: Timer0 and Timer1 External Start-up Timer, Power-up Timer, and Clock Requirements.................................192 Brown-out Reset Requirements...............239 Table 18-6: Capture/Compare/PWM Table 21-5: Timer0 and Timer1 External Requirements (CCP1)..............................193 Clock Requirements.................................240 Table 18-7: Parallel Slave Port Requirements (PIC16C64) Table 21-6: Capture/Compare/PWM 194 Requirements (CCP1 and CCP2)............241 Table 18-8: SPI Mode Requirements...........................195 Table 21-7: Parallel Slave Port Requirements Table 18-9: I2C Bus Start/Stop Bits (PIC16C65A)............................................242 Requirements...........................................196 Table 21-8: SPI Mode Requirements..........................243 Table 18-10: I2C Bus Data Requirements.....................197 Table 21-9: I2C Bus Start/Stop Bits Table 19-1: Cross Reference of Device Specs Requirements...........................................244 for Oscillator Configurations and Table 21-10: I2C Bus Data Requirements.....................245 Frequencies of Operation Table 21-11: USART Synchronous (Commercial Devices)..............................199 Transmission Requirements.....................246 Table 19-2: External Clock Timing Table 21-12: USART Synchronous Receive Requirements...........................................205 Requirements..........................................246 Table 19-3: CLKOUT and I/O Timing Table 22-1: Cross Reference of Device Specs Requirements...........................................206 for Oscillator Configurations and Table 19-4: Reset, Watchdog Timer, Frequencies of Operation Oscillator Start-up Timer, (Commercial Devices)..............................247 Power-up Timer, and Brown-out Table 22-2: External Clock Timing Reset Requirements.................................207 Requirements...........................................253 Table 19-5: Timer0 and Timer1 External Table 22-3: CLKOUT and I/O Timing Clock Requirements.................................208 Requirements...........................................254 Table 19-6: Capture/Compare/PWM Table 22-4: Reset, Watchdog Timer, Requirements (CCP1)..............................209 Oscillator Start-up Timer, Table 19-7: Parallel Slave Port Requirements Power-up Timer, and Brown-out (PIC16C64A/R64).....................................210 Reset Requirements.................................255 Table 19-8: SPI Mode Requirements...........................211 Table 22-5: Timer0 and Timer1 External Table 19-9: I2C Bus Start/Stop Bits Clock Requirements.................................256 Requirements...........................................212 Table 22-6: Capture/Compare/PWM Table 19-10: I2C Bus Data Requirements.....................213 Requirements (CCP1 and CCP2)............257 Table 20-1: Cross Reference of Device Specs Table 22-7: Parallel Slave Port Requirements for Oscillator Configurations and (PIC16CR65)............................................258 Frequencies of Operation Table 22-8: SPI Mode Requirements..........................259 (Commercial Devices)..............................215 Table 22-9: I2C Bus Start/Stop Bits Table 20-2: External Clock Timing Requirements...........................................260 Requirements...........................................221 Table 22-10: I2C Bus Data Requirements.....................261 Table 20-3: CLKOUT and I/O Timing Table 22-11: USART Synchronous Transmission Requirements...........................................222 Requirements...........................................262 Table 20-4: Reset, Watchdog Timer, Table 22-12: USART Synchronous Receive Oscillator Start-up Timer and Requirements..........................................262 Power-up Timer Requirements.................223 Table 23-1: Cross Reference of Device Specs Table 20-5: Timer0 and Timer1 External for Oscillator Configurations and Clock Requirements.................................224 Frequencies of Operation Table 20-6: Capture/Compare/PWM (Commercial Devices)..............................263 Requirements (CCP1 and CCP2).............225 Table 23-2: External Clock Timing Table 20-7: Parallel Slave Port Requirements.............226 Requirements...........................................269 Table 20-8: SPI Mode Requirements...........................227 Table 23-3: CLKOUT and I/O Timing Table 20-9: I2C Bus Start/Stop Bits Requirements...........................................270 Requirements...........................................228 Table 23-4: Reset, Watchdog Timer, Table 20-10: i2C Bus Data Requirements......................229 Oscillator Start-up Timer, Table 20-11: USART Synchronous Transmission Power-up Timer, and Brown-out Requirements...........................................230 Reset Requirements.................................271  1997-2013 Microchip Technology Inc. DS30234E-page 327

PIC16C6X Table 23-5: Timer0 and Timer1 External Clock Requirements.................................272 Table 23-6: Capture/Compare/PWM Requirements (CCP1 and CCP2).............273 Table 23-7: Parallel Slave Port Requirements (PIC16C67) 274 Table 23-8: SPI Mode Requirements...........................277 Table 23-9: I2C Bus Start/Stop Bits Requirements...........................................278 Table 23-10: I2C Bus Data Requirements.....................279 Table 23-11: USART Synchronous Transmission Requirements...........................................280 Table 23-12: USART Synchronous Receive Requirements...........................................280 Table 24-1: RC Oscillator Frequencies........................287 Table 24-2: Capacitor Selection for Crystal Oscillators.................................................288 Table E-1: Pin Compatible Devices............................315 DS30234E-page 328  1997-2013 Microchip Technology Inc.

PIC16C6X ON-LINE SUPPORT The procedure to connect will vary slightly from country to country. Please check with your local CompuServe Microchip provides two methods of on-line support. agent for details if you have a problem. CompuServe These are the Microchip BBS and the Microchip World service allow multiple users various baud rates Wide Web (WWW) site. depending on the local point of access. Use Microchip's Bulletin Board Service (BBS) to get The following connect procedure applies in most loca- current information and help about Microchip products. tions. Microchip provides the BBS communication channel for you to use in extending your technical staff with 1.Set your modem to 8-bit, No parity, and One stop microcontroller and memory experts. (8N1). This is not the normal CompuServe setting which is 7E1. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts 2.Dial your local CompuServe access number. the latest component data and software tool updates, 3.Depress the <Enter> key and a garbage string will provides technical help and embedded systems appear because CompuServe is expecting a 7E1 insights, and discusses how Microchip products pro- setting. vide project solutions. 4.Type +, depress the <Enter> key and “Host Name:” The web site, like the BBS, is used by Microchip as a will appear. means to make files and information easily available to 5.Type MCHIPBBS, depress the <Enter> key and you customers. To view the site, the user must have access will be connected to the Microchip BBS. to the Internet and a web browser, such as Netscape or In the United States, to find the CompuServe phone Microsoft Explorer. Files are also available for FTP number closest to you, set your modem to 7E1 and dial download from our FTP site. (800) 848-4480 for 300-2400 baud or (800) 331-7166 Connecting to the Microchip Internet Web Site for 9600-14400 baud connection. After the system responds with “Host Name:”, type NETWORK, depress The Microchip web site is available by using your the <Enter> key and follow CompuServe's directions. favorite Internet browser to attach to: www.microchip.com For voice information (or calling from overseas), you may call (614) 723-1550 for your local CompuServe The file transfer site is available by using an FTP ser- number. vice to connect to: Microchip regularly uses the Microchip BBS to distribute ftp://ftp.futureone.com/pub/microchip technical information, application notes, source code, The web site and file transfer site provide a variety of errata sheets, bug reports, and interim patches for services. Users may download files for the latest Microchip systems software products. For each SIG, a Development Tools, Data Sheets, Application Notes, moderator monitors, scans, and approves or disap- User's Guides, Articles and Sample Programs. A vari- proves files submitted to the SIG. No executable files ety of Microchip specific business information is also are accepted from the user community in general to available, including listings of Microchip sales offices, limit the spread of computer viruses. distributors and factory representatives. Other data Systems Information and Upgrade Hot Line available for consideration is: The Systems Information and Upgrade Line provides (cid:129) Latest Microchip Press Releases system users a listing of the latest versions of all of (cid:129) Technical Support Section with Frequently Asked Microchip's development systems software products. Questions Plus, this line provides information on how customers (cid:129) Design Tips can receive any currently available upgrade kits.The (cid:129) Device Errata Hot Line Numbers are: (cid:129) Job Postings 1-800-755-2345 for U.S. and most of Canada, and (cid:129) Microchip Consultant Program Member Listing 1-602-786-7302 for the rest of the world. (cid:129) Links to other useful web sites related to Microchip Products 970301 Connecting to the Microchip BBS Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Connect worldwide to the Microchip BBS using either the Internet or the CompuServe communications net- Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB, are trade- work. marks and SQTP is a service mark of Microchip in the Internet: U.S.A. You can telnet or ftp to the Microchip BBS at the fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of address: mchipbbs.microchip.com International Business Machines Corp. Pentium is a trade- CompuServe Communications Network: mark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks When using the BBS via the Compuserve Network, of Microsoft Corporation. CompuServe is a registered in most cases, a local call is your only expense. trademark of CompuServe Incorporated. The Microchip BBS connection does not use CompuServe All other trademarks mentioned herein are the property of membership services, therefore you do not need their respective companies. CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS.  1997-2013 Microchip Technology Inc. DS30234E-page 329

PIC16C6X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16C6X Literature Number: DS30234E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30234E-page 330  1997-2013 Microchip Technology Inc.

PIC16C6X PIC16C6X Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NO. -XX X /XX XXX Pattern: 3-Digit Pattern Code for QTP (blank otherwise) Package: L = PLCC SP = Skinny DIP P = PDIP SO = SOIC (Gull Wing, 300 mil body) PQ = MQFP (Metric PQFP) TQ = TQFP JW* = Windowed CERDIP SS = Shrink SOIC (Gull Wing, 300 mil body) Temperature - = 0°C to +70°C (T for tape/reel) Range: I = – 40°C to +85°C (S for tape/reel) E = – 40°C to +125°C Frequency 04 = 200 kHz (PIC16C6X-04) Range: 04 = 4 MHz 10 = 10 MHz 20 = 20 MHz Device: PIC16C6X :VDD range 4.0V to 6.0V PIC16C6XT :VDD range 4.0V to 6.0V (Tape and Reel) PIC16LC6X :VDD range 2.5V to 6.0V PIC16LC6XT:VDD range 2.5V to 6.0V (Tape and Reel) PIC16CR6X :VDD range 4.0V to 6.0V PIC16CR6XT:VDD range 4.0V to 6.0V (Tape and Reel) PIC16LCR6X:VDD range 2.5V to 6.0V PIC16LCR6XT:VDD range 2.5V to 6.0V Examples: a)PIC16C62A - 04/P 301= Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301 b)PIC16LC65A - 04I/PQ = Industrial temp., MQFP package, 4 MHz, extended VDD limits c)PIC16C67 - 10E/P = Extended temp., PDIP package, 10 MHz, normal VDD limits * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. The Microchip Website at www.microchip.com 2. Your local Microchip sales office (see following page)  1997-2013 Microchip Technology Inc. DS30234E-page 331

PIC16C6X DS30234E-page 332  1997-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1997-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769652 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == adreev ifcoer sit,s S PeIrCia®l MEECPURsO aMnds ,d msPicIrCo®p eDrSipChse,r aKlEsE, LnOonQv®o cloadtilee hmoepmpionrgy and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  1997-2013 Microchip Technology Inc. DS30234E-page 333

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office India - Bangalore Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 91-80-3090-4123 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon India - New Delhi Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 91-11-4160-8631 Tel: 45-4450-2828 Technical Support: Tel: 852-2401-1200 Fax: 91-11-4160-8632 Fax: 45-4485-2829 http://www.microchip.com/ support Fax: 852-2401-3431 India - Pune France - Paris Web Address: Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20 www.microchip.com Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79 Atlanta Fax: 61-2-9868-6755 Japan - Osaka Germany - Munich Duluth, GA China - Beijing Tel: 81-6-6152-7160 Tel: 49-89-627-144-0 Tel: 86-10-8569-7000 Fax: 49-89-627-144-44 Tel: 678-957-9614 Fax: 81-6-6152-9310 Fax: 678-957-1455 Fax: 86-10-8528-2104 Japan - Tokyo Italy - Milan China - Chengdu Tel: 39-0331-742611 Boston Tel: 81-3-6880- 3770 Tel: 86-28-8665-5511 Fax: 39-0331-466781 Westborough, MA Fax: 81-3-6880-3771 Tel: 774-760-0087 Fax: 86-28-8665-7889 Korea - Daegu Netherlands - Drunen Fax: 774-760-0088 China - Chongqing Tel: 82-53-744-4301 Tel: 31-416-690399 Chicago Tel: 86-23-8980-9588 Fax: 82-53-744-4302 Fax: 31-416-690340 Itasca, IL Fax: 86-23-8980-9500 Korea - Seoul Spain - Madrid Tel: 630-285-0071 China - Hangzhou Tel: 82-2-554-7200 Tel: 34-91-708-08-90 Fax: 630-285-0075 Tel: 86-571-2819-3187 Fax: 82-2-558-5932 or Fax: 34-91-708-08-91 Cleveland Fax: 86-571-2819-3189 82-2-558-5934 UK - Wokingham Independence, OH China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 44-118-921-5869 Tel: 216-447-0464 Tel: 852-2943-5100 Tel: 60-3-6201-9857 Fax: 44-118-921-5820 Fax: 216-447-0643 Fax: 852-2401-3431 Fax: 60-3-6201-9859 Dallas China - Nanjing Malaysia - Penang Addison, TX Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 60-4-227-4068 Fax: 972-818-2924 China - Qingdao Philippines - Manila Detroit Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Farmington Hills, MI Fax: 86-532-8502-7205 Fax: 63-2-634-9069 Tel: 248-538-2250 Fax: 248-538-2260 China - Shanghai Singapore Tel: 86-21-5407-5533 Tel: 65-6334-8870 Indianapolis Fax: 86-21-5407-5066 Fax: 65-6334-8850 Noblesville, IN Tel: 317-773-8323 China - Shenyang Taiwan - Hsin Chu Fax: 317-773-5453 Tel: 86-24-2334-2829 Tel: 886-3-5778-366 Fax: 86-24-2334-2393 Fax: 886-3-5770-955 Los Angeles Mission Viejo, CA China - Shenzhen Taiwan - Kaohsiung Tel: 949-462-9523 Tel: 86-755-8864-2200 Tel: 886-7-213-7828 Fax: 949-462-9608 Fax: 86-755-8203-1760 Fax: 886-7-330-9305 Santa Clara China - Wuhan Taiwan - Taipei Santa Clara, CA Tel: 86-27-5980-5300 Tel: 886-2-2508-8600 Tel: 408-961-6444 Fax: 86-27-5980-5118 Fax: 886-2-2508-0102 Fax: 408-961-6445 China - Xian Thailand - Bangkok Toronto Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Mississauga, Ontario, Fax: 86-29-8833-7256 Fax: 66-2-694-1350 Canada China - Xiamen Tel: 905-673-0699 Tel: 86-592-2388138 Fax: 905-673-6509 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 11/29/12 DS30234E-page 334  1997-2013 Microchip Technology Inc.