PIC16C62X Data Sheet EPROM-Based 8-Bit CMOS Microcontrollers  2003 Microchip Technology Inc. DS30235J

Note the following details of the code protection feature on Microchip devices: (cid:127) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:127) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, KEELOQ, ensure that your application meets with your specifications. No MPLAB, PIC, PICmicro, PICSTART, PRO MATE and representation or warranty is given and no liability is assumed by PowerSmart are registered trademarks of Microchip Technology Microchip Technology Incorporated with respect to the accuracy Incorporated in the U.S.A. and other countries. or use of such information, or infringement of patents or other FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL intellectual property rights arising from such use or otherwise. and The Embedded Control Solutions Company are registered Use of Microchip’s products as critical components in life trademarks of Microchip Technology Incorporated in the U.S.A. support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or Accuron, Application Maestro, dsPIC, dsPICDEM, otherwise, under any intellectual property rights. dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. DS30235J - page ii  2003 Microchip Technology Inc.

PIC16C62X EPROM-Based 8-Bit CMOS Microcontrollers Devices included in this data sheet: Pin Diagrams Referred to collectively as PIC16C62X. PDIP, SOIC, Windowed CERDIP (cid:127) PIC16C620 (cid:127) PIC16C620A (cid:127) PIC16C621 (cid:127) PIC16C621A RA2/AN2/VREF (cid:127)1 18 RA1/AN1 (cid:127)(cid:127) PPIICC1166CCR626220A (cid:127) PIC16C622A RMARC4AL/T3R0//AVVCNPSK3PSI 2345 PIC16C 11117546 ROVODASSD0CC/21A//NCC0LLKKOINUT RB0/INT 6 6 13 RB7 High Performance RISC CPU: RB1 7 2X 12 RB6 RB2 8 11 RB5 (cid:127) Only 35 instructions to learn RB3 9 10 RB4 (cid:127) All single cycle instructions (200ns), except for program branches which are two-cycle SSOP (cid:127) Operating speed: - DC - 40MHz clock input RA2/AN2/VREF (cid:127)1 20 RA1/AN1 RA3/AN3 2 19 RA0/AN0 - DC - 100ns instruction cycle RA4/T0CKI 3 P 18 OSC1/CLKIN MCLR/VPP 4 IC 17 OSC2/CLKOUT Program Data VVSSSS 56 16C 1165 VVDDDD Device Memory Memory RB0/INT 7 62 14 RB7 RB1 8 X 13 RB6 RB2 9 12 RB5 PIC16C620 512 80 RRBB33 10 11 RB4 PIC16C620A 512 96 Special Microcontroller Features: PIC16CR620A 512 96 (cid:127) Power-on Reset (POR) PIC16C621 1K 80 (cid:127) Power-up Timer (PWRT) and Oscillator Start-up PIC16C621A 1K 96 Timer (OST) (cid:127) Brown-out Reset PIC16C622 2K 128 (cid:127) Watchdog Timer (WDT) with its own on-chip RC PIC16C622A 2K 128 oscillator for reliable operation (cid:127) Interrupt capability (cid:127) Programmable code protection (cid:127) 16 special function hardware registers (cid:127) Power saving SLEEP mode (cid:127) 8-level deep hardware stack (cid:127) Selectable oscillator options (cid:127) Direct, Indirect and Relative addressing modes (cid:127) Serial in-circuit programming (via two pins) (cid:127) Four user programmable ID locations Peripheral Features: CMOS Technology: (cid:127) 13 I/O pins with individual direction control (cid:127) High current sink/source for direct LED drive (cid:127) Low power, high speed CMOS EPROM (cid:127) Analog comparator module with: technology - Two analog comparators (cid:127) Fully static design - Programmable on-chip voltage reference (cid:127) Wide operating range (VREF) module - 2.5V to 5.5V - Programmable input multiplexing from device (cid:127) Commercial, industrial and extended tempera- inputs and internal voltage reference ture range - Comparator outputs can be output signals (cid:127) Low power consumption (cid:127) Timer0: 8-bit timer/counter with 8-bit - < 2.0 mA @ 5.0V, 4.0 MHz programmable prescaler - 15 µA typical @ 3.0V, 32 kHz - < 1.0 µA typical standby current @ 3.0V  2003 Microchip Technology Inc. DS30235J-page 1

PIC16C62X Device Differences Process Technology Device Voltage Range Oscillator (Microns) (3) PIC16C620 2.5 - 6.0 See Note 1 0.9 (3) PIC16C621 2.5 - 6.0 See Note 1 0.9 (3) PIC16C622 2.5 - 6.0 See Note 1 0.9 (4) PIC16C620A 2.7 - 5.5 See Note 1 0.7 (2) PIC16CR620A 2.5 - 5.5 See Note 1 0.7 (4) PIC16C621A 2.7 - 5.5 See Note 1 0.7 (4) PIC16C622A 2.7 - 5.5 See Note 1 0.7 Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. 2: For ROM parts, operation from 2.5V - 3.0V will require the PIC16LCR62X parts. 3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X parts. 4: For OTP parts, operations from 2.7V - 3.0V will require the PIC16LC62XA parts. DS30235J-page 2  2003 Microchip Technology Inc.

PIC16C62X Table of Contents 1.0 General Description.................................................................................................................................................................. 5 2.0 PIC16C62X Device Varieties.................................................................................................................................................... 7 3.0 Architectural Overview.............................................................................................................................................................. 9 4.0 Memory Organization .............................................................................................................................................................13 5.0 I/O Ports.................................................................................................................................................................................. 25 6.0 Timer0 Module........................................................................................................................................................................ 31 7.0 Comparator Module................................................................................................................................................................ 37 8.0 Voltage Reference Module..................................................................................................................................................... 43 9.0 Special Features of the CPU.................................................................................................................................................. 45 10.0 Instruction Set Summary ........................................................................................................................................................61 11.0 Development Support............................................................................................................................................................. 75 12.0 Electrical Specifications ..........................................................................................................................................................81 13.0 Device Characterization Information .....................................................................................................................................109 14.0 Packaging Information.......................................................................................................................................................... 113 Appendix A: Enhancements.............................................................................................................................................................. 119 Appendix B: Compatibility................................................................................................................................................................. 119 Index ...............................................................................................................................................................................................121 On-Line Support ................................................................................................................................................................................123 Systems Information and Upgrade Hot Line..................................................................................................................................... 123 Reader Response............................................................................................................................................................................. 124 Product Identification System........................................................................................................................................................... 125 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Micro- chip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:127) Microchip’s Worldwide Web site; http://www.microchip.com (cid:127) Your local Microchip sales office (see last page) (cid:127) The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.  2003 Microchip Technology Inc. DS30235J-page 3

PIC16C62X NOTES: DS30235J-page 4  2003 Microchip Technology Inc.

PIC16C62X 1.0 GENERAL DESCRIPTION customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast The PIC16C62X devices are 18 and 20-Pin ROM/ and convenient. The small footprint packages make ® EPROM-based members of the versatile PICmicro this microcontroller series perfect for all applications family of low cost, high performance, CMOS, fully- with space limitations. Low cost, low power, high static, 8-bit microcontrollers. performance, ease of use and I/O flexibility make the All PICmicro microcontrollers employ an advanced PIC16C62X very versatile. RISC architecture. The PIC16C62X devices have 1.1 Family and Upward Compatibility enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The Those users familiar with the PIC16C5X family of separate instruction and data buses of the Harvard microcontrollers will realize that this is an enhanced architecture allow a 14-bit wide instruction word with version of the PIC16C5X architecture. Please refer to the separate 8-bit wide data. The two-stage instruction Appendix A for a detailed list of enhancements. Code pipeline allows all instructions to execute in a single written for the PIC16C5X can be easily ported to cycle, except for program branches (which require two PIC16C62X family of devices (Appendix B). The cycles). A total of 35 instructions (reduced instruction PIC16C62X family fills the niche for users wanting to set) are available. Additionally, a large register set migrate up from the PIC16C5X family and not needing gives some of the architectural innovations used to various peripheral features of other members of the achieve a very high performance. PIC16XX mid-range microcontroller family. PIC16C62X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over 1.2 Development Support other 8-bit microcontrollers in their class. The PIC16C62X family is supported by a full-featured The PIC16C620A, PIC16C621A and PIC16CR620A macro assembler, a software simulator, an in-circuit have 96 bytes of RAM. The PIC16C622(A) has 128 emulator, a low cost development programmer and a bytes of RAM. Each device has 13 I/O pins and an 8- full-featured programmer. Third Party “C” compilers are bit timer/counter with an 8-bit programmable prescaler. also available. In addition, the PIC16C62X adds two analog compara- tors with a programmable on-chip voltage reference module. The comparator module is ideally suited for applications requiring a low cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers,etc). PIC16C62X devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power con- sumption. There are four oscillator options, of which the single pin RC oscillator provides a low cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (Power-down) mode offers power savings. The user can wake-up the chip from SLEEP through several external and internal interrupts and RESET. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock- up. A UV-erasable CERDIP-packaged version is ideal for code development while the cost effective One-Time- Programmable (OTP) version is suitable for production in any volume. Table1-1 shows the features of the PIC16C62X mid- range microcontroller families. A simplified block diagram of the PIC16C62X is shown in Figure3-1. The PIC16C62X series fits perfectly in applications ranging from battery chargers to low power remote sensors. The EPROM technology makes  2003 Microchip Technology Inc. DS30235J-page 5

PIC16C62X TABLE 1-1: PIC16C62X FAMILY OF DEVICES PIC16C620(3) PIC16C620A(1)(4) PIC16CR620A(2) PIC16C621(3) PIC16C621A(1)(4) PIC16C622(3) PIC16C622A(1)(4) Clock Maximum Frequency 20 40 20 20 40 20 40 of Operation (MHz) Memory EPROM Program 512 512 512 1K 1K 2K 2K Memory (x14 words) Data Memory (bytes) 80 96 96 80 96 128 128 Peripherals Timer Module(s) TMR0 TMR0 TMRO TMR0 TMR0 TMR0 TMR0 Comparators(s) 2 2 2 2 2 2 2 Internal Reference Yes Yes Yes Yes Yes Yes Yes Voltage Features Interrupt Sources 4 4 4 4 4 4 4 I/O Pins 13 13 13 13 13 13 13 Voltage Range (Volts) 2.5-6.0 2.7-5.5 2.5-5.5 2.5-6.0 2.7-5.5 2.5-6.0 2.7-5.5 Brown-out Reset Yes Yes Yes Yes Yes Yes Yes Packages 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; SOIC; SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP ® All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. 2: For ROM parts, operation from 2.0V - 2.5V will require the PIC16LCR62XA parts. 3: For OTP parts, operation from 2.5V - 3.0V will require the PIC16LC62X part. 4: For OTP parts, operation from 2.7V - 3.0V will require the PIC16LC62XA part. DS30235J-page 6  2003 Microchip Technology Inc.

PIC16C62X 2.0 PIC16C62X DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP) Devices A variety of frequency ranges and packaging options are available. Depending on application and production Microchip offers a QTP programming service for requirements, the proper device option can be selected factory production orders. This service is made using the information in the PIC16C62X Product available for users who chose not to program a medium Identification System section at the end of this data to high quantity of units and whose code patterns have sheet. When placing orders, please use this page of stabilized. The devices are identical to the OTP the data sheet to specify the correct part number. devices, but with all EPROM locations and configura- tion options already programmed by the factory. 2.1 UV Erasable Devices Certain code and prototype verification procedures apply before production shipments are available. The UV erasable version, offered in CERDIP package, Please contact your Microchip Technology sales office is optimal for prototype development and pilot for more details. programs. This version can be erased and reprogrammed to any of the Oscillator modes. 2.4 Serialized Quick-Turnaround-   Microchip's PICSTART and PROMATE ProductionSM (SQTPSM) Devices programmers both support programming of the PIC16C62X. Microchip offers a unique programming service where a few user-defined locations in each device are Note: Microchip does not recommend code programmed with different serial numbers. The serial protecting windowed devices. numbers may be random, pseudo-random or sequential. 2.2 One-Time-Programmable (OTP) Devices Serial programming allows each device to have a unique number, which can serve as an entry-code, The availability of OTP devices is especially useful for password or ID number. customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed.  2003 Microchip Technology Inc. DS30235J-page 7

PIC16C62X NOTES: DS30235J-page 8  2003 Microchip Technology Inc.

PIC16C62X 3.0 ARCHITECTURAL OVERVIEW The PIC16C62X devices contain an 8-bit ALU and working register. The ALU is a general purpose The high performance of the PIC16C62X family can be arithmetic unit. It performs arithmetic and Boolean attributed to a number of architectural features functions between data in the working register and any commonly found in RISC microprocessors. To begin register file. with, the PIC16C62X uses a Harvard architecture, in The ALU is 8-bits wide and capable of addition, which, program and data are accessed from separate subtraction, shift and logical operations. Unless memories using separate busses. This improves otherwise mentioned, arithmetic operations are two's bandwidth over traditional von Neumann architecture, complement in nature. In two-operand instructions, where program and data are fetched from the same typically one operand is the working register memory. Separating program and data memory further (Wregister). The other operand is a file register or an allows instructions to be sized differently than 8-bit immediate constant. In single operand instructions, the wide data word. Instruction opcodes are 14-bits wide operand is either the W register or a file register. making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a The W register is an 8-bit working register used for ALU 14-bit instruction in a single cycle. A two-stage pipeline operations. It is not an addressable register. overlaps fetch and execution of instructions. Depending on the instruction executed, the ALU may Consequently, all instructions (35) execute in a single affect the values of the Carry (C), Digit Carry (DC), and cycle (200 ns @ 20 MHz) except for program branches. Zero (Z) bits in the STATUS register. The C and DC bits The PIC16C620(A) and PIC16CR620A address operate as a Borrow and Digit Borrow out bit, 512x14 on-chip program memory. The PIC16C621(A) respectively, bit in subtraction. See the SUBLW and addresses 1Kx14 program memory. The SUBWF instructions for examples. PIC16C622(A) addresses 2Kx14 program memory. A simplified block diagram is shown in Figure3-1, with All program memory is internal. a description of the device pins in Table3-1. The PIC16C62X can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16C62X has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any Addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16C62X simple yet efficient. In addition, the learning curve is reduced significantly.  2003 Microchip Technology Inc. DS30235J-page 9

PIC16C62X FIGURE 3-1: BLOCK DIAGRAM Program Data Memory Device Memory (RAM) PIC16C620 512 x 14 80 x 8 PIC16C620A 512 x 14 96 x 8 PIC16CR620A 512 x 14 96 x 8 PIC16C621 1K x 14 80 x 8 PIC16C621A 1K x 14 96 x 8 PIC16C622 2K x 14 128 x 8 PIC16C622A 2K x 14 128 x 8 Voltage 13 Data Bus 8 Reference Program Counter EPROM Program RAM 8-Level Stack Memory (13-bit) File Registers Program Bus 14 RAM Addr (1) 9 Comparator RA0/AN0 Addr MUX Instruction reg RA1/AN1 Direct Addr 7 8 InAddirderct +- RA2/AN2/VREF RA3/AN3 - FSR reg + STATUS reg TMR0 3 MUX Power-up Timer RA4/T0CKI Instruction Decode & Oscillator Control Start-up Timer ALU Power-on Timing Reset Generation Watchdog W reg I/O Ports OSC1/CLKIN Timer OSC2/CLKOUT Brown-out Reset PORTB MCLR VDD, VSS Note 1: Higher order bits are from the STATUS register. DS30235J-page 10  2003 Microchip Technology Inc.

PIC16C62X TABLE 3-1: PIC16C62X PINOUT DESCRIPTION DIP/SOIC SSOP Buffer Name I/O/P Type Description Pin # Pin # Type OSC1/CLKIN 16 18 I ST/CMOS Oscillator crystal input/external clock source input. OSC2/CLKOUT Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin out- 15 17 O — puts CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. MCLR/VPP Master Clear (Reset) input/programming voltage input. 4 4 I/P ST This pin is an Active Low Reset to the device. PORTA is a bi-directional I/O port. RA0/AN0 17 19 I/O ST Analog comparator input RA1/AN1 18 20 I/O ST Analog comparator input RA2/AN2/VREF 1 1 I/O ST Analog comparator input or VREF output RA3/AN3 2 2 I/O ST Analog comparator input /output RA4/T0CKI Can be selected to be the clock input to the Timer0 3 3 I/O ST timer/counter or a comparator output. Output is open drain type. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT RB0/INT can also be selected as an external 6 7 I/O TTL/ST(1) interrupt pin. RB1 7 8 I/O TTL RB2 8 9 I/O TTL RB3 9 10 I/O TTL RB4 10 11 I/O TTL Interrupt-on-change pin. RB5 11 12 I/O TTL Interrupt-on-change pin. RB6 12 13 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming clock. RB7 13 14 I/O TTL/ST(2) Interrupt-on-change pin. Serial programming data. VSS 5 5,6 P — Ground reference for logic and I/O pins. VDD 14 15,16 P — Positive supply for logic and I/O pins. Legend: O = output I/O = input/output P = power — = Not used I = Input ST = Schmitt Trigger input TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.  2003 Microchip Technology Inc. DS30235J-page 11

PIC16C62X 3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining Cycle An “Instruction Cycle” consists of four Q cycles (Q1, The clock input (OSC1/CLKIN pin) is internally divided Q2, Q3 and Q4). The instruction fetch and execute are by four to generate four non-overlapping quadrature pipelined such that fetch takes one instruction cycle clocks namely Q1, Q2, Q3 and Q4. Internally, the while decode and execute takes another instruction program counter (PC) is incremented every Q1, the cycle. However, due to the pipelining, each instruction instruction is fetched from the program memory and effectively executes in one cycle. If an instruction latched into the instruction register in Q4. The causes the program counter to change (e.g., GOTO) instruction is decoded and executed during the then two cycles are required to complete the instruction following Q1 through Q4. The clocks and instruction (Example3-1). execution flow is shown in Figure3-2. A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS30235J-page 12  2003 Microchip Technology Inc.

PIC16C62X 4.0 MEMORY ORGANIZATION FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR THE 4.1 Program Memory Organization PIC16C621/PIC16C621A The PIC16C62X has a 13-bit program counter capable PC<12:0> of addressing an 8Kx14 program memory space. Only CALL, RETURN 13 the first 512 x 14 (0000h - 01FFh) for the RETFIE, RETLW PIC16C620(A) and PIC16CR620, 1K x 14 (0000h - 03FFh) for the PIC16C621(A) and 2K x 14 (0000h - Stack Level 1 07FFh) for the PIC16C622(A) are physically Stack Level 2 implemented. Accessing a location above these boundaries will cause a wrap-around within the first 512x14 space (PIC16C(R)620(A)) or 1K x 14 space Stack Level 8 (PIC16C621(A)) or 2Kx14 space (PIC16C622(A)). The RESET vector is at 0000h and the interrupt vector RESET Vector 000h is at 0004h (Figure4-1, Figure4-2, Figure4-3). FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE Interrupt Vector 0004 PIC16C620/PIC16C620A/ 0005 PIC16CR620A On-Chip Program PC<12:0> Memory CALL, RETURN 03FFh 13 RETFIE, RETLW 0400h Stack Level 1 Stack Level 2 1FFFh FIGURE 4-3: PROGRAM MEMORY MAP Stack Level 8 AND STACK FOR THE PIC16C622/PIC16C622A RESET Vector 000h PC<12:0> CALL, RETURN 13 RETFIE, RETLW Stack Level 1 Interrupt Vector 0004 Stack Level 2 0005 On-Chip Program Stack Level 8 Memory RESET Vector 01FFh 000h 0200h Interrupt Vector 0004 1FFFh 0005 On-Chip Program Memory 07FFh 0800h 1FFFh  2003 Microchip Technology Inc. DS30235J-page 13

PIC16C62X 4.2 Data Memory Organization 4.2.1 GENERAL PURPOSE REGISTER FILE The data memory (Figure4-4, Figure4-5, Figure4-6 and Figure4-7) is partitioned into two banks, which The register file is organized as 80 x 8 in the contain the General Purpose Registers and the Special PIC16C620/621, 96 x 8 in the PIC16C620A/621A/ Function Registers. Bank 0 is selected when the RP0 CR620A and 128 x 8 in the PIC16C622(A). Each is bit is cleared. Bank 1 is selected when the RP0 bit accessed either directly or indirectly through the File (STATUS <5>) is set. The Special Function Registers Select Register FSR (Section4.4). are located in the first 32 locations of each bank. Register locations 20-7Fh (Bank0) on the PIC16C620A/CR620A/621A and 20-7Fh (Bank0) and A0-BFh (Bank1) on the PIC16C622 and PIC16C622A are General Purpose Registers implemented as static RAM. Some Special Purpose Registers are mapped in Bank 1. Addresses F0h-FFh of bank1 are implemented as common ram and mapped back to addresses 70h-7Fh in bank0 on the PIC16C620A/621A/622A/CR620A. DS30235J-page 14  2003 Microchip Technology Inc.

PIC16C62X FIGURE 4-4: DATA MEMORY MAP FOR FIGURE 4-5: DATA MEMORY MAP FOR THE PIC16C620/621 THE PIC16C622 File File File File Address Address Address Address (1) (1) (1) (1) 00h INDF INDF 80h 00h INDF INDF 80h 01h TMR0 OPTION 81h 01h TMR0 OPTION 81h 02h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h 07h 87h 07h 87h 08h 88h 08h 88h 09h 89h 09h 89h 0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Ch PIR1 PIE1 8Ch 0Dh 8Dh 0Dh 8Dh 0Eh PCON 8Eh 0Eh PCON 8Eh 0Fh 8Fh 0Fh 8Fh 10h 90h 10h 90h 11h 91h 11h 91h 12h 92h 12h 92h 13h 93h 13h 93h 14h 94h 14h 94h 15h 95h 15h 95h 16h 96h 16h 96h 17h 97h 17h 97h 18h 98h 18h 98h 19h 99h 19h 99h 1Ah 9Ah 1Ah 9Ah 1Bh 9Bh 1Bh 9Bh 1Ch 9Ch 1Ch 9Ch 1Dh 9Dh 1Dh 9Dh 1Eh 9Eh 1Eh 9Eh 1Fh CMCON VRCON 9Fh 1Fh CMCON VRCON 9Fh 20h A0h 20h A0h General General General Purpose Purpose Purpose Register Register Register 6Fh BFh 70h C0h 7Fh FFh 7Fh FFh Bank 0 Bank 1 Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. Note 1: Not a physical register.  2003 Microchip Technology Inc. DS30235J-page 15

PIC16C62X FIGURE 4-6: DATA MEMORY MAP FOR THE FIGURE 4-7: DATA MEMORY MAP FOR PIC16C620A/CR620A/621A THE PIC16C622A File File File File Address Address Address Address (1) (1) (1) (1) 00h INDF INDF 80h 00h INDF INDF 80h 01h TMR0 OPTION 81h 01h TMR0 OPTION 81h 02h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h 07h 87h 07h 87h 08h 88h 08h 88h 09h 89h 09h 89h 0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Ch PIR1 PIE1 8Ch 0Dh 8Dh 0Dh 8Dh 0Eh PCON 8Eh 0Eh PCON 8Eh 0Fh 8Fh 0Fh 8Fh 10h 90h 10h 90h 11h 91h 11h 91h 12h 92h 12h 92h 13h 93h 13h 93h 14h 94h 14h 94h 15h 95h 15h 95h 16h 96h 16h 96h 17h 97h 17h 97h 18h 98h 18h 98h 19h 99h 19h 99h 1Ah 9Ah 1Ah 9Ah 1Bh 9Bh 1Bh 9Bh 1Ch 9Ch 1Ch 9Ch 1Dh 9Dh 1Dh 9Dh 1Eh 9Eh 1Eh 9Eh 1Fh CMCON VRCON 9Fh 1Fh CMCON VRCON 9Fh 20h A0h 20h A0h General General General Purpose Purpose Purpose Register Register Register BFh C0h 6Fh 6Fh F0h F0h 70h General 70h General Purpose Accesses Purpose Accesses Register 70h-7Fh Register 70h-7Fh 7Fh FFh 7Fh FFh Bank 0 Bank 1 Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. Note 1: Not a physical register. DS30235J-page 16  2003 Microchip Technology Inc.

PIC16C62X 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets (core and peripheral). The Special Function The Special Function Registers are registers used by Registers associated with the “core” functions are the CPU and Peripheral functions for controlling the described in this section. Those related to the operation desired operation of the device (Table4-1). These of the peripheral features are described in the section registers are static RAM. of that peripheral feature. TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C62X Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR Reset RESETS(1) Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx xxxx xxxx register) 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 03h STATUS IRP(2) RP1(2) RP0 TO PD Z DC C 0001 1xxx 000q quuu 04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h-09h Unimplemented — — 0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 0Dh-1Eh Unimplemented — — 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx xxxx xxxx register) 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 83h STATUS IRP(2) RP1(2) RP0 TO PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 87h-89h Unimplemented — — 8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 — CMIE — — — — — — -0-- ---- -0-- ---- 8Dh Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --0x ---- --uq 8Fh-9Eh Unimplemented — — 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation. 2: IRP & RP1 bits are reserved; always maintain these bits clear.  2003 Microchip Technology Inc. DS30235J-page 17

PIC16C62X 4.2.2.1 STATUS Register It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The STATUS register, shown in Register4-1, contains STATUS register, because these instructions do not the arithmetic status of the ALU, the RESET status and affect any STATUS bit. For other instructions not the bank select bits for data memory. affecting any STATUS bits, see the “Instruction Set The STATUS register can be the destination for any Summary”. instruction, like any other register. If the STATUS register is the destination for an instruction that affects Note 1: The IRP and RP1 bits (STATUS<7:6>) the Z, DC or C bits, then the write to these three bits is are not used by the PIC16C62X and should be programmed as ’0'. Use of disabled. These bits are set or cleared according to the these bits as general purpose R/W bits is device logic. Furthermore, the TO and PD bits are not NOT recommended, since this may affect writable. Therefore, the result of an instruction with the upward compatibility with future products. STATUS register as destination may be different than intended. 2: The C and DC bits operate as a Borrow For example, CLRF STATUS will clear the upper-three and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF bits and set the Z bit. This leaves the STATUS register as 000uu1uu (where u = unchanged). instructions for examples. REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H) Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) The IRP bit is reserved on the PIC16C62X; always maintain this bit clear. bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C62X; always maintain this bit clear. bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30235J-page 18  2003 Microchip Technology Inc.

PIC16C62X 4.2.2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for The OPTION register is a readable and writable TMR0, assign the prescaler to the WDT register, which contains various control bits to configure (PSA = 1). the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: OPTION REGISTER (ADDRESS 81H) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS30235J-page 19

PIC16C62X 4.2.2.3 INTCON Register Note: Interrupt flag bits get set when an interrupt The INTCON register is a readable and writable condition occurs, regardless of the state of register, which contains the various enable and flag bits its corresponding enable bit or the global for all interrupt sources except the comparator module. enable bit, GIE (INTCON<7>). See Section4.2.2.4 and Section4.2.2.5 for a description of the comparator enable and flag bits. REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit 7 bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30235J-page 20  2003 Microchip Technology Inc.

PIC16C62X 4.2.2.4 PIE1 Register This register contains the individual enable bit for the comparator interrupt. REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — CMIE — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt bit 5-0 Unimplemented: Read as '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown 4.2.2.5 PIR1 Register This register contains the individual flag bit for the comparator interrupt. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — CMIF — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed bit 5-0 Unimplemented: Read as '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS30235J-page 21

PIC16C62X 4.2.2.6 PCON Register The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR Reset, WDT Reset or a Brown-out Reset. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is cleared, indicating a brown-out has occurred. The BOR STATUS bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BODEN bit in the Configuration word). REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — POR BOR bit 7 bit 0 bit 7-2 Unimplemented: Read as '0' bit 1 POR: Power-on Reset STATUS bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset STATUS bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown DS30235J-page 22  2003 Microchip Technology Inc.

PIC16C62X 4.3 PCL and PCLATH 4.3.2 STACK The program counter (PC) is 13-bits wide. The low byte The PIC16C62X family has an 8-level deep x 13-bit comes from the PCL register, which is a readable and wide hardware stack (Figure4-2 and Figure4-3). The writable register. The high byte (PC<12:8>) is not stack space is not part of either program or data space directly readable or writable and comes from PCLATH. and the stack pointer is not readable or writable. The On any RESET, the PC is cleared. Figure4-8 shows PC is PUSHed onto the stack when a CALL instruction the two situations for the loading of the PC. The upper is executed or an interrupt causes a branch. The stack example in the figure shows how the PC is loaded on a is POPed in the event of a RETURN, RETLW or a write to PCL (PCLATH<4:0> → PCH). The lower RETFIE instruction execution. PCLATH is not affected example in the figure shows how the PC is loaded by a PUSH or POP operation. during a CALL or GOTO instruction (PCLATH<4:3> → The stack operates as a circular buffer. This means that PCH). after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first FIGURE 4-8: LOADING OF PC IN push. The tenth push overwrites the second push (and DIFFERENT SITUATIONS so on). Note 1: There are no STATUS bits to indicate PCH PCL stack overflow or stack underflow 12 8 7 0 Instruction with conditions. PC PCL as 2: There are no instructions/mnemonics Destination PCLATH<4:0> 8 called PUSH or POP. These are actions 5 ALU result that occur from the execution of the CALL, RETURN, RETLW and RETFIE PCLATH instructions, or the vectoring to an interrupt address. PCH PCL 12 11 10 8 7 0 PC GOTO,CALL PCLATH<4:3> 11 2 Opcode <10:0> PCLATH 4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note, “Implementing a Table Read" (AN556).  2003 Microchip Technology Inc. DS30235J-page 23

PIC16C62X 4.4 Indirect Addressing, INDF and EXAMPLE 4-1: INDIRECT ADDRESSING FSR Registers movlw 0x20 ;initialize pointer movwf FSR ;to RAM The INDF register is not a physical register. Addressing NEXT clrf INDF ;clear INDF register the INDF register will cause indirect addressing. incf FSR ;inc pointer btfss FSR,7 ;all done? Indirect addressing is possible by using the INDF goto NEXT ;no clear next register. Any instruction using the INDF register ;yes continue actually accesses data pointed to by the File Select CONTINUE: Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure4-9. However, IRP is not used in the PIC16C62X. A simple program to clear RAM location 20h-7Fh using indirect addressing is shown in Example4-1. FIGURE 4-9: DIRECT/INDIRECT ADDRESSING PIC16C62X Direct Addressing Indirect Addressing RP1 RP0(1) 6 from opcode 0 IRP(1) 7 FSR register 0 bank select location select bank select location select 00 01 10 11 00h 180h not used Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see (Figure4-4, Figure4-5, Figure4-6 and Figure4-7). Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. DS30235J-page 24  2003 Microchip Technology Inc.

PIC16C62X 5.0 I/O PORTS Note: On RESET, the TRISA register is set to all The PIC16C62X have two ports, PORTA and PORTB. inputs. The digital inputs are disabled and Some pins for these I/O ports are multiplexed with an the comparator inputs are forced to ground alternate function for the peripheral features on the to reduce excess current consumption. device. In general, when a peripheral is enabled, that TRISA controls the direction of the RA pins, even when pin may not be used as a general purpose I/O pin. they are being used as comparator inputs. The user must make sure to keep the pins configured as inputs 5.1 PORTA and TRISA Registers when using them as comparator inputs. PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger The RA2 pin will also function as the output for the input and an open drain output. Port RA4 is multiplexed voltage reference. When in this mode, the VREF pin is a with the T0CKI clock input. All other RA port pins have very high impedance output and must be buffered prior Schmitt Trigger input levels and full CMOS output to any external load. The user must configure drivers. All pins have data direction bits (TRIS regis- TRISA<2> bit as an input and use high impedance ters), which can configure these pins as input or output. loads. A '1' in the TRISA register puts the corresponding out- In one of the Comparator modes defined by the put driver in a Hi-impedance mode. A '0' in the TRISA CMCON register, pins RA3 and RA4 become outputs register puts the contents of the output latch on the of the comparators. The TRISA<4:3> bits must be selected pin(s). cleared to enable outputs to use this function. Reading the PORTA register reads the status of the EXAMPLE 5-1: INITIALIZING PORTA pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a CLRF PORTA ;Initialize PORTA by setting write to a port implies that the port pins are first read, ;output data latches then this value is modified and written to the port data MOVLW 0X07 ;Turn comparators off and latch. MOVWF CMCON ;enable pins for I/O ;functions The PORTA pins are multiplexed with comparator and BSF STATUS, RP0 ;Select Bank1 voltage reference functions. The operation of these pins are selected by control bits in the CMCON MOVLW 0x1F ;Value used to initialize (comparator control register) register and the VRCON ;data direction (voltage reference control register) register. When MOVWF TRISA ;Set RA<4:0> as inputs selected as a comparator input, these pins will read ;TRISA<7:5> are always as'0's. ;read as '0'. FIGURE 5-1: BLOCK DIAGRAM OF FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN RA1:RA0 PINS Data Bus Data D Q Bus D Q WR VDD VDD PORTA WR VDD VDD CK Q P PORTA CK Q Data Latch P Data Latch D Q RA2 D Q WR N Pin WR N PI/Oin TRISA CK Q VSS TRISA CK Q VSS TRIS Latch Analog VSS Input Mode TRIS Latch VSS Analog Schmitt Trigger Input Mode Input Buffer RD TRISA Schmitt Trigger Input Buffer Q D RD TRISA Q D EN RD PORTA EN To Comparator RD PORTA VROE To Comparator VREF  2003 Microchip Technology Inc. DS30235J-page 25

PIC16C62X FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN Data Comparator Mode = 110 Bus D Q Comparator Output WR VDD VDD PORTA CK Q P Data Latch D Q RA3 Pin WR N TRISA CK Q VSS TRIS Latch VSS Analog Input Mode Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA To Comparator FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN Data Comparator Mode = 110 Bus D Q Comparator Output WR PORTA CK Q Data Latch D Q RA4 Pin WR N TRISA CK Q VSS TRIS Latch VSS Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA TMR0 Clock Input DS30235J-page 26  2003 Microchip Technology Inc.

PIC16C62X TABLE 5-1: PORTA FUNCTIONS Buffer Name Bit # Function Type RA0/AN0 bit0 ST Input/output or comparator input RA1/AN1 bit1 ST Input/output or comparator input RA2/AN2/VREF bit2 ST Input/output or comparator input or VREF output RA3/AN3 bit3 ST Input/output or comparator input/output RA4/T0CKI Input/output or external clock input for TMR0 or comparator output. bit4 ST Output is open drain type. Legend: ST = Schmitt Trigger input TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR RESETS 05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 85h TRISA TRISA TRISA TRISA TRISA TRISA ---1 1111 ---1 1111 — — — 4 3 2 1 0 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown Note: Shaded bits are not used by PORTA.  2003 Microchip Technology Inc. DS30235J-page 27

PIC16C62X 5.2 PORTB and TRISB Registers This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the PORTB is an 8-bit wide, bi-directional port. The interrupt in the following manner: corresponding data direction register is TRISB. A '1' in a) Any read or write of PORTB. This will end the the TRISB register puts the corresponding output driver mismatch condition. in a High Impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected b) Clear flag bit RBIF. pin(s). A mismatch condition will continue to set flag bit RBIF. Reading PORTB register reads the status of the pins, Reading PORTB will end the mismatch condition and whereas writing to it will write to the port latch. All write allow flag bit RBIF to be cleared. operations are read-modify-write operations. So a write This interrupt on mismatch feature, together with to a port implies that the port pins are first read, then software configurable pull-ups on these four pins allow this value is modified and written to the port data latch. easy interface to a key pad and make it possible for Each of the PORTB pins has a weak internal pull-up wake-up on key-depression. (See AN552, “Implement- (≈200 µA typical). A single control bit can turn on all the ing Wake-Up on Key Strokes.) pull-ups. This is done by clearing the RBPU Note: If a change on the I/O pin should occur (OPTION<7>) bit. The weak pull-up is automatically when the read operation is being executed turned off when the port pin is configured as an output. (start of the Q2 cycle), then the RBIF inter- The pull-ups are disabled on Power-on Reset. rupt flag may not getset. Four of PORTB’s pins, RB<7:4>, have an interrupt on The interrupt-on-change feature is recommended for change feature. Only pins configured as inputs can wake-up on key depression operation and operations cause this interrupt to occur (e.g., any RB<7:4> pin where PORTB is only used for the interrupt on change configured as an output is excluded from the interrupt feature. Polling of PORTB is not recommended while on change comparison). The input pins (of RB<7:4>) using the interrupt-on-change feature. are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB<7:4> FIGURE 5-6: BLOCK DIAGRAM OF are OR’ed together to generate the RBIF interrupt (flag RB<3:0> PINS latched in INTCON<0>). VDD FIGURE 5-5: BLOCK DIAGRAM OF RBPU(1) weak RB<7:4> PINS P pull-up VCC VDD RBPU(1) weak Data Latch Ppull-up Data Bus D Q VCC I/O WR PORTB pin CK Q Data Bus Data Latch VSS D Q I/O D Q WR PORTB pin TTL CK Q VSS WR TRISB CK Q IBnupfufetr TRIS Latch D Q WR TRISB TTL CKQ Input RD TRISB Buffer ST Buffer Q D RD TRISB Latch RD PORTB EN Q D RB0/INT RD PORTB EN Set RBIF ST Buffer RD PORTB Note 1: TRISB = 1 enables weak pull-up if RBPU = '0' From other Q D (OPTION<7>). RB<7:4> pins EN RD PORTB RB<7:6> in Serial Programming mode Note 1: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>). DS30235J-page 28  2003 Microchip Technology Inc.

PIC16C62X TABLE 5-3: PORTB FUNCTIONS Name Bit # Buffer Type Function (1) RB0/INT bit0 TTL/ST Input/output or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. (2) RB6 bit6 TTL/ST Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock pin. (2) RB7 bit7 TTL/ST Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data pin. Legend: ST = Schmitt Trigger, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR RESETS 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: u = unchanged, x = unknown Note 1: Shaded bits are not used by PORTB.  2003 Microchip Technology Inc. DS30235J-page 29

PIC16C62X 5.3 I/O Programming Considerations EXAMPLE 5-2: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O 5.3.1 BI-DIRECTIONAL I/O PORTS PORT Any instruction which writes, operates internally as a ;Initial PORT settings: PORTB<7:4> Inputs ; read followed by a write operation. The BCF and BSF ; PORTB<3:0> Outputs instructions, for example, read the register into the CPU, execute the bit operation and write the result ;PORTB<7:6> have external pull-up and are not ;connected to other circuitry back to the register. Caution must be used when these ; instructions are applied to a port with both inputs and ; PORT latch PORT pins outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read ; ---------- --------- - into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If BCF PORTB, 7 ;01pp pppp 11pp pppp another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the BCF PORTB, 6 ;10pp pppp 11pp pppp input signal present on the pin itself would be read into BSF STATUS,RP0 ; the CPU and re-written to the data latch of this BCF TRISB, 7 ;10pp pppp 11pp pppp particular pin, overwriting the previous content. As long BCF TRISB, 6 ;10pp pppp 10pp pppp as the pin stays in the Input mode, no problem occurs. ; However, if bit0 is switched into Output mode later on, ;Note that the user may have expected the pin the content of the data latch may now be unknown. ;values to be 00pp pppp. The 2nd BCF caused Reading the port register reads the values of the port ;RB7 to be latched as the pin value (High). pins. Writing to the port register writes the value to the 5.3.2 SUCCESSIVE OPERATIONS ON I/O port latch. When using read-modify-write instructions PORTS (ex. BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and The actual write to an I/O port happens at the end of an this value is then written to the port latch. instruction cycle, whereas for reading, the data must be Example5-2 shows the effect of two sequential read- valid at the beginning of the instruction cycle (Figure5-7). modify-write instructions (ex., BCF, BSF, etc.) on an Therefore, care must be exercised if a write followed by a I/Oport. read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin A pin actively outputting a Low or High should not be voltage to stabilize (load dependent) before the next driven from external devices at the same time in order instruction which causes that file to be read into the CPU to change the level on this pin (“wired-or”, “wired-and”). is executed. Otherwise, the previous state of that pin may The resulting high output currents may damage be read into the CPU rather than the new state. When in the chip. doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-7: SUCCESSIVE I/O OPERATION Note: QQ11 QQ22 QQ33 QQ44 QQ11 QQ22 QQ33 QQ44 QQ11 QQ22 QQ33 QQ44 QQ11 QQ22 QQ33 QQ44 This example shows write to PORTB PPCC PPCC PPCC ++ 11 PPCC ++ 22 PPCC ++3 3 followed by a read from PORTB. IInnssttrruucctitoionn MMOOVVWWFF, P OPORRTTBB MMOOVVFF, P OPORRTTBB, ,W W NNOOPP NNOOPP Note that: ffeettcchheedd WWrriittee ttoo RReeaadd PPOORRTTBB PPOORRTTBB data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and RB<7:0> RB <7:0> TPD = propagation delay of Q1 cycle to output valid. PPoorrtt ppiinn Therefore, at higher clock frequen- ssaammpplleedd hheerree cies, a write followed by a read may TTPPDD be problematic. EExxeeccuuttee EExxeeccuuttee EExxeeccuuttee MMOOVVWWFF MMOOVVFF NNOOPP PPOORRTTBB PPOORRTTBB,, WW DS30235J-page 30  2003 Microchip Technology Inc.

PIC16C62X 6.0 TIMER0 MODULE The prescaler is shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is The Timer0 module timer/counter has the following controlled in software by the control bit PSA features: (OPTION<3>). Clearing the PSA bit will assign the (cid:127) 8-bit timer/counter prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 (cid:127) Readable and writable module, prescale value of 1:2, 1:4, ..., 1:256 are (cid:127) 8-bit software programmable prescaler selectable. Section6.3 details the operation of the (cid:127) Internal or external clock select prescaler. (cid:127) Interrupt on overflow from FFh to 00h 6.1 TIMER0 Interrupt (cid:127) Edge select for external clock Figure6-1 is a simplified block diagram of the Timer0 Timer0 interrupt is generated when the TMR0 register module. timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by Timer mode is selected by clearing the T0CS bit clearing the T0IE bit (INTCON<5>). The T0IF bit (OPTION<5>). In Timer mode, the TMR0 will increment (INTCON<2>) must be cleared in software by the every instruction cycle (without prescaler). If Timer0 is Timer0 module interrupt service routine before re- written, the increment is inhibited for the following two enabling this interrupt. The Timer0 interrupt cannot cycles (Figure6-2 and Figure6-3). The user can work wake the processor from SLEEP, since the timer is shut around this by writing an adjusted value to TMR0. off during SLEEP. See Figure6-4 for Timer0 interrupt Counter mode is selected by setting the T0CS bit. In timing. this mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge (T0SE) control bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section6.2. FIGURE 6-1: TIMER0 BLOCK DIAGRAM Data Bus RA4/T0CKI FOSC/4 0 pin PSout 8 1 Sync with 1 Internal TMR0 clocks Programmable 0 PSout Prescaler T0SE (2 Tcy delay) Set Flag bit T0IF PS<2:0> PSA on Overflow T0CS Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register. 2: The prescaler is shared with Watchdog Timer (Figure6-6). FIGURE 6-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W Fetch TMR0 T0 T0+1 T0+2 NT0 NT0+1 NT0+2 T0 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2  2003 Microchip Technology Inc. DS30235J-page 31

PIC16C62X FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W Fetch TMR0 T0 T0+1 NT0 NT0+1 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 FIGURE 6-4: TIMER0 INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) TMR0 timer FEh FFh 00h 01h 02h 1 1 T0IF bit (INTCON<2>) GIE bit (INTCON<7>) Interrupt Latency Time(2) INSTRUCTION FLOW PC PC PC +1 PC +1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h) Instruction Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h) executed Note 1: T0IF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 3TCY, where TCY = instruction cycle time. 3: CLKOUT is available only in RC Oscillator mode. DS30235J-page 32  2003 Microchip Technology Inc.

PIC16C62X 6.2 Using Timer0 with External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type When an external clock input is used for Timer0, it must prescaler, so that the prescaler output is symmetrical. meet certain requirements. The external clock For the external clock to meet the sampling requirement is due to internal phase clock (TOSC) requirement, the ripple-counter must be taken into synchronization. Also, there is a delay in the actual account. Therefore, it is necessary for T0CKI to have a incrementing of Timer0 after synchronization. period of at least 4TOSC (and a small RC delay of 40ns) divided by the prescaler value. The only requirement 6.2.1 EXTERNAL CLOCK on T0CKI high and low time is that they do not violate SYNCHRONIZATION the minimum pulse width requirement of 10ns. Refer to parameters 40, 41 and 42 in the electrical specification When no prescaler is used, the external clock input is of the desired device. the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is 6.2.2 TIMER0 INCREMENT DELAY accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Since the prescaler output is synchronized with the (Figure6-5). Therefore, it is necessary for T0CKI to be internal clocks, there is a small delay from the time the high for at least 2TOSC (and a small RC delay of 20 ns) external clock edge occurs to the time the TMR0 is and low for at least 2TOSC (and a small RC delay of actually incremented. Figure6-5 shows the delay from 20ns). Refer to the electrical specification of the the external clock edge to the timer incrementing. desired device. FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse External Clock Input or (2) misses sampling Prescaler output (1) (3) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.  2003 Microchip Technology Inc. DS30235J-page 33

PIC16C62X 6.3 Prescaler The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. An 8-bit counter is available as a prescaler for the When assigned to the Timer0 module, all instructions Timer0 module, or as a postscaler for the Watchdog writing to the TMR0 register (e.g., CLRF 1, Timer, respectively (Figure6-6). For simplicity, this MOVWF 1, BSF 1,x....etc.) will clear the prescaler. counter is being referred to as “prescaler” throughout When assigned to WDT, a CLRWDT instruction will clear this data sheet. Note that there is only one prescaler the prescaler along with the Watchdog Timer. The available which is mutually exclusive between the prescaler is not readable or writable. Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer and vice-versa. FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (= Fosc/4) Data Bus 8 M 0 1 T0CKI U M SYNC pin 1 X 0 U 2 TMR0 reg X Cycles T0SE T0CS Set flag bit T0IF PSA on Overflow 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8-to-1MUX PS<2:0> PSA 0 1 WDT Enable bit M U X PSA WDT Time-out Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. DS30235J-page 34  2003 Microchip Technology Inc.

PIC16C62X 6.3.1 SWITCHING PRESCALER To change prescaler from the WDT to the TMR0 ASSIGNMENT module, use the sequence shown in Example6-2. This precaution must be taken even if the WDT is disabled. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during EXAMPLE 6-2: CHANGING PRESCALER program execution). To avoid an unintended device (WDT→TIMER0) RESET, the following instruction sequence (Example6-1) must be executed when changing the CLRWDT ;Clear WDT and ;prescaler prescaler assignment from Timer0 to WDT.) BSF STATUS, RP0 MOVLW b'xxxx0xxx' ;Select TMR0, new EXAMPLE 6-1: CHANGING PRESCALER ;prescale value and ;clock source (TIMER0→WDT) MOVWF OPTION_REG BCF STATUS, RP0 1.BCF STATUS, RP0 ;Skip if already in ;Bank 0 2.CLRWDT ;Clear WDT 3.CLRF TMR0 ;Clear TMR0 & Prescaler 4.BSF STATUS, RP0 ;Bank 1 5.MOVLW '00101111’b; ;These 3 lines (5, 6, 7) 6.MOVWF OPTION ;are required only if ;desired PS<2:0> are 7.CLRWDT ;000 or 001 8.MOVLW '00101xxx’b ;Set Postscaler to 9.MOVWF OPTION ;desired WDT rate 10.BCF STATUS, RP0 ;Return to Bank 0 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR RESETS 01h TMR0 Timer0 module register xxxx xxxx uuuu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown Note: Shaded bits are not used by TMR0 module.  2003 Microchip Technology Inc. DS30235J-page 35

PIC16C62X NOTES: DS30235J-page 36  2003 Microchip Technology Inc.

PIC16C62X 7.0 COMPARATOR MODULE The CMCON register, shown in Register7-1, controls the comparator input and output multiplexers. A block The comparator module contains two analog diagram of the comparator is shown in Figure7-1. comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The On- Chip Voltage Reference (Section8.0) can also be an input to the comparators. REGISTER 7-1: CMCON REGISTER (ADDRESS 1Fh) R-0 R-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT — — CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 output 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- bit 6 C1OUT: Comparator 1 output 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- bit 5-4 Unimplemented: Read as ‘0’ bit 3 CIS: Comparator Input Switch When CM<2:0>: = 001: 1 = C1 VIN- connects to RA3 0 = C1 VIN- connects to RA0 When CM<2:0> = 010: 1 = C1 VIN- connects to RA3 C2 VIN- connects to RA2 0 = C1 VIN- connects to RA0 C2 VIN- connects to RA1 bit 2-0 CM<2:0>: Comparator mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown  2003 Microchip Technology Inc. DS30235J-page 37

PIC16C62X 7.1 Comparator Configuration mode is changed, the comparator output level may not be valid for the specified mode change delay shown There are eight modes of operation for the in Table12-2. comparators. The CMCON register is used to select the mode. Figure7-1 shows the eight possible modes. Note: Comparator interrupts should be disabled The TRISA register controls the data direction of the during a Comparator mode change other- comparator pins for each mode. If the Comparator wise a false interrupt may occur. FIGURE 7-1: COMPARATOR I/O OPERATING MODES A VIN- - D VIN- - RA0/AN0 Off RA0/AN0 Off C1 C1 A VIN+ + (Read as '0') D VIN+ + (Read as '0') RA3/AN3 RA3/AN3 A VIN- - D VIN- - RA1/AN1 Off RA1/AN1 Off C2 C2 A VIN+ + (Read as '0') D VIN+ + (Read as '0') RA2/AN2 RA2/AN2 CM<2:0> = 000 CM<2:0> = 111 Comparators Reset Comparators Off RA0/AN0 A VIN- - C1 C1OUT RA0/AN0 A CIS=0 VIN- - A VIN+ + RA3/AN3 A CIS=1 C1 C1OUT RA3/AN3 VIN+ + A VIN- - RA1/AN1 A CIS=0 RA1/AN1 C2 C2OUT VIN- - A VIN+ + RA2/AN2 A CIS=1 C2 C2OUT RA2/AN2 VIN+ + CM<2:0> = 100 From VREF Module Two Independent Comparators Four Inputs Multiplexed to CM<2:0> = 010 Two Comparators A VIN- - A VIN- - RA0/AN0 RA0/AN0 C1 C1OUT C1 C1OUT D VIN+ + D VIN+ + RA3/AN3 RA3/AN3 A VIN- - A VIN- - RA1/AN1 RA1/AN1 C2 C2OUT C2 C2OUT A VIN+ + A VIN+ + RA2/AN2 RA2/AN2 RA4 Open Drain CM<2:0> = 011 CM<2:0> = 110 Two Common Reference Comparators Two Common Reference Comparators with Outputs D VIN- - A CIS=0 RA0/AN0 Off RA0/AN0 VIN- - C1 RA3/AN3 D VIN+ + (Read as '0') RA3/AN3 A CVISIN=+1 + C1 C1OUT A VIN- - RA1/AN1 A VIN+ + C2 C2OUT RA1/AN1 A VIN- - C2 C2OUT RA2/AN2 A VIN+ + RA2/AN2 CM<2:0> = 101 CM<2:0> = 001 One Independent Comparator Three Inputs Multiplexed to Two Comparators A = Analog Input, Port Reads Zeros Always D = Digital Input CIS = CMCON<3>, Comparator Input Switch DS30235J-page 38  2003 Microchip Technology Inc.

PIC16C62X The code example in Example7-1 depicts the steps 7.3 Comparator Reference required to configure the comparator module. RA3 and An external or internal reference signal may be used RA4 are configured as digital output. RA0 and RA1 are depending on the comparator Operating mode. The configured as the V- inputs and RA2 as the V+ input to analog signal that is present at VIN- is compared to the both comparators. signal at VIN+, and the digital output of the comparator EXAMPLE 7-1: INITIALIZING is adjusted accordingly (Figure7-2). COMPARATOR MODULE FIGURE 7-2: SINGLE COMPARATOR MOVLW 0x03 ;Init comparator mode MOVWF CMCON ;CM<2:0> = 011 CLRF PORTA ;Init PORTA VIN+ + BSF STATUS,RP0 ;Select Bank1 Output VIN- – MOVLW 0x07 ;Initialize data direction MOVWF TRISA ;Set RA<2:0> as inputs ;RA<4:3> as outputs ;TRISA<7:5> always read ‘0’ BCF STATUS,RP0 ;Select Bank 0 CALL DELAY 10 ;10µs delay VVININ-– MOVF CMCON,F ;Read CMCON to end change condition VVININ++ BCF PIR1,CMIF ;Clear pending interrupts BSF STATUS,RP0 ;Select Bank 1 BSF PIE1,CMIE ;Enable comparator interrupts BCF STATUS,RP0 ;Select Bank 0 Ouuttppuutt BSF INTCON,PEIE ;Enable peripheral interrupts BSF INTCON,GIE ;Global interrupt enable 7.2 Comparator Operation 7.3.1 EXTERNAL REFERENCE SIGNAL A single comparator is shown in Figure7-2 along with When external voltage references are used, the the relationship between the analog input levels and comparator module can be configured to have the the digital output. When the analog input at VIN+ is less comparators operate from the same or different than the analog input VIN-, the output of the comparator reference sources. However, threshold detector is a digital low level. When the analog input at VIN+ is applications may require the same reference. The greater than the analog input VIN-, the output of the reference signal must be between VSS and VDD, and comparator is a digital high level. The shaded areas of can be applied to either pin of the comparator(s). the output of the comparator in Figure7-2 represent 7.3.2 INTERNAL REFERENCE SIGNAL the uncertainty due to input offsets and response time. The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 10, Instruction Sets, contains a detailed description of the Voltage Reference Module that provides this signal. The internal reference signal is used when the comparators are in mode CM<2:0>=010 (Figure7-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.  2003 Microchip Technology Inc. DS30235J-page 39

PIC16C62X 7.4 Comparator Response Time 7.5 Comparator Outputs Response time is the minimum time, after selecting a The comparator outputs are read through the CMCON new reference voltage or input source, before the register. These bits are read only. The comparator comparator output has a valid level. If the internal outputs may also be directly output to the RA3 and RA4 reference is changed, the maximum delay of the I/O pins. When the CM<2:0> = 110, multiplexors in the internal voltage reference must be considered when output path of the RA3 and RA4 pins will switch and the using the comparator outputs. Otherwise the maximum output of each pin will be the unsynchronized output of delay of the comparators should be used (Table12-2). the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure7-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RA3 and RA4 pins while in this mode. Note 1: When reading the PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. FIGURE 7-3: COMPARATOR OUTPUT BLOCK DIAGRAM PORT PINS MULTIPLEX + - To RA3 or RA4 Pin Bus Q D Data RD CMCON EN Set CMIF Q D Bit FROM OTHER EN COMPARATOR CL RD CMCON NRESET DS30235J-page 40  2003 Microchip Technology Inc.

PIC16C62X 7.6 Comparator Interrupts wake up the device from SLEEP mode when enabled. While the comparator is powered-up, higher SLEEP The comparator interrupt flag is set whenever there is currents than shown in the power-down current a change in the output value of either comparator. specification will occur. Each comparator that is Software will need to maintain information about the operational will consume additional current as shown in status of the output bits, as read from CMCON<7:6>, to the comparator specifications. To minimize power determine the actual change that has occurred. The consumption while in SLEEP mode, turn off the CMIF bit, PIR1<6>, is the comparator interrupt flag. comparators, CM<2:0>=111, before entering SLEEP. The CMIF bit must be RESET by clearing ‘0’. Since it is If the device wakes up from SLEEP, the contents of the also possible to write a '1' to this register, a simulated CMCON register are not affected. interrupt may be initiated. 7.8 Effects of a RESET The CMIE bit (PIE1<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In A device RESET forces the CMCON register to its addition, the GIE bit must also be set. If any of these RESET state. This forces the comparator module to be bits are clear, the interrupt is not enabled, though the in the comparator RESET mode, CM<2:0>=000. This CMIF bit will still be set if an interrupt condition occurs. ensures that all potential inputs are analog inputs. Note: If a change in the CMCON register Device current is minimized when analog inputs are (C1OUT or C2OUT) should occur when a present at RESET time. The comparators will be read operation is being executed (start of powered-down during the RESET interval. the Q2 cycle), then the CMIF (PIR1<6>) 7.9 Analog Input Connection interrupt flag may not get set. Considerations The user, in the interrupt service routine, can clear the interrupt in the following manner: A simplified circuit for an analog input is shown in a) Any read or write of CMCON. This will end the Figure7-4. Since the analog pins are connected to a mismatch condition. digital output, they have reverse biased diodes to VDD b) Clear flag bit CMIF. and VSS. The analog input therefore, must be between VSS and VDD. If the input voltage deviates from this A mismatch condition will continue to set flag bit CMIF. range by more than 0.6V in either direction, one of the Reading CMCON will end the mismatch condition and diodes is forward biased and a latchup may occur. A allow flag bit CMIF to be cleared. maximum source impedance of 10kΩ is recommended for the analog sources. Any external 7.7 Comparator Operation During component connected to an analog input pin, such as SLEEP a capacitor or a Zener diode, should have very little leakage current. When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will FIGURE 7-4: ANALOG INPUT MODEL VDD VT = 0.6V RS < 10K RIC AIN CPIN ILEAKAGE VA 5 pF VT = 0.6V ±500 nA VSS Legend CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage  2003 Microchip Technology Inc. DS30235J-page 41

PIC16C62X TABLE 7-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR RESETS 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 8Ch PIE1 — CMIE — — — — — — -0-- ---- -0-- ---- 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as "0" DS30235J-page 42  2003 Microchip Technology Inc.

PIC16C62X 8.0 VOLTAGE REFERENCE 8.1 Configuring the Voltage Reference MODULE The Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate The Voltage Reference is a 16-tap resistor ladder the output of the Voltage Reference are as follows: network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges if VRR = 1: VREF = (VR<3:0>/24) x VDD of VREF values and has a power-down function to if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD conserve power when the reference is not being used. The setting time of the Voltage Reference must be The VRCON register controls the operation of the considered when changing the VREF output (Table12-1). reference as shown in Register8-1. The block diagram Example8-1 shows an example of how to configure the is given in Figure8-1. Voltage Reference for an output voltage of 1.25V with VDD = 5.0V. REGISTER 8-1: VRCON REGISTER(ADDRESS 9Fh) R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 bit 7 VREN: VREF Enable 1 = VREF circuit powered on 0 = VREF circuit powered down, no IDD drain bit 6 VROE: VREF Output Enable 1 = VREF is output on RA2 pin 0 = VREF is disconnected from RA2 pin bit 5 VRR: VREF Range selection 1 = Low Range 0 = High Range bit 4 Unimplemented: Read as '0' bit 3-0 VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15 when VRR = 1: VREF = (VR<3:0>/ 24) * VDD when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown FIGURE 8-1: VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages VREN 8R R R R R 8R VRR VR3 VREF 16-1 Analog Mux (From VRCON<3:0>) VR0 Note: R is defined in Table12-2.  2003 Microchip Technology Inc. DS30235J-page 43

PIC16C62X EXAMPLE 8-1: VOLTAGE REFERENCE 8.4 Effects of a RESET CONFIGURATION A device RESET disables the voltage reference by MOVLW 0x02 ; 4 Inputs Muxed clearing bit VREN (VRCON<7>). This reset also disconnects the reference from the RA2 pin by clearing MOVWF CMCON ; to 2 comps. bit VROE (VRCON<6>) and selects the high voltage BSF STATUS,RP0 ; go to Bank 1 range by clearing bit VRR (VRCON<5>). The VREF MOVLW 0x0F ; RA3-RA0 are value select bits, VRCON<3:0>, are also cleared. MOVWF TRISA ; inputs 8.5 Connection Considerations MOVLW 0xA6 ; enable VREF MOVWF VRCON ; low range The voltage reference module operates independently ; set VR<3:0>=6 of the comparator module. The output of the reference BCF STATUS,RP0 ; go to Bank 0 generator may be connected to the RA2 pin if the CALL DELAY10 ; 10µs delay TRISA<2> bit is set and the VROE bit, VRCON<6>, is set. Enabling the voltage reference output onto the 8.2 Voltage Reference Accuracy/Error RA2 pin with an input signal present will increase current consumption. Connecting RA2 as a digital The full range of VSS to VDD cannot be realized due to the output with VREF enabled will also increase current construction of the module. The transistors on the top consumption. and bottom of the resistor ladder network (Figure8-1) The RA2 pin can be used as a simple D/A output with keep VREF from approaching VSS or VDD. The voltage limited drive capability. Due to the limited drive reference is VDD derived and therefore, the VREF output capability, a buffer must be used in conjunction with the changes with fluctuations in VDD. The tested absolute voltage reference output for external connections to accuracy of the voltage reference can be found in VREF. Figure8-2 shows an example buffering Table12-2. technique. 8.3 Operation During SLEEP When the device wakes up from SLEEP through an interrupt or a Watchdog Timer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the voltage reference should be disabled. FIGURE 8-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE (1) R RA VREF (cid:127) + Module (cid:127) VREF Output – Voltage Reference Output Impedance Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>. TABLE 8-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Value On Value On Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR RESETS 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 Note: - = Unimplemented, read as "0" DS30235J-page 44  2003 Microchip Technology Inc.

PIC16C62X 9.0 SPECIAL FEATURES OF THE The PIC16C62X devices have a Watchdog Timer CPU which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two Special circuits to deal with the needs of real-time timers that offer necessary delays on power-up. One is applications are what sets a microcontroller apart from the Oscillator Start-up Timer (OST), intended to keep other processors. The PIC16C62X family has a host of the chip in RESET until the crystal oscillator is stable. such features intended to maximize system reliability, The other is the Power-up Timer (PWRT), which minimize cost through elimination of external compo- provides a fixed delay of 72ms (nominal) on power-up nents, provide power saving operating modes and offer only, designed to keep the part in RESET while the code protection. power supply stabilizes. There is also circuitry to RESET the device if a brown-out occurs, which pro- These are: vides at least a 72ms RESET. With these three 1. OSC selection functions on-chip, most applications need no external 2. RESET RESET circuitry. Power-on Reset (POR) The SLEEP mode is designed to offer a very low Power-up Timer (PWRT) current Power-down mode. The user can wake-up from Oscillator Start-up Timer (OST) SLEEP through external RESET, Watchdog Timer Brown-out Reset (BOR) wake-up or through an interrupt. Several oscillator 3. Interrupts options are also made available to allow the part to fit 4. Watchdog Timer (WDT) the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of 5. SLEEP configuration bits are used to select various options. 6. Code protection 7. ID Locations 8. In-Circuit Serial Programming™  2003 Microchip Technology Inc. DS30235J-page 45

PIC16C62X 9.1 Configuration Bits The user will note that address 2007h is beyond the user program memory space. In fact, it belongs The configuration bits can be programmed (read as '0') to the special test/configuration memory space or left unprogrammed (read as '1') to select various (2000h –3FFFh), which can be accessed only during device configurations. These bits are mapped in programming. program memory location 2007h. REGISTER 9-1: CONFIGURATION WORD (ADDRESS 2007h) CP1 CP0 (2) CP1 CP0 (2) CP1 CP0 (2) BODEN CP1 CP0 (2) PWRTE WDTE F0SC1 F0SC0 bit 13 bit 0 (2) bit 13-8, CP<1:0>: Code protection bit pairs 5-4: Code protection for 2K program memory 11 = Program memory code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected Code protection for 1K program memory 11 = Program memory code protection off 10 = Program memory code protection off 01 = 0200h-03FFh code protected 00 = 0000h-03FFh code protected Code protection for 0.5K program memory 11 = Program memory code protection off 10 = Program memory code protection off 01 = Program memory code protection off 00 = 0000h-01FFh code protected bit 7 Unimplemented: Read as ‘0’ (1) bit 6 BODEN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled (1, 3) bit 3 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Detect Reset is enabled. 2: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed. 3: Unprogrammed parts default the Power-up Timer disabled. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown DS30235J-page 46  2003 Microchip Technology Inc.

PIC16C62X 9.2 Oscillator Configurations TABLE 9-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS 9.2.1 OSCILLATOR TYPES Ranges Characterized: The PIC16C62X devices can be operated in four Mode Freq OSC1(C1) OSC2(C2) different oscillator options. The user can program two configuration bits (FOSC1 and FOSC0) to select one of XT 455 kHz 22 - 100 pF 22 - 100 pF these four modes: 2.0 MHz 15 - 68 pF 15 - 68 pF 4.0 MHz 15 - 68 pF 15 - 68 pF (cid:127) LP Low Power Crystal HS 8.0 MHz 10 - 68 pF 10 - 68 pF (cid:127) XT Crystal/Resonator 16.0 MHz 10 - 22 pF 10 - 22 pF (cid:127) HS High Speed Crystal/Resonator Higher capacitance increases the stability of the oscil- (cid:127) RC Resistor/Capacitor lator but also increases the start-up time. These values are for design guidance only. Since each 9.2.2 CRYSTAL OSCILLATOR / CERAMIC resonator has its own characteristics, the user RESONATORS should consult the resonator manufacturer for appropriate values of external components. In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish TABLE 9-2: CAPACITOR SELECTION FOR oscillation (Figure9-1). The PIC16C62X oscillator CRYSTAL OSCILLATOR design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the Mode Freq OSC1(C1) OSC2(C2) crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock 32 kHz 68 - 100 pF 68 - 100 pF LP source to drive the OSC1 pin (Figure9-2). 200 kHz 15 - 30 pF 15 - 30 pF 100 kHz 68 - 150 pF 150 - 200 pF FIGURE 9-1: CRYSTAL OPERATION XT 2 MHz 15 - 30 pF 15 - 30 pF (OR CERAMIC 4 MHz 15 - 30 pF 15 - 30 pF RESONATOR) (HS, XT OR 8 MHz 15 - 30 pF 15 - 30 pF LP OSC HS 10 MHz 15 - 30 pF 15 - 30 pF CONFIGURATION) 20 MHz 15 - 30 pF 15 - 30 pF OSC1 Higher capacitance increases the stability of the oscillator but also increases the start-up time. C1 To internal logic These values are for design guidance only. Rs may be required in HS mode as well as XT mode to XTAL SLEEP RF avoid overdriving crystals with low drive level OSC2 specification. Since each crystal has its own RS characteristics, the user should consult the crystal C2 See Note PIC16C62X manufacturer for appropriate values of external components. See Table9-1 and Table9-2 for recommended values of C1 and C2. Note: A series resistor may be required for AT strip cut crystals. FIGURE 9-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) clock from OSC1 ext. system PIC16C62X Open OSC2  2003 Microchip Technology Inc. DS30235J-page 47

PIC16C62X 9.2.3 EXTERNAL CRYSTAL OSCILLATOR 9.2.4 RC OSCILLATOR CIRCUIT For timing insensitive applications the “RC” device Either a prepackaged oscillator can be used or a simple option offers additional cost savings. The RC oscillator oscillator circuit with TTL gates can be built. frequency is a function of the supply voltage, the Prepackaged oscillators provide a wide operating resistor (REXT) and capacitor (CEXT) values, and the range and better stability. A well-designed crystal operating temperature. In addition to this, the oscillator oscillator will provide good performance with TTL frequency will vary from unit to unit due to normal gates. Two types of crystal oscillator circuits can be process parameter variation. Furthermore, the used; one with series resonance or one with parallel difference in lead frame capacitance between package resonance. types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to Figure9-3 shows implementation of a parallel resonant take into account variation due to tolerance of external oscillator circuit. The circuit is designed to use the R and C components used. Figure9-5 shows how the fundamental frequency of the crystal. The 74AS04 R/C combination is connected to the PIC16C62X. For inverter performs the 180° phase shift that a parallel REXT values below 2.2 kΩ, the oscillator operation may oscillator requires. The 4.7kΩ resistor provides the become unstable or stop completely. For very high negative feedback for stability. The 10kΩ REXT values (e.g., 1 MΩ), the oscillator becomes potentiometers bias the 74AS04 in the linear region. sensitive to noise, humidity and leakage. Thus, we This could be used for external oscillator designs. recommend to keep REXT between 3 kΩ and 100 kΩ. FIGURE 9-3: EXTERNAL PARALLEL Although the oscillator will operate with no external RESONANT CRYSTAL capacitor (CEXT = 0 pF), we recommend using values OSCILLATOR CIRCUIT above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency +5V can vary dramatically due to changes in external To Other capacitances, such as PCB trace capacitance or Devices 10k package lead frame capacitance. 4.7k 74AS04 PIC16C62X See Section13.0 for RC frequency variation from part 74AS04 CLKIN to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller 10k C (since variation of input capacitance will affect RC XTAL frequency more). See Section13.0 for variation of oscillator frequency 10k due to VDD for given REXT/CEXT values, as well as frequency variation due to operating temperature for 20 pF 20 pF given R, C and VDD values. The oscillator frequency, divided by 4, is available on Figure9-4 shows a series resonant oscillator circuit. the OSC2/CLKOUT pin, and can be used for test This circuit is also designed to use the fundamental purposes or to synchronize other logic (Figure3-2 for frequency of the crystal. The inverter performs a 180° waveform). phase shift in a series resonant oscillator circuit. The 330kΩ resistors provide the negative feedback to bias FIGURE 9-5: RC OSCILLATOR MODE the inverters in their linear region. FIGURE 9-4: EXTERNAL SERIES VDD RESONANT CRYSTAL PIC16C62X OSCILLATOR CIRCUIT REXT OSC1 Internal Clock To Other CEXT 330 kΩ 330 kΩ Devices 74AS04 74AS04 74AS04 PIC16C62X VDD CLKIN FOSC/4 OSC2/CLKOUT 0.1 µF XTAL DS30235J-page 48  2003 Microchip Technology Inc.

PIC16C62X 9.3 RESET MCLR Reset, WDT Reset and MCLR Reset during SLEEP. They are not affected by a WDT wake-up, The PIC16C62X differentiates between various kinds since this is viewed as the resumption of normal of RESET: operation. TO and PD bits are set or cleared differently a) Power-on Reset (POR) in different RESET situations as indicated in Table9-2. These bits are used in software to determine the nature b) MCLR Reset during normal operation of the RESET. See Table9-5 for a full description of c) MCLR Reset during SLEEP RESET states of all registers. d) WDT Reset (normal operation) A simplified block diagram of the on-chip RESET circuit e) WDT wake-up (SLEEP) is shown in Figure9-6. f) Brown-out Reset (BOR) The MCLR Reset path has a noise filter to detect and Some registers are not affected in any RESET ignore small pulses. See Table12-5 for pulse width condition Their status is unknown on POR and specification. unchanged in any other RESET. Most other registers are reset to a “RESET state” on Power-on Reset, FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External RESET MCLR/ VPP Pin SLEEP WDT WDT Module Time-out Reset VDD rise detect Power-on Reset VDD Brown-out Reset BODEN S Q OST/PWRT OST Chip_Reset 10-bit Ripple-counter R Q OSC1/ CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter RC OSC Enable PWRT See Table9-1 for time-out situations. Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.  2003 Microchip Technology Inc. DS30235J-page 49

PIC16C62X 9.4 Power-on Reset (POR), Power-up The Power-up Time delay will vary from chip-to-chip Timer (PWRT), Oscillator Start-up and due to VDD, temperature and process variation. See DC parameters for details. Timer (OST) and Brown-out Reset (BOR) 9.4.3 OSCILLATOR START-UP TIMER (OST) 9.4.1 POWER-ON RESET (POR) The Oscillator Start-Up Timer (OST) provides a 1024 The on-chip POR circuit holds the chip in RESET until oscillator cycle (from OSC1 input) delay after the VDD has reached a high enough level for proper PWRT delay is over. This ensures that the crystal operation. To take advantage of the POR, just tie the oscillator or resonator has started and stabilized. MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create The OST time-out is invoked only for XT, LP and HS Power-on Reset. A maximum rise time for VDD is modes and only on Power-on Reset or wake-up from SLEEP. required. See Electrical Specifications for details. The POR circuit does not produce an internal RESET 9.4.4 BROWN-OUT RESET (BOR) when VDD declines. The PIC16C62X members have on-chip Brown-out When the device starts normal operation (exits the Reset circuitry. A configuration bit, BODEN, can RESET condition), device operating parameters (volt- disable (if clear/programmed) or enable (if set) the age, frequency, temperature, etc.) must be met to Brown-out Reset circuitry. If VDD falls below 4.0V refer ensure operation. If these conditions are not met, the to VBOR parameter D005 (VBOR) for greater than device must be held in RESET until the operating parameter (TBOR) in Table12-5. The brown-out situa- conditions are met. tion will RESET the chip. A RESET won’t occur if VDD For additional information, refer to Application Note falls below 4.0V for less than parameter (TBOR). AN607, “Power-up Trouble Shooting”. On any RESET (Power-on, Brown-out, Watchdog, etc.) the chip will remain in RESET until VDD rises above 9.4.2 POWER-UP TIMER (PWRT) BVDD. The Power-up Timer will now be invoked and will The Power-up Timer provides a fixed 72ms (nominal) keep the chip in RESET an additional 72ms. time-out on power-up only, from POR or Brown-out If VDD drops below BVDD while the Power-up Timer is Reset. The Power-up Timer operates on an internal RC running, the chip will go back into a Brown-out Reset oscillator. The chip is kept in RESET as long as PWRT and the Power-up Timer will be re-initialized. Once VDD is active. The PWRT delay allows the VDD to rise to an rises above BVDD, the Power-Up Timer will execute a acceptable level. A configuration bit, PWRTE can 72ms RESET. The Power-up Timer should always be disable (if set) or enable (if cleared or programmed) the enabled when Brown-out Reset is enabled. Figure9-7 Power-up Timer. The Power-up Timer should always shows typical Brown-out situations. be enabled when Brown-out Reset is enabled. FIGURE 9-7: BROWN-OUT SITUATIONS VDD BVDD INTERNAL 72 ms RESET VDD BVDD INTERNAL <72 ms 72 ms RESET VDD BVDD INTERNAL 72 ms RESET DS30235J-page 50  2003 Microchip Technology Inc.

PIC16C62X 9.4.5 TIME-OUT SEQUENCE 9.4.6 POWER CONTROL (PCON)/ STATUS REGISTER On power-up the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired. Then The power control/STATUS register, PCON (address OST is activated. The total time-out will vary based on 8Eh), has two bits. oscillator configuration and PWRTE bit status. For Bit0 is BOR (Brown-out). BOR is unknown on Power- example, in RC mode with PWRTE bit erased (PWRT on Reset. It must then be set by the user and checked disabled), there will be no time-out at all. Figure9-8, on subsequent RESETS to see if BOR = 0, indicating Figure9-9 and Figure9-10 depict time-out sequences. that a brown-out has occurred. The BOR STATUS bit is Since the time-outs occur from the POR pulse, if MCLR a don’t care and is not necessarily predictable if the is kept low long enough, the time-outs will expire. Then brown-out circuit is disabled (by setting BODEN bit = 0 bringing MCLR high will begin execution immediately in the Configuration word). (see Figure9-9). This is useful for testing purposes or Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on to synchronize more than one PIC16C62X device Reset and unaffected otherwise. The user must write a operating in parallel. ‘1’ to this bit following a Power-on Reset. On a Table9-4 shows the RESET conditions for some subsequent RESET, if POR is ‘0’, it will indicate that a special registers, while Table9-5 shows the RESET Power-on Reset must have occurred (VDD may have conditions for all the registers. gone too low). TABLE 9-1: TIME-OUT IN VARIOUS SITUATIONS Power-up Wake-up Oscillator Configuration Brown-out Reset from SLEEP PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC RC 72 ms — 72 ms — TABLE 9-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 X 1 1 Power-on Reset 0 X 0 X Illegal, TO is set on POR 0 X X 0 Illegal, PD is set on POR 1 0 X X Brown-out Reset 1 1 0 u WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP Legend: u = unchanged, x = unknown TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR Reset (1) RESETS 83h STATUS TO PD 0001 1xxx 000q quuu 8Eh PCON — — — — — — POR BOR ---- --0x ---- --uq Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation.  2003 Microchip Technology Inc. DS30235J-page 51

PIC16C62X TABLE 9-4: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 000x xuuu ---- --u0 (1) Interrupt Wake-up from SLEEP PC + 1 uuu1 0uuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1. TABLE 9-5: INITIALIZATION CONDITION FOR REGISTERS (cid:127) MCLR Reset during (cid:127) Wake-up from SLEEP normal operation through interrupt (cid:127) MCLR Reset during (cid:127) Wake-up from SLEEP SLEEP through WDT time-out (cid:127) WDT Reset Register Address Power-on Reset (cid:127) Brown-out Reset (1) W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h — — — TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000 0000 0000 0000 PC + 1(3) STATUS 03h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu PORTA 05h ---x xxxx ---u uuuu ---u uuuu PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu CMCON 1Fh 00-- 0000 00-- 0000 uu-- uuuu PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh 0000 000x 0000 000u uuuu uqqq(2) PIR1 0Ch -0-- ---- -0-- ---- -q-- ----(2,5) OPTION 81h 1111 1111 1111 1111 uuuu uuuu TRISA 85h ---1 1111 ---1 1111 ---u uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuu PIE1 8Ch -0-- ---- -0-- ---- -u-- ---- PCON 8Eh ---- --0x ---- --uq(1,6) ---- --uu VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table9-4 for RESET value for specific condition. 5: If wake-up was due to comparator input changing, then bit 6 = 1. All other interrupts generating a wake-up will cause bit 6 = u. 6: If RESET was due to brown-out, then bit 0 = 0. All other RESETS will cause bit 0 = u. DS30235J-page 52  2003 Microchip Technology Inc.

PIC16C62X FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ): CASE 1 DD VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ): CASE 2 DD VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V ) DD VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2003 Microchip Technology Inc. DS30235J-page 53

PIC16C62X FIGURE 9-11: EXTERNAL POWER-ON FIGURE 9-13: EXTERNAL BROWN-OUT RESET CIRCUIT (FOR PROTECTION CIRCUIT 2 SLOW V POWER-UP) DD VDD VDD VDD VDD R1 Q1 MCLR R D R2 R1 40k PIC16C62X MCLR PIC16C62X C Note 1: External Power-on Reset circuit is Note 1: This brown-out circuit is less expen- required only if VDD power-up slope is sive, albeit less accurate. Transistor too slow. The diode D helps discharge Q1 turns off when VDD is below a the capacitor quickly when VDD powers certain level such that: down. R1 2: < 40 kΩ is recommended to make sure VDD x R1 + R2 = 0.7V that voltage drop across R does not violate the device’s electrical specifica- 2: Internal Brown-out Reset should be tion. disabled when using this circuit. 3: R1 = 100Ω to 1 kΩ will limit any current 3: Resistors should be adjusted for the flowing into MCLR from external capaci- characteristics of the transistor. tor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Over- FIGURE 9-14: EXTERNAL BROWN-OUT stress (EOS). PROTECTION CIRCUIT 3 VDD FIGURE 9-12: EXTERNAL BROWN-OUT MCP809 PROTECTION CIRCUIT 1 bypass VDD capacitor Vss VDD VDD VDD RST 33k MCLR PIC16C62X 10k MCLR 40k PIC16C62X This brown-out protection circuit employs Microchip Technology’s MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open Note 1: This circuit will activate RESET when collector outputs with both high and low active VDD goes below (Vz + 0.7V) where RESET pins. There are 7 different trip point Vz=Zener voltage. selections to accommodate 5V and 3V systems. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit. DS30235J-page 54  2003 Microchip Technology Inc.

PIC16C62X 9.5 Interrupts Once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt The PIC16C62X has 4 sources of interrupt: flag bits. The interrupt flag bit(s) must be cleared in (cid:127) External interrupt RB0/INT software before re-enabling interrupts to avoid RB0/ INT recursive interrupts. (cid:127) TMR0 overflow interrupt (cid:127) PORTB change interrupts (pins RB<7:4>) For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be (cid:127) Comparator interrupt three or four instruction cycles. The exact latency The interrupt control register (INTCON) records depends when the interrupt event occurs (Figure9-16). individual interrupt requests in flag bits. It also has The latency is the same for one or two cycle individual and global interrupt enable bits. instructions. Once in the interrupt service routine, the A global interrupt enable bit, GIE (INTCON<7>) source(s) of the interrupt can be determined by polling enables (if set) all un-masked interrupts or disables (if the interrupt flag bits. The interrupt flag bit(s) must be cleared) all interrupts. Individual interrupts can be cleared in software before re-enabling interrupts to disabled through their corresponding enable bits in avoid multiple interrupt requests. INTCON register. GIE is cleared on RESET. Note 1: Individual interrupt flag bits are set The “return from interrupt” instruction, RETFIE, exits regardless of the status of their interrupt routine, as well as sets the GIE bit, which re- corresponding mask bit or the GIE bit. enable RB0/INT interrupts. 2: When an instruction that clears the GIE The INT pin interrupt, the RB port change interrupt and bit is executed, any interrupts that were the TMR0 overflow interrupt flags are contained in the pending for execution in the next cycle INTCON register. are ignored. The CPU will execute a NOP The peripheral interrupt flag is contained in the special in the cycle immediately following the register PIR1. The corresponding interrupt enable bit is instruction which clears the GIE bit. The contained in special registers PIE1. interrupts which were ignored are still pending to be serviced when the GIE bit When an interrupt is responded to, the GIE is cleared is set again. to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. FIGURE 9-15: INTERRUPT LOGIC Wake-up T0IF (If in SLEEP mode) T0IE INTF INTE Interrupt to CPU RBIF RBIE CMIF CMIE PEIE GIE  2003 Microchip Technology Inc. DS30235J-page 55

PIC16C62X 9.5.1 RB0/INT INTERRUPT 9.5.2 TMR0 INTERRUPT External interrupt on RB0/INT pin is edge triggered, An overflow (FFh → 00h) in the TMR0 register will either rising if INTEDG bit (OPTION<6>) is set, or fall- set the T0IF (INTCON<2>) bit. The interrupt can ing, if INTEDG bit is clear. When a valid edge appears be enabled/disabled by setting/clearing T0IE on the RB0/INT pin, the INTF bit (INTCON<1>) is set. (INTCON<5>) bit. For operation of the Timer0 module, This interrupt can be disabled by clearing the INTE see Section6.0. control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re- 9.5.3 PORTB INTERRUPT enabling this interrupt. The RB0/INT interrupt can An input change on PORTB <7:4> sets the RBIF wake-up the processor from SLEEP, if the INTE bit was (INTCON<0>) bit. The interrupt can be enabled/dis- set prior to going into SLEEP. The status of the GIE bit abled by setting/clearing the RBIE (INTCON<4>) bit. decides whether or not the processor branches to the For operation of PORTB (Section5.2). interrupt vector following wake-up. See Section9.8 for details on SLEEP and Figure9-18 for timing of wake- Note: If a change on the I/O pin should occur up from SLEEP through RB0/INT interrupt. when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. 9.5.4 COMPARATOR INTERRUPT See Section7.6 for complete description of comparator interrupts. FIGURE 9-16: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag 5 Interrupt Latency 2 (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 PC+1 0004h 0005h Instruction fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h) Instruction Inst (PC-1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. DS30235J-page 56  2003 Microchip Technology Inc.

PIC16C62X TABLE 9-6: SUMMARY OF INTERRUPT REGISTERS Value on all Value on POR Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other Reset RESETS(1) 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 8Ch PIE1 — CMIE — — — — — — -0-- ---- -0-- ---- Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation. 9.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W register and STATUS register). This will have to be implemented in software. Example9-3 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x20 in Bank 0 and it must also be defined at 0xA0 in Bank 1). The user register, STATUS_TEMP, must be defined in Bank 0. The Example9-3: (cid:127) Stores the W register (cid:127) Stores the STATUS register in Bank 0 (cid:127) Executes the ISR code (cid:127) Restores the STATUS (and bank select bit register) (cid:127) Restores the W register EXAMPLE 9-3: SAVING THE STATUS AND W REGISTERS IN RAM MOVWF W_TEMP ;copy W to temp register, ;could be in either bank SWAPF STATUS,W ;swap status to be saved into W BCF STATUS,RP0 ;change to bank 0 regardless ;of current bank MOVWF STATUS_TEMP ;save status to bank 0 ;register : : (ISR) : SWAPF STATUS_TEMP, ;swap STATUS_TEMP register W ;into W, sets bank to origi- nal ;state MOVWF STATUS ;move W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W  2003 Microchip Technology Inc. DS30235J-page 57

PIC16C62X 9.7 Watchdog Timer (WDT) DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be The Watchdog Timer is a free running on-chip RC oscil- assigned to the WDT under software control by writing lator which does not require any external components. to the OPTION register. Thus, time-out periods up to This RC oscillator is separate from the RC oscillator of 2.3 seconds can be realized. the CLKIN pin. That means that the WDT will run, even The CLRWDT and SLEEP instructions clear the WDT if the clock on the OSC1 and OSC2 pins of the device and the postscaler, if assigned to the WDT, and prevent has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT it from timing out and generating a device RESET. time-out generates a device RESET. If the device is in The TO bit in the STATUS register will be cleared upon SLEEP mode, a WDT time-out causes the device to a Watchdog Timer time-out. wake-up and continue with normal operation. The WDT can be permanently disabled by programming the 9.7.2 WDT PROGRAMMING configuration bit WDTE as clear (Section9.1). CONSIDERATIONS 9.7.1 WDT PERIOD It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. The WDT has a nominal time-out period of 18 ms, (with WDT prescaler) it may take several seconds before a no prescaler). The time-out periods vary with tempera- WDT time-out occurs. ture, VDD and process variations from part to part (see FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure6-6) 0 M Postscaler Watchdog 1 U Timer 8 X 8 - to -1 MUX PS<2:0> PSA WDT Enable Bit To TMR0 (Figure6-6) 0 1 MUX PSA WDT Time-out Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. TABLE 9-7: SUMMARY OF WATCHDOG TIMER REGISTERS Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR Reset RESETS 2007h Config. bits — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 — — 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded cells are not used by the Watchdog Timer. _ Note: = Unimplemented location, read as “0” + = Reserved for future use DS30235J-page 58  2003 Microchip Technology Inc.

PIC16C62X 9.8 Power-Down Mode (SLEEP) The first event will cause a device RESET. The two latter events are considered a continuation of program The Power-down mode is entered by executing a execution. The TO and PD bits in the STATUS register SLEEP instruction. can be used to determine the cause of device RESET. If enabled, the Watchdog Timer will be cleared but PD bit, which is set on power-up, is cleared when keeps running, the PD bit in the STATUS register is SLEEP is invoked. TO bit is cleared if WDT wake-up cleared, the TO bit is set, and the oscillator driver is occurred. turned off. The I/O ports maintain the status they had, When the SLEEP instruction is being executed, the before SLEEP was executed (driving high, low, or hi- next instruction (PC + 1) is pre-fetched. For the device impedance). to wake-up through an interrupt event, the correspond- For lowest current consumption in this mode, all I/O ing interrupt enable bit must be set (enabled). Wake-up pins should be either at VDD or VSS with no external is regardless of the state of the GIE bit. If the GIE bit is circuitry drawing current from the I/O pin and the clear (disabled), the device continues execution at the comparators and VREF should be disabled. I/O pins that instruction after the SLEEP instruction. If the GIE bit is are hi-impedance inputs should be pulled high or low set (enabled), the device executes the instruction after externally to avoid switching currents caused by float- the SLEEP instruction and then branches to the inter- ing inputs. The T0CKI input should also be at VDD or rupt address (0004h). In cases where the execution of VSS for lowest current consumption. The contribution the instruction following SLEEP is not desirable, the from on chip pull-ups on PORTB should be considered. user should have an NOP after the SLEEP instruction. The MCLR pin must be at a logic high level (VIHMC). Note: If the global interrupts are disabled (GIE is cleared), but any interrupt source has both Note: It should be noted that a RESET generated its interrupt enable bit and the correspond- by a WDT time-out does not drive MCLR ing interrupt flag bits set, the device will pin low. immediately wake-up from SLEEP. The 9.8.1 WAKE-UP FROM SLEEP SLEEP instruction is completely executed. The WDT is cleared when the device wakes up from The device can wake-up from SLEEP through one of SLEEP, regardless of the source of wake-up. the following events: 1. External RESET input on MCLR pin 2. Watchdog Timer Wake-up (if WDT was enabled) 3. Interrupt from RB0/INT pin, RB Port change, or the Peripheral Interrupt (Comparator). FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) Tost(2) INT pin INTF flag Interrupt Latency (INTCON<1>) (Note 2) GIE bit Processor in (INTCON<7>) SLEEP INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Instruction Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) fetched Ienxsetcruuctetidon Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC Osc mode. 3: GIE = '1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these Osc modes, but shown here for timing reference.  2003 Microchip Technology Inc. DS30235J-page 59

PIC16C62X 9.9 Code Protection 9.11 In-Circuit Serial Programming™ If the code protection bit(s) have not been The PIC16C62X microcontrollers can be serially programmed, the on-chip program memory can be programmed while in the end application circuit. This is read out for verification purposes. simply done with two lines for clock and data and three other lines for power, ground and the programming Note: Microchip does not recommend code voltage. This allows customers to manufacture boards protecting windowed devices. with unprogrammed devices and then program the microcontroller just before shipping the product. This 9.10 ID Locations also allows the most recent firmware or a custom Four memory locations (2000h-2003h) are designated firmware to be programmed. as ID locations where the user can store checksum or The device is placed into a Program/Verify mode by other code identification numbers. These locations are holding the RB6 and RB7 pins low, while raising the not accessible during normal execution, but are MCLR (VPP) pin from VIL to VIHH (see programming readable and writable during Program/Verify. Only the specification). RB6 becomes the programming clock Least Significant 4 bits of the ID locations are used. and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After RESET, to place the device into Programming/ Verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X/9XX Programming Specification (DS30228). A typical In-Circuit Serial Programming connection is shown in Figure9-19. FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector PIC16C62X Signals +5V VDD 0V VSS VPP MCLR/VPP CLK RB6 Data I/O RB7 VDD To Normal Connections DS30235J-page 60  2003 Microchip Technology Inc.

PIC16C62X 10.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped into three basic categories: Each PIC16C62X instruction is a 14-bit word divided (cid:127) Byte-oriented operations into an OPCODE which specifies the instruction type and one or more operands which further specify the (cid:127) Bit-oriented operations operation of the instruction. The PIC16C62X instruc- (cid:127) Literal and control operations tion set summary in Table10-2 lists byte-oriented, bit- All instructions are executed within one single oriented, and literal and control operations. instruction cycle, unless a conditional test is true or the Table10-1 shows the opcode field descriptions. program counter is changed as a result of an For byte-oriented instructions, 'f' represents a file instruction. In this case, the execution takes two register designator and 'd' represents a destination instruction cycles with the second cycle executed as a designator. The file register designator specifies which NOP. One instruction cycle consists of four oscillator file register is to be used by the instruction. periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1µs. If a The destination designator specifies where the result of conditional test is true or the program counter is the operation is to be placed. If 'd' is zero, the result is changed as a result of an instruction, the instruction placed in the W register. If 'd' is one, the result is placed execution time is 2 µs. in the file register specified in the instruction. Table10-1 lists the instructions recognized by the For bit-oriented instructions, 'b' represents a bit field MPASM™ assembler. designator which selects the number of the bit affected by the operation, while 'f' represents the number of the Figure10-1 shows the three general formats that the file in which the bit is located. instructions can have. For literal and control operations, 'k' represents an Note: To maintain upward compatibility with eight or eleven bit constant or literal value. future PICmicro® products, do not use the OPTION and TRIS instructions. TABLE 10-1: OPCODE FIELD All examples use the following format to represent a DESCRIPTIONS hexadecimal number: Field Description 0xhh f Register file address (0x00 to 0x7F) where h signifies a hexadecimal digit. W Working register (accumulator) b Bit address within an 8-bit file register FIGURE 10-1: GENERAL FORMAT FOR k Literal field, constant data or label INSTRUCTIONS x Don't care location (= 0 or 1) Byte-oriented file register operations The assembler will generate code with x = 0. It is the 13 8 7 6 0 recommended form of use for compatibility with all OPCODE d f (FILE #) Microchip software tools. d Destination select; d = 0: store result in W, d = 0 for destination W d = 1: store result in file register f. d = 1 for destination f Default is d = 1 f = 7-bit file register address label Label name TOS Top of Stack Bit-oriented file register operations 13 10 9 7 6 0 PC Program Counter OPCODE b (BIT #) f (FILE #) PCLAT Program Counter High Latch H b = 3-bit bit address GIE Global Interrupt Enable bit f = 7-bit file register address WDT Watchdog Timer/Counter TO Time-out bit Literal and control operations PD Power-down bit General dest Destination either the W register or the specified regis- 13 8 7 0 ter file location OPCODE k (literal) [ ] Options ( ) Contents k = 8-bit immediate value → Assigned to < > Register bit field CALL and GOTO instructions only ∈ In the set of 13 11 10 0 italics User defined term (font is courier) OPCODE k (literal) k = 11-bit immediate value  2003 Microchip Technology Inc. DS30235J-page 61

PIC16C62X TABLE 10-2: PIC16C62X INSTRUCTION SET Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0000 0011 Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into Standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS30235J-page 62  2003 Microchip Technology Inc.

PIC16C62X 10.1 Instruction Descriptions ANDLW AND Literal with W ADDLW Add Literal and W Syntax: [ label ] ADDLW k Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W) Status Affected: Z Status Affected: C, DC, Z Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk Description: The contents of W register are Description: The contents of the W register are AND’ed with the eight bit literal 'k'. added to the eight bit literal 'k' and The result is placed in the W the result is placed in the W register. register. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example ANDLW 0x5F Example ADDLW 0x15 Before Instruction Before Instruction W = 0xA3 W = 0x10 After Instruction After Instruction W = 0x03 W = 0x25 ANDWF AND W with f ADDWF Add W and f Syntax: [ label ] ANDWF f,d Syntax: [ label ] ADDWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Operation: (W) + (f) → (dest) Status Affected: Z Status Affected: C, DC, Z Encoding: 00 0101 dfff ffff Encoding: 00 0111 dfff ffff Description: AND the W register with register Description: Add the contents of the W register 'f'. If 'd' is 0, the result is stored in with register 'f'. If 'd' is 0, the result the W register. If 'd' is 1, the result is stored in the W register. If 'd' is is stored back in register 'f'. 1, the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example ANDWF FSR, 1 Example ADDWF FSR, 0 Before Instruction W = 0x17 Before Instruction FSR= 0xC2 W = 0x17 After Instruction FSR= 0xC2 W = 0x17 After Instruction FSR= 0x02 W = 0xD9 FSR= 0xC2  2003 Microchip Technology Inc. DS30235J-page 63

PIC16C62X BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 0 ≤ b ≤ 7 Operation: 0 → (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff Description: Bit 'b' in register 'f' is cleared. Description: If bit 'b' in register 'f' is '0', then the next instruction is skipped. Words: 1 If bit 'b' is '0', then the next instruc- Cycles: 1 tion fetched during the current Example BCF FLAG_REG, 7 instruction execution is discarded, and a NOP is executed instead, Before Instruction making this a two-cycle instruction. FLAG_REG = 0xC7 Words: 1 After Instruction Cycles: 1(2) FLAG_REG = 0x47 Example HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CO TRUE (cid:127) BSF Bit Set f DE (cid:127) Syntax: [ label ] BSF f,b (cid:127) Operands: 0 ≤ f ≤ 127 Before Instruction 0 ≤ b ≤ 7 PC = address HERE Operation: 1 → (f<b>) After Instruction if FLAG<1> = 0, Status Affected: None PC = address TRUE Encoding: 01 01bb bfff ffff if FLAG<1>=1, PC = address FALSE Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Example BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A DS30235J-page 64  2003 Microchip Technology Inc.

PIC16C62X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 2047 0 ≤ b < 7 Operation: (PC)+ 1→ TOS, Operation: skip if (f<b>) = 1 k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding: 01 11bb bfff ffff Status Affected: None Encoding: 10 0kkk kkkk kkkk Description: If bit 'b' in register 'f' is '1', then the next instruction is skipped. Description: Call Subroutine. First, return If bit 'b' is '1', then the next instruc- address (PC+1) is pushed onto tion fetched during the current the stack. The eleven bit immedi- instruction execution, is discarded ate address is loaded into PC bits and a NOP is executed instead, <10:0>. The upper bits of the PC making this a two-cycle instruction. are loaded from PCLATH. CALL is a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Example HERE BTFSS FLAG,1 Cycles: 2 FALSE GOTO PROCESS_CO Example HERE CALL TRUE (cid:127) DE THER (cid:127) E (cid:127) Before Instruction Before Instruction PC = Address HERE PC = address HERE After Instruction After Instruction PC = Address THERE if FLAG<1> = 0, TOS= Address HERE+1 PC = address FALSE if FLAG<1> = 1, PC = address TRUE CLRF Clear f Syntax: [ label ] CLRF f Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1 → Z Status Affected: Z Encoding: 00 0001 1fff ffff Description: The contents of register 'f' are cleared and the Z bit is set. Words: 1 Cycles: 1 Example CLRF FLAG_REG Before Instruction FLAG_REG = 0x5A After Instruction FLAG_REG = 0x00 Z = 1  2003 Microchip Technology Inc. DS30235J-page 65

PIC16C62X CLRW Clear W COMF Complement f Syntax: [ label ] CLRW Syntax: [ label ] COMF f,d Operands: None Operands: 0 ≤ f ≤ 127 Operation: 00h → (W) d ∈ [0,1] 1 → Z Operation: (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 00 0001 0000 0011 Encoding: 00 1001 dfff ffff Description: W register is cleared. Zero bit (Z) Description: The contents of register 'f' are is set. complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the Words: 1 result is stored back in register 'f'. Cycles: 1 Words: 1 Example CLRW Cycles: 1 Before Instruction Example COMF REG1,0 W = 0x5A After Instruction Before Instruction W = 0x00 REG1 = 0x13 Z = 1 After Instruction REG1 = 0x13 W = 0xEC CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT DECF Decrement f Operands: None Syntax: [ label ] DECF f,d Operation: 00h → WDT 0 → WDT prescaler, Operands: 0 ≤ f ≤ 127 1 → TO d ∈ [0,1] 1 → PD Operation: (f) - 1 → (dest) Status Affected: TO, PD Status Affected: Z Encoding: 00 0000 0110 0100 Encoding: 00 0011 dfff ffff Description: CLRWDT instruction resets the Description: Decrement register 'f'. If 'd' is 0, Watchdog Timer. It also resets the the result is stored in the W prescaler of the WDT. STATUS register. If 'd' is 1, the result is bits TO and PD are set. stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example CLRWDT Example DECF CNT, 1 Before Instruction Before Instruction WDT counter = ? CNT = 0x01 After Instruction Z = 0 WDT counter = 0x00 After Instruction WDT prescaler= 0 CNT = 0x00 TO = 1 Z = 1 PD = 1 DS30235J-page 66  2003 Microchip Technology Inc.

PIC16C62X DECFSZ Decrement f, Skip if 0 INCF Increment f Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) - 1 → (dest); skip if result = 0 Operation: (f) + 1 → (dest) Status Affected: None Status Affected: Z Encoding: 00 1011 dfff ffff Encoding: 00 1010 dfff ffff Description: The contents of register 'f' are Description: The contents of register 'f' are decremented. If 'd' is 0, the result incremented. If 'd' is 0, the result is placed in the W register. If 'd' is is placed in the W register. If 'd' is 1, the result is placed back in 1, the result is placed back in register 'f'. register 'f'. If the result is 0, the next instruc- Words: 1 tion, which is already fetched, is discarded. A NOP is executed Cycles: 1 instead making it a two-cycle Example INCF CNT, 1 instruction. Before Instruction Words: 1 CNT = 0xFF Z = 0 Cycles: 1(2) After Instruction Example HERE DECFSZ CNT, 1 CNT = 0x00 GOTO LOOP Z = 1 CONTINUE (cid:127) (cid:127) (cid:127) Before Instruction PC = address HERE After Instruction CNT = CNT - 1 if CNT= 0, PC = address CONTINUE if CNT≠ 0, PC = address HERE+1 GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: None Encoding: 10 1kkk kkkk kkkk Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two- cycle instruction. Words: 1 Cycles: 2 Example GOTO THERE After Instruction PC = Address THERE  2003 Microchip Technology Inc. DS30235J-page 67

PIC16C62X INCFSZ Increment f, Skip if 0 IORWF Inclusive OR W with f Syntax: [ label ] INCFSZ f,d Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Operation: (W) .OR. (f) → (dest) Status Affected: None Status Affected: Z Encoding: 00 1111 dfff ffff Encoding: 00 0100 dfff ffff Description: The contents of register 'f' are Description: Inclusive OR the W register with incremented. If 'd' is 0 the result is register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1, placed in the W register. If 'd' is 1 the result is placed back in the result is placed back in register 'f'. register 'f'. If the result is 0, the next instruc- Words: 1 tion, which is already fetched, is discarded. A NOP is executed Cycles: 1 instead making it a two-cycle Example IORWF RESULT, 0 instruction. Before Instruction Words: 1 RESULT = 0x13 W = 0x91 Cycles: 1(2) After Instruction Example HERE INCFSZ CNT, 1 RESULT = 0x13 GOTO LOOP W = 0x93 CONTINUE (cid:127) Z = 1 (cid:127) (cid:127) Before Instruction MOVLW Move Literal to W PC = address HERE Syntax: [ label ] MOVLW k After Instruction CNT = CNT + 1 Operands: 0 ≤ k ≤ 255 if CNT= 0, Operation: k → (W) PC = address CONTINUE if CNT≠ 0, Status Affected: None PC = address HERE +1 Encoding: 11 00xx kkkk kkkk Description: The eight bit literal 'k' is loaded into W register. The don’t cares IORLW Inclusive OR Literal with W will assemble as 0’s. Syntax: [ label ] IORLW k Words: 1 Operands: 0 ≤ k ≤ 255 Cycles: 1 Operation: (W) .OR. k → (W) Example MOVLW 0x5A Status Affected: Z After Instruction Encoding: 11 1000 kkkk kkkk W = 0x5A Description: The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example IORLW 0x35 Before Instruction W = 0x9A After Instruction W = 0xBF Z = 1 DS30235J-page 68  2003 Microchip Technology Inc.

PIC16C62X MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0 ≤ f ≤ 127 Operands: None d ∈ [0,1] Operation: No operation Operation: (f) → (dest) Status Affected: None Status Affected: Z Encoding: 00 0000 0xx0 0000 Encoding: 00 1000 dfff ffff Description: No operation. Description: The contents of register f is Words: 1 moved to a destination dependent upon the status of d. If d = 0, Cycles: 1 destination is W register. If d = 1, Example NOP the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. OPTION Load Option Register Words: 1 Syntax: [ label ] OPTION Cycles: 1 Operands: None Example MOVF FSR, 0 Operation: (W) → OPTION After Instruction Status Affected: None W = value in FSR Encoding: 00 0000 0110 0010 register Z = 1 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for MOVWF Move W to f code compatibility with PIC16C5X products. Since OPTION is a read- Syntax: [ label ] MOVWF f able/writable register, the user can Operands: 0 ≤ f ≤ 127 directly addressit. Operation: (W) → (f) Words: 1 Status Affected: None Cycles: 1 Encoding: 00 0000 1fff ffff Example Description: Move data from W register to reg- To maintain upward compatibil- ® ister 'f'. ity with future PICmicro products, do not use this Words: 1 instruction. Cycles: 1 Example MOVWF OPTION Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F  2003 Microchip Technology Inc. DS30235J-page 69

PIC16C62X RETFIE Return from Interrupt RETLW Return with Literal in W Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, Operation: k → (W); 1 → GIE TOS → PC Status Affected: None Status Affected: None Encoding: 00 0000 0000 1001 Encoding: 11 01xx kkkk kkkk Description: Return from Interrupt. Stack is Description: The W register is loaded with the POPed and Top of Stack (TOS) is eight bit literal 'k'. The program loaded in the PC. Interrupts are counter is loaded from the top of enabled by setting Global the stack (the return address). Interrupt Enable bit, GIE This is a two-cycle instruction. (INTCON<7>). This is a two-cycle Words: 1 instruction. Cycles: 2 Words: 1 Example CALL TABLE;W contains Cycles: 2 table Example RETFIE ;offset value TABLE (cid:127) ;W now has table value After Interrupt (cid:127) PC = TOS (cid:127) GIE = 1 ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; (cid:127) (cid:127) (cid:127) RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS → PC Status Affected: None Encoding: 00 0000 0000 1000 Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETURN After Interrupt PC = TOS DS30235J-page 70  2003 Microchip Technology Inc.

PIC16C62X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: 00 1101 dfff ffff Encoding: 00 1100 dfff ffff Description: The contents of register 'f' are Description: The contents of register 'f' are rotated one bit to the left through rotated one bit to the right through the Carry Flag. If 'd' is 0, the result the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is is placed in the W register. If 'd' is 1, the result is stored back in 1, the result is placed back in register 'f'. register 'f'. C Register f C Register f Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example RLF REG1,0 Example RRF REG1, Before Instruction 0 REG1 = 1110 0110 Before Instruction C = 0 REG1 = 1110 0110 After Instruction C = 0 REG1 = 1110 0110 After Instruction W = 1100 1100 REG1 = 1110 0110 C = 1 W = 0111 0011 C = 0 SLEEP Syntax: [ label SLEEP ] Operands: None Operation: 00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD Status Affected: TO, PD Encoding: 00 0000 0110 0011 Description: The power-down STATUS bit, PD is cleared. Time-out STATUS bit, TO is set. Watch- dog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section9.8 for more details. Words: 1 Cycles: 1 Example: SLEEP  2003 Microchip Technology Inc. DS30235J-page 71

PIC16C62X SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF f,d Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 Operation: k - (W) → (W) d ∈ [0,1] Operation: (f) - (W) → (dest) Status C, DC, Z Affected: Status C, DC, Z Affected: Encoding: 11 110x kkkk kkkk Encoding: 00 0010 dfff ffff Description: The W register is subtracted (2’s complement method) from the eight Description: Subtract (2’s complement method) bit literal 'k'. The result is placed in Wregister from register 'f'. If 'd' is 0, the W register. the result is stored in the W register. If 'd' is 1, the result is stored back in Words: 1 register 'f'. Cycles: 1 Words: 1 Example 1: SUBLW 0x02 Cycles: 1 Before Instruction Example 1: SUBWF REG1,1 W = 1 Before Instruction C = ? After Instruction REG1= 3 W = 2 W = 1 C = ? C = 1; result is positive After Instruction Example 2: Before Instruction REG1= 1 W = 2 W = 2 C = ? C = 1; result is positive After Instruction Example 2: Before Instruction W = 0 REG1= 2 C = 1; result is zero W = 2 Example 3: Before Instruction C = ? W = 3 After Instruction C = ? REG1= 0 After Instruction W = 2 C = 1; result is zero W = 0xFF C = 0; result is negative Example 3: Before Instruction REG1= 1 W = 2 C = ? After Instruction REG1= 0xFF W = 2 C = 0; result is negative DS30235J-page 72  2003 Microchip Technology Inc.

PIC16C62X SWAPF Swap Nibbles in f XORLW Exclusive OR Literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label XORLW k Operands: 0 ≤ f ≤ 127 ] d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (f<3:0>) → (dest<7:4>), Operation: (W) .XOR. k → (W) (f<7:4>) → (dest<3:0>) Status Affected: Z Status Affected: None Encoding: 11 1010 kkkk kkkk Encoding: 00 1110 dfff ffff Description: The contents of the W register Description: The upper and lower nibbles of are XOR’ed with the eight bit register 'f' are exchanged. If 'd' is literal 'k'. The result is placed in 0, the result is placed in W the Wregister. register. If 'd' is 1, the result is Words: 1 placed in register 'f'. Cycles: 1 Words: 1 Example: XORLW 0xAF Cycles: 1 Before Instruction Example SWAPF REG, 0 W = 0xB5 Before Instruction After Instruction REG1 = 0xA5 W = 0x1A After Instruction REG1 = 0xA5 W = 0x5A XORWF Exclusive OR W with f Syntax: [ label ] XORWF f,d TRIS Load TRIS Register Operands: 0 ≤ f ≤ 127 Syntax: [ label ] TRIS f d ∈ [0,1] Operands: 5 ≤ f ≤ 7 Operation: (W) .XOR. (f) → (dest) Operation: (W) → TRIS register f; Status Affected: Z Status Affected: None Encoding: 00 0110 dfff ffff Encoding: 00 0000 0110 0fff Description: Exclusive OR the contents of the Description: The instruction is supported for Wregister with register 'f'. If 'd' is code compatibility with the 0, the result is stored in the W PIC16C5X products. Since TRIS register. If 'd' is 1, the result is registers are readable and stored back in register 'f'. writable, the user can directly Words: 1 address them. Cycles: 1 Words: 1 Example XORWF REG 1 Cycles: 1 Before Instruction Example REG = 0xAF To maintain upward compatibil- ® W = 0xB5 ity with future PICmicro prod- ucts, do not use this After Instruction instruction. REG = 0x1A W = 0xB5  2003 Microchip Technology Inc. DS30235J-page 73

PIC16C62X NOTES: DS30235J-page 74  2003 Microchip Technology Inc.

PIC16C62X 11.0 DEVELOPMENT SUPPORT 11.1 MPLAB Integrated Development Environment Software The PICmicro® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- (cid:127) Integrated Development Environment - MPLAB® IDE Software controller market. The MPLAB IDE is a Windows® based application that contains: (cid:127) Assemblers/Compilers/Linkers (cid:127) An interface to debugging tools - MPASMTM Assembler - simulator - MPLAB C17 and MPLAB C18 C Compilers - programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - emulator (sold separately) - in-circuit debugger (sold separately) - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library (cid:127) A full-featured editor with color coded context (cid:127) A multiple project manager (cid:127) Simulators (cid:127) Customizable data windows with direct edit of - MPLAB SIM Software Simulator contents - MPLAB dsPIC30 Software Simulator (cid:127) High level source code debugging (cid:127) Emulators (cid:127) Mouse over variable inspection - MPLAB ICE 2000 In-Circuit Emulator (cid:127) Extensive on-line help - MPLAB ICE 4000 In-Circuit Emulator The MPLAB IDE allows you to: (cid:127) In-Circuit Debugger - MPLAB ICD 2 (cid:127) Edit your source files (either assembly or C) (cid:127) Device Programmers (cid:127) One touch assemble (or compile) and download - PRO MATE® II Universal Device Programmer to PICmicro emulator and simulator tools - PICSTART® Plus Development Programmer (automatically updates all project information) (cid:127) Debug using: (cid:127) Low Cost Demonstration Boards - source files (assembly or C) - PICDEMTM 1 Demonstration Board - absolute listing file (mixed assembly and C) - PICDEM.netTM Demonstration Board - machine code - PICDEM 2 Plus Demonstration Board MPLAB IDE supports multiple debugging tools in a - PICDEM 3 Demonstration Board single development paradigm, from the cost effective - PICDEM 4 Demonstration Board simulators, through low cost in-circuit debuggers, to - PICDEM 17 Demonstration Board full-featured emulators. This eliminates the learning - PICDEM 18R Demonstration Board curve when upgrading to tools with increasing flexibility - PICDEM LIN Demonstration Board and power. - PICDEM USB Demonstration Board 11.2 MPASM Assembler (cid:127) Evaluation Kits - KEELOQ® The MPASM assembler is a full-featured, universal - PICDEM MSC macro assembler for all PICmicro MCUs. - microID® The MPASM assembler generates relocatable object - CAN files for the MPLINK object linker, Intel® standard HEX - PowerSmart® files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines - Analog and generated machine code and COFF files for debugging. The MPASM assembler features include: (cid:127) Integration into MPLAB IDE projects (cid:127) User defined macros to streamline assembly code (cid:127) Conditional assembly for multi-purpose source files (cid:127) Directives that allow complete control over the assembly process  2003 Microchip Technology Inc. DS30235J-page 75

PIC16C62X 11.3 MPLAB C17 and MPLAB C18 11.6 MPLAB ASM30 Assembler, Linker, C Compilers and Librarian The MPLAB C17 and MPLAB C18 Code Development MPLAB ASM30 assembler produces relocatable Systems are complete ANSI C compilers for machine code from symbolic assembly language for Microchip’s PIC17CXXX and PIC18CXXX family of dsPIC30F devices. MPLAB C30 compiler uses the microcontrollers. These compilers provide powerful assembler to produce it’s object file. The assembler integration capabilities, superior code optimization and generates relocatable object files that can then be ease of use not found with other compilers. archived or linked with other relocatable object files and archives to create an executable file. Notable features For easy source level debugging, the compilers provide of the assembler include: symbol information that is optimized to the MPLAB IDE debugger. (cid:127) Support for the entire dsPIC30F instruction set (cid:127) Support for fixed-point and floating-point data 11.4 MPLINK Object Linker/ (cid:127) Command line interface MPLIB Object Librarian (cid:127) Rich directive set The MPLINK object linker combines relocatable (cid:127) Flexible macro language objects created by the MPASM assembler and the (cid:127) MPLAB IDE compatibility MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from pre-compiled libraries, using 11.7 MPLAB SIM Software Simulator directives from a linker script. The MPLAB SIM software simulator allows code devel- The MPLIB object librarian manages the creation and opment in a PC hosted environment by simulating the modification of library files of pre-compiled code. When PICmicro series microcontrollers on an instruction a routine from a library is called from a source file, only level. On any given instruction, the data areas can be the modules that contain that routine will be linked in examined or modified and stimuli can be applied from with the application. This allows large libraries to be a file, or user defined key press, to any pin. The execu- used efficiently in many different applications. tion can be performed in Single-Step, Execute Until The object linker/library features include: Break, or Trace mode. (cid:127) Efficient linking of single libraries instead of many The MPLAB SIM simulator fully supports symbolic smaller files debugging using the MPLAB C17 and MPLAB C18 (cid:127) Enhanced code maintainability by grouping CCompilers, as well as the MPASM assembler. The related modules together software simulator offers the flexibility to develop and debug code outside of the laboratory environment, (cid:127) Flexible creation of libraries with easy module making it an excellent, economical software listing, replacement, deletion and extraction development tool. 11.5 MPLAB C30 C Compiler 11.8 MPLAB SIM30 Software Simulator The MPLAB C30 C compiler is a full-featured, ANSI The MPLAB SIM30 software simulator allows code compliant, optimizing compiler that translates standard development in a PC hosted environment by simulating ANSI C programs into dsPIC30F assembly language the dsPIC30F series microcontrollers on an instruction source. The compiler also supports many command- level. On any given instruction, the data areas can be line options and language extensions to take full examined or modified and stimuli can be applied from advantage of the dsPIC30F device hardware capabili- a file, or user defined key press, to any of the pins. ties, and afford fine control of the compiler code generator. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB C30 is distributed with a complete ANSI C MPLAB ASM30 assembler. The simulator runs in either standard library. All library functions have been a Command Line mode for automated tasks, or from validated and conform to the ANSI C library standard. MPLAB IDE. This high speed simulator is designed to The library includes functions for string manipulation, debug, analyze and optimize time intensive DSP dynamic memory allocation, data conversion, time- routines. keeping, and math functions (trigonometric, exponen- tial and hyperbolic). The compiler provides symbolic information for high level source debugging with the MPLAB IDE. DS30235J-page 76  2003 Microchip Technology Inc.

PIC16C62X 11.9 MPLAB ICE 2000 11.11 MPLAB ICD 2 In-Circuit Debugger High Performance Universal Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed The MPLAB ICE 2000 universal in-circuit emulator is USB interface. This tool is based on the FLASH intended to provide the product development engineer PICmicro MCUs and can be used to develop for these with a complete microcontroller design tool set for and other PICmicro microcontrollers. The MPLAB PICmicro microcontrollers. Software control of the ICD2 utilizes the in-circuit debugging capability built MPLAB ICE 2000 in-circuit emulator is advanced by into the FLASH devices. This feature, along with the MPLAB Integrated Development Environment, Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) which allows editing, building, downloading and source protocol, offers cost effective in-circuit FLASH debug- debugging from a single environment. ging from the graphical user interface of the MPLAB The MPLAB ICE 2000 is a full-featured emulator Integrated Development Environment. This enables a system with enhanced trace, trigger and data monitor- designer to develop and debug source code by setting ing features. Interchangeable processor modules allow breakpoints, single-stepping and watching variables, the system to be easily reconfigured for emulation of CPU status and peripheral registers. Running at full different processors. The universal architecture of the speed enables testing hardware and applications in MPLAB ICE in-circuit emulator allows expansion to real-time. MPLAB ICD2 also serves as a development support new PICmicro microcontrollers. programmer for selected PICmicro devices. The MPLAB ICE 2000 in-circuit emulator system has 11.12 PRO MATE II Universal Device been designed as a real-time emulation system with advanced features that are typically found on more Programmer expensive development tools. The PC platform and Microsoft® Windows 32-bit operating system were The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at chosen to best make these features available in a VDDMIN and VDDMAX for maximum reliability. It features simple, unified application. an LCD display for instructions and error messages 11.10 MPLAB ICE 4000 and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the High Performance Universal PROMATE II device programmer can read, verify, and In-Circuit Emulator program PICmicro devices without a PC connection. It can also set code protection in this mode. The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer 11.13 PICSTART Plus Development with a complete microcontroller design tool set for high- Programmer end PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the The PICSTART Plus development programmer is an MPLAB Integrated Development Environment, which easy-to-use, low cost, prototype programmer. It allows editing, building, downloading and source connects to the PC via a COM (RS-232) port. MPLAB debugging from a single environment. Integrated Development Environment software makes The MPLAB ICD 4000 is a premium emulator system, using the programmer simple and efficient. The providing the features of MPLAB ICE 2000, but with PICSTART Plus development programmer supports increased emulation memory and high speed perfor- most PICmicro devices up to 40 pins. Larger pin count mance for dsPIC30F and PIC18XXXX devices. Its devices, such as the PIC16C92X and PIC17C76X, advanced emulator features include complex triggering may be supported with an adapter socket. The and timing, up to 2 Mb of emulation memory, and the PICSTART Plus development programmer is CE ability to view variables in real-time. compliant. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.  2003 Microchip Technology Inc. DS30235J-page 77

PIC16C62X 11.14 PICDEM 1 PICmicro 11.17 PICDEM 3 PIC16C92X Demonstration Board Demonstration Board The PICDEM 1 demonstration board demonstrates the The PICDEM 3 demonstration board supports the capabilities of the PIC16C5X (PIC16C54 to PIC16C923 and PIC16C924 in the PLCC package. All PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, the necessary hardware and software is included to run PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All the demonstration programs. necessary hardware and software is included to run basic demo programs. The sample microcontrollers 11.18 PICDEM 4 8/14/18-Pin provided with the PICDEM 1 demonstration board can Demonstration Board be programmed with a PRO MATE II device program- The PICDEM 4 can be used to demonstrate the capa- mer, or a PICSTART Plus development programmer. bilities of the 8-, 14-, and 18-pin PIC16XXXX and The PICDEM 1 demonstration board can be connected PIC18XXXX MCUs, including the PIC16F818/819, to the MPLAB ICE in-circuit emulator for testing. A PIC16F87/88, PIC16F62XA and the PIC18F1320 prototype area extends the circuitry for additional family of microcontrollers. PICDEM 4 is intended to application components. Features include an RS-232 showcase the many features of these low pin count interface, a potentiometer for simulated analog input, parts, including LIN and Motor Control using ECCP. push button switches and eight LEDs. Special provisions are made for low power operation 11.15 PICDEM.net Internet/Ethernet with the supercapacitor circuit, and jumpers allow on- Demonstration Board board hardware to be disabled to eliminate current draw in this mode. Included on the demo board are pro- The PICDEM.net demonstration board is an Internet/ visions for Crystal, RC or Canned Oscillator modes, a Ethernet demonstration board using the PIC18F452 five volt regulator for use with a nine volt wall adapter microcontroller and TCP/IP firmware. The board or battery, DB-9 RS-232 interface, ICD connector for supports any 40-pin DIP device that conforms to the programming via ICSP and development with MPLAB standard pinout used by the PIC16F877 or ICD 2, 2x16 liquid crystal display, PCB footprints for H- PIC18C452. This kit features a user friendly TCP/IP Bridge motor driver, LIN transceiver and EEPROM. stack, web server with HTML, a 24L256 Serial Also included are: header for expansion, eight LEDs, EEPROM for Xmodem download to web pages into four potentiometers, three push buttons and a proto- Serial EEPROM, ICSP/MPLAB ICD 2 interface con- typing area. Included with the kit is a PIC16F627A and nector, an Ethernet interface, RS-232 interface, and a a PIC18F1320. Tutorial firmware is included along with 16 x 2 LCD display. Also included is the book and the User’s Guide. CD-ROM “TCP/IP Lean, Web Servers for Embedded Systems,” by Jeremy Bentham 11.19 PICDEM 17 Demonstration Board 11.16 PICDEM 2 Plus The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Demonstration Board Microchip microcontrollers, including PIC17C752, The PICDEM 2 Plus demonstration board supports PIC17C756A, PIC17C762 and PIC17C766. A many 18-, 28-, and 40-pin microcontrollers, including programmed sample is included. The PRO MATE II PIC16F87X and PIC18FXX2 devices. All the neces- device programmer, or the PICSTART Plus develop- sary hardware and software is included to run the dem- ment programmer, can be used to reprogram the onstration programs. The sample microcontrollers device for user tailored application development. The provided with the PICDEM 2 demonstration board can PICDEM 17 demonstration board supports program be programmed with a PRO MATE II device program- download and execution from external on-board mer, PICSTART Plus development programmer, or FLASH memory. A generous prototype area is MPLAB ICD 2 with a Universal Programmer Adapter. available for user hardware expansion. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2x16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs, and sample PIC18F452 and PIC16F877 FLASH microcontrollers. DS30235J-page 78  2003 Microchip Technology Inc.

PIC16C62X 11.20 PICDEM 18R PIC18C601/801 11.23 PICDEM USB PIC16C7X5 Demonstration Board Demonstration Board The PICDEM 18R demonstration board serves to assist The PICDEM USB Demonstration Board shows off the development of the PIC18C601/801 family of Microchip capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. It provides hardware implementation microcontrollers. This board provides the basis for of both 8-bit Multiplexed/De-multiplexed and 16-bit future USB products. Memory modes. The board includes 2 Mb external FLASH memory and 128 Kb SRAM memory, as well as 11.24 Evaluation and serial EEPROM, allowing access to the wide range of Programming Tools memory types supported by the PIC18C601/801. In addition to the PICDEM series of circuits, Microchip 11.21 PICDEM LIN PIC16C43X has a line of evaluation kits and demonstration software Demonstration Board for these products. (cid:127) KEELOQ evaluation and programming tools for The powerful LIN hardware and software kit includes a Microchip’s HCS Secure Data Products series of boards and three PICmicro microcontrollers. (cid:127) CAN developers kit for automotive network The small footprint PIC16C432 and PIC16C433 are applications used as slaves in the LIN communication and feature (cid:127) Analog design boards and filter design software on-board LIN transceivers. A PIC16F874 FLASH microcontroller serves as the master. All three micro- (cid:127) PowerSmart battery charging evaluation/ controllers are programmed with firmware to provide calibration kits LIN bus communication. (cid:127) IrDA® development kit 11.22 PICkitTM 1 FLASH Starter Kit (cid:127) microID development and rfLabTM development software A complete "development system in a box", the PICkit (cid:127) SEEVAL® designer kit for memory evaluation and FLASH Starter Kit includes a convenient multi-section endurance calculations board for programming, evaluation, and development (cid:127) PICDEM MSC demo boards for Switching mode of 8/14-pin FLASH PIC® microcontrollers. Powered via power supply, high power IR driver, delta sigma USB, the board operates under a simple Windows GUI. ADC, and flow rate sensor The PICkit 1 Starter Kit includes the user's guide (on Check the Microchip web page and the latest Product CD ROM), PICkit1 tutorial software and code for vari- Line Card for the complete list of demonstration and ous applications. Also included are MPLAB® IDE evaluation kits. (Integrated Development Environment) software, soft- ware and hardware "Tips 'n Tricks for 8-pin FLASH PIC® Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices.  2003 Microchip Technology Inc. DS30235J-page 79

PIC16C62X NOTES: DS30235J-page 80  2003 Microchip Technology Inc.

PIC16C62X 12.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings † Ambient Temperature under bias..............................................................................................................-40° to +125°C Storage Temperature................................................................................................................................-65° to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR).......................................................-0.6V to VDD +0.6V Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +14V Voltage on RA4 with respect to VSS...........................................................................................................................8.5V Total power Dissipation (Note 1)...............................................................................................................................1.0W Maximum Current out of VSS pin..........................................................................................................................300 mA Maximum Current into VDD pin.............................................................................................................................250 mA Input Clamp Current, IIK (VI <0 or VI> VDD)......................................................................................................................±20 mA Output Clamp Current, IOK (VO <0 or VO>VDD)................................................................................................................±20 mA Maximum Output Current sunk by any I/O pin........................................................................................................25 mA Maximum Output Current sourced by any I/O pin...................................................................................................25 mA Maximum Current sunk by PORTA and PORTB...................................................................................................200 mA Maximum Current sourced by PORTA and PORTB..............................................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL). 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100Ω should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2003 Microchip Technology Inc. DS30235J-page 81

PIC16C62X FIGURE 12-1: PIC16C62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 12-2: PIC16LC62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. DS30235J-page 82  2003 Microchip Technology Inc.

PIC16C62X FIGURE 12-3: PIC16C62XA VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +70°C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 12-4: PIC16C62XA VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ 0°C, +70°C ≤ T ≤ A A +125°C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.  2003 Microchip Technology Inc. DS30235J-page 83

PIC16C62X FIGURE 12-5: PIC16LC620A/LC621A/LC622A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ 0°C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.7 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 12-6: PIC16LC620A/LC621A/LC622A VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +125°C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. DS30235J-page 84  2003 Microchip Technology Inc.

PIC16C62X FIGURE 12-7: PIC16CR62XA VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +70°C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 12-8: PIC16CR62XA VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ 0°C, A +70°C ≤ T ≤ +125°C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.  2003 Microchip Technology Inc. DS30235J-page 85

PIC16C62X FIGURE 12-9: PIC16LCR62XA VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 6.0 5.5 5.0 4.5 VDD (VOLTS) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. DS30235J-page 86  2003 Microchip Technology Inc.

PIC16C62X FIGURE 12-10: PIC16C620A/C621A/C622A/CR620A - 40 VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +70°C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 0 4 10 20 25 40 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 3: Operation between 20 to 40 MHz requires the following: (cid:127) VDD between 4.5V. and 5.5V (cid:127) OSC1 externally driven (cid:127) OSC2 not connected (cid:127) HS mode (cid:127) Commercial temperatures Devices qualified for 40 MHz operation have -40 designation (ex: PIC16C620A-40/P).  2003 Microchip Technology Inc. DS30235J-page 87

PIC16C62X 12.1 DC Characteristics: PIC16C62X-04 (Commercial, Industrial, Extended) PIC16C62X-20 (Commercial, Industrial, Extended) PIC16LC62X-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16C62X 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LC62X 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range is the PIC16C62X range. Param. Sym Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 3.0 — 6.0 V See Figures 12-1, 12-2, 12-3, 12-4, and 12-5 D001 VDD Supply Voltage 2.5 — 6.0 V See Figures 12-1, 12-2, 12-3, 12-4, and 12-5 D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D003 VPOR VDD start voltage to ensure — Vss — V See section on Power-on Reset for details Power-on Reset D003 VPOR VDD start voltage to — VSS — V See section on Power-on Reset for details ensure Power-on Reset D004 SVDD VDD rise rate to ensure 0.05* — — V/ms See section on Power-on Reset for details Power-on Reset D004 SVDD VDD rise rate to ensure 0.05* — — V/ms See section on Power-on Reset for details Power-on Reset D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.3 V BOREN configuration bit is cleared D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.3 V BOREN configuration bit is cleared D010 IDD Supply Current(2) — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT mode, (Note 4)* — 35 70 µA FOSC = 32 kHz, VDD = 4.0V, WDT disabled, LP mode — 9.0 20 mA FOSC = 20 MHz, VDD = 5.5V, WDT disabled, HS mode D010 IDD Supply Current(2) — 1.4 2.5 mA FOSC = 2.0MHz, VDD = 3.0V, WDT disabled, XT mode, (Note 4) — 26 53 µA FOSC = 32kHz, VDD = 3.0V, WDT disabled, LP mode D020 IPD Power-down Current(3) — 1.0 2.5 µA VDD=4.0V, WDT disabled 15 µA (125°C) D020 IPD Power-down Current(3) — 0.7 2 µA VDD=3.0V, WDT disabled * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS30235J-page 88  2003 Microchip Technology Inc.

PIC16C62X 12.1 DC Characteristics: PIC16C62X-04 (Commercial, Industrial, Extended) PIC16C62X-20 (Commercial, Industrial, Extended) PIC16LC62X-04 (Commercial, Industrial, Extended) (CONT.) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16C62X 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LC62X 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range is the PIC16C62X range. Param Sym Characteristic Min Typ† Max Units Conditions . No. D022 ∆IWDT WDT Current(5) — 6.0 20 µA VDD=4.0V 25 µA (125°C) D022A ∆IBOR Brown-out Reset Current(5) — 350 425 µA BOD enabled, VDD = 5.0V D023 ∆ICOM Comparator Current for each — — 100 µA VDD = 4.0V P Comparator(5) D023A VREF Current(5) — — 300 µA VDD = 4.0V ∆IVREF D022 ∆IWDT WDT Current(5) — 6.0 15 µA VDD=3.0V D022A ∆IBOR Brown-out Reset Current(5) — 350 425 µA BOD enabled, VDD = 5.0V D023 ∆ICOM Comparator Current for each — — 100 µA VDD = 3.0V P Comparator(5) D023A VREF Current(5) — — 300 µA VDD = 3.0V ∆IVREF 1A FOSC LP Oscillator Operating Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures 1A FOSC LP Oscillator Operating Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.  2003 Microchip Technology Inc. DS30235J-page 89

PIC16C62X 12.2 DC Characteristics: PIC16C62XA-04 (Commercial, Industrial, Extended) PIC16C62XA-20 (Commercial, Industrial, Extended) PIC16LC62XA-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16C62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LC62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 3.0 — 5.5 V See Figures 12-1, 12-2, 12-3, 12-4, and 12-5 D001 VDD Supply Voltage 2.5 — 5.5 V See Figures 12-1, 12-2, 12-3, 12-4, and 12-5 D002 VDR RAM Data Retention — 1.5* — V Device in SLEEP mode Voltage(1) D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D003 VPOR VDD start voltage to — VSS — V See section on Power-on Reset for details ensure Power-on Reset D003 VPOR VDD start voltage to — VSS — V See section on Power-on Reset for details ensure Power-on Reset D004 SVDD VDD rise rate to ensure 0.05* — — V/ms See section on Power-on Reset for details Power-on Reset D004 SVDD VDD rise rate to ensure 0.05* — — V/ms See section on Power-on Reset for details Power-on Reset D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.35 V BOREN configuration bit is cleared D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.35 V BOREN configuration bit is cleared * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only. DS30235J-page 90  2003 Microchip Technology Inc.

PIC16C62X 12.2 DC Characteristics: PIC16C62XA-04 (Commercial, Industrial, Extended) PIC16C62XA-20 (Commercial, Industrial, Extended) PIC16LC62XA-04 (Commercial, Industrial, Extended) (CONT.) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16C62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LC62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. D010 IDD Supply Current(2, 4) — 1.2 2.0 mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT mode, (Note 4)* — 0.4 1.2 mA FOSC = 4 MHz, VDD = 3.0V, WDT disabled, XT mode, (Note 4)* — 1.0 2.0 mA FOSC = 10 MHz, VDD = 3.0V, WDT dis- abled, HS mode, (Note 6) — 4.0 6.0 mA FOSC = 20 MHz, VDD = 4.5V, WDT dis- abled, HS mode — 4.0 7.0 mA FOSC = 20 MHz, VDD = 5.5V, WDT dis- abled*, HS mode — 35 70 µA FOSC = 32 kHz, VDD = 3.0V, WDT dis- abled, LP mode D010 IDD Supply Current(2) — 1.2 2.0 mA FOSC = 4MHz, VDD = 5.5V, WDT disabled, XT mode, (Note 4)* — — 1.1 mA FOSC = 4MHz, VDD = 2.5V, WDT disabled, XT mode, (Note 4) — 35 70 µA FOSC = 32kHz, VDD = 2.5V, WDT dis- abled, LP mode D020 IPD Power-down Current(3) — — 2.2 µA VDD = 3.0V — — 5.0 µA VDD = 4.5V* — — 9.0 µA VDD = 5.5V — — 15 µA VDD = 5.5V Extended Temp. D020 IPD Power-down Current(3) — — 2.0 µA VDD = 2.5V — — 2.2 µA VDD = 3.0V* — — 9.0 µA VDD = 5.5V — — 15 µA VDD = 5.5V Extended Temp. * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only.  2003 Microchip Technology Inc. DS30235J-page 91

PIC16C62X 12.2 DC Characteristics: PIC16C62XA-04 (Commercial, Industrial, Extended) PIC16C62XA-20 (Commercial, Industrial, Extended) PIC16LC62XA-04 (Commercial, Industrial, Extended (CONT.) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16C62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LC62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. D022 ∆IWDT WDT Current(5) — 6.0 10 µA VDD = 4.0V 12 µA (125°C) D022A ∆IBOR Brown-out Reset Current(5) — 75 125 µA BOD enabled, VDD = 5.0V D023 ∆ICOMP Comparator Current for each — 30 60 µA VDD = 4.0V (5) Comparator D023A ∆IVREF VREF Current(5) — 80 135 µA VDD = 4.0V D022 ∆IWDT WDT Current(5) — 6.0 10 µA VDD=4.0V 12 µA (125°C) D022A ∆IBOR Brown-out Reset Current(5) — 75 125 µA BOD enabled, VDD = 5.0V D023 ∆ICOMP Comparator Current for each — 30 60 µA VDD = 4.0V (5) Comparator D023A ∆IVREF VREF Current(5) — 80 135 µA VDD = 4.0V 1A FOSC LP Oscillator Operating Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures 1A FOSC LP Oscillator Operating Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only. DS30235J-page 92  2003 Microchip Technology Inc.

PIC16C62X 12.3 DC CHARACTERISTICS: PIC16CR62XA-04 (Commercial, Industrial, Extended) PIC16CR62XA-20 (Commercial, Industrial, Extended) PIC16LCR62XA-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) PIC16CR62XA-04 Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16CR62XA-20 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LCR62XA-04 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 3.0 — 5.5 V See Figures 12-7, 12-8, 12-9 D001 VDD Supply Voltage 2.5 — 5.5 V See Figures 12-7, 12-8, 12-9 D002 VDR RAM Data Retention — 1.5* — V Device in SLEEP mode (1) Voltage D002 VDR RAM Data Retention — 1.5* — V Device in SLEEP mode (1) Voltage D003 VPOR VDD start voltage to — VSS — V See section on Power-on Reset for details ensure Power-on Reset D003 VPOR VDD start voltage to — VSS — V See section on Power-on Reset for details ensure Power-on Reset D004 SVDD VDD rise rate to ensure 0.05* — — V/ms See section on Power-on Reset for details Power-on Reset D004 SVDD VDD rise rate to ensure 0.05* — — V/ms See section on Power-on Reset for details Power-on Reset D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.35 V BOREN configuration bit is cleared D005 VBOR Brown-out Detect Voltage 3.7 4.0 4.35 V BOREN configuration bit is cleared D010 IDD Supply Current(2) — 1.2 1.7 mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT mode, (Note 4)* — 500 900 µA FOSC = 4 MHz, VDD = 3.0V, WDT disabled, XT mode, (Note 4) — 1.0 2.0 mA FOSC = 10 MHz, VDD = 3.0V, WDT disabled, HS mode, (Note 6) — 4.0 7.0 mA FOSC = 20 MHz, VDD = 5.5V, WDT disabled*, HS — 3.0 6.0 mA mode — 35 70 µA FOSC = 20 MHz, VDD = 4.5V, WDT disabled, HS mode FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP mode D010 IDD Supply Current(2) — 1.2 1.7 mA FOSC = 4.0 MHz, VDD = 5.5V, WDT disabled, XT mode, (Note 4)* — 400 800 µA FOSC = 4.0 MHz, VDD = 2.5V, WDT disabled, XT mode (Note 4) — 35 70 µA FOSC = 32 kHz, VDD = 2.5V, WDT disabled, LP mode  2003 Microchip Technology Inc. DS30235J-page 93

PIC16C62X Standard Operating Conditions (unless otherwise stated) PIC16CR62XA-04 Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16CR62XA-20 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LCR62XA-04 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only. DS30235J-page 94  2003 Microchip Technology Inc.

PIC16C62X 12.3 DC CHARACTERISTICS: PIC16CR62XA-04 (Commercial, Industrial, Extended) PIC16CR62XA-20 (Commercial, Industrial, Extended) PIC16LCR62XA-04 (Commercial, Industrial, Extended) (CONT.) Standard Operating Conditions (unless otherwise stated) PIC16CR62XA-04 Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16CR62XA-20 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LCR62XA-04 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. D020 IPD Power-down Current(3) — 200 950 nA VDD = 3.0V — 0.400 1.8 µA VDD = 4.5V* — 0.600 2.2 µA VDD = 5.5V — 5.0 9.0 µA VDD = 5.5V Extended Temp. D020 IPD Power-down Current(3) — 200 850 nA VDD = 2.5V — 200 950 nA VDD = 3.0V* — 0.600 2.2 µA VDD = 5.5V — 5.0 9.0 µA VDD = 5.5V Extended D022 ∆IWDT WDT Current(5) — 6.0 10 µA VDD=4.0V 12 µA (125°C) D022A ∆IBOR Brown-out Reset Current(5) — 75 125 µA BOD enabled, VDD = 5.0V D023 ∆ICOMP Comparator Current for each — 30 60 µA VDD = 4.0V (5) Comparator D023A ∆IVREF VREF Current(5) — 80 135 µA VDD = 4.0V D022 ∆IWDT WDT Current(5) — 6.0 10 µA VDD=4.0V 12 µA (125°C) D022A ∆IBOR Brown-out Reset Current(5) — 75 125 µA BOD enabled, VDD = 5.0V D023 ∆ICOMP Comparator Current for each — 30 60 µA VDD = 4.0V (5) Comparator D023A ∆IVREF VREF Current(5) — 80 135 µA VDD = 4.0V 1A FOSC LP Oscillator Operating Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures 1A FOSC LP Oscillator Operating Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula: Ir = VDD/2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only.  2003 Microchip Technology Inc. DS30235J-page 95

PIC16C62X 12.4 DC Characteristics: PIC16C62X/C62XA/CR62XA (Commercial, Industrial, Extended) PIC16LC62X/LC62XA/LCR62XA (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16C62X/C62XA/CR62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LC62X/LC62XA/LCR62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports D030 with TTL buffer VSS — 0.8V V VDD = 4.5V to 5.5V 0.15 VDD otherwise D031 with Schmitt Trigger input VSS — 0.2 VDD V D032 MCLR, RA4/T0CKI,OSC1 (in RC mode) Vss — 0.2 VDD V (Note 1) D033 OSC1 (in XT and HS) Vss — 0.3 VDD V OSC1 (in LP) Vss — 0.6 VDD- V 1.0 VIL Input Low Voltage I/O ports D030 with TTL buffer VSS — 0.8V V VDD = 4.5V to 5.5V 0.15 VDD otherwise D031 with Schmitt Trigger input VSS — 0.2 VDD V D032 MCLR, RA4/T0CKI,OSC1 (in RC mode) Vss — 0.2 VDD V (Note 1) D033 OSC1 (in XT and HS) Vss — 0.3 VDD V OSC1 (in LP) Vss — 0.6 VDD- V 1.0 VIH Input High Voltage I/O ports D040 with TTL buffer 2.0V — VDD V VDD = 4.5V to 5.5V 0.25 VDD VDD otherwise + 0.8V D041 with Schmitt Trigger input 0.8 VDD — VDD D042 MCLR RA4/T0CKI 0.8 VDD — VDD V D043 OSC1 (XT, HS and LP) 0.7 VDD — V D043A OSC1 (in RC mode) 0.9 VDD VDD (Note 1) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C62X(A) be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. DS30235J-page 96  2003 Microchip Technology Inc.

PIC16C62X 12.4 DC Characteristics: PIC16C62X/C62XA/CR62XA (Commercial, Industrial, Extended) PIC16LC62X/LC62XA/LCR62XA (Commercial, Industrial, Extended) (CONT.) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16C62X/C62XA/CR62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LC62X/LC62XA/LCR62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. VIH Input High Voltage I/O ports D040 with TTL buffer 2.0V — V VDD = 4.5V to 5.5V 0.25 VDD VDD otherwise VDD + 0.8V D041 with Schmitt Trigger input 0.8 VDD — VDD D042 MCLR RA4/T0CKI 0.8 VDD — VDD V D043 OSC1 (XT, HS and LP) 0.7 VDD — V D043A OSC1 (in RC mode) 0.9 VDD VDD (Note 1) D070 IPURB PORTB weak pull-up current 50 200 400 µA VDD = 5.0V, VPIN = VSS D070 IPURB PORTB weak pull-up current 50 200 400 µA VDD = 5.0V, VPIN = VSS IIL Input Leakage Current(2, 3) I/O ports (Except PORTA) ±1.0 µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance D060 PORTA — — ±0.5 µA Vss ≤ VPIN ≤ VDD, pin at hi-impedance D061 RA4/T0CKI — — ±1.0 µA Vss ≤ VPIN ≤ VDD D063 OSC1, MCLR — — µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc ±5.0 configuration IIL Input Leakage Current(2, 3) I/O ports (Except PORTA) ±1.0 µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance D060 PORTA — — ±0.5 µA Vss ≤ VPIN ≤ VDD, pin at hi-impedance D061 RA4/T0CKI — — ±1.0 µA Vss ≤ VPIN ≤ VDD D063 OSC1, MCLR — — µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc ±5.0 configuration VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40° to +85°C — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, +125°C D083 OSC2/CLKOUT (RC only) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40° to +85°C — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, +125°C * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C62X(A) be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin.  2003 Microchip Technology Inc. DS30235J-page 97

PIC16C62X 12.4 DC Characteristics: PIC16C62X/C62XA/CR62XA (Commercial, Industrial, Extended) PIC16LC62X/LC62XA/LCR62XA (Commercial, Industrial, Extended) (CONT.) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16C62X/C62XA/CR62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and PIC16LC62X/LC62XA/LCR62XA 0°C ≤ TA ≤ +70°C for commercial and -40°C ≤ TA ≤ +125°C for extended Param. Sym Characteristic Min Typ† Max Units Conditions No. VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40° to +85°C — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, +125°C D083 OSC2/CLKOUT (RC only) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40° to +85°C — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, +125°C VOH Output High Voltage(3) D090 I/O ports (Except RA4) VDD-0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40° to +85°C VDD-0.7 — — V IOH = -2.5 mA, VDD = 4.5V, +125°C D092 OSC2/CLKOUT (RC only) VDD-0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40° to +85°C VDD-0.7 — — V IOH = -1.0 mA, VDD = 4.5V, +125°C VOH Output High Voltage(3) D090 I/O ports (Except RA4) VDD-0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40° to +85°C VDD-0.7 — — V IOH = -2.5 mA, VDD = 4.5V, +125°C D092 OSC2/CLKOUT (RC only) VDD-0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40° to +85°C VDD-0.7 — — V IOH = -1.0 mA, VDD = 4.5V, +125°C *D150 VOD Open-Drain High Voltage 10* V RA4 pin PIC16C62X, PIC16LC62X 8.5* RA4 pin PIC16C62XA, PIC16LC62XA, PIC16CR62XA, PIC16LCR62XA *D150 VOD Open-Drain High Voltage 10* V RA4 pin PIC16C62X, PIC16LC62X 8.5* RA4 pin PIC16C62XA, PIC16LC62XA, PIC16CR62XA, PIC16LCR62XA Capacitive Loading Specs on Output Pins D100 COSC OSC2 pin pF In XT, HS and LP modes when external 15 2 clock used to drive OSC1. D101 CIO All I/O pins/OSC2 (in RC mode) 50 pF Capacitive Loading Specs on Output Pins D100 COSC OSC2 pin pF In XT, HS and LP modes when external 15 2 clock used to drive OSC1. D101 CIO All I/O pins/OSC2 (in RC mode) 50 pF * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C62X(A) be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. DS30235J-page 98  2003 Microchip Technology Inc.

PIC16C62X (7) 12.5 DC CHARACTERISTICS: PIC16C620A/C621A/C622A-40 (Commercial) (7) PIC16CR620A-40 (Commercial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature 0°C ≤ TA ≤ +70°C for commercial Param Sym Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 3.0 — 5.5 V FOSC = DC to 20 MHz D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D003 VPOR VDD start voltage to ensure — VSS — V See section on Power-on Reset for details Power-on Reset D004 SVDD VDD rise rate to ensure Power-on 0.05 — — V/ms See section on Power-on Reset for details Reset * D005 VBOR Brown-out Detect Voltage 3.65 4.0 4.35 V BOREN configuration bit is cleared D010 IDD Supply Current(2,4) — 1.2 2.0 mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled, XT OSC mode, (Note 4)* — 0.4 1.2 mA FOSC = 4 MHz, VDD = 3.0V, WDT disabled, XT OSC mode, (Note 4) — 1.0 2.0 mA FOSC = 10 MHz, VDD = 3.0V, WDT disabled, HS OSC mode, (Note 6) — 4.0 6.0 mA FOSC = 20 MHz, VDD = 4.5V, WDT disabled, HS OSC mode — 4.0 7.0 mA FOSC = 20 MHz, VDD = 5.5V, WDT disabled*, HS OSC mode — 35 70 µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP OSC mode D020 IPD Power Down Current(3) — — 2.2 µA VDD = 3.0V — — 5.0 µA VDD = 4.5V* — — 9.0 µA VDD = 5.5V — — 15 µA VDD = 5.5V Extended D022 ∆IWDT WDT Current(5) — 6.0 10 µA VDD = 4.0V 12 µA (125°C) D022A ∆IBOR Brown-out Reset Current(5) — 75 125 µA BOD enabled, VDD = 5.0V D023 ∆ICOMP Comparator Current for each — 30 60 µA VDD = 4.0V Comparator(5) D023A ∆IVREF VREF Current(5) — 80 135 µA VDD = 4.0V ∆IEE Write Operating Current — 3 mA VCC = 5.5V, SCL = 400 kHz ∆IEE Read Operating Current — 1 mA ∆IEE Standby Current — 30 µA VCC = 3.0V, EE VDD = VCC ∆IEE Standby Current — 100 µA VCC = 3.0V, EE VDD = VCC 1A FOSC LP Oscillator Operating Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC OSC configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/ 2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only. 7: See Section12.1 and Section12.3 for 16C62X and 16CR62X devices for operation between 20 MHz and 40 MHz for valid modified characteristics.  2003 Microchip Technology Inc. DS30235J-page 99

PIC16C62X (7) 12.5 DC CHARACTERISTICS: PIC16C620A/C621A/C622A-40 (Commercial) (7) PIC16CR620A-40 (Commercial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature 0°C ≤ TA ≤ +70°C for commercial Param Sym Characteristic Min Typ† Max Unit Conditions No. VIL Input Low Voltage I/O ports D030 with TTL buffer VSS — 0.8V V VDD = 4.5V to 5.5V, otherwise 0.15VDD D031 with Schmitt Trigger input VSS 0.2VDD V D032 MCLR, RA4/T0CKI, OSC1 VSS — 0.2VDD V (Note 1) (in RC mode) D033 OSC1 (in XT and HS) VSS — 0.3VDD V OSC1 (in LP) VSS — 0.6VDD - 1.0 V VIH Input High Voltage I/O ports D040 with TTL buffer 2.0V — VDD V VDD = 4.5V to 5.5V, otherwise 0.25 VDD + 0.8 VDD D041 with Schmitt Trigger input 0.8 VDD VDD D042 MCLR RA4/T0CKI 0.8 VDD — VDD V D043 OSC1 (XT, HS and LP) 0.7 VDD — VDD V D043A OSC1 (in RC mode) 0.9 VDD (Note 1) D070 IPURB PORTB Weak Pull-up Current 50 200 400 µA VDD = 5.0V, VPIN = VSS (2, 3) IIL Input Leakage Current I/O ports (except PORTA) ±1.0 µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance D060 PORTA — — ±0.5 µA Vss ≤ VPIN ≤ VDD, pin at hi-impedance D061 RA4/T0CKI — — ±1.0 µA Vss ≤ VPIN ≤ VDD D063 OSC1, MCLR — — ±5.0 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP OSC con- figuration VOL Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40° to +85°C — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, +125°C D083 OSC2/CLKOUT (RC only) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40° to +85°C — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, +125°C (3) VOH Output High Voltage D090 I/O ports (except RA4) VDD-0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40° to +85°C VDD-0.7 — — V IOH = -2.5 mA, VDD = 4.5V, +125°C D092 OSC2/CLKOUT (RC only) VDD-0.7 — — V IOH = -1.3 mA, VDD = 4.5V, -40° to +85°C VDD-0.7 — — V IOH = -1.0 mA, VDD = 4.5V, +125°C *D150 VOD Open Drain High Voltage 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin 15 pF In XT, HS and LP modes when external clock used to drive OSC1. D101 CIO All I/O pins/OSC2 (in RC mode) 50 pF * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: For RC OSC configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/ 2REXT (mA) with REXT in kΩ. 5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: Commercial temperature range only. 7: See Section12.1 and Section12.3 for 16C62X and 16CR62X devices for operation between 20 MHz and 40 MHz for valid modified characteristics. DS30235J-page 100  2003 Microchip Technology Inc.

PIC16C62X (3) 12.6 DC Characteristics: PIC16C620A/C621A/C622A-40 (Commercial) (3) PIC16CR620A-40 (Commercial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Power Supply Pins Operating temperature 0°C ≤ TA ≤ +70°C for commercial (1) Characteristic Sym Min Typ Max Units Conditions Supply Voltage VDD 4.5 — 5.5 V HS Option from 20 - 40 MHz (2) Supply Current IDD — 5.5 11.5 mA FOSC = 40 MHz, VDD = 4.5V, HS mode — 7.7 16 mA FOSC = 40 MHz, VDD = 5.5V, HS mode HS Oscillator Operating FOSC 20 — 40 MHz OSC1 pin is externally driven, Frequency OSC2 pin not connected Input Low Voltage OSC1 VIL VSS — 0.2VDD V HS mode, OSC1 externally driven Input High Voltage OSC1 VIH 0.8VDD — VDD V HS mode, OSC1 externally driven * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT disabled, HS mode with OSC2 not connected. 3: For device operation between DC and 20 MHz. See Table12-1 and Table12-2. (2) 12.7 AC Characteristics: PIC16C620A/C621A/C622A-40 (Commercial) (2) PIC16CR620A-40 (Commercial) AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) All Pins Except Power Supply Pins Operating temperature 0°C ≤ TA ≤ +70°C for commercial (1) Characteristic Sym Min Typ Max Units Conditions External CLKIN Frequency FOSC 20 — 40 MHz HS mode, OSC1 externally driven External CLKIN Period TOSC 25 — 50 ns HS mode (40), OSC1 externally driven Clock in (OSC1) Low or High Time TOSL, TOSH 6 — — ns HS mode, OSC1 externally driven Clock in (OSC1) Rise or Fall Time TOSR, TOSF — — 6.5 ns HS mode, OSC1 externally driven OSC1↑ (Q1 cycle) to Port out valid TOSH2IOV — — 100 ns — OSC1↑ (Q2 cycle) to Port input TOSH2IOI 50 — — ns — invalid (I/O in hold time) Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: For device operation between DC and 20 MHz. See Table12-1 and Table12-2.  2003 Microchip Technology Inc. DS30235J-page 101

PIC16C62X TABLE 12-1: COMPARATOR SPECIFICATIONS Operating Conditions: VDD range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is specified in Table12-1. Characteristics Sym Min Typ Max Units Comments Input offset voltage ± 5.0 ± 10 mV Input common mode voltage 0 VDD - 1.5 V CMRR +55* δβ (1) Response Time 400* ns PIC16C62X(A) 150* 600* ns PIC16LC62X Comparator mode change to 10* µs output valid * These parameters are characterized but not tested. Note1: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. TABLE 12-2: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions:VDD range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is specified in Table12-1. Characteristics Sym Min Typ Max Units Comments Resolution VDD/24 LSB Low Range (VRR=1) VDD/32 LSB High Range (VRR=0) Absolute Accuracy +1/4 LSB Low Range (VRR=1) +1/2 LSB High Range (VRR=0) Unit Resistor Value (R) 2K* Ω Figure8-1 (1) Settling Time 10* µs * These parameters are characterized but not tested. Note1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. DS30235J-page 102  2003 Microchip Technology Inc.

PIC16C62X 12.8 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp ck CLKOUT osc OSC1 io I/O port t0 T0CKI mc MCLR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-Impedance FIGURE 12-11: LOAD CONDITIONS Load condition 1 Load condition 2 VDD/2 RL CL CL Pin Pin VSS VSS RL = 464Ω CL = 50 pF for all pins except OSC2 15 pF for OSC2 output  2003 Microchip Technology Inc. DS30235J-page 103

PIC16C62X 12.9 Timing Diagrams and Specifications FIGURE 12-12: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 12-3: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 1A Fosc External CLKIN Frequency(1) DC — 4 MHz XT and RC Osc mode, VDD=5.0V DC — 20 MHz HS Osc mode DC — 200 kHz LP Osc mode Oscillator Frequency(1) DC — 4 MHz RC Osc mode, VDD=5.0V 0.1 — 4 MHz XT Osc mode 1 — 20 MHz HS Osc mode DC — 200 kHz LP Osc mode 1 Tosc External CLKIN Period(1) 250 — — ns XT and RC Osc mode 50 — — ns HS Osc mode 5 — — µs LP Osc mode Oscillator Period(1) 250 — — ns RC Osc mode 250 — 10,000 ns XT Osc mode 50 — 1,000 ns HS Osc mode 5 — — µs LP Osc mode 2 TCY Instruction Cycle Time(1) 1.0 FOSC/4 DC µs TCYS=FOSC/4 3* TosL, External Clock in (OSC1) High or 100* — — ns XT oscillator, TOSC L/H duty cycle TosH Low Time 2* — — µs LP oscillator, TOSC L/H duty cycle 20* — — ns HS oscillator, TOSC L/H duty cycle 4* TosR, External Clock in (OSC1) Rise or 25* — — ns XT oscillator TosF Fall Time 50* — — ns LP oscillator 15* — — ns HS oscillator 2: * These parameters are characterized but not tested. 3: † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS30235J-page 104  2003 Microchip Technology Inc.

PIC16C62X FIGURE 12-13: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 10 11 22 CLKOUT 23 13 18 12 14 19 16 I/O Pin (input) 17 15 I/O Pin old value new value (output) 20, 21 Note: All tests must be done with specified capacitance loads (Figure12-11) 50 pF on I/O pins and CLKOUT.  2003 Microchip Technology Inc. DS30235J-page 105

PIC16C62X TABLE 12-4: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1↑ to CLKOUT↓(1) — 75 200 ns PIC16C62X(A) — — 400 ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA 11* TosH2ck OSC1↑ to CLKOUT↑(1) — 75 200 ns PIC16C62X(A) H — — 400 ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA (1) 12* TckR CLKOUT rise time — 35 100 ns PIC16C62X(A) — — 200 ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA (1) 13* TckF CLKOUT fall time — 35 100 ns PIC16C62X(A) — — 200 ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA 14* TckL2ioV CLKOUT ↓ to Port out valid(1) — — 20 ns 15* TioV2ckH Port in valid before CLKOUT ↑(1) TOSC +200 — — ns PIC16C62X(A) ns — — ns PIC16LC62X(A) TOSC +400 PIC16CR62XA ns PIC16LCR62XA 16* TckH2ioI Port in hold after CLKOUT ↑(1) 0 — — ns 17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns PIC16C62X(A) — 300 ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA 18* TosH2ioI OSC1↑ (Q2 cycle) to Port input 100 — — ns PIC16C62X(A) invalid (I/O in hold time) 200 — — ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA 19* TioV2osH Port input valid to OSC1↑ (I/O in 0 — — ns setup time) 20* TioR Port output rise time — 10 40 ns PIC16C62X(A) — — 80 ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA 21* TioF Port output fall time — 10 40 ns PIC16C62X(A) — — 80 ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA 22* Tinp RB0/INT pin high or low time 25 — — ns PIC16C62X(A) 40 — — ns PIC16LC62X(A) PIC16CR62XA PIC16LCR62XA 23 Trbp RB<7:4> change interrupt high or TCY — — ns low time * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. DS30235J-page 106  2003 Microchip Technology Inc.

PIC16C62X FIGURE 12-14: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins FIGURE 12-15: BROWN-OUT RESET TIMING VDD BVDD 35 TABLE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2000 — — ns -40° to +85°C 31 Twdt Watchdog Timer Time-out Period 7* 18 33* ms VDD = 5.0V, -40° to +85°C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33 Tpwrt Power-up Timer Period 28* 72 132* ms VDD = 5.0V, -40° to +85°C 34 TIOZ I/O hi-impedance from MCLR low — 2.0 µs 35 TBOR Brown-out Reset Pulse Width 100* — — µs 3.7V ≤ VDD ≤ 4.3V * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested.  2003 Microchip Technology Inc. DS30235J-page 107

PIC16C62X FIGURE 12-16: TIMER0 CLOCK TIMING RA4/T0CKI 40 41 42 TMR0 TABLE 12-6: TIMER0 CLOCK REQUIREMENTS Parameter Sym Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 42 Tt0P T0CKI Period TCY + 40* — — ns N = prescale value N (1, 2, 4, ..., 256) * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. DS30235J-page 108  2003 Microchip Technology Inc.

PIC16C62X 13.0 DEVICE CHARACTERIZATION INFORMATION The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution, while “max” or “min” represents (mean + 3σ) and (mean – 3σ) respectively, where σ is standard deviation. FIGURE 13-1: I VS. FREQUENCY (XT MODE, V = 5.5V) DD DD 1.20 1.00 0.8 A) m (D 0.6 D I 0.4 0.2 0.00 0.20 1.00 2.00 4.00 Frequency (MHz) FIGURE 13-2: PIC16C622A I VS. V (WDT DISABLE) PD DD 0.35 0.30 0.25 0.20 A) u 0.15 (D P I 0.10 0.05 0.00 -0.05 3 4 5 6 VDD (V)  2003 Microchip Technology Inc. DS30235J-page 109

PIC16C62X FIGURE 13-3: I VS. V (XT OSC 4MHZ) DD DD 1.00 0.9 0.8 0.7 A) m 0.6 (D D I 0.5 0.4 0.3 0.2 2.5 3 3.5 4 4.5 5 5.5 VDD (VOLTS) FIGURE 13-4: I I . V , V = 3.0V) O VS OL DD 50 45 MAX -40°C 40 35 TYP 25°C A) 30 m I (O 25 MIN 85°C I 20 15 10 5 0 0 .5 1 1.5 2 2.5 3 Vol (V) DS30235J-page 110  2003 Microchip Technology Inc.

PIC16C62X FIGURE 13-5: I . V , V = 3.0V) OHVS OH DD 0 -5 MIN 85°C A) -10 m (H O TYP 25°C I -15 MAX -40°C -20 -25 0 .5 1 1.5 2 2.5 3 VOH (V) FIGURE 13-6: I I . V , V = 5.5V) O VS OL DD 100 90 MAX -40°C 80 70 TYP 25°C A) 60 MIN 85°C m I (O 50 I 40 30 20 10 0 0 .5 1 1.5 2 2.5 3 Vol (V)  2003 Microchip Technology Inc. DS30235J-page 111

PIC16C62X FIGURE 13-7: I . V , V = 5.5V) OHVS OH DD 0 -10 A) -20 m (OH MIN 85°C I -30 TYP 25°C -40 MAX -40°C -50 3 3.5 4 4.5 5 5.5 VOH (V) DS30235J-page 112  2003 Microchip Technology Inc.

PIC16C62X 14.0 PACKAGING INFORMATION 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) E1 W2 D 2 n 1 W1 E A A2 c L A1 eB B1 B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .170 .183 .195 4.32 4.64 4.95 Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19 Standoff A1 .015 .023 .030 0.38 0.57 0.76 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Ceramic Pkg. Width E1 .285 .290 .295 7.24 7.37 7.49 Overall Length D .880 .900 .920 22.35 22.86 23.37 Tip to Seating Plane L .125 .138 .150 3.18 3.49 3.81 Lead Thickness c .008 .010 .012 0.20 0.25 0.30 Upper Lead Width B1 .050 .055 .060 1.27 1.40 1.52 Lower Lead Width B .016 .019 .021 0.41 0.47 0.53 Overall Row Spacing § eB .345 .385 .425 8.76 9.78 10.80 Window Width W1 .130 .140 .150 3.30 3.56 3.81 Window Length W2 .190 .200 .210 4.83 5.08 5.33 * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010  2003 Microchip Technology Inc. DS30235J-page 113

PIC16C62X 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A c L A1 B1 β B p eB Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .890 .898 .905 22.61 22.80 22.99 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top α 5 10 15 5 10 15 Mold Draft Angle Bottom β 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 DS30235J-page 114  2003 Microchip Technology Inc.

PIC16C62X 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45° c A A2 φ β L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .291 .295 .299 7.39 7.49 7.59 Overall Length D .446 .454 .462 11.33 11.53 11.73 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle φ 0 4 8 0 4 8 Lead Thickness c .009 .011 .012 0.23 0.27 0.30 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top α 0 12 15 0 12 15 Mold Draft Angle Bottom β 0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051  2003 Microchip Technology Inc. DS30235J-page 115

PIC16C62X 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 n 1 α c A A2 φ L A1 β Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p .026 0.65 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .322 7.59 7.85 8.18 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .278 .284 .289 7.06 7.20 7.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle φ 0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top α 0 5 10 0 5 10 Mold Draft Angle Bottom β 0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 DS30235J-page 116  2003 Microchip Technology Inc.

PIC16C62X 14.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16C622A XXXXXXXXXXXXXXXXX -04I / P456 AABBCDE 9923CBA 18-Lead SOIC (.300") Example XXXXXXXXXXXX PIC16C622 XXXXXXXXXXXX -04I / S0218 XXXXXXXXXXXX AABBCDE 9918CDK 18-Lead CERDIP Windowed Example XXXXXXXX 16C622 XXXXXXXX /JW AABBCDE 9901CBA 20-Lead SSOP Example XXXXXXXXXX PIC16C622A XXXXXXXXXX -04I / 218 AABBCDE 9951CBP Legend: XX...X Customer specific information* Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2003 Microchip Technology Inc. DS30235J-page 117

PIC16C62X NOTES: DS30235J-page 118  2003 Microchip Technology Inc.

PIC16C62X APPENDIX A: ENHANCEMENTS APPENDIX B: COMPATIBILITY The following are the list of enhancements over the To convert code written for PIC16C5X to PIC16CXX, PIC16C5X microcontroller family: the user should take the following steps: 1. Instruction word length is increased to 14 bits. 1. Remove any program memory page select This allows larger page sizes both in program operations (PA2, PA1, PA0 bits) for CALL, GOTO. memory (4K now as opposed to 512 before) and 2. Revisit any computed jump operations (write to register file (up to 128 bytes now versus 32 PC or add to PC, etc.) to make sure page bits bytes before). are set properly under the new scheme. 2. A PC high latch register (PCLATH) is added to 3. Eliminate any data memory page switching. handle program memory paging. PA2, PA1, PA0 Redefine data variables to reallocate them. bits are removed from STATUS register. 4. Verify all writes to STATUS, OPTION, and FSR 3. Data memory paging is slightly redefined. registers since these have changed. STATUS register is modified. 5. Change RESET vector to 0000h. 4. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out, although they are kept for compatibility with PIC16C5X. 5. OPTION and TRIS registers are made addressable. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8 deep. 8. RESET vector is changed to 0000h. 9. RESET of all registers is revisited. Five different RESET (and wake-up) types are recognized. Registers are reset differently. 10. Wake-up from SLEEP through interrupt is added. 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. PORTB has weak pull-ups and interrupt-on- change feature. 13. Timer0 clock input, T0CKI pin is also a port pin (RA4/T0CKI) and has a TRIS bit. 14. FSR is made a full 8-bit register. 15. “In-circuit programming” is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, VPP, RB6 (clock) and RB7 (data in/out). 16. PCON STATUS register is added with a Power- on-Reset (POR) STATUS bit and a Brown-out Reset STATUS bit (BOD). 17. Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. 18. PORTA inputs are now Schmitt Trigger inputs. 19. Brown-out Reset reset has been added. 20. Common RAM registers F0h-FFh implemented in bank1.  2003 Microchip Technology Inc. DS30235J-page 119

PIC16C62X NOTES: DS30235J-page 120  2003 Microchip Technology Inc.

PIC16C62X INDEX I A I/O Ports.............................................................................25 I/O Programming Considerations.......................................30 ADDLW Instruction.............................................................63 ID Locations........................................................................60 ADDWF Instruction.............................................................63 INCF Instruction..................................................................67 ANDLW Instruction.............................................................63 INCFSZ Instruction.............................................................68 ANDWF Instruction.............................................................63 In-Circuit Serial Programming.............................................60 Architectural Overview..........................................................9 Indirect Addressing, INDF and FSR Registers...................24 Assembler Instruction Flow/Pipelining..................................................12 MPASM Assembler.....................................................75 Instruction Set B ADDLW.......................................................................63 BCF Instruction...................................................................64 ADDWF......................................................................63 Block Diagram ANDLW.......................................................................63 TIMER0.......................................................................31 ANDWF......................................................................63 TMR0/WDT PRESCALER..........................................34 BCF............................................................................64 Brown-Out Detect (BOD)....................................................50 BSF.............................................................................64 BSF Instruction...................................................................64 BTFSC........................................................................64 BTFSC Instruction...............................................................64 BTFSS........................................................................65 BTFSS Instruction...............................................................65 CALL...........................................................................65 C CLRF..........................................................................65 CLRW.........................................................................66 C Compilers CLRWDT....................................................................66 MPLAB C17................................................................76 COMF.........................................................................66 MPLAB C18................................................................76 DECF..........................................................................66 MPLAB C30................................................................76 DECFSZ.....................................................................67 CALL Instruction.................................................................65 GOTO.........................................................................67 Clocking Scheme/Instruction Cycle....................................12 INCF...........................................................................67 CLRF Instruction.................................................................65 INCFSZ.......................................................................68 CLRW Instruction................................................................66 IORLW........................................................................68 CLRWDT Instruction...........................................................66 IORWF........................................................................68 Code Protection..................................................................60 MOVF.........................................................................69 COMF Instruction................................................................66 MOVLW......................................................................68 Comparator Configuration...................................................38 MOVWF......................................................................69 Comparator Interrupts.........................................................41 NOP............................................................................69 Comparator Module............................................................37 OPTION......................................................................69 Comparator Operation........................................................39 RETFIE.......................................................................70 Comparator Reference.......................................................39 RETLW.......................................................................70 Configuration Bits................................................................46 RETURN.....................................................................70 Configuring the Voltage Reference.....................................43 RLF.............................................................................71 Crystal Operation................................................................47 RRF............................................................................71 D SLEEP........................................................................71 Data Memory Organization.................................................14 SUBLW.......................................................................72 DC Characteristics......................................................87, 101 SUBWF.......................................................................72 PIC16C717/770/771...............88, 89, 90, 91, 96, 97, 98 SWAPF.......................................................................73 DECF Instruction.................................................................66 TRIS...........................................................................73 DECFSZ Instruction............................................................67 XORLW......................................................................73 Demonstration Boards XORWF......................................................................73 PICDEM 1...................................................................78 Instruction Set Summary....................................................61 PICDEM 17.................................................................78 INT Interrupt.......................................................................56 PICDEM 18R PIC18C601/801....................................79 INTCON Register................................................................20 PICDEM 2 Plus...........................................................78 Interrupts............................................................................55 PICDEM 3 PIC16C92X...............................................78 IORLW Instruction..............................................................68 PICDEM 4...................................................................78 IORWF Instruction..............................................................68 PICDEM LIN PIC16C43X...........................................79 M PICDEM USB PIC16C7X5..........................................79 MOVF Instruction................................................................69 PICDEM.net Internet/Ethernet....................................78 MOVLW Instruction.............................................................68 Development Support.........................................................75 MOVWF Instruction............................................................69 E MPLAB ASM30 Assembler, Linker, Librarian.....................76 Errata....................................................................................3 MPLAB ICD 2 In-Circuit Debugger.....................................77 Evaluation and Programming Tools....................................79 MPLAB ICE 2000 High Performance Universal External Crystal Oscillator Circuit.......................................48 In-Circuit Emulator..............................................................77 G MPLAB ICE 4000 High Performance Universal In-Circuit Emulator..............................................................77 General purpose Register File............................................14 MPLAB Integrated Development Environment Software....75 GOTO Instruction................................................................67 MPLINK Object Linker/MPLIB Object Librarian..................76  2003 Microchip Technology Inc. DS30235J-page 121

PIC16C62X N V NOP Instruction...................................................................69 Voltage Reference Module.................................................43 O VRCON Register................................................................43 W One-Time-Programmable (OTP) Devices.............................7 OPTION Instruction.............................................................69 Watchdog Timer (WDT)......................................................58 OPTION Register................................................................19 WWW, On-Line Support.......................................................3 Oscillator Configurations.....................................................47 X Oscillator Start-up Timer (OST)..........................................50 XORLW Instruction.............................................................73 P XORWF Instruction.............................................................73 Package Marking Information...........................................117 Packaging Information......................................................113 PCL and PCLATH...............................................................23 PCON Register...................................................................22 PICkit 1 FLASH Starter Kit..................................................79 PICSTART Plus Development Programmer.......................77 PIE1 Register......................................................................21 PIR1 Register......................................................................21 Port RB Interrupt.................................................................56 PORTA................................................................................25 PORTB................................................................................28 Power Control/Status Register (PCON)..............................51 Power-Down Mode (SLEEP)...............................................59 Power-On Reset (POR)......................................................50 Power-up Timer (PWRT).....................................................50 Prescaler.............................................................................34 PRO MATE II Universal Device Programmer.....................77 Program Memory Organization...........................................13 Q Quick-Turnaround-Production (QTP) Devices......................7 R RC Oscillator.......................................................................48 Reset...................................................................................49 RETFIE Instruction..............................................................70 RETLW Instruction..............................................................70 RETURN Instruction............................................................70 RLF Instruction....................................................................71 RRF Instruction...................................................................71 S Serialized Quick-Turnaround-Production (SQTP) Devices...7 SLEEP Instruction...............................................................71 Software Simulator (MPLAB SIM).......................................76 Software Simulator (MPLAB SIM30)...................................76 Special Features of the CPU...............................................45 Special Function Registers.................................................17 Stack...................................................................................23 Status Register....................................................................18 SUBLW Instruction..............................................................72 SUBWF Instruction..............................................................72 SWAPF Instruction..............................................................73 T Timer0 TIMER0.......................................................................31 TIMER0 (TMR0) Interrupt...........................................31 TIMER0 (TMR0) Module.............................................31 TMR0 with External Clock...........................................33 Timer1 Switching Prescaler Assignment.................................35 Timing Diagrams and Specifications.................................104 TMR0 Interrupt....................................................................56 TRIS Instruction..................................................................73 TRISA..................................................................................25 TRISB..................................................................................28 DS30235J-page 122  2003 Microchip Technology Inc.

PIC16C62X ON-LINE SUPPORT SYSTEMS INFORMATION AND UPGRADE HOT LINE Microchip provides on-line support on the Microchip World Wide Web site. The Systems Information and Upgrade Line provides The web site is used by Microchip as a means to make system users a listing of the latest versions of all of files and information easily available to customers. To Microchip's development systems software products. view the site, the user must have access to the Internet Plus, this line provides information on how customers and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits.The Hot Line Internet Explorer. Files are also available for FTP Numbers are: download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and Connecting to the Microchip Internet Web 1-480-792-7302 for the rest of the world. Site The Microchip web site is available at the following URL: 092002 www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: (cid:127) Latest Microchip Press Releases (cid:127) Technical Support Section with Frequently Asked Questions (cid:127) Design Tips (cid:127) Device Errata (cid:127) Job Postings (cid:127) Microchip Consultant Program Member Listing (cid:127) Links to other useful web sites related to Microchip Products (cid:127) Conferences for products, Development Systems, technical information and more (cid:127) Listing of seminars and events  2003 Microchip Technology Inc. DS30235J-page 123

PIC16C62X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16C62X Literature Number: DS30235J Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS30235J-page 124  2003 Microchip Technology Inc.

PIC16C62X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XX X /XX XXX Examples: Device Frequency Temperature Package Pattern a) PIC16C621A - 04/P 301 = Commercial temp., Range Range PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. b) PIC16LC622- 04I/SO = Industrial temp., SOIC Device PIC16C62X: VDD range 3.0V to 6.0V package, 200kHz, extended VDD limits. PIC16C62XT: VDD range 3.0V to 6.0V (Tape and Reel) PIC16C62XA: VDD range 3.0V to 5.5V PIC16C62XAT: VDD range 3.0V to 5.5V (Tape and Reel) PIC16LC62X: VDD range 2.5V to 6.0V PIC16LC62XT: VDD range 2.5V to 6.0V (Tape and Reel) PIC16LC62XA: VDD range 2.5V to 5.5V PIC16LC62XAT: VDD range 2.5V to 5.5V (Tape and Reel) PIC16CR620A: VDD range 2.5V to 5.5V PIC16CR620AT: VDD range 2.5V to 5.5V (Tape and Reel) PIC16LCR620A: VDD range 2.0V to 5.5V PIC16LCR620AT: VDD range 2.0V to 5.5V (Tape and Reel) Frequency Range 04 200kHz (LP osc) 04 4MHz (XT and RC osc) 20 20MHz (HS osc) Temperature Range - = 0°C to +70°C I = -40°C to +85°C E = -40°C to +125°C Package P = PDIP SO = SOIC (Gull Wing, 300 mil body) SS = SSOP (209 mil) JW* = Windowed CERDIP Pattern 3-Digit Pattern Code for QTP (blank otherwise) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. DS30235J-page 125

W S S ORLDWIDE ALES AND ERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia Microchip Technology Japan K.K. Benex S-1 6F 2355 West Chandler Blvd. Microchip Technology Australia Pty Ltd 3-18-20, Shinyokohama Chandler, AZ 85224-6199 Marketing Support Division Kohoku-Ku, Yokohama-shi Tel: 480-792-7200 Fax: 480-792-7277 Suite 22, 41 Rawson Street Kanagawa, 222-0033, Japan Technical Support: 480-792-7627 Epping 2121, NSW Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Web Address: http://www.microchip.com Australia Korea Atlanta Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Microchip Technology Korea 3780 Mansell Road, Suite 130 168-1, Youngbo Bldg. 3 Floor Alpharetta, GA 30022 Microchip Technology Consulting (Shanghai) Samsung-Dong, Kangnam-Ku Tel: 770-640-0034 Fax: 770-640-0307 Co., Ltd., Beijing Liaison Office Seoul, Korea 135-882 Unit 915 Boston Tel: 82-2-554-7200 Fax: 82-2-558-5934 Bei Hai Wan Tai Bldg. 2 Lan Drive, Suite 120 No. 6 Chaoyangmen Beidajie Singapore Westford, MA 01886 Beijing, 100027, No. China Microchip Technology Singapore Pte Ltd. Tel: 978-692-3848 Fax: 978-692-3821 Tel: 86-10-85282100 Fax: 86-10-85282104 200 Middle Road Chicago China - Chengdu #07-02 Prime Centre Singapore, 188980 333 Pierce Road, Suite 180 Microchip Technology Consulting (Shanghai) Tel: 65-6334-8870 Fax: 65-6334-8850 Itasca, IL 60143 Co., Ltd., Chengdu Liaison Office Taiwan Tel: 630-285-0071 Fax: 630-285-0075 Rm. 2401-2402, 24th Floor, Microchip Technology (Barbados) Inc., Dallas Ming Xing Financial Tower Taiwan Branch No. 88 TIDU Street 4570 Westgrove Drive, Suite 160 11F-3, No. 207 Chengdu 610016, China Addison, TX 75001 Tung Hua North Road Tel: 86-28-86766200 Fax: 86-28-86766599 Tel: 972-818-7423 Fax: 972-818-2924 Taipei, 105, Taiwan China - Fuzhou Detroit Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Microchip Technology Consulting (Shanghai) Tri-Atria Office Building Co., Ltd., Fuzhou Liaison Office EUROPE 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Unit 28F, World Trade Plaza Austria No. 71 Wusi Road Tel: 248-538-2250 Fax: 248-538-2260 Microchip Technology Austria GmbH Fuzhou 350001, China Kokomo Tel: 86-591-7503506 Fax: 86-591-7503521 Durisolstrasse 2 A-4600 Wels 2767 S. Albright Road China - Hong Kong SAR Austria Kokomo, Indiana 46902 Microchip Technology Hongkong Ltd. Tel: 43-7242-2244-399 Tel: 765-864-8360 Fax: 765-864-8387 Unit 901-6, Tower 2, Metroplaza Fax: 43-7242-2244-393 Los Angeles 223 Hing Fong Road Denmark 18201 Von Karman, Suite 1090 Kwai Fong, N.T., Hong Kong Microchip Technology Nordic ApS Irvine, CA 92612 Tel: 852-2401-1200 Fax: 852-2401-3431 Regus Business Centre Tel: 949-263-1888 Fax: 949-263-1338 China - Shanghai Lautrup hoj 1-3 Phoenix Microchip Technology Consulting (Shanghai) Ballerup DK-2750 Denmark Co., Ltd. Tel: 45 4420 9895 Fax: 45 4420 9910 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Room 701, Bldg. B France Far East International Plaza Tel: 480-792-7966 Fax: 480-792-4338 Microchip Technology SARL No. 317 Xian Xia Road Parc d’Activite du Moulin de Massy San Jose Shanghai, 200051 43 Rue du Saule Trapu Microchip Technology Inc. Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Batiment A - ler Etage 2107 North First Street, Suite 590 China - Shenzhen 91300 Massy, France San Jose, CA 95131 Microchip Technology Consulting (Shanghai) Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Tel: 408-436-7950 Fax: 408-436-7955 Co., Ltd., Shenzhen Liaison Office Germany Toronto Rm. 1812, 18/F, Building A, United Plaza Microchip Technology GmbH 6285 Northam Drive, Suite 108 No. 5022 Binhe Road, Futian District Steinheilstrasse 10 Mississauga, Ontario L4V 1X5, Canada Shenzhen 518033, China D-85737 Ismaning, Germany Tel: 905-673-0699 Fax: 905-673-6509 Tel: 86-755-82901380 Fax: 86-755-82966626 Tel: 49-89-627-144-0 China - Qingdao Fax: 49-89-627-144-44 Rm. B505A, Fullhope Plaza, Italy No. 12 Hong Kong Central Rd. Microchip Technology SRL Qingdao 266071, China Via Quasimodo, 12 Tel: 86-532-5027355 Fax: 86-532-5027205 20025 Legnano (MI) India Milan, Italy Microchip Technology Inc. Tel: 39-0331-742611 Fax: 39-0331-466781 India Liaison Office United Kingdom Marketing Support Division Microchip Ltd. Divyasree Chambers 505 Eskdale Road 1 Floor, Wing A (A3/A4) Winnersh Triangle No. 11, O’Shaugnessey Road Wokingham Bangalore, 560 025, India Berkshire, England RG41 5TU Tel: 91-80-2290061 Fax: 91-80-2290062 Tel: 44 118 921 5869 Fax: 44-118 921-5820 03/25/03 DS30235J-page 126  2003 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16C621AT-20E/SO PIC16C622AT-20I/SO PIC16C622AT-20I/SS PIC16C621AT-20E/SS PIC16LC621A-04E/SS PIC16LC621A-04E/SO PIC16C620A-20I/SS PIC16C620A-20I/SO PIC16LC621AT-04E/SS PIC16LC621AT-04E/SO PIC16C620AT-04I/SS PIC16C620AT-04I/SO PIC16C620A/JW PIC16C621A-20/SS PIC16C622A-20/SS PIC16LC620A-04E/SO PIC16C620AT-04E/SO PIC16C620AT-04E/SS PIC16LC620A-04E/SS PIC16LC620T-04E/SS PIC16LC620T-04E/SO PIC16C622-04/SS PIC16C620-04/SS PIC16C622-04/SO PIC16C620-04/SO PIC16C622T- 04/SS PIC16C622T-04/SO PIC16C620T-04/SS PIC16C621T-04I/SS PIC16C621T-04/SO PIC16C621T-04/SS PIC16C622AT-20/SS PIC16C621A-04I/SO PIC16C621A-04I/SS PIC16C621AT-04I/SS PIC16C622AT-04E/SO PIC16C622A-20I/SO PIC16C622A-20I/SS PIC16C620T-04E/SO PIC16C620T-04E/SS PIC16C621AT-04E/SS PIC16C621AT-04E/SO PIC16C621AT-04/SO PIC16C621T-20/SS PIC16C621T-20/SO PIC16C621-20/SO PIC16C622-20/SS PIC16LC620A-04/P PIC16LC622A-04/P PIC16LC621A-04/P PIC16LC620-04I/SS PIC16LC620- 04I/SO PIC16LC621-04I/SO PIC16C621-04E/P PIC16C620-04E/P PIC16LC620T-04I/SS PIC16C620AT-20E/SS PIC16C620AT-20E/SO PIC16LC622AT-04/SS PIC16C620AT-20/SS PIC16LC621AT-04/SS PIC16LC621AT-04/SO PIC16C620T-04I/SS PIC16C620T-04I/SO PIC16LC622-04I/P PIC16LC621-04I/P PIC16C622T-04I/SO PIC16C622T- 04I/SS PIC16LC620AT-04E/SO PIC16LC620AT-04E/SS PIC16LC621-04/P PIC16C620AT-40/SS PIC16C620AT- 40/SO PIC16LC620A-04I/P PIC16LC622A-04I/P PIC16LC620-04/SS PIC16LC622-04/SS PIC16LC622-04/SO PIC16C620T-20I/SS PIC16C620T-20I/SO PIC16C620AT-04/SO PIC16LC622-04E/P PIC16LC620-04E/P PIC16LC621-04E/P PIC16C622A-20E/P PIC16C620A-20E/P PIC16C621A-20E/P PIC16LC621T-04I/SS PIC16LC621A-04I/SO PIC16LC621A-04I/SS PIC16LC621T-04I/SO PIC16C620/JW PIC16LC620-04E/SS PIC16LC621-04E/SS PIC16C620A-20/P PIC16LC621-04E/SO PIC16LC622-04E/SO PIC16LC622-04E/SS PIC16LC620-04E/SO PIC16C622A-20E/SO