PIC16C5X EPROM/ROM-Based 8-bit CMOS Microcontroller Series Devices Included in this Data Sheet: • 12-bit wide instructions • 8-bit wide data path • PIC16C54 • Seven or eight special function hardware registers • PIC16CR54 • Two-level deep hardware stack • PIC16C55 • Direct, indirect and relative addressing modes for • PIC16C56 data and instructions • PIC16CR56 • PIC16C57 Peripheral Features: • PIC16CR57 • 8-bit real time clock/counter (TMR0) with 8-bit • PIC16C58 programmable prescaler • PIC16CR58 • Power-on Reset (POR) Note: PIC16C5X refers to all revisions of the part • Device Reset Timer (DRT) (i.e., PIC16C54 refers to PIC16C54, • Watchdog Timer (WDT) with its own on-chip PIC16C54A, and PIC16C54C), unless RC oscillator for reliable operation specifically called out otherwise. • Programmable Code Protection High-Performance RISC CPU: • Power saving SLEEP mode • Selectable oscillator options: • Only 33 single word instructions to learn - RC: Low cost RC oscillator • All instructions are single cycle except for pro- - XT: Standard crystal/resonator gram branches which are two-cycle - HS: High speed crystal/resonator • Operating speed: DC - 40 MHz clock input - LP: Power saving, low frequency crystal DC - 100ns instruction cycle EPROM/ CMOS Technology: Device Pins I/O RAM ROM • Low power, high speed CMOS EPROM/ROM tech- PIC16C54 18 12 512 25 nology PIC16C54A 18 12 512 25 • Fully static design PIC16C54C 18 12 512 25 • Wide operating voltage and temperature range: PIC16CR54A 18 12 512 25 - EPROM Commercial/Industrial 2.0V to 6.25V PIC16CR54C 18 12 512 25 - ROM Commercial/Industrial 2.0V to 6.25V PIC16C55 28 20 512 24 - EPROM Extended 2.5V to 6.0V PIC16C55A 28 20 512 24 - ROM Extended 2.5V to 6.0V PIC16C56 18 12 1K 25 • Low power consumption PIC16C56A 18 12 1K 25 - < 2 mA typical @ 5V, 4 MHz PIC16CR56A 18 12 1K 25 - 15 A typical @ 3V, 32 kHz PIC16C57 28 20 2K 72 - < 0.6 A typical standby current PIC16C57C 28 20 2K 72 (with WDT disabled) @ 3V, 0C to 70C PIC16CR57C 28 20 2K 72 PIC16C58B 18 12 2K 73 Note: In this document, figure and table titles PIC16CR58B 18 12 2K 73 refer to all varieties of the part number indi- cated, (i.e., The title “Figure15-1: Load Conditions For Device Timing Specifica- tions - PIC16C54A”, also refers to PIC16LC54A and PIC16LV54A parts), unless specifically called out otherwise. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 1

PIC16C5X Pin Diagrams PDIP, SOIC, Windowed CERDIP PDIP, SOIC, Windowed CERDIP RA2 1 18 RA1 T0CKI •1 28 MCLR/VPP RA3 2 PPPPPP 17 RA0 VDD 2 27 OSC1/CLKIN MCLTR0/RVVCBPSK0PSI 3456 IC16CR5IC16C58IC16CR5IC16C56IC16CR5IC16C54 11116543 OOVRDBSSD7CC12//CCLLKKIONUT NVNS//CCS 345 PPP 222654 ORRCCS76C2/CLKOUT RB1 7 8 6 4 12 RB6 RA0 6 ICICIC 23 RC5 RB2 8 11 RB5 RA1 7 161616 22 RC4 CCC RB3 9 10 RB4 RA2 8 R55 21 RC3 575 RA3 9 7 20 RC2 RB0 10 19 RC1 RB1 11 18 RC0 RB2 12 17 RB7 RB3 13 16 RB6 RB4 14 15 RB5 SSOP SSOP RA2 1 20 RA1 VSS 1 28 MCLR/VPP RA3 2 19 RA0 T0CKI 2 27 OSC1/CLKIN VDD 3 26 OSC2/CLKOUT T0CKI 3 PPPPPP 18 OSC1/CLKIN VDD 4 25 RC7 MCLR/RRVVVBBPSS01PSS 45678 IC16CR58IC16C58IC16CR56IC16C56IC16CR54IC16C54 1111176543 OVVRRDDBBSDD76C2/CLKOUT RRRRRRAAAABB012301 5678910 PIC16CR57 PIC16C57 PIC16C55 222221432109 RRRRRRCCCCCC654321 RB2 9 12 RB5 RB2 11 18 RC0 RB3 10 11 RB4 RB3 12 17 RB7 RB4 13 16 RB6 VSS 14 15 RB5 Device Differences Oscillator Process Voltage ROM MCLR Device Selection Oscillator Technology Range Equivalent Filter (Program) (Microns) PIC16C54 2.5-6.25 Factory See Note 1 1.2 PIC16CR54A No PIC16C54A 2.0-6.25 User See Note 1 0.9 — No PIC16C54C 2.5-5.5 User See Note 1 0.7 PIC16CR54C Yes PIC16C55 2.5-6.25 Factory See Note 1 1.7 — No PIC16C55A 2.5-5.5 User See Note 1 0.7 — Yes PIC16C56 2.5-6.25 Factory See Note 1 1.7 — No PIC16C56A 2.5-5.5 User See Note 1 0.7 PIC16CR56A Yes PIC16C57 2.5-6.25 Factory See Note 1 1.2 — No PIC16C57C 2.5-5.5 User See Note 1 0.7 PIC16CR57C Yes PIC16C58B 2.5-5.5 User See Note 1 0.7 PIC16CR58B Yes PIC16CR54A 2.5-6.25 Factory See Note 1 1.2 N/A Yes PIC16CR54C 2.5-5.5 Factory See Note 1 0.7 N/A Yes PIC16CR56A 2.5-5.5 Factory See Note 1 0.7 N/A Yes PIC16CR57C 2.5-5.5 Factory See Note 1 0.7 N/A Yes PIC16CR58B 2.5-5.5 Factory See Note 1 0.7 N/A Yes Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. Note: The table shown above shows the generic names of the PIC16C5X devices. For device varieties, please refer to Section2.0. Preliminary DS30453E-page 2  1997-2013 Microchip Technology Inc.

PIC16C5X Table of Contents 1.0 General Description......................................................................................................................................................................5 2.0 PIC16C5X Device Varieties.........................................................................................................................................................7 3.0 Architectural Overview ................................................................................................................................................................9 4.0 Oscillator Configurations............................................................................................................................................................15 5.0 Reset..........................................................................................................................................................................................19 6.0 Memory Organization.................................................................................................................................................................25 7.0 I/O Ports.....................................................................................................................................................................................35 8.0 Timer0 Module and TMR0 Register...........................................................................................................................................37 9.0 Special Features of the CPU......................................................................................................................................................43 10.0 Instruction Set Summary............................................................................................................................................................49 11.0 Development Support.................................................................................................................................................................61 12.0 Electrical Characteristics - PIC16C54/55/56/57.........................................................................................................................67 13.0 Electrical Characteristics - PIC16CR54A...................................................................................................................................79 14.0 Device Characterization - PIC16C54/55/56/57/CR54A..............................................................................................................91 15.0 Electrical Characteristics - PIC16C54A....................................................................................................................................103 16.0 Device Characterization - PIC16C54A.....................................................................................................................................117 17.0 Electrical Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ........................................131 18.0 Device Characterization - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B..........................................145 19.0 Electrical Characteristics - PIC16C54C/C55A/C56A/C57C/C58B 40MHz...............................................................................155 20.0 Device Characterization - PIC16C54C/C55A/C56A/C57C/C58B 40MHz................................................................................165 21.0 Packaging Information..............................................................................................................................................................171 Appendix A: Compatibility .............................................................................................................................................................182 On-Line Support.................................................................................................................................................................................187 Reader Response..............................................................................................................................................................................188 Product Identification System............................................................................................................................................................189 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 3

PIC16C5X NOTES: Preliminary DS30453E-page 4  1997-2013 Microchip Technology Inc.

PIC16C5X 8-Bit EPROM/ROM-Based CMOS Microcontrollers 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC16C5X from Microchip Technology is a family The PIC16C5X series fits perfectly in applications rang- of low cost, high performance, 8-bit fully static, ing from high speed automotive and appliance motor EPROM/ROM-based CMOS microcontrollers. It control to low power remote transmitters/receivers, employs a RISC architecture with only 33 single word/ pointing devices and telecom processors. The EPROM single cycle instructions. All instructions are single technology makes customizing application programs cycle except for program branches which take two (transmitter codes, motor speeds, receiver frequen- cycles. The PIC16C5X delivers performance in an cies, etc.) extremely fast and convenient. The small order of magnitude higher than its competitors in the footprint packages, for through hole or surface mount- same price category. The 12-bit wide instructions are ing, make this microcontroller series perfect for applica- highly symmetrical resulting in 2:1 code compression tions with space limitations. Low cost, low power, high over other 8-bit microcontrollers in its class. The easy performance ease of use and I/O flexibility make the to use and easy to remember instruction set reduces PIC16C5X series very versatile even in areas where no development time significantly. microcontroller use has been considered before (e.g., timer functions, replacement of “glue” logic in larger The PIC16C5X products are equipped with special fea- systems, co-processor applications). tures that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external RESET circuitry. There are four oscillator configurations to choose from, including the power saving LP (Low Power) oscillator and cost saving RC oscillator. Power saving SLEEP mode, Watchdog Timer and Code Protection features improve system cost, power and reliability. The UV erasable CERDIP packaged versions are ideal for code development, while the cost effective One Time Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in OTP microcontrollers, while benefiting from the OTP’s flexibility. The PIC16C5X products are supported by a full fea- tured macro assembler, a software simulator, an in-cir- cuit emulator, a low cost development programmer and a full featured programmer. All the tools are supported on IBM PC and compatible machines. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 5

PIC16C5X TABLE 1-1: PIC16C5X FAMILY OF DEVICES Features PIC16C54 PIC16CR54 PIC16C55 PIC16C56 PIC16CR56 Maximum Operation Frequency 40 MHz 20 MHz 40 MHz 40 MHz 20 MHz EPROM Program Memory (x12 words) 512 — 512 1K — ROM Program Memory (x12 words) — 512 — — 1K RAM Data Memory (bytes) 25 25 24 25 25 Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 I/O Pins 12 12 20 12 12 Number of Instructions 33 33 33 33 33 Packages 18-pin DIP, 18-pin DIP, 28-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC; SOIC; SOIC; SOIC; 20-pin SSOP 20-pin SSOP 28-pin SSOP 20-pin SSOP 20-pin SSOP All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability. Features PIC16C57 PIC16CR57 PIC16C58 PIC16CR58 Maximum Operation Frequency 40 MHz 20 MHz 40 MHz 20 MHz EPROM Program Memory (x12 words) 2K — 2K — ROM Program Memory (x12 words) — 2K — 2K RAM Data Memory (bytes) 72 72 73 73 Timer Module(s) TMR0 TMR0 TMR0 TMR0 I/O Pins 20 20 12 12 Number of Instructions 33 33 33 33 Packages 28-pin DIP, SOIC; 28-pin DIP, SOIC; 18-pin DIP, SOIC; 18-pin DIP, SOIC; 28-pin SSOP 28-pin SSOP 20-pin SSOP 20-pin SSOP All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability. Preliminary DS30453E-page 6  1997-2013 Microchip Technology Inc.

PIC16C5X 2.0 PIC16C5X DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP) Devices A variety of frequency ranges and packaging options are available. Depending on application and production Microchip offers a QTP Programming Service for fac- requirements, the proper device option can be selected tory production orders. This service is made available using the information in this section. When placing for users who choose not to program a medium to high orders, please use the PIC16C5X Product Identifica- quantity of units and whose code patterns have stabi- tion System at the back of this data sheet to specify the lized. The devices are identical to the OTP devices but correct part number. with all EPROM locations and configuration bit options already programmed by the factory. Certain code and For the PIC16C5X family of devices, there are four device types, as indicated in the device number: prototype verification procedures apply before produc- tion shipments are available. Please contact your 1. C, as in PIC16C54C. These devices have Microchip Technology sales office for more details. EPROM program memory and operate over the standard voltage range. 2.4 Serialized Quick-Turnaround- 2. LC, as in PIC16LC54A. These devices have Production (SQTPSM) Devices EPROM program memory and operate over an extended voltage range. Microchip offers the unique programming service where a few user defined locations in each device are 3. CR, as in PIC16CR54A. These devices have programmed with different serial numbers. The serial ROM program memory and operate over the numbers may be random, pseudo-random or sequen- standard voltage range. tial. The devices are identical to the OTP devices but 4. LCR, as in PIC16LCR54A. These devices have with all EPROM locations and configuration bit options ROM program memory and operate over an already programmed by the factory. extended voltage range. Serial programming allows each device to have a 2.1 UV Erasable Devices (EPROM) unique number which can serve as an entry code, password or ID number. The UV erasable versions offered in CERDIP pack- ages, are optimal for prototype development and pilot 2.5 Read Only Memory (ROM) Devices programs. Microchip offers masked ROM versions of several of UV erasable devices can be programmed for any of the the highest volume parts, giving the customer a low four oscillator configurations. Microchip's PICSTART Plus(1) and PRO MATE programmers cost option for high volume, mature products. both support programming of the PIC16C5X. Third party programmers also are available. Refer to the Third Party Guide (DS00104) for a list of sources. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers expecting frequent code changes and updates, or small volume applications. The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must be pro- grammed. Note 1: PIC16LC54C and PIC16C54A devices require OSC2 not to be connected while programming with PICSTART® Plus programmer. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 7

PIC16C5X NOTES: Preliminary DS30453E-page 8  1997-2013 Microchip Technology Inc.

PIC16C5X 3.0 ARCHITECTURAL OVERVIEW The PIC16C5X device contains an 8-bit ALU and work- ing register. The ALU is a general purpose arithmetic The high performance of the PIC16C5X family can be unit. It performs arithmetic and Boolean functions attributed to a number of architectural features com- between data in the working register and any register monly found in RISC microprocessors. To begin with, file. the PIC16C5X uses a Harvard architecture in which The ALU is 8 bits wide and capable of addition, subtrac- program and data are accessed on separate buses. tion, shift and logical operations. Unless otherwise This improves bandwidth over traditional von Neumann mentioned, arithmetic operations are two's comple- architecture where program and data are fetched on ment in nature. In two-operand instructions, typically the same bus. Separating program and data memory one operand is the W (working) register. The other further allows instructions to be sized differently than operand is either a file register or an immediate con- the 8-bit wide data word. Instruction opcodes are 12 stant. In single operand instructions, the operand is bits wide making it possible to have all single word either the W register or a file register. instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two- The W register is an 8-bit working register used for ALU stage pipeline overlaps fetch and execution of instruc- operations. It is not an addressable register. tions. Consequently, all instructions (33) execute in a Depending on the instruction executed, the ALU may single cycle except for program branches. affect the values of the Carry (C), Digit Carry (DC), and The PIC16C54/CR54 and PIC16C55 address 512x12 Zero (Z) bits in the STATUS register. The C and DC bits of program memory, the PIC16C56/CR56 address operate as a borrow and digit borrow out bit, respec- 1Kx12 of program memory, and the PIC16C57/CR57 tively, in subtraction. See the SUBWF and ADDWF and PIC16C58/CR58 address 2Kx12 of program instructions for examples. memory. All program memory is internal. A simplified block diagram is shown in Figure3-1, with The PIC16C5X can directly or indirectly address its the corresponding device pins described in Table3-1 register files and data memory. All special function reg- (for PIC16C54/56/58) and Table3-2 (for PIC16C55/ isters including the program counter are mapped in the 57). data memory. The PIC16C5X has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16C5X simple yet efficient. In addition, the learning curve is reduced significantly. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 9

PIC16C5X FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM EPROM/ROM 9-11 9-11 STACK 1 TP0CINKI CONFIGURATION WORD OSC1 OSC2 MCLR 512 X 12 TO STACK 2 “DISABLE” “OSC 2048 X 12 PC SELECT” 12 WATCHDOG 2 TIMER “CODE PROTECT” OSCILLATOR/ INSTRUCTION TIMING & REGISTER CONTROL 9 WDT TIME WDT/TMR0 CLKOUT 12 OUT PRESCALER 8 “SLEEP” INSTRUCTION 6 DECODER OPTION REG. “OPTION” DIRECT ADDRESS DIRECT RAM FROM W GENERAL ADDRESS PURPOSE 5 REGISTER FILE 8 5-7 (SRAM) 24, 25, 72 or S L STATUS 73 Bytes A R TMR0 FSR E T LI 8 DATA BUS W ALU 8 FROM W FROM W FROM W 4 8 8 4 8 8 “TRIS 5” “TRIS 6” “TRIS 7” TRISA PORTA TRISB PORTB TRISC PORTC 4 8 8 RA<3:0> RB<7:0> RC<7:0> (28-Pin Devices Only) Preliminary DS30453E-page 10  1997-2013 Microchip Technology Inc.

PIC16C5X TABLE 3-1: PINOUT DESCRIPTION - PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58, PIC16CR58 Pin Number Pin Buffer Pin Name Description DIP SOIC SSOP Type Type RA0 17 17 19 I/O TTL Bi-directional I/O port RA1 18 18 20 I/O TTL RA2 1 1 1 I/O TTL RA3 2 2 2 I/O TTL RB0 6 6 7 I/O TTL Bi-directional I/O port RB1 7 7 8 I/O TTL RB2 8 8 9 I/O TTL RB3 9 9 10 I/O TTL RB4 10 10 11 I/O TTL RB5 11 11 12 I/O TTL RB6 12 12 13 I/O TTL RB7 13 13 14 I/O TTL T0CKI 3 3 3 I ST Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR/VPP 4 4 4 I ST Master clear (RESET) input/programming voltage input. This pin is an active low RESET to the device. Voltage on the MCLR/VPP pin must not exceed VDD to avoid unin- tended entering of Programming mode. OSC1/CLKIN 16 16 18 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 15 17 O — Oscillator crystal output. Connects to crystal or resonator in crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. VDD 14 14 15,16 P — Positive supply for logic and I/O pins. VSS 5 5 5,6 P — Ground reference for logic and I/O pins. Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 11

PIC16C5X TABLE 3-2: PINOUT DESCRIPTION - PIC16C55, PIC16C57, PIC16CR57 Pin Number Pin Buffer Pin Name Description Type Type DIP SOIC SSOP RA0 6 6 5 I/O TTL Bi-directional I/O port RA1 7 7 6 I/O TTL RA2 8 8 7 I/O TTL RA3 9 9 8 I/O TTL RB0 10 10 9 I/O TTL Bi-directional I/O port RB1 11 11 10 I/O TTL RB2 12 12 11 I/O TTL RB3 13 13 12 I/O TTL RB4 14 14 13 I/O TTL RB5 15 15 15 I/O TTL RB6 16 16 16 I/O TTL RB7 17 17 17 I/O TTL RC0 18 18 18 I/O TTL Bi-directional I/O port RC1 19 19 19 I/O TTL RC2 20 20 20 I/O TTL RC3 21 21 21 I/O TTL RC4 22 22 22 I/O TTL RC5 23 23 23 I/O TTL RC6 24 24 24 I/O TTL RC7 25 25 25 I/O TTL T0CKI 1 1 2 I ST Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to reduce current consumption. MCLR 28 28 28 I ST Master clear (RESET) input. This pin is an active low RESET to the device. OSC1/CLKIN 27 27 27 I ST Oscillator crystal input/external clock source input. OSC2/CLKOUT 26 26 26 O — Oscillator crystal output. Connects to crystal or resonator in crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. VDD 2 2 3,4 P — Positive supply for logic and I/O pins. VSS 4 4 1,14 P — Ground reference for logic and I/O pins. N/C 3,5 3,5 — — — Unused, do not connect. Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input Preliminary DS30453E-page 12  1997-2013 Microchip Technology Inc.

PIC16C5X 3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining Cycle An Instruction Cycle consists of four Q cycles (Q1, Q2, The clock input (OSC1/CLKIN pin) is internally divided Q3 and Q4). The instruction fetch and execute are by four to generate four non-overlapping quadrature pipelined such that fetch takes one instruction cycle, clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro- while decode and execute takes another instruction gram counter is incremented every Q1 and the instruc- cycle. However, due to the pipelining, each instruction tion is fetched from program memory and latched into effectively executes in one cycle. If an instruction the instruction register in Q4. It is decoded and exe- causes the program counter to change (e.g., GOTO), cuted during the following Q1 through Q4. The clocks then two cycles are required to complete the instruction and instruction execution flow are shown in Figure3-2 (Example3-1). and Example3-1. A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register in cycle Q1. This instruc- tion is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (oper- and read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW H'55' Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 13

PIC16C5X NOTES: Preliminary DS30453E-page 14  1997-2013 Microchip Technology Inc.

PIC16C5X 4.0 OSCILLATOR FIGURE 4-2: EXTERNAL CLOCK INPUT CONFIGURATIONS OPERATION (HS, XT OR LP OSC 4.1 Oscillator Types CONFIGURATION) PIC16C5Xs can be operated in four different oscillator Clock from modes. The user can program two configuration bits OSC1 ext. system (FOSC1:FOSC0) to select one of these four modes: PIC16C5X 1. LP: Low Power Crystal Open OSC2 2. XT: Crystal/Resonator 3. HS: High Speed Crystal/Resonator 4. RC: Resistor/Capacitor TABLE 4-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC16C5X, PIC16CR5X Note: Not all oscillator selections available for all parts. See Section9.1. Osc Resonator Cap. Range Cap. Range Type Freq C1 C2 4.2 Crystal Oscillator/Ceramic XT 455 kHz 68-100 pF 68-100 pF Resonators 2.0 MHz 15-33 pF 15-33 pF 4.0 MHz 10-22 pF 10-22 pF In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT HS 8.0 MHz 10-22 pF 10-22 pF pins to establish oscillation (Figure4-1). The 16.0 MHz 10 pF 10 pF PIC16C5X oscillator design requires the use of a paral- These values are for design guidance only. Since lel cut crystal. Use of a series cut crystal may give a fre- each resonator has its own characteristics, the user quency out of the crystal manufacturers specifications. should consult the resonator manufacturer for When in XT, LP or HS modes, the device can have an appropriate values of external components. external clock source drive the OSC1/CLKIN pin (Figure4-2). TABLE 4-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - FIGURE 4-1: CRYSTAL/CERAMIC PIC16C5X, PIC16CR5X RESONATOR OPERATION Osc Crystal Cap.Range Cap. Range (HS, XT OR LP OSC Type Freq C1 C2 CONFIGURATION) LP 32 kHz(1) 15 pF 15 pF C1(1) OSC1 PIC16C5X XT 100 kHz 15-30 pF 200-300 pF 200 kHz 15-30 pF 100-200 pF SLEEP 455 kHz 15-30 pF 15-100 pF XTAL RF(3) 1 MHz 15-30 pF 15-30 pF To internal 2 MHz 15 pF 15 pF logic OSC2 4 MHz 15 pF 15 pF RS(2) C2(1) HS 4 MHz 15 pF 15 pF 8 MHz 15 pF 15 pF Note 1: See Capacitor Selection tables for 20 MHz 15 pF 15 pF recommended values of C1 and C2. Note 1: For VDD > 4.5V, C1 = C2  30 pF is 2: A series resistor (RS) may be required recommended. for AT strip cut crystals. These values are for design guidance only. Rs may 3: RF varies with the Oscillator mode cho- be required in HS mode as well as XT mode to avoid sen (approx. value = 10 M). overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Note: If you change from this device to another device, please verify oscillator characteris- tics in your application. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 15

PIC16C5X 4.3 External Crystal Oscillator Circuit Figure4-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental fre- Either a prepackaged oscillator or a simple oscillator quency of the crystal. The inverter performs a 180- circuit with TTL gates can be used as an external crys- degree phase shift in a series resonant oscillator cir- tal oscillator circuit. Prepackaged oscillators provide a cuit. The 330k resistors provide the negative feed- wide operating range and better stability. A well- back to bias the inverters in their linear region. designed crystal oscillator will provide good perfor- mance with TTL gates. Two types of crystal oscillator FIGURE 4-4: EXAMPLE OF EXTERNAL circuits can be used: one with parallel resonance, or SERIES RESONANT one with series resonance. CRYSTAL OSCILLATOR Figure4-3 shows an implementation example of a par- CIRCUIT (USING XT, HS allel resonant oscillator circuit. The circuit is designed OR LP OSCILLATOR to use the fundamental frequency of the crystal. The MODE) 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor To Other provides the negative feedback for stability. The 10k 330K 330K Devices potentiometers bias the 74AS04 in the linear region. 74AS04 74AS04 74AS04 PIC16C5X This circuit could be used for external oscillator CLKIN designs. 0.1 F Open OSC2 XTAL FIGURE 4-3: EXAMPLE OF EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE) +5V To Other Devices 10K 4.7K 74AS04 PIC16C5X 74AS04 CLKIN Open OSC2 10K XTAL 10K 20 pF 20 pF Preliminary DS30453E-page 16  1997-2013 Microchip Technology Inc.

PIC16C5X 4.4 RC Oscillator FIGURE 4-5: RC OSCILLATOR MODE For timing insensitive applications, the RC device VDD option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resis- REXT Internal tor (REXT) and capacitor (CEXT) values, and the operat- OSC1 clock ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal pro- N cess parameter variation. Furthermore, the difference CEXT PIC16C5X in lead frame capacitance between package types will VSS also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account OSC2/CLKOUT Fosc/4 variation due to tolerance of external R and C compo- nents used. Figure4-5 shows how the R/C combination is con- Note: If you change from this device to another nected to the PIC16C5X. For REXT values below device, please verify oscillator characteris- 2.2k, the oscillator operation may become unstable, tics in your application. or stop completely. For very high REXT values (e.g.,1M) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 3k and 100k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or pack- age lead frame capacitance. The Electrical Specifications sections show RC fre- quency variation from part to part due to normal pro- cess variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for vari- ation of oscillator frequency due to VDD for given REXT/ CEXT values as well as frequency variation due to oper- ating temperature for given R, C, and VDD values. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test pur- poses or to synchronize other logic. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 17

PIC16C5X NOTES: Preliminary DS30453E-page 18  1997-2013 Microchip Technology Inc.

PIC16C5X 5.0 RESET The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different RESET conditions (Table5- PIC16C5X devices may be RESET in one of the follow- 1). These bits may be used to determine the nature of ing ways: the RESET. • Power-On Reset (POR) Table5-3 lists a full description of RESET states of all • MCLR Reset (normal operation) registers. Figure5-1 shows a simplified block diagram • MCLR Wake-up Reset (from SLEEP) of the On-chip Reset circuit. • WDT Reset (normal operation) • WDT Wake-up Reset (from SLEEP) Table5-1 shows these RESET conditions for the PCL and STATUS registers. Some registers are not affected in any RESET condi- tion. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a “RESET state” on Power-On Reset (POR), MCLR or WDT Reset. A MCLR or WDT wake-up from SLEEP also results in a device RESET, and not a continuation of operation before SLEEP. TABLE 5-1: STATUS BITS AND THEIR SIGNIFICANCE Condition TO PD Power-On Reset 1 1 MCLR Reset (normal operation) u u MCLR Wake-up (from SLEEP) 1 0 WDT Reset (normal operation) 0 1 WDT Wake-up (from SLEEP) 0 0 Legend: u = unchanged, x = unknown, — = unimplemented read as '0'. TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH RESET Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MCLR and POR WDT Reset 03h STATUS PA2 PA1 PA0 TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, q = see Table5-1 for possible values. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 19

PIC16C5X TABLE 5-3: RESET CONDITIONS FOR ALL REGISTERS Register Address Power-On Reset MCLR or WDT Reset W N/A xxxx xxxx uuuu uuuu TRIS N/A 1111 1111 1111 1111 OPTION N/A --11 1111 --11 1111 INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000q quuu FSR(1) 04h 1xxx xxxx 1uuu uuuu PORTA 05h ---- xxxx ---- uuuu PORTB 06h xxxx xxxx uuuu uuuu PORTC(2) 07h xxxx xxxx uuuu uuuu General Purpose Register Files 07-7Fh xxxx xxxx uuuu uuuu Legend: x = unknown u = unchanged - = unimplemented, read as '0' q = see tables in Table5-1 for possible values. Note 1: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu. 2: General purpose register file on PIC16C54/CR54/C56/CR56/C58/CR58. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-Up Detect VDD POR (Power-On Reset) MCLR/VPP pin WDT Time-out RESET S Q WDT 8-bit Asynch On-Chip Ripple Counter RC OSC (Device Reset R Q Timer) CHIP RESET Preliminary DS30453E-page 20  1997-2013 Microchip Technology Inc.

PIC16C5X 5.1 Power-On Reset (POR) FIGURE 5-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR The PIC16C5X family incorporates on-chip Power-On SLOW VDD POWER-UP) Reset (POR) circuitry which provides an internal chip RESET for most power-up situations. To use this fea- VDD VDD ture, the user merely ties the MCLR/VPP pin to VDD. A simplified block diagram of the on-chip Power-On D R Reset circuit is shown in Figure5-1. R1 The Power-On Reset circuit and the Device Reset MCLR Timer (Section5.2) circuit are closely related. On C PIC16C5X power-up, the RESET latch is set and the DRT is RESET. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is • External Power-On Reset circuit is required typically 18ms, it will RESET the reset latch and thus only if VDD power-up is too slow. The diode D end the on-chip RESET signal. helps discharge the capacitor quickly when A power-up example where MCLR is not tied to VDD is VDD powers down. shown in Figure5-3. VDD is allowed to rise and stabilize • R < 40k is recommended to make sure that before bringing MCLR high. The chip will actually come voltage drop across R does not violate the out of reset TDRT msec after MCLR goes high. device electrical specification. In Figure5-4, the on-chip Power-On Reset feature is • R1 = 100 to 1k will limit any current flow- being used (MCLR and VDD are tied together). The VDD ing into MCLR from external capacitor C in the is stable before the start-up timer times out and there is event of MCLR pin breakdown due to Electro- no problem in getting a proper RESET. However, static Discharge (ESD) or Electrical Over- Figure5-5 depicts a problem situation where VDD rises stress (EOS). too slowly. The time between when the DRT senses a high on the MCLR/VPP pin, and when the MCLR/VPP pin (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external RC cir- cuits be used to achieve longer POR delay times (Figure5-2). Note: When the device starts normal operation (exits the RESET condition), device oper- ating parameters (voltage, frequency, tem- perature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For more information on PIC16C5X POR, see Power- Up Considerations - AN522 in the Embedded Control Handbook. The POR circuit does not produce an internal RESET when VDD declines. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 21

PIC16C5X FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will RESET properly if, and only if, V1  VDD min Preliminary DS30453E-page 22  1997-2013 Microchip Technology Inc.

PIC16C5X 5.2 Device Reset Timer (DRT) FIGURE 5-7: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 The Device Reset Timer (DRT) provides an 18ms nominal time-out on RESET regardless of Oscillator VDD mode used. The DRT operates on an internal RC oscil- lator. The processor is kept in RESET as long as the VDD DRT is active. The DRT delay allows VDD to rise above R1 VDD min., and for the oscillator to stabilize. Q1 Oscillator circuits based on crystals or ceramic resona- MCLR tors require a certain time after power-up to establish a R2 40K stable oscillation. The on-chip DRT keeps the device in PIC16C5X a RESET condition for approximately 18ms after the voltage on the MCLR/VPP pin has reached a logic high (VIH) level. Thus, external RC networks connected to the MCLR input are not required in most cases, allow- ing for savings in cost-sensitive and/or space restricted This brown-out circuit is less expensive, although applications. less accurate. Transistor Q1 turns off when VDD The Device Reset time delay will vary from chip to chip is below a certain level such that: due to VDD, temperature, and process variation. See R1 AC parameters for details. VDD • = 0.7V R1 + R2 The DRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake the PIC16C5X from SLEEP mode automatically. FIGURE 5-8: EXTERNAL BROWN-OUT 5.3 Reset on Brown-Out PROTECTION CIRCUIT 3 A brown-out is a condition where device power (VDD) VDD dips below its minimum value, but not to zero, and then recovers. The device should be RESET in the event of VDD cbayppaacsitsor VDD a brown-out. MCP809 To RESET PIC16C5X devices when a brown-out RST MCLR occurs, external brown-out protection circuits may be Vss built, as shown in Figure5-6, Figure5-7 and Figure5- PIC16C5X 8. This brown-out protection circuit employs Micro- FIGURE 5-6: EXTERNAL BROWN-OUT chip Technology’s MCP809 microcontroller PROTECTION CIRCUIT 1 supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collec- tor outputs with both "active high and active low" VDD RESET pins. There are 7 different trip point selec- tions to accommodate 5V and 3V systems. VDD 33K Q1 10K MCLR 40K PIC16C5X This circuit will activate RESET when VDD goes below Vz + 0.7V (where Vz = Zener voltage). Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 23

PIC16C5X NOTES: Preliminary DS30453E-page 24  1997-2013 Microchip Technology Inc.

PIC16C5X 6.0 MEMORY ORGANIZATION FIGURE 6-2: PIC16C56/CR56 PROGRAM MEMORY MAP PIC16C5X memory is organized into program memory AND STACK and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. PC<9:0> Program memory pages are accessed using one or two 10 STATUS Register bits. For devices with a data memory CALL, RETLW register file of more than 32 registers, a banking Stack Level 1 scheme is used. Data memory banks are accessed Stack Level 2 using the File Selection Register (FSR). 000h 6.1 Program Memory Organization On-chip Program ory Memory (Page 0) 01F00Fhh The PIC16C54, PIC16CR54 and PIC16C55 have a 9- me ec bit Program Counter (PC) capable of addressing a 512 Ma 1FFh x 12 program memory space (Figure6-1). The er Sp 200h s PIC16C56 and PIC16CR56 have a 10-bit Program U On-chip Program 2FFh Counter (PC) capable of addressing a 1K x 12 program Memory (Page 1) 300h memory space (Figure6-2). The PIC16CR57, PIC16C58 and PIC16CR58 have an 11-bit Program RESET Vector 3FFh Counter capable of addressing a 2K x 12 program memory space (Figure6-3). Accessing a location above the physically implemented address will cause a FIGURE 6-3: PIC16C57/CR57/C58/ wraparound. CR58 PROGRAM A NOP at the RESET vector location will cause a restart MEMORY MAP AND at location 000h. The RESET vector for the PIC16C54, STACK PIC16CR54 and PIC16C55 is at 1FFh. The RESET vector for the PIC16C56 and PIC16CR56 is at 3FFh. PC<10:0> The RESET vector for the PIC16C57, PIC16CR57, 11 CALL, RETLW PIC16C58, and PIC16CR58 is at 7FFh. See Stack Level 1 Section6.5 for additional information using CALL and Stack Level 2 GOTO instructions. 000h FIGURE 6-1: PIC16C54/CR54/C55 On-chip Program 0FFh PROGRAM MEMORY MAP Memory (Page 0) 100h AND STACK 1FFh 200h PC<8:0> On-chip Program 9 y 2FFh CALL, RETLW more Memory (Page 1) 300h Stack Level 1 Mepac 3FFh Stack Level 2 er S 400h s U On-chip Program 000h Memory (Page 2) 4FFh 500h y emorce POrno-gcrhaimp 0FFh 56F00Fhh User MSpa Memory 100h MOne-mcohripy P(Proaggrea m3) 67F00Fhh RESET Vector 7FFh RESET Vector 1FFh Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 25

PIC16C5X 6.2 Data Memory Organization FIGURE 6-4: PIC16C54, PIC16CR54, PIC16C55, PIC16C56, Data memory is composed of registers, or bytes of PIC16CR56 REGISTER RAM. Therefore, data memory for a device is specified FILE MAP by its register file. The register file is divided into two functional groups: Special Function Registers and Gen- File Address eral Purpose Registers. 00h INDF(1) The Special Function Registers include the TMR0 reg- ister, the Program Counter (PC), the Status Register, 01h TMR0 the I/O registers (ports) and the File Select Register 02h PCL (FSR). In addition, Special Purpose Registers are used 03h STATUS to control the I/O port configuration and prescaler options. 04h FSR The General Purpose Registers are used for data and 05h PORTA control information under command of the instructions. 06h PORTB For the PIC16C54, PIC16CR54, PIC16C56 and 07h PORTC(2) PIC16CR56, the register file is composed of 7 Special Function Registers and 25 General Purpose Registers 08h (Figure6-4). General For the PIC16C55, the register file is composed of 8 Purpose Registers Special Function Registers and 24 General Purpose Registers. For the PIC16C57 and PIC16CR57, the register file is composed of 8 Special Function Registers, 24 General 1Fh Purpose Registers and up to 48 additional General Purpose Registers that may be addressed using a Note 1: Not a physical register. See banking scheme (Figure6-5). Section6.7. 2: PIC16C55 only, in all other devices this For the PIC16C58 and PIC16CR58, the register file is is implemented as a a general purpose composed of 7 Special Function Registers, 25 General register. Purpose Registers and up to 48 additional General Purpose Registers that may be addressed using a banking scheme (Figure6-6). 6.2.1 GENERAL PURPOSE REGISTER FILE The register file is accessed either directly or indirectly through the File Select Register (FSR). The FSR Reg- ister is described in Section6.7. Preliminary DS30453E-page 26  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 6-5: PIC16C57/CR57 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 20h 40h 60h 01h TMR0 02h PCL 03h STATUS 04h FSR Addresses map back to 05h PORTA addresses in Bank 0. 06h PORTB 07h POR TC 08h General Purpose 0Fh Registers 2Fh 4Fh 6Fh 10h 30h 50h 70h General General General General Purpose Purpose Purpose Purpose Registers Registers Registers Registers 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: Not a physical register. See Section6.7. FIGURE 6-6: PIC16C58/CR58 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 20h 40h 60h 01h TMR0 02h PCL 03h STATUS 04h FSR Addresses map back to 05h PORTA addresses in Bank 0. 06h PORTB 07h General Purpose Registers 0Fh 2Fh 4Fh 6Fh 10h 30h 50h 70h General General General General Purpose Purpose Purpose Purpose Registers Registers Registers Registers 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: Not a physical register. See Section6.7. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 27

PIC16C5X 6.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions to control the opera- tion of the device (Table6-1). The Special Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 6-1: SPECIAL FUNCTION REGISTER SUMMARY Value on Details Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on on Page Reset N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 35 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 30 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 32 01h TMR0 Timer0 Module Register xxxx xxxx 38 02h(1) PCL Low order 8 bits of PC 1111 1111 31 03h STATUS PA2 PA1 PA0 TO PD Z DC C 0001 1xxx 29 04h FSR Indirect data memory address pointer 1xxx xxxx(3) 32 05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx 35 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 35 07h(2) PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 35 Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable). Shaded cells = unimplemented or unused Note 1: The upper byte of the Program Counter is not directly accessible. See Section6.5 for an explanation of how to access these bits. 2: File address 07h is a General Purpose Register on the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and PIC16CR58. 3: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu. Preliminary DS30453E-page 28  1997-2013 Microchip Technology Inc.

PIC16C5X 6.3 STATUS Register writable. Therefore, the result of an instruction with the STATUS Register as destination may be different than This register contains the arithmetic status of the ALU, intended. the RESET status and the page preselect bits for pro- For example, CLRF STATUS will clear the upper three gram memories larger than 512 words. bits and set the Z bit. This leaves the STATUS Register The STATUS Register can be the destination for any as 000u u1uu (where u = unchanged). instruction, as with any other register. If the STATUS It is recommended, therefore, that only BCF, BSF and Register is the destination for an instruction that affects MOVWF instructions be used to alter the STATUS Reg- the Z, DC or C bits, then the write to these three bits is ister because these instructions do not affect the Z, DC disabled. These bits are set or cleared according to the or C bits from the STATUS Register. For other instruc- device logic. Furthermore, the TO and PD bits are not tions which do affect STATUS Bits, see Section10.0, Instruction Set Summary. REGISTER 6-1: STATUS REGISTER (ADDRESS: 03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x PA2 PA1 PA0 TO PD Z DC C bit 7 bit 0 bit 7: PA2: This bit unused at this time. Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. bit 6-5: PA<1:0>: Program page preselect bits (PIC16C56/CR56)(PIC16C57/CR57)(PIC16C58/CR58) 00 = Page 0 (000h - 1FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58 01 = Page 1 (200h - 3FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58 10 = Page 2 (400h - 5FFh) - PIC16C57/CR57, PIC16C58/CR58 11 = Page 3 (600h - 7FFh) - PIC16C57/CR57, PIC16C58/CR58 Each page is 512 words. Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Loaded with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 29

PIC16C5X 6.4 OPTION Register The OPTION Register is a 6-bit wide, write-only regis- ter which contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W Register will be transferred to the OPTION Reg- ister. A RESET sets the OPTION<5:0> bits. REGISTER 6-2: OPTION REGISTER U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1 — — T0CS TOSE PSA PS2 PS1 PS0 bit 7 bit 0 bit 7-6: Unimplemented: Read as ‘0’ bit 5: T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: Timer0 source edge select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3: PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS<2:0>: Prescaler rate select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown Preliminary DS30453E-page 30  1997-2013 Microchip Technology Inc.

PIC16C5X 6.5 Program Counter FIGURE 6-8: LOADING OF PC BRANCH INSTRUCTIONS As a program instruction is executed, the Program - PIC16C56/PIC16CR56 Counter (PC) will contain the address of the next pro- gram instruction to be executed. The PC value is GOTO Instruction increased by one, every instruction cycle, unless an 10 9 8 7 0 instruction changes the PC. PC 0 PCL For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> (Figure6-7, Figure6-8 and Instruction Word Figure6-9). 2 PA<1:0> For the PIC16C56, PIC16CR56, PIC16C57, 7 0 PIC16CR57, PIC16C58 and PIC16CR58, a page num- 0 ber must be supplied as well. Bit5 and bit6 of the STA- STATUS TUS Register provide page information to bit9 and bit10 of the PC (Figure6-8 and Figure6-9). CALL or Modify PCL Instruction For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are pro- 10 9 8 7 0 vided by the instruction word. However, PC<8> does PC 0 PCL not come from the instruction word, but is always cleared (Figure6-7 and Figure6-8). Instruction Word Instructions where the PCL is the destination, or modify PCL instructions, include MOVWF PCL, ADDWF PCL, Reset to ‘0’ and BSF PCL,5. 2 PA<1:0> 7 0 For the PIC16C56, PIC16CR56, PIC16C57, 0 PIC16CR57, PIC16C58 and PIC16CR58, a page num- STATUS ber again must be supplied. Bit5 and bit6 of the STA- TUS Register provide page information to bit9 and bit10 of the PC (Figure6-8 and Figure6-9). FIGURE 6-9: LOADING OF PC BRANCH INSTRUCTIONS Note: Because PC<8> is cleared in the CALL - PIC16C57/PIC16CR57, instruction, or any modify PCL instruction, all subroutine calls or computed jumps are AND PIC16C58/ limited to the first 256 locations of any pro- PIC16CR58 gram memory page (512 words long). GOTO Instruction 10 9 8 7 0 FIGURE 6-7: LOADING OF PC PC PCL BRANCH INSTRUCTIONS - PIC16C54, PIC16CR54, PIC16C55 Instruction Word GOTO Instruction 2 PA<1:0> 7 0 8 7 0 PC PCL STATUS Instruction Word CALL or Modify PCL Instruction 10 9 8 7 0 CALL or Modify PCL Instruction PC PCL 8 7 0 PC PCL Instruction Word Reset to ‘0’ Reset to '0' Instruction Word 2 PA<1:0> 7 0 STATUS Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 31

PIC16C5X 6.5.1 PAGING CONSIDERATIONS – PIC16C56/CR56, PIC16C57/CR57 AND PIC16C58/CR58 If the Program Counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. However, the page preselect bits in the STATUS Reg- ister will not be updated. Therefore, the next GOTO, CALL or modify PCL instruction will send the program to the page specified by the page preselect bits (PA0 or PA<1:0>). For example, a NOP at location 1FFh (page 0) incre- ments the PC to 200h (page 1). A GOTO xxx at 200h will return the program to address xxh on page 0 (assuming that PA<1:0> are clear). To prevent this, the page preselect bits must be updated under program control. 6.5.2 EFFECTS OF RESET The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page (i.e., the RESET vector). The STATUS Register page preselect bits are cleared upon a RESET, which means that page 0 is pre- selected. Therefore, upon a RESET, a GOTO instruction at the RESET vector location will automatically cause the pro- gram to jump to page0. 6.6 Stack PIC16C5X devices have a 10-bit or 11-bit wide, two- level hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program coun- ter value, incremented by one, into stack level 1. If more than two sequential CALL’s are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled with the address previously stored in level 2. Note that the WRegister will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the pro- gram memory. For the RETLW instruction, the PC is loaded with the Top of Stack (TOS) contents. All of the devices covered in this data sheet have a two-level stack. The stack has the same bit width as the device PC, therefore, paging is not an issue when returning from a subroutine. Preliminary DS30453E-page 32  1997-2013 Microchip Technology Inc.

PIC16C5X 6.7 Indirect Data Addressing; INDF EXAMPLE 6-2: HOW TO CLEAR RAM and FSR Registers USING INDIRECT ADDRESSING The INDF Register is not a physical register. Addressing INDF actually addresses the register MOVLW H'10' ;initialize pointer whose address is contained in the FSR Register (FSR MOVWF FSR ; to RAM NEXT CLRF INDF ;clear INDF Register is a pointer). This is indirect addressing. INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? EXAMPLE 6-1: INDIRECT ADDRESSING GOTO NEXT ;NO, clear next CONTINUE • Register file 08 contains the value 10h : ;YES, continue • Register file 09 contains the value 0Ah • Load the value 08 into the FSR Register The FSR is either a 5-bit (PIC16C54, PIC16CR54, • A read of the INDF Register will return the value PIC16C55, PIC16C56, PIC16CR56) or 7-bit of10h (PIC16C57, PIC16CR57, PIC16C58, PIC16CR58) • Increment the value of the FSR Register by one wide register. It is used in conjunction with the INDF (FSR = 09h) Register to indirectly address the data memory area. • A read of the INDF register now will return the The FSR<4:0> bits are used to select data memory value of 0Ah. addresses 00h to 1Fh. Reading INDF itself indirectly (FSR = 0) will produce PIC16C54, PIC16CR54, PIC16C55, PIC16C56, 00h. Writing to the INDF Register indirectly results in a PIC16CR56: These do not use banking. FSR<6:5> bits no-operation (although STATUS bits may be affected). are unimplemented and read as'1's. A simple program to clear RAM locations 10h-1Fh PIC16C57, PIC16CR57, PIC16C58, PIC16CR58: using indirect addressing is shown in Example6-2. FSR<6:5> are the bank select bits and are used to select the bank to be addressed (00 = bank0, 01=bank 1, 10 = bank 2, 11 = bank 3). FIGURE 6-10: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing (FSR) (opcode) (FSR) 6 5 4 3 2 1 0 6 5 4 3 2 1 0 bank select location select bank location select 00 01 10 11 00h Addresses map back to addresses in Bank 0. Data 0Fh Memory(1) 10h 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register map detail see Section6.2. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 33

PIC16C5X NOTES: Preliminary DS30453E-page 34  1997-2013 Microchip Technology Inc.

PIC16C5X 7.0 I/O PORTS 7.5 I/O Interfacing As with any other register, the I/O Registers can be The equivalent circuit for an I/O port pin is shown in written and read under program control. However, read Figure7-1. All ports may be used for both input and instructions (e.g., MOVF PORTB,W) always read the I/O output operation. For input operations these ports are pins independent of the pin’s input/output modes. On non-latching. Any input must be present until read by RESET, all I/O ports are defined as input (inputs are at an input instruction (e.g., MOVF PORTB, W). The out- hi-impedance) since the I/O control registers (TRISA, puts are latched and remain unchanged until the output TRISB, TRISC) are all set. latch is rewritten. To use a port pin as output, the corre- sponding direction control bit (in TRISA, TRISB, 7.1 PORTA TRISC) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be PORTA is a 4-bit I/O Register. Only the low order 4 bits programmed individually as input or output. are used (RA<3:0>). Bits 7-4 are unimplemented and read as '0's. 7.2 PORTB FIGURE 7-1: EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN PORTB is an 8-bit I/O Register (PORTB<7:0>). Data Bus 7.3 PORTC D Q Data PORTC is an 8-bit I/O Register for PIC16C55, VDD WR Latch PIC16C57 and PIC16CR57. Port CK Q PORTC is a General Purpose Register for PIC16C54, P PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and PIC16CR58. W N I/O Reg pin(1) 7.4 TRIS Registers D Q TRIS The Output Driver Control Registers are loaded with Latch VSS the contents of the W Register by executing the TRIS ‘f’ CK Q TRIS f instruction. A '1' from a TRIS Register bit puts the corresponding output driver in a hi-impedance (input) mode. A '0' puts the contents of the output data RESET latch on the selected pins, enabling the output buffer. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a RD Port read of the port will indicate that the pin is Note 1: I/O pins have protection diodes to VDD and VSS. low. The TRIS Registers are “write-only” and are set (output drivers disabled) upon RESET. TABLE 7-1: SUMMARY OF PORT REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On MCLR and Reset WDT Reset N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111 05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, — = unimplemented, read as '0', Shaded cells = unimplemented, read as ‘0’ Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 35

PIC16C5X 7.6 I/O Programming Considerations EXAMPLE 7-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O 7.6.1 BI-DIRECTIONAL I/O PORTS PORT Some instructions operate internally as read followed ;Initial PORT Settings by write operations. The BCF and BSF instructions, for ; PORTB<7:4> Inputs example, read the entire port into the CPU, execute the ; PORTB<3:0> Outputs bit operation and re-write the result. Caution must be ;PORTB<7:6> have external pull-ups and are used when these instructions are applied to a port ;not connected to other circuitry ; where one or more pins are used as input/outputs. For ; PORT latch PORT pins example, a BSF operation on bit5 of PORTB will cause ; ---------- ---------- all eight bits of PORTB to be read into the CPU, bit5 to BCF PORTB, 7 ;01pp pppp 11pp pppp be set and the PORTB value to be written to the output BCF PORTB, 6 ;10pp pppp 11pp pppp latches. If another bit of PORTB is used as a bi-direc- MOVLW H'3F' ; tional I/O pin (say bit0) and it is defined as an input at TRIS PORTB ;10pp pppp 10pp pppp this time, the input signal present on the pin itself would ; be read into the CPU and rewritten to the data latch of ;Note that the user may have expected the pin this particular pin, overwriting the previous content. As ;values to be 00pp pppp. The 2nd BCF caused long as the pin stays in the Input mode, no problem ;RB7 to be latched as the pin value (High). occurs. However, if bit0 is switched into Output mode 7.6.2 SUCCESSIVE OPERATIONS ON I/O later on, the content of the data latch may now be PORTS unknown. Example7-1 shows the effect of two sequential read- The actual write to an I/O port happens at the end of an modify-write instructions (e.g., BCF, BSF, etc.) on an instruction cycle, whereas for reading, the data must be I/O port. valid at the beginning of the instruction cycle (Figure7- 2). Therefore, care must be exercised if a write followed A pin actively outputting a high or a low should not be by a read operation is carried out on the same I/O port. driven from external devices at the same time in order The sequence of instructions should allow the pin volt- to change the level on this pin (“wired-or”, “wired-and”). age to stabilize (load dependent) before the next The resulting high output currents may damage the instruction, which causes that file to be read into the chip. CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instruc- tions with a NOP or another instruction not accessing this I/O port. FIGURE 7-2: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 Instruction fetched MOVWF PORTB MOVF PORTB,W NOP NOP This example shows a write to PORTB followed by a read RB<7:0> from PORTB. Port pin Port pin written here sampled here MOVWF PORTB MOVF PORTB,W NOP Instruction (Write to (Read executed PORTB) PORTB) Preliminary DS30453E-page 36  1997-2013 Microchip Technology Inc.

PIC16C5X 8.0 TIMER0 MODULE AND TMR0 Counter mode is selected by setting the T0CS bit REGISTER (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The The Timer0 module has the following features: incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit • 8-bit timer/counter register, TMR0 selects the rising edge. Restrictions on the external - Readable and writable clock input are discussed in detail in Section8.1. • 8-bit software programmable prescaler Note: The prescaler may be used by either the • Internal or external clock select Timer0 module or the Watchdog Timer, but - Edge select for external clock not both. Figure8-1 is a simplified block diagram of the Timer0 The prescaler assignment is controlled in software by module, while Figure8-2 shows the electrical structure the control bit PSA (OPTION<3>). Clearing the PSA bit of the Timer0 input. will assign the prescaler to Timer0. The prescaler is not Timer mode is selected by clearing the T0CS bit readable or writable. When the prescaler is assigned to (OPTION<5>). In Timer mode, the Timer0 module will the Timer0 module, prescale values of 1:2, 1:4,..., increment every instruction cycle (without prescaler). If 1:256 are selectable. Section8.2 details the operation TMR0 register is written, the increment is inhibited for of the prescaler. the following two cycles (Figure8-3 and Figure8-4). A summary of registers associated with the Timer0 The user can work around this by writing an adjusted module is found in Table8-1. value to the TMR0 register. FIGURE 8-1: TIMER0 BLOCK DIAGRAM Data Bus FOSC/4 0 PSout 8 1 Sync with 1 Internal TMR0 reg Clocks T0CKI Programmable 0 PSout pin Prescaler(2) Sync T0SE(1) (2 cycle delay) 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register (Section6.4). 2: The prescaler is shared with the Watchdog Timer (Figure8-6). FIGURE 8-2: ELECTRICAL STRUCTURE OF T0CKI PIN RIN T0CKI (1) Schmitt Trigger pin (1) N Input Buffer VSS VSS Note 1: ESD protection circuits. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 37

PIC16C5X FIGURE 8-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 FIGURE 8-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0+1 NT0 NT0+1 T0 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on MCLR and Reset WDT Reset 01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells not used by Timer0. Preliminary DS30453E-page 38  1997-2013 Microchip Technology Inc.

PIC16C5X 8.1 Using Timer0 with an External When a prescaler is used, the external clock input is Clock divided by the asynchronous ripple counter-type pres- caler so that the prescaler output is symmetrical. For When an external clock input is used for Timer0, it must the external clock to meet the sampling requirement, meet certain requirements. The external clock require- the ripple counter must be taken into account. There- ment is due to internal phase clock (TOSC) synchroniza- fore, it is necessary for T0CKI to have a period of at tion. Also, there is a delay in the actual incrementing of least 4TOSC (and a small RC delay of 40ns) divided by Timer0 after synchronization. the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the mini- 8.1.1 EXTERNAL CLOCK mum pulse width requirement of 10 ns. Refer to param- SYNCHRONIZATION eters 40, 41 and 42 in the electrical specification of the desired device. When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization 8.1.2 TIMER0 INCREMENT DELAY of T0CKI with the internal phase clocks is accom- plished by sampling the prescaler output on the Q2 and Since the prescaler output is synchronized with the Q4 cycles of the internal phase clocks (Figure8-5). internal clocks, there is a small delay from the time the Therefore, it is necessary for T0CKI to be high for at external clock edge occurs to the time the Timer0 mod- least 2TOSC (and a small RC delay of 20ns) and low for ule is actually incremented. Figure8-5 shows the delay at least 2TOSC (and a small RC delay of 20ns). Refer from the external clock edge to the timer incrementing. to the electrical specification of the desired device. FIGURE 8-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output (1) misses sampling (3) External Clock/Prescaler (2) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: External clock if no prescaler selected, prescaler output otherwise. 2: The arrows indicate the points in time where sampling occurs. 3: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc (duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input =  4Tosc max. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 39

PIC16C5X 8.2 Prescaler EXAMPLE 8-1: CHANGING PRESCALER (TIMER0WDT) An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog CLRWDT ;Clear WDT Timer (WDT), respectively (Section9.2.1). For simplic- CLRF TMR0 ;Clear TMR0 & Prescaler ity, this counter is being referred to as “prescaler” MOVLW B'00xx1111’ ;Last 3 instructions in this example throughout this data sheet. Note that the prescaler may OPTION ;are required only if be used by either the Timer0 module or the WDT, but ;desired not both. Thus, a prescaler assignment for the Timer0 CLRWDT ;PS<2:0> are 000 or module means that there is no prescaler for the WDT, ;001 and vice-versa. MOVLW B'00xx1xxx’ ;Set Prescaler to The PSA and PS<2:0> bits (OPTION<3:0>) determine OPTION ;desired WDT rate prescaler assignment and prescale ratio. To change prescaler from the WDT to the Timer0 mod- ule, use the sequence shown in Example8-2. This When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, sequence must be used even if the WDT is disabled. A MOVWF 1, BSF 1,x, etc.) will clear the prescaler. CLRWDT instruction should be executed before switch- When assigned to WDT, a CLRWDT instruction will clear ing the prescaler. the prescaler along with the WDT. The prescaler is nei- ther readable nor writable. On a RESET, the prescaler EXAMPLE 8-2: CHANGING PRESCALER contains all '0's. (WDTTIMER0) CLRWDT ;Clear WDT and 8.2.1 SWITCHING PRESCALER ;prescaler ASSIGNMENT MOVLW B'xxxx0xxx' ;Select TMR0, new ;prescale value and The prescaler assignment is fully under software con- ;clock source trol (i.e., it can be changed “on the fly” during program OPTION execution). To avoid an unintended device RESET, the following instruction sequence (Example8-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. Preliminary DS30453E-page 40  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 8-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = FOSC/4) Data Bus 0 8 M 1 U T0CKI 1 X M Sync pin U 2 TMR0 reg 0 X Cycles T0SE T0CS PSA 0 8-bit Prescaler M U 1 X Watchdog 8 Timer 8 - to - 1MUX PS<2:0> PSA 0 1 WDT Enable bit MUX PSA WDT Time-Out Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 41

PIC16C5X NOTES: Preliminary DS30453E-page 42  1997-2013 Microchip Technology Inc.

PIC16C5X 9.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other proces- sors are special circuits that deal with the needs of real- time applications. The PIC16C5X family of microcon- trollers have a host of such features intended to maxi- mize system reliability, minimize cost through elimination of external components, provide power sav- ing operating modes and offer code protection. These features are: • Oscillator Selection (Section4.0) • RESET (Section5.0) • Power-On Reset (Section5.1) • Device Reset Timer (Section5.2) • Watchdog Timer (WDT) (Section9.2) • SLEEP (Section9.3) • Code protection (Section9.4) • ID locations (Section9.5) The PIC16C5X Family has a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in RESET until the crystal oscillator is stable. With this timer on-chip, most applications need no external RESET circuitry. The SLEEP mode is designed to offer a very low cur- rent Power-down mode. The user can wake up from SLEEP through external RESET or through a Watch- dog Timer time-out. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 43

PIC16C5X 9.1 Configuration Bits PIC16C58B, and PIC16CR58B devices (Register9-1). One bit is for code protection for the PIC16C54, Configuration bits can be programmed to select various PIC16C55, PIC16C56 and PIC16C57 devices device configurations. Two bits are for the selection of (Register9-2). the oscillator type and one bit is the Watchdog Timer QTP or ROM devices have the oscillator configuration enable bit. Nine bits are code protection bits for the programmed at the factory and these parts are tested PIC16C54A, PIC16CR54A, PIC16C54C, accordingly (see "Product Identification System" dia- PIC16CR54C, PIC16C55A, PIC16C56A, grams in the back of this data sheet). PIC16CR56A, PIC16C57C, PIC16CR57C, REGISTER 9-1: CONFIGURATION WORD FOR PIC16C54A/CR54A/C54C/CR54C/C55A/C56A/ CR56A/C57C/CR57C/C58B/CR58B CP CP CP CP CP CP CP CP CP WDTE FOSC1 FOSC0 bit 11 bit 0 bit 11-3: CP: Code Protection Bit 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection Bit 00 = LP oscillator 01 = XT oscillator 10 = HS oscillator 11 = RC oscillator Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to access the configuration word. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown Preliminary DS30453E-page 44  1997-2013 Microchip Technology Inc.

PIC16C5X REGISTER 9-2: CONFIGURATION WORD FOR PIC16C54/C55/C56/C57 — — — — — — — — CP WDTE FOSC1 FOSC0 bit 11 bit 0 bit 11-4: Unimplemented: Read as ‘0’ bit 3: CP: Code protection bit. 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator selection bits(2) 00 = LP oscillator 01 = XT oscillator 10 = HS oscillator 11 = RC oscillator Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the configuration word. 2: PIC16LV54A supports XT, RC and LP oscillator only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 45

PIC16C5X 9.2 Watchdog Timer (WDT) both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, The Watchdog Timer (WDT) is a free running on-chip and vice-versa. RC oscillator which does not require any external com- The PSA and PS<2:0> bits (OPTION<3:0>) determine ponents. This RC oscillator is separate from the RC prescaler assignment and prescale ratio (Section6.4). oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and The WDT has a nominal time-out period of 18ms (with OSC2/CLKOUT pins have been stopped, for example, no prescaler). If a longer time-out period is desired, a by execution of a SLEEP instruction. During normal prescaler with a division ratio of up to 1:128 can be operation or SLEEP, a WDT Reset or Wake-up Reset assigned to the WDT (under software control) by writ- generates a device RESET. ing to the OPTION register. Thus, time-out a period of a nominal 2.3 seconds can be realized. These periods The TO bit (STATUS<4>) will be cleared upon a Watch- dog Timer Reset (Section6.3). vary with temperature, VDD and part-to-part process variations (see Device Characterization). The WDT can be permanently disabled by program- ming the configuration bit WDTE as a '0' (Section9.1). Under worst case conditions (VDD = Min., Temperature = Max., WDT prescaler = 1:128), it may take several Refer to the PIC16C5X Programming Specifications seconds before a WDT time-out occurs. (Literature Number DS30190) to determine how to access the configuration word. 9.2.2 WDT PROGRAMMING 9.2.1 WDT PERIOD CONSIDERATIONS An 8-bit counter is available as a prescaler for the The CLRWDT instruction clears the WDT and the pres- Timer0 module (Section8.2), or as a postscaler for the caler, if assigned to the WDT, and prevents it from tim- Watchdog Timer (WDT), respectively. For simplicity, ing out and generating a device RESET. this counter is being referred to as “prescaler” through- The SLEEP instruction RESETS the WDT and the pres- out this data sheet. Note that the prescaler may be caler, if assigned to the WDT. This gives the maximum used by either the Timer0 module or the WDT, but not SLEEP time before a WDT Wake-up Reset. FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source 0 M Watchdog 1 Prescaler U Timer X 8 - to - 1 MUX PS2:PS0 WDT Enable PSA EPROM Bit To TMR0 0 1 MUX PSA Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the WDT OPTION register. Time-out TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On MCLR and Reset WDT Reset N/A OPTION — — Tosc Tose PSA PS2 PS1 PS0 --11 1111 --11 1111 Legend: u = unchanged, - = unimplemented, read as '0'. Shaded cells not used by Watchdog Timer. Preliminary DS30453E-page 46  1997-2013 Microchip Technology Inc.

PIC16C5X 9.3 Power-Down Mode (SLEEP) 9.4 Program Verification/Code Protection A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). If the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read 9.3.1 SLEEP out for verification purposes. The Power-down mode is entered by executing a Note: Microchip does not recommend code pro- SLEEP instruction. tecting windowed devices. If enabled, the Watchdog Timer will be cleared but 9.5 ID Locations keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is Four memory locations are designated as ID locations turned off. The I/O ports maintain the status they had where the user can store checksum or other code-iden- before the SLEEP instruction was executed (driving tification numbers. These locations are not accessible high, driving low, or hi-impedance). during normal execution but are readable and writable It should be noted that a RESET generated by a WDT during program/verify. time-out does not drive the MCLR/VPP pin low. Use only the lower 4 bits of the ID locations and always For lowest current consumption while powered down, program the upper 8 bits as '1's. the T0CKI input should be at VDD or VSS and the Note: Microchip will assign a unique pattern MCLR/VPP pin must be at a logic high level number for QTP and SQTP requests and (MCLR = VIH). for ROM devices. This pattern number will 9.3.2 WAKE-UP FROM SLEEP be unique and traceable to the submitted code. The device can wake up from SLEEP through one of the following events: 1. An external RESET input on MCLR/VPP pin. 2. A Watchdog Timer Time-out Reset (if WDT was enabled). Both of these events cause a device RESET. The TO and PD bits can be used to determine the cause of device RESET. The TO bit is cleared if a WDT time- out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The WDT is cleared when the device wakes from SLEEP, regardless of the wake-up source. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 47

PIC16C5X NOTES: Preliminary DS30453E-page 48  1997-2013 Microchip Technology Inc.

PIC16C5X 10.0 INSTRUCTION SET SUMMARY All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- Each PIC16C5X instruction is a 12-bit word divided into gram counter is changed as a result of an instruction. an OPCODE, which specifies the instruction type and In this case, the execution takes two instruction cycles. one or more operands which further specify the opera- One instruction cycle consists of four oscillator periods. tion of the instruction. The PIC16C5X instruction set Thus, for an oscillator frequency of 4 MHz, the normal summary in Table10-2 groups the instructions into instruction execution time would be 1 s. If a condi- byte-oriented, bit-oriented, and literal and control oper- tional test is true or the program counter is changed as ations. Table10-1 shows the opcode field descriptions. a result of an instruction, the instruction execution time For byte-oriented instructions, 'f' represents a file reg- would be 2 s. ister designator and 'd' represents a destination desig- Figure10-1 shows the three general formats that the nator. The file register designator is used to specify instructions can have. All examples in the figure use which one of the 32 file registers in that bank is to be the following format to represent a hexadecimal num- used by the instruction. ber: The destination designator specifies where the result of 0xhhh the operation is to be placed. If 'd' is '0', the result is where 'h' signifies a hexadecimal digit. placed in the W register. If 'd' is '1', the result is placed in the file register specified in the instruction. FIGURE 10-1: GENERAL FORMAT FOR For bit-oriented instructions, 'b' represents a bit field INSTRUCTIONS designator which selects the number of the bit affected by the operation, while 'f' represents the number of the Byte-oriented file register operations file in which the bit is located. 11 6 5 4 0 For literal and control operations, 'k' represents an OPCODE d f (FILE #) 8or 9-bit constant or literal value. d = 0 for destination W d = 1 for destination f TABLE 10-1: OPCODE FIELD f = 5-bit file register address DESCRIPTIONS Bit-oriented file register operations Field Description 11 8 7 5 4 0 OPCODE b (BIT #) f (FILE #) f Register file address (0x00 to 0x1F) W Working register (accumulator) b = 3-bit bit address b Bit address within an 8-bit file register f = 5-bit file register address k Literal field, constant data or label Literal and control operations (except GOTO) x Don't care location (= 0 or 1) The assembler will generate code with x = 0. 11 8 7 0 It is the recommended form of use for com- OPCODE k (literal) patibility with all Microchip software tools. k = 8-bit immediate value d Destination select; d = 0 (store result in W) Literal and control operations - GOTO instruction d = 1 (store result in file register 'f') 11 9 8 0 Default is d = 1 OPCODE k (literal) label Label name TOS Top of Stack k = 9-bit immediate value PC Program Counter WDT Watchdog Timer Counter TO Time-out bit PD Power-down bit dest Destination, either the W register or the specified register file location [ ] Options ( ) Contents  Assigned to < > Register bit field  In the set of italics User defined term (font is courier) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 49

PIC16C5X TABLE 10-2: INSTRUCTION SET SUMMARY Mnemonic, 12-Bit Opcode Status Description Cycles Notes Operands Affected MSb LSb ADDWF f,d Add W and f 1 0001 11df ffff C,DC,Z 1,2,4 ANDWF f,d AND W with f 1 0001 01df ffff Z 2,4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW – Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2,4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2,4 INCF f, d Increment f 1 0010 10df ffff Z 2,4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2,4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2,4 MOVF f, d Move f 1 0010 00df ffff Z 2,4 MOVWF f Move W to f 1 0000 001f ffff None 1,4 NOP – No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2,4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2,4 SUBWF f, d Subtract W from f 1 0000 10df ffff C,DC,Z 1,2,4 SWAPF f, d Swap f 1 0011 10df ffff None 2,4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2,4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2,4 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1 (2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call subroutine 2 1001 kkkk kkkk None 1 CLRWDT k Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION k Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk None SLEEP – Go into standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO (see Section6.5 for more on program counter). 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 3: The instruction TRIS f, where f = 5, 6 or 7 causes the contents of the W register to be written to the tristate latches of PORTA, B or C respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). Preliminary DS30453E-page 50  1997-2013 Microchip Technology Inc.

PIC16C5X ADDWF Add W and f ANDWF AND W with f Syntax: [ label ] ADDWF f,d Syntax: [ label ] ANDWF f,d Operands: 0  f  31 Operands: 0  f  31 d  d  Operation: (W) + (f)  (dest) Operation: (W) .AND. (f)  (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 0001 11df ffff Encoding: 0001 01df ffff Description: Add the contents of the W register Description: The contents of the W register are and register 'f'. If 'd' is 0 the result AND’ed with register 'f'. If 'd' is 0 is stored in the W register. If 'd' is the result is stored in the W regis- '1' the result is stored back in ter. If 'd' is '1' the result is stored register 'f'. back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: ADDWF TEMP_REG, 0 Example: ANDWF TEMP_REG, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 TEMP_REG = 0xC2 TEMP_REG = 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 TEMP_REG = 0xC2 TEMP_REG = 0x02 ANDLW AND literal with W BCF Bit Clear f Syntax: [ label ] ANDLW k Syntax: [ label ] BCF f,b Operands: 0  k  255 Operands: 0  f  31 0  b  7 Operation: (W).AND. (k)  (W) Operation: 0  (f<b>) Status Affected: Z Status Affected: None Encoding: 1110 kkkk kkkk Encoding: 0100 bbbf ffff Description: The contents of the W register are AND’ed with the eight-bit literal 'k'. Description: Bit 'b' in register 'f' is cleared. The result is placed in the W regis- Words: 1 ter. Cycles: 1 Words: 1 Example: BCF FLAG_REG, 7 Cycles: 1 Before Instruction Example: ANDLW H'5F' FLAG_REG = 0xC7 Before Instruction After Instruction W = 0xA3 FLAG_REG = 0x47 After Instruction W = 0x03 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 51

PIC16C5X BSF Bit Set f BTFSS Bit Test f, Skip if Set Syntax: [ label ] BSF f,b Syntax: [ label ] BTFSS f,b Operands: 0  f  31 Operands: 0  f  31 0  b  7 0  b < 7 Operation: 1  (f<b>) Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 0101 bbbf ffff Encoding: 0111 bbbf ffff Description: Bit 'b' in register 'f' is set. Description: If bit 'b' in register 'f' is '1' then the next instruction is skipped. Words: 1 If bit 'b' is '1', then the next instruc- Cycles: 1 tion fetched during the current Example: BSF FLAG_REG, 7 instruction execution, is discarded and a NOP is executed instead, Before Instruction making this a 2-cycle instruction. FLAG_REG = 0x0A After Instruction Words: 1 FLAG_REG = 0x8A Cycles: 1(2) Example: HERE BTFSS FLAG,1 FALSE GOTO PROCESS_CODE BTFSC Bit Test f, Skip if Clear TRUE  Syntax: [ label ] BTFSC f,b   Operands: 0  f  31 0  b  7 Before Instruction PC = address (HERE) Operation: skip if (f<b>) = 0 After Instruction Status Affected: None If FLAG<1> = 0, PC = address (FALSE); Encoding: 0110 bbbf ffff if FLAG<1> = 1, Description: If bit 'b' in register 'f' is 0 then the PC = address (TRUE) next instruction is skipped. If bit 'b' is 0 then the next instruc- tion fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2-cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address (HERE) After Instruction if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address(FALSE) Preliminary DS30453E-page 52  1997-2013 Microchip Technology Inc.

PIC16C5X CALL Subroutine Call CLRW Clear W Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0  k  255 Operands: None Operation: (PC) + 1 TOS; Operation: 00h  (W); k  PC<7:0>; 1  Z (STATUS<6:5>)  PC<10:9>; Status Affected: Z 0  PC<8> Encoding: 0000 0100 0000 Status Affected: None Description: The W register is cleared. Zero bit Encoding: 1001 kkkk kkkk (Z) is set. Description: Subroutine call. First, return Words: 1 address (PC+1) is pushed onto the stack. The eight bit immediate Cycles: 1 address is loaded into PC bits Example: CLRW <7:0>. The upper bits PC<10:9> Before Instruction are loaded from STATUS<6:5>, W = 0x5A PC<8> is cleared. CALL is a two- After Instruction cycle instruction. W = 0x00 Words: 1 Z = 1 Cycles: 2 Example: HERE CALL THERE CLRWDT Clear Watchdog Timer Before Instruction PC = address (HERE) Syntax: [ label ] CLRWDT After Instruction Operands: None PC = address (THERE) Operation: 00h  WDT; TOS = address (HERE + 1) 0  WDT prescaler (if assigned); 1  TO; 1  PD CLRF Clear f Status Affected: TO, PD Syntax: [ label ] CLRF f Encoding: 0000 0000 0100 Operands: 0  f  31 Description: The CLRWDT instruction resets the Operation: 00h  (f); WDT. It also resets the prescaler, if 1  Z the prescaler is assigned to the WDT and not Timer0. Status bits Status Affected: Z TO and PD are set. Encoding: 0000 011f ffff Words: 1 Description: The contents of register 'f' are Cycles: 1 cleared and the Z bit is set. Words: 1 Example: CLRWDT Before Instruction Cycles: 1 WDT counter = ? Example: CLRF FLAG_REG After Instruction Before Instruction WDT counter = 0x00 FLAG_REG = 0x5A WDT prescaler = 0 After Instruction TO = 1 FLAG_REG = 0x00 PD = 1 Z = 1 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 53

PIC16C5X COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: (f)  (dest) Operation: (f) – 1  d; skip if result = 0 Status Affected: Z Status Affected: None Encoding: 0010 01df ffff Encoding: 0010 11df ffff Description: The contents of register 'f' are Description: The contents of register 'f' are dec- complemented. If 'd' is 0 the result remented. If 'd' is 0 the result is is stored in the W register. If 'd' is 1 placed in the W register. If 'd' is 1 the result is stored back in the result is placed back in register 'f'. register 'f'. If the result is 0, the next instruc- Words: 1 tion, which is already fetched, is Cycles: 1 discarded and a NOP is executed Example: COMF REG1,0 instead making it a two-cycle instruction. Before Instruction REG1 = 0x13 Words: 1 After Instruction Cycles: 1(2) REG1 = 0x13 Example: HERE DECFSZ CNT, 1 W = 0xEC GOTO LOOP CONTINUE • • DECF Decrement f • Syntax: [ label ] DECF f,d Before Instruction Operands: 0  f  31 PC = address(HERE) d  [0,1] After Instruction CNT = CNT - 1; Operation: (f) – 1  (dest) if CNT = 0, Status Affected: Z PC = address (CONTINUE); if CNT  0, Encoding: 0000 11df ffff PC = address (HERE+1) Description: Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example: DECF CNT, 1 Before Instruction CNT = 0x01 Z = 0 After Instruction CNT = 0x00 Z = 1 Preliminary DS30453E-page 54  1997-2013 Microchip Technology Inc.

PIC16C5X GOTO Unconditional Branch INCFSZ Increment f, Skip if 0 Syntax: [ label ] GOTO k Syntax: [ label ] INCFSZ f,d Operands: 0  k  511 Operands: 0  f  31 d  [0,1] Operation: k  PC<8:0>; STATUS<6:5>  PC<10:9> Operation: (f) + 1  (dest), skip if result = 0 Status Affected: None Status Affected: None Encoding: 101k kkkk kkkk Encoding: 0011 11df ffff Description: GOTO is an unconditional branch. Description: The contents of register 'f' are The 9-bit immediate value is incremented. If 'd' is 0 the result is loaded into PC bits <8:0>. The placed in the W register. If 'd' is 1 upper bits of PC are loaded from the result is placed back in STATUS<6:5>. GOTO is a two- register 'f'. cycle instruction. If the result is 0, then the next instruction, which is already Words: 1 fetched, is discarded and a NOP is Cycles: 2 executed instead making it a two- Example: GOTO THERE cycle instruction. After Instruction Words: 1 PC = address (THERE) Cycles: 1(2) Example: HERE INCFSZ CNT, 1 GOTO LOOP INCF Increment f CONTINUE • Syntax: [ label ] INCF f,d • • Operands: 0  f  31 d  [0,1] Before Instruction PC = address (HERE) Operation: (f) + 1  (dest) After Instruction Status Affected: Z CNT = CNT + 1; if CNT = 0, Encoding: 0010 10df ffff PC = address (CONTINUE); Description: The contents of register 'f' are if CNT  0, incremented. If 'd' is 0 the result is PC = address (HERE +1) placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Example: INCF CNT, 1 Before Instruction CNT = 0xFF Z = 0 After Instruction CNT = 0x00 Z = 1 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 55

PIC16C5X IORLW Inclusive OR literal with W MOVF Move f Syntax: [ label ] IORLW k Syntax: [ label ] MOVF f,d Operands: 0  k  255 Operands: 0  f  31 d  [0,1] Operation: (W) .OR. (k)  (W) Operation: (f)  (dest) Status Affected: Z Status Affected: Z Encoding: 1101 kkkk kkkk Encoding: 0010 00df ffff Description: The contents of the W register are OR’ed with the eight bit literal 'k'. Description: The contents of register 'f' is The result is placed in the W regis- moved to destination 'd'. If 'd' is 0, ter. destination is the W register. If 'd' is 1, the destination is file Words: 1 register 'f'. 'd' is 1 is useful to test a Cycles: 1 file register since status flag Z is Example: IORLW 0x35 affected. Before Instruction Words: 1 W = 0x9A Cycles: 1 After Instruction Example: MOVF FSR, 0 W = 0xBF Z = 0 After Instruction W = value in FSR register IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d MOVLW Move Literal to W Operands: 0  f  31 Syntax: [ label ] MOVLW k d  [0,1] Operands: 0  k  255 Operation: (W).OR. (f)  (dest) Operation: k  (W) Status Affected: Z Status Affected: None Encoding: 0001 00df ffff Encoding: 1100 kkkk kkkk Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is Description: The eight bit literal 'k' is loaded into placed in the W register. If 'd' is 1 the W register. the result is placed back in Words: 1 register 'f'. Cycles: 1 Words: 1 Example: MOVLW 0x5A Cycles: 1 After Instruction Example: IORWF RESULT, 0 W = 0x5A Before Instruction RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 Z = 0 Preliminary DS30453E-page 56  1997-2013 Microchip Technology Inc.

PIC16C5X MOVWF Move W to f OPTION Load OPTION Register Syntax: [ label ] MOVWF f Syntax: [ label ] OPTION Operands: 0  f  31 Operands: None Operation: (W)  (f) Operation: (W)  OPTION Status Affected: None Status Affected: None Encoding: 0000 0000 0010 Encoding: 0000 001f ffff Description: The content of the W register is Description: Move data from the W register to loaded into the OPTION register. register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example OPTION Example: MOVWF TEMP_REG Before Instruction Before Instruction W = 0x07 TEMP_REG = 0xFF After Instruction W = 0x4F OPTION = 0x07 After Instruction TEMP_REG = 0x4F W = 0x4F RETLW Return with Literal in W Syntax: [ label ] RETLW k NOP No Operation Operands: 0  k  255 Syntax: [ label ] NOP Operation: k  (W); TOS  PC Operands: None Status Affected: None Operation: No operation Encoding: 1000 kkkk kkkk Status Affected: None Description: The W register is loaded with the Encoding: 0000 0000 0000 eight bit literal 'k'. The program Description: No operation. counter is loaded from the top of the stack (the return address). This Words: 1 is a two-cycle instruction. Cycles: 1 Words: 1 Example: NOP Cycles: 2 Example: CALL TABLE ;W contains ;table offset ;value. • ;W now has table • ;value. TABLE • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 57

PIC16C5X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: 0011 01df ffff Encoding: 0011 00df ffff Description: The contents of register 'f' are Description: The contents of register 'f' are rotated one bit to the left through rotated one bit to the right through the Carry Flag (STATUS<0>). If 'd' the Carry Flag (STATUS<0>). If 'd' is 0 the result is placed in the W is 0 the result is placed in the W register. If 'd' is 1 the result is register. If 'd' is 1 the result is stored back in placed back in register 'f'. register 'f'. C register 'f' C register 'f' Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: RLF REG1,0 Example: RRF REG1,0 Before Instruction Before Instruction REG1 = 1110 0110 REG1 = 1110 0110 C = 0 C = 0 After Instruction After Instruction REG1 = 1110 0110 REG1 = 1110 0110 W = 1100 1100 W = 0111 0011 C = 1 C = 0 SLEEP Enter SLEEP Mode Syntax: [label] SLEEP Operands: None Operation: 00h  WDT; 0  WDT prescaler; if assigned 1  TO; 0  PD Status Affected: TO, PD Encoding: 0000 0000 0011 Description: Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT and its pres- caler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See section on SLEEP for more details. Words: 1 Cycles: 1 Example: SLEEP Preliminary DS30453E-page 58  1997-2013 Microchip Technology Inc.

PIC16C5X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [label] SUBWF f,d Syntax: [ label ] SWAPF f,d Operands: 0 f 31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: (f) – (W) dest) Operation: (f<3:0>)  (dest<7:4>); (f<7:4>)  (dest<3:0>) Status Affected: C, DC, Z Status Affected: None Encoding: 0000 10df ffff Encoding: 0011 10df ffff Description: Subtract (2’s complement method) the W register from register 'f'. If 'd' Description: The upper and lower nibbles of is 0 the result is stored in the W register 'f' are exchanged. If 'd' is 0 register. If 'd' is 1 the result is the result is placed in W register. If stored back in register 'f'. 'd' is 1 the result is placed in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example 1: SUBWF REG1, 1 Example SWAPF REG1, 0 Before Instruction REG1 = 3 Before Instruction W = 2 REG1 = 0xA5 C = ? After Instruction After Instruction REG1 = 0xA5 REG1 = 1 W = 0x5A W = 2 C = 1 ; result is positive Example 2: TRIS Load TRIS Register Before Instruction REG1 = 2 Syntax: [ label ] TRIS f W = 2 Operands: f = 5, 6 or 7 C = ? Operation: (W)  TRIS register f After Instruction Status Affected: None REG1 = 0 W = 2 Encoding: 0000 0000 0fff C = 1 ; result is zero Description: TRIS register 'f' (f = 5, 6, or 7) is Example 3: loaded with the contents of the W Before Instruction register. REG1 = 1 Words: 1 W = 2 C = ? Cycles: 1 After Instruction Example TRIS PORTB REG1 = 0xFF Before Instruction W = 2 W = 0xA5 C = 0 ; result is negative After Instruction TRISB = 0xA5 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 59

PIC16C5X XORLW Exclusive OR literal with W Syntax: [label] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Encoding: 1111 kkkk kkkk Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W regis- ter. Words: 1 Cycles: 1 Example: XORLW 0xAF Before Instruction W = 0xB5 After Instruction W = 0x1A XORWF Exclusive OR W with f Syntax: [ label ] XORWF f,d Operands: 0  f  31 d  [0,1] Operation: (W) .XOR. (f) dest) Status Affected: Z Encoding: 0001 10df ffff Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W regis- ter. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Example XORWF REG,1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 Preliminary DS30453E-page 60  1997-2013 Microchip Technology Inc.

PIC16C5X 11.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: • Edit your source files (either assembly or ‘C’) The PIC® microcontrollers are supported with a full range of hardware and software development tools: • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (auto- • Integrated Development Environment matically updates all project information) - MPLAB® IDE Software • Debug using: • Assemblers/Compilers/Linkers - source files - MPASMTM Assembler - absolute listing file - MPLAB C17 and MPLAB C18 C Compilers - machine code - MPLINKTM Object Linker/ The ability to use MPLAB IDE with multiple debugging MPLIBTM Object Librarian tools allows users to easily switch from the cost- • Simulators effective simulator to a full-featured emulator with - MPLAB SIM Software Simulator minimal retraining. • Emulators 11.2 MPASM Assembler - MPLAB ICE 2000 In-Circuit Emulator - ICEPIC™ In-Circuit Emulator The MPASM assembler is a full-featured universal • In-Circuit Debugger macro assembler for all PIC MCUs. - MPLAB ICD The MPASM assembler has a command line interface • Device Programmers and a Windows shell. It can be used as a stand-alone - PRO MATE® II Universal Device Programmer application on a Windows 3.x or greater system, or it - PICSTART® Plus Entry-Level Development can be used through MPLAB IDE. The MPASM assem- bler generates relocatable object files for the MPLINK Programmer object linker, Intel® standard HEX files, MAP files to • Low Cost Demonstration Boards detail memory usage and symbol reference, an abso- - PICDEMTM 1 Demonstration Board lute LST file that contains source lines and generated - PICDEM 2 Demonstration Board machine code, and a COD file for debugging. - PICDEM 3 Demonstration Board The MPASM assembler features include: - PICDEM 17 Demonstration Board • Integration into MPLAB IDE projects. - KEELOQ® Demonstration Board • User-defined macros to streamline assembly code. 11.1 MPLAB Integrated Development • Conditional assembly for multi-purpose source Environment Software files. The MPLAB IDE software brings an ease of software • Directives that allow complete control over the development previously unseen in the 8-bit microcon- assembly process. troller market. The MPLAB IDE is a Windows®-based application that contains: 11.3 MPLAB C17 and MPLAB C18 C Compilers • An interface to debugging tools - simulator The MPLAB C17 and MPLAB C18 Code Development - programmer (sold separately) Systems are complete ANSI ‘C’ compilers for - emulator (sold separately) Microchip’s PIC17CXXX and PIC18CXXX family of - in-circuit debugger (sold separately) microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not • A full-featured editor found with other compilers. • A project manager For easier source level debugging, the compilers pro- • Customizable toolbar and key mapping vide symbol information that is compatible with the • A status bar MPLAB IDE memory display. • On-line help Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 61

PIC16C5X 11.4 MPLINK Object Linker/ 11.6 MPLAB ICE High Performance MPLIB Object Librarian Universal In-Circuit Emulator with MPLAB IDE The MPLINK object linker combines relocatable objects created by the MPASM assembler and the The MPLAB ICE universal in-circuit emulator is intended MPLAB C17 and MPLAB C18 C compilers. It can also to provide the product development engineer with a link relocatable objects from pre-compiled libraries, complete microcontroller design tool set for PIC micro- using directives from a linker script. controllers (MCUs). Software control of the MPLAB ICE The MPLIB object librarian is a librarian for pre- in-circuit emulator is provided by the MPLAB Integrated compiled code to be used with the MPLINK object Development Environment (IDE), which allows editing, linker. When a routine from a library is called from building, downloading and source debugging from a another source file, only the modules that contain that single environment. routine will be linked in with the application. This allows The MPLAB ICE 2000 is a full-featured emulator sys- large libraries to be used efficiently in many different tem with enhanced trace, trigger and data monitoring applications. The MPLIB object librarian manages the features. Interchangeable processor modules allow the creation and modification of library files. system to be easily reconfigured for emulation of differ- The MPLINK object linker features include: ent processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to • Integration with MPASM assembler and MPLAB support new PIC microcontrollers. C17 and MPLAB C18 C compilers. The MPLAB ICE in-circuit emulator system has been • Allows all memory areas to be defined as sections designed as a real-time emulation system, with to provide link-time flexibility. advanced features that are generally found on more The MPLIB object librarian features include: expensive development tools. The PC platform and • Easier linking because single libraries can be Microsoft® Windows environment were chosen to best included instead of many smaller files. make these features available to you, the end user. • Helps keep code maintainable by grouping 11.7 ICEPIC In-Circuit Emulator related modules together. • Allows libraries to be created and modules to be The ICEPIC low cost, in-circuit emulator is a solution added, listed, replaced, deleted or extracted. for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit One- 11.5 MPLAB SIM Software Simulator Time-Programmable (OTP) microcontrollers. The mod- ular system can support different subsets of PIC16C5X The MPLAB SIM software simulator allows code devel- or PIC16CXXX products through the use of inter- opment in a PC-hosted environment by simulating the changeable personality modules, or daughter boards. PIC series microcontrollers on an instruction level. On The emulator is capable of emulating without target any given instruction, the data areas can be examined application circuitry being present. or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execu- tion can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debug- ging using the MPLAB C17 and the MPLAB C18 C com- pilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi- project software development tool. Preliminary DS30453E-page 62  1997-2013 Microchip Technology Inc.

PIC16C5X 11.8 MPLAB ICD In-Circuit Debugger 11.11 PICDEM 1 Low Cost PIC MCU Demonstration Board Microchip's In-Circuit Debugger, MPLAB ICD, is a pow- erful, low cost, run-time development tool. This tool is The PICDEM 1 demonstration board is a simple board based on the FLASH PIC MCUs and can be used to which demonstrates the capabilities of several of develop for this and other PIC microcontrollers. The Microchip’s microcontrollers. The microcontrollers sup- MPLAB ICD utilizes the in-circuit debugging capability ported are: PIC16C5X (PIC16C54 to PIC16C58A), built into the FLASH devices. This feature, along with PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, Microchip's In-Circuit Serial ProgrammingTM protocol, PIC17C42, PIC17C43 and PIC17C44. All necessary offers cost-effective in-circuit FLASH debugging from hardware and software is included to run basic demo the graphical user interface of the MPLAB Integrated programs. The user can program the sample microcon- Development Environment. This enables a designer to trollers provided with the PICDEM 1 demonstration develop and debug source code by watching variables, board on a PROMATE II device programmer, or a single-stepping and setting break points. Running at PICSTART Plus development programmer, and easily full speed enables testing hardware in real-time. test firmware. The user can also connect the PICDEM1 demonstration board to the MPLAB ICE in- 11.9 PRO MATE II Universal Device circuit emulator and download the firmware to the emu- Programmer lator for testing. A prototype area is available for the user to build some additional hardware and connect it The PRO MATE II universal device programmer is a to the microcontroller socket(s). Some of the features full-featured programmer, capable of operating in include an RS-232 interface, a potentiometer for simu- Stand-alone mode, as well as PC-hosted mode. The lated analog input, push button switches and eight PRO MATE II device programmer is CE compliant. LEDs connected to PORTB. The PRO MATE II device programmer has program- mable VDD and VPP supplies, which allow it to verify 11.12 PICDEM 2 Low Cost PIC16CXX programmed memory at VDD min and VDD max for max- Demonstration Board imum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a The PICDEM 2 demonstration board is a simple dem- modular detachable socket assembly to support various onstration board that supports the PIC16C62, package types. In Stand-alone mode, the PRO MATE II PIC16C64, PIC16C65, PIC16C73 and PIC16C74 device programmer can read, verify, or program PIC microcontrollers. All the necessary hardware and soft- devices. It can also set code protection in this mode. ware is included to run the basic demonstration pro- grams. The user can program the sample 11.10 PICSTART Plus Entry Level microcontrollers provided with the PICDEM2 demon- Development Programmer stration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and The PICSTART Plus development programmer is an easily test firmware. The MPLAB ICE in-circuit emula- easy-to-use, low cost, prototype programmer. It con- tor may also be used with the PICDEM 2 demonstration nects to the PC via a COM (RS-232) port. MPLAB board to test firmware. A prototype area has been pro- Integrated Development Environment software makes vided to the user for adding additional hardware and using the programmer simple and efficient. connecting it to the microcontroller socket(s). Some of The PICSTART Plus development programmer sup- the features include a RS-232 interface, push button ports all PIC devices with up to 40 pins. Larger pin switches, a potentiometer for simulated analog input, a count devices, such as the PIC16C92X and serial EEPROM to demonstrate usage of the I2CTM bus PIC17C76X, may be supported with an adapter socket. and separate headers for connection to an LCD The PICSTART Plus development programmer is CE module and a keypad. compliant. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 63

PIC16C5X 11.13 PICDEM 3 Low Cost PIC16CXXX 11.14 PICDEM 17 Demonstration Board Demonstration Board The PICDEM 17 demonstration board is an evaluation The PICDEM 3 demonstration board is a simple dem- board that demonstrates the capabilities of several onstration board that supports the PIC16C923 and Microchip microcontrollers, including PIC17C752, PIC16C924 in the PLCC package. It will also support PIC17C756A, PIC17C762 and PIC17C766. All neces- future 44-pin PLCC microcontrollers with an LCD Mod- sary hardware is included to run basic demo programs, ule. All the necessary hardware and software is which are supplied on a 3.5-inch disk. A programmed included to run the basic demonstration programs. The sample is included and the user may erase it and user can program the sample microcontrollers pro- program it with the other sample programs using the vided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or the PICSTART PRO MATE II device programmer, or a PICSTART Plus Plus development programmer, and easily debug and development programmer with an adapter socket, and test the sample code. In addition, the PICDEM17 dem- easily test firmware. The MPLAB ICE in-circuit emula- onstration board supports downloading of programs to tor may also be used with the PICDEM 3 demonstration and executing out of external FLASH memory on board. board to test firmware. A prototype area has been pro- The PICDEM 17 demonstration board is also usable vided to the user for adding hardware and connecting it with the MPLAB ICE in-circuit emulator, or the to the microcontroller socket(s). Some of the features PICMASTER emulator and all of the sample programs include a RS-232 interface, push button switches, a can be run and modified using either emulator. Addition- potentiometer for simulated analog input, a thermistor ally, a generous prototype area is available for user and separate headers for connection to an external hardware. LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 11.15 KEELOQ Evaluation and commons and 12 segments, that is capable of display- Programming Tools ing time, temperature and day of the week. The KEELOQ evaluation and programming tools support PICDEM 3 demonstration board provides an additional Microchip’s HCS Secure Data Products. The HCS eval- RS-232 interface and Windows software for showing uation kit includes a LCD display to show changing the demultiplexed LCD signals on a PC. A simple serial codes, a decoder to decode transmissions and a pro- interface allows the user to construct a hardware gramming interface to program test transmitters. demultiplexer for the LCD signals. Preliminary DS30453E-page 64  1997-2013 Microchip Technology Inc.

PIC16C5X TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP 7. 0152PCM  6, 7 7 4, 7 XXXFRCM     73, 2, 7 5, XXXSCH     4, 6 6 XXC39 63, //XXXXCC4522   C62, 6 1 C XXXF81CIP         h PI wit 1) 2XXC81CIP        00 4 6 1 V D XX7C71CIP        er ( g g u X4C71CIP        eb D uit XX9C61CIP        Circ n- D I XX8F61CIP       C ® I B A L X8C61CIP        MP e h e t XX7C61CIP       us o w t o X7C61CIP     *   † † n h o n o X26F61CIP   ** ** ** mati or nf XXXC61CIP        m for i o c p. X6C61CIP     *   † hi c o cr mi XX0X50XC0C462111CCCIIPPIP ®MPLAB IntegratedDevelopment Environment ®MPLAB C17 C Compiler ®MPLAB C18 C Compiler TMMPASM Assembler/ TMMPLINKObject Linker ®MPLAB ICE In-Circuit Emulator TMICEPIC In-Circuit Emulator ®MPLAB ICD In-Circuit Debugger ®PICSTART Plus Entry LevelDevelopment Programmer ®PRO MATE II Universal Device Programmer TMPICDEM 1 Demonstration Board TMPICDEM 2 Demonstration Board TMPICDEM 3 Demonstration Board TMPICDEM 14A Demonstration Board TMPICDEM 17 Demonstration Board ® KLEvaluation KitEEOQ ®KL Transponder KitEEOQ TMmicroID Programmer’s Kit TM125 kHz microID Developer’s Kit TM125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision TMmicroID Developer’s Kit MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site at www.Contact Microchip Technology Inc. for availability date.Development tool is available on select devices. slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***† Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 65

PIC16C5X NOTES: Preliminary DS30453E-page 66  1997-2013 Microchip Technology Inc.

PIC16C5X 12.0 ELECTRICAL CHARACTERISTICS - PIC16C54A Absolute Maximum Ratings(†) Ambient Temperature under bias.....................................................................................................–55°C to +125°C Storage Temperature.......................................................................................................................–65°C to +150°C Voltage on VDD with respect to VSS..........................................................................................................0V to +7.5V Voltage on MCLR with respect to VSS(1)....................................................................................................0V to +14V Voltage on all other pins with respect to VSS............................................................................–0.6V to (VDD + 0.6V) Total power dissipation(2)...............................................................................................................................800 mW Max. current out of VSS pin.............................................................................................................................150 mA Max. current into VDD pin................................................................................................................................100 mA Max. current into an input pin (T0CKI only)....................................................................................................±500 A Input clamp current, IIK (VI < 0 or VI > VDD)....................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................±20 mA Max. output current sunk by any I/O pin...........................................................................................................25 mA Max. output current sourced by any I/O pin......................................................................................................20 mA Max. output current sourced by a single I/O port (PORTA, B or C)..................................................................40 mA Max. output current sunk by a single I/O port (PORTA, B or C)........................................................................50 mA Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50 to 100  should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS. 2: Power Dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 67

PIC16C5X 12.1 DC Characteristics:PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial) PIC16C54/55/56/57-RC, XT, 10, HS, LP Standard Operating Conditions (unless otherwise specified) (Commercial) Operating Temperature 0°C  TA  +70°C for commercial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. D001 VDD Supply Voltage PIC16C5X-RC 3.0 — 6.25 V PIC16C5X-XT 3.0 — 6.25 V PIC16C5X-10 4.5 — 5.5 V PIC16C5X-HS 4.5 — 5.5 V PIC16C5X-LP 2.5 — 6.25 V D002 VDR RAM Data Retention Voltage(1) 1.5* — V Device in SLEEP Mode D003 VPOR VDD Start Voltage to ensure VSS — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset D010 IDD Supply Current(2) PIC16C5X-RC(3) — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V PIC16C5X-XT — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V PIC16C5X-10 — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V PIC16C5X-HS — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V PIC16C5X-HS — 9.0 20 mA FOSC = 20 MHz, VDD = 5.5V PIC16C5X-LP — 15 32 A FOSC = 32 kHz, VDD = 3.0V, WDT disabled D020 IPD Power-down Current(2) — 4.0 12 A VDD = 3.0V, WDT enabled — 0.6 9 A VDD = 3.0V, WDT disabled * These parameters are characterized but not tested. † Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR=VDD/2REXT(mA) with REXT in k. Preliminary DS30453E-page 68  1997-2013 Microchip Technology Inc.

PIC16C5X 12.2 DC Characteristics:PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial) PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI Standard Operating Conditions (unless otherwise specified) (Industrial) Operating Temperature –40°C  TA  +85°C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. D001 VDD Supply Voltage PIC16C5X-RCI 3.0 — 6.25 V PIC16C5X-XTI 3.0 — 6.25 V PIC16C5X-10I 4.5 — 5.5 V PIC16C5X-HSI 4.5 — 5.5 V PIC16C5X-LPI 2.5 — 6.25 V D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D003 VPOR VDD Start Voltage to ensure — VSS — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset D010 IDD Supply Current(2) PIC16C5X-RCI(3) — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V PIC16C5X-XTI — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V PIC16C5X-10I — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V PIC16C5X-HSI — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V PIC16C5X-HSI — 9.0 20 mA FOSC = 20 MHz, VDD = 5.5V PIC16C5X-LPI — 15 40 A FOSC = 32 kHz, VDD = 3.0V, WDT disabled D020 IPD Power-down Current(2) — 4.0 14 A VDD = 3.0V, WDT enabled — 0.6 12 A VDD = 3.0V, WDT disabled * These parameters are characterized but not tested. † Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR=VDD/2REXT(mA) with REXT in k. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 69

PIC16C5X 12.3 DC Characteristics:PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended) PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE Standard Operating Conditions (unless otherwise specified) (Extended) Operating Temperature –40°C  TA  +125°C for extended Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. D001 VDD Supply Voltage PIC16C5X-RCE 3.25 — 6.0 V PIC16C5X-XTE 3.25 — 6.0 V PIC16C5X-10E 4.5 — 5.5 V PIC16C5X-HSE 4.5 — 5.5 V PIC16C5X-LPE 2.5 — 6.0 V D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D003 VPOR VDD Start Voltage to ensure — VSS — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset D010 IDD Supply Current(2) PIC16C5X-RCE(3) — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V PIC16C5X-XTE — 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V PIC16C5X-10E — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V PIC16C5X-HSE — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V PIC16C5X-HSE — 9.0 20 mA FOSC = 16 MHz, VDD = 5.5V PIC16C5X-LPE — 19 55 A FOSC = 32 kHz, VDD = 3.25V, WDT disabled D020 IPD Power-down Current(2) — 5.0 22 A VDD = 3.25V, WDT enabled — 0.8 18 A VDD = 3.25V, WDT disabled * These parameters are characterized but not tested. † Data in “Typ” column is based on characterization results at 25C.This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR=VDD/2REXT(mA) with REXT in k. Preliminary DS30453E-page 70  1997-2013 Microchip Technology Inc.

PIC16C5X 12.4 DC Characteristics:PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial) PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature 0°C  TA  +70°C for commercial –40°C  TA  +85°C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. D030 VIL Input Low Voltage I/O ports VSS — 0.2 VDD V Pin at hi-impedance MCLR (Schmitt Trigger) VSS — 0.15 VDD V T0CKI (Schmitt Trigger) VSS — 0.15 VDD V OSC1 (Schmitt Trigger) VSS — 0.15 VDD V PIC16C5X-RC only(3) OSC1 (Schmitt Trigger) VSS — 0.3 VDD V PIC16C5X-XT, 10, HS, LP D040 VIH Input High Voltage I/O ports 0.45 VDD — VDD V For all VDD(4) I/O ports 2.0 — VDD V 4.0V < VDD  5.5V(4) I/O ports 0.36 VDD — VDD V VDD > 5.5V MCLR (Schmitt Trigger) 0.85 VDD — VDD V T0CKI (Schmitt Trigger) 0.85 VDD — VDD V OSC1 (Schmitt Trigger) 0.85 VDD — VDD V PIC16C5X-RC only(3) OSC1 (Schmitt Trigger) 0.7 VDD — VDD V PIC16C5X-XT, 10, HS, LP D050 VHYS Hysteresis of Schmitt 0.15 VDD* — — V Trigger inputs D060 IIL Input Leakage Current(1,2) For VDD  5.5V: I/O ports –1 0.5 +1 A VSS  VPIN  VDD, pin at hi-impedance MCLR –5 — — A VPIN = VSS + 0.25V MCLR — 0.5 +5 A VPIN = VDD T0CKI –3 0.5 +3 A VSS  VPIN  VDD OSC1 –3 0.5 +3 A VSS  VPIN  VDD, PIC16C5X-XT, 10, HS, LP D080 VOL Output Low Voltage I/O ports — — 0.6 V IOL = 8.7 mA, VDD = 4.5V OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, PIC16C5X-RC D090 VOH Output High Voltage(2) I/O ports VDD – 0.7 — — V IOH = –5.4 mA, VDD = 4.5V OSC2/CLKOUT VDD – 0.7 — — V IOH = –1.0 mA, VDD = 4.5V, PIC16C5X-RC * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 4: The user may use the better of the two specifications. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 71

PIC16C5X 12.5 DC Characteristics:PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. D030 VIL Input Low Voltage I/O ports Vss — 0.15 VDD V Pin at hi-impedance MCLR (Schmitt Trigger) Vss — 0.15 VDD V T0CKI (Schmitt Trigger) Vss — 0.15 VDD V OSC1 (Schmitt Trigger) Vss — 0.15 VDD V PIC16C5X-RC only(3) OSC1 (Schmitt Trigger) Vss — 0.3 VDD V PIC16C5X-XT, 10, HS, LP D040 VIH Input High Voltage I/O ports 0.45 VDD — VDD V For all VDD(4) I/O ports 2.0 — VDD V 4.0V < VDD  5.5V(4) I/O ports 0.36 VDD — VDD V VDD > 5.5 V MCLR (Schmitt Trigger) 0.85 VDD — VDD V T0CKI (Schmitt Trigger) 0.85 VDD — VDD V OSC1 (Schmitt Trigger) 0.85 VDD — VDD V PIC16C5X-RC only(3) OSC1 (Schmitt Trigger) 0.7 VDD — VDD V PIC16C5X-XT, 10, HS, LP D050 VHYS Hysteresis of Schmitt 0.15 VDD* — — V Trigger inputs D060 IIL Input Leakage Current (1,2) For VDD  5.5 V: I/O ports –1 0.5 +1 A VSS  VPIN  VDD, pin at hi-impedance MCLR –5 — — A VPIN = VSS + 0.25V MCLR — 0.5 +5 A VPIN = VDD T0CKI –3 0.5 +3 A VSS  VPIN  VDD OSC1 –3 0.5 +3 A VSS  VPIN  VDD, PIC16C5X-XT, 10, HS, LP D080 VOL Output Low Voltage I/O ports — — 0.6 V IOL = 8.7 mA, VDD = 4.5V OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, PIC16C5X-RC D090 VOH Output High Voltage(2) I/O ports VDD – 0.7 — — V IOH = –5.4 mA, VDD = 4.5V OSC2/CLKOUT VDD – 0.7 — — V IOH = –1.0 mA, VDD = 4.5V, PIC16C5X-RC * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 4: The user may use the better of the two specifications. Preliminary DS30453E-page 72  1997-2013 Microchip Technology Inc.

PIC16C5X 12.6 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 12-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54/55/56/57 Pin CL = 50 pF for all pins and OSC2 for RC mode CL 0 - 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 73

PIC16C5X 12.7 Timing Diagrams and Specifications FIGURE 12-2: EXTERNAL CLOCK TIMING - PIC16C54/55/56/57 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 1A FOSC External CLKIN Frequency(1) DC — 4.0 MHz XT OSC mode DC — 10 MHz 10 MHz mode DC — 20 MHz HS OSC mode (Comm/Ind) DC — 16 MHz HS OSC mode (Ext) DC — 40 kHz LP OSC mode Oscillator Frequency(1) DC — 4.0 MHz RC OSC mode 0.1 — 4.0 MHz XT OSC mode 4.0 — 10 MHz 10 MHz mode 4.0 — 20 MHz HS OSC mode (Comm/Ind) 4.0 — 16 MHz HS OSC mode (Ext) DC — 40 kHz LP OSC mode * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary DS30453E-page 74  1997-2013 Microchip Technology Inc.

PIC16C5X TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 1 TOSC External CLKIN Period(1) 250 — — ns XT OSC mode 100 — — ns 10 MHz mode 50 — — ns HS OSC mode (Comm/Ind) 62.5 — — ns HS OSC mode (Ext) 25 — — s LP OSC mode Oscillator Period(1) 250 — — ns RC OSC mode 250 — 10,000 ns XT OSC mode 100 — 250 ns 10 MHz mode 50 — 250 ns HS OSC mode (Comm/Ind) 62.5 — 250 ns HS OSC mode (Ext) 25 — — s LP OSC mode 2 Tcy Instruction Cycle Time(2) — 4/FOSC — — 3 TosL, Clock in (OSC1) Low or High 85* — — ns XT oscillator TosH Time 20* — — ns HS oscillator 2.0* — — s LP oscillator 4 TosR, Clock in (OSC1) Rise or Fall — — 25* ns XT oscillator TosF Time — — 25* ns HS oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 75

PIC16C5X FIGURE 12-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57 Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin Old Value New Value (output) 20, 21 Note: Please refer to Figure12-1 for load conditions. TABLE 12-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units No. 10 TosH2ckL OSC1 to CLKOUT(1) — 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(1) — 15 30** ns 12 TckR CLKOUT rise time(1) — 5.0 15** ns 13 TckF CLKOUT fall time(1) — 5.0 15** ns 14 TckL2ioV CLKOUT to Port out valid(1) — — 40** ns 15 TioV2ckH Port in valid before CLKOUT(1) 0.25 TCY+30* — — ns 16 TckH2ioI Port in hold after CLKOUT(1) 0* — — ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(2) — — 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1 TBD — — ns (I/O in setup time) 20 TioR Port output rise time(2) — 10 25** ns 21 TioF Port output fall time(2) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x Tosc. 2: Please refer to Figure12-1 for load conditions. Preliminary DS30453E-page 76  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C54/55/56/57 VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O pin (Note 1) Note 1: Please refer to Figure12-1 for load conditions. TABLE 12-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param No. Symbol Characteristic Min Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 100* — — ns VDD = 5.0V 31 Twdt Watchdog Timer Time-out Period 9.0* 18* 30* ms VDD = 5.0V (Comm) (No Prescaler) 32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Comm) 34 TioZ I/O Hi-impedance from MCLR Low — — 100* ns * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 77

PIC16C5X FIGURE 12-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57 T0CKI 40 41 42 Note: Please refer to Figure12-1 for load conditions. TABLE 12-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary DS30453E-page 78  1997-2013 Microchip Technology Inc.

PIC16C5X 13.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A Absolute Maximum Ratings(†) Ambient Temperature under bias.....................................................................................................–55°C to +125°C Storage Temperature.......................................................................................................................–65°C to +150°C Voltage on VDD with respect to VSS............................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS(1)......................................................................................................0 to +14V Voltage on all other pins with respect to VSS............................................................................–0.6V to (VDD + 0.6V) Total power dissipation(2)...............................................................................................................................800 mW Max. current out of VSS pin.............................................................................................................................150 mA Max. current into VDD pin..................................................................................................................................50 mA Max. current into an input pin (T0CKI only)500 A Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (V0 < 0 or V0 > VDD)20 mA Max. output current sunk by any I/O pin...........................................................................................................25 mA Max. output current sourced by any I/O pin......................................................................................................20 mA Max. output current sourced by a single I/O port (PORTA or B).......................................................................40 mA Max. output current sunk by a single I/O port (PORTA or B)............................................................................50 mA Note 1: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus, a series resistor of 50 to 100  should be used when applying a low level to the MCLR pin rather than pulling this pin directly to Vss. 2: Power Dissipation is calculated as follows: PDIS = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 79

PIC16C5X 13.1 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial) PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial) PIC16LCR54A-04 Standard Operating Conditions (unless otherwise specified) PIC16LCR54A-04I Operating Temperature 0°C  TA  +70°C for commercial (Commercial, Industrial) –40°C  TA  +85°C for industrial PIC16CR54A-04, 10, 20 Standard Operating Conditions (unless otherwise specified) PIC16CR54A-04I, 10I, 20I Operating Temperature 0°C  TA  +70°C for commercial (Commercial, Industrial) –40°C  TA  +85°C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. VDD Supply Voltage D001 PIC16LCR54A 2.0 — 6.25 V D001 PIC16CR54A 2.5 — 6.25 V RC and XT modes D001A 4.5 — 5.5 V HS mode D002 VDR RAM Data Retention — 1.5* — V Device in SLEEP mode Voltage(1) D003 VPOR VDD Start Voltage to ensure — VSS — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset IDD Supply Current(2) D005 PICLCR54A — 10 20 A Fosc = 32 kHz, VDD = 2.0V — — 70 A Fosc = 32 kHz, VDD = 6.0V D005A RC(3) and XT modes: PIC16CR54A — 2.0 3.6 mA FOSC = 4.0 MHz, VDD = 6.0V — 0.8 1.8 mA FOSC = 4.0 MHz, VDD = 3.0V — 90 350 A FOSC = 200 kHz, VDD = 2.5V HS mode: — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V — 9.0 20 mA FOSC = 20 MHz, VDD = 5.5V Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR= VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR= VDD/2REXT (mA) with REXT in k. Preliminary DS30453E-page 80  1997-2013 Microchip Technology Inc.

PIC16C5X 13.1 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial) PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial) PIC16LCR54A-04 Standard Operating Conditions (unless otherwise specified) PIC16LCR54A-04I Operating Temperature 0°C  TA  +70°C for commercial (Commercial, Industrial) –40°C  TA  +85°C for industrial PIC16CR54A-04, 10, 20 Standard Operating Conditions (unless otherwise specified) PIC16CR54A-04I, 10I, 20I Operating Temperature 0°C  TA  +70°C for commercial (Commercial, Industrial) –40°C  TA  +85°C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. IPD Power-down Current(2) D006 PIC16LCR54A-Commercial — 1.0 6.0 A VDD = 2.5V, WDT disabled — 2.0 8.0* A VDD = 4.0V, WDT disabled — 3.0 15 A VDD = 6.0V, WDT disabled — 5.0 25 A VDD = 6.0V, WDT enabled D006A PIC16CR54A-Commercial — 1.0 6.0 A VDD = 2.5V, WDT disabled — 2.0 8.0* A VDD = 4.0V, WDT disabled — 3.0 15 A VDD = 6.0V, WDT disabled — 5.0 25 A VDD = 6.0V, WDT enabled D007 PIC16LCR54A-Industrial — 1.0 8.0 A VDD = 2.5V, WDT disabled — 2.0 10* A VDD = 4.0V, WDT disabled — 3.0 20* A VDD = 4.0V, WDT enabled — 3.0 18 A VDD = 6.0V, WDT disabled — 5.0 45 A VDD = 6.0V, WDT enabled D007A PIC16CR54A-Industrial — 1.0 8.0 A VDD = 2.5V, WDT disabled — 2.0 10* A VDD = 4.0V, WDT disabled — 3.0 20* A VDD = 4.0V, WDT enabled — 3.0 18 A VDD = 6.0V, WDT disabled — 5.0 45 A VDD = 6.0V, WDT enabled Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR= VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR= VDD/2REXT (mA) with REXT in k. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 81

PIC16C5X 13.2 DC Characteristics:PIC16CR54A-04E, 10E, 20E (Extended) PIC16CR54A-04E, 10E, 20E Standard Operating Conditions (unless otherwise specified) (Extended) Operating Temperature –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage RC, XT and LP modes 3.25 — 6.0 V HS mode 4.5 — 5.5 V D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D003 VPOR VDD Start Voltage to ensure — VSS — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure Power- 0.05* — — V/ms See Section5.1 for details on on Reset Power-on Reset D010 IDD Supply Current(2) RC(3) and XT modes — 1.8 3.3 mA FOSC = 4.0 MHz, VDD = 5.5V HS mode — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V HS mode — 9.0 20 mA FOSC = 16 MHz, VDD = 5.5V D020 IPD Power-down Current(2) — 5.0 22 A VDD = 3.25V, WDT enabled — 0.8 18 A VDD = 3.25V, WDT disabled * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. Preliminary DS30453E-page 82  1997-2013 Microchip Technology Inc.

PIC16C5X 13.3 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial) PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature 0°C  TA  +70°C for commercial –40°C  TA  +85°C for industrial Param Symbol Characteristic Min Typ† Max Units Conditions No. D030 VIL Input Low Voltage I/O ports VSS — 0.2 VDD V Pin at hi-impedance MCLR (Schmitt Trigger) VSS — 0.15 VDD V T0CKI (Schmitt Trigger) VSS — 0.15 VDD V OSC1 (Schmitt Trigger) VSS — 0.15 VDD V RC mode only(3) OSC1 VSS — 0.15 VDD V XT, HS and LP modes D040 VIH Input High Voltage I/O ports 2.0 — VDD V VDD = 3.0V to 5.5V(4) I/O ports 0.6 VDD — VDD V Full VDD range(4) MCLR (Schmitt Trigger) 0.85 VDD — VDD V T0CKI (Schmitt Trigger) 0.85 VDD — VDD V OSC1 (Schmitt Trigger) 0.85 VDD — VDD V RC mode only(3) OSC1 0.85 VDD — VDD V XT, HS and LP modes D050 VHYS Hysteresis of Schmitt 0.15 VDD* — — V Trigger inputs D060 IIL Input Leakage Current(1,2) For VDD  5.5V: I/O ports –1.0 — +1.0 A VSS  VPIN  VDD, pin at hi-impedance MCLR –5.0 — — A VPIN = VSS + 0.25V MCLR — 0.5 +5.0 A VPIN = VDD T0CKI –3.0 0.5 +3.0 A VSS  VPIN  VDD OSC1 –3.0 0.5 +3.0 A VSS  VPIN  VDD, XT, HS and LP modes D080 VOL Output Low Voltage I/O ports — — 0.5 V IOL = 10 mA, VDD = 6.0V OSC2/CLKOUT — — 0.5 V IOL = 1.9 mA, VDD = 6.0V, RC mode only D090 VOH Output High Voltage(2) I/O ports VDD – 0.5 — — V IOH = –4.0 mA, VDD = 6.0V OSC2/CLKOUT VDD – 0.5 — — V IOH = –0.8 mA, VDD = 6.0V, RC mode only * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 4: The user may use the better of the two specifications. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 83

PIC16C5X 13.4 DC Characteristics:PIC16CR54A-04E, 10E, 20E (Extended) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. D030 VIL Input Low Voltage I/O ports Vss — 0.15 VDD V Pin at hi-impedance MCLR (Schmitt Trigger) Vss — 0.15 VDD V T0CKI (Schmitt Trigger) Vss — 0.15 VDD V OSC1 (Schmitt Trigger) Vss — 0.15 VDD V RC mode only(3) OSC1 Vss — 0.3 VDD V XT, HS and LP modes D040 VIH Input High Voltage I/O ports 0.45 VDD — VDD V For all VDD(4) I/O ports 2.0 — VDD V 4.0V < VDD  5.5V(4) I/O ports 0.36 VDD — VDD V VDD > 5.5V MCLR (Schmitt Trigger) 0.85 VDD — VDD V T0CKI (Schmitt Trigger) 0.85 VDD — VDD V OSC1 (Schmitt Trigger) 0.85 VDD — VDD V RC mode only(3) OSC1 0.7 VDD — VDD V XT, HS and LP modes D050 VHYS Hysteresis of Schmitt 0.15 VDD* — — V Trigger inputs D060 IIL Input Leakage Current(1,2) For VDD  5.5V: I/O ports –1.0 0.5 +1.0 A VSS  VPIN  VDD, pin at hi-impedance MCLR –5.0 — — A VPIN = VSS + 0.25V MCLR — 0.5 +5.0 A VPIN = VDD T0CKI –3.0 0.5 +3.0 A VSS  VPIN  VDD OSC1 –3.0 0.5 +3.0 A VSS  VPIN  VDD, XT, HS and LP modes D080 VOL Output Low Voltage I/O ports — — 0.6 V IOL = 8.7 mA, VDD = 4.5V OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, RC mode only D090 VOH Output High Voltage(2) I/O ports VDD – 0.7 — — V IOH = –5.4 mA, VDD = 4.5V OSC2/CLKOUT VDD – 0.7 — — V IOH = –1.0 mA, VDD = 4.5V, RC mode only * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. 4: The user may use the better of the two specifications. Preliminary DS30453E-page 84  1997-2013 Microchip Technology Inc.

PIC16C5X 13.5 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 13-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16CR54A Pin CL = 50 pF for all pins and OSC2 for RC modes CL 0 -15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 85

PIC16C5X 13.6 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC16CR54A Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. FOSC External CLKIN Frequency(1) DC — 4.0 MHz XT OSC mode DC — 4.0 MHz HS OSC mode (04) DC — 10 MHz HS OSC mode (10) DC — 20 MHz HS OSC mode (20) DC — 200 kHz LP OSC mode Oscillator Frequency(1) DC — 4.0 MHz RC OSC mode 0.1 — 4.0 MHz XT OSC mode 4.0 — 4.0 MHz HS OSC mode (04) 4.0 — 10 MHz HS OSC mode (10) 4.0 — 20 MHz HS OSC mode (20) 5.0 — 200 kHz LP OSC mode * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary DS30453E-page 86  1997-2013 Microchip Technology Inc.

PIC16C5X TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 1 TOSC External CLKIN Period(1) 250 — — ns XT OSC mode 250 — — ns HS OSC mode (04) 100 — — ns HS OSC mode (10) 50 — — ns HS OSC mode (20) 5.0 — — s LP OSC mode Oscillator Period(1) 250 — — ns RC OSC mode 250 — 10,000 ns XT OSC mode 250 — 250 ns HS OSC mode (04) 100 — 250 ns HS OSC mode (10) 50 — 250 ns HS OSC mode (20) 5.0 — 200 s LP OSC mode 2 Tcy Instruction Cycle Time(2) — 4/FOSC — — 3 TosL, TosH Clock in (OSC1) Low or High 50* — — ns XT oscillator Time 20* — — ns HS oscillator 2.0* — — s LP oscillator 4 TosR, TosF Clock in (OSC1) Rise or Fall — — 25* ns XT oscillator Time — — 25* ns HS oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 87

PIC16C5X FIGURE 13-3: CLKOUT AND I/O TIMING - PIC16CR54A Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 19 18 16 14 I/O Pin (input) 17 15 I/O Pin Old Value New Value (output) 20, 21 Note: Please refer to Figure13.1 for load conditions. TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units No. 10 TosH2ckL OSC1 to CLKOUT(1) — 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(1) — 15 30** ns 12 TckR CLKOUT rise time(1) — 5.0 15** ns 13 TckF CLKOUT fall time(1) — 5.0 15** ns 14 TckL2ioV CLKOUT to Port out valid(1) — — 40** ns 15 TioV2ckH Port in valid before CLKOUT(1) 0.25 TCY+30* — — ns 16 TckH2ioI Port in hold after CLKOUT(1) 0* — — ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(2) — — 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1 TBD — — ns (I/O in setup time) 20 TioR Port output rise time(2) — 10 25** ns 21 TioF Port output fall time(2) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 2: Please refer to Figure13.1 for load conditions. Preliminary DS30453E-page 88  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: Please refer to Figure13.1 for load conditions. TABLE 13-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70°C for commercial AC Characteristics –40C  TA  +85C for industrial –40C  TA  +125C for extended Param No. Symbol Characteristic Min Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 1.0* — — s VDD = 5.0V 31 Twdt Watchdog Timer Time-out Period 7.0* 18* 40* ms VDD = 5.0V (Comm) (No Prescaler) 32 TDRT Device Reset Timer Period 7.0* 18* 30* ms VDD = 5.0V (Comm) 34 TioZ I/O Hi-impedance from MCLR Low — — 1.0* s * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 89

PIC16C5X FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC16CR54A T0CKI 40 41 42 Note: Please refer to Figure13.1 for load conditions. TABLE 13-4: TIMER0 CLOCK REQUIREMENTS - PIC16CR54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary DS30453E-page 90  1997-2013 Microchip Technology Inc.

PIC16C5X 14.0 DEVICE CHARACTERIZATION - PIC16C54A The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran- teed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean – 3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 14-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE FOSC Frequency normalized to +25C FOSC (25C) 1.10 REXT 10k 1.08 CEXT = 100 pF 1.06 1.04 1.02 1.00 0.98 VDD = 5.5V 0.96 0.94 VDD = 3.5V 0.92 0.90 0.88 0 10 20 25 30 40 50 60 70 T(C) TABLE 14-1: RC OSCILLATOR FREQUENCIES Average CEXT REXT FOSC @ 5 V, 25C 20 pF 3.3K 5 MHz  27% 5K 3.8 MHz  21% 10K 2.2 MHz  21% 100K 262 kHz  31% 100 pF 3.3K 1.6 MHz  13% 5K 1.2 MHz  13% 10K 684 kHz  18% 100K 71 kHz  25% 300 pF 3.3K 660 kHz  10% 5.0K 484 kHz  14% 10K 267 kHz  15% 100K 29 kHz  19% The frequencies are measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviations from the average value for VDD = 5V. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 91

PIC16C5X FIGURE 14-2: TYPICAL RC OSC FIGURE 14-3: TYPICAL RC OSC FREQUENCY vs. VDD, FREQUENCY vs. VDD, CEXT = 20 PF CEXT = 100 PF Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 5.5 1.8 R = 3.3K R = 3.3K 5.0 1.6 4.5 1.4 R = 5K 4.0 R = 5K 1.2 3.5 z) H1.0 z) M MH c ( sc ( 3.0 R = 10K Fos0.8 o F R = 10K 2.5 0.6 Measured on DIP Packages, T = 25C 2.0 0.4 Measured on DIP Packages, T = 25C 1.5 0.2 R = 100K 1.0 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 R = 100K VDD (Volts) 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary DS30453E-page 92  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 14-4: TYPICAL RC OSC FIGURE 14-5: TYPICAL IPD vs. VDD, FREQUENCY vs. VDD, WATCHDOG DISABLED CEXT = 300 PF Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Typical: statistical mean @ 25°C Minimum: mean – 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.5 800 2.0 700 R = 3.3K T = 25C 600 1.5 500 R = 5K A) Hz) (D 1.0 k P c ( 400 I s o F 0.5 300 R = 10K 200 0.0 Measured on DIP Packages, T = 25C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 100 VDD (Volts) R = 100K 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 93

PIC16C5X FIGURE 14-6: MAXIMUM IPD vs. VDD, FIGURE 14-8: MAXIMUM IPD vs. VDD, WATCHDOG DISABLED WATCHDOG ENABLED Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 100 60 50 +125°C +85°C 10 40 +70°C –55C 0°C +85C A) 30  –40°C pd ( A) +125C –40C I 1 –55°C (D 20 +70C P I 0C 10 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (Volts) VDD (Volts) IPD, with WDT enabled, has two components: The leakage current, which increases with higher temper- FIGURE 14-7: TYPICAL IPD vs. VDD, ature, and the operating current of the WDT logic, which WATCHDOG ENABLED increases with lower temperature. At –40C, the latter dominates explaining the apparently anomalous behav- Typical: statistical mean @ 25°C ior. Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 20 18 16 14 T = 25C 12 10 A)  (D 8 P I 6 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary DS30453E-page 94  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 14-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.00 1.80 Max (–40C to +85C) 1.60 Volts) 1.40 Typ (+25C) (TH 1.20 V 1.00 Min (–40C to +85C) 0.80 0.60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 14-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (RC MODE) vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 4.5 (Volts)L 3324....5050 VIVHI Hm VmaIxHin (t –y(–4p40 +02CC5 t otCo + +8855CC) ) VI , H 2.0 VI 1.5 VIL max (–40C to +85C) 1.0 VIH typ +25C 0.5 VIL min (–40C to +85C) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Note: These input pins have Schmitt Trigger input buffers. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 95

PIC16C5X FIGURE 14-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (XT, HS, AND LP MODES) vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 3.4 3.2 3.0 s) 222...468 Max (–T4y0p C(+ t2o5 +C8)5C) olt 2.2 V (VTH 21..08 Min (–40C to +85C) 1.6 1.4 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 14-12: TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10 1.0 A) m (D D I 0.1 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0.01 10K 100K 1M 10M 100M External Clock Frequency (Hz) Preliminary DS30453E-page 96  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 14-13: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, –40C TO +85C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10 1.0 A) m (D D I 7.0 6.5 0.1 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 0.01 10K 100K 1M 10M 100M External Clock Frequency (Hz) FIGURE 14-14: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –55C TO +125C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10 1.0 A) m 7.0 (D 6.5 ID 6.0 5.5 5.0 0.1 4.5 4.0 3.5 3.0 2.5 0.01 10K 100K 1M 10M 100M External Clock Frequency (Hz) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 97

PIC16C5X FIGURE 14-15: WDT TIMER TIME-OUT FIGURE 14-16: TRANSCONDUCTANCE PERIOD vs. VDD(1) (gm) OF HS OSCILLATOR vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Typical: statistical mean @ 25°C Minimum: mean – 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 50 9000 45 8000 Max –40C 40 7000 35 s) 6000 m d ( 30 o eri Max +85C 5000 DT p 25 A/V) Typ +25C W  Max +70C m ( 4000 g 20 Typ +25C 3000 15 Min +85C MIn 0C 2000 10 MIn –40C 100 5 2.0 3.0 4.0 5.0 6.0 7.0 0 VDD (Volts) 2.0 3.0 4.0 5.0 6.0 7.0 Note 1: Prescaler set to 1:1. VDD (Volts) Preliminary DS30453E-page 98  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 14-17: TRANSCONDUCTANCE FIGURE 14-18: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR (gm) OF XT OSCILLATOR vs. VDD vs. VDD Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 45 2500 40 Max –40C Max –40C 2000 35 30 1500 25 A/V) Typ +25C A/V) Typ +25C gm ( 20 gm ( 1000 15 Min +85C 500 10 Min +85C 5 0 2.0 3.0 4.0 5.0 6.0 7.0 0 2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts) VDD (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 99

PIC16C5X FIGURE 14-19: PORTA, B AND C IOH vs. FIGURE 14-20: PORTA, B AND C IOH vs. VOH, VDD = 3 V VOH, VDD = 5 V Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 0 0 Min +85C –5 –10 Min +85C –10 A) A) m m (H Typ +25C (H –20 O O I I Typ +25C –15 Max –40C –30 Max –40C –20 –40 –25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOH (Volts) VOH (Volts) Preliminary DS30453E-page 100  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 14-21: PORTA, B AND C IOL vs. FIGURE 14-22: PORTA, B AND C IOL vs. VOL, VDD = 3 V VOL, VDD = 5 V Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 45 90 40 Max –40C 80 Max –40C 35 70 30 60 Typ +25C 25 50 A) A) m m I (OL 20 Typ +25C I (OL 40 Min +85C 15 30 Min +85C 10 20 5 10 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts) VOL (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 101

PIC16C5X TABLE 14-2: INPUT CAPACITANCE FOR PIC16C54/56 Typical Capacitance (pF) Pin 18L PDIP 18L SOIC RA port 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of ±25% (three standard deviations) should be taken into account. TABLE 14-3: INPUT CAPACITANCE FOR PIC16C55/57 Typical Capacitance (pF) Pin 28L PDIP 28L SOIC (600 mil) RA port 5.2 4.8 RB port 5.6 4.7 RC port 5.0 4.1 MCLR 17.0 17.0 OSC1 6.6 3.5 OSC2/CLKOUT 4.6 3.5 T0CKI 4.5 3.5 All capacitance values are typical at 25C. A part-to-part variation of ±25% (three standard deviations) should be taken into account. Preliminary DS30453E-page 102  1997-2013 Microchip Technology Inc.

PIC16C5X 15.0 ELECTRICAL CHARACTERISTICS - PIC16C54A Absolute Maximum Ratings(†) Ambient temperature under bias......................................................................................................–55°C to +125°C Storage temperature....................................................................................................................... –65°C to +150°C Voltage on VDD with respect to VSS............................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS..........................................................................................................0 to +14V Voltage on all other pins with respect to VSS............................................................................–0.6V to (VDD + 0.6V) Total power dissipation(1)...............................................................................................................................800 mW Max. current out of VSS pin.............................................................................................................................150 mA Max. current into VDD pin................................................................................................................................100 mA Max. current into an input pin (T0CKI only)500 A Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Max. output current sunk by any I/O pin...........................................................................................................25 mA Max. output current sourced by any I/O pin......................................................................................................20 mA Max. output current sourced by a single I/O port (PORTA or B).......................................................................50 mA Max. output current sunk by a single I/O port (PORTA or B)............................................................................50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 103

PIC16C5X 15.1 DC Characteristics:PIC16C54A-04, 10, 20 (Commercial) PIC16C54A-04I, 10I, 20I (Industrial) PIC16LC54A-04 (Commercial) PIC16LC54A-04I (Industrial) PIC16LC54A-04 Standard Operating Conditions (unless otherwise specified) PIC16LC54A-04I Operating Temperature 0°C  TA  +70°C for commercial (Commercial, Industrial) –40°C  TA  +85°C for industrial PIC16C54A-04, 10, 20 Standard Operating Conditions (unless otherwise specified) PIC16C54A-04I, 10I, 20I Operating Temperature 0°C  TA  +70°C for commercial (Commercial, Industrial) –40°C  TA  +85°C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. VDD Supply Voltage D001 PIC16LC54A 3.0 — 6.25 V XT and RC modes 2.5 — 6.25 V LP mode D001A PIC16C54A 3.0 — 6.25 V RC, XT and LP modes 4.5 — 5.5 V HS mode D002 VDR RAM Data Retention — 1.5* — V Device in SLEEP mode Voltage(1) D003 VPOR VDD Start Voltage to — Vss — V See Section5.1 for details on ensure Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset IDD Supply Current(2) D005 PIC16LC5X — 0.5 2.5 mA FOSC = 4.0 MHz, VDD = 5.5V, RC(3) and XT modes — 11 27 A FOSC = 32 kHz, VDD = 2.5V, WDT disabled, LP mode, Commercial — 11 35 A FOSC = 32 kHz, VDD = 2.5V, WDT disabled, LP mode, Industrial D005A PIC16C5X — 1.8 2.4 mA FOSC = 4.0 MHz, VDD = 5.5V, RC(3) and XT modes — 2.4 8.0 mA FOSC = 10 MHz, VDD = 5.5V, HS mode — 4.5 16 mA FOSC = 20 MHz, VDD = 5.5V, HS mode — 14 29 A FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP mode, Commercial — 17 37 A FOSC = 32 kHz, VDD = 3.0V, WDT disabled, LP mode, Industrial Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR= VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR=VDD/2REXT (mA) with REXT in k. Preliminary DS30453E-page 104  1997-2013 Microchip Technology Inc.

PIC16C5X 15.1 DC Characteristics:PIC16C54A-04, 10, 20 (Commercial) PIC16C54A-04I, 10I, 20I (Industrial) PIC16LC54A-04 (Commercial) PIC16LC54A-04I (Industrial) PIC16LC54A-04 Standard Operating Conditions (unless otherwise specified) PIC16LC54A-04I Operating Temperature 0°C  TA  +70°C for commercial (Commercial, Industrial) –40°C  TA  +85°C for industrial PIC16C54A-04, 10, 20 Standard Operating Conditions (unless otherwise specified) PIC16C54A-04I, 10I, 20I Operating Temperature 0°C  TA  +70°C for commercial (Commercial, Industrial) –40°C  TA  +85°C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. IPD Power-down Current(2) D006 PIC16LC5X — 2.5 12 A VDD = 2.5V, WDT enabled, Commercial — 0.25 4.0 A VDD = 2.5V, WDT disabled, Commercial — 2.5 14 A VDD = 2.5V, WDT enabled, Industrial — 0.25 5.0 A VDD = 2.5V, WDT disabled, Industrial D006A PIC16C5X — 4.0 12 A VDD = 3.0V, WDT enabled, Commercial — 0.25 4.0 A VDD = 3.0V, WDT disabled, Commercial — 5.0 14 A VDD = 3.0V, WDT enabled, Industrial — 0.3 5.0 A VDD = 3.0V, WDT disabled, Industrial Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR= VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR=VDD/2REXT (mA) with REXT in k. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 105

PIC16C5X 15.2 DC Characteristics: PIC16C54A-04E, 10E, 20E (Extended) PIC16LC54A-04E (Extended) PIC16LC54A-04E Standard Operating Conditions (unless otherwise specified) (Extended) Operating Temperature –40°C  TA  +125C for extended PIC16C54A-04E, 10E, 20E Standard Operating Conditions (unless otherwise specified) (Extended) Operating Temperature –40°C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. VDD Supply Voltage D001 PIC16LC54A 3.0 — 6.25 V XT and RC modes 2.5 — 6.25 V LP mode D001A PIC16C54A 3.5 — 5.5 V RC and XT modes 4.5 — 5.5 V HS mode D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset IDD Supply Current(2) D010 PIC16LC54A — 0.5 25 mA FOSC = 4.0 MHz, VDD = 5.5V, RC(3) and XT modes — 11 27 A FOSC = 32 kHz, VDD = 2.5V, LP mode, Commercial — 11 35 A FOSC = 32 kHz, VDD = 2.5V, LP mode, Industrial — 11 37 A FOSC = 32 kHz, VDD = 2.5V, LP mode, Extended D010A PIC16C54A — 1.8 3.3 mA FOSC = 4.0 MHz, VDD = 5.5V, RC(3) and XT modes — 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V, HS mode — 9.0 20 mA FOSC = 20 MHz, VDD = 5.5V, HS mode Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR= VDD/2REXT (mA) with REXT in k. Preliminary DS30453E-page 106  1997-2013 Microchip Technology Inc.

PIC16C5X 15.2 DC Characteristics: PIC16C54A-04E, 10E, 20E (Extended) PIC16LC54A-04E (Extended) PIC16LC54A-04E Standard Operating Conditions (unless otherwise specified) (Extended) Operating Temperature –40°C  TA  +125C for extended PIC16C54A-04E, 10E, 20E Standard Operating Conditions (unless otherwise specified) (Extended) Operating Temperature –40°C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. IPD Power-down Current(2) D020 PIC16LC54A — 2.5 15 A VDD = 2.5V, WDT enabled, Extended — 0.25 7.0 A VDD = 2.5V, WDT disabled, Extended D020A PIC16C54A — 5.0 22 A VDD = 3.5V, WDT enabled — 0.8 18* A VDD = 3.5V, WDT disabled Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR= VDD/2REXT (mA) with REXT in k. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 107

PIC16C5X 15.3 DC Characteristics:PIC16LV54A-02 (Commercial) PIC16LV54A-02I (Industrial) PIC16LV54A-02 Standard Operating Conditions (unless otherwise specified) PIC16LV54A-02I Operating Temperature 0C  TA  +70C for commercial (Commercial, Industrial) –20C  TA  +85C for industrial Param Symbol Characteristic Min Typ† Max Units Conditions No. D001 Supply Voltage VDD RC and XT modes 2.0 — 3.8 V D002 VDR RAM Data Retention — 1.5* — V Device in SLEEP mode Voltage(1) D003 VPOR VDD Start Voltage to ensure — Vss — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset D010 IDD Supply Current(2) RC(3) and XT modes — 0.5 — mA FOSC = 2.0 MHz, VDD = 3.0V LP mode, Commercial — 11 27 A FOSC = 32 kHz, VDD = 2.5V WDT disabled LP mode, Industrial — 14 35 A FOSC = 32 kHz, VDD = 2.5V WDT disabled D020 IPD Power-down Current(2,4) Commercial — 2.5 12 A VDD = 2.5V, WDT enabled Commercial — 0.25 4.0 A VDD = 2.5V, WDT disabled Industrial — 3.5 14 A VDD = 2.5V, WDT enabled Industrial — 0.3 5.0 A VDD = 2.5V, WDT disabled * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR=VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR=VDD/2REXT (mA) with REXT in k. 4: The oscillator start-up time can be as much as 8 seconds for XT and LP oscillator selection on wake-up from SLEEP mode or during initial power-up. Preliminary DS30453E-page 108  1997-2013 Microchip Technology Inc.

PIC16C5X 15.4 DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial) PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial) PIC16C54A-04E, 10E, 20E, PIC16LC54A-04E (Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial DC CHARACTERISTICS –40C  TA  +85C for industrial –20C  TA  +85C for industrial-PIC16LV54A-02I –40°C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. D030 VIL Input Low Voltage I/O ports VSS — 0.2 VDD V Pin at hi-impedance MCLR (Schmitt Trigger) VSS — 0.15 VDD V T0CKI (Schmitt Trigger) VSS — 0.15 VDD V OSC1 (Schmitt Trigger) VSS — 0.15 VDD V RC mode only(3) OSC1 VSS — 0.3 VDD XT, HS and LP modes D040 VIH Input High Voltage I/O ports 0.2 VDD + 1 — VDD V For all VDD(4) I/O ports 2.0 — VDD V 4.0V < VDD 5.5V(4) MCLR (Schmitt Trigger) 0.85 VDD — VDD V T0CKI (Schmitt Trigger) 0.85 VDD — VDD V OSC1 (Schmitt Trigger) 0.85 VDD — VDD V RC mode only(3) OSC1 0.7 VDD — VDD V XT, HS and LP modes D050 VHYS Hysteresis of Schmitt 0.15 VDD* — — V Trigger inputs D060 IIL Input Leakage Current(1,2) For VDD  5.5V: I/O ports -1.0 0.5 +1.0 A VSS  VPIN  VDD, pin at hi-impedance MCLR -5.0 — +5.0 A VPIN = VSS +0.25V MCLR — 0.5 +3.0 A VPIN = VDD T0CKI -3.0 0.5 +3.0 A VSS  VPIN VDD OSC1 -3.0 0.5 — A VSS  VPIN  VDD, XT, HS and LP modes D080 VOL Output Low Voltage I/O ports — — 0.6 V IOL = 8.7 mA, VDD = 4.5V OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, RC mode only VOH Output High Voltage(2) I/O ports VDD - 0.7 — — V IOH = -5.4 mA, VDD = 4.5V OSC2/CLKOUT VDD - 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, RC mode only * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 109

PIC16C5X 15.5 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 15-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54A Pin CL = 50 pF for all pins and OSC2 for RC modes CL 0 -15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS Preliminary DS30453E-page 110  1997-2013 Microchip Technology Inc.

PIC16C5X 15.6 Timing Diagrams and Specifications FIGURE 15-2: EXTERNAL CLOCK TIMING - PIC16C54A Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –20C  TA  +85C for industrial - PIC16LV54A-02I –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. FOSC External CLKIN Fre- DC — 4.0 MHz XT OSC mode quency(1) DC — 2.0 MHz XT OSC mode (PIC16LV54A) DC — 4.0 MHz HS OSC mode (04) DC — 10 MHz HS OSC mode (10) DC — 20 MHz HS OSC mode (20) DC — 200 kHz LP OSC mode Oscillator Frequency(1) DC — 4.0 MHz RC OSC mode DC — 2.0 MHz RC OSC mode (PIC16LV54A) 0.1 — 4.0 MHz XT OSC mode 0.1 — 2.0 MHz XT OSC mode (PIC16LV54A) 4.0 — 4.0 MHz HS OSC mode (04) 4.0 — 10 MHz HS OSC mode (10) 4.0 — 20 MHz HS OSC mode (20) 5.0 — 200 kHz LP OSC mode * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 111

PIC16C5X TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –20C  TA  +85C for industrial - PIC16LV54A-02I –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 1 TOSC External CLKIN Period(1) 250 — — ns XT OSC mode 500 — — ns XT OSC mode (PIC16LV54A) 250 — — ns HS OSC mode (04) 100 — — ns HS OSC mode (10) 50 — — ns HS OSC mode (20) 5.0 — — s LP OSC mode Oscillator Period(1) 250 — — ns RC OSC mode 500 — — ns RC OSC mode (PIC16LV54A) 250 — 10,000 ns XT OSC mode 500 — — ns XT OSC mode (PIC16LV54A) 250 — 250 ns HS OSC mode (04) 100 — 250 ns HS OSC mode (10) 50 — 250 ns HS OSC mode (20) 5.0 — 200 s LP OSC mode 2 Tcy Instruction Cycle Time(2) — 4/FOSC — — 3 TosL, TosH Clock in (OSC1) Low or 85* — — ns XT oscillator High Time 20* — — ns HS oscillator 2.0* — — s LP oscillator 4 TosR, TosF Clock in (OSC1) Rise or — — 25* ns XT oscillator Fall Time — — 25* ns HS oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary DS30453E-page 112  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 15-3: CLKOUT AND I/O TIMING - PIC16C54A Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin Old Value New Value (output) 20, 21 Note: Please refer to Figure15-1 for load conditions. TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –20C  TA  +85C for industrial - PIC16LV54A-02I –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units No. 10 TosH2ckL OSC1 to CLKOUT(1) — 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(1) — 15 30** ns 12 TckR CLKOUT rise time(1) — 5.0 15** ns 13 TckF CLKOUT fall time(1) — 5.0 15** ns 14 TckL2ioV CLKOUT to Port out valid(1) — — 40** ns 15 TioV2ckH Port in valid before CLKOUT(1) 0.25 TCY+30* — — ns 16 TckH2ioI Port in hold after CLKOUT(1) 0* — — ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(2) — — 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1 TBD — — ns (I/O in setup time) 20 TioR Port output rise time(2) — 10 25** ns 21 TioF Port output fall time(2) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 2: Please refer to Figure15-1 for load conditions. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 113

PIC16C5X FIGURE 15-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C54A VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: Please refer to Figure15-1 for load conditions. TABLE 15-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –20C  TA  +85C for industrial - PIC16LV54A-02I –40C  TA  +125C for extended Param No. Symbol Characteristic Min Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 100* — — ns VDD = 5.0V 1 — — s VDD = 5.0V (PIC16LV54A only) 31 Twdt Watchdog Timer Time-out 9.0* 18* 30* ms VDD = 5.0V (Comm) Period (No Prescaler) 32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Comm) 34 TioZ I/O Hi-impedance from MCLR — — 100* ns Low — — 1s — (PIC16LV54A only) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary DS30453E-page 114  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 15-5: TIMER0 CLOCK TIMINGS - PIC16C54A T0CKI 40 41 42 Note: Please refer to Figure15-1 for load conditions. TABLE 15-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54A Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –20C  TA  +85C for industrial - PIC16LV54A-02I –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 115

PIC16C5X NOTES: Preliminary DS30453E-page 116  1997-2013 Microchip Technology Inc.

PIC16C5X 16.0 DEVICE CHARACTERIZATION - PIC16C54A The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran- teed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean – 3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 16-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE Fosc Frequency normalized to +25C Fosc (25C) 1.10 REXT  10 kW 1.08 CEXT = 100 pF 1.06 1.04 1.02 1.00 0.98 VDD = 5.5V 0.96 0.94 VDD = 3.5V 0.92 0.90 0.88 0 10 20 25 30 40 50 60 70 T(C) TABLE 16-1: RC OSCILLATOR FREQUENCIES Average CEXT REXT Fosc @ 5 V, 25C 20 pF 3.3K 5 MHz  27% 5K 3.8 MHz  21% 10K 2.2 MHz  21% 100K 262 kHz  31% 100 pF 3.3K 1.6 MHz  13% 5K 1.2 MHz  13% 10K 684 kHz  18% 100K 71 kHz  25% 300 pF 3.3K 660 kHz  10% 5.0K 484 kHz  14% 10K 267 kHz  15% 100K 29 kHz  19% The frequencies are measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 117

PIC16C5X FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 6 R=3.3K 5 R=5K 4 z) H M 3 (C S R=10K O F 2 1 R=100K 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 16-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 6 R=3.3K 5 R=5K 4 z) H M 3 (C OS R=10K F 2 1 R=100K 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary DS30453E-page 118  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 700 R=3.3K 600 500 R=5K 400 z) H k (C S 300 O F R=10K 200 100 R=100K 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 119

PIC16C5X FIGURE 16-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.5 2.0 1.5 A)  (D 1.0 P I 0.5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 16-6: TYPICAL IPD VS. VDD, WATCHDOG ENABLED (25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 25.00 20.00 15.00 10.00 5.00 0.00 2.5 3 3.5 4 4.5 5 5.5 6 VDD (Volts) Preliminary DS30453E-page 120  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 16-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS - VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.0 1.8 Max (–40C to +85C) 1.6 Volts) 1.4 Typ (+25C) (TH 1.2 V 1.0 Min (–40C to +85C) 0.8 0.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 16-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES) vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 3.4 3.2 3.0 s) 222...468 Max (–T4y0p C(+ t2o5 +C8)5C) olt 2.2 V (VTH 21..08 Min (–40C to +85C) 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 121

PIC16C5X FIGURE 16-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 4.5 (Volts)L 3324....5050 VIVHI Hm VmaIxHin (t –y(–4p40 +02CC5 t otCo + +8855CC) ) VI , H 2.0 VI 1.5 VIL max (–40C to +85C) 1.0 Vil typ +25C 0.5 VIL min (–40C to +85C) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Note: These input pins have Schmitt Trigger input buffers. Preliminary DS30453E-page 122  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 16-10: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D D I 6.0V 5.5V 100 54..05VV 4.0V 3.5V 3.0V 2.5V 10 0.1 1 10 Freq (MHz) FIGURE 16-11: MAXIMUM IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, –40C to +85C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D 6.0V D 5.5V I 5.0V 4.5V 100 4.0V 3.5V 3.0V 2.5V 10 0.1 1 10 Freq (MHz) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 123

PIC16C5X FIGURE 16-12: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D D I 6.0V 100 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 10 0.01 0.1 1 10 Freq (MHz) FIGURE 16-13: MAXIMUM IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, –40C to +85C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D D I 6.0V 5.5V 5.0V 100 4.5V 4.0V 3.5V 3.0V 2.5V 10 0.01 0.1 1 10 Freq (MHz) Preliminary DS30453E-page 124  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 16-14: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D D I 6.0V 100 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 10 0.01 0.1 1 Freq (MHz) FIGURE 16-15: MAXIMUM IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, –40C to +85C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D D I 6.0V 5.5V 100 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 10 0.01 0.1 1 Freq (MHz) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 125

PIC16C5X FIGURE 16-16: WDT TIMER TIME-OUT FIGURE 16-17: TRANSCONDUCTANCE PERIOD vs. VDD(1) (gm) OF HS OSCILLATOR vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Typical: statistical mean @ 25°C Minimum: mean – 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 50 9000 45 8000 Max –40C 40 7000 35 s) 6000 m d ( 30 DT perio 25 Max +85C A/W) 5000 Typ +25C W m ( 4000 Max +70C g 20 Typ +25C 3000 15 Min +85C MIn 0C 2000 10 MIn –40C 100 5 2.0 3.0 4.0 5.0 6.0 7.0 0 VDD (Volts) 2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts) Note 1: Prescaler set to 1:1. Preliminary DS30453E-page 126  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 16-18: TRANSCONDUCTANCE FIGURE 16-19: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR (gm) OF XT OSCILLATOR vs. VDD vs. VDD Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 45 2500 40 Max –40C Max –40C 2000 35 30 1500 25 V) V) Typ +25C A/ Typ +25C A/   m ( 20 m ( 1000 g g 15 Min +85C 500 10 Min +85C 5 0 2.0 3.0 4.0 5.0 6.0 7.0 0 2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts) VDD (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 127

PIC16C5X FIGURE 16-20: PORTA, B AND C IOH vs. FIGURE 16-21:PORTA, B AND C IOH vs. VOH, VOH, VDD = 3V VDD = 5V Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 0 0 Min +85C –5 Min +85C –10 –10 A) A) m m (H Typ +25C (H –20 O O I I Typ +25C –15 Max –40C –30 Max –40C –20 –40 –25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOH (Volts) VOH (Volts) Preliminary DS30453E-page 128  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 16-22: PORTA, B AND C IOL vs. FIGURE 16-23: PORTA, B AND C IOL vs. VOL, VDD = 3V VOL, VDD = 5V Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 45 90 40 Max –40C 80 Max –40C 35 70 30 60 Typ +25C mA) 25 mA) 50 I (OL 20 Typ +25C I (OL 40 Min +85C 15 30 Min +85C 10 20 5 10 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts) VOL (Volts) TABLE 16-2: INPUT CAPACITANCE FOR PIC16C54A/C58A Typical Capacitance (pF) Pin 18L PDIP 18L SOIC RA port 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of 25% (three standard deviations) should be taken into account. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 129

PIC16C5X NOTES: Preliminary DS30453E-page 130  1997-2013 Microchip Technology Inc.

PIC16C5X 17.0 ELECTRICAL CHARACTERISTICS - PIC16LC54A Absolute Maximum Ratings(†) Ambient temperature under bias............................................................................................................–55°C to +125°C Storage temperature............................................................................................................................. –65°C to +150°C Voltage on VDD with respect to VSS..................................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on all other pins with respect to VSS.................................................................................–0.6V to (VDD + 0.6V) Total power dissipation(1).....................................................................................................................................800 mW Max. current out of VSS pin...................................................................................................................................150 mA Max. current into VDD pin......................................................................................................................................100 mA Max. current into an input pin (T0CKI only)500 A Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Max. output current sunk by any I/O pin.................................................................................................................25 mA Max. output current sourced by any I/O pin............................................................................................................20 mA Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA Max. output current sunk by a single I/O (Port A, B or C).......................................................................................50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 131

PIC16C5X FIGURE 17-1: PIC16C54C/55A/56A/57C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH, 0C  T  +70C (COMMERCIAL TEMPS) A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 17-2: PIC16C54C/55A/56A/57C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH, -40C  T  0C, +70C  T  +125C (OUTSIDE OF COMMERCIAL TEMPS) A A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. Preliminary DS30453E-page 132  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 17-3: PIC16LC54C/55A/56A/57C/58B VOLTAGE-FREQUENCY GRAPH, 0C  T  +85C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 17-4: PIC16LC54C/55A/56A/57C/58B VOLTAGE-FREQUENCY GRAPH, -40C  T  0C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.7 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 133

PIC16C5X 17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial) PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial) PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial) PIC16LC5X Standard Operating Conditions (unless otherwise specified) PIC16LCR5X Operating Temperature 0C  TA  +70C for commercial (Commercial, Industrial) –40C  TA  +85C for industrial PIC16C5X Standard Operating Conditions (unless otherwise specified) PIC16CR5X Operating Temperature 0C  TA  +70C for commercial (Commercial, Industrial) –40C  TA  +85C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. VDD Supply Voltage D001 PIC16LC5X 2.5 — 5.5 V –40C TA + 85C, 16LCR5X 2.7 — 5.5 V –40C TA  0C, 16LC5X 2.5 — 5.5 V 0C TA + 85C 16LC5X PIC16C5X RC, XT, LP and HS mode D001A 3.0 — 5.5 V from 0 - 10 MHz 4.5 — 5.5 V from 10 - 20 MHz D002 VDR RAM Data Retention Volt- — 1.5* — V Device in SLEEP mode age(1) D003 VPOR VDD Start Voltage to ensure — VSS — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con- sumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. Preliminary DS30453E-page 134  1997-2013 Microchip Technology Inc.

PIC16C5X 17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial) PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial) PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial) PIC16LC5X Standard Operating Conditions (unless otherwise specified) PIC16LCR5X Operating Temperature 0C  TA  +70C for commercial (Commercial, Industrial) –40C  TA  +85C for industrial PIC16C5X Standard Operating Conditions (unless otherwise specified) PIC16CR5X Operating Temperature 0C  TA  +70C for commercial (Commercial, Industrial) –40C  TA  +85C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. IDD Supply Current(2,3) D010 PIC16LC5X — 0.5 2.4 mA FOSC = 4.0 MHz, VDD = 5.5V, XT and — 11 27 A RC modes FOSC = 32 kHz, VDD = 2.5V, LP mode, — 14 35 A Commercial FOSC = 32 kHz, VDD = 2.5V, LP mode, Industrial D010A PIC16C5X — 1.8 2.4 mA FOSC = 4 MHz, VDD = 5.5V, XT and RC — 2.6 3.6* mA modes — 4.5 16 mA FOSC = 10 MHz, VDD = 3.0V, HS mode — 14 32 A FOSC = 20 MHz, VDD = 5.5V, HS mode FOSC = 32 kHz, VDD = 3.0V, LP mode, — 17 40 A Commercial FOSC = 32 kHz, VDD = 3.0V, LP mode, Industrial Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con- sumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 135

PIC16C5X 17.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial) PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial) PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial) PIC16LC5X Standard Operating Conditions (unless otherwise specified) PIC16LCR5X Operating Temperature 0C  TA  +70C for commercial (Commercial, Industrial) –40C  TA  +85C for industrial PIC16C5X Standard Operating Conditions (unless otherwise specified) PIC16CR5X Operating Temperature 0C  TA  +70C for commercial (Commercial, Industrial) –40C  TA  +85C for industrial Param Symbol Characteristic/Device Min Typ† Max Units Conditions No. IPD Power-down Current(2) D020 PIC16LC5X — 0.25 2 A VDD = 2.5V, WDT disabled, Commercial — 0.25 3 A VDD = 2.5V, WDT disabled, Industrial — 1 5 A VDD = 2.5V, WDT enabled, Commercial — 1.25 8 A VDD = 2.5V, WDT enabled, Industrial D020A PIC16C5X — 0.25 4.0 A VDD = 3.0V, WDT disabled, Commercial — 0.25 5.0 A VDD = 3.0V, WDT disabled, Industrial — 1.8 7.0* A VDD = 5.5V, WDT disabled, Commercial — 2.0 8.0* A VDD = 5.5V, WDT disabled, Industrial — 4 12* A VDD = 3.0V, WDT enabled, Commercial — 4 14* A VDD = 3.0V, WDT enabled, Industrial — 9.8 27* A VDD = 5.5V, WDT enabled, Commercial — 12 30* A VDD = 5.5V, WDT enabled, Industrial Legend: Rows with standard voltage device data only are shaded for improved readability. * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con- sumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. Preliminary DS30453E-page 136  1997-2013 Microchip Technology Inc.

PIC16C5X 17.2 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E (Extended) PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E (Extended) PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E Standard Operating Conditions (unless otherwise specified) PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E Operating Temperature –40C  TA  +125C for extended (Extended) Param Symbol Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage RC, XT, LP, and HS mode 3.0 — 5.5 V from 0 - 10MHz 4.5 — 5.5 V from 10 - 20MHz D002 VDR RAM Data Retention Voltage(1) — 1.5* — V Device in SLEEP mode D003 VPOR VDD start voltage to ensure — Vss — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD rise rate to ensure 0.05* — — V/ms See Section5.1 for details on Power-on Reset Power-on Reset D010 IDD Supply Current(2) XT and RC(3) modes — 1.8 3.3 mA FOSC = 4.0MHz, VDD = 5.5V HS mode — 9.0 20 mA FOSC = 20MHz, VDD = 5.5V D020 IPD Power-down Current(2) — 0.3 17 A VDD = 3.0V, WDT disabled — 10 50* A VDD = 4.5V, WDT disabled — 12 60* A VDD = 5.5V, WDT disabled — 4.8 31* A VDD = 3.0V, WDT enabled — 18 68* A VDD = 4.5V, WDT enabled — 26 90* A VDD = 5.5V, WDT enabled * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only, and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/ disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. 3: Does not include current through REXT. The current through the resistor can be estimated by the formula: IR = VDD/2REXT (mA) with REXT in k. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 137

PIC16C5X 17.3 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial, Extended) PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial) PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial, Extended) PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70C for commercial DC CHARACTERISTICS –40C  TA  +85C for industrial –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. D030 VIL Input Low Voltage I/O Ports VSS — 0.8 V V 4.5V <VDD  5.5V I/O Ports VSS — 0.15 VDD V Otherwise MCLR (Schmitt Trigger) VSS — 0.15 VDD V T0CKI (Schmitt Trigger) VSS — 0.15 VDD V OSC1 (Schmitt Trigger) VSS — 0.15 VDD V RC mode only(3) OSC1 VSS — 0.3 VDD V XT, HS and LP modes D040 VIH Input High Voltage I/O ports 2.0 — VDD V 4.5V < VDD 5.5V I/O ports 0.25 VDD+0.8 — VDD V Otherwise MCLR (Schmitt Trigger) 0.85 VDD — VDD V T0CKI (Schmitt Trigger) 0.85 VDD — VDD V OSC1 (Schmitt Trigger) 0.85 VDD — VDD V RC mode only(3) OSC1 0.7 VDD — VDD V XT, HS and LP modes D050 VHYS Hysteresis of Schmitt 0.15 VDD* — — V Trigger inputs D060 IIL Input Leakage Current(1,2) For VDD 5.5V: I/O ports -1.0 0.5 +1.0 A VSS  VPIN  VDD, pin at hi-impedance MCLR -5.0 — +5.0 A VPIN = VSS +0.25V MCLR 0.5 +3.0 A VPIN = VDD T0CKI -3.0 0.5 +3.0 A VSS  VPIN VDD OSC1 -3.0 0.5 — A VSS  VPIN  VDD, XT, HS and LP modes D080 VOL Output Low Voltage I/O ports — — 0.6 V IOL = 8.7 mA, VDD = 4.5V OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, RC mode only D090 VOH Output High Voltage(2) I/O ports VDD - 0.7 — — V IOH = -5.4 mA, VDD = 4.5V OSC2/CLKOUT VDD - 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, RC mode only * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guid- ance only and is not tested. Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltage. 2: Negative current is defined as coming out of the pin. 3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be driven with external clock in RC mode. Preliminary DS30453E-page 138  1997-2013 Microchip Technology Inc.

PIC16C5X 17.4 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 17-5: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B-04, 20 Pin CL = 50 pF for all pins and OSC2 for RC mode CL 0 -15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 139

PIC16C5X 17.5 Timing Diagrams and Specifications FIGURE 17-6: EXTERNAL CLOCK TIMING - PIC16C5X, PIC16CR5X Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. FOSC External CLKIN Frequency(1) DC — 4.0 MHz XT OSC mode DC — 4.0 MHz HS OSC mode (04) DC — 20 MHz HS OSC mode (20) DC — 200 kHz LP OSC mode Oscillator Frequency(1) DC — 4.0 MHz RC OSC mode 0.45 — 4.0 MHz XT OSC mode 4.0 — 4.0 MHz HS OSC mode (04) 4.0 — 20 MHz HS OSC mode (20) 5.0 — 200 kHz LP OSC mode 1 TOSC External CLKIN Period(1) 250 — — ns XT OSC mode 250 — — ns HS OSC mode (04) 50 — — ns HS OSC mode (20) 5.0 — — s LP OSC mode Oscillator Period(1) 250 — — ns RC OSC mode 250 — 2,200 ns XT OSC mode 250 — 250 ns HS OSC mode (04) 50 — 250 ns HS OSC mode (20) 5.0 — 200 s LP OSC mode * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary DS30453E-page 140  1997-2013 Microchip Technology Inc.

PIC16C5X TABLE 17-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 2 Tcy Instruction Cycle Time(2) — 4/FOSC — — 3 TosL, TosH Clock in (OSC1) Low or High 50* — — ns XT oscillator Time 20* — — ns HS oscillator 2.0* — — s LP oscillator 4 TosR, TosF Clock in (OSC1) Rise or Fall — — 25* ns XT oscillator Time — — 25* ns HS oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 141

PIC16C5X FIGURE 17-7: CLKOUT AND I/O TIMING - PIC16C5X, PIC16CR5X Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin Old Value New Value (output) 20, 21 Note: Refer to Figure17-5 for load conditions. TABLE 17-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70C for commercial AC Characteristics –40C  TA  +85C for industrial –40C  TA  +125C for extended Param Symbol Characteristic Min Typ† Max Units No. 10 TosH2ckL OSC1 to CLKOUT(1) — 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(1) — 15 30** ns 12 TckR CLKOUT rise time(1) — 5.0 15** ns 13 TckF CLKOUT fall time(1) — 5.0 15** ns 14 TckL2ioV CLKOUT to Port out valid(1) — — 40** ns 15 TioV2ckH Port in valid before CLKOUT(1) 0.25 TCY+30* — — ns 16 TckH2ioI Port in hold after CLKOUT(1) 0* — — ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(2) — — 100* ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1 TBD — — ns (I/O in setup time) 20 TioR Port output rise time(2) — 10 25** ns 21 TioF Port output fall time(2) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 2: Refer to Figure17-5 for load conditions. Preliminary DS30453E-page 142  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 17-8: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C5X, PIC16CR5X VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: Please refer to Figure17-5 for load conditions. TABLE 17-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X, PIC16CR5X Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param No. Symbol Characteristic Min Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 1000* — — ns VDD = 5.0V 31 Twdt Watchdog Timer Time-out Period 9.0* 18* 30* ms VDD = 5.0V (Comm) (No Prescaler) 32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Comm) 34 TioZ I/O Hi-impedance from MCLR Low 100* 300* 1000* ns * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 143

PIC16C5X FIGURE 17-9: TIMER0 CLOCK TIMINGS - PIC16C5X, PIC16CR5X T0CKI 40 41 42 Note: Please refer to Figure17-5 for load conditions. TABLE 17-4: TIMER0 CLOCK REQUIREMENTS - PIC16C5X, PIC16CR5X Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70°C for commercial AC Characteristics –40°C  TA  +85°C for industrial –40°C  TA  +125°C for extended Param Symbol Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guid- ance only and are not tested. Preliminary DS30453E-page 144  1997-2013 Microchip Technology Inc.

PIC16C5X 18.0 DEVICE CHARACTERIZATION - PIC16LC54A The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran- teed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean – 3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 18-1: TYPICAL RC OSCILLATOR FREQUENCY VS. TEMPERATURE FOSC Frequency normalized to +25C FOSC (25C) 1.10 REXT  10 kW 1.08 CEXT = 100 pF 1.06 1.04 1.02 1.00 0.98 VDD = 5.5V 0.96 0.94 VDD = 3.5V 0.92 0.90 0.88 0 10 20 25 30 40 50 60 70 T(C) TABLE 18-1: RC OSCILLATOR FREQUENCIES Average CEXT REXT Fosc @ 5V, 25C 20 pF 3.3K 5 MHz ± 27% 5K 3.8 MHz ± 21% 10K 2.2 MHz ± 21% 100K 262 kHz ± 31% 100 pF 3.3K 1.63 MHz ± 13% 5K 1.2 MHz ± 13% 10K 684 kHz ± 18% 100K 71 kHz ± 25% 300 pF 3.3K 660 kHz ± 10% 5.0K 484 kHz ± 14% 10K 267 kHz ± 15% 100K 29 kHz ± 19% The frequencies are measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation indicated is ±3 standard deviation from average value for VDD = 5V. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 145

PIC16C5X FIGURE 18-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 6 R=3.3K 5 R=5K 4 3 R=10K 2 1 R=100K 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 18-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.8 R=3.3K 1.6 1.4 R=5K z) H M (C 1.0 S O F R=10K 0.6 0.2 R=100K 0 6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary DS30453E-page 146  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 18-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 700 R=3.3K 600 500 R=5K z) H k (C 400 S O F 300 R=10K 200 100 R=100K 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 18-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 25 20 15 A) u (D P I10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 147

PIC16C5X FIGURE 18-6: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 25 20 15 A) u (D P I10 5.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 18-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 35 30 25 20 A) u (D P 15 I 10 5.0 (-40C) (+85C) 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary DS30453E-page 148  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 18-8: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.0 1.8 1.6 Volts) 1.4 Typ (+25C) (TH 1.2 V 1.0 0.8 0.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 18-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 4.5 (Volts)L 3324....5050 VIVHI Hm VmaIxHin (t –y(–4p40 +02CC5 t otCo + +8855CC) ) VI , H 2.0 VI 1.5 VIL max (–40C to +85C) 1.0 VIL typ +25C 0.5 VIL min (–40C to +85C) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Note: These input pins have Schmitt Trigger input buffers. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 149

PIC16C5X FIGURE 18-10: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT (IN XT, HS AND LP MODES) vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 3.4 3.2 3.0 2.8 2.6 s) 2.4 Typ (+25C) olt 2.2 V (H 2.0 T V 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 18-11: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25C) TYPICAL IDD vs FREQ(RC MODE @ 20pF/25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D D I 5.5V 100 4.5V 3.5V 2.5V 10 0.1 1 10 FREQ(MHz) Preliminary DS30453E-page 150  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 18-12: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25C) TYPICAL IDD vs FREQ(RC MODE @ 100 pF/25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D D I100 5.5V 4.5V 3.5V 2.5V 10 0.1 1 10 FREQ(MHz) FIGURE 18-13: TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25C) TYPICAL IDD vs FREQ (RC MODE @ 300 pF/25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 10000 1000 A)  (D ID 100 5.5V 4.5V 3.5V 2.5V 10 0.01 0.1 1 FREQ(MHz) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 151

PIC16C5X FIGURE 18-14: WDT TIMER TIME-OUT FIGURE 18-15: PORTA, B AND C IOH vs. PERIOD vs. VDD(1) VOH, VDD = 3 V Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 50 0 45 –5 40 Min +85C 35 –10 ms) A) period ( 30 I (mOH Typ +25C T Typ +125C D 25 –15 W Typ +85C Max –40C 20 Typ +25C –20 15 Typ –40C 10 –25 0 0.5 1.0 1.5 2.0 2.5 3.0 5.0 VOH (Volts) 2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts) Note 1: Prescaler set to 1:1. Preliminary DS30453E-page 152  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 18-16: PORTA, B AND C IOH vs. FIGURE 18-17: PORTA, B AND C IOL vs. VOH, VDD = 5 V VOL, VDD = 3 V Typical: statistical mean @ 25°C Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 0 45 40 Max –40C –10 35 30 Typ +125C A) m 25 (OH –20 Typ +85C mA) I (L Typ +25C Typ +25C IO 20 Typ –40C 15 –30 Min +85C 10 –40 5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOH (Volts) 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 153

PIC16C5X FIGURE 18-18: PORTA, B AND C IOL vs. VOL, VDD = 5 V Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 90 80 Max –40C 70 60 Typ +25C 50 A) m (L IO 40 Min +85C 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts) TABLE 18-2: INPUT CAPACITANCE Typical Capacitance (pF) Pin 18L PDIP 18L SOIC RA port 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of ±25% (three standard deviations) should be taken into account. Preliminary DS30453E-page 154  1997-2013 Microchip Technology Inc.

PIC16C5X 19.0 ELECTRICAL CHARACTERISTICS - PIC16LC54C 40MHz Absolute Maximum Ratings(†) Ambient temperature under bias............................................................................................................–55°C to +125°C Storage temperature............................................................................................................................. –65°C to +150°C Voltage on VDD with respect to VSS..................................................................................................................0 to +7.5V Voltage on MCLR with respect to VSS................................................................................................................0 to +14V Voltage on all other pins with respect to VSS.................................................................................–0.6V to (VDD + 0.6V) Total power dissipation(1).....................................................................................................................................800 mW Max. current out of VSS pin...................................................................................................................................150 mA Max. current into VDD pin......................................................................................................................................100 mA Max. current into an input pin (T0CKI only)500 A Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (VO < 0 or VO > VDD)20 mA Max. output current sunk by any I/O pin.................................................................................................................25 mA Max. output current sourced by any I/O pin............................................................................................................20 mA Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA Max. output current sunk by a single I/O (Port A, B or C).......................................................................................50 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOL x IOL) † NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 155

PIC16C5X FIGURE 19-1: PIC16C54C/C55A/C56A/C57C/C58B-40 VOLTAGE-FREQUENCY GRAPH, 0C  T  +70C A 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 0 4 10 20 25 40 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 3: Operation between 20 to 40 MHz requires the following: • VDD between 4.5V. and 5.5V • OSC1 externally driven • OSC2 not connected • HS mode • Commercial temperatures Devices qualified for 40 MHz operation have -40 designation (ex: PIC16C54C-40/P). 4: For operation between DC and 20MHz, see Section17.1. Preliminary DS30453E-page 156  1997-2013 Microchip Technology Inc.

PIC16C5X 19.1 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial)(1) PIC16C54C/C55A/C56A/C57C/C58B-40 Standard Operating Conditions (unless otherwise specified) (Commercial) Operating Temperature 0C  TA  +70C for commercial Param Symbol Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 4.5 — 5.5 V HS mode from 20 - 40 MHz D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in SLEEP mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section5.1 for details on Power-on Reset Power-on Reset D004 SVDD VDD Rise Rate to ensure Power- 0.05* — — V/ms See Section5.1 for details on on Reset Power-on Reset D010 IDD Supply Current(3) — 5.2 12.3 mA FOSC = 40 MHz, VDD = 4.5V, HS mode — 6.8 16 mA FOSC = 40 MHz, VDD = 5.5V, HS mode D020 IPD Power-down Current(3) — 1.8 7.0 A VDD = 5.5V, WDT disabled, Commercial — 9.8 27* A VDD = 5.5V, WDT enabled, Commercial * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. Note 1: Device operation between 20 MHz to 40 MHz requires the following: VDD between 4.5V to 5.5V, OSC1 pin externally driven, OSC2 pin not connected, HS oscillator mode and commercial temperatures. For operation between DC and 20MHz, See Section19.1. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus load- ing, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/dis- abled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. The power-down current in SLEEP mode does not depend on the oscillator type. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 157

PIC16C5X 19.2 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial)(1) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C  TA  +70C for commercial Param Symbol Characteristic Min Typ† Max Units Conditions No. D030 VIL Input Low Voltage I/O Ports VSS — 0.8 V 4.5V <VDD  5.5V MCLR (Schmitt Trigger) VSS — 0.15 VDD V T0CKI (Schmitt Trigger) VSS — 0.15 VDD V OSC1 VSS — 0.2 VDD V HS, 20 MHz  FOSC 40 MHz D040 VIH Input High Voltage I/O ports 2.0 — VDD V 4.5V < VDD 5.5V MCLR (Schmitt Trigger) 0.85 VDD — VDD V T0CKI (Schmitt Trigger) 0.85 VDD — VDD V OSC1 0.8 VDD — VDD V HS, 20 MHz FOSC 40 MHz D050 VHYS Hysteresis of Schmitt 0.15 VDD* — — V Trigger inputs D060 IIL Input Leakage Current(2,3) For VDD 5.5V: I/O ports -1.0 0.5 +1.0 A VSS  VPIN  VDD, pin at hi-impedance MCLR -5.0 — +5.0 A VPIN = VSS +0.25V MCLR — 0.5 +3.0 A VPIN = VDD T0CKI -3.0 0.5 +3.0 A VSS  VPIN VDD OSC1 -3.0 0.5 — A VSS  VPIN  VDD, HS D080 VOL Output Low Voltage I/O ports — — 0.6 V IOL = 8.7 mA, VDD = 4.5V D090 VOH Output High Voltage(3) I/O ports VDD - 0.7 — — V IOH = -5.4 mA, VDD = 4.5V * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. Note 1: Device operation between 20 MHz to 40 MHz requires the following: VDD between 4.5V to 5.5V, OSC1 pin externally driven, OSC2 pin not connected and HS oscillator mode and commercial temperatures. For opera- tion between DC and 20MHz, See Section17.3. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- age. 3: Negative current is defined as coming out of the pin. Preliminary DS30453E-page 158  1997-2013 Microchip Technology Inc.

PIC16C5X 19.3 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 19-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54C/C55A/C56A/C57C/C58B-40 CL = 50 pF for all pins except OSC2 Pin 0 pF for OSC2 in HS mode for CL operation between 20 MHz to 40 MHz VSS Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 159

PIC16C5X 19.4 Timing Diagrams and Specifications FIGURE 19-3: EXTERNAL CLOCK TIMING - PIC16C5X-40 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 19-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X-40 Standard Operating Conditions (unless otherwise specified) AC Characteristics Operating Temperature 0C  TA  +70C for commercial Param Symbol Characteristic Min Typ† Max Units Conditions No. FOSC External CLKIN Frequency(1) 20 — 40 MHz HS OSC mode 1 TOSC External CLKIN Period(1) 25 — — ns HS OSC mode 2 Tcy Instruction Cycle Time(2) — 4/FOSC — — 3 TosL, TosH Clock in (OSC1) Low or High 6.0* — — ns HS oscillator Time 4 TosR, TosF Clock in (OSC1) Rise or Fall — — 6.5* ns HS oscillator Time * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. Preliminary DS30453E-page 160  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 19-4: CLKOUT AND I/O TIMING - PIC16C5X-40 Q4 Q1 Q2 Q3 OSC1 10 11 CLKOUT 13 12 14 19 18 16 I/O Pin (input) 17 15 I/O Pin Old Value New Value (output) 20, 21 . Note: Refer to Figure19-2 for load conditions. TABLE 19-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X-40 Standard Operating Conditions (unless otherwise specified) AC Characteristics Operating Temperature 0°C  TA  +70C for commercial Param Symbol Characteristic Min Typ† Max Units No. 10 TosH2ckL OSC1 to CLKOUT(1,2) — 15 30** ns 11 TosH2ckH OSC1 to CLKOUT(1,2) — 15 30** ns 12 TckR CLKOUT rise time(1,2) — 5.0 15** ns 13 TckF CLKOUT fall time(1,2) — 5.0 15** ns 14 TckL2ioV CLKOUT to Port out valid(1,2) — — 40** ns 15 TioV2ckH Port in valid before CLKOUT(1,2) 0.25 TCY+30* — — ns 16 TckH2ioI Port in hold after CLKOUT(1,2) 0* — — ns 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid(2) — — 100 ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1 TBD — — ns (I/O in setup time) 20 TioR Port output rise time(2) — 10 25** ns 21 TioF Port output fall time(2) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 2: Refer to Figure19-2 for load conditions. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 161

PIC16C5X FIGURE 19-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C5X-40 VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin(1) Note 1: Please refer to Figure19-2 for load conditions. TABLE 19-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X-40 Standard Operating Conditions (unless otherwise specified) AC Characteristics Operating Temperature 0°C  TA  +70°C (commercial) Operating Voltage VDD range is described in Section19.1. Param No. Symbol Characteristic Min Typ† Max Units Conditions 30 TmcL MCLR Pulse Width (low) 1000* — — ns VDD = 5.0V 31 Twdt Watchdog Timer Time-out Period 9.0* 18* 30* ms VDD = 5.0V (Comm) (No Prescaler) 32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Comm) 34 TioZ I/O Hi-impedance from MCLR Low 100* 300* 1000* ns * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary DS30453E-page 162  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 19-6: TIMER0 CLOCK TIMINGS - PIC16C5X-40 T0CKI 40 41 42 Note: Refer to Figure19-2 for load conditions. TABLE 19-4: TIMER0 CLOCK REQUIREMENTS PIC16C5X-40 Standard Operating Conditions (unless otherwise specified) AC Characteristics Operating Temperature 0°C  TA  +70°C for commercial Param Symbol Characteristic Min Typ† Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. † Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 163

PIC16C5X NOTES: Preliminary DS30453E-page 164  1997-2013 Microchip Technology Inc.

PIC16C5X 20.0 DEVICE CHARACTERIZATION - PIC16LC54C 40MHz The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran- teed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean – 3) respectively, where  is a standard deviation, over the whole temperature range. FIGURE 20-1: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 25 20 15 A) u (D P I 10 5.0 0 2.5 3.0 3.5 44..00 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 165

PIC16C5X FIGURE 20-2: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 25 20 15 A) u (D P I10 5.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 20-3: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 35 30 25 20 A) u (D P 15 I 10 5.0 (-40C) (+85C) 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary DS30453E-page 166  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 20-4: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.0 1.8 1.6 Volts) 1.4 Typ (+25C) (TH 1.2 V 1.0 0.8 0.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 20-5: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT (HS MODE) vs. VDD Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 3.4 3.2 3.0 2.8 2.6 s) 2.4 Typ (+25C) olt 2.2 V (H 2.0 T V 1.8 1.6 1.4 1.2 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 167

PIC16C5X FIGURE 20-6: TYPICAL IDD vs. VDD (40 MHZ, WDT DISABLED, HS MODE, 70C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 12 11 10 9.0 A) m (D D 8.0 I 7.0 6.0 5.0 4.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts) Preliminary DS30453E-page 168  1997-2013 Microchip Technology Inc.

PIC16C5X FIGURE 20-7: WDT TIMER TIME-OUT FIGURE 20-8: IOH vs. VOH, VDD = 5 V PERIOD vs. VDD(1) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Typical: statistical mean @ 25°C Minimum: mean – 3s (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 0 50 45 –10 40 Typ +125C 35 A) s) m d (m 30 (OH –20 Typ +85C o I eri T p Typ +125C Typ +25C D 25 W Typ –40C Typ +85C –30 20 Typ +25C 15 Typ –40C –40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 VOH (Volts) 5.0 2.0 3.0 4.0 5.0 6.0 7.0 VDD (Volts) Note 1: Prescaler set to 1:1. TABLE 20-1: INPUT CAPACITANCE Typical Capacitance (pF) Pin 18L PDIP 18L SOIC RA port 5.0 4.3 RB port 5.0 4.3 MCLR 17.0 17.0 OSC1 4.0 3.5 OSC2/CLKOUT 4.3 3.5 T0CKI 3.2 2.8 All capacitance values are typical at 25C. A part-to-part variation of ±25% (three standard deviations) should be taken into account. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 169

PIC16C5X FIGURE 20-9: IOL vs. VOL, VDD = 5 V Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 90 80 Max –40C 70 60 Typ +25C 50 A) m (L IO 40 Min +85C 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VOL (Volts) Preliminary DS30453E-page 170  1997-2013 Microchip Technology Inc.

PIC16C5X 21.0 PACKAGING INFORMATION 21.1 Package Marketing Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX PIC16C56A XXXXXXXXXXXXXXXXX -04I/P456 YYWWNNN 0023CBA 28-Lead Skinny PDIP (.300") Example XXXXXXXXXXXXXXXXX PIC16C55A XXXXXXXXXXXXXXXXX -04I/SP456 YYWWNNN 0023CBA 28-Lead PDIP (.600") Example XXXXXXXXXXXXXXX PIC16C55A XXXXXXXXXXXXXXX -04/P126 XXXXXXXXXXXXXXX YYWWNNN 0042CDA 18-Lead SOIC Example XXXXXXXXXXXX PIC16C54C XXXXXXXXXXXX -04/S0218 XXXXXXXXXXXX YYWWNNN 0018CDK 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX PIC16C57C XXXXXXXXXXXXXXXXXXXX -04/SO XXXXXXXXXXXXXXXXXXXX YYWWNNN 0015CBK 20-Lead SSOP Example XXXXXXXXXXX PIC16C54C XXXXXXXXXXX -04/SS218 YYWWNNN 0020CBP 28-Lead SSOP Example XXXXXXXXXXXX PIC16C57C XXXXXXXXXXXX -04/SS123 YYWWNNN 0025CBK Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 171

PIC16C5X Package Marking Information (Cont’d) 18-Lead CERDIP Windowed Example XXXXXXXX PIC16C54C XXXXXXXX /JW YYWWNNN 0001CBA 28-Lead CERDIP Windowed Example XXXXXXXXXXX PIC16C57C XXXXXXXXXXX /JW XXXXXXXXXXX YYWWNNN 0038CBA Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Preliminary DS30453E-page 172  1997-2013 Microchip Technology Inc.

PIC16C5X 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A c L A1 B1  B p eB Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .890 .898 .905 22.61 22.80 22.99 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 173

PIC16C5X 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A2 A L c  A1 B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 8.26 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .040 .053 .065 1.02 1.33 1.65 Lower Lead Width B .016 .019 .022 0.41 0.48 0.56 Overall Row Spacing § eB .320 .350 .430 8.13 8.89 10.92 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 Preliminary DS30453E-page 174  1997-2013 Microchip Technology Inc.

PIC16C5X 28-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1  E A A2 c L B1  A1 B p eB Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .160 .175 .190 4.06 4.45 4.83 Molded Package Thickness A2 .140 .150 .160 3.56 3.81 4.06 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88 Molded Package Width E1 .505 .545 .560 12.83 13.84 14.22 Overall Length D 1.395 1.430 1.465 35.43 36.32 37.21 Tip to Seating Plane L .120 .130 .135 3.05 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .030 .050 .070 0.76 1.27 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .620 .650 .680 15.75 16.51 17.27 Mold Draft Angle Top  5 10 15 5 10 15 Mold Draft Angle Bottom  5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-079 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 175

PIC16C5X 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E p E1 D 2 B n 1 h  45 c A A2   L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .291 .295 .299 7.39 7.49 7.59 Overall Length D .446 .454 .462 11.33 11.53 11.73 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle  0 4 8 0 4 8 Lead Thickness c .009 .011 .012 0.23 0.27 0.30 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top  0 12 15 0 12 15 Mold Draft Angle Bottom  0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051 Preliminary DS30453E-page 176  1997-2013 Microchip Technology Inc.

PIC16C5X 28-Lead Plastic Small Outline (SO) –Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1 h  45 c A A2   L A1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .050 1.27 Overall Height A .093 .099 .104 2.36 2.50 2.64 Molded Package Thickness A2 .088 .091 .094 2.24 2.31 2.39 Standoff § A1 .004 .008 .012 0.10 0.20 0.30 Overall Width E .394 .407 .420 10.01 10.34 10.67 Molded Package Width E1 .288 .295 .299 7.32 7.49 7.59 Overall Length D .695 .704 .712 17.65 17.87 18.08 Chamfer Distance h .010 .020 .029 0.25 0.50 0.74 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle Top  0 4 8 0 4 8 Lead Thickness c .009 .011 .013 0.23 0.28 0.33 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top  0 12 15 0 12 15 Mold Draft Angle Bottom  0 12 15 0 12 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 177

PIC16C5X 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1  c A A2  L A1  Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 20 20 Pitch p .026 0.65 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .322 7.59 7.85 8.18 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .278 .284 .289 7.06 7.20 7.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle  0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 Preliminary DS30453E-page 178  1997-2013 Microchip Technology Inc.

PIC16C5X 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D B 2 n 1  A c A2  A1 L  Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .026 0.65 Overall Height A .068 .073 .078 1.73 1.85 1.98 Molded Package Thickness A2 .064 .068 .072 1.63 1.73 1.83 Standoff § A1 .002 .006 .010 0.05 0.15 0.25 Overall Width E .299 .309 .319 7.59 7.85 8.10 Molded Package Width E1 .201 .207 .212 5.11 5.25 5.38 Overall Length D .396 .402 .407 10.06 10.20 10.34 Foot Length L .022 .030 .037 0.56 0.75 0.94 Lead Thickness c .004 .007 .010 0.10 0.18 0.25 Foot Angle  0 4 8 0.00 101.60 203.20 Lead Width B .010 .013 .015 0.25 0.32 0.38 Mold Draft Angle Top  0 5 10 0 5 10 Mold Draft Angle Bottom  0 5 10 0 5 10 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-150 Drawing No. C04-073 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 179

PIC16C5X 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 W2 D 2 n 1 W1 E A A2 c L A1 eB B1 B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 18 18 Pitch p .100 2.54 Top to Seating Plane A .170 .183 .195 4.32 4.64 4.95 Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19 Standoff A1 .015 .023 .030 0.38 0.57 0.76 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Ceramic Pkg. Width E1 .285 .290 .295 7.24 7.37 7.49 Overall Length D .880 .900 .920 22.35 22.86 23.37 Tip to Seating Plane L .125 .138 .150 3.18 3.49 3.81 Lead Thickness c .008 .010 .012 0.20 0.25 0.30 Upper Lead Width B1 .050 .055 .060 1.27 1.40 1.52 Lower Lead Width B .016 .019 .021 0.41 0.47 0.53 Overall Row Spacing § eB .345 .385 .425 8.76 9.78 10.80 Window Width W1 .130 .140 .150 3.30 3.56 3.81 Window Length W2 .190 .200 .210 4.83 5.08 5.33 * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-036 Drawing No. C04-010 Preliminary DS30453E-page 180  1997-2013 Microchip Technology Inc.

PIC16C5X 28-Lead Ceramic Dual In-line with Window (JW) –600 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 W D 2 n 1 E A A2 c L B1 eB A1 B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 28 28 Pitch p .100 2.54 Top to Seating Plane A .195 .210 .225 4.95 5.33 5.72 Ceramic Package Height A2 .155 .160 .165 3.94 4.06 4.19 Standoff A1 .015 .038 .060 0.38 0.95 1.52 Shoulder to Shoulder Width E .595 .600 .625 15.11 15.24 15.88 Ceramic Pkg. Width E1 .514 .520 .526 13.06 13.21 13.36 Overall Length D 1.430 1.460 1.490 36.32 37.08 37.85 Tip to Seating Plane L .125 .138 .150 3.18 3.49 3.81 Lead Thickness c .008 .010 .012 0.20 0.25 0.30 Upper Lead Width B1 .050 .058 .065 1.27 1.46 1.65 Lower Lead Width B .016 .020 .023 0.41 0.51 0.58 Overall Row Spacing § eB .610 .660 .710 15.49 16.76 18.03 Window Diameter W .270 .280 .290 6.86 7.11 7.37 * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-103 Drawing No. C04-013 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 181

PIC16C5X APPENDIX A: COMPATIBILITY APPENDIX B: REVISION HISTORY To convert code written for PIC16CXX to PIC16C5X, Revision KE (January 2013) the user should take the following steps: Added a note to each package outline drawing. 1. Check any CALL, GOTO or instructions that modify the PC to determine if any program memory page select operations (PA2, PA1, PA0 bits) need to be made. 2. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. 3. Eliminate any special function register page switching. Redefine data variables to reallocate them. 4. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. 5. Change RESET vector to proper value for processor used. 6. Remove any use of the ADDLW, RETURN and SUBLW instructions. 7. Rewrite any code segments that use interrupts. Preliminary DS30453E-page 182  1997-2013 Microchip Technology Inc.

PIC16C5X INDEX Extended......................................................82, 84 Industrial.......................................................80, 83 A PIC16LV54A Absolute Maximum Ratings Commercial..............................................108, 109 PIC16C54/55/56/57....................................................67 Industrial...................................................108, 109 PIC16C54A...............................................................103 DECF..................................................................................54 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ DECFSZ.............................................................................54 C58B/CR58B............................................................131 Development Support.........................................................61 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ Device Characterization C58B/CR58B-40.......................................................155 PIC16C54/55/56/57/CR54A.......................................91 PIC16CR54A..............................................................79 PIC16C54A...............................................................117 ADDWF...............................................................................51 PIC16C54C/C55A/C56A/C57C/C58B-40.................165 ALU.......................................................................................9 Device Reset Timer (DRT).................................................23 ANDLW...............................................................................51 Device Varieties....................................................................7 ANDWF...............................................................................51 Digit Carry (DC) bit.........................................................9, 29 Applications...........................................................................5 DRT....................................................................................23 Architectural Overview..........................................................9 E Assembler MPASM Assembler.....................................................61 Electrical Specifications PIC16C54/55/56/57....................................................67 B PIC16C54A...............................................................103 Block Diagram PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ On-Chip Reset Circuit.................................................20 C58B/CR58B............................................................131 PIC16C5X Series........................................................10 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ Timer0.........................................................................37 C58B/CR58B-40.......................................................155 TMR0/WDT Prescaler.................................................41 PIC16CR54A..............................................................79 Watchdog Timer..........................................................46 Errata....................................................................................3 Brown-Out Protection Circuit..............................................23 External Power-On Reset Circuit........................................21 BSF.....................................................................................52 F BTFSC................................................................................52 BTFSS................................................................................52 Family of Devices PIC16C5X.....................................................................6 C FSR Register......................................................................33 CALL.............................................................................31, 53 Value on reset.............................................................20 Carry (C) bit....................................................................9, 29 G Clocking Scheme................................................................13 CLRF...................................................................................53 General Purpose Registers CLRW.................................................................................53 Value on reset.............................................................20 CLRWDT.............................................................................53 GOTO...........................................................................31, 55 CMOS Technology................................................................1 H Code Protection............................................................43, 47 COMF.................................................................................54 High-Performance RISC CPU..............................................1 Compatibility.....................................................................182 I Configuration Bits................................................................44 I/O Interfacing.....................................................................35 D I/O Ports.............................................................................35 Data Memory Organization.................................................26 I/O Programming Considerations.......................................36 DC Characteristics ICEPIC In-Circuit Emulator.................................................62 PIC16C54/55/56/57 ID Locations..................................................................43, 47 Commercial...................................................68, 71 INCF...................................................................................55 Extended.......................................................70, 72 INCFSZ...............................................................................55 Industrial.......................................................69, 71 INDF Register.....................................................................33 PIC16C54A Value on reset.............................................................20 Commercial...............................................104, 109 Indirect Data Addressing....................................................33 Extended...................................................106, 109 Instruction Cycle.................................................................13 Industrial...................................................104, 109 Instruction Flow/Pipelining..................................................13 PIC16C54C/C55A/C56A/C57C/C58B-40 Instruction Set Summary....................................................49 Commercial...............................................157, 158 IORLW................................................................................56 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ IORWF................................................................................56 C58B/CR58B K Commercial...............................................134, 138 Extended...................................................137, 138 KeeLoq Evaluation and Programming Tools......................64 Industrial...................................................134, 138 L PIC16CR54A Commercial...................................................80, 83 Loading of PC.....................................................................31 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 183

PIC16C5X M Q MCLR Reset Q cycles..............................................................................13 Register values on......................................................20 Quick-Turnaround-Production (QTP) Devices......................7 Memory Map R PIC16C54/CR54/C55..................................................25 PIC16C56/CR56.........................................................25 RC Oscillator.......................................................................17 PIC16C57/CR57/C58/CR58.......................................25 Read Only Memory (ROM) Devices.....................................7 Memory Organization..........................................................25 Read-Modify-Write..............................................................36 MOVF..................................................................................56 Register File Map MOVLW...............................................................................56 PIC16C54, PIC16CR54, PIC16C55, PIC16C56, MOVWF..............................................................................57 PIC16CR56................................................................26 MPLAB C17 and MPLAB C18 C Compilers........................61 PIC16C57/CR57.........................................................27 MPLAB ICD In-Circuit Debugger.........................................63 PIC16C58/CR58.........................................................27 MPLAB ICE High Performance Universal In-Circuit Emulator Registers with MPLAB IDE..................................................................62 Special Function.........................................................28 MPLAB Integrated Development Environment Software....61 Value on reset.............................................................20 MPLINK Object Linker/MPLIB Object Librarian..................62 Reset..................................................................................19 Reset on Brown-Out...........................................................23 N RETLW...............................................................................57 NOP....................................................................................57 RLF.....................................................................................58 RRF....................................................................................58 O S One-Time-Programmable (OTP) Devices.............................7 OPTION..............................................................................57 Serialized Quick-Turnaround-Production (SQTP) Devices...7 OPTION Register................................................................30 SLEEP....................................................................43, 47, 58 Value on reset.............................................................20 Software Simulator (MPLAB SIM)......................................62 Oscillator Configurations.....................................................15 Special Features of the CPU..............................................43 Oscillator Types Special Function Registers.................................................28 HS...............................................................................15 Stack...................................................................................32 LP................................................................................15 STATUS Register...........................................................9, 29 RC...............................................................................15 Value on reset.............................................................20 XT...............................................................................15 SUBWF...............................................................................59 SWAPF...............................................................................59 P T PA0 bit.................................................................................29 PA1 bit.................................................................................29 Timer0 Paging.................................................................................31 Switching Prescaler Assignment................................40 PC.......................................................................................31 Timer0 (TMR0) Module...............................................37 Value on reset.............................................................20 TMR0 register - Value on reset...................................20 PD bit............................................................................19, 29 TMR0 with External Clock..........................................39 Peripheral Features...............................................................1 Timing Diagrams and Specifications PICDEM 1 Low Cost PIC MCU Demonstration Board........63 PIC16C54/55/56/57....................................................74 PICDEM 17 Demonstration Board......................................64 PIC16C54A...............................................................111 PICDEM 2 Low Cost PIC16CXX Demonstration Board......63 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ PICDEM 3 Low Cost PIC16CXXX Demonstration Board...64 C58B/CR58B............................................................140 PICSTART Plus Entry Level Development Programmer....63 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ Pin Configurations.................................................................2 C58B/CR58B-40.......................................................160 Pinout Description - PIC16C54, PIC16CR54, PIC16C56, PIC16CR54A..............................................................86 PIC16CR56, PIC16C58, PIC16CR58.................................11 Timing Parameter Symbology and Load Conditions Pinout Description - PIC16C55, PIC16C57, PIC16CR57...12 PIC16C54/55/56/57....................................................73 PORTA................................................................................35 PIC16C54A...............................................................110 Value on reset.............................................................20 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ PORTB................................................................................35 C58B/CR58B............................................................139 Value on reset.............................................................20 PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/ PORTC................................................................................35 C58B/CR58B-40.......................................................159 Value on reset.............................................................20 PIC16CR54A..............................................................85 Power-Down Mode..............................................................47 TO bit............................................................................19, 29 Power-On Reset (POR)......................................................21 TRIS....................................................................................59 Register values on......................................................20 TRIS Registers...................................................................35 Prescaler.............................................................................40 Value on reset.............................................................20 PRO MATE II Universal Device Programmer.....................63 U Program Counter.................................................................31 Program Memory Organization...........................................25 UV Erasable Devices............................................................7 Program Verification/Code Protection.................................47 Preliminary DS30453E-page 184  1997-2013 Microchip Technology Inc.

PIC16C5X W W Register Value on reset.............................................................20 Wake-up from SLEEP...................................................19, 47 Watchdog Timer (WDT)................................................43, 46 Period..........................................................................46 Programming Considerations.....................................46 Register values on reset.............................................20 WWW, On-Line Support.......................................................3 X XORLW...............................................................................60 XORWF...............................................................................60 Z Zero (Z) bit......................................................................9, 29 Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 185

PIC16C5X NOTES: Preliminary DS30453E-page 186  1997-2013 Microchip Technology Inc.

PIC16C5X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events Preliminary © 1997-2013 Microchip Technology Inc. DS30453E-page187

PIC16C5X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16C5X Literature Number: DS30453E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? Preliminary DS30453E-page188 © 1997-2013 Microchip Technology Inc.

PIC16C5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. - XX X /XX XXX Examples: Device Frequency Temperature Package Pattern a) PIC16C55A - 04/P 301 = Commercial Temp., Range/OSC Range PDIP package, 4 MHz, standard VDD limits, Type QTP pattern #301 b) PIC16LC54C - 04I/SO Industrial Temp., SOIC Device PIC16C54 PIC16C54T(2) package, 200 kHz, extended VDD limits PIC16C54A PIC16C54AT(2) c) PIC16C57 - RC/SP = RC Oscillator, commer- PIC16CR54A PIC16CR54AT(2) cial temp, skinny PDIP package, 4 MHz, stan- PIC16C54C PIC16C54CT(2) dard VDD limits PIC16CR54C PIC16CR54CT(2) d) PIC16C58BT -40/SS 123 = commercial PIC16C55 PIC16C55T(2) temp, SSOP package in tape and reel, 4 PIC16C55A PIC16C55AT(2) MHz, extended VDD limits, ROM pattern PIC16C56 PIC16C56T(2) PIC16C56A PIC16C56AT(2) #123 PIC16CR56A PIC16CR56AT(2) PIC16C57 PIC16C57T(2) PIC16C57C PIC16C57CT(2) PIC16CR57C PIC16CR57CT(2) PIC16C58B PIC16C58BT(2) Note 1: C = normal voltage range PIC16CR58B PIC16CR58BT(2) LC = extended 2: T = in tape and reel - SOIC and SSOP packages only Frequency Range/ RC Resistor Capacitor Oscillator Type LP Low Power Crystal 3: JW Devices are UV erasable and can be XT Standard Crystal/Resonator programmed to any device configura- HS High Speed Crystal tion. JW Devices meet the electrical 02 200 KHz (LP) or 2 MHz (XT and RC) requirements of each oscillator type, 04 200 KHz (LP) or 4 MHz (XT and RC) including LC devices. 10 10 MHz (HS only) 20 20 MHz (HS only) 4: b = Blank 40 40 MHz (HS only) b(4) No oscillator type for JW packages(3) *RC/LP/XT/HS are for 16C54/55/56/57 devices only -02 is available for 16LV54A only -04/10/20 options are available for all other devices -40 is available for 16C54C/55A/56A/57C/58B devices only Temperature Range b(4) = 0C to +70C I = -40C to +85C E = -40C to +125C Package S = Die in Waffle Pack JW = 28-pin 600 mil/18-pin 300 mil windowed CER- DIP(3) P = 28-pin 600 mil/18-pin 300 mil PDIP SO = 300 mil SOIC SS = 209 mil SSOP SP = 28-pin 300 mil Skinny PDIP *See Section 21 for additional package information. Pattern QTP, SQTP, ROM code (factory specified) or Special Requirements. Blank for OTP and Windowed devices. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com) Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page189

PIC16C5X Preliminary DS30453E-page 190  1997-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1997-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620769355 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary  1997-2013 Microchip Technology Inc. DS30453E-page 191

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16C54-RC/P PIC16C58BT-04I/SS PIC16C54T-HSI/SS PIC16C54T-HSI/SO PIC16C58BT-04I/SO PIC16C54AT- 10I/SS PIC16C54AT-10I/SO PIC16C58B-20I/SO PIC16C58B-20I/SS PIC16C54-HS/P PIC16C57-LPE/SP PIC16C56-LPE/SO PIC16C57-LPE/SS PIC16LC56A-04I/SS PIC16C56-LPE/SS PIC16C54CT-04I/SO PIC16C57CT- 04E/SO PIC16C54CT-04I/SS PIC16C57CT-04E/SS PIC16C55-LPE/SP PIC16C57-LPE/SO PIC16C54-LPE/SO PIC16C54-LPE/SS PIC16LC56A-04I/SO PIC16C55-LPE/SO PIC16C55-LPE/SS PIC16LC56A-04/P PIC16LV54A- 02I/P PIC16LC54A-04/P PIC16LC55A-04/P PIC16C56T-LPE/SS PIC16C56T-LPE/SO PIC16LC56AT-04/SS PIC16LC56AT-04/SO PIC16C56A-04I/SO PIC16C56A-04I/SS PIC16LC54AT-04E/SS PIC16LC54AT-04E/SO PIC16C58B-04/SO PIC16C57C-04/SO PIC16C57C-04/SS PIC16C57C-04/SP PIC16C56A-04/SS PIC16C54A-04/SS PIC16C55A-04/SP PIC16C56A-04/SO PIC16C54C-04/SS PIC16C55A-04/SS PIC16C55A-04/SO PIC16C58B- 04/SS PIC16C54C-04/SO PIC16C55-XT/P PIC16C54-HSE/SO PIC16C54-HSE/SS PIC16C56-HSE/SS PIC16C56- HSE/SO PIC16C55-HSE/SS PIC16C57-HSE/SO PIC16C57-HSE/SS PIC16C55-HSE/SP PIC16C57-HSE/SP PIC16C55-HSE/SO PIC16C54CT-20/SS PIC16C54CT-20/SO PIC16C54AT-20/SO PIC16C54AT-20/SS PIC16C57C- 04/P PIC16C55AT-20/SS PIC16C55AT-20/SO PIC16C57CT-20/SS PIC16C57CT-20/SO PIC16C56A-04E/SS PIC16C55-LP/P PIC16C56A-04E/SO PIC16C55T-LPE/SS PIC16C55T-LPE/SO PIC16C55-RC/SO PIC16LC57CT- 04/SS PIC16LC57CT-04/SO PIC16C54-10/P PIC16C55A-20E/P PIC16C54T-10/SO PIC16C54T-10/SS PIC16C57T- 10/SO PIC16C54C-20E/P PIC16C54A-20E/P PIC16C56A-20E/P PIC16C57T-10/SS PIC16C58B-20E/P PIC16C55T-10/SS PIC16C54C-04/P PIC16C55T-10/SO PIC16C57T-HSE/SS PIC16C56T-10/SO PIC16C57T- HSE/SO PIC16C57C-20E/P PIC16C56T-10/SS PIC16C54T-RCI/SO PIC16C56T-HSE/SS PIC16C56AT-04/SO