PIC16C505 14-Pin, 8-Bit CMOS Microcontroller Device included in this Data Sheet: Special Microcontroller Features: PIC16C505 • In-Circuit Serial Programming (ICSP™) High-Performance RISC CPU: • Power-on Reset (POR) • Device Reset Timer (DRT) • Only 33 instructions to learn • Operating speed: • Watchdog Timer (WDT) with dedicated on-chip - DC - 20 MHz clock input RC oscillator for reliable operation - DC - 200 ns instruction cycle • Programmable Code Protection • Internal weak pull-ups on I/O pins Memory • Wake-up from Sleep on pin change Device Program Data • Power-saving Sleep mode • Selectable oscillator options: PIC16C505 1024 x 12 72 x 8 - INTRC: Precision internal 4 MHz oscillator • Direct, indirect and relative addressing modes for - EXTRC: External low-cost RC oscillator data and instructions - XT: Standard crystal/resonator • 12-bit wide instructions - HS: High speed crystal/resonator • 8-bit wide data path - LP: Power saving, low frequency • 2-level deep hardware stack crystal • Eight special function hardware registers CMOS Technology: • Direct, indirect and relative addressing modes for data and instructions • Low-power, high-speed CMOS EPROM • All single cycle instructions (200 ns) except for technology • Fully static design program branches which are two-cycle • Wide operating voltage range (2.5V to 5.5V) Peripheral Features: • Wide temperature ranges • 11 I/O pins with individual direction control - Commercial: 0°C to +70°C • 1 input pin - Industrial: -40°C to +85°C • High current sink/source for direct LED drive - Extended: -40°C to +125°C • Timer0: 8-bit timer/counter with 8-bit - < 1.0 m A typical standby current @ 5V programmable prescaler • Low power consumption Pin Diagram: - < 2.0 mA @ 5V, 4 MHz - 15m A typical @ 3.0V, 32 kHz for TMR0 PDIP, SOIC, Ceramic Side Brazed running in SLEEP mode - < 1.0 m A typical standby current @ 5V VDD 1 14 VSS RB5/OSC1/CLKIN 2 P 13 RB0 RB4/OSC2/CLKOUT 3 IC 12 RB1 RB3/MCLR/VPP 4 16 11 RB2 RC5/T0CKI 5 C 10 RC0 5 RC4 6 0 9 RC1 RC3 7 5 8 RC2 (cid:211) 1999 Microchip Technology Inc. DS40192C-page 1

PIC16C505 TABLE OF CONTENTS 1.0 General Description.....................................................................................................................................................................3 2.0 PIC16C505 Device Varieties.......................................................................................................................................................5 3.0 Architectural Overview................................................................................................................................................................7 4.0 Memory Organization................................................................................................................................................................11 5.0 I/O Port......................................................................................................................................................................................19 6.0 Timer0 Module and TMR0 Register..........................................................................................................................................23 7.0 Special Features of the CPU.....................................................................................................................................................27 8.0 Instruction Set Summary...........................................................................................................................................................39 9.0 Development Support................................................................................................................................................................51 10.0 Electrical Characteristics - PIC16C505.....................................................................................................................................57 11.0 DC and AC Characteristics - PIC16C505..................................................................................................................................71 11.0 Packaging Information...............................................................................................................................................................75 Index....................................................................................................................................................................................................79 On-Line Support...................................................................................................................................................................................81 Reader Response................................................................................................................................................................................82 PIC16C505 Product Identification System ..........................................................................................................................................83 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi- sion of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. DS40192C-page 2 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC16C505 from Microchip Technology is a low- The PIC16C505 fits in applications ranging from per- cost, high-performance, 8-bit, fully static, EPROM/ sonal care appliances and security systems to low- ROM-based CMOS microcontroller. It employs a RISC power remote transmitters/receivers. The EPROM architecture with only 33 single word/single cycle technology makes customizing application programs instructions. All instructions are single cycle (200 m s) (transmitter codes, appliance settings, receiver fre- except for program branches, which take two cycles. quencies, etc.) extremely fast and convenient. The The PIC16C505 delivers performance an order of mag- small footprint packages, for through hole or surface nitude higher than its competitors in the same price cat- mounting, make this microcontroller perfect for applica- egory. The 12-bit wide instructions are highly tions with space limitations. Low-cost, low-power, high- symmetrical resulting in a typical 2:1 code compression performance, ease of use and I/O flexibility make the over other 8-bit microcontrollers in its class. The easy PIC16C505 very versatile even in areas where no to use and easy to remember instruction set reduces microcontroller use has been considered before (e.g., development time significantly. timer functions, replacement of “glue” logic and PLD’s The PIC16C505 product is equipped with special fea- in larger systems, and coprocessor applications). tures that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are five oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC16C505 is available in the cost-effective One- Time-Programmable (OTP) version, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in OTP microcontrollers, while benefiting from the OTP’s flexibility. The PIC16C505 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost development pro- grammer and a full featured programmer. All the tools (cid:210) are supported on IBM PC and compatible machines. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 3

PIC16C505 TABLE 1-1: PIC16C505 DEVICE PIC16C505 Maximum Frequency 20 Clock of Operation (MHz) EPROM Program Memory 1024 Memory Data Memory (bytes) 72 Timer Module(s) TMR0 Peripherals Wake-up from SLEEP on Yes pin change I/O Pins 11 Input Pins 1 Features Internal Pull-ups Yes In-Circuit Serial Programming Yes Number of Instructions 33 Packages 14-pin DIP, SOIC, JW The PIC16C505 device has Power-on Reset, selectable Watchdog Timer, selectable code protect, high I/O current capability and precision internal oscillator. The PIC16C505 device uses serial programming with data pin RB0 and clock pin RB1. DS40192C-page 4 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 2.0 PIC16C505 DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP) Devices A variety of packaging options are available. Depending on application and production Microchip offers a QTP Programming Service for requirements, the proper device option can be factory production orders. This service is made selected using the information in this section. When available for users who choose not to program medium placing orders, please use the PIC16C505 Product to high quantity units and whose code patterns have Identification System at the back of this data sheet to stabilized. The devices are identical to the OTP devices specify the correct part number. but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype 2.1 UV Erasable Devices verification procedures do apply before production The UV erasable version, offered in a ceramic win- shipments are available. Please contact your local dowed package, is optimal for prototype development Microchip Technology sales office for more details. and pilot programs. 2.4 Serialized Quick-Turnaround The UV erasable version can be erased and Production (SQTPSM) Devices reprogrammed to any of the configuration modes. Microchip offers a unique programming service, where Note: Please note that erasing the device will a few user-defined locations in each device are also erase the pre-programmed internal programmed with different serial numbers. The serial calibration value for the internal oscillator. numbers may be random, pseudo-random or The calibration value must be saved prior sequential. to erasing the part. (cid:226) (cid:226) Serial programming allows each device to have a Microchip’s PICSTART PLUS and PRO MATE II pro- unique number, which can serve as an entry-code, grammers all support programming of the PIC16C505. password or ID number. Third party programmers also are available; refer to the Microchip Third Party Guide, (DS00104), for a list of sources. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility of frequent code updates or small volume applications. The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 5

PIC16C505 NOTES: DS40192C-page 6 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 3.0 ARCHITECTURAL OVERVIEW The PIC16C505 device contains an 8-bit ALU and working register. The ALU is a general purpose The high performance of the PIC16C505 can be arithmetic unit. It performs arithmetic and Boolean attributed to a number of architectural features functions between data in the working register and any commonly found in RISC microprocessors. To begin register file. with, the PIC16C505 uses a Harvard architecture in which program and data are accessed on separate The ALU is 8-bits wide and capable of addition, buses. This improves bandwidth over traditional von subtraction, shift and logical operations. Unless Neumann architecture where program and data are otherwise mentioned, arithmetic operations are two's fetched on the same bus. Separating program and complement in nature. In two-operand instructions, data memory further allows instructions to be sized one operand is typically the W (working) register. The differently than the 8-bit wide data word. Instruction other operand is either a file register or an immediate opcodes are 12 bits wide, making it possible to have constant. In single operand instructions, the operand is all single word instructions. A 12-bit wide program either the W register or a file register. memory access bus fetches a 12-bit instruction in a The W register is an 8-bit working register used for single cycle. A two-stage pipeline overlaps fetch and ALU operations. It is not an addressable register. execution of instructions. Consequently, all instructions Depending on the instruction executed, the ALU may (33) execute in a single cycle (200ns @ 20MHz) affect the values of the Carry (C), Digit Carry (DC), except for program branches. and Zero (Z) bits in the STATUS register. The C and The Table below lists program memory (EPROM) and DC bits operate as a borrow and digit borrow out bit, data memory (RAM) for the PIC16C505. respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. Memory Device A simplified block diagram is shown in Figure3-1, with Program Data the corresponding device pins described in Table3-1. PIC16C505 1024 x 12 72 x 8 The PIC16C505 can directly or indirectly address its register files and data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C505 has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16C505 simple yet efficient. In addition, the learning curve is reduced significantly. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 7

PIC16C505 FIGURE 3-1: PIC16C505 BLOCK DIAGRAM 12 Data Bus 8 PORTB Program Counter EPROM RB0 1K x 12 RB1 Program RAM RB2 Memory STACK1 72 bytes RB3/MCLR/VPP STACK2 File RB4/OSC2/CLKOUT Registers RB5/OSC1/CLKIN Program 12 Bus RAM Addr 9 PORTC Addr MUX Instruction reg RC0 Direct Addr 5 Indirect RC1 5-7 Addr RC2 RC3 FSR reg RC4 RC5/T0CKI STATUS reg 8 3 MUX Device Reset Timer Instruction Power-on ALU Decode & Reset Control 8 Watchdog Timer W reg OSC1/CLKIN Timing OSC2 Generation Internal RC OSC Timer0 MCLR VDD, VSS DS40192C-page 8 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 TABLE 3-1: PIC16C505 PINOUT DESCRIPTION DIP SOIC I/O/P Buffer Name Description Pin # Pin # Type Type RB0 13 13 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. RB1 12 12 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. RB2 11 11 I/O TTL Bi-directional I/O port. RB3/MCLR/VPP 4 4 I TTL/ST Input port/master clear (reset) input/programming volt- age input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull- up only when configured as RB3. ST when configured as MCLR. RB4/OSC2/CLKOUT 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con- nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, RB4 in other modes). Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. In EXTRC and INTRC modes, the pin output can be configured to CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. RB5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external clock source input (RB5 in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when RB5, ST input in external RC oscillator mode. RC0 10 10 I/O TTL Bi-directional I/O port. RC1 9 9 I/O TTL Bi-directional I/O port. RC2 8 8 I/O TTL Bi-directional I/O port. RC3 7 7 I/O TTL Bi-directional I/O port. RC4 6 6 I/O TTL Bi-directional I/O port. RC5/T0CKI 5 5 I/O ST Bi-directional I/O port. Can be configured as T0CKI. VDD 1 1 P — Positive supply for logic and I/O pins VSS 14 14 P — Ground reference for logic and I/O pins Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input, ST = Schmitt Trigger input (cid:211) 1999 Microchip Technology Inc. DS40192C-page 9

PIC16C505 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining The clock input (OSC1/CLKIN pin) is internally divided An Instruction cycle consists of four Q cycles (Q1, Q2, by four to generate four non-overlapping quadrature Q3 and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle, program counter is incremented every Q1, and the while decode and execute takes another instruction instruction is fetched from program memory and cycle. However, due to the pipelining, each instruction latched into the instruction register in Q4. It is decoded effectively executes in one cycle. If an instruction and executed during the following Q1 through Q4. The causes the program counter to change (e.g., GOTO) clocks and instruction execution flow is shown in then two cycles are required to complete the Figure3-2 and Example3-1. instruction (Example3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC+1 PC+2 Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTB, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS40192C-page 10 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16C505 memory is organized into program mem- PIC16C505 ory and data memory. For the PIC16C505, a paging scheme is used. Program memory pages are PC<11:0> accessed using one STATUS register bit. Data mem- CALL, RETLW 12 ory banks are accessed using the File Select Register (FSR). Stack Level 1 Stack Level 2 4.1 Program Memory Organization The PIC16C505 devices have a 12-bit Program Reset Vector (note 1) 0000h Counter (PC). The 1K x 12 (0000h-03FFh) for the PIC16C505 are physically implemented. Refer to Figure4-1. Accessing a location above this boundary will cause a wrap-around within the first 1K x 12 space. The ory effective reset vector is at 0000h, (see Figure4-1). me ec Location 03FFh contains the internal clock oscillator Mpa 01FFh calibration value. This value should never be ser S 0200h U overwritten. On-chip Program Memory 1024 Words 03FFh 0400h 7FFh Note 1: Address 0000h becomes the effective reset vector. Location 03FFh contains the MOVLW XX INTERNAL RC oscillator calibration value. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 11

PIC16C505 4.2 Data Memory Organization For the PIC16C505, the register file is composed of 8 Special Function Registers, 24 General Purpose Data memory is composed of registers or bytes of Registers and 48 General Purpose Registers that may RAM. Therefore, data memory for a device is specified be addressed using a banking scheme (Figure4-2). by its register file. The register file is divided into two functional groups: Special Function Registers and 4.2.1 GENERAL PURPOSE REGISTER FILE General Purpose Registers. The General Purpose Register file is accessed, either The Special Function Registers include the TMR0 directly or indirectly, through the File Select Register register, the Program Counter (PCL), the Status FSR (Section4.8). Register, the I/O registers (ports) and the File Select Register (FSR). In addition, Special Function Registers are used to control the I/O port configuration and prescaler options. The General Purpose Registers are used for data and control information under command of the instructions. FIGURE 4-2: PIC16C505 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 20h 40h 60h 01h TMR0 02h PCL 03h STATUS Addresses map back to addresses in Bank 0. 04h FSR 05h OSCCAL 06h PORTB 07h POR TC 08h General Purpose 0Fh Registers 2Fh 4Fh 6Fh 10h 30h 50h 70h General General General General Purpose Purpose Purpose Purpose Registers Registers Registers Registers 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: Not a physical register. DS40192C-page 12 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets. The Special Function Registers associated The Special Function Registers (SFRs) are registers with the “core” functions are described in this section. used by the CPU and peripheral functions to control Those related to the operation of the peripheral the operation of the device (Table4-1). features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY Value on Value on Power-On All Other Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Resets(2) 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111 03h STATUS RBWUF — PAO TO PD Z DC C 0001 1xxx q00q quuu(1) 04h FSR Indirect data memory address pointer 110x xxxx 11uu uuuu 05h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- uuuu uu-- N/A TRISB — — I/O control registers --11 1111 --11 1111 N/A TRISC — — I/O control registers --11 1111 --11 1111 N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = depends on condition. Note 1: If reset was due to wake-up on pin change, then bit 7 = 1. All other rests will cause bit 7 = 0. Note 2: Other (non-power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 13

PIC16C505 4.3 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register This register contains the arithmetic status of the ALU, as 000u u1uu (where u = unchanged). the RESET status and the page preselect bit. It is recommended, therefore, that only BCF, BSF and The STATUS register can be the destination for any MOVWF instructions be used to alter the STATUS instruction, as with any other register. If the STATUS register, because these instructions do not affect the register is the destination for an instruction that affects Z, DC or C bits from the STATUS register. For other the Z, DC or C bits, then the write to these three bits is instructions, which do affect STATUS bits, see disabled. These bits are set or cleared according to Instruction Set Summary. the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 4-1: STATUS REGISTER (ADDRESS:03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x RBWUF — PA0 TO PD Z DC C R = Readable bit W = Writable bit bit7 6 5 4 3 2 1 bit0 U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: RBWUF: I/O reset bit 1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset bit 6: Unimplemented bit 5: PA0: Program page preselect bits 1 = Page 1 (200h - 3FFh) 0 = Page 0 (000h - 1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively 0 = A carry did not occur 0 = A borrow occurred DS40192C-page 14 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 4.4 OPTION Register Note: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled The OPTION register is a 8-bit wide, write-only for that pin (i.e., note that TRIS overrides register, which contains various control bits to OPTION control of RBPU and RBWU). configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<7:0> bits. REGISTER 4-2: OPTION REGISTER W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit bit7 6 5 4 3 2 1 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: RBWU: Enable wake-up on pin change (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 6: RBPU: Enable weak pull-ups (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 5: T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin (overrides TRIS <RC57> 0 = Transition on internal instruction cycle clock, Fosc/4 bit 4: T0SE: Timer0 source edge select bit 1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin bit 3: PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS<2:0>: Prescaler rate select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 (cid:211) 1999 Microchip Technology Inc. DS40192C-page 15

PIC16C505 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for calibration Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part, so it can be repro- grammed correctly later. After you move in the calibration constant, do not change the value. See Section7.2.5 REGISTER 4-3: OSCCAL REGISTER (ADDRESS 05h) PIC16C505 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented read as ‘0’ DS40192C-page 16 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program The Program Counter is set upon a RESET, which Counter (PC) will contain the address of the next means that the PC addresses the last location in the program instruction to be executed. The PC value is last page (i.e., the oscillator calibration instruction.) increased by one every instruction cycle, unless an After executing MOVLW XX, the PC will roll over to instruction changes the PC. location 00h and begin executing user code. For a GOTO instruction, bits 8:0 of the PC are provided The STATUS register page preselect bits are cleared by the GOTO instruction word. The PC Latch (PCL) is upon a RESET, which means that page 0 is pre- mapped to PC<7:0>. Bit 5 of the STATUS register selected. provides page information to bit 9 of the PC Therefore, upon a RESET, a GOTO instruction will (Figure4-3). automatically cause the program to jump to page0 For a CALL instruction, or any instruction where the until the value of the page bits is altered. PCL is the destination, bits 7:0 of the PC again are 4.7 Stack provided by the instruction word. However, PC<8> does not come from the instruction word, but is always PIC16C505 devices have a 12-bit wide hardware cleared (Figure4-3). push/pop stack. Instructions where the PCL is the destination, or A CALL instruction will push the current value of stack Modify PCL instructions, include MOVWF PC, ADDWF 1 into stack 2 and then push the current program PC, and BSF PC,5. counter value, incremented by one, into stack level 1. If Note: Because PC<8> is cleared in the CALL more than two sequential CALL’s are executed, only instruction or any Modify PCL instruction, the most recent two return addresses are stored. all subroutine calls or computed jumps are A RETLW instruction will pop the contents of stack level limited to the first 256 locations of any pro- 1 into the program counter and then copy stack level 2 gram memory page (512 words long). contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled with the FIGURE 4-3: LOADING OF PC address previously stored in level 2. Note that the BRANCH INSTRUCTIONS - Wregister will be loaded with the literal value specified PIC16C505 in the instruction. This is particularly useful for the implementation of data look-up tables within the GOTO Instruction program memory. 11 10 9 8 7 0 PC PCL Note 1: There are no STATUS bits to indicate stack overflows or stack underflow condi- Instruction Word tions. PA0 Note 2: There are no instructions mnemonics 7 0 called PUSH or POP. These are actions that occur from the execution of the CALL, STATUS RETLW, and instructions. CALL or Modify PCL Instruction 11 10 9 8 7 0 PC PCL Instruction Word Reset to ‘0’ PA0 7 0 STATUS (cid:211) 1999 Microchip Technology Inc. DS40192C-page 17

PIC16C505 4.8 Indirect Data Addressing; INDF and EXAMPLE 4-2: HOW TO CLEAR RAM FSR Registers USING INDIRECT ADDRESSING The INDF register is not a physical register. movlw 0x10 ;initialize pointer Addressing INDF actually addresses the register movwf FSR ; to RAM whose address is contained in the FSR register (FSR NEXT clrf INDF ;clear INDF register is a pointer). This is indirect addressing. incf FSR,F ;inc pointer btfsc FSR,4 ;all done? EXAMPLE 4-1: INDIRECT ADDRESSING goto NEXT ;NO, clear next CONTINUE • Register file 07 contains the value 10h : ;YES, continue • Register file 08 contains the value 0Ah : The FSR is a 5-bit wide register. It is used in • Load the value 07 into the FSR register conjunction with the INDF register to indirectly address • A read of the INDF register will return the value the data memory area. of10h The FSR<4:0> bits are used to select data memory • Increment the value of the FSR register by one addresses 00h to 1Fh. (FSR = 08) The device uses FSR<6:5> to select between banks • A read of the INDR register now will return the 0:3. value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example4-2. FIGURE 4-4: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing (FSR) 6 5 4 (opcode) 0 6 5 4 (FSR) 0 bank select location select bank location select 00 01 10 11 00h Addresses map back to addresses in Bank 0. Data 0Fh Memory(1) 10h 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register map detail see Section4.2. DS40192C-page 18 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 5.0 I/O PORT 5.4 I/O Interfacing As with any other register, the I/O register can be The equivalent circuit for an I/O port pin is shown in written and read under program control. However, Figure5-1. All port pins except RB3, which is input read instructions (e.g., MOVF PORTB,W) always read only, may be used for both input and output operations. the I/O pins independent of the pin’s input/output For input operations, these ports are non-latching. Any modes. On RESET, all I/O ports are defined as input input must be present until read by an input instruction (inputs are at hi-impedance) since the I/O control (e.g., MOVF PORTB,W). The outputs are latched and registers are all set. remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction 5.1 PORTB control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O PORTB is an 8-bit I/O register. Only the low order 6 pin (except RB3) can be programmed individually as bits are used (RB<5:0>). Bits 7 and 6 are input or output. unimplemented and read as '0's. Please note that RB3 is an input only pin. The configuration word can set FIGURE 5-1: EQUIVALENT CIRCUIT several I/O’s to alternate functions. When acting as alternate functions, the pins will read as ‘0’ during port FOR A SINGLE I/O PIN read. Pins RB0, RB1, RB3 and RB4 can be configured Data with weak pull-ups and also with wake-up on change. Bus The wake-up on change and weak pull-up functions D Q Data are not pin selectable. If pin 4 is configured as MCLR, VDD WR Latch weak pull-up is always off and wake-up on change for Port this pin is not enabled. CK Q P 5.2 PORTC W N I/O PORTC is an 8-bit I/O register. Only the low order 6 bits Reg pin(1) are used (RC<5:0>). Bits 7 and 6 are unimplemented D Q and read as ‘0’s. TRIS VSS Latch TRIS ‘f’ 5.3 TRIS Registers CK Q The output driver control register is loaded with the contents of the W register by executing the TRIS f Reset instruction. A '1' from a TRIS register bit puts the (2) corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The RD Port exceptions are RB3, which is input only, and RC5, which may be controlled by the option register. See Note 1: I/O pins have protection diodes to VDD and VSS. Register4-2. Note 2: See Table 3-1 for buffer type. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 19

PIC16C505 TABLE 5-1: SUMMARY OF PORT REGISTERS Value on Power-On Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset All Other Resets N/A TRISB — — I/O control registers --11 1111 --11 1111 N/A TRISC — — I/O control registers --11 1111 --11 1111 N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS RBWUF — PAO TO PD Z DC C 0001 1xxx q00q quuu(1) 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = depends on condition. Note 1: If reset was due to wake-up on pin change, then bit 7 = 1. All other rests will cause bit 7 = 0. 5.5 I/O Programming Considerations EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 5.5.1 BI-DIRECTIONAL I/O PORTS I/O PORT Some instructions operate internally as read followed ;Initial PORTB Settings ; PORTB<5:3> Inputs by write operations. The BCF and BSF instructions, for ; PORTB<2:0> Outputs example, read the entire port into the CPU, execute ; the bit operation and re-write the result. Caution must ; PORTB latch PORTB pins be used when these instructions are applied to a port ; ---------- ---------- where one or more pins are used as input/outputs. For BCF PORTB, 5 ;--01 -ppp --11 pppp example, a BSF operation on bit5 of PORTB will cause BCF PORTB, 4 ;--10 -ppp --11 pppp all eight bits of PORTB to be read into the CPU, bit5 to MOVLW 007h ; be set and the PORTB value to be written to the output TRIS PORTB ;--10 -ppp --11 pppp latches. If another bit of PORTB is used as a bi- ; directional I/O pin (say bit0) and it is defined as an ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused input at this time, the input signal present on the pin ;RB5 to be latched as the pin value (High). itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the 5.5.2 SUCCESSIVE OPERATIONS ON I/O previous content. As long as the pin stays in the input PORTS mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch The actual write to an I/O port happens at the end of may now be unknown. an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle Example5-1 shows the effect of two sequential read- (Figure5-2). Therefore, care must be exercised if a modify-write instructions (e.g., BCF, BSF, etc.) on an write followed by a read operation is carried out on the I/O port. same I/O port. The sequence of instructions should A pin actively outputting a high or a low should not be allow the pin voltage to stabilize (load dependent) driven from external devices at the same time in order before the next instruction causes that file to be read to change the level on this pin (“wired-or”, “wired- into the CPU. Otherwise, the previous state of that pin and”). The resulting high output currents may damage may be read into the CPU rather than the new state. the chip. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. DS40192C-page 20 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 FIGURE 5-2: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB Instruction followed by a read from PORTB. fetched MOVWF PORTB MOVF PORTB,W NOP NOP Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle. RB<5:0> TPD = propagation delay Port pin Port pin Therefore, at higher clock frequencies, a written here sampled here write followed by a read may be problematic. Instruction executed MOVWF PORTB MOVF PORTB,W NOP (Write to PORTB) (Read PORTB) (cid:211) 1999 Microchip Technology Inc. DS40192C-page 21

PIC16C505 NOTES: DS40192C-page 22 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 6.0 TIMER0 MODULE AND TMR0 Counter mode is selected by setting the T0CS bit REGISTER (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The The Timer0 module has the following features: T0SE bit (OPTION<4>) determines the source edge. • 8-bit timer/counter register, TMR0 Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed - Readable and writable in detail in Section6.1. • 8-bit software programmable prescaler The prescaler may be used by either the Timer0 • Internal or external clock select module or the Watchdog Timer, but not both. The - Edge select for external clock prescaler assignment is controlled in software by the Figure6-1 is a simplified block diagram of the Timer0 control bit PSA (OPTION<3>). Clearing the PSA bit module. will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is Timer mode is selected by clearing the T0CS bit assigned to the Timer0 module, prescale values of 1:2, (OPTION<5>). In timer mode, the Timer0 module will 1:4,..., 1:256 are selectable. Section6.2 details the increment every instruction cycle (without prescaler). If operation of the prescaler. TMR0 register is written, the increment is inhibited for the following two cycles (Figure6-2 and Figure6-3). A summary of registers associated with the Timer0 The user can work around this by writing an adjusted module is found in Table6-1. value to the TMR0 register. FIGURE 6-1: TIMER0 BLOCK DIAGRAM Data Bus RC5/T0CKI FOSC/4 0 Pin PSout 8 1 Sync with 1 Internal TMR0 reg Clocks Programmable 0 PSout Prescaler(2) Sync T0SE (2 TCY delay) 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) Note1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure6-5). (cid:211) 1999 Microchip Technology Inc. DS40192C-page 23

PIC16C505 FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0+1 T0+2 NT0 NT0+1 NT0+2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0+1 NT0 NT0+1 T0 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Power-On All Other Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Resets 01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu N/A OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRISC — — RC5 RC4 RC3 RC2 RC1 RC0 --11 1111 --11 1111 Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged. DS40192C-page 24 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 6.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type When an external clock input is used for Timer0, it prescaler, so that the prescaler output is symmetrical. must meet certain requirements. The external clock For the external clock to meet the sampling requirement is due to internal phase clock (TOSC) requirement, the ripple counter must be taken into synchronization. Also, there is a delay in the actual account. Therefore, it is necessary for T0CKI to have a incrementing of Timer0 after synchronization. period of at least 4TOSC (and a small RC delay of 40ns) divided by the prescaler value. The only 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION requirement on T0CKI high and low time is that they When no prescaler is used, the external clock input is do not violate the minimum pulse width requirement of the same as the prescaler output. The synchronization 10 ns. Refer to parameters 40, 41 and 42 in the of T0CKI with the internal phase clocks is electrical specification of the desired device. accomplished by sampling the prescaler output on the 6.1.2 TIMER0 INCREMENT DELAY Q2 and Q4 cycles of the internal phase clocks (Figure6-4). Therefore, it is necessary for T0CKI to be Since the prescaler output is synchronized with the high for at least 2TOSC (and a small RC delay of 20ns) internal clocks, there is a small delay from the time the and low for at least 2TOSC (and a small RC delay of external clock edge occurs to the time the Timer0 20ns). Refer to the electrical specification of the module is actually incremented. Figure6-4 shows the desired device. delay from the external clock edge to the timer incrementing. FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output (2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = – 4Tosc max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 25

PIC16C505 6.2 Prescaler RESET, the following instruction sequence (Example6-1) must be executed when changing the An 8-bit counter is available as a prescaler for the prescaler assignment from Timer0 to the WDT. Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (Section7.6). For simplicity, EXAMPLE 6-1: CHANGING PRESCALER this counter is being referred to as “prescaler” (TIMER0fi WDT) throughout this data sheet. Note that the prescaler 1.CLRWDT ;Clear WDT may be used by either the Timer0 module or the WDT, 2.CLRF TMR0 ;Clear TMR0 & Prescaler but not both. Thus, a prescaler assignment for the 3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7) Timer0 module means that there is no prescaler for 4.OPTION ; are required only if the WDT, and vice-versa. ; desired 5.CLRWDT ;PS<2:0> are 000 or 001 The PSA and PS<2:0> bits (OPTION<3:0>) determine 6.MOVLW '00xx1xxx’b ;Set Postscaler to prescaler assignment and prescale ratio. 7.OPTION ; desired WDT rate When assigned to the Timer0 module, all instructions To change prescaler from the WDT to the Timer0 writing to the TMR0 register (e.g., CLRF 1, module, use the sequence shown in Example6-2. MOVWF 1, BSF 1,x, etc.) will clear the prescaler. This sequence must be used even if the WDT is When assigned to WDT, a CLRWDT instruction will disabled. A CLRWDT instruction should be executed clear the prescaler along with the WDT. The prescaler before switching the prescaler. is neither readable nor writable. On a RESET, the prescaler contains all '0's. EXAMPLE 6-2: CHANGING PRESCALER 6.2.1 SWITCHING PRESCALER ASSIGNMENT (WDTfi TIMER0) CLRWDT ;Clear WDT and The prescaler assignment is fully under software ;prescaler control (i.e., it can be changed “on-the-fly” during MOVLW 'xxxx0xxx' ;Select TMR0, new program execution). To avoid an unintended device ;prescale value and ;clock source OPTION FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = Fosc/4) Data Bus 0 8 RC5P/Tin0CKI M 1 U M 1 X Sync U 2 TMR0 reg 0 X Cycles T0SE T0CS PSA 0 8-bit Prescaler M U 1 X Watchdog 8 Timer 8 - to - 1MUX PS<2:0> PSA 0 1 WDT Enable bit MUX PSA WDT Time-Out Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. DS40192C-page 26 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 7.0 SPECIAL FEATURES OF THE The PIC16C505 has a Watchdog Timer, which can be CPU shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using What sets a microcontroller apart from other HS, XT or LP selectable oscillator options, there is processors are special circuits to deal with the needs always an 18 ms (nominal) delay provided by the of real-time applications. The PIC16C505 Device Reset Timer (DRT), intended to keep the chip microcontroller has a host of such features intended to in reset until the crystal oscillator is stable. If using maximize system reliability, minimize cost through INTRC or EXTRC, there is an 18 ms delay only on VDD elimination of external components, provide power power-up. With this timer on-chip, most applications saving operating modes and offer code protection. need no external reset circuitry. These features are: The SLEEP mode is designed to offer a very low • Oscillator selection current power-down mode. The user can wake-up • Reset from SLEEP through a change on input pins or - Power-On Reset (POR) through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit - Device Reset Timer (DRT) the application, including an internal 4 MHz oscillator. - Wake-up from SLEEP on pin change The EXTRC oscillator option saves system cost while • Watchdog Timer (WDT) the LP crystal option saves power. A set of • SLEEP configuration bits are used to select various options. • Code protection 7.1 Configuration Bits • ID locations • In-circuit Serial Programming The PIC16C505 configuration word consists of 12 bits. • Clock Out Configuration bits can be programmed to select various device configurations. Three bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit, and one bit is the MCLR enable bit. Seven bits are for code protection (Register7-1). REGISTER 7-1: CONFIGURATION WORD FOR PIC16C505 CP CP CP CP CP CP MCLRE CP WDTE FOSC2 FOSC1 FOSC0 Register: CONFIG bit11 10 9 8 7 6 5 4 3 2 1 bit0 Address(2): 0FFFh bit 11-6, 4:CP Code Protection bits (1)(2)(3) bit 5: MCLRE: RB3/MCLR pin function select 1 = RB3/MCLR pin function is MCLR 0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 3: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0: FOSC<1:0>: Oscillator Selection bits 111 = external RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 110 = external RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 101 = internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 100 = internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 011 = invalid selection 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Note 1: 03FFh is always uncode protected on the PIC16C505. This location contains the MOVLWxx calibration instruction for the INTRC. 2: Refer to the PIC16C505 Programming Specifications to determine how to access the con- figuration word. This register is not user addressable during device operation. 3: All code protect bits must be written to the same value. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 27

PIC16C505 7.2 Oscillator Configurations TABLE 7-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS 7.2.1 OSCILLATOR TYPES - PIC16C505 The PIC16C505 can be operated in four different Osc Resonator Cap. Range Cap. Range oscillator modes. The user can program three Type Freq C1 C2 configuration bits (FOSC<2:0>) to select one of these XT 4.0 MHz 30 pF 30 pF four modes: HS 16 MHz 10-47 pF 10-47 pF • LP: Low Power Crystal These values are for design guidance only. Since • XT: Crystal/Resonator each resonator has its own characteristics, the user • HS: High Speed Crystal/Resonator should consult the resonator manufacturer for appropriate values of external components. • INTRC: Internal 4 MHz Oscillator • EXTRC: External Resistor/Capacitor TABLE 7-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - 7.2.2 CRYSTAL OSCILLATOR / CERAMIC PIC16C505 RESONATORS Osc Resonator Cap.Range Cap. Range In HS, XT or LP modes, a crystal or ceramic resonator Type Freq C1 C2 is connected to the RB5/OSC1/CLKIN and RB4/ OSC2/CLKOUT pins to establish oscillation LP 32 kHz(1) 15 pF 15 pF (Figure7-1). The PIC16C505 oscillator design XT 200 kHz 47-68 pF 47-68 pF requires the use of a parallel cut crystal. Use of a 1 MHz 15 pF 15 pF series cut crystal may give a frequency out of the 4 MHz 15 pF 15 pF crystal manufacturers specifications. When in HS, XT HS 20 MHz 15-47 pF 15-47 pF or LP modes, the device can have an external clock Note1: For VDD > 4.5V, C1 = C2 » 30 pF is source drive the RB5/OSC1/CLKIN pin (Figure7-2). recommended. These values are for design guidance only. Rs may FIGURE 7-1: CRYSTAL OPERATION (OR be required to avoid overdriving crystals with low CERAMIC RESONATOR) drive level specification. Since each crystal has its (HS, XT OR LP OSC own characteristics, the user should consult the crys- CONFIGURATION) tal manufacturer for appropriate values of external components. C1(1) OSC1 PIC16C505 SLEEP XTAL RF(3) To internal logic OSC2 RS(2) C2(1) Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF approx. value = 10 MW . FIGURE 7-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock from OSC1 ext. system PIC16C505 Open OSC2 DS40192C-page 28 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 7.2.3 EXTERNAL CRYSTAL OSCILLATOR 7.2.4 EXTERNAL RC OSCILLATOR CIRCUIT For timing insensitive applications, the RC device Either a prepackaged oscillator or a simple oscillator option offers additional cost savings. The RC oscillator circuit with TTL gates can be used as an external frequency is a function of the supply voltage, the crystal oscillator circuit. Prepackaged oscillators resistor (Rext) and capacitor (Cext) values, and the provide a wide operating range and better stability. A operating temperature. In addition to this, the oscillator well-designed crystal oscillator will provide good frequency will vary from unit to unit due to normal performance with TTL gates. Two types of crystal process parameter variation. Furthermore, the oscillator circuits can be used: one with parallel difference in lead frame capacitance between package resonance, or one with series resonance. types will also affect the oscillation frequency, especially for low Cext values. The user also needs to Figure7-3 shows implementation of a parallel take into account variation due to tolerance of external resonant oscillator circuit. The circuit is designed to R and C components used. use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift Figure7-5 shows how the R/C combination is that a parallel oscillator requires. The 4.7 kW resistor connected to the PIC16C505. For Rext values below provides the negative feedback for stability. The 10kW 2.2kW , the oscillator operation may become unstable, potentiometers bias the 74AS04 in the linear region. or stop completely. For very high Rext values This circuit could be used for external oscillator (e.g.,1MW ) the oscillator becomes sensitive to noise, designs. humidity and leakage. Thus, we recommend keeping Rext between 3kW and 100kW . FIGURE 7-3: EXTERNAL PARALLEL Although the oscillator will operate with no external RESONANT CRYSTAL capacitor (Cext = 0 pF), we recommend using values OSCILLATOR CIRCUIT above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency +5V can vary dramatically due to changes in external To Other Devices capacitances, such as PCB trace capacitance or 10k package lead frame capacitance. 4.7k 74AS04 PIC16C505 The Electrical Specifications section shows RC 74AS04 CLKIN frequency variation from part to part due to normal process variation. The variation is larger for larger values of R (since leakage current variation will affect 10k RC frequency more for large R) and for smaller values XTAL of C (since variation of input capacitance will affect RC frequency more). 10k Also, see the Electrical Specifications section for 20 pF 20 pF variation of oscillator frequency due to VDD for given Rext/Cext values, as well as frequency variation due to operating temperature for given R, C and VDD values. Figure7-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental FIGURE 7-5: EXTERNAL RC OSCILLATOR frequency of the crystal. The inverter performs a 180- MODE degree phase shift in a series resonant oscillator circuit. The 330W resistors provide the negative VDD feedback to bias the inverters in their linear region. Rext Internal FIGURE 7-4: EXTERNAL SERIES OSC1 clock RESONANT CRYSTAL OSCILLATOR CIRCUIT N Cext PIC16C505 To Other 330 330 Devices VSS 74AS04 74AS04 74AS04 PIC16C505 FOSC/4 OSC2/CLKOUT CLKIN 0.1 mF XTAL (cid:211) 1999 Microchip Technology Inc. DS40192C-page 29

PIC16C505 7.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nom- inal) system clock at VDD = 5V and 25°C, see Electrical Specifications section for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the last address of memory, which contains the calibra- tion value for the internal RC oscillator. This location is always protected, regardless of the code protect set- tings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the reset vector. This will load the W register with the calibration value upon reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be repro- grammed correctly later. For the PIC16C505, only bits <7:2> of OSCCAL are implemented. 7.3 RESET The device differentiates between various kinds of reset: a) Power on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WDT time-out reset during normal operation e) WDT time-out reset during SLEEP f) Wake-up from SLEEP on pin change Some registers are not reset in any way, they are unknown on POR and unchanged in any other reset. Most other registers are reset to “reset state” on power- on reset (POR), MCLR, WDT or wake-up on pin change reset during normal operation. They are not affected by a WDT reset during SLEEP or MCLR reset during SLEEP, since these resets are viewed as resumption of normal operation. The exceptions to this are TO, PD and RBWUF bits. They are set or cleared differently in different reset situations. These bits are used in software to determine the nature of reset. See Table7-3 for a full description of reset states of all registers. DS40192C-page 30 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 TABLE 7-3: RESET CONDITIONS FOR REGISTERS MCLR Reset Register Address Power-on Reset WDT time-out Wake-up on Pin Change W — qqqq qqqq(1) qqqq qqqq(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu(2,3) FSR 04h 110x xxxx 11uu uuuu OSCCAL 05h 1000 00-- uuuu uu-- PORTB 06h --xx xxxxx --uu uuuu PORTC 07h --xx xxxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRISB — --11 1111 --11 1111 TRISC — --11 1111 --11 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. Note 2: See Table7-7 for reset value for specific conditions. Note 3: If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0. TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h PCL Addr: 02h Power on reset 0001 1xxx 1111 1111 MCLR reset during normal operation 000u uuuu 1111 1111 MCLR reset during SLEEP 0001 0uuu 1111 1111 WDT reset during SLEEP 0000 0uuu 1111 1111 WDT reset normal operation 0000 uuuu 1111 1111 Wake-up from SLEEP on pin change 1001 0uuu 1111 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 31

PIC16C505 7.3.1 MCLR ENABLE The Power-On Reset circuit and the Device Reset Timer (Section7.5) circuit are closely related. On This configuration bit when unprogrammed (left in the power-up, the reset latch is set and the DRT is reset. ‘1’ state) enables the external MCLR function. When The DRT timer begins counting once it detects MCLR programmed, the MCLR function is tied to the internal to be high. After the time-out period, which is typically VDD, and the pin is assigned to be a I/O. See 18 ms, it will reset the reset latch and thus end the on- Figure7-6. chip reset signal. A power-up example where MCLR is held low is FIGURE 7-6: MCLR SELECT shown in Figure7-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will RBWU MCLRE actually come out of reset TDRT msec after MCLR goes high. In Figure7-9, the on-chip Power-On Reset feature is being used (MCLR and VDD are tied together or the WEAK pin is programmed to be RB3.). The VDD is stable PULL-UP INTERNAL MCLR before the start-up timer times out and there is no problem in getting a proper reset. However, RB3/MCLR/VPP Figure7-10 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR and VDD 7.4 Power-On Reset (POR) actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has The PIC16C505 family incorporates on-chip Power-On not reached the VDD (min) value and the chip may not Reset (POR) circuitry, which provides an internal chip function correctly. For such situations, we recommend reset for most power-up situations. that external RC circuits be used to achieve longer The on chip POR circuit holds the chip in reset until VDD POR delay times (Figure7-9). has reached a high enough level for proper operation. Note: When the device starts normal operation To take advantage of the internal POR, program the (exits the reset condition), device operating RB3/MCLR/VPP pin as MCLR and tie through a resistor parameters (voltage, frequency, tempera- to VDD or program the pin as RB3. An internal weak ture, etc.) must be met to ensure operation. pull-up resistor is implemented using a transistor. Refer If these conditions are not met, the device to Table10-1 for the pull-up resistor ranges. This will must be held in reset until the operating eliminate external RC components usually needed to conditions are met. create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. For additional information refer to Application Notes “Power-Up Considerations” - AN522 and “Power-up When the device starts normal operation (exits the Trouble Shooting” - AN607. reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating parameters are met. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure7-7. DS40192C-page 32 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-Up Detect VDD POR (Power-On Reset) Pin Change Wake-up on pin change SLEEP RB3/MCLR/VPP WDT Time-out MCLRE RESET S Q 8-bit Asynch On-Chip Ripple Counter DRT OSC (Start-Up Timer) R Q CHIP RESET FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET (cid:211) 1999 Microchip Technology Inc. DS40192C-page 33

PIC16C505 FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ‡ VDD min. 7.5 Device Reset Timer (DRT) 7.6 Watchdog Timer (WDT) In the PIC16C505, the DRT runs any time the device is The Watchdog Timer (WDT) is a free running on-chip powered up. DRT runs from RESET and varies based RC oscillator, which does not require any external on oscillator selection and reset type (see Table7-5). components. This RC oscillator is separate from the external RC oscillator of the RB5/OSC1/CLKIN pin The DRT operates on an internal RC oscillator. The and the internal 4 MHz oscillator. That means that the processor is kept in RESET as long as the DRT is WDT will run even if the main processor clock has active. The DRT delay allows VDD to rise above VDD been stopped, for example, by execution of a SLEEP min. and for the oscillator to stabilize. instruction. During normal operation or SLEEP, a WDT Oscillator circuits based on crystals or ceramic reset or wake-up reset generates a device RESET. resonators require a certain time after power-up to The TO bit (STATUS<4>) will be cleared upon a establish a stable oscillation. The on-chip DRT keeps Watchdog Timer reset. the device in a RESET condition for approximately 18 ms after MCLR has reached a logic high (VIHMCLR) The WDT can be permanently disabled by level. Thus, programming RB3/MCLR/VPP as MCLR programming the configuration bit WDTE as a ’0’ and using an external RC network connected to the (Section7.1). Refer to the PIC16C505 Programming MCLR input is not required in most cases, allowing for Specifications to determine how to access the savings in cost-sensitive and/or space restricted configuration word. applications, as well as allowing the use of the RB3/ TABLE 7-5: DRT (DEVICE RESET TIMER MCLR/VPP pin as a general purpose input. PERIOD) The Device Reset time delay will vary from chip to chip due to VDD, temperature and process variation. See Oscillator POR Reset Subsequent AC parameters for details. Configuration Resets The DRT will also be triggered upon a Watchdog IntRC & 18 ms (typical) 300 µs Timer time-out. This is particularly important for ExtRC (typical) applications using the WDT to wake from SLEEP HS, XT & LP 18 ms (typical) 18 ms (typical) mode automatically. Reset sources are POR, MCLR, WDT time-out and Wake-up on pin change. (See Section 7.9.2, Notes 1, 2, and 3, page 37.) DS40192C-page 34 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 7.6.1 WDT PERIOD 7.6.2 WDT PROGRAMMING CONSIDERATIONS The WDT has a nominal time-out period of 18 ms, The CLRWDT instruction clears the WDT and the (with no prescaler). If a longer time-out period is postscaler, if assigned to the WDT, and prevents it desired, a prescaler with a division ratio of up to 1:128 from timing out and generating a device RESET. can be assigned to the WDT (under software control) The SLEEP instruction resets the WDT and the by writing to the OPTION register. Thus, a time-out postscaler, if assigned to the WDT. This gives the period of a nominal 2.3 seconds can be realized. maximum SLEEP time before a WDT wake-up reset. These periods vary with temperature, VDD and part-to- part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs. FIGURE 7-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure6-5) 0 Watchdog 1 M PPoosststsccaalelerr U Timer X 8 - to - 1 MUX PS<2:0> WDT Enable PSA Configuration Bit To Timer0 (Figure6-4) 0 1 MUX PSA Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. WDT Time-out TABLE 7-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Power-On All Other Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Resets N/A OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as '0', u = unchanged. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 35

PIC16C505 7.7 Time-Out Sequence, Power Down, FIGURE 7-13: BROWN-OUT PROTECTION and Wake-up from SLEEP Status Bits CIRCUIT 2 (TO/PD/RBWUF) VDD The TO, PD, and RBWUF bits in the STATUS register VDD can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or R1 PIC16C505 Watchdog Timer (WDT) reset. Q1MCLR(1) TABLE 7-7: TO/PD/RBWUF STATUS R2 40k* AFTER RESET RBWUF TO PD RESET caused by 0 0 0 WDT wake-up from SLEEP 0 0 u WDT time-out (not from This brown-out circuit is less expensive, although SLEEP) less accurate. Transistor Q1 turns off when VDD 0 1 0 MCLR wake-up from is below a certain level such that: SLEEP R1 0 1 1 Power-up VDD • = 0.7V R1 + R2 0 u u MCLR not during SLEEP 1 1 0 Wake-up from SLEEP on Note 1: Pin must be confirmed as MCLR. pin change Legend: u = unchanged FIGURE 7-14: BROWN-OUT PROTECTION Note 1: The TO, PD, and RBWUF bits maintain their status (u) until a reset occurs. A low-pulse on the CIRCUIT 3 MCLR input does not change the TO, PD, and RBWUF status bits. VDD 7.8 Reset on Brown-Out MCP809 bypass VDD VSS capacitor A brown-out is a condition where device power (VDD) VDD dips below its minimum value, but not to zero, and then RST recovers. The device should be reset in the event of a MCLR brown-out. PIC12C5XX To reset PIC16C505 devices when a brown-out occurs, external brown-out protection circuits may be This brown-out protection circuit employs Microchip built, as shown in Figure7-12 and Figure7-13. Technology’s MCP809 microcontroller supervisor. There are 7 different trip point selections to FIGURE 7-12: BROWN-OUT PROTECTION accommodate 5V to 3V systems. CIRCUIT 1 VDD VDD 33k PIC16C505 10k Q1 MCLR(1) 40k* This circuit will activate reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). Note 1: Pin must be confirmed as MCLR. DS40192C-page 36 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 7.9 Power-Down Mode (SLEEP) 7.10 Program Verification/Code Protection A device may be powered down (SLEEP) and later If the code protection bit has not been programmed, powered up (Wake-up from SLEEP). the on-chip program memory can be read out for verification purposes. 7.9.1 SLEEP The first 64 locations and the last location (OSCCAL) The Power-Down mode is entered by executing a can be read, regardless of the code protection bit SLEEP instruction. setting. If enabled, the Watchdog Timer will be cleared but 7.11 ID Locations keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is Four memory locations are designated as ID locations turned off. The I/O ports maintain the status they had where the user can store checksum or other code- before the SLEEP instruction was executed (driving identification numbers. These locations are not high, driving low or hi-impedance). accessible during normal execution, but are readable It should be noted that a RESET generated by a WDT and writable during program/verify. time-out does not drive the MCLR pin low. Use only the lower 4 bits of the ID locations and For lowest current consumption while powered down, always program the upper 8 bits as ’0’s. the T0CKI input should be at VDD or VSS and the RB3/ MCLR/VPP pin must be at a logic high level (VIHMC) if MCLR is enabled. 7.9.2 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. An external reset input on RB3/MCLR/VPP pin, when configured as MCLR. 2. A Watchdog Timer time-out reset (if WDT was enabled). 3. A change on input pin RB0, RB1, RB3 or RB4 when wake-up on change is enabled. These events cause a device reset. The TO, PD, and RBWUF bits can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The RBWUF bit indicates a change in state while in SLEEP at pins RB0, RB1, RB3 or RB4 (since the last file or bit operation on RB port). Caution: Right before entering SLEEP, read the input pins. When in SLEEP, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering SLEEP, a wake-up will occur immediately even if no pins change while in SLEEP mode. The WDT is cleared when the device wakes from sleep, regardless of the wake-up source. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 37

PIC16C505 7.12 In-Circuit Serial Programming FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING The PIC16C505 microcontrollers can be serially CONNECTION programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming To Normal voltage. This allows customers to manufacture boards Connections External with unprogrammed devices, and then program the Connector PIC16C505 microcontroller just before shipping the product. This Signals also allows the most recent firmware or a custom +5V VDD firmware to be programmed. 0V VSS The device is placed into a program/verify mode by VPP MCLR/VPP holding the RB1 and RB0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming CLK RB1 specification). RB1 becomes the programming clock and RB0 becomes the programming data. Both RB1 Data I/O RB0 and RB0 are Schmitt Trigger inputs in this mode. After reset, a 6-bit command is then supplied to the VDD device. Depending on the command, 14 bits of program data are then supplied to or from the device, depending To Normal if the command was a load or a read. For complete Connections details of serial programming, please refer to the PIC16C505 Programming Specifications. A typical in-circuit serial programming connection is shown in Figure7-15. DS40192C-page 38 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 8.0 INSTRUCTION SET SUMMARY All instructions are executed within a single instruction cycle, unless a conditional test is true or the program Each PIC16C505 instruction is a 12-bit word divided counter is changed as a result of an instruction. In this into an OPCODE, which specifies the instruction type, case, the execution takes two instruction cycles. One and one or more operands which further specify the instruction cycle consists of four oscillator periods. operation of the instruction. The PIC16C505 Thus, for an oscillator frequency of 4 MHz, the normal instruction set summary in Table8-2 groups the instruction execution time is 1 m s. If a conditional test is instructions into byte-oriented, bit-oriented, and literal true or the program counter is changed as a result of and control operations. Table8-1 shows the opcode an instruction, the instruction execution time is 2 m s. field descriptions. Figure8-1 shows the three general formats that the For byte-oriented instructions, ’f’ represents a file instructions can have. All examples in the figure use the register designator and ’d’ represents a destination following format to represent a hexadecimal number: designator. The file register designator is used to specify which one of the 32 file registers is to be used 0xhhh by the instruction. where ’h’ signifies a hexadecimal digit. The destination designator specifies where the result of the operation is to be placed. If ’d’ is ’0’, the result is FIGURE 8-1: GENERAL FORMAT FOR placed in the W register. If ’d’ is ’1’, the result is placed INSTRUCTIONS in the file register specified in the instruction. Byte-oriented file register operations For bit-oriented instructions, ’b’ represents a bit field 11 6 5 4 0 designator which selects the number of the bit affected OPCODE d f (FILE #) by the operation, while ’f’ represents the number of the file in which the bit is located. d = 0 for destination W d = 1 for destination f For literal and control operations, ’k’ represents an f = 5-bit file register address 8or 9-bit constant or literal value. Bit-oriented file register operations TABLE 8-1: OPCODE FIELD 11 8 7 5 4 0 DESCRIPTIONS OPCODE b (BIT #) f (FILE #) Field Description b = 3-bit bit address f = 5-bit file register address f Register file address (0x00 to 0x7F) W Working register (accumulator) Literal and control operations (except GOTO) b Bit address within an 8-bit file register 11 8 7 0 k Literal field, constant data or label OPCODE k (literal) Don’t care location (= 0 or 1) k = 8-bit immediate value The assembler will generate code with x = 0. It is x the recommended form of use for compatibility Literal and control operations - GOTO instruction with all Microchip software tools. 11 9 8 0 Destination select; OPCODE k (literal) d = 0 (store result in W) d d = 1 (store result in file register ’f’) k = 9-bit immediate value Default is d = 1 label Label name TOS Top of Stack PC Program Counter WDT Watchdog Timer Counter TO Time-Out bit PD Power-Down bit Destination, either the W register or the specified dest register file location [ ] Options ( ) Contents fi Assigned to < > Register bit field ˛ In the set of italics User defined term (font is courier) (cid:211) 1999 Microchip Technology Inc. DS40192C-page 39

PIC16C505 TABLE 8-2: INSTRUCTION SET SUMMARY 12-Bit Opcode Mnemonic, Status Operands Description Cycles MSb LSb Affected Notes ADDWF f,d Add W and f 1 0001 11df ffff C,DC,Z 1,2,4 ANDWF f,d AND W with f 1 0001 01df ffff Z 2,4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW – Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2,4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2,4 INCF f, d Increment f 1 0010 10df ffff Z 2,4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2,4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2,4 MOVF f, d Move f 1 0010 00df ffff Z 2,4 MOVWF f Move W to f 1 0000 001f ffff None 1,4 NOP – No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2,4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2,4 SUBWF f, d Subtract W from f 1 0000 10df ffff C,DC,Z 1,2,4 SWAPF f, d Swap f 1 0011 10df ffff None 2,4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2,4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2,4 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1 (2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call subroutine 2 1001 kkkk kkkk None 1 CLRWDT k Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION – Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk None SLEEP – Go into standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z Note1: The 9th bit of the program counter will be forced to a ’0’ by any instruction that writes to the PC except for GOTO. (Section4.6) 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ’0’. 3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of PORTB. A ’1’ forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS40192C-page 40 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 ADDWF Add W and f ANDWF AND W with f Syntax: [ label ] ADDWF f,d Syntax: [ label ] ANDWF f,d Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 d ˛ [0,1] d ˛ [0,1] Operation: (W) + (f) fi (dest) Operation: (W) .AND. (f) fi (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 0001 11df ffff Encoding: 0001 01df ffff Description: Add the contents of the W register Description: The contents of the W register are and register ’f’. If ’d’ is 0, the result AND’ed with register 'f'. If 'd' is 0, the is stored in the W register. If ’d’ is result is stored in the W register. If ’1’, the result is stored back in reg- 'd' is '1', the result is stored back in ister ’f’. register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: ADDWF FSR, 0 Example: ANDWF FSR, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 FSR = 0xC2 FSR = 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 FSR = 0xC2 FSR = 0x02 ANDLW And literal with W BCF Bit Clear f Syntax: [ label ] ANDLW k Syntax: [ label ] BCF f,b Operands: 0 £ k £ 255 Operands: 0 £ f £ 31 Operation: (W).AND. (k) fi (W) 0 £ b £ 7 Operation: 0 fi (f<b>) Status Affected: Z Status Affected: None Encoding: 1110 kkkk kkkk Encoding: 0100 bbbf ffff Description: The contents of the W register are AND’ed with the eight-bit literal 'k'. Description: Bit 'b' in register 'f' is cleared. The result is placed in the W regis- Words: 1 ter. Cycles: 1 Words: 1 Example: BCF FLAG_REG, 7 Cycles: 1 Before Instruction Example: ANDLW 0x5F FLAG_REG = 0xC7 Before Instruction After Instruction W = 0xA3 FLAG_REG = 0x47 After Instruction W = 0x03 (cid:211) 1999 Microchip Technology Inc. DS40192C-page 41

PIC16C505 BSF Bit Set f BTFSS Bit Test f, Skip if Set Syntax: [ label ] BSF f,b Syntax: [ label ] BTFSS f,b Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 0 £ b £ 7 0 £ b < 7 Operation: 1 fi (f<b>) Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 0101 bbbf ffff Encoding: 0111 bbbf ffff Description: Bit ’b’ in register ’f’ is set. Description: If bit ’b’ in register ’f’ is ’1’, then the next instruction is skipped. Words: 1 If bit ’b’ is ’1’, then the next instruc- Cycles: 1 tion fetched during the current Example: BSF FLAG_REG, 7 instruction execution, is discarded Before Instruction and a NOP is executed instead, making this a 2 cycle instruction. FLAG_REG = 0x0A After Instruction Words: 1 FLAG_REG = 0x8A Cycles: 1(2) Example: HERE BTFSS FLAG,1 FALSE GOTO PROCESS_CODE BTFSC Bit Test f, Skip if Clear TRUE • • Syntax: [ label ] BTFSC f,b • Operands: 0 £ f £ 31 0 £ b £ 7 Before Instruction PC = address (HERE) Operation: skip if (f<b>) = 0 After Instruction Status Affected: None If FLAG<1> = 0, Encoding: 0110 bbbf ffff PC = address (FALSE); if FLAG<1> = 1, Description: If bit ’b’ in register ’f’ is 0, then the PC = address (TRUE) next instruction is skipped. If bit ’b’ is 0, then the next instruc- tion fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2 cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address (HERE) After Instruction if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address(FALSE) DS40192C-page 42 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 CALL Subroutine Call CLRW Clear W Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 £ k £ 255 Operands: None Operation: (PC) + 1fi Top of Stack; Operation: 00h fi (W); k fi PC<7:0>; 1 fi Z (STATUS<6:5>) fi PC<10:9>; Status Affected: Z 0 fi PC<8> Encoding: 0000 0100 0000 Status Affected: None Description: The W register is cleared. Zero bit Encoding: 1001 kkkk kkkk (Z) is set. Description: Subroutine call. First, return Words: 1 address (PC+1) is pushed onto the stack. The eight bit immediate Cycles: 1 address is loaded into PC bits Example: CLRW <7:0>. The upper bits PC<10:9> Before Instruction are loaded from STATUS<6:5>, W = 0x5A PC<8> is cleared. CALL is a two cycle instruction. After Instruction W = 0x00 Words: 1 Z = 1 Cycles: 2 Example: HERE CALL THERE CLRWDT Clear Watchdog Timer Before Instruction Syntax: [ label ] CLRWDT PC = address (HERE) After Instruction Operands: None PC = address (THERE) Operation: 00h fi WDT; TOS= address (HERE + 1) 0 fi WDT prescaler (if assigned); 1 fi TO; 1 fi PD CLRF Clear f Status Affected: TO, PD Syntax: [ label ] CLRF f Encoding: 0000 0000 0100 Operands: 0 £ f £ 31 Description: The CLRWDT instruction resets the Operation: 00h fi (f); WDT. It also resets the prescaler, if 1 fi Z the prescaler is assigned to the WDT and not Timer0. Status bits Status Affected: Z TO and PD are set. Encoding: 0000 011f ffff Words: 1 Description: The contents of register ’f’ are cleared and the Z bit is set. Cycles: 1 Words: 1 Example: CLRWDT Cycles: 1 Before Instruction WDT counter = ? Example: CLRF FLAG_REG After Instruction Before Instruction WDT counter = 0x00 FLAG_REG = 0x5A WDT prescale = 0 After Instruction TO = 1 FLAG_REG = 0x00 PD = 1 Z = 1 (cid:211) 1999 Microchip Technology Inc. DS40192C-page 43

PIC16C505 COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 d ˛ [0,1] d ˛ [0,1] Operation: (f) fi (dest) Operation: (f) – 1 fi d; skip if result = 0 Status Affected: Z Status Affected: None Encoding: 0010 01df ffff Encoding: 0010 11df ffff Description: The contents of register ’f’ are Description: The contents of register 'f' are dec- complemented. If ’d’ is 0, the result remented. If 'd' is 0, the result is is stored in the W register. If ’d’ is placed in the W register. If 'd' is 1, 1, the result is stored back in regis- the result is placed back in register ter ’f’. 'f'. Words: 1 If the result is 0, the next instruc- tion, which is already fetched, is Cycles: 1 discarded and a NOP is executed Example: COMF REG1,0 instead making it a two cycle Before Instruction instruction. REG1 = 0x13 Words: 1 After Instruction Cycles: 1(2) REG1 = 0x13 Example: HERE DECFSZ CNT, 1 W = 0xEC GOTO LOOP CONTINUE • • DECF Decrement f • Syntax: [ label ] DECF f,d Before Instruction Operands: 0 £ f £ 31 PC = address (HERE) d ˛ [0,1] After Instruction Operation: (f) – 1 fi (dest) CNT = CNT - 1; if CNT = 0, Status Affected: Z PC = address (CONTINUE); if CNT „ 0, Encoding: 0000 11df ffff PC = address (HERE+1) Description: Decrement register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in GOTO Unconditional Branch register 'f'. Syntax: [ label ] GOTO k Words: 1 Operands: 0 £ k £ 511 Cycles: 1 Operation: k fi PC<8:0>; Example: DECF CNT, 1 STATUS<6:5> fi PC<10:9> Before Instruction Status Affected: None CNT = 0x01 Encoding: 101k kkkk kkkk Z = 0 After Instruction Description: GOTO is an unconditional branch. CNT = 0x00 The 9-bit immediate value is Z = 1 loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a two cycle instruction. Words: 1 Cycles: 2 Example: GOTO THERE After Instruction PC = address (THERE) DS40192C-page 44 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 INCF Increment f INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCF f,d Syntax: [ label ] INCFSZ f,d Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 d ˛ [0,1] d ˛ [0,1] Operation: (f) + 1 fi (dest) Operation: (f) + 1 fi (dest), skip if result = 0 Status Affected: Z Status Affected: None Encoding: 0010 10df ffff Encoding: 0011 11df ffff Description: The contents of register ’f’ are Description: The contents of register ’f’ are incremented. If ’d’ is 0, the result is incremented. If ’d’ is 0, the result is placed in the W register. If ’d’ is 1, placed in the W register. If ’d’ is 1, the result is placed back in register the result is placed back in register ’f’. ’f’. Words: 1 If the result is 0, then the next instruction, which is already Cycles: 1 fetched, is discarded and a NOP is Example: INCF CNT, 1 executed instead making it a two Before Instruction cycle instruction. CNT = 0xFF Words: 1 Z = 0 Cycles: 1(2) After Instruction Example: HERE INCFSZ CNT, 1 CNT = 0x00 GOTO LOOP Z = 1 CONTINUE • • • Before Instruction PC = address (HERE) After Instruction CNT = CNT + 1; if CNT = 0, PC = address (CONTINUE); if CNT „ 0, PC = address (HERE +1) (cid:211) 1999 Microchip Technology Inc. DS40192C-page 45

PIC16C505 IORLW Inclusive OR literal with W MOVF Move f Syntax: [ label ] IORLW k Syntax: [ label ] MOVF f,d Operands: 0 £ k £ 255 Operands: 0 £ f £ 31 Operation: (W) .OR. (k) fi (W) d ˛ [0,1] Operation: (f) fi (dest) Status Affected: Z Status Affected: Z Encoding: 1101 kkkk kkkk Encoding: 0010 00df ffff Description: The contents of the W register are OR’ed with the eight bit literal 'k'. Description: The contents of register 'f' are The result is placed in the W regis- moved to destination 'd'. If 'd' is 0, ter. destination is the W register. If 'd' is 1, the destination is file register Words: 1 'f'. 'd' = 1 is useful as a test of a file Cycles: 1 register since status flag Z is Example: IORLW 0x35 affected. Before Instruction Words: 1 W = 0x9A Cycles: 1 After Instruction Example: MOVF FSR, 0 W = 0xBF Z = 0 After Instruction W = value in FSR register IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d MOVLW Move Literal to W Operands: 0 £ f £ 31 Syntax: [ label ] MOVLW k d ˛ [0,1] Operands: 0 £ k £ 255 Operation: (W).OR. (f) fi (dest) Operation: k fi (W) Status Affected: Z Status Affected: None Encoding: 0001 00df ffff Encoding: 1100 kkkk kkkk Description: Inclusive OR the W register with register 'f'. If 'd' is 0, the result is Description: The eight bit literal 'k' is loaded into placed in the W register. If 'd' is 1, the W register. The don’t cares the result is placed back in register will assembled as 0s. 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: MOVLW 0x5A Example: IORWF RESULT, 0 After Instruction Before Instruction W = 0x5A RESULT = 0x13 W = 0x91 After Instruction RESULT = 0x13 W = 0x93 Z = 0 DS40192C-page 46 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 MOVWF Move W to f OPTION Load OPTION Register Syntax: [ label ] MOVWF f Syntax: [ label ] OPTION Operands: 0 £ f £ 31 Operands: None Operation: (W) fi (f) Operation: (W) fi OPTION Status Affected: None Status Affected: None Encoding: 0000 0000 0010 Encoding: 0000 001f ffff Description: The content of the W register is Description: Move data from the W register to loaded into the OPTION register. register ’f’. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example OPTION Example: MOVWF TEMP_REG Before Instruction Before Instruction W = 0x07 TEMP_REG = 0xFF After Instruction W = 0x4F OPTION = 0x07 After Instruction TEMP_REG = 0x4F W = 0x4F RETLW Return with Literal in W Syntax: [ label ] RETLW k NOP No Operation Operands: 0 £ k £ 255 Syntax: [ label ] NOP Operation: k fi (W); TOS fi PC Operands: None Status Affected: None Operation: No operation Encoding: 1000 kkkk kkkk Status Affected: None Description: The W register is loaded with the Encoding: 0000 0000 0000 eight bit literal ’k’. The program Description: No operation. counter is loaded from the top of Words: 1 the stack (the return address). This is a two cycle instruction. Cycles: 1 Words: 1 Example: NOP Cycles: 2 Example: CALL TABLE ;W contains ;table offset ;value. • ;W now has table • ;value. • TABLE ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 (cid:211) 1999 Microchip Technology Inc. DS40192C-page 47

PIC16C505 RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] RLF f,d Syntax: [ label ] RRF f,d Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 d ˛ [0,1] d ˛ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: 0011 01df ffff Encoding: 0011 00df ffff Description: The contents of register ’f’ are Description: The contents of register ’f’ are rotated one bit to the left through rotated one bit to the right through the Carry Flag. If ’d’ is 0, the result the Carry Flag. If ’d’ is 0, the result is placed in the W register. If ’d’ is is placed in the W register. If ’d’ is 1, the result is stored back in regis- 1, the result is placed back in reg- ter ’f’. ister ’f’. C register ’f’ C register ’f’ Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: RLF REG1,0 Example: RRF REG1,0 Before Instruction Before Instruction REG1 = 1110 0110 REG1 = 1110 0110 C = 0 C = 0 After Instruction After Instruction REG1 = 1110 0110 REG1 = 1110 0110 W = 1100 1100 W = 0111 0011 C = 1 C = 0 DS40192C-page 48 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 SLEEP Enter SLEEP Mode SUBWF Subtract W from f Syntax: [label] SLEEP Syntax: [label] SUBWF f,d Operands: None Operands: 0 £ f £ 31 d ˛ [0,1] Operation: 00h fi WDT; 0 fi WDT prescaler; Operation: (f) – (W) fi( dest) 1 fi TO; Status Affected: C, DC, Z 0 fi PD Encoding: 0000 10df ffff Status Affected: TO, PD, RBWUF Description: Subtract (2’s complement method) Encoding: 0000 0000 0011 the W register from register 'f'. If 'd' Description: Time-out status bit (TO) is set. The is 0, the result is stored in the W power down status bit (PD) is register. If 'd' is 1, the result is cleared. stored back in register 'f'. RBWUF is unaffected. Words: 1 The WDT and its prescaler are Cycles: 1 cleared. Example 1: SUBWF REG1, 1 The processor is put into SLEEP mode with the oscillator stopped. Before Instruction See section on SLEEP for more REG1 = 3 details. W = 2 C = ? Words: 1 After Instruction Cycles: 1 REG1 = 1 Example: SLEEP W = 2 C = 1 ; result is positive Example 2: Before Instruction REG1 = 2 W = 2 C = ? After Instruction REG1 = 0 W = 2 C = 1 ; result is zero Example 3: Before Instruction REG1 = 1 W = 2 C = ? After Instruction REG1 = FF W = 2 C = 0 ; result is negative (cid:211) 1999 Microchip Technology Inc. DS40192C-page 49

PIC16C505 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [label] XORLW k Operands: 0 £ f £ 31 Operands: 0 £ k £ 255 d ˛ [0,1] Operation: (W) .XOR. k fi( W) Operation: (f<3:0>) fi (dest<7:4>); Status Affected: Z (f<7:4>) fi (dest<3:0>) Encoding: 1111 kkkk kkkk Status Affected: None Description: The contents of the W register are Encoding: 0011 10df ffff XOR’ed with the eight bit literal 'k'. Description: The upper and lower nibbles of The result is placed in the W regis- register ’f’ are exchanged. If ’d’ is ter. 0, the result is placed in W regis- Words: 1 ter. If ’d’ is 1, the result is placed in register ’f’. Cycles: 1 Words: 1 Example: XORLW 0xAF Cycles: 1 Before Instruction W = 0xB5 Example SWAPF REG1, 0 After Instruction Before Instruction W = 0x1A REG1 = 0xA5 After Instruction REG1 = 0xA5 XORWF Exclusive OR W with f W = 0X5A Syntax: [ label ] XORWF f,d Operands: 0 £ f £ 31 TRIS Load TRIS Register d ˛ [0,1] Syntax: [ label ] TRIS f Operation: (W) .XOR. (f) fi( dest) Operands: f = 6 Status Affected: Z Operation: (W) fi TRIS register f Encoding: 0001 10df ffff Status Affected: None Description: Exclusive OR the contents of the Encoding: 0000 0000 0fff W register with register 'f'. If 'd' is 0, Description: TRIS register ’f’ (f = 6 or 7) is the result is stored in the W regis- loaded with the contents of the W ter. If 'd' is 1, the result is stored register back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example TRIS PORTB Example XORWF REG,1 Before Instruction Before Instruction W = 0XA5 REG = 0xAF After Instruction W = 0xB5 TRIS = 0XA5 After Instruction REG = 0x1A W = 0xB5 DS40192C-page 50 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 9.0 DEVELOPMENT SUPPORT MPLAB allows you to: The PICmicro® microcontrollers are supported with a • Edit your source files (either assembly or ‘C’) full range of hardware and software development tools: • One touch assemble (or compile) and download to PICmicro tools (automatically updates all • Integrated Development Environment project information) - MPLAB™ IDE Software • Debug using: • Assemblers/Compilers/Linkers - source files - MPASM Assembler - absolute listing file - MPLAB-C17 and MPLAB-C18 C Compilers - object code - MPLINK/MPLIB Linker/Librarian The ability to use MPLAB with Microchip’s simulator, • Simulators MPLAB-SIM, allows a consistent platform and the abil- - MPLAB-SIM Software Simulator ity to easily switch from the cost-effective simulator to • Emulators the full featured emulator with minimal retraining. - MPLAB-ICE Real-Time In-Circuit Emulator - PICMASTER®/PICMASTER-CE In-Circuit 9.2 MPASM Assembler Emulator MPASM is a full featured universal macro assembler for - ICEPIC™ all PICmicro MCU’s. It can produce absolute code • In-Circuit Debugger directly in the form of HEX files for device program- - MPLAB-ICD for PIC16F877 mers, or it can generate relocatable objects for MPLINK. • Device Programmers - PRO MATE(cid:226) II Universal Programmer MPASM has a command line interface and a Windows (cid:226) shell and can be used as a standalone application on a - PICSTART Plus Entry-Level Prototype Windows 3.x or greater system. MPASM generates Programmer relocatable object files, Intel standard HEX files, MAP • Low-Cost Demonstration Boards files to detail memory usage and symbol reference, an - SIMICE absolute LST file which contains source lines and gen- - PICDEM-1 erated machine code, and a COD file for MPLAB - PICDEM-2 debugging. - PICDEM-3 MPASM features include: - PICDEM-17 • MPASM and MPLINK are integrated into MPLAB (cid:226) - SEEVAL projects. (cid:226) - KEELOQ • MPASM allows user defined macros to be created for streamlined assembly. 9.1 MPLAB Integrated Development • MPASM allows conditional assembly for multi pur- Environment Software pose source files. • The MPLAB IDE software brings an ease of soft- • MPASM directives allow complete control over the ware development previously unseen in the 8-bit assembly process. (cid:226) microcontroller market. MPLAB is a Windows - 9.3 MPLAB-C17 and MPLAB-C18 based application which contains: C Compilers • Multiple functionality - editor The MPLAB-C17 and MPLAB-C18 Code Development - simulator Systems are complete ANSI ‘C’ compilers and inte- - programmer (sold separately) grated development environments for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrol- - emulator (sold separately) lers, respectively. These compilers provide powerful • A full featured editor integration capabilities and ease of use not found with • A project manager other compilers. • Customizable tool bar and key mapping For easier source level debugging, the compilers pro- • A status bar vide symbol information that is compatible with the • On-line help MPLAB IDE memory display. ª 1999 Microchip Technology Inc. DS40192C-page 51

PIC16C505 9.4 MPLINK/MPLIB Linker/Librarian Interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- MPLINK is a relocatable linker for MPASM and cessors. The universal architecture of the MPLAB-ICE MPLAB-C17 and MPLAB-C18. It can link relocatable allows expansion to support new PICmicro microcon- objects from assembly or C source files along with pre- trollers. compiled libraries using directives from a linker script. The MPLAB-ICE Emulator System has been designed MPLIB is a librarian for pre-compiled code to be used as a real-time emulation system with advanced fea- with MPLINK. When a routine from a library is called tures that are generally found on more expensive devel- from another source file, only the modules that contains opment tools. The PC platform and Microsoft® Windows that routine will be linked in with the application. This 3.x/95/98 environment were chosen to best make these allows large libraries to be used efficiently in many dif- features available to you, the end user. ferent applications. MPLIB manages the creation and MPLAB-ICE 2000 is a full-featured emulator system modification of library files. with enhanced trace, trigger, and data monitoring fea- MPLINK features include: tures. Both systems use the same processor modules • MPLINK works with MPASM and MPLAB-C17 and will operate across the full operating speed range and MPLAB-C18. of the PICmicro MCU. • MPLINK allows all memory areas to be defined as 9.7 PICMASTER/PICMASTER CE sections to provide link-time flexibility. MPLIB features include: The PICMASTER system from Microchip Technology is a full-featured, professional quality emulator system. • MPLIB makes linking easier because single librar- This flexible in-circuit emulator provides a high-quality, ies can be included instead of many smaller files. universal platform for emulating Microchip 8-bit • MPLIB helps keep code maintainable by grouping PICmicro microcontrollers (MCUs). PICMASTER sys- related modules together. tems are sold worldwide, with a CE compliant model • MPLIB commands allow libraries to be created available for European Union (EU) countries. and modules to be added, listed, replaced, deleted, or extracted. 9.8 ICEPIC 9.5 MPLAB-SIM Software Simulator ICEPIC is a low-cost in-circuit emulation solution for the Microchip Technology PIC16C5X, PIC16C6X, The MPLAB-SIM Software Simulator allows code PIC16C7X, and PIC16CXXX families of 8-bit one-time- development in a PC host environment by simulating programmable (OTP) microcontrollers. The modular the PICmicro series microcontrollers on an instruction system can support different subsets of PIC16C5X or level. On any given instruction, the data areas can be PIC16CXXX products through the use of examined or modified and stimuli can be applied from interchangeable personality modules or daughter a file or user-defined key press to any of the pins. The boards. The emulator is capable of emulating without execution can be performed in single step, execute until target application circuitry being present. break, or trace mode. 9.9 MPLAB-ICD In-Circuit Debugger MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPLAB-C18 and MPASM. The Soft- Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow- ware Simulator offers the flexibility to develop and erful, low-cost run-time development tool. This tool is debug code outside of the laboratory environment mak- based on the flash PIC16F877 and can be used to ing it an excellent multi-project software development develop for this and other PICmicro microcontrollers tool. from the PIC16CXXX family. MPLAB-ICD utilizes the In-Circuit Debugging capability built into the 9.6 MPLAB-ICE High Performance PIC16F87X. This feature, along with Microchip’s In-Cir- Universal In-Circuit Emulator with cuit Serial Programming protocol, offers cost-effective MPLAB IDE in-circuit flash programming and debugging from the graphical user interface of the MPLAB Integrated The MPLAB-ICE Universal In-Circuit Emulator is Development Environment. This enables a designer to intended to provide the product development engineer develop and debug source code by watching variables, with a complete microcontroller design tool set for single-stepping and setting break points. Running at PICmicro microcontrollers (MCUs). Software control of full speed enables testing hardware in real-time. The MPLAB-ICE is provided by the MPLAB Integrated MPLAB-ICD is also a programmer for the flash Development Environment (IDE), which allows editing, PIC16F87X family. “make” and download, and source debugging from a single environment. DS40192C-page 52 ª 1999 Microchip Technology Inc.

PIC16C505 9.10 PRO MATE II Universal Programmer the PICDEM-1 board, on a PROMATE II or PICSTART-Plus programmer, and easily test firm- The PRO MATE II Universal Programmer is a full-fea- ware. The user can also connect the PICDEM-1 tured programmer capable of operating in stand-alone board to the MPLAB-ICE emulator and download the mode as well as PC-hosted mode. PRO MATE II is CE firmware to the emulator for testing. Additional proto- compliant. type area is available for the user to build some addi- The PRO MATE II has programmable VDD and VPP tional hardware and connect it to the microcontroller supplies which allows it to verify programmed memory socket(s). Some of the features include an RS-232 at VDD min and VDD max for maximum reliability. It has interface, a potentiometer for simulated analog input, an LCD display for instructions and error messages, push-button switches and eight LEDs connected to keys to enter commands and a modular detachable PORTB. socket assembly to support various package types. In 9.14 PICDEM-2 Low-Cost PIC16CXX stand-alone mode the PRO MATE II can read, verify or Demonstration Board program PICmicro devices. It can also set code-protect bits in this mode. The PICDEM-2 is a simple demonstration board that 9.11 PICSTART Plus Entry Level supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the Development System necessary hardware and software is included to The PICSTART programmer is an easy-to-use, low- run the basic demonstration programs. The user cost prototype programmer. It connects to the PC via can program the sample microcontrollers provided one of the COM (RS-232) ports. MPLAB Integrated with the PICDEM-2 board, on a PRO MATE II pro- Development Environment software makes using the grammer or PICSTART-Plus, and easily test firmware. programmer simple and efficient. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype PICSTART Plus supports all PICmicro devices with up area has been provided to the user for adding addi- to 40 pins. Larger pin count devices such as the tional hardware and connecting it to the microcontroller PIC16C92X, and PIC17C76X may be supported with socket(s). Some of the features include a RS-232 inter- an adapter socket. PICSTART Plus is CE compliant. face, push-button switches, a potentiometer for simu- 9.12 SIMICE Entry-Level lated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connec- Hardware Simulator tion to an LCD module and a keypad. SIMICE is an entry-level hardware development sys- 9.15 PICDEM-3 Low-Cost PIC16CXXX tem designed to operate in a PC-based environment Demonstration Board with Microchip’s simulator MPLAB-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s The PICDEM-3 is a simple demonstration board that MPLAB Integrated Development Environment (IDE) supports the PIC16C923 and PIC16C924 in the PLCC software. Specifically, SIMICE provides hardware sim- package. It will also support future 44-pin PLCC ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and microcontrollers with a LCD Module. All the neces- PIC16C5X families of PICmicro 8-bit microcontrollers. sary hardware and software is included to run the SIMICE works in conjunction with MPLAB-SIM to pro- basic demonstration programs. The user can pro- vide non-real-time I/O port emulation. SIMICE enables gram the sample microcontrollers provided with a developer to run simulator code for driving the target the PICDEM-3 board, on a PRO MATE II program- system. In addition, the target system can provide input mer or PICSTART Plus with an adapter socket, and to the simulator code. This capability allows for simple easily test firmware. The MPLAB-ICE emulator may and interactive debugging without having to manually also be used with the PICDEM-3 board to test firm- generate MPLAB-SIM stimulus files. SIMICE is a valu- ware. Additional prototype area has been provided to able debugging tool for entry-level system develop- the user for adding hardware and connecting it to the ment. microcontroller socket(s). Some of the features include 9.13 PICDEM-1 Low-Cost PICmicro an RS-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and Demonstration Board separate headers for connection to an external LCD The PICDEM-1 is a simple board which demonstrates module and a keypad. Also provided on the PICDEM-3 the capabilities of several of Microchip’s microcontrol- board is an LCD panel, with 4 commons and 12 seg- lers. The microcontrollers supported are: PIC16C5X ments, that is capable of displaying time, temperature (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, and day of the week. The PICDEM-3 provides an addi- PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and tional RS-232 interface and Windows 3.1 software for PIC17C44. All necessary hardware and software is showing the demultiplexed LCD signals on a PC. A sim- included to run basic demo programs. The users can ple serial interface allows the user to construct a hard- program the sample microcontrollers provided with ware demultiplexer for the LCD signals. ª 1999 Microchip Technology Inc. DS40192C-page 53

PIC16C505 9.16 PICDEM-17 The PICDEM-17 is an evaluation board that demon- strates the capabilities of several Microchip microcon- trollers, including PIC17C752, PIC17C756, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are sup- plied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with the other sample programs using the PRO MATE II or PICSTART Plus device programmers and easily debug and test the sample code. In addition, PICDEM-17 sup- ports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM-17 is also usable with the MPLAB-ICE or PICMASTER emu- lator, and all of the sample programs can be run and modified using either emulator. Additionally, a gener- ous prototype area is available for user hardware. 9.17 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials(cid:212) and secure serials. The Total Endurance(cid:212) Disk is included to aid in trade- off analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system. 9.18 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS40192C-page 54 ª 1999 Microchip Technology Inc.

PIC16C505 TABLE 9-1: DEVELOPMENT TOOLS FROM MICROCHIP 0152PCM Æ 7 7 XXXFRCM Æ Æ Æ Æ 76, 4, 7 3, XXXSCH Æ Æ Æ Æ 2, 7 7 XXC39 65, /XXC52 Æ Æ 4, 6 /XXC42 3, 6 2, 2XXC81CIP Æ Æ Æ Æ Æ Æ Æ C6 6 1 C PI XX7C71CIP Æ Æ Æ Æ Æ Æ Æ Æ with 1) 0 0 X4C71CIP Æ Æ Æ Æ Æ Æ Æ Æ 64 1 V D XX9C61CIP Æ Æ Æ Æ Æ Æ Æ Æ ger ( g u b e D XX8F61CIP Æ Æ Æ Æ Æ Æ uit c Cir n- X8C61CIP Æ Æ Æ Æ Æ Æ Æ Æ D I C B-I A L XX7C61CIP Æ Æ Æ Æ Æ Æ Æ P M e h e t X7C61CIP Æ Æ Æ Æ Æ *Æ Æ Æ †Æ†Æ us o w t o h X26F61CIP Æ Æ**Æ **Æ **Æ on n o ati XXXC61CIP Æ Æ Æ Æ Æ Æ Æ Æ orm nf or i X6C61CIP Æ Æ Æ Æ Æ *Æ Æ Æ †Æ m f o c p. hi c X5C61CIP Æ Æ Æ Æ Æ Æ Æ Æ Æ cro mi ww.e. X0X0X0C4211CCIPIP (cid:228) MPLABIntegratedDevelopment EnvironmentÆÆ(cid:228)MPLAB C17 Compiler (cid:228)MPLAB C18 Compiler MPASM/MPLINKÆÆMPLAB™-ICEÆÆPICMASTER/PICMASTER-CEÆÆ(cid:228) ICEPICLow-CostIn-Circuit EmulatorÆ MPLAB-ICD In-Circuit Debugger (cid:226)PICSTARTPlus Low-Cost Universal Dev. KitÆÆ (cid:226)PRO MATE II Universal ProgrammerÆÆ SIMICEÆPICDEM-1 PICDEM-2 PICDEM-3 PICDEM-14AÆPICDEM-17 ® KLEvaluation KitEEOQ KL Transponder KitEEOQ microID™ Programmer’s Kit 125 kHz microID Developer’s Kit 125 kHz Anticollision microID Developer’s Kit 13.56 MHz Anticollision microID Developer’s Kit MCP2510 CAN Developer’s Kit Contact the Microchip Technology Inc. web site at wContact Microchip Technology Inc. for availability datDevelopment tool is available on select devices. slooT erawtfoS srotalumE reggubeD sremmargorP stiK lavE dna sdraoB omeD ***† ª 1999 Microchip Technology Inc. DS40192C-page 55

PIC16C505 NOTES: DS40192C-page 56 ª 1999 Microchip Technology Inc.

PIC16C505 10.0 ELECTRICAL CHARACTERISTICS - PIC16C505 Absolute Maximum Ratings† Ambient Temperature under bias...........................................................................................................–40°C to +125°C Storage Temperature.............................................................................................................................–65°C to +150°C Voltage on VDD with respect to VSS....................................................................................................................0 to +7 V Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V Voltage on all other pins with respect to VSS...............................................................................–0.6 V to (VDD + 0.6 V) Total Power Dissipation(1)....................................................................................................................................700 mW Max. Current out of VSS pin..................................................................................................................................150 mA Max. Current into VDD pin.....................................................................................................................................125 mA Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................– 20 mA Output Clamp Current, IOK (VO < 0 or VO > VDD).............................................................................................................– 20 mA Max. Output Current sunk by any I/O pin................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................25 mA Max. Output Current sourced by I/O port .............................................................................................................100 mA Max. Output Current sunk by I/O port ..................................................................................................................100 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD-VOH) x IOH} + (cid:229) (VOL x IOL) †NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 57

PIC16C505 FIGURE 10-1: PIC16C505 VOLTAGE-FREQUENCY GRAPH, 0(cid:176) C £ TA £ +70(cid:176) C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. FIGURE 10-2: PIC16C505 VOLTAGE-FREQUENCY GRAPH, -40(cid:176) C £ TA £ 0(cid:176) C, +70(cid:176) C £ TA £ +125(cid:176) C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. DS40192C-page 58 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 FIGURE 10-3: PIC16LC505 VOLTAGE-FREQUENCY GRAPH, -40(cid:176) C £ TA £ +85(cid:176) C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 59

PIC16C505 10.1 DC CHARACTERISTICS: PIC16C505-04 (Commercial, Industrial, Extended) PIC16C505-20(Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 0(cid:176) C £ TA £ +70(cid:176) C (commercial) Power Supply Pins –40(cid:176) C £ TA £ +85(cid:176) C (industrial) –40(cid:176) C £ TA £ +125(cid:176) C (extended) Parm. Characteristic Sym Min Typ(1) Max Units Conditions No. D001 Supply Voltage VDD 3.0 5.5 V See Figure10-1 through Figure10-3 D002 RAM Data Retention VDR — 1.5* — V Device in SLEEP mode Voltage(2) D003 VDD Start Voltage to ensure VPOR — VSS — V See section on Power-on Reset for details Power-on Reset D004 VDD Rise Rate to ensure SVDD 0.05* — — V/ms See section on Power-on Reset for details Power-on Reset D010 Supply Current(3) IDD — 0.8 1.4 mA FOSC = 4MHz, VDD = 5.5V, WDT disabled (Note 4)* — 0.6 1.0 mA FOSC = 4MHz, VDD = 3.0V, WDT disabled (Note 4) — 3 7 mA FOSC = 10MHz, VDD = 3.0V, WDT disabled (Note 6) — 4 12 mA FOSC = 20MHz, VDD = 4.5V, WDT disabled — 4.5 16 mA FOSC = 20MHz, VDD = 5.5V, WDT disabled* — 19 27 m A FOSC = 32kHz, VDD = 3.0V, WDT disabled (Note 6) D020 Power-Down Current (5) IPD — 0.25 4 m A VDD = 3.0V (Note 6) — 0.4 5.5 m A VDD = 4.5V* (Note 6) — 3 8 m A VDD = 5.5V, Industrial — 5 14 m A VDD = 5.5V, Extended Temp. D022 WDT Current(5) D IWDT — 2.2 5 m A VDD = 3.0V (Note 6) 1A LP Oscillator Operating Fosc Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 20 MHz All temperatures * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25(cid:176) C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 6: Commercial temperature range only. DS40192C-page 60 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 10.2 DC CHARACTERISTICS: PIC16LC505-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 0(cid:176) C £ TA £ +70(cid:176) C (commercial) Power Supply Pins –40(cid:176) C £ TA £ +85(cid:176) C (industrial) Parm. Characteristic Sym Min Typ(1) Max Units Conditions No. D001 Supply Voltage VDD 2.5 — 5.5 V See Figure10-1 through Figure10-3 D002 RAM Data Retention VDR — 1.5* — V Device in SLEEP mode Voltage(2) D003 VDD Start Voltage to ensure VPOR — VSS — V See section on Power-on Reset for details Power-on Reset D004 VDD Rise Rate to ensure SVDD 0.05* — — V/ms See section on Power-on Reset for details Power-on Reset D010 Supply Current(3) IDD — 0.8 1.4 mA FOSC = 4MHz, VDD = 5.5V, WDT disabled (Note 4)* — 0.4 0.8 mA FOSC = 4MHz, VDD = 2.5V, WDT disabled (Note 4) — 15 23 m A FOSC = 32kHz, VDD = 2.5V, WDT disabled (Note 6) D020 Power-Down Current (5) IPD — 0.25 3 m A VDD = 2.5V (Note 6) — 0.25 4 m A VDD = 3.0V * (Note 6) — 3 8 m A VDD = 5.5V Industrial D022 WDT Current(5) D IWDT — 2.0 4 m A VDD = 2.5V (Note 6) 1A LP Oscillator Operating FOSC Frequency 0 — 200 kHz All temperatures RC Oscillator Operating Frequency 0 — 4 MHz All temperatures XT Oscillator Operating Frequency 0 — 4 MHz All temperatures HS Oscillator Operating Frequency 0 — 4 MHz All temperatures * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25(cid:176) C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 6: Commercial temperature range only. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 61

PIC16C505 10.3 DC CHARACTERISTICS: PIC16C505-04 (Commercial, Industrial, Extended) PIC16C505-20(Commercial, Industrial, Extended) PIC16LC505-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) DC CHARACTERISTICS –40°C £ TA £ +125°C (extended) Operating voltage VDD range as described in DC spec Section10.1 and Section10.3. Param Characteristic Sym Min Typ† Max Units Conditions No. Input Low Voltage I/O ports VIL D030 with TTL buffer VSS — 0.8V V For all 4.5 £ VDD £ 5.5V D030A VSS — 0.15VDD V otherwise D031 with Schmitt Trigger buffer VSS — 0.2VDD V D032 MCLR, RC5/T0CKI VSS — 0.2VDD V (in EXTRC mode) D033 OSC1 (in XT, HS and LP) VSS — 0.3VDD V Note1 Input High Voltage I/O ports VIH — D040 with TTL buffer 2.0 — VDD V 4.5 £ VDD £ 5.5V D040A 0.25VDD — VDD V + 0.8VDD otherwise D041 with Schmitt Trigger buffer 0.8VDD — VDD V For entire VDD range D042 MCLR, RC5/T0CKI 0.8VDD — VDD V D042A OSC1 (XT, HS and LP) 0.7VDD — VDD V Note1 D043 OSC1 (in EXTRC mode) 0.9VDD — VDD V D070 GPIO weak pull-up current (Note 4) IPUR 50 250 400 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL — — ±1 m A Vss £ VPIN £ VDD, Pin at hi-impedance D061 GP3/MCLRI (Note 5) — — ±30 m A Vss £ VPIN £ VDD D061A GP3/MCLRI (Note 6) — — ±5 m A Vss £ VPIN £ VDD D063 OSC1 — — ±5 m A Vss £ VPIN £ VDD, XT, HS and LP osc configuration Output Low Voltage D080 I/O ports/CLKOUT VOL — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, –40(cid:176) C to +85(cid:176) C D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, –40(cid:176) C to +125(cid:176) C D083 OSC2 — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, –40(cid:176) C to +85(cid:176) C D083A — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, –40(cid:176) C to +125(cid:176) C † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C505 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent nor- mal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: Does not include GP3. For GP3 see parameters D061 and D061A. 5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up enabled. 6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic. DS40192C-page 62 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) DC CHARACTERISTICS –40°C £ TA £ +125°C (extended) Operating voltage VDD range as described in DC spec Section10.1 and Section10.3. Param Characteristic Sym Min Typ† Max Units Conditions No. Output High Voltage D090 I/O ports/CLKOUT (Note 3) VOH VDD - 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, –40(cid:176) C to +85(cid:176) C D090A VDD - 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, –40(cid:176) C to +125(cid:176) C D092 OSC2 VDD - 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, –40(cid:176) C to +85(cid:176) C D092A VDD - 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, –40(cid:176) C to +125(cid:176) C Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 All I/O pins and OSC2 CIO — — 50 pF † Data in “Typ” column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C505 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent nor- mal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: Does not include GP3. For GP3 see parameters D061 and D061A. 5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up enabled. 6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 63

PIC16C505 TABLE 10-1: PULL-UP RESISTOR RANGES - PIC16C505 VDD (Volts) Temperature ((cid:176) C) Min Typ Max Units RB0/RB1/RB4 2.5 –40 38K 42K 63K W 25 42K 48K 63K W 85 42K 49K 63K W 125 50K 55K 63K W 5.5 –40 15K 17K 20K W 25 18K 20K 23K W 85 19K 22K 25K W 125 22K 24K 28K W RB3 2.5 –40 285K 346K 417K W 25 343K 414K 532K W 85 368K 457K 532K W 125 431K 504K 593K W 5.5 –40 247K 292K 360K W 25 288K 341K 437K W 85 306K 371K 448K W 125 351K 407K 500K W * These parameters are characterized but not tested. DS40192C-page 64 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 10.4 Timing Parameter Symbology and Load Conditions - PIC16C505 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 10-4: LOAD CONDITIONS - PIC16C505 Pin CL = 50 pF for all pins except OSC2 CL 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS (cid:211) 1999 Microchip Technology Inc. DS40192C-page 65

PIC16C505 10.5 Timing Diagrams and Specifications FIGURE 10-5: EXTERNAL CLOCK TIMING - PIC16C505 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176) C £ TA £ +70(cid:176) C (commercial), –40(cid:176) C £ TA £ +85(cid:176) C (industrial), –40(cid:176) C £ TA £ +125(cid:176) C (extended) Operating Voltage VDD range is described in Section10.1 Parameter Sym Characteristic Min Typ(1) Max Units Conditions No. 1A FOSC External CLKIN Frequency(2) DC — 4 MHz XT osc mode DC — 4 MHz HS osc mode (PIC16C505-04) DC — 20 MHz HS osc mode (PIC16C505-20) DC — 200 kHz LP osc mode Oscillator Frequency(2) DC — 4 MHz EXTRC osc mode 0.1 — 4 MHz XT osc mode 4 — 4 MHz HS osc mode (PIC16C505-04) DC — 200 kHz LP osc mode 1 TOSC External CLKIN Period(2) 250 — — ns XT osc mode 50 — — ns HS osc mode (PIC16C505-20) — — µs LP osc mode Oscillator Period(2) 250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS ocs mode (PIC16C505-04) 50 — 250 ns HS ocs mode (PIC16C505-20) 5 — — µs LP osc mode 2 TCY Instruction Cycle Time — 4/FOSC DC ns 200 — ns * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS40192C-page 66 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505 (CONTINUED) AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176) C £ TA £ +70(cid:176) C (commercial), –40(cid:176) C £ TA £ +85(cid:176) C (industrial), –40(cid:176) C £ TA £ +125(cid:176) C (extended) Operating Voltage VDD range is described in Section10.1 Parameter Sym Characteristic Min Typ(1) Max Units Conditions No. 3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator 2* — — µs LP oscillator 10 ns HS oscillator 4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator — — 50* ns LP oscillator — — 15 ns HS oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. TABLE 10-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC16C505 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176) C £ TA £ +70(cid:176) C (commercial), –40(cid:176) C £ TA £ +85(cid:176) C (industrial), –40(cid:176) C £ TA £ +125(cid:176) C (extended) Operating Voltage VDD range is described in Section10.1 Parameter Sym Characteristic Min* Typ(1) Max* Units Conditions No. Internal Calibrated RC Frequency 3.65 4.00 4.28 MHz VDD = 5.0V Internal Calibrated RC Frequency 3.55 4.00 4.31 MHz VDD = 2.5V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 67

PIC16C505 FIGURE 10-6: I/O TIMING - PIC16C505 Q4 Q1 Q2 Q3 OSC1 I/O Pin (input) 17 19 18 I/O Pin Old Value New Value (output) 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 10-4: TIMING REQUIREMENTS - PIC16C505 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176) C £ TA £ +70(cid:176) C (commercial) –40(cid:176) C £ TA £ +85(cid:176) C (industrial) –40(cid:176) C £ TA £ +125(cid:176) C (extended) Operating Voltage VDD range is described in Section10.1 Parameter No. Sym Characteristic Min Typ(1) Max Units 17 TosH2ioV OSC1› (Q1 cycle) to Port out valid(2,3) — — 100* ns 18 TosH2ioI OSC1› (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time)(2) 19 TioV2osH Port input valid to OSC1› TBD — — ns (I/O in setup time) 20 TioR Port output rise time(3) — 10 25** ns 21 TioF Port output fall time(3) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure10-4 for loading conditions. DS40192C-page 68 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 FIGURE 10-7: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C505 VDD MCLR 30 Internal POR 32 32 32 DRT Timeout (Note 2) Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT, LP and HS modes. TABLE 10-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C505 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176) C £ TA £ +70(cid:176) C (commercial) –40(cid:176) C £ TA £ +85(cid:176) C (industrial) –40(cid:176) C £ TA £ +125(cid:176) C (extended) Operating Voltage VDD range is described in Section10.1 Parameter No. Sym Characteristic Min Typ(1) Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5.0 V 31 Twdt Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5.0 V (Commercial) (No Prescaler) 32 TDRT Device Reset Timer Period(2) 9* 18* 30* ms VDD = 5.0 V (Commercial) 34 TioZ I/O Hi-impedance from MCLR Low — — 2000* ns * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176) C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 10-6: DRT (DEVICE RESET TIMER PERIOD - PIC16C505 Oscillator Configuration POR Reset Subsequent Resets IntRC & ExtRC 18 ms (typical) 300 µs (typical) XT, HS & LP 18 ms (typical) 18 ms (typical) (cid:211) 1999 Microchip Technology Inc. DS40192C-page 69

PIC16C505 FIGURE 10-8: TIMER0 CLOCK TIMINGS - PIC16C505 T0CKI 40 41 42 TABLE 10-7: TIMER0 CLOCK REQUIREMENTS - PIC16C505 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176) C £ TA £ +70(cid:176) C (commercial) –40(cid:176) C £ TA £ +85(cid:176) C (industrial) –40(cid:176) C £ TA £ +125(cid:176) C (extended) Operating Voltage VDD range is described in Section10.1. Parm Sym Characteristic Min Typ(1) Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40192C-page 70 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 11.0 DC AND AC FIGURE 11-2: CALIBRATED INTERNAL RC CHARACTERISTICS - FREQUENCY RANGE VS. PIC16C505 TEMPERATURE (VDD = 2.5V) (INTERNAL RC IS The graphs and tables provided in this section are for CALIBRATED TO 25°C, 5.0V) design guidance and are not tested. In some graphs or tables the data presented are outside specified 4.50 operating range (e.g., outside specified VDD range). This is for information only and devices will operate 4.40 properly only within the specified range. The data presented in this section is a statistical 4.30 summary of data collected on units from different lots Max. over a period of time. “Typical” represents the mean of 4.20 the distribution while “max” or “min” represents (mean + 3s ) and (mean – 3s ) respectively, where s is ) 4.10 z standard deviation. H M FIGURE 11-1: CALIBRATED INTERNAL RC y ( 4.00 c FREQUENCY RANGE VS. n e TEMPERATURE (VDD = 5.0V) qu 3.90 (INTERNAL RC IS Fre CALIBRATED TO 25°C, 5.0V) 3.80 4.50 3.70 4.40 3.60 4.30 Min. 3.50 -40 0 25 85 125 4.20 Max. Temperature (Deg.C) z) 4.10 H M ( y 4.00 c n e u q 3.90 e Fr 3.80 3.70 Min. 3.60 3.50 -40 0 25 85 125 Temperature (Deg.C) (cid:211) 1999 Microchip Technology Inc. DS40192C-page 71

PIC16C505 TABLE 11-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C Oscillator Frequency VDD = 3.0V(1) VDD = 5.5V External RC 4 MHz 240 µA(2) 800 µA(2) Internal RC 4 MHz 320 µA 800 µA XT 4 MHz 300 µA 800 µA LP 32 kHz 19 µA 50 µA HS 20 MHz N/A 4.5 mA Note 1: LP oscillator based on VDD = 2.5V 2: Does not include current through external R&C. FIGURE 11-3: WDT TIMER TIME-OUT FIGURE 11-4: SHORT DRT PERIOD VS. VDD PERIOD vs. VDD 950 55 850 50 750 45 650 40 ) s µ S) d ( 550 d (µ 35 erio Max +125(cid:176)C erio Max +125(cid:176)C T p 450 p D Max +85(cid:176)C T 30 W D W Max +85(cid:176)C 350 25 Typ +25(cid:176)C 250 20 MIn –40(cid:176)C Typ +25(cid:176)C 150 15 MIn –40(cid:176)C 0 0 2.5 3.5 4.5 5.5 6.5 10 0 2.5 3.5 4.5 5.5 6.5 VDD (Volts) VDD (Volts) DS40192C-page 72 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 FIGURE 11-5: IOH vs. VOH, VDD = 2.5 V FIGURE 11-7: IOL vs. VOL, VDD = 2.5 V 25 0 -1 20 -2 Max –40(cid:176)C 15 ) -3 A m I (OH -4 (mA)L Typ +25(cid:176)C O I 10 Min +125(cid:176)C -5 Min +85(cid:176)C Min +85(cid:176)C Min +125(cid:176)C 5 -6 Typ +25(cid:176)C Max –40(cid:176)C -7 500m 1.0 1.5 2.0 2.5 0 VOH (Volts) 0 250.0m 500.0m 1.0 VOL (Volts) FIGURE 11-6: IOH vs. VOH, VDD = 5.5 V FIGURE 11-8: IOL vs. VOL, VDD = 5.5 V 0 50 -5 Max –40(cid:176)C 40 -10 mA) 30 Typ +25(cid:176)C (H -15 A) IO m -20 Min +12(cid:176)5CC I (OL 20 Min +85(cid:176)C Min +8(cid:176)5 C -25 TyMp a+x 2(cid:176)–54(cid:176)0C 10 Min +125(cid:176)C -30 3.5 4.0 4.5 5.0 5.5 VOH (Volts) 0 250.0m 500.0m 750.0m 1.0 VOL (Volts) (cid:211) 1999 Microchip Technology Inc. DS40192C-page 73

PIC16C505 NOTES: DS40192C-page 74 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 11.0 PACKAGING INFORMATION 11.1 Package Marking Information 14-Lead PDIP (300 mil) Example XXXXXXXXXXXXXX 16C505-04I/P XXXXXXXXXXXXXX BUILT 4 SPEED AABBCDE 9904SAZ 14-Lead SOIC (150 mil) Example XXXXXXXXXX 16C505-04I AABBCDE 9904SAZ 14-Lead Windowed Ceramic (300 mil) Example XXX JW XXXXXX 16C505 Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5” Line S = 6” Line H = 8” Line D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 75

PIC16C505 14-Lead Plastic Dual In-line (P) –300 mil (PDIP) E1 D 2 n 1 a E A A2 c L A1 b B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .740 .750 .760 18.80 19.05 19.30 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness c .008 .012 .015 0.20 0.29 0.38 Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom b 5 10 15 5 10 15 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS40192C-page 76 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 14-Lead Plastic Small Outline (SL) –Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 a h 45(cid:176) c A A2 f A1 L b Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .050 1.27 Overall Height A .053 .061 .069 1.35 1.55 1.75 Molded Package Thickness A2 .052 .056 .061 1.32 1.42 1.55 Standoff A1 .004 .007 .010 0.10 0.18 0.25 Overall Width E .228 .236 .244 5.79 5.99 6.20 Molded Package Width E1 .150 .154 .157 3.81 3.90 3.99 Overall Length D .337 .342 .347 8.56 8.69 8.81 Chamfer Distance h .010 .015 .020 0.25 0.38 0.51 Foot Length L .016 .033 .050 0.41 0.84 1.27 Foot Angle f 0 4 8 0 4 8 Lead Thickness c .008 .009 .010 0.20 0.23 0.25 Lead Width B .014 .017 .020 0.36 0.42 0.51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom b 0 12 15 0 12 15 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 (cid:211) 1999 Microchip Technology Inc. DS40192C-page 77

PIC16C505 14-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil E1 W T D 2 n 1 U A A2 L A1 c B1 eB B p Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Top to Seating Plane A .142 .162 .182 3.61 4.11 4.62 Top of Body to Seating Plane A2 .100 .120 .140 2.54 3.05 3.56 Standoff A1 .025 .035 .045 0.64 0.89 1.14 Package Width E1 .280 .290 .300 7.11 7.37 7.62 Overall Length D .693 .700 .707 17.60 17.78 17.96 Tip to Seating Plane L .130 .140 .150 3.30 3.56 3.81 Lead Thickness c .008 .010 .012 0.20 0.25 0.30 Upper Lead Width B1 .052 .054 .056 1.32 1.37 1.42 Lower Lead Width B .016 .018 .020 0.41 0.46 0.51 Overall Row Spacing eB .296 .310 .324 7.52 7.87 8.23 Window Diameter W .161 .166 .171 4.09 4.22 4.34 Lid Length T .440 .450 .460 11.18 11.43 11.68 Lid Width U .260 .270 .280 6.60 6.86 7.11 *Controlling Parameter JEDEC Equivalent: MS-015 Drawing No. C04-107 DS40192C-page 78 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 INDEX Oscillator Types HS...............................................................................28 A LP...............................................................................28 ALU.......................................................................................7 RC..............................................................................28 Applications...........................................................................3 XT...............................................................................28 Architectural Overview..........................................................7 P Assembler MPASM Assembler.....................................................51 Package Marking Information.............................................75 Packaging Information........................................................75 B PICDEM-1 Low-Cost PICmicro Demo Board.....................53 Block Diagram PICDEM-2 Low-Cost PIC16CXX Demo Board...................53 On-Chip Reset Circuit.................................................33 PICDEM-3 Low-Cost PIC16CXXX Demo Board................53 Timer0.........................................................................23 PICSTART(cid:210) Plus Entry Level Development System.........53 TMR0/WDT Prescaler.................................................26 POR Watchdog Timer..........................................................35 Device Reset Timer (DRT)...................................27, 34 Brown-Out Protection Circuit..............................................36 PD...............................................................................36 C Power-On Reset (POR)..............................................27 CAL0 bit..............................................................................16 TO...............................................................................36 CAL1 bit..............................................................................16 PORTB...............................................................................19 CAL2 bit..............................................................................16 Power-Down Mode.............................................................37 CAL3 bit..............................................................................16 Prescaler............................................................................26 CALFST bit.........................................................................16 PRO MATE(cid:210) II Universal Programmer..............................53 CALSLW bit........................................................................16 Program Counter................................................................17 Carry.....................................................................................7 Q Clocking Scheme................................................................10 Q cycles..............................................................................10 Code Protection............................................................27, 37 R Configuration Bits................................................................27 Configuration Word.............................................................27 RC Oscillator.......................................................................29 Read Modify Write..............................................................20 D Register File Map................................................................12 DC and AC Characteristics.................................................71 Registers Development Support.........................................................51 Special Function.........................................................13 Device Varieties....................................................................5 Reset..................................................................................27 Digit Carry.............................................................................7 Reset on Brown-Out...........................................................36 E S Errata....................................................................................2 SEEVAL(cid:210) Evaluation and Programming System..............54 F SLEEP..........................................................................27, 37 Family of Devices Software Simulator (MPLAB-SIM)......................................52 PIC16C505...................................................................4 Special Features of the CPU..............................................27 FSR.....................................................................................18 Special Function Registers.................................................13 Stack...................................................................................17 I STATUS...............................................................................7 I/O Interfacing.....................................................................19 STATUS Register...............................................................14 I/O Ports..............................................................................19 T I/O Programming Considerations........................................20 ID Locations..................................................................27, 37 Timer0 INDF....................................................................................18 Switching Prescaler Assignment................................26 Indirect Data Addressing.....................................................18 Timer0........................................................................23 Instruction Cycle.................................................................10 Timer0 (TMR0) Module..............................................23 Instruction Flow/Pipelining..................................................10 TMR0 with External Clock..........................................25 Instruction Set Summary.....................................................40 Timing Diagrams and Specifications..................................66 Timing Parameter Symbology and Load Conditions..........65 K TRIS Registers...................................................................19 KeeLoq(cid:210) Evaluation and Programming Tools....................54 W L Wake-up from SLEEP.........................................................37 Loading of PC.....................................................................17 Watchdog Timer (WDT)................................................27, 34 M Period.........................................................................35 Memory Organization..........................................................11 Programming Considerations.....................................35 Data Memory..............................................................12 WWW, On-Line Support.......................................................2 Program Memory........................................................11 Z MPLAB Integrated Development Environment Software....51 Zero bit.................................................................................7 O OPTION Register................................................................15 OSC selection.....................................................................27 OSCCAL Register...............................................................16 Oscillator Configurations.....................................................28 (cid:211) 1999 Microchip Technology Inc. DS40192B-page 79

PIC16C505 NOTES: DS40192B-page 80 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 ON-LINE SUPPORT Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides Microchip provides on-line support on the Microchip system users a listing of the latest versions of all of World Wide Web (WWW) site. Microchip’s development systems software products. The web site is used by Microchip as a means to make Plus, this line provides information on how customers files and information easily available to customers. To can receive any currently available upgrade kits.The view the site, the user must have access to the Internet Hot Line Numbers are: and a web browser, such as Netscape or Microsoft 1-800-755-2345 for U.S. and most of Canada, and Explorer. Files are also available for FTP download from our FTP site. 1-480-786-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 981103 The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User’s Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: Trademarks: The Microchip name, logo, PIC, PICmicro, • Latest Microchip Press Releases PICSTART, PICMASTER and PRO MATE are registered • Technical Support Section with Frequently Asked trademarks of Microchip Technology Incorporated in the Questions U.S.A. and other countries. FlexROM, MPLAB and fuzzy- LAB are trademarks and SQTP is a service mark of • Design Tips Microchip in the U.S.A. • Device Errata All other trademarks mentioned herein are the property of • Job Postings their respective companies. • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Sys- tems, technical information and more • Listing of seminars and events (cid:211) 1999 Microchip Technology Inc. DS40192C-page 81

PIC16C505 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC16C505 Literature Number: DS40192C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS40192C-page 82 (cid:211) 1999 Microchip Technology Inc.

PIC16C505 PIC16C505 Product Identification System PART NO. -XX X /XX XXX Examples Pattern: Special Requirements a) PIC16C505-04/P Commercial Temp., Package: SL = 150 mil SOIC PDIP Package, 4MHz, P = 300 mil PDIP normal VDD limits JW = 300 mil Windowed Ceramic Side Brazed b) PIC16C505-04I/SL Temperature - = 0(cid:176) C to +70(cid:176) C Industrial Temp., SOIC Range: IE == --4400(cid:176)(cid:176) CC ttoo ++1825(cid:176)5C(cid:176) C package, 4MHz, normal VDD limits Frequency 04 = 4 MHz (XT, INTRC, EXTRC OSC) Range: 20 = 20 MHz (HS OSC) c) PIC16C505-04I/P Industrial Temp., PDIP package, 4MHz, Device PIC16C505 PIC16LC505 normal VDD limits PIC16C505T (Tape & reel for SOIC only) PIC16LC505T (Tape & reel for SOIC only) Please contact your local sales office for exact ordering procedures. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. (cid:211) 1999 Microchip Technology Inc. DS40192C-page 83

Note the following details of the code protection feature on PICmicro® MCUs. (cid:127) The PICmicro family meets the specifications contained in the Microchip Data Sheet. (cid:127) Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl- edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”. (cid:127) Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab, ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech- to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries. patents or other intellectual property rights arising from such dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, use or otherwise. Use of Microchip’s products as critical com- In-Circuit Serial Programming, ICSP, ICEPIC, microPort, ponents in life support systems is not authorized except with Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, express written approval by Microchip. No licenses are con- MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode veyed, implicitly or otherwise, under any intellectual property and Total Endurance are trademarks of Microchip Technology rights. Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc.

M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia Microchip Technology Japan K.K. Benex S-1 6F 2355 West Chandler Blvd. Microchip Technology Australia Pty Ltd 3-18-20, Shinyokohama Chandler, AZ 85224-6199 Suite 22, 41 Rawson Street Kohoku-Ku, Yokohama-shi Tel: 480-792-7200 Fax: 480-792-7277 Epping 2121, NSW Kanagawa, 222-0033, Japan Technical Support: 480-792-7627 Australia Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Web Address: http://www.microchip.com Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Rocky Mountain China - Beijing Korea 2355 West Chandler Blvd. Microchip Technology Consulting (Shanghai) Microchip Technology Korea Chandler, AZ 85224-6199 Co., Ltd., Beijing Liaison Office 168-1, Youngbo Bldg. 3 Floor Tel: 480-792-7966 Fax: 480-792-7456 Unit 915 Samsung-Dong, Kangnam-Ku Bei Hai Wan Tai Bldg. Seoul, Korea 135-882 Atlanta No. 6 Chaoyangmen Beidajie Tel: 82-2-554-7200 Fax: 82-2-558-5934 500 Sugar Mill Road, Suite 200B Beijing, 100027, No. China Singapore Atlanta, GA 30350 Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Singapore Pte Ltd. Tel: 770-640-0034 Fax: 770-640-0307 China - Chengdu 200 Middle Road Boston #07-02 Prime Centre Microchip Technology Consulting (Shanghai) 2 Lan Drive, Suite 120 Singapore, 188980 Co., Ltd., Chengdu Liaison Office Westford, MA 01886 Tel: 65-334-8870 Fax: 65-334-8850 Rm. 2401, 24th Floor, Tel: 978-692-3848 Fax: 978-692-3821 Taiwan Ming Xing Financial Tower Chicago No. 88 TIDU Street Microchip Technology Taiwan 333 Pierce Road, Suite 180 Chengdu 610016, China 11F-3, No. 207 Itasca, IL 60143 Tel: 86-28-6766200 Fax: 86-28-6766599 Tung Hua North Road Tel: 630-285-0071 Fax: 630-285-0075 China - Fuzhou Taipei, 105, Taiwan Dallas Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Microchip Technology Consulting (Shanghai) 4570 Westgrove Drive, Suite 160 Co., Ltd., Fuzhou Liaison Office Addison, TX 75001 Unit 28F, World Trade Plaza EUROPE Tel: 972-818-7423 Fax: 972-818-2924 No. 71 Wusi Road Detroit Fuzhou 350001, China Denmark Tri-Atria Office Building Tel: 86-591-7503506 Fax: 86-591-7503521 Microchip Technology Nordic ApS 32255 Northwestern Highway, Suite 190 China - Shanghai Regus Business Centre Farmington Hills, MI 48334 Microchip Technology Consulting (Shanghai) Lautrup hoj 1-3 Tel: 248-538-2250 Fax: 248-538-2260 Co., Ltd. Ballerup DK-2750 Denmark Kokomo Room 701, Bldg. B Tel: 45 4420 9895 Fax: 45 4420 9910 2767 S. Albright Road Far East International Plaza France Kokomo, Indiana 46902 No. 317 Xian Xia Road Microchip Technology SARL Tel: 765-864-8360 Fax: 765-864-8387 Shanghai, 200051 Parc d’Activite du Moulin de Massy Los Angeles Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 43 Rue du Saule Trapu 18201 Von Karman, Suite 1090 China - Shenzhen Batiment A - ler Etage Irvine, CA 92612 Microchip Technology Consulting (Shanghai) 91300 Massy, France Tel: 949-263-1888 Fax: 949-263-1338 Co., Ltd., Shenzhen Liaison Office Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 New York Rm. 1315, 13/F, Shenzhen Kerry Centre, Germany 150 Motor Parkway, Suite 202 Renminnan Lu Microchip Technology GmbH Hauppauge, NY 11788 Shenzhen 518001, China Gustav-Heinemann Ring 125 Tel: 631-273-5305 Fax: 631-273-5335 Tel: 86-755-2350361 Fax: 86-755-2366086 D-81739 Munich, Germany San Jose Hong Kong Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology Inc. Microchip Technology Hongkong Ltd. 2107 North First Street, Suite 590 Unit 901-6, Tower 2, Metroplaza Microchip Technology SRL San Jose, CA 95131 223 Hing Fong Road Centro Direzionale Colleoni Tel: 408-436-7950 Fax: 408-436-7955 Kwai Fong, N.T., Hong Kong Palazzo Taurus 1 V. Le Colleoni 1 Toronto Tel: 852-2401-1200 Fax: 852-2401-3431 20041 Agrate Brianza Milan, Italy 6285 Northam Drive, Suite 108 India Tel: 39-039-65791-1 Fax: 39-039-6899883 Mississauga, Ontario L4V 1X5, Canada Microchip Technology Inc. United Kingdom Tel: 905-673-0699 Fax: 905-673-6509 India Liaison Office Divyasree Chambers Arizona Microchip Technology Ltd. 505 Eskdale Road 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Winnersh Triangle Bangalore, 560 025, India Wokingham Tel: 91-80-2290061 Fax: 91-80-2290062 Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 01/18/02  2002 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC16C505-20/P PIC16C505T-20E/SL PIC16C505T-20/SL PIC16C505-20/SL PIC16C505-20I/P PIC16C505/JW PIC16C505-04E/SL PIC16C505T-04I/SL PIC16C505-20E/SL PIC16LC505T-04I/SL PIC16LC505T-04/SL PIC16C505T-04E/SL PIC16LC505-04/P PIC16LC505-04I/SL PIC16C505-04E/P PIC16C505-04/P PIC16C505-20E/P PIC16C505T-04/SL PIC16C505-04/SL PIC16C505-04I/P PIC16C505T-20I/SL PIC16LC505-04/SL PIC16LC505- 04I/P PIC16C505-04I/SL PIC16C505-20I/SL