PIC12F683 Data Sheet 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology © 2007 Microchip Technology Inc. DS41211D

Note the following details of the code protection feature on Microchip devices: (cid:129) Microchip products meet the specification contained in their particular Microchip Data Sheet. (cid:129) Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. (cid:129) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. (cid:129) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:129) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, ensure that your application meets with your specifications. PICmicro, PICSTART, PROMATE, PowerSmart, rfPIC, and MICROCHIP MAKES NO REPRESENTATIONS OR SmartShunt are registered trademarks of Microchip WARRANTIES OF ANY KIND WHETHER EXPRESS OR Technology Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41211D-page ii © 2007 Microchip Technology Inc.

PIC12F683 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology High-Performance RISC CPU: Low-Power Features: (cid:129) Only 35 instructions to learn: (cid:129) Standby Current: - All single-cycle instructions except branches - 50nA @ 2.0V, typical (cid:129) Operating speed: (cid:129) Operating Current: - DC – 20MHz oscillator/clock input - 11μA @ 32kHz, 2.0V, typical - DC – 200ns instruction cycle - 220μA @ 4MHz, 2.0V, typical (cid:129) Interrupt capability (cid:129) Watchdog Timer Current: (cid:129) 8-level deep hardware stack - 1μA @ 2.0V, typical (cid:129) Direct, Indirect and Relative Addressing modes Peripheral Features: Special Microcontroller Features: (cid:129) 6 I/O pins with individual direction control: (cid:129) Precision Internal Oscillator: - High current source/sink for direct LED drive - Factory calibrated to ±1%, typical - Interrupt-on-pin change - Software selectable frequency range of - Individually programmable weak pull-ups 8MHz to 125kHz - Ultra Low-Power Wake-up on GP0 - Software tunable (cid:129) Analog Comparator module with: - Two-Speed Start-up mode - One analog comparator - Crystal fail detect for critical applications - Clock mode switching during operation for - Programmable on-chip voltage reference power savings (CVREF) module (% of VDD) (cid:129) Power-Saving Sleep mode - Comparator inputs and output externally (cid:129) Wide operating voltage range (2.0V-5.5V) accessible (cid:129) Industrial and Extended temperature range (cid:129) A/D Converter: (cid:129) Power-on Reset (POR) - 10-bit resolution and 4 channels (cid:129) Power-up Timer (PWRT) and Oscillator Start-up (cid:129) Timer0: 8-bit timer/counter with 8-bit Timer (OST) programmable prescaler (cid:129) Brown-out Reset (BOR) with software control (cid:129) Enhanced Timer1: option - 16-bit timer/counter with prescaler (cid:129) Enhanced Low-Current Watchdog Timer (WDT) - External Timer1 Gate (count enable) with on-chip oscillator (software selectable nomi- - Option to use OSC1 and OSC2 in LP mode as nal 268 seconds with full prescaler) with software Timer1 oscillator if INTOSC mode selected enable (cid:129) Timer2: 8-bit timer/counter with 8-bit period (cid:129) Multiplexed Master Clear with pull-up/input pin register, prescaler and postscaler (cid:129) Programmable code protection (cid:129) Capture, Compare, PWM module: (cid:129) High Endurance Flash/EEPROM cell: - 16-bit Capture, max resolution 12.5ns - 100,000 write Flash endurance - Compare, max resolution 200ns - 1,000,000 write EEPROM endurance - 10-bit PWM, max frequency 20kHz - Flash/Data EEPROM Retention: > 40 years (cid:129) In-Circuit Serial Programming™ (ICSP™) via two pins Program Memory Data Memory Timers Device I/O 10-bit A/D (ch) Comparators Flash (words) SRAM (bytes) EEPROM (bytes) 8/16-bit PIC12F683 2048 128 256 6 4 1 2/1 © 2007 Microchip Technology Inc. DS41211D-page 1

PIC12F683 8-Pin Diagram (PDIP, SOIC) VDD 1 8 VSS 3 GP5/T1CKI/OSC1/CLKIN 2 8 7 GP0/AN0/CIN+/ICSPDAT/ULPWU 6 F 2 1 GP4/AN3/T1G/OSC2/CLKOUT 3 C 6 GP1/AN1/CIN-/VREF/ICSPCLK PI GP3/MCLR/VPP 4 5 GP2/AN2/T0CKI/INT/COUT/CCP1 8-Pin Diagram (DFN) VDD 1 8 VSS GP5/TICKI/OSC1/CLKIN 2 7 GP0/AN0/CIN+/ICSPDAT/ULPWU PIC12F683 GP4/AN3/TIG/OSC2/CLKOUT 3 6 GP1/AN1/CIN-/VREF/ICSPCLK GP3/MCLR/VPP 4 5 GP2/AN2/T0CKI/INT/COUT/CCP1 8-Pin Diagram (DFN-S) VDD 1 8 VSS GP5/TICKI/OSC1/CLKIN 2 7 GP0/AN0/CIN+/ICSPDAT/ULPWU PIC12F683 GP4/AN3/TIG/OSC2/CLKOUT 3 6 GP1/AN1/CIN-/VREF/ICSPCLK GP3/MCLR/VPP 4 5 GP2/AN2/T0CKI/INT/COUT/CCP1 TABLE 1: 8-PIN SUMMARY I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic GP0 7 AN0 CIN+ — — IOC Y ICSPDAT/ULPWU GP1 6 AN1/VREF CIN- — — IOC Y ICSPCLK GP2 5 AN2 COUT T0CKI CCP1 INT/IOC Y — GP3(1) 4 — — — — IOC Y(2) MCLR/VPP GP4 3 AN3 — T1G — IOC Y OSC2/CLKOUT GP5 2 — — T1CKI — IOC Y OSC1/CLKIN — 1 — — — — — — VDD — 8 — — — — — — VSS Note 1: Input only. 2: Only when pin is configured for external MCLR. DS41211D-page 2 © 2007 Microchip Technology Inc.

PIC12F683 Table of Contents 1.0 Device Overview..........................................................................................................................................................................5 2.0 Memory Organization...................................................................................................................................................................7 3.0 Oscillator Module (With Fail-Safe Clock Monitor).......................................................................................................................19 4.0 GPIO Port...................................................................................................................................................................................31 5.0 Timer0 Module...........................................................................................................................................................................41 6.0 Timer1 Module with Gate Control...............................................................................................................................................44 7.0 Timer2 Module...........................................................................................................................................................................49 8.0 Comparator Module....................................................................................................................................................................51 9.0 Analog-to-Digital Converter (ADC) Module................................................................................................................................61 10.0 Data EEPROM Memory.............................................................................................................................................................71 11.0 Capture/Compare/PWM (CCP) Module.....................................................................................................................................75 12.0 Special Features of the CPU......................................................................................................................................................83 13.0 Instruction Set Summary..........................................................................................................................................................101 14.0 Development Support...............................................................................................................................................................111 15.0 Electrical Specifications............................................................................................................................................................115 16.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................137 17.0 Packaging Information..............................................................................................................................................................159 Appendix A: Data Sheet Revision History..........................................................................................................................................165 Appendix B: Migrating From Other PIC® Devices.............................................................................................................................165 The Microchip Web Site.....................................................................................................................................................................171 Customer Change Notification Service..............................................................................................................................................171 Customer Support..............................................................................................................................................................................171 Reader Response..............................................................................................................................................................................172 Product Identification System............................................................................................................................................................173 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: (cid:129) Microchip’s Worldwide Web site; http://www.microchip.com (cid:129) Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. DS41211D-page 3

PIC12F683 NOTES: DS41211D-page 4 © 2007 Microchip Technology Inc.

PIC12F683 1.0 DEVICE OVERVIEW The PIC12F683 is covered by this data sheet. It is available in 8-pin PDIP, SOIC and DFN-S packages. Figure1-1 shows a block diagram of the PIC12F683 device. Table1-1 shows the pinout description. FIGURE 1-1: PIC12F683 BLOCK DIAGRAM INT Configuration 13 8 Data Bus Program Counter GP0 Flash GP1 2k x 14 Program RAM GP2 Memory 8-Level Stack 128 bytes GP3 (13-bit) File GP4 Registers GP5 Program 14 Bus RAM Addr 9 Addr MUX Instruction Reg Direct Addr 7 Indirect 8 Addr FSR Reg STATUS Reg 8 3 MUX Power-up Timer Instruction Oscillator Decode & Start-up Timer ALU Control Power-on 8 Reset OSC1/CLKIN GeTnimeriantgion WaTticmhedrog W Reg Brown-out OSC2/CLKOUT Reset Internal Oscillator Block CCP1 T1G MCLR VDD VSS T1CKI Timer0 Timer1 Timer2 CCP T0CKI Analog-to-Digital Converter 1 Analog Comparator EEDATA 256 bytes 8 Data EEPROM EEADDR VREF AN0 AN1AN2 AN3 CVREF CIN- CIN+ COUT © 2007 Microchip Technology Inc. DS41211D-page 5

PIC12F683 TABLE 1-1: PIC12F683 PINOUT DESCRIPTION Input Output Name Function Description Type Type VDD VDD Power — Positive supply GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change T1CKI ST — Timer1 clock OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection GP4/AN3/T1G/OSC2/CLKOUT GP4 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change AN3 AN — A/D Channel 3 input T1G ST — Timer1 gate OSC2 — XTAL Crystal/Resonator CLKOUT — CMOS FOSC/4 output GP3/MCLR/VPP GP3 TTL — GPIO input with interrupt-on-change MCLR ST — Master Clear with internal pull-up VPP HV — Programming voltage GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 ST CMOS GPIO I/O with prog. pull-up and interrupt-on-change AN2 AN — A/D Channel 2 input T0CKI ST — Timer0 clock input INT ST — External Interrupt COUT — CMOS Comparator 1 output CCP1 ST CMOS Capture input/Compare output/PWM output GP1/AN1/CIN-/VREF/ICSPCLK GP1 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change AN1 AN — A/D Channel 1 input CIN- AN — Comparator 1 input VREF AN — External Voltage Reference for A/D ICSPCLK ST — Serial Programming Clock GP0/AN0/CIN+/ICSPDAT/ULPWU GP0 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change AN0 AN — A/D Channel 0 input CIN+ AN — Comparator 1 input ICSPDAT ST CMOS Serial Programming Data I/O ULPWU AN — Ultra Low-Power Wake-up input VSS VSS Power — Ground reference Legend: AN = Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal DS41211D-page 6 © 2007 Microchip Technology Inc.

PIC12F683 2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization The data memory (see Figure2-2) is partitioned into two 2.1 Program Memory Organization banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The The PIC12F683 has a 13-bit program counter capable Special Function Registers are located in the first 32 of addressing an 8k x 14 program memory space. Only locations of each bank. Register locations 20h-7Fh in the first 2k x 14 (0000h-07FFh) for the PIC12F683 is Bank 0 and A0h-BFh in Bank 1 are General Purpose physically implemented. Accessing a location above Registers, implemented as static RAM. Register these boundaries will cause a wraparound within the locations F0h-FFh in Bank 1 point to addresses 70h-7Fh first 2K x 14 space. The Reset vector is at 0000h and in Bank 0. All other RAM is unimplemented and returns the interrupt vector is at 0004h (see Figure2-1). ‘0’ when read. RP0 of the STATUS register is the bank select bit. FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE RP0 PIC12F683 0 → Bank 0 is selected 1 → Bank 1 is selected PC<12:0> CALL, RETURN 13 RETFIE, RETLW Note: The IRP and RP1 bits of the STATUS register are reserved and should always Stack Level 1 be maintained as ‘0’s. Stack Level 2 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory 07FFh 0800h Wraps to 0000h-07FFh 1FFFh © 2007 Microchip Technology Inc. DS41211D-page 7

PIC12F683 2.2.1 GENERAL PURPOSE REGISTER FIGURE 2-2: DATA MEMORY MAP OF FILE THE PIC12F683 The register file is organized as 128 x 8 in the File File PIC12F683. Each register is accessed, either directly Address Address or indirectly, through the File Select Register FSR (see Indirect addr.(1) 00h Indirect addr.(1) 80h Section2.4 “Indirect Addressing, INDF and FSR TMR0 01h OPTION_REG 81h Registers”). PCL 02h PCL 82h 2.2.2 SPECIAL FUNCTION REGISTERS STATUS 03h STATUS 83h FSR 04h FSR 84h The Special Function Registers are registers used by GPIO 05h TRISIO 85h the CPU and peripheral functions for controlling the 06h 86h desired operation of the device (see Table2-1). These 07h 87h registers are static RAM. 08h 88h The special registers can be classified into two sets: 09h 89h core and peripheral. The Special Function Registers PCLATH 0Ah PCLATH 8Ah associated with the “core” are described in this section. INTCON 0Bh INTCON 8Bh Those related to the operation of the peripheral PIR1 0Ch PIE1 8Ch features are described in the section of that peripheral 0Dh 8Dh feature. TMR1L 0Eh PCON 8Eh TMR1H 0Fh OSCCON 8Fh T1CON 10h OSCTUNE 90h TMR2 11h 91h T2CON 12h PR2 92h CCPR1L 13h 93h CCPR1H 14h 94h CCP1CON 15h WPU 95h 16h IOC 96h 17h 97h WDTCON 18h 98h CMCON0 19h VRCON 99h CMCON1 1Ah EEDAT 9Ah 1Bh EEADR 9Bh 1Ch EECON1 9Ch 1Dh EECON2(1) 9Dh ADRESH 1Eh ADRESL 9Eh ADCON0 1Fh ANSEL 9Fh 20h General A0h Purpose Registers 32 Bytes BFh General Purpose C0h Registers 96 Bytes EFh F0h Accesses 70h-7Fh 7Fh FFh BANK 0 BANK 1 Unimplemented data memory locations, read as ‘0’. Note1: Not a physical register. DS41211D-page 8 © 2007 Microchip Technology Inc.

PIC12F683 TABLE 2-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0 Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90 01h TMR0 Timer0 Module Register xxxx xxxx 41, 90 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 90 03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 11, 90 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 90 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31, 90 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 90 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 90 0Ch PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 15, 90 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 47, 90 11h TMR2 Timer2 Module Register 0000 0000 49, 90 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 90 13h CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 76, 90 14h CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 76, 90 15h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 75, 90 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 97, 90 19h CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 56, 90 1Ah CMCON1 — — — — — — T1GSS CMSYNC ---- --10 57, 90 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 61,90 1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 65,90 Legend: – = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. © 2007 Microchip Technology Inc. DS41211D-page 9

PIC12F683 TABLE 2-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOR Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12, 90 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 90 83h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 11, 90 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 90 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 32, 90 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 90 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 90 8Ch PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 14, 90 8Dh — Unimplemented — — 8Eh PCON — — ULPWUE SBOREN — — POR BOR --01 --qq 16, 90 8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(2) HTS LTS SCS -110 x000 20, 90 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 24, 90 91h — Unimplemented — — 92h PR2 Timer2 Module Period Register 1111 1111 49, 90 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU(3) — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 34, 90 96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 90 97h — Unimplemented — — 98h — Unimplemented — — 99h VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 58, 90 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 71, 90 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 71, 90 9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 72, 91 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 72, 91 9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 66, 91 9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 33, 91 Legend: – = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: OSTS bit of the OSCCON register reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator. 3: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. DS41211D-page 10 © 2007 Microchip Technology Inc.

PIC12F683 2.2.2.1 STATUS Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register2-1, contains: as 000u u1uu (where u = unchanged). (cid:129) Arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, (cid:129) Reset status SWAPF and MOVWF instructions are used to alter the (cid:129) Bank select bits for data memory (SRAM) STATUS register, because these instructions do not The STATUS register can be the destination for any affect any Status bits. For other instructions not affect- instruction, like any other register. If the STATUS ing any Status bits, see the “Instruction Set Summary”. register is the destination for an instruction that affects Note1: Bits IRP and RP1 of the STATUS register the Z, DC or C bits, then the write to these three bits is are not used by the PIC12F683 and disabled. These bits are set or cleared according to the should be maintained as clear. Use of device logic. Furthermore, the TO and PD bits are not these bits is not recommended, since this writable. Therefore, the result of an instruction with the may affect upward compatibility with STATUS register as destination may be different than future products. intended. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. REGISTER 2-1: STATUS: STATUS REGISTER Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h–FFh) 0 = Bank 0 (00h–7Fh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2007 Microchip Technology Inc. DS41211D-page 11

PIC12F683 2.2.2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for The OPTION register is a readable and writable Timer0, assign the prescaler to the WDT register, which contains various control bits to by setting PSA bit of the OPTION register configure: to ‘1’ See Section5.1.3 “Software Pro- (cid:129) TMR0/WDT prescaler grammable Prescaler”. (cid:129) External GP2/INT interrupt (cid:129) TMR0 (cid:129) Weak pull-ups on GPIO REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE TIMER0 RATE WDT RATE 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Note 1: A dedicated 16-bit WDT postscaler is available. See Section12.6 “Watchdog Timer (WDT)” for more information. DS41211D-page 12 © 2007 Microchip Technology Inc.

PIC12F683 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON register is a readable and writable condition occurs, regardless of the state of register, which contains the various enable and flag bits its corresponding enable bit or the global for TMR0 register overflow, GPIO change and external enable bit, GIE of the INTCON register. GP2/INT pin interrupts. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GIE PEIE T0IE INTE GPIE T0IF INTF GPIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt bit 3 GPIE: GPIO Change Interrupt Enable bit(1) 1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow bit 1 INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur bit 0 GPIF: GPIO Change Interrupt Flag bit 1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software) 0 = None of the GPIO <5:0> pins have changed state Note 1: IOC register must also be enabled. 2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. © 2007 Microchip Technology Inc. DS41211D-page 13

PIC12F683 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be shown in Register2-4. set to enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 4 Unimplemented: Read as ‘0’ bit 3 CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt bit 2 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt DS41211D-page 14 © 2007 Microchip Technology Inc.

PIC12F683 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register2-5. condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started bit 6 ADIF: A/D Interrupt Flag bit 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started bit 5 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit 1 = Comparator 1 output has changed (must be cleared in software) 0 = Comparator 1 output has not changed bit 2 OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed © 2007 Microchip Technology Inc. DS41211D-page 15

PIC12F683 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits (see Table12-2) to differentiate between a: (cid:129) Power-on Reset (POR ) (cid:129) Brown-out Reset (BOR ) (cid:129) Watchdog Timer Reset (WDT) (cid:129) External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR. The PCON register bits are shown in Register2-6. REGISTER 2-6: PCON: POWER CONTROL REGISTER U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x — — ULPWUE SBOREN — — POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-Up Enable bit 1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled bit 4 SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) Note 1: Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR. DS41211D-page 16 © 2007 Microchip Technology Inc.

PIC12F683 2.3 PCL and PCLATH The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth The Program Counter (PC) is 13 bits wide. The low byte push overwrites the value that was stored from the first comes from the PCL register, which is a readable and push. The tenth push overwrites the second push (and writable register. The high byte (PC<12:8>) is not so on). directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure2-3 shows the Note1: There are no Status bits to indicate stack overflow or stack underflow conditions. two situations for the loading of the PC. The upper example in Figure2-3 shows how the PC is loaded on a 2: There are no instructions/mnemonics write to PCL (PCLATH<4:0> → PCH). The lower exam- called PUSH or POP. These are actions ple in Figure2-3 shows how the PC is loaded during a that occur from the execution of the CALL or GOTO instruction (PCLATH<4:3> → PCH). CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an FIGURE 2-3: LOADING OF PC IN interrupt address. DIFFERENT SITUATIONS 2.4 Indirect Addressing, INDF and PCH PCL Instruction with FSR Registers 12 8 7 0 PCL as PC Destination The INDF register is not a physical register. Addressing PCLATH<4:0> 8 the INDF register will cause indirect addressing. 5 ALU Result Indirect addressing is possible by using the INDF register. Any instruction using the INDF register PCLATH actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will PCH PCL produce 00h. Writing to the INDF register indirectly 12 11 10 8 7 0 results in a no operation (although Status bits may be PC GOTO, CALL affected). An effective 9-bit address is obtained by PCLATH<4:3> 11 concatenating the 8-bit FSR register and the IRP bit of 2 OPCODE<10:0> the STATUS register, as shown in Figure2-4. PCLATH A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example2-1. 2.3.1 COMPUTED GOTO EXAMPLE 2-1: INDIRECT ADDRESSING A computed GOTO is accomplished by adding an offset MOVLW 0x20 ;initialize pointer to the program counter (ADDWF PCL). When perform- MOVWF FSR ;to RAM ing a table read using a computed GOTO method, care NEXT CLRF INDF ;clear INDF register should be exercised if the table location crosses a PCL INCF FSR ;inc pointer memory boundary (each 256-byte block). Refer to the BTFSS FSR,4 ;all done? Application Note AN556, “Implementing a Table Read” GOTO NEXT ;no clear next (DS00556). CONTINUE ;yes continue 2.3.2 STACK The PIC12F683 family has an 8-levelx13-bit wide hardware stack (see Figure2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. © 2007 Microchip Technology Inc. DS41211D-page 17

PIC12F683 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F683 Direct Addressing Indirect Addressing RP1(1) RP0 6 From Opcode 0 IRP(1) 7 File Select Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h Data Not Used Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figure2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. DS41211D-page 18 © 2007 Microchip Technology Inc.

PIC12F683 3.0 OSCILLATOR MODULE (WITH The Oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. EC – External clock with I/O on OSC2/CLKOUT. 3.1 Overview 2. LP – 32kHz Low-Power Crystal mode. 3. XT – Medium Gain Crystal or Ceramic The Oscillator module has a wide variety of clock Resonator Oscillator mode. sources and selection features that allow it to be used 4. HS – High Gain Crystal or Ceramic Resonator in a wide range of applications while maximizing perfor- mode. mance and minimizing power consumption. Figure3-1 illustrates a block diagram of the Oscillator module. 5. RC – External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. Clock sources can be configured from external 6. RCIO – External Resistor-Capacitor (RC) with oscillators, quartz crystal resonators, ceramic resonators I/O on OSC2/CLKOUT. and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two 7. INTOSC – Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. internal oscillators, with a choice of speeds selectable via software. Additional clock features include: 8. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. (cid:129) Selectable system clock source between external or internal via software. Clock Source modes are configured by the FOSC<2:0> (cid:129) Two-Speed Start-up mode, which minimizes bits in the Configuration Word register (CONFIG). The latency between external oscillator start-up and internal clock can be generated from two internal code execution. oscillators. The HFINTOSC is a calibrated high-frequency oscillator. The LFINTOSC is an (cid:129) Fail-Safe Clock Monitor (FSCM) designed to uncalibrated low-frequency oscillator. detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FOSC<2:0> (Configuration Word Register) External Oscillator SCS<0> (OSCCON Register) OSC2 Sleep LP, XT, HS, RC, RCIO, EC OSC1 IRCF<2:0> UX (OSCCON Register) M System Clock (CPU and Peripherals) 8 MHz 111 INTOSC Internal Oscillator 4 MHz 110 2 MHz 101 er 1 MHz HFINTOSC al 100 X 8 MHz stsc 500 kHz 011 MU o P 250 kHz 010 125 kHz 001 LFINTOSC 31 kHz 000 31 kHz Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) © 2007 Microchip Technology Inc. DS41211D-page 19

PIC12F683 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: (cid:129) Frequency selection bits (IRCF) (cid:129) Frequency Status bits (HTS, LTS) (cid:129) System clock control bits (OSTS, SCS) REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0 — IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8MHz 110 = 4MHz (default) 101 = 2MHz 100 = 1MHz 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31kHz (LFINTOSC) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word register 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) bit 2 HTS: HFINTOSC Status bit (High Frequency – 8MHz to 125kHz) 1 = HFINTOSC is stable 0 = HFINTOSC is not stable bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31kHz) 1 = LFINTOSC is stable 0 = LFINTOSC is not stable bit 0 SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the Configuration Word register Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. DS41211D-page 20 © 2007 Microchip Technology Inc.

PIC12F683 3.3 Clock Source Modes 3.4 External Clock Modes Clock Source modes can be classified as external or 3.4.1 OSCILLATOR START-UP TIMER (OST) internal. If the Oscillator module is configured for LP, XT or HS (cid:129) External Clock modes rely on external circuitry for modes, the Oscillator Start-up Timer (OST) counts the clock source. Examples are: Oscillator mod- 1024 oscillations from OSC1. This occurs following a ules (EC mode), quartz crystal resonators or Power-on Reset (POR) and when the Power-up Timer ceramic resonators (LP, XT and HS modes) and (PWRT) has expired (if configured), or a wake-up from Resistor-Capacitor (RC) mode circuits. Sleep. During this time, the program counter does not (cid:129) Internal clock sources are contained internally increment and program execution is suspended. The within the Oscillator module. The Oscillator OST ensures that the oscillator circuit, using a quartz module has two internal oscillators: the 8MHz crystal resonator or ceramic resonator, has started and High-Frequency Internal Oscillator (HFINTOSC) is providing a stable system clock to the Oscillator and the 31kHz Low-Frequency Internal Oscillator module. When switching between clock sources, a (LFINTOSC). delay is required to allow the new clock to stabilize. The system clock can be selected between external or These oscillator delays are shown in Table3-1. internal clock sources via the System Clock Select In order to minimize latency between external oscillator (SCS) bit of the OSCCON register. See Section3.6 start-up and code execution, the Two-Speed Clock “Clock Switching” for additional information. Start-up mode can be selected (see Section3.7 “Two-Speed Clock Start-up Mode”). TABLE 3-1: OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay LFINTOSC 31kHz Sleep/POR Oscillator Warm-Up Delay (TWARM) HFINTOSC 125kHz to 8MHz Sleep/POR EC, RC DC – 20MHz 2 instruction cycles LFINTOSC (31kHz) EC, RC DC – 20MHz 1 cycle of each Sleep/POR LP, XT, HS 32kHz to 20MHz 1024 Clock Cycles (OST) LFINTOSC (31kHz) HFINTOSC 125kHz to 8MHz 1μs (approx.) 3.4.2 EC MODE FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is Clock from OSC1/CLKIN connected to the OSC1 input and the OSC2 is available Ext. System for general purpose I/O. Figure3-2 shows the pin PIC® MCU connections for EC mode. I/O OSC2/CLKOUT(1) The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up Note 1: Alternate pin functions are listed in the from Sleep. Because the PIC® MCU design is fully Device Overview. static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. © 2007 Microchip Technology Inc. DS41211D-page 21

PIC12F683 3.4.3 LP, XT, HS MODES Note 1: Quartz crystal characteristics vary according The LP, XT and HS modes support the use of quartz to type, package and manufacturer. The crystal resonators or ceramic resonators connected to user should consult the manufacturer data OSC1 and OSC2 (Figure3-3). The mode selects a low, sheets for specifications and recommended medium or high gain setting of the internal application. inverter-amplifier to support various resonator types 2: Always verify oscillator performance over and speed. the VDD and temperature range that is LP Oscillator mode selects the lowest gain setting of the expected for the application. internal inverter-amplifier. LP mode current consumption 3: For oscillator design assistance, reference is the least of the three modes. This mode is designed to the following Microchip Applications Notes: drive only 32.768 kHz tuning-fork type crystals (watch crystals). (cid:129)AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® XT Oscillator mode selects the intermediate gain Devices” (DS00826) setting of the internal inverter-amplifier. XT mode (cid:129)AN849, “Basic PIC® Oscillator Design” current consumption is the medium of the three modes. (DS00849) This mode is best suited to drive resonators with a medium drive level specification. (cid:129)AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) HS Oscillator mode selects the highest gain setting of the (cid:129)AN949, “Making Your Oscillator Work” internal inverter-amplifier. HS mode current consumption (DS00949) is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. FIGURE 3-4: CERAMIC RESONATOR Figure3-3 and Figure3-4 show typical circuits for OPERATION quartz crystal and ceramic resonators, respectively. (XT OR HS MODE) FIGURE 3-3: QUARTZ CRYSTAL PIC® MCU OPERATION (LP, XT OR HS MODE) OSC1/CLKIN PIC® MCU C1 To Internal Logic OSC1/CLKIN RP(3) RF(2) Sleep C1 To Internal Logic QCruyasrttazl RF(2) Sleep C2 Ceramic RS(1) OSC2/CLKOUT Resonator Note 1: A series resistor (RS) may be required for C2 RS(1) OSC2/CLKOUT ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode Note 1: A series resistor (RS) may be required for selected (typically between 2MΩ to 10MΩ). quartz crystals with low drive level. 3: An additional parallel feedback resistor (RP) 2: The value of RF varies with the Oscillator mode may be required for proper ceramic resonator selected (typically between 2MΩ to 10MΩ). operation. DS41211D-page 22 © 2007 Microchip Technology Inc.

PIC12F683 3.4.4 EXTERNAL RC MODES 3.5 Internal Clock Modes The external Resistor-Capacitor (RC) modes support The Oscillator module has two independent, internal the use of an external RC circuit. This allows the oscillators that can be configured or selected as the designer maximum flexibility in frequency choice while system clock source. keeping costs to a minimum when clock accuracy is not 1. The HFINTOSC (High-Frequency Internal required. There are two modes: RC and RCIO. Oscillator) is factory calibrated and operates at In RC mode, the RC circuit connects to OSC1. 8MHz. The frequency of the HFINTOSC can be OSC2/CLKOUT outputs the RC oscillator frequency user-adjusted via software using the OSCTUNE divided by 4. This signal may be used to provide a clock register (Register3-2). for external circuitry, synchronization, calibration, test 2. The LFINTOSC (Low-Frequency Internal or other application requirements. Figure3-5 shows Oscillator) is uncalibrated and operates at 31kHz. the external RC mode connections. The system clock speed can be selected via software FIGURE 3-5: EXTERNAL RC MODES using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. VDD PIC® MCU The system clock can be selected between external or internal clock sources via the System Clock Selection REXT (SCS) bit of the OSCCON register. See Section3.6 “Clock Switching” for more information. OSC1/CLKIN Internal Clock 3.5.1 INTOSC AND INTOSCIO MODES CEXT The INTOSC and INTOSCIO modes configure the VSS internal oscillators as the system clock source when FOSC/4 or OSC2/CLKOUT(1) the device is programmed using the oscillator selection I/O(2) or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section12.0 “Special Features of the CPU” for more information. Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V 3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V In INTOSC mode, OSC1/CLKIN is available for general CEXT > 20 pF, 2-5V purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT Note 1: Alternate pin functions are listed in the Device signal may be used to provide a clock for external Overview. circuitry, synchronization, calibration, test or other 2: Output depends upon RC or RCIO clock mode. application requirements. In RCIO mode, the RC circuit is connected to OSC1. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT OSC2 becomes an additional general purpose I/O pin. are available for general purpose I/O. The RC oscillator frequency is a function of the supply 3.5.2 HFINTOSC voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting The High-Frequency Internal Oscillator (HFINTOSC) is the oscillator frequency are: a factory calibrated 8MHz internal clock source. The (cid:129) threshold voltage variation frequency of the HFINTOSC can be altered via (cid:129) component tolerances software using the OSCTUNE register (Register3-2). (cid:129) packaging variations in capacitance The output of the HFINTOSC connects to a postscaler The user also needs to take into account variation due and multiplexer (see Figure3-1). One of seven to tolerance of external RC components used. frequencies can be selected via software using the IRCF<2:0> bits of the OSCCON register. See Section3.5.4 “Frequency Select Bits (IRCF)” for more information. The HFINTOSC is enabled by selecting any frequency between 8MHz and 125kHz by setting the IRCF<2:0> bits of the OSCCON register≠000. Then, set the System Clock Source (SCS) bit of the OSCCON register to ‘1’ or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to ‘1’. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not. © 2007 Microchip Technology Inc. DS41211D-page 23

PIC12F683 3.5.2.1 OSCTUNE Register When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new The HFINTOSC is factory calibrated but can be frequency. Code execution continues during this shift. adjusted in software by writing to the OSCTUNE There is no indication that the shift has occurred. register (Register3-2). OSCTUNE does not affect the LFINTOSC frequency. The default value of the OSCTUNE register is ‘0’. The Operation of features that depend on the LFINTOSC value is a 5-bit two’s complement number. clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = (cid:129) (cid:129) (cid:129) 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = (cid:129) (cid:129) (cid:129) 10000 = Minimum frequency DS41211D-page 24 © 2007 Microchip Technology Inc.

PIC12F683 3.5.3 LFINTOSC 3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31kHz internal clock source. When switching between the LFINTOSC and the The output of the LFINTOSC connects to a postscaler HFINTOSC, the new oscillator may already be shut down to save power (see Figure3-6). If this is the case, and multiplexer (see Figure3-1). Select 31kHz, via software, using the IRCF<2:0> bits of the OSCCON there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency register. See Section3.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows: The LFINTOSC is enabled by selecting 31kHz (IRCF<2:0> bits of the OSCCON register=000) as the 1. IRCF<2:0> bits of the OSCCON register are system clock source (SCS bit of the OSCCON modified. register= 1), or when any of the following are enabled: 2. If the new clock is shut down, a clock start-up delay is started. (cid:129) Two-Speed Start-up IESO bit of the Configuration Word register = 1 and IRCF<2:0> bits of the 3. Clock switch circuitry waits for a falling edge of OSCCON register = 000 the current clock. 4. CLKOUT is held low and the clock switch (cid:129) Power-up Timer (PWRT) circuitry waits for a rising edge in the new clock. (cid:129) Watchdog Timer (WDT) 5. CLKOUT is now connected with the new clock. (cid:129) Fail-Safe Clock Monitor (FSCM) LTS and HTS bits of the OSCCON register are The LF Internal Oscillator (LTS) bit of the OSCCON updated as required. register indicates whether the LFINTOSC is stable or 6. Clock switch is complete. not. See Figure3-1 for more details. 3.5.4 FREQUENCY SELECT BITS (IRCF) If the internal oscillator speed selected is between The output of the 8MHz HFINTOSC and 31kHz 8MHz and 125kHz, there is no start-up delay before LFINTOSC connects to a postscaler and multiplexer the new frequency is selected. This is because the old (see Figure3-1). The Internal Oscillator Frequency and new frequencies are derived from the HFINTOSC Select bits IRCF<2:0> of the OSCCON register select via the postscaler and multiplexer. the frequency output of the internal oscillators. One of Start-up delay specifications are located in the eight frequencies can be selected via software: Electrical Specifications Chapter of this data sheet, (cid:129) 8 MHz under AC Specifications (Oscillator Module). (cid:129) 4 MHz (Default after Reset) (cid:129) 2 MHz (cid:129) 1 MHz (cid:129) 500 kHz (cid:129) 250 kHz (cid:129) 125 kHz (cid:129) 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4MHz. The user can modify the IRCF bits to select a different frequency. © 2007 Microchip Technology Inc. DS41211D-page 25

PIC12F683 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING HF LF(1) HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <2:0> ≠ 0 = 0 System Clock Note 1: When going from LF to HF. HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC ≠ = IRCF <2:0> 0 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <2:0> = 0 ≠ 0 System Clock DS41211D-page 26 © 2007 Microchip Technology Inc.

PIC12F683 3.6 Clock Switching When the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is The system clock source can be switched between enabled (see Section3.4.1 “Oscillator Start-up Timer external and internal clock sources via software using (OST)”). The OST will suspend program execution until the System Clock Select (SCS) bit of the OSCCON 1024 oscillations are counted. Two-Speed Start-up register. mode minimizes the delay in code execution by operating from the internal oscillator as the OST is 3.6.1 SYSTEM CLOCK SELECT (SCS) BIT counting. When the OST count reaches 1024 and the The System Clock Select (SCS) bit of the OSCCON OSTS bit of the OSCCON register is set, program register selects the system clock source that is used for execution switches to the external oscillator. the CPU and peripherals. 3.7.1 TWO-SPEED START-UP MODE (cid:129) When the SCS bit of the OSCCON register = 0, CONFIGURATION the system clock source is determined by configuration of the FOSC<2:0> bits in the Two-Speed Start-up mode is configured by the Configuration Word register (CONFIG). following settings: (cid:129) When the SCS bit of the OSCCON register = 1, (cid:129) IESO (of the Configuration Word register) = 1; the system clock source is chosen by the internal Internal/External Switchover bit (Two-Speed oscillator frequency selected by the IRCF<2:0> Start-up mode enabled). bits of the OSCCON register. After a Reset, the (cid:129) SCS (of the OSCCON register) = 0. SCS bit of the OSCCON register is always (cid:129) FOSC<2:0> bits in the Configuration Word cleared. register (CONFIG) configured for LP, XT or HS Note: Any automatic clock switch, which may mode. occur from Two-Speed Start-up or Fail-Safe Two-Speed Start-up mode is entered after: Clock Monitor, does not update the SCS bit of the OSCCON register. The user can (cid:129) Power-on Reset (POR) and, if enabled, after monitor the OSTS bit of the OSCCON Power-up Timer (PWRT) has expired, or register to determine the current system (cid:129) Wake-up from Sleep. clock source. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then 3.6.2 OSCILLATOR START-UP TIME-OUT Two-Speed Start-up is disabled. This is because the STATUS (OSTS) BIT external clock oscillator does not require any The Oscillator Start-up Time-out Status (OSTS) bit of stabilization time after POR or an exit from Sleep. the OSCCON register indicates whether the system clock is running from the external clock source, as 3.7.2 TWO-SPEED START-UP defined by the FOSC<2:0> bits in the Configuration SEQUENCE Word register (CONFIG), or from the internal clock 1. Wake-up from Power-on Reset or Sleep. source. In particular, OSTS indicates that the Oscillator 2. Instructions begin execution by the internal Start-up Timer (OST) has timed out for LP, XT or HS oscillator at the frequency set in the IRCF<2:0> modes. bits of the OSCCON register. 3.7 Two-Speed Clock Start-up Mode 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the Two-Speed Start-up mode provides additional power internal oscillator. savings by minimizing the latency between external 5. OSTS is set. oscillator start-up and code execution. In applications 6. System clock held low until the next falling edge that make heavy use of the Sleep mode, Two-Speed of new clock (LP, XT or HS mode). Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the 7. System clock is switched to external clock overall power consumption of the device. source. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. © 2007 Microchip Technology Inc. DS41211D-page 27

PIC12F683 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock DS41211D-page 28 © 2007 Microchip Technology Inc.

PIC12F683 3.8 Fail-Safe Clock Monitor 3.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset, to continue operating should the external oscillator fail. executing a SLEEP instruction or toggling the SCS bit The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bit is toggled, the Oscillator Start-up Timer (OST) has expired. The the OST is restarted. While the OST is running, the FSCM is enabled by setting the FCMEN bit in the device continues to operate from the INTOSC selected Configuration Word register (CONFIG). The FSCM is in OSCCON. When the OST times out, the Fail-Safe applicable to all external oscillator modes (LP, XT, HS, condition is cleared and the device will be operating EC, RC and RCIO). from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. FIGURE 3-8: FSCM BLOCK DIAGRAM 3.8.4 RESET OR WAKE-UP FROM SLEEP Clock Monitor The FSCM is designed to detect an oscillator failure Latch after the Oscillator Start-up Timer (OST) has expired. External S Q The OST is used after waking up from Sleep and after Clock any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as LFINTOSC soon as the Reset or wake-up has completed. When Oscillator ÷ 64 R Q the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing 31 kHz 488 Hz code while the OST is operating. (~32 μs) (~2 ms) Note: Due to the wide range of oscillator start-up Sample Clock Clock times, the Fail-Safe circuit is not active Failure during oscillator start-up (i.e., after exiting Detected Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify 3.8.1 FAIL-SAFE DETECTION the oscillator start-up and that the system The FSCM module detects a failed oscillator by clock switchover has successfully comparing the external oscillator to the FSCM sample completed. clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure3-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the primary clock goes low. 3.8.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR1 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE1 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2007 Microchip Technology Inc. DS41211D-page 29

PIC12F683 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets(1) CONFIG(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000 OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register12-1) for operation of all register bits. DS41211D-page 30 © 2007 Microchip Technology Inc.

PIC12F683 4.0 GPIO PORT Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the There are as many as six general purpose I/O pins PORT data latch. GP3 reads ‘0’ when MCLRE = 1. available. Depending on which peripherals are The TRISIO register controls the direction of the GPIO enabled, some or all of the pins may not be available as pins, even when they are being used as analog inputs. general purpose I/O. In general, when a peripheral is The user must ensure the bits in the TRISIO register enabled, the associated pin may not be used as a are maintained set when using them as analog inputs. general purpose I/O pin. I/O pins configured as analog input always read ‘0’. 4.1 GPIO and the TRISIO Registers Note: The ANSEL and CMCON0 registers must be initialized to configure an analog GPIO is a 6-bit wide, bidirectional port. The channel as a digital input. Pins configured corresponding data direction register is TRISIO. as analog inputs will read ‘0’. Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., put the corresponding output EXAMPLE 4-1: INITIALIZING GPIO driver in a High-Impedance mode). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an BANKSEL GPIO ; output (i.e., put the contents of the output latch on the CLRF GPIO ;Init GPIO MOVLW 07h ;Set GP<2:0> to selected pin). An exception is GP3, which is input only MOVWF CMCON0 ;digital I/O and its TRISIO bit will always read as ‘1’. Example4-1 BANKSEL ANSEL ; shows how to initialize GPIO. CLRF ANSEL ;digital I/O Reading the GPIO register reads the status of the pins, MOVLW 0Ch ;Set GP<3:2> as inputs whereas writing to it will write to the PORT latch. All MOVWF TRISIO ;and set GP<5:4,1:0> write operations are read-modify-write operations. ;as outputs REGISTER 4-1: GPIO: GENERAL PURPOSE I/O REGISTER U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0 — — GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GP<5:0>: GPIO I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL © 2007 Microchip Technology Inc. DS41211D-page 31

PIC12F683 REGISTER 4-2: TRISIO GPIO TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISIO5(2,3) TRISIO4(2) TRISIO3(1) TRISIO2 TRISIO1 TRISIO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5:4 TRISIO<5:4>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output bit 3 TRISIO<3>: GPIO Tri-State Control bit Input only bit 2:0 TRISIO<2:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output Note 1: TRISIO<3> always reads ‘1’. 2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP OSC modes. 3: TRISIO<5> always reads ‘1’ in RC and RCIO and EC modes. 4.2 Additional Pin Functions 4.2.3 INTERRUPT-ON-CHANGE Every GPIO pin on the PIC12F683 has an Each of the GPIO pins is individually configurable as an interrupt-on-change option and a weak pull-up option. interrupt-on-change pin. Control bits IOCx enable or GP0 has an Ultra Low-Power Wake-up option. The disable the interrupt function for each pin. Refer to next three sections describe these functions. Register4-5. The interrupt-on-change is disabled on a Power-on Reset. 4.2.1 ANSEL REGISTER For enabled interrupt-on-change pins, the values are The ANSEL register is used to configure the Input compared with the old value latched on the last read of mode of an I/O pin to analog. Setting the appropriate GPIO. The ‘mismatch’ outputs of the last read are OR’d ANSEL bit high will cause all digital reads on the pin to together to set the GPIO Change Interrupt Flag bit be read as ‘0’ and allow analog functions on the pin to (GPIF) in the INTCON register (Register2-3). operate correctly. This interrupt can wake the device from Sleep. The The state of the ANSEL bits has no affect on digital user, in the Interrupt Service Routine, clears the output functions. A pin with TRIS clear and ANSEL set interrupt by: will still operate as a digital output, but the Input mode a) Any read or write of GPIO. This will end the will be analog. This can cause unexpected behavior mismatch condition, then, when executing read-modify-write instructions on the b) Clear the flag bit GPIF. affected port. A mismatch condition will continue to set flag bit GPIF. 4.2.2 WEAK PULL-UPS Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The latch holding the Each of the GPIO pins, except GP3, has an individually last read value is not affected by a MCLR nor configurable internal weak pull-up. Control bits WPUx Brown-out Reset. After these resets, the GPIF flag will enable or disable each pull-up. Refer to Register4-4. continue to be set if a mismatch is present. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are Note: If a change on the I/O pin should occur disabled on a Power-on Reset by the GPPU bit of the when any GPIO operation is being OPTION register). A weak pull-up is automatically executed, then the GPIF interrupt flag may enabled for GP3 when configured as MCLR and not getset. disabled when GP3 is an I/O. There is no software control of the MCLR pull-up. DS41211D-page 32 © 2007 Microchip Technology Inc.

PIC12F683 REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 bit 3-0 ANS<3:0>: Analog Select bits Analog select between analog or digital function on pins AN<3:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. © 2007 Microchip Technology Inc. DS41211D-page 33

PIC12F683 REGISTER 4-4: WPU: WEAK PULL-UP REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPU5 WPU4 — WPU2 WPU1 WPU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPU<2:0>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global GPPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). 3: The GP3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word. 4: WPU<5:4> always reads ‘1’ in XT, HS and LP OSC modes. REGISTER 4-5: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOC<5:0>: Interrupt-on-change GPIO Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOC<5:4> always reads ‘0’ in XT, HS and LP OSC modes. DS41211D-page 34 © 2007 Microchip Technology Inc.

PIC12F683 4.2.4 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on GP0 Note: For more information, refer to the Applica- allows a slow falling voltage to generate an inter- tion Note AN879, “Using the Microchip rupt-on-change on GP0 without excess current con- Ultra Low-Power Wake-up Module” sumption. The mode is selected by setting the (DS00879). ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a EXAMPLE 4-2: ULTRA LOW-POWER capacitor on GP0. WAKE-UP INITIALIZATION To use this feature, the GP0 pin is configured to output BANKSEL CMCON0 ; ‘1’ to charge the capacitor, interrupt-on-change for GP0 MOVLW H’7’ ;Turn off is enabled and GP0 is configured as an input. The ULP- MOVWF CMCON0 ;comparators WUE bit is set to begin the discharge and a SLEEP BANKSEL ANSEL ; instruction is performed. When the voltage on GP0 BCF ANSEL,0 ;RA0 to digital I/O drops below VIL, an interrupt will be generated which will BCF TRISA,0 ;Output high to cause the device to wake-up. Depending on the state of BANKSEL PORTA ; the GIE bit of the INTCON register, the device will either BSF PORTA,0 ;charge capacitor jump to the interrupt vector (0004h) or execute the next CALL CapDelay ; BANKSEL PCON ; instruction when the interrupt event occurs. See BSF PCON,ULPWUE ;Enable ULP Wake-up Section4.2.3 “Interrupt-on-Change” and BSF IOCA,0 ;Select RA0 IOC Section12.4.3 “GPIO Interrupt” for more information. BSF TRISA,0 ;RA0 to input This feature provides a low-power technique for period- MOVLW B’10001000’ ;Enable interrupt ically waking up the device from Sleep. The time-out is MOVWF INTCON ; and clear flag dependent on the discharge time of the RC circuit SLEEP ;Wait for IOC NOP ; onGP0. See Example4-2 for initializing the Ultra Low-Power Wake-up module. The series resistor provides overcurrent protection for the GP0 pin and can allow for software calibration of the time-out (see Figure4-1). A timer can be used to mea- sure the charge time and discharge time of the capaci- tor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor. © 2007 Microchip Technology Inc. DS41211D-page 35

PIC12F683 4.2.5 PIN DESCRIPTIONS AND 4.2.5.1 GP0/AN0/CIN+/ICSPDAT/ULPWU DIAGRAMS Figure4-1 shows the diagram for this pin. The GP0 pin Each GPIO pin is multiplexed with other functions. The is configurable to function as one of the following: pins and their combined functions are briefly described (cid:129) a general purpose I/O here. For specific information about individual functions (cid:129) an analog input for the ADC such as the comparator or the ADC, refer to the (cid:129) an analog input to the comparator appropriate section in this data sheet. (cid:129) In-Circuit Serial Programming™ data (cid:129) an analog input to the Ultra Low-Power Wake-up FIGURE 4-1: BLOCK DIAGRAM OF GP0 Analog Input Mode(1) VDD Data Bus D Q Weak WR CK Q WPU GPPU RD WPU VDD D Q WR CK I/O pin Q GPIO VSS - + VT D Q TRISWIOR CK Q IULP 0 1 RD TRISIO Analog VSS Input Mode(1) ULPWUE RD GPIO D Q Q D WR CK Q IOC EN Q3 RD IOC Q D EN Interrupt-on- Change RD GPIO To Comparator To A/D Converter Note 1: Comparator mode and ANSEL determines Analog Input mode. DS41211D-page 36 © 2007 Microchip Technology Inc.

PIC12F683 4.2.5.2 GP1/AN1/CIN-/VREF/ICSPCLK 4.2.5.3 GP2/AN2/T0CKI/INT/COUT/CCP1 Figure4-2 shows the diagram for this pin. The GP1 pin Figure4-3 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: is configurable to function as one of the following: (cid:129) a general purpose I/O (cid:129) a general purpose I/O (cid:129) an analog input for the ADC (cid:129) an analog input for the ADC (cid:129) a analog input to the comparator (cid:129) the clock input for Timer0 (cid:129) a voltage reference input for the ADC (cid:129) an external edge triggered interrupt (cid:129) In-Circuit Serial Programming clock (cid:129) a digital output from the Comparator (cid:129) a digital input/output for the CCP (refer to FIGURE 4-2: BLOCK DIAGRAM OF GP1 Section11.0 “Capture/Compare/PWM (CCP) Module”). Analog DBautas Input Mode(1) FIGURE 4-3: BLOCK DIAGRAM OF GP2 D Q VDD WWPRU CK Q Weak DBautas InpAunta Mloogde D Q VDD RD GPPU WPU WWPRU CK Q Weak RD GPPU D Q VDD WPU Analog WR CK COUT Input GPIO Q Enable Mode VDD D Q I/O pin D Q WR CK GPIO Q COUT 1 WR CK TRISIO Q VSS 0 I/O pin Analog D Q RD Input Mode(1) TRISIO WR CK TRISIO Q VSS Analog RD GPIO RD Input Mode TRISIO D Q Q D WR CK Q RD IOC GPIO EN Q3 D Q RD IOC Q D WR CK Q D Q IOC EN EN Q3 Interrupt-on- RD change IOC Q D RD GPIO EN Interrupt-on- To Comparator change To A/D Converter RD GPIO Note 1: Comparator mode and ANSEL determines Analog To Timer0 Input mode. To INT To A/D Converter Note 1: Comparator mode and ANSEL determines Analog Input mode. © 2007 Microchip Technology Inc. DS41211D-page 37

PIC12F683 4.2.5.4 GP3/MCLR/VPP 4.2.5.5 GP4/AN3/T1G/OSC2/CLKOUT Figure4-4 shows the diagram for this pin. The GP3 pin Figure4-5 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: is configurable to function as one of the following: (cid:129) a general purpose input (cid:129) a general purpose I/O (cid:129) as Master Clear Reset with weak pull-up (cid:129) an analog input for the ADC (cid:129) a Timer1 gate input FIGURE 4-4: BLOCK DIAGRAM OF GP3 (cid:129) a crystal/resonator connection (cid:129) a clock output VDD MCLRE Weak FIGURE 4-5: BLOCK DIAGRAM OF GP4 Data Analog Bus MCLRE Reset Input Input Mode CLK(1) pin Data Modes TRISRIOD VSS Bus D Q VDD RD MCLRE VSS WWPUR CK Q Weak GPIO D Q RD GPPU WPU WR CK Q D Oscillator IOC Q Circuit OSC1 EN Q3 CLKOUT VDD RD Enable IOC Q D FOSC/4 1 D Q EN Intechrraunpgt-eon- GPWIOR CK Q 0 I/O pin CLKOUT RD GPIO Enable VSS D Q INTOSC/ WR CK RC/EC(2) TRISIO Q CLKOUT RD Enable TRISIO Analog Input Mode RD GPIO D Q Q D WR CK Q IOC EN Q3 RD IOC Q D EN Interrupt-on- change RD GPIO To T1G To A/D Converter Note1: CLK modes are XT, HS, LP, optional LP oscillator and CLKOUT Enable. 2: With CLKOUT option. DS41211D-page 38 © 2007 Microchip Technology Inc.

PIC12F683 4.2.5.6 GP5/T1CKI/OSC1/CLKIN FIGURE 4-6: BLOCK DIAGRAM OF GP5 Figure4-6 shows the diagram for this pin. The GP5 pin INTOSC Mode is configurable to function as one of the following: Data TMR1LPEN(1) (cid:129) a general purpose I/O Bus D Q VDD (cid:129) a Timer1 clock input WR CK Weak Q (cid:129) a crystal/resonator connection WPU (cid:129) a clock input GPPU RD WPU Oscillator Circuit OSC2 VDD D Q WR CK GPIO Q I/O pin D Q WR CK TRISIO Q VSS INTOSC RD Mode TRISIO (1) RD GPIO D Q Q D WR CK Q IOC EN Q3 RD IOC Q D EN Interrupt-on- change RD GPIO To Timer1 or CLKGEN Note 1: Timer1 LP oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed. TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --x0 x000 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 --11 -111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO. © 2007 Microchip Technology Inc. DS41211D-page 39

PIC12F683 NOTES: DS41211D-page 40 © 2007 Microchip Technology Inc.

PIC12F683 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used following features: as either an 8-bit timer or an 8-bit counter. (cid:129) 8-bit timer/counter register (TMR0) 5.1.1 8-BIT TIMER MODE (cid:129) 8-bit prescaler (shared with Watchdog Timer) When used as a timer, the Timer0 module will (cid:129) Programmable internal or external clock source increment every instruction cycle (without prescaler). (cid:129) Programmable external clock edge selection Timer mode is selected by clearing the T0CS bit of the (cid:129) Interrupt on overflow OPTION register to ‘0’. Figure5-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. 5.1.2 8-BIT COUNTER MODE When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER FOSC/4 Data Bus 0 8 1 Sync 1 TMR0 2 Tcy T0CKI 0 pin 0 T0SE T0CS 8-bit Set Flag bit T0IF on Overflow Prescaler PSA 1 8 WDTE PSA SWDTEN 1 PS<2:0> WDT 16-bit Time-out 0 Prescaler 16 31kHz Watchdog INTOSC Timer PSA WDTPS<3:0> Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. DS41211D-page 41

PIC12F683 5.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the PRESCALER WDT to the Timer0 module, the following instruction sequence must be executed (see Example5-2). A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer EXAMPLE 5-2: CHANGING PRESCALER (WDT), but not both simultaneously. The prescaler (WDT→TIMER0) assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and must be cleared to a ‘0’. ;prescaler BANKSEL OPTION_REG ; There are 8 prescaler options for the Timer0 module MOVLW b’11110000’ ;Mask TMR0 select and ranging from 1:2 to 1:256. The prescale values are ANDWF OPTION_REG,W ;prescaler bits selectable via the PS<2:0> bits of the OPTION register. IORLW b’00000011’ ;Set prescale to 1:16 In order to have a 1:1 prescaler value for the Timer0 MOVWF OPTION_REG ; module, the prescaler must be assigned to the WDT module. 5.1.4 TIMER0 INTERRUPT The prescaler is not readable or writable. When Timer0 will generate an interrupt when the TMR0 assigned to the Timer0 module, all instructions writing to register overflows from FFh to 00h. The T0IF interrupt the TMR0 register will clear the prescaler. flag bit of the INTCON register is set every time the When the prescaler is assigned to WDT, a CLRWDT TMR0 register overflows, regardless of whether or not instruction will clear the prescaler along with the WDT. the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the 5.1.3.1 Switching Prescaler Between T0IE bit of the INTCON register. Timer0 and WDT Modules Note: The Timer0 interrupt cannot wake the As a result of having the prescaler assigned to either processor from Sleep since the timer is Timer0 or the WDT, it is possible to generate an frozen during Sleep. unintended device Reset when switching prescaler values. When changing the prescaler assignment from 5.1.5 USING TIMER0 WITH AN Timer0 to the WDT module, the instruction sequence EXTERNAL CLOCK shown in Example5-1, must be executed. When Timer0 is in Counter mode, the synchronization EXAMPLE 5-1: CHANGING PRESCALER of the T0CKI input and the Timer0 register is accom- (TIMER0→WDT) plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the BANKSEL TMR0 ; high and low periods of the external clock source must CLRWDT ;Clear WDT meet the timing requirements as shown in the CLRF TMR0 ;Clear TMR0 and Section15.0 “Electrical Specifications”. ;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ; ; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32 DS41211D-page 42 © 2007 Microchip Technology Inc.

PIC12F683 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits BIT VALUE TIMER0 RATE WDT RATE 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Note 1: A dedicated 16-bit WDT postscaler is available. See Section12.6 “Watchdog Timer (WDT)” for more information. TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. DS41211D-page 43

PIC12F683 6.0 TIMER1 MODULE WITH GATE 6.1 Timer1 Operation CONTROL The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register The Timer1 module is a 16-bit timer/counter with the pair. Writes to TMR1H or TMR1L directly update the following features: counter. (cid:129) 16-bit timer/counter register pair (TMR1H:TMR1L) When used with an internal clock source, the module is (cid:129) Programmable internal or external clock source a timer. When used with an external clock source, the (cid:129) 3-bit prescaler module can be used as either a timer or counter. (cid:129) Optional LP oscillator (cid:129) Synchronous or asynchronous operation 6.2 Clock Source Selection (cid:129) Timer1 gate (count enable) via comparator or The TMR1CS bit of the T1CON register is used to select T1G pin the clock source. When TMR1CS = 0, the clock source (cid:129) Interrupt on overflow is FOSC/4. When TMR1CS = 1, the clock source is (cid:129) Wake-up on overflow (external clock, supplied externally. Asynchronous mode only) (cid:129) Special Event Trigger (with CCP) Clock Source TMR1CS (cid:129) Comparator output synchronization to Timer1 FOSC/4 0 clock T1CKI pin 1 Figure6-1 is a block diagram of the Timer1 module. FIGURE 6-1: TIMER1 BLOCK DIAGRAM TMR1GE T1GINV TMR1ON Set flag bit TMR1IF on To Comparator Module Overflow TMR1(2) Timer1 Clock Synchronized EN 0 clock input TMR1H TMR1L 1 Oscillator (1) T1SYNC OSC1/T1CKI 1 Prescaler Synchronize(3) FOSC/4 1, 2, 4, 8 det Internal 0 OSC2/T1G Clock 2 T1CKPS<1:0> TMR1CS 1 INTOSC Without CLKOUT COUT 0 T1OSCEN T1GSS Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. DS41211D-page 44 © 2007 Microchip Technology Inc.

PIC12F683 6.2.1 INTERNAL CLOCK SOURCE 6.5 Timer1 Operation in Asynchronous Counter Mode When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples If control bit T1SYNC of the T1CON register is set, the of TCY as determined by the Timer1 prescaler. external clock input is not synchronized. The timer continues to increment asynchronous to the internal 6.2.2 EXTERNAL CLOCK SOURCE phase clocks. The timer will continue to run during When the external clock source is selected, the Timer1 Sleep and can generate an interrupt on overflow, module may work as a timer or a counter. which will wake-up the processor. However, special When counting, Timer1 is incremented on the rising precautions in software are needed to read/write the edge of the external clock input T1CKI. In addition, the timer (see Section6.5.1 “Reading and Writing Counter mode clock can be synchronized to the Timer1 in Asynchronous Counter Mode”). microcontroller system clock or run asynchronously. Note: When switching from synchronous to If an external clock oscillator is needed (and the asynchronous operation, it is possible to microcontroller is using the INTOSC without CLKOUT), skip an increment. When switching from Timer1 can use the LP oscillator as a clock source. asynchronous to synchronous operation, it is possible to produce a single spurious Note: In Counter mode, a falling edge must be increment. registered by the counter prior to the first incrementing rising edge. 6.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER 6.3 Timer1 Prescaler MODE Timer1 has four prescaler options allowing 1, 2, 4 or 8 Reading TMR1H or TMR1L while the timer is running divisions of the clock input. The T1CKPS bits of the from an external asynchronous clock will ensure a valid T1CON register control the prescale counter. The read (taken care of in hardware). However, the user prescale counter is not directly readable or writable; should keep in mind that reading the 16-bit timer in two however, the prescaler counter is cleared upon a write to 8-bit values itself, poses certain problems, since the TMR1H or TMR1L. timer may overflow between the reads. For writes, it is recommended that the user simply stop 6.4 Timer1 Oscillator the timer and write the desired values. A write contention may occur by writing to the timer registers, A low-power 32.768 kHz crystal oscillator is built-in while the register is incrementing. This may produce an between pins OSC1 (input) and OSC2 (amplifier unpredictable value in the TMR1H:TTMR1L register output). The oscillator is enabled by setting the pair. T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. 6.6 Timer1 Gate The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when Timer1 gate source is software configurable to be the the primary system clock is derived from the internal T1G pin or the output of the Comparator. This allows the oscillator or when in LP oscillator mode. The user must device to directly time external events using T1G or provide a software time delay to ensure proper oscilla- analog events using Comparator 2. See the CMCON1 tor start-up. register (Register8-2) for selecting the Timer1 gate source. This feature can simplify the software for a TRISIO<5:4> bits are set when the Timer1 oscillator is enabled. GP5 and GP4 bits read as ‘0’ and TRISIO5 Delta-Sigma A/D converter and many other applications. and TRISIO4 bits read as ‘1’. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Note: The oscillator requires a start-up and stabilization time before use. Thus, Note: TMR1GE bit of the T1CON register must T1OSCEN should be set and a suitable be set to use either T1G or COUT as the Timer1 gate source. See Register8-2 for delay observed prior to enabling Timer1. more information on selecting the Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events. © 2007 Microchip Technology Inc. DS41211D-page 45

PIC12F683 6.7 Timer1 Interrupt 6.9 CCP Special Event Trigger The Timer1 register pair (TMR1H:TMR1L) increments If a CCP is configured to trigger a special event, the to FFFFh and rolls over to 0000h. When Timer1 rolls trigger will clear the TMR1H:TMR1L register pair. This over, the Timer1 interrupt flag bit of the PIR1 register is special event does not cause a Timer1 interrupt. The set. To enable the interrupt on rollover, you must set CCP module may still be configured to generate a CCP these bits: interrupt. (cid:129) Timer1 interrupt enable bit of the PIE1 register In this mode of operation, the CCPR1H:CCPR1L regis- (cid:129) PEIE bit of the INTCON register ter pair effectively becomes the period register for Timer1. (cid:129) GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger. Asynchronous operation of the Interrupt Service Routine. Timer1 can cause a Special Event Trigger to be Note: The TMR1H:TTMR1L register pair and the missed. TMR1IF bit should be cleared before In the event that a write to TMR1H or TMR1L coincides enabling interrupts. with a Special Event Trigger from the CCP, the write will take precedence. 6.8 Timer1 Operation During Sleep For more information, see Section on CCP. Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external 6.10 Comparator Synchronization crystal or clock source can be used to increment the counter. To set up the timer to wake the device: The same clock used to increment Timer1 can also be used to synchronize the comparator output. This (cid:129) TMR1ON bit of the T1CON register must be set feature is enabled in the Comparator module. (cid:129) TMR1IE bit of the PIE1 register must be set When using the comparator for Timer1 gate, the (cid:129) PEIE bit of the INTCON register must be set comparator output should be synchronized to Timer1. The device will wake-up on an overflow and execute This ensures Timer1 does not miss an increment if the the next instruction. If the GIE bit of the INTCON comparator changes. register is set, the device will call the Interrupt Service For more information, see Section8.0 “Comparator Routine (0004h). Module”. FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS41211D-page 46 © 2007 Microchip Technology Inc.

PIC12F683 6.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 6 TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is not active 0 = Timer1 is on bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. LP oscillator is disabled. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register, as a Timer1 gate source. © 2007 Microchip Technology Inc. DS41211D-page 47

PIC12F683 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CONFIG(1) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: See Configuration Word register (Register12-1) for operation of all register bits. DS41211D-page 48 © 2007 Microchip Technology Inc.

PIC12F683 7.0 TIMER2 MODULE The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to The Timer2 module is an 8-bit timer with the following 00h and the PR2 register is set to FFh. features: Timer2 is turned on by setting the TMR2ON bit in the (cid:129) 8-bit timer register (TMR2) T2CON register to a ‘1’. Timer2 is turned off by clearing (cid:129) 8-bit period register (PR2) the TMR2ON bit to a ‘0’. (cid:129) Interrupt on TMR2 match with PR2 The Timer2 prescaler is controlled by the T2CKPS bits (cid:129) Software programmable prescaler (1:1, 1:4, 1:16) in the T2CON register. The Timer2 postscaler is (cid:129) Software programmable postscaler (1:1 to 1:16) controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared See Figure7-1 for a block diagram of Timer2. when: 7.1 Timer2 Operation (cid:129) A write to TMR2 occurs. (cid:129) A write to T2CON occurs. The clock input to the Timer2 module is the system (cid:129) Any device Reset occurs (Power-on Reset, MCLR instruction clock (FOSC/4). The clock is fed into the Reset, Watchdog Timer Reset, or Brown-out Timer2 prescaler, which has prescale options of 1:1, Reset). 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. Note: TMR2 is not cleared when T2CON is written. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: (cid:129) TMR2 is reset to 00h on the next increment cycle. (cid:129) The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. FIGURE 7-1: TIMER2 BLOCK DIAGRAM Sets Flag TMR2 bit TMR2IF Output Prescaler Reset FOSC/4 TMR2 1:1, 1:4, 1:16 2 Comparator Postscaler EQ 1:1 to 1:16 T2CKPS<1:0> PR2 4 TOUTPS<3:0> © 2007 Microchip Technology Inc. DS41211D-page 49

PIC12F683 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 =Prescaler is 1 01 =Prescaler is 4 1x =Prescaler is 16 TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2 REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. DS41211D-page 50 © 2007 Microchip Technology Inc.

PIC12F683 8.0 COMPARATOR MODULE FIGURE 8-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output VIN- – The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. The analog comparator module includes the following features: (cid:129) Multiple comparator configurations VIN- VIN+ (cid:129) Comparator output is available internally/externally (cid:129) Programmable output polarity (cid:129) Interrupt-on-change (cid:129) Wake-up from Sleep Output (cid:129) Timer1 gate (count enable) (cid:129) Output synchronization to Timer1 clock input (cid:129) Programmable voltage reference Note: The black areas of the output of the 8.1 Comparator Overview comparator represents the uncertainty due to input offsets and response time. The comparator is shown in Figure8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. FIGURE 8-2: COMPARATOR OUTPUT BLOCK DIAGRAM CMSYNC To Timer1 Gate M CINV P U ort P LTIP 0 To COUT pin in L s E D Q 1 X Timer1 clock source(1) To Data Bus D Q Q1 EN RD CMCON0 Set CMIF bit D Q Q3*RD CMCON0 EN CL Reset Note 1: Comparator output is latched on falling edge of Timer1 clock source. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. © 2007 Microchip Technology Inc. DS41211D-page 51

PIC12F683 8.2 Analog Input Connection Considerations Note1: When reading a PORT register, all pins configured as analog inputs will read as a A simplified circuit for an analog input is shown in ‘0’. Pins configured as digital inputs will Figure8-3. Since the analog input pins share their con- convert as an analog input, according to nection with a digital input, they have reverse biased the input specification. ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the 2: Analog levels on any pin defined as a input voltage deviates from this range by more than digital input, may cause the input buffer to 0.6V in either direction, one of the diodes is forward consume more current than is specified. biased and a latch-up may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. FIGURE 8-3: ANALOG INPUT MODEL VDD Rs < 10K VT ≈ 0.6V RIC To ADC Input AIN VA C5 PpIFN VT ≈ 0.6V I±L5E0A0K AnGAE Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage DS41211D-page 52 © 2007 Microchip Technology Inc.

PIC12F683 8.3 Comparator Configuration The port pins denoted as “A” will read as a ‘0’ regardless of the state of the I/O pin or the I/O control There are eight modes of operation for the comparator. TRIS bit. Pins used as analog inputs should also have The CM<2:0> bits of the CMCON0 register are used to the corresponding TRIS bit set to ‘1’ to disable the select these modes as shown in Figure8-4. digital output driver. Pins denoted as “D” should have (cid:129) Analog function (A): digital input buffer is disabled the corresponding TRIS bit set to ‘0’ to enable the (cid:129) Digital function (D): comparator digital output, digital output driver. overrides port function Note: Comparator interrupts should be disabled (cid:129) Normal port function (I/O): independent of com- during a Comparator mode change to parator prevent unintended interrupts. FIGURE 8-4: COMPARATOR I/O OPERATING MODES Comparator Reset (POR Default Value – low power) Comparator w/o Output and with Internal Reference CM<2:0> = 000 CM<2:0> = 100 CIN- A CIN- A CIN+ A Off(1) CIN+ I/O COUT COUT (pin) I/O COUT (pin) I/O From CVREF Module Comparator with Output Multiplexed Input with Internal Reference and Output CM<2:0> = 001 CM<2:0> = 101 A CIN- A CIN- CIS = 0 CIN+ A COUT CIN+ A CIS = 1 COUT COUT (pin) D COUT (pin) D From CVREF Module Comparator without Output Multiplexed Input with Internal Reference CM<2:0> = 010 CM<2:0> = 110 A CIN- A CIN- CIS = 0 CIN+ A COUT CIN+ A CIS = 1 COUT I/O COUT (pin) I/O COUT (pin) From CVREF Module Comparator with Output and Internal Reference Comparator Off (Lowest power) CM<2:0> = 011 CM<2:0> = 111 CIN- A CIN- I/O COUT CIN+ I/O Off(1) CIN+ I/O COUT (pin) D COUT (pin) I/O From CVREF Module Legend: A = Analog Input, ports always reads ‘0’ CIS = Comparator Input Switch (CMCON0<3>) I/O = Normal port I/O D = Comparator Digital Output Note 1: Reads as ‘0’, unless CINV = 1. © 2007 Microchip Technology Inc. DS41211D-page 53

PIC12F683 8.4 Comparator Control 8.5 Comparator Response Time The CMCON0 register (Register8-1) provides access The comparator output is indeterminate for a period of to the following comparator features: time after the change of an input source or the selection of a new reference voltage. This period is referred to as (cid:129) Mode selection the response time. The response time of the (cid:129) Output state comparator differs from the settling time of the voltage (cid:129) Output polarity reference. Therefore, both of these times must be (cid:129) Input switch considered when determining the total response time to a comparator input change. See the Comparator and 8.4.1 COMPARATOR OUTPUT STATE Voltage Reference Specifications in Section15.0 The Comparator state can always be read internally via “Electrical Specifications” for more details. the COUT bit of the CMCON0 register. The comparator state may also be directed to the COUT pin in the following modes: (cid:129) CM<2:0> = 001 (cid:129) CM<2:0> = 011 (cid:129) CM<2:0> = 101 When one of the above modes is selected, the associ- ated TRIS bit of the COUT pin must be cleared. 8.4.2 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CINV bit of the CMCON0 register. Clearing CINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table8-1. TABLE 8-1: OUTPUT STATE VS. INPUT CONDITIONS Input Conditions CINV COUT VIN- > VIN+ 0 0 VIN- < VIN+ 0 1 VIN- > VIN+ 1 1 VIN- < VIN+ 1 0 Note: COUT refers to both the register bit and output pin. 8.4.3 COMPARATOR INPUT SWITCH The inverting input of the comparator may be switched between two analog pins in the following modes: (cid:129) CM<2:0> = 101 (cid:129) CM<2:0> = 110 In the above modes, both pins remain in analog mode regardless of which pin is selected as the input. The CIS bit of the CMCON0 register controls the comparator input switch. DS41211D-page 54 © 2007 Microchip Technology Inc.

PIC12F683 8.6 Comparator Interrupt Operation FIGURE 8-5: COMPARATOR INTERRUPT TIMING W/O The comparator interrupt flag is set whenever there is CMCON0 READ a change in the output value of the comparator. Changes are recognized by means of a mismatch cir- Q1 cuit which consists of two latches and an exclusive-or Q3 gate (see Figure8.2). One latch is updated with the CIN+ TRT comparator output level when the CMCON0 register is COUT read. This latch retains the value until the next read of Set CMIF (level) the CMCON0 register or the occurrence of a Reset. CMIF The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch condition will occur reset by software when a comparator output change is clocked through the second latch on the Q1 clock cycle. The mismatch FIGURE 8-6: COMPARATOR condition will persist, holding the CMIF bit of the PIR1 INTERRUPT TIMING WITH register true, until either the CMCON0 register is read CMCON0 READ or the comparator output returns to the previous state. Q1 Note: A write operation to the CMCON0 register will also clear the mismatch condition Q3 because all writes include a read CIN+ TRT operation at the beginning of the write COUT cycle. Set CMIF (level) Software will need to maintain information about the CMIF status of the comparator output to determine the actual cleared by CMCON0 read reset by software change that has occurred. The CMIF bit of the PIR1 register, is the comparator interrupt flag. This bit must be reset in software by Note1: If a change in the CMCON0 register clearing it to ‘0’. Since it is also possible to write a ‘1’ to (COUT) should occur when a read opera- this register, a simulated interrupt may be initiated. tion is being executed (start of the Q2 The CMIE bit of the PIE1 register and the PEIE and GIE cycle), then the CMIF of the PIR1 register bits of the INTCON register must all be set to enable interrupt flag may not get set. comparator interrupts. If any of these bits are cleared, 2: When either comparator is first enabled, the interrupt is not enabled, although the CMIF bit of bias circuitry in the Comparator module the PIR1 register will still be set if an interrupt condition may cause an invalid output from the occurs. comparator until the bias circuitry is The user, in the Interrupt Service Routine, can clear the stable. Allow about 1 μs for bias settling interrupt in the following manner: then clear the mismatch condition and interrupt flags before enabling comparator a) Any read or write of CMCON0. This will end the interrupts. mismatch condition. b) Clear the CMIF interrupt flag. A persistent mismatch condition will preclude clearing the CMIF interrupt flag. Reading CMCON0 will end the mismatch condition and allow the CMIF bit to be cleared. Note: If a change in the CMCON0 register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF interrupt flag may not get set. © 2007 Microchip Technology Inc. DS41211D-page 55

PIC12F683 8.7 Operation During Sleep 8.8 Effects of a Reset The comparator, if enabled before entering Sleep mode, A device Reset forces the CMCON0 and CMCON1 remains active during Sleep. The additional current registers to their Reset states. This forces the Compar- consumed by the comparator is shown separately in ator module to be in the Comparator Reset mode Section15.0 “Electrical Specifications”. If the (CM<2:0>=000). Thus, all comparator inputs are comparator is not used to wake the device, power analog inputs with the comparator disabled to consume consumption can be minimized while in Sleep mode by the smallest current possible. turning off the comparator. The comparator is turned off by selecting mode CM<2:0>=000 or CM<2:0>=111 of the CMCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CMIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. REGISTER 8-1: CMCON0: COMPARATOR CONFIGURATION REGISTER U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — COUT — CINV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 COUT: Comparator Output bit When CINV = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CINV = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 5 Unimplemented: Read as ‘0’ bit 4 CINV: Comparator Output Inversion bit 1 = Output inverted 0 = Output not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110 or 101: 1 = CIN+ connects to VIN- 0 = CIN- connects to VIN- When CM<2:0> = 0xx or 100 or 111: CIS has no effect. bit 2-0 CM<2:0>: Comparator Mode bits (See Figure8-5) 000 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off 001 = CIN pins are configured as analog, COUT pin configured as Comparator output 010 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally 011 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin configured as Comparator output, CVREF is non-inverting input 100 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comparator output available internally, CVREF is non-inverting input 101 = CIN pins are configured as analog and multiplexed, COUT pin is configured as Comparator output, CVREF is non-inverting input 110 = CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O, Comparator output available internally, CVREF is non-inverting input 111 = CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off. DS41211D-page 56 © 2007 Microchip Technology Inc.

PIC12F683 8.9 Comparator Gating Timer1 8.10 Synchronizing Comparator Output to Timer1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the The comparator output can be synchronized with CMCON1 register will enable Timer1 to increment Timer1 by setting the CMSYNC bit of the CMCON1 based on the output of the comparator. This requires register. When enabled, the comparator output is that Timer1 is on and gating is enabled. See latched on the falling edge of the Timer1 clock source. Section6.0 “Timer1 Module with Gate Control” for If a prescaler is used with Timer1, the comparator details. output is latched after the prescaling function. To It is recommended to synchronize the comparator with prevent a race condition, the comparator output is Timer1 by setting the CMSYNC bit when the latched on the falling edge of the Timer1 clock source comparator is used as the Timer1 gate source. This and Timer1 increments on the rising edge of its clock ensures Timer1 does not miss an increment if the source. See the Comparator Block Diagram (Figure8- comparator changes during an increment. 2) and the Timer1 Block Diagram (Figure6-1) for more information. REGISTER 8-2: CMCON1: COMPARATOR CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 — — — — — — T1GSS CMSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Timer 1 Gate Source is comparator output bit 0 CMSYNC: Comparator Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section6.6 “Timer1 Gate”. 2: Refer to Figure8-2. © 2007 Microchip Technology Inc. DS41211D-page 57

PIC12F683 8.11 Comparator Voltage Reference EQUATION 8-1: CVREF OUTPUT VOLTAGE The Comparator Voltage Reference module provides VRR = 1 (low range): an internally generated voltage reference for the CVREF = (VR<3:0>/24)×VDD comparators. The following features are available: VRR = 0 (high range): (cid:129) Independent from Comparator operation CVREF = (VDD/4) + (VR<3:0>×VDD/32) (cid:129) Two 16-level voltage ranges (cid:129) Output clamped to V SS The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure8-1. (cid:129) Ratiometric with V DD The VRCON register (Register8-3) controls the 8.11.3 OUTPUT CLAMPED TO VSS Voltage Reference module shown in Figure8-7. The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: 8.11.1 INDEPENDENT OPERATION (cid:129) VREN= 0 The comparator voltage reference is independent of (cid:129) VRR= 1 the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference. (cid:129) VR<3:0>= 0000 This allows the comparator to detect a zero-crossing 8.11.2 OUTPUT VOLTAGE SELECTION while not consuming additional CVREF module current. The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is 8.11.4 OUTPUT RATIOMETRIC TO VDD controlled by the VRR bit of the VRCON register. The The comparator voltage reference is VDD derived and 16 levels are set with the VR<3:0> bits of the VRCON therefore, the CVREF output changes with fluctuations in register. VDD. The tested absolute accuracy of the Comparator The CVREF output voltage is determined by the following Voltage Reference can be found in Section15.0 equations: “Electrical Specifications”. REGISTER 8-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN — VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS. bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR<3:0>: CVREF Value Selection 0 ≤ VR<3:0> ≤ 15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD DS41211D-page 58 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 8-7: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN 15 CVREF to 14 Comparator 2 Input 1 0 VR<3:0>(1) VREN VR<3:0> = 0000 VRR Note 1: Care should be taken to ensure VREF remains within the comparator Common mode input range. See Section15.0 “Electrical Specifications” for more detail. TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 0000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 -0-0 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator. © 2007 Microchip Technology Inc. DS41211D-page 59

PIC12F683 NOTES: DS41211D-page 60 © 2007 Microchip Technology Inc.

PIC12F683 9.0 ANALOG-TO-DIGITAL The ADC voltage reference is software selectable to CONVERTER (ADC) MODULE either VDD or a voltage applied to the external reference pins. The Analog-to-Digital Converter (ADC) allows The ADC can generate an interrupt upon completion of conversion of an analog input signal to a 10-bit binary a conversion. This interrupt can be used to wake-up the representation of that signal. This device uses analog device from Sleep. inputs, which are multiplexed into a single sample and Figure9-1 shows the block diagram of the ADC. hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). FIGURE 9-1: ADC BLOCK DIAGRAM VDD VCFG = 0 VREF VCFG = 1 GP0/AN0 GP1/AN1/VREF A/D GP2/AN2 GP4/AN3 GO/DONE 10 0 = Left Justify ADFM CHS 1 = Right Justify ADON 10 ADRESH ADRESL 9.1 ADC Configuration 9.1.2 CHANNEL SELECTION When configuring and using the ADC the following The CHS bits of the ADCON0 register determine which functions must be considered: channel is connected to the sample and hold circuit. (cid:129) GPIO configuration When changing channels, a delay is required before starting the next conversion. Refer to Section9.2 (cid:129) Channel selection “ADC Operation” for more information. (cid:129) ADC voltage reference selection (cid:129) ADC conversion clock source (cid:129) Interrupt control (cid:129) Results formatting 9.1.1 GPIO CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding GPIO section for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. © 2007 Microchip Technology Inc. DS41211D-page 61

PIC12F683 9.1.3 ADC VOLTAGE REFERENCE The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods The VCFG bit of the ADCON0 register provides control as shown in Figure9-2. of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage For correct conversion, the appropriate TAD specification source. The negative voltage reference is always must be met. See A/D conversion requirements in connected to the ground reference. Section15.0 “Electrical Specifications” for more information. Table9-1 gives examples of appropriate 9.1.4 CONVERSION CLOCK ADC clock selections. The source of the conversion clock is software select- Note: Unless using the FRC, any changes in the able via the ADCS bits of the ANSEL register. There system clock frequency will change the are seven possible clock options: ADC clock frequency, which may (cid:129) F OSC/2 adversely affect the ADC result. (cid:129) F OSC/4 (cid:129) F OSC/8 (cid:129) F OSC/16 (cid:129) F OSC/32 (cid:129) F OSC/64 (cid:129) F RC (dedicated internal oscillator) TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 μs FOSC/4 100 200 ns(2) 500 ns(2) 1.0 μs(2) 4.0 μs FOSC/8 001 400 ns(2) 1.0 μs(2) 2.0 μs 8.0 μs(3) FOSC/16 101 800 ns(2) 2.0 μs 4.0 μs 16.0 μs(3) FOSC/32 010 1.6 μs 4.0 μs 8.0 μs(3) 32.0 μs(3) FOSC/64 110 3.2 μs 8.0 μs(3) 16.0 μs(3) 64.0 μs(3) FRC x11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY to TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding Capacitor is Disconnected from Analog Input (typically 100 ns) Set GO/DONE bit ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input DS41211D-page 62 © 2007 Microchip Technology Inc.

PIC12F683 9.1.5 INTERRUPTS 9.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit A/D conversion result can be supplied in two interrupt upon completion of an Analog-to-Digital formats, left justified or right justified. The ADFM bit of conversion. The ADC interrupt flag is the ADIF bit in the the ADCON0 register controls the output format. PIR1 register. The ADC interrupt enable is the ADIE bit Figure9-3 shows the two output formats. in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the interrupt service routine. Please see Section12.4 “Interrupts” for more information. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result 9.2 ADC Operation 9.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, 9.2.1 STARTING A CONVERSION the GO/DONE bit can be cleared in software. The To enable the ADC module, the ADON bit of the ADRESH:ADRESL registers will not be updated with ADCON0 register must be set to a ‘1’. Setting the the partially complete Analog-to-Digital conversion GO/DONE bit of the ADCON0 register to a ‘1’ will start sample. Instead, the ADRESH:ADRESL register pair the Analog-to-Digital conversion. will retain the value of the previous conversion. Addi- tionally, a 2TAD delay is required before another acqui- Note: The GO/DONE bit should not be set in the sition can be initiated. Following this delay, an input same instruction that turns on the ADC. acquisition is automatically started on the selected Refer to Section9.2.6 “A/D Conversion channel. Procedure”. Note: A device Reset forces all registers to their 9.2.2 COMPLETION OF A CONVERSION Reset state. Thus, the ADC module is turned off and any pending conversion is When the conversion is complete, the ADC module will: terminated. (cid:129) Clear the GO/DONE bit (cid:129) Set the ADIF flag bit (cid:129) Update the ADRESH:ADRESL registers with new conversion result © 2007 Microchip Technology Inc. DS41211D-page 63

PIC12F683 9.2.4 ADC OPERATION DURING SLEEP 8. Clear the ADC interrupt flag (required if interrupt is enabled). The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the Note1: The global interrupt can be disabled if the ADC waits one additional instruction before starting the user is attempting to wake-up from Sleep conversion. This allows the SLEEP instruction to be and resume in-line code execution. executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device 2: See Section9.3 “A/D Acquisition will wake-up from Sleep when the conversion Requirements”. completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, EXAMPLE 9-1: A/D CONVERSION although the ADON bit remains set. ;This code block configures the ADC When the ADC clock source is something other than ;for polling, Vdd reference, Frc clock FRC, a SLEEP instruction causes the present conver- ;and GP0 input. sion to be aborted and the ADC module is turned off, ; although the ADON bit remains set. ;Conversion start & polling for completion ; are included. 9.2.5 SPECIAL EVENT TRIGGER ; BANKSEL TRISIO ; The CCP Special Event Trigger allows periodic ADC BSF TRISIO,0 ;Set GP0 to input measurements without software intervention. When BANKSEL ANSEL ; this trigger occurs, the GO/DONE bit is set by hardware MOVLW B’01110001’ ;ADC Frc clock, and the Timer1 counter resets to zero. IORWF ANSEL ; and GP0 as analog BANKSEL ADCON0 ; Using the Special Event Trigger does not assure proper MOVLW B’10000001’ ;Right justify, ADC timing. It is the user’s responsibility to ensure that MOVWF ADCON0 ;Vdd Vref, AN0, On the ADC timing requirements are met. CALL SampleTime ;Acquisiton delay See Section11.0 “Capture/Compare/PWM (CCP) BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? Module” for more information. GOTO $-1 ;No, test again BANKSEL ADRESH ; 9.2.6 A/D CONVERSION PROCEDURE MOVF ADRESH,W ;Read upper 2 bits This is an example procedure for using the ADC to MOVWF RESULTHI ;Store in GPR space perform an Analog-to-Digital conversion: BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits 1. Configure GPIO Port: MOVWF RESULTLO ;Store in GPR space (cid:129) Disable pin output driver (See TRIS register) (cid:129) Configure pin as analog 9.2.7 ADC REGISTER DEFINITIONS 2. Configure the ADC module: The following registers are used to control the (cid:129) Select ADC conversion clock operation of the ADC. (cid:129) Configure voltage reference (cid:129) Select ADC input channel (cid:129) Select result format (cid:129) Turn on ADC module 3. Configure ADC interrupt (optional): (cid:129) Clear ADC interrupt flag (cid:129) Enable ADC interrupt (cid:129) Enable peripheral interrupt (cid:129) Enable global interrupt (1) 4. Wait the required acquisition time(2). 5. Start conversion by setting the GO/DONE bit. 6. Wait for ADC conversion to complete by one of the following: (cid:129) Polling the GO/DONE bit (cid:129) Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result DS41211D-page 64 © 2007 Microchip Technology Inc.

PIC12F683 REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CHS<1:0>: Analog Channel Select bits 00 = AN0 01 = AN1 10 = AN2 11 = AN3 bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current © 2007 Microchip Technology Inc. DS41211D-page 65

PIC12F683 REGISTER 9-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-3: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 9-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 9-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result DS41211D-page 66 © 2007 Microchip Technology Inc.

PIC12F683 9.3 A/D Acquisition Requirements an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition For the ADC to meet its specified accuracy, the charge time, Equation9-1 may be used. This equation holding capacitor (CHOLD) must be allowed to fully assumes that 1/2 LSb error is used (1024 steps for the charge to the input channel voltage level. The Analog ADC). The 1/2 LSb error is the maximum error allowed Input model is shown in Figure9-4. The source for the ADC to meet its specified resolution. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure9-4. The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), EQUATION 9-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10kΩ 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+[(Temperature - 25°C)(0.05µs/°C)] The value for TC can be approximated with the following equations: ⎛ 1 ⎞ VAPPLIED⎝1– 2---0---4---7---⎠ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb ⎛ –----T---C---⎞ VAPPLIED⎜1–eRC⎟ = VCHOLD ;[2] VCHOLD charge response to VAPPLIED ⎝ ⎠ –Tc ⎛ -R----C----⎞ ⎛ 1 ⎞ VAPPLIED⎜1–e ⎟ = VAPPLIED⎝1– 2---0---4---7---⎠ ;combining [1] and [2] ⎝ ⎠ Solving for TC: TC = –CHOLD(RIC+RSS+RS) ln(1/2047) = –10pF(1kΩ+7kΩ+10kΩ) ln(0.0004885) = 1.37µs Therefore: TACQ = 2µS+1.37µS+[(50°C- 25°C)(0.05µS/°C)] = 4.67µS Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10kΩ. This is required to meet the pin leakage specification. © 2007 Microchip Technology Inc. DS41211D-page 67

PIC12F683 FIGURE 9-4: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS Rss VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE CHOLD = 10 pF VSS/VREF- 6V 5V RSS Legend: CPIN = Input Capacitance VDD4V VT = Threshold Voltage 3V 2V I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance 5 6 7 891011 SS = Sampling Switch Sampling Switch CHOLD = Sample/Hold Capacitance (kΩ) FIGURE 9-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh de 3FCh 1 LSB ideal o C 3FBh ut p ut Full-Scale O C 004h Transition D A 003h 002h 001h 000h Analog Input Voltage 1 LSB ideal VSS/VREF- Zero-Scale VDD/VREF+ Transition DS41211D-page 68 © 2007 Microchip Technology Inc.

PIC12F683 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets ADCON0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 0000 0000 ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 0000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. © 2007 Microchip Technology Inc. DS41211D-page 69

PIC12F683 NOTES: DS41211D-page 70 © 2007 Microchip Technology Inc.

PIC12F683 10.0 DATA EEPROM MEMORY The EEPROM data memory allows byte read and write. A byte write automatically erases the location and The EEPROM data memory is readable and writable writes the new data (erase before write). The EEPROM during normal operation (full VDD range). This memory data memory is rated for high erase/write cycles. The is not directly mapped in the register file space. write time is controlled by an on-chip timer. The write Instead, it is indirectly addressed through the Special time will vary with voltage and temperature as well as Function Registers. There are four SFRs used to read from chip-to-chip. Please refer to AC Specifications in and write this memory: Section15.0 “Electrical Specifications” for exact (cid:129) EECON1 limits. (cid:129) EECON2 (not a physically implemented register) When the data memory is code-protected, the CPU (cid:129) EEDAT may continue to read and write the data EEPROM memory. The device programmer can no longer access (cid:129) EEADR the data EEPROM data and will read zeroes. EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC12F683 has 256 bytes of data EEPROM with an address range from 0h to FFh. REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEDATn: Byte Value to Write To or Read From Data EEPROM bits REGISTER 10-2: EEADR: EEPROM ADDRESS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits © 2007 Microchip Technology Inc. DS41211D-page 71

PIC12F683 10.1 EECON1 and EECON2 Registers operation. In these situations, following Reset, the user can check the WRERR bit, clear it and rewrite the EECON1 is the control register with four low-order bits location. The data and address will be cleared. physically implemented. The upper four bits are non- Therefore, the EEDAT and EEADRregisters will need implemented and read as ‘0’s. to be re-initialized. Control bits RD and WR initiate read and write, Interrupt flag, EEIF bit of the PIR1 register, is set when respectively. These bits cannot be cleared, only set in write is complete. This bit must be cleared in software. software. They are cleared in hardware at completion EECON2 is not a physical register. Reading EECON2 of the read or write operation. The inability to clear the will read all ‘0’s. The EECON2 register is used WR bit in software prevents the accidental, premature exclusively in the data EEPROM write sequence. termination of a write operation. Note: The EECON1, EEDAT and EEADR The WREN bit, when set, will allow a write operation. registers should not be modified during a On power-up, the WREN bit is clear. The WRERR bit is data EEPROM write (WR bit = 1). set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal REGISTER 10-3: EECON1: EEPROM CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 — — — — WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an EEPROM read DS41211D-page 72 © 2007 Microchip Technology Inc.

PIC12F683 10.2 Reading the EEPROM Data After a write sequence has been initiated, clearing the Memory WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. To read a data memory location, the user must write the At the completion of the write cycle, the WR bit is address to the EEADR register and then set control bit cleared in hardware and the EE Write Complete RD of the EECON1 register, as shown in Example10-1. Interrupt Flag bit (EEIF) is set. The user can either The data is available, at the very next cycle, in the enable this interrupt or poll this bit. The EEIF bit of the EEDAT register. Therefore, it can be read in the next PIR1 register must be cleared by software. instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation). 10.4 Write Verify EXAMPLE 10-1: DATA EEPROM READ Depending on the application, good programming practice may dictate that the value written to the data BANKSEL EEADR ; EEPROM should be verified (see Example10-3) to the MOVLW CONFIG_ADDR; MOVWF EEADR ;Address to read desired value to be written. BSF EECON1,RD ;EE Read MOVF EEDAT,W ;Move data to W EXAMPLE 10-3: WRITE VERIFY BANKSELEEDAT ; 10.3 Writing to the EEPROM Data MOVF EEDAT,W ;EEDAT not changed Memory ;from previous write BSF EECON1,RD ;YES, Read the To write an EEPROM data location, the user must first ;value written write the address to the EEADR register and the data XORWF EEDAT,W to the EEDAT register. Then the user must follow a BTFSS STATUS,Z ;Is data the same GOTO WRITE_ERR ;No, handle error specific sequence to initiate the write for each byte, as : ;Yes, continue shown in Example10-2. EXAMPLE 10-2: DATA EEPROM WRITE 10.4.1 USING THE DATA EEPROM BANKSEL EECON1 ; The data EEPROM is a high-endurance, byte BSF EECON1,WREN ;Enable write addressable array that has been optimized for the BCF INTCON,GIE ;Disable INTs storage of frequently changing information (e.g., BTFSC INTCON,GIE ;See AN576 program variables or other data that are updated often). GOTO $-2 ; When variables in one section change frequently, while MOVLW 55h ;Unlock write RequiredSequence MMMOOOVVVWLWFWF EAEEAEChCOONN22 ;;; vtEoaE rPieaxRbclOeesMe di n ( sathpneeo cthitfoeictraa slt ieoncnut iomDnb1 de2or4 )n oowft ictwhhroaitunetg eecx,y cicte lieses dp iontosgs ittbhhleee BSF EECON1,WR ;Start the write total number of write cycles to a single byte BSF INTCON,GIE ;Enable INTS (specifications D120 and D120A). If this is the case, then a refresh of the array must be performed. For this The write will not initiate if the above sequence is not reason, variables that change infrequently (such as exactly followed (write 55h to EECON2, write AAh to constants, IDs, calibration, etc.) should be stored in EECON2, then set WR bit) for each byte. We strongly Flash program memory. recommend that interrupts be disabled during this codesegment. A cycle count is executed during the required sequence. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared byhardware. © 2007 Microchip Technology Inc. DS41211D-page 73

PIC12F683 10.5 Protection Against Spurious Write 10.6 Data EEPROM Operation During Code-Protect There are conditions when the user may not want to write to the data EEPROM memory. To protect against Data memory can be code-protected by programming spurious EEPROM writes, various mechanisms have the CPD bit in the Configuration Word register been built in. On power-up, WREN is cleared. Also, the (Register12-1) to ‘0’. Power-up Timer (64ms duration) prevents When the data memory is code-protected, the CPU is EEPROMwrite. able to read and write data to the data EEPROM. It is The write initiate sequence and the WREN bit together recommended to code-protect the program memory help prevent an accidental write during: when code-protecting data memory. This prevents (cid:129) Brown-out anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added (cid:129) Power Glitch routine, programmed in unused program memory, (cid:129) Software Malfunction which outputs the contents of data memory. Programming unused locations in program memory to ‘0’ will also help prevent data memory code protection from becoming breached. TABLE 10-1: SUMMARY OF ASSOCIATED DATA EEPROM REGISTERS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000 EECON2(1) EEPROM Control Register 2 ---- ---- ---- ---- Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the Data EEPROM module. Note 1: EECON2 is not a physical register. DS41211D-page 74 © 2007 Microchip Technology Inc.

PIC12F683 11.0 CAPTURE/COMPARE/PWM Additional information on CCP modules is available in (CCP) MODULE the Application Note AN594, “Using the CCP Modules” (DS00594). The Capture/Compare/PWM module is a peripheral which allows the user to time and control different TABLE 11-1: CCP MODE – TIMER events. In Capture mode, the peripheral allows the RESOURCES REQUIRED timing of the duration of an event.The Compare mode CCP Mode Timer Resource allows the user to trigger an external event when a predetermined amount of time has expired. The PWM Capture Timer1 mode can generate a Pulse-Width Modulated signal of Compare Timer1 varying frequency and duty cycle. PWM Timer2 The timer resources used by the module are shown in Table11-1 REGISTER 11-1: CCP1CON: CCP1 CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP module) 0001 = Unused (reserved) 0010 = Unused (reserved) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCP1 pin is unaffected.) 110x = PWM mode active-high 111x = PWM mode active-low © 2007 Microchip Technology Inc. DS41211D-page 75

PIC12F683 11.1 Capture Mode 11.1.2 TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the Timer1 must be running in Timer mode or Synchronized 16-bit value of the TMR1 register when an event occurs Counter mode for the CCP module to use the capture on pin CCP1. An event is defined as one of the feature. In Asynchronous Counter mode, the capture following and is configured by the CCP1M<3:0> bits of operation may not work. the CCP1CON register: 11.1.3 SOFTWARE INTERRUPT (cid:129) Every falling edge When the Capture mode is changed, a false capture (cid:129) Every rising edge interrupt may be generated. The user should keep the (cid:129) Every 4th rising edge CCP1IE interrupt enable bit of the PIE1 register clear to (cid:129) Every 16th rising edge avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag following any change in operating mode. must be cleared in software. If another capture occurs 11.1.4 CCP PRESCALER before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new There are four prescaler settings specified by the captured value (see Figure11-1). CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP 11.1.1 CCP1 PIN CONFIGURATION module is not in Capture mode, the prescaler counter In Capture mode, the CCP1 pin should be configured is cleared. Any Reset will clear the prescaler counter. as an input by setting the associated TRIS control bit. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To Note: If the CCP1 pin is configured as an output, avoid this unexpected operation, turn the module off by a write to the GPIO port can cause a clearing the CCP1CON register before changing the capture condition. prescaler (see Example11-1). FIGURE 11-1: CAPTURE MODE EXAMPLE 11-1: CHANGING BETWEEN OPERATION BLOCK CAPTURE PRESCALERS DIAGRAM BANKSELCCP1CON ;Set Bank bits to point Set Flag bit CCP1IF ;to CCP1CON (PIR1 register) Prescaler CLRF CCP1CON ;Turn CCP module off ÷ 1, 4, 16 MOVLW NEW_CAPT_PS;Load the W reg with CCP1 CCPR1H CCPR1L ; the new prescaler pin ; move value and CCP ON and Capture MOVWF CCP1CON ;Load CCP1CON with this Edge Detect Enable ; value TMR1H TMR1L CCP1CON<3:0> System Clock (FOSC) DS41211D-page 76 © 2007 Microchip Technology Inc.

PIC12F683 11.2 Compare Mode 11.2.2 TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is In Compare mode, Timer1 must be running in either constantly compared against the TMR1 register pair Timer mode or Synchronized Counter mode. The value. When a match occurs, the CCP1 module may: compare operation may not work in Asynchronous Counter mode. (cid:129) Toggle the CCP1 output. (cid:129) Set the CCP1 output. 11.2.3 SOFTWARE INTERRUPT MODE (cid:129) Clear the CCP1 output. When Generate Software Interrupt mode is chosen (cid:129) Generate a Special Event Trigger. (CCP1M<3:0>=1010), the CCP1 module does not (cid:129) Generate a Software Interrupt. assert control of the CCP1 pin (see the CCP1CON register). The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. 11.2.4 SPECIAL EVENT TRIGGER All Compare modes can generate an interrupt. When Special Event Trigger mode is chosen (CCP1M<3:0>=1011), the CCP1 module does the FIGURE 11-2: COMPARE MODE following: OPERATION BLOCK (cid:129) Resets Timer1 DIAGRAM (cid:129) Starts an ADC conversion if ADC is enabled CCP1CON<3:0> Mode Select The CCP1 module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). Set CCP1IF Interrupt Flag The Special Event Trigger output of the CCP occurs (PIR1) CCP1 4 immediately upon a match between the TMR1H, Pin CCPR1H CCPR1L TMR1L register pair and the CCPR1H, CCPR1L Q S register pair. The TMR1H, TMR1L register pair is not Output Comparator R Logic Match reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to TMR1H TMR1L TRIS effectively provide a 16-bit programmable period Output Enable register for Timer1. Special Event Trigger Note1: The Special Event Trigger from the CCP Special Event Trigger will: module does not set interrupt flag bit (cid:129) Clear TMR1H and TMR1L registers. TMRxIF of the PIR1 register. (cid:129) NOT set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by (cid:129) Set the GO/DONE bit to start the ADC conversion. changing the contents of the CCPR1H and CCPR1L register pair, between the 11.2.1 CCP1 PIN CONFIGURATION clock edge that generates the Special Event Trigger and the clock edge that The user must configure the CCP1 pin as an output by generates the Timer1 Reset, will preclude clearing the associated TRIS bit. the Reset from occurring. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the GPIO I/O data latch. © 2007 Microchip Technology Inc. DS41211D-page 77

PIC12F683 11.3 PWM Mode The PWM output (Figure11-4) has a time base (period) and a time that the output stays high (duty The PWM mode generates a Pulse-Width Modulated cycle). signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: FIGURE 11-4: CCP PWM OUTPUT (cid:129) PR2 (cid:129) T2CON Period (cid:129) CCPR1L Pulse Width (cid:129) CCP1CON TMR2 = PR2 In Pulse-Width Modulation (PWM) mode, the CCP TMR2 = CCPR1L:CCP1CON<5:4> module produces up to a 10-bit resolution PWM output TMR2 = 0 on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCP1 pin output driver. Note: Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin. Figure11-1 shows a simplified block diagram of PWM operation. Figure11-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section11.3.7 “Setup for PWM Operation”. FIGURE 11-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H(2) (Slave) CCP1 Pin Comparator R Q S TMR2 (1) TRIS Comparator Clear Timer2, toggle CCP1 pin and latch duty cycle PR2 Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. 2: In PWM mode, CCPR1H is a read-only register. DS41211D-page 78 © 2007 Microchip Technology Inc.

PIC12F683 11.3.1 PWM PERIOD EQUATION 11-2: PULSE WIDTH The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the Pulse Width = (CCPR1L:CCP1CON<5:4>) • formula of Equation11-1. TOSC • (TMR2 Prescale Value) EQUATION 11-1: PWM PERIOD EQUATION 11-3: DUTY CYCLE RATIO PWM Period = [(PR2)+1]•4•TOSC• (TMR2 Prescale Value) (CCPR1L:CCP1CON<5:4>) Duty Cycle Ratio = ----------------------------------------------------------------------- 4(PR2+1) When TMR2 is equal to PR2, the following three events occur on the next increment cycle: The CCPR1H register and a 2-bit internal latch are (cid:129) TMR2 is cleared used to double buffer the PWM duty cycle. This double (cid:129) The CCP1 pin is set. (Exception: If the PWM duty buffering is essential for glitchless PWM operation. cycle=0%, the pin will not be set.) The 8-bit timer TMR2 register is concatenated with (cid:129) The PWM duty cycle is latched from CCPR1L into either the 2-bit internal system clock (FOSC), or 2 bits of CCPR1H. the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. Note: The Timer2 postscaler (see Section7.0 When the 10-bit time base matches the CCPR1H and 2- “Timer2 Module”) is not used in the bit latch, then the CCP1 pin is cleared (see Figure11-1). determination of the PWM frequency. 11.3.3 PWM RESOLUTION 11.3.2 PWM DUTY CYCLE The resolution determines the number of available duty The PWM duty cycle is specified by writing a 10-bit cycles for a given period. For example, a 10-bit resolution value to multiple registers: CCPR1L register and will result in 1024 discrete duty cycles, whereas an 8-bit DC1B<1:0> bits of the CCP1CON register. The resolution will result in 256 discrete duty cycles. CCPR1L contains the eight MSbs and the CCP1<1:0> The maximum PWM resolution is 10 bits when PR2 is bits of the CCP1CON register contain the two LSbs. 255. The resolution is a function of the PR2 register CCPR1L and DC1B<1:0> bits of the CCP1CON value as shown by Equation11-4. register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 EQUATION 11-4: PWM RESOLUTION registers occurs). While using the PWM, the CCPR1H register is read-only. log[4(PR2+1)] Resolution = ------------------------------------------ bits Equation11-2 is used to calculate the PWM pulse log(2) width. Equation11-3 is used to calculate the PWM duty cycle Note: If the pulse width value is greater than the ratio. period the assigned PWM pin(s) will remain unchanged. TABLE 11-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 © 2007 Microchip Technology Inc. DS41211D-page 79

PIC12F683 11.3.4 OPERATION IN SLEEP MODE 11.3.7 SETUP FOR PWM OPERATION In Sleep mode, the TMR2register will not increment The following steps should be taken when configuring and the state of the module will not change. If the CCP1 the CCP module for PWM operation: pin is driving a value, it will continue to drive that value. 1. Disable the PWM pin (CCP1) output drivers by When the device wakes up, TMR2 will continue from its setting the associated TRIS bit. previous state. 2. Set the PWM period by loading the PR2 register. 11.3.5 CHANGES IN SYSTEM CLOCK 3. Configure the CCP module for the PWM mode FREQUENCY by loading the CCP1CON register with the appropriate values. The PWM frequency is derived from the system clock 4. Set the PWM duty cycle by loading the CCPR1L frequency. Any changes in the system clock frequency register and DC1B bits of the CCP1CON register. will result in changes to the PWM frequency. See Section3.0 “Oscillator Module (With Fail-Safe 5. Configure and start Timer2: Clock Monitor)” for additional details. (cid:129) Clear the TMR2IF interrupt flag bit of the PIR1 register. 11.3.6 EFFECTS OF RESET (cid:129) Set the Timer2 prescale value by loading the Any Reset will force all ports to Input mode and the T2CKPS bits of the T2CON register. CCP registers to their Reset states. (cid:129) Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: (cid:129) Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). (cid:129) Enable the CCP1 pin output driver by clearing the associated TRIS bit. DS41211D-page 80 © 2007 Microchip Technology Inc.

PIC12F683 TABLE 11-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx xxxx xxxx CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx xxxx xxxx CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare. TABLE 11-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx xxxx xxxx CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx xxxx xxxx INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 -000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TMR2 Timer2 Module Register 0000 0000 0000 0000 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. © 2007 Microchip Technology Inc. DS41211D-page 81

PIC12F683 NOTES: DS41211D-page 82 © 2007 Microchip Technology Inc.

PIC12F683 12.0 SPECIAL FEATURES OF THE The PIC12F683 has two timers that offer necessary CPU delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crys- The PIC12F683 has a host of features intended to tal oscillator is stable. The other is the Power-up Timer maximize system reliability, minimize cost through (PWRT), which provides a fixed delay of 64ms (nomi- elimination of external components, provide power nal) on power-up only, designed to keep the part in saving features and offer code protection. Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which These features are: can use the Power-up Timer to provide at least a 64ms (cid:129) Reset Reset. With these three functions on-chip, most - Power-on Reset (POR) applications need no external Reset circuitry. - Power-up Timer (PWRT) The Sleep mode is designed to offer a very low-current - Oscillator Start-up Timer (OST) Power-down mode. The user can wake-up from Sleep - Brown-out Reset (BOR) through: (cid:129) Interrupts (cid:129) External Reset (cid:129) Watchdog Timer (WDT) (cid:129) Watchdog Timer Wake-up (cid:129) Oscillator Selection (cid:129) An interrupt (cid:129) Sleep Several oscillator options are also made available to (cid:129) Code Protection allow the part to fit the application. The INTOSC option (cid:129) ID Locations saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select (cid:129) In-Circuit Serial Programming™ various options (see Register12-1). Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX Memory Program- ming Specification” (DS41204) for more information. 12.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register12-1. These bits are mapped in program memory location 2007h. © 2007 Microchip Technology Inc. DS41211D-page 83

PIC12F683 REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER — — — — FCMEN IESO BOREN1 BOREN0 bit 15 bit 8 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘1’ bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 10 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled bit 7 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 6 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: GP3/MCLR pin function select bit(4) 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 110 = RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased when the code protection is turned off. 4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41211D-page 84 © 2007 Microchip Technology Inc.

PIC12F683 12.2 Calibration Bits Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any Brown-out Reset (BOR), Power-on Reset (POR) and other Reset. Most other registers are reset to a “Reset 8MHz internal oscillator (HFINTOSC) are factory cali- state” on: brated. These calibration values are stored in fuses (cid:129) Power-on Reset located in the Calibration Word (2009h). The Calibra- tion Word is not erased when using the specified bulk (cid:129) MCLR Reset erase sequence in the “PIC12F6XX/16F6XX Memory (cid:129) MCLR Reset during Sleep Programming Specification” (DS41244) and thus, does (cid:129) WDT Reset not require reprogramming. (cid:129) Brown-out Reset (BOR) WDT wake-up does not cause register resets in the 12.3 Reset same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation. TO and The PIC12F683 differentiates between various kinds of PD bits are set or cleared differently in different Reset Reset: situations, as indicated in Table12-2. Software can use a) Power-on Reset (POR) these bits to determine the nature of the Reset. See b) WDT Reset during normal operation Table12-4 for a full description of Reset states of all c) WDT Reset during Sleep registers. d) MCLR Reset during normal operation A simplified block diagram of the On-Chip Reset Circuit e) MCLR Reset during Sleep is shown in Figure12-1. f) Brown-out Reset (BOR) The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section15.0 “Electrical Specifications” for pulse-width specifications. FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/VPP pin SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out(1) Reset BOREN SBOREN S OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1/ CLKI pin PWRT LFINTOSC 11-bit Ripple Counter Enable PWRT Enable OST Note 1: Refer to the Configuration Word register (Register12-1). © 2007 Microchip Technology Inc. DS41211D-page 85

PIC12F683 12.3.1 POWER-ON RESET FIGURE 12-2: RECOMMENDED MCLR CIRCUIT The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper VDD operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This PIC® will eliminate external RC components usually needed R1 MCU to create Power-on Reset. A maximum rise time for 1kΩ (or greater) VDD is required. See Section15.0 “Electrical Specifications” for details. If the BOR is enabled, the R2 maximum rise time specification does not apply. The MCLR BOR circuitry will keep the device in Reset until VDD SW1 (needed 1w0i0th Ω capacitor) reaches VBOD (see Section12.3.4 “Brown-Out Reset (optional) (BOR)”). C1 Note: The POR circuit does not produce an 0.1 μF (optional, not critical) internal Reset when VDD declines. To re-enable the POR, VDD must reach Vss for a minimum of 100μs. When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., 12.3.3 POWER-UP TIMER (PWRT) voltage, frequency, temperature, etc.) must be met to The Power-up Timer provides a fixed 64ms (nominal) ensure operation. If these conditions are not met, the time-out on power-up only, from POR or Brown-out device must be held in Reset until the operating Reset. The Power-up Timer operates from the 31kHz conditions are met. LFINTOSC oscillator. For more information, see For additional information, refer to the Application Note Section3.5 “Internal Clock Modes”. The chip is kept AN607, “Power-up Trouble Shooting” (DS00607). in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A 12.3.2 MCLR Configuration bit, PWRTE, can disable (if set) or enable PIC12F683 has a noise filter in the MCLR Reset path. (if cleared or programmed) the Power-up Timer. The The filter will detect and ignore small pulses. Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. It should be noted that a WDT Reset does not drive MCLR pin low. The Power-up Timer delay will vary from chip-to-chip due to: Voltages applied to the MCLR pin that exceed its specification can result in both MCLR Resets and (cid:129) V DD variation excessive current beyond the device specification (cid:129) Temperature variation during the ESD event. For this reason, Microchip (cid:129) Process variation recommends that the MCLR pin no longer be tied See DC parameters for details (Section15.0 directly to VDD. The use of an RC network, as shown in “Electrical Specifications”). Figure12-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When Note: Voltage spikes below VSS at the MCLR MCLRE = 0, the Reset signal to the chip is generated pin, inducing currents greater than 80 mA, internally. When the MCLRE = 1, the GP3/MCLR pin may cause latch-up. Thus, a series resis- becomes an external Reset input. In this mode, the tor of 50-100 Ω should be used when GP3/MCLR pin has a weak pull-up to VDD. applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. DS41211D-page 86 © 2007 Microchip Technology Inc.

PIC12F683 12.3.4 BROWN-OUT RESET (BOR) If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset The BOREN0 and BOREN1 bits in the Configuration and the Power-up Timer will be re-initialized. Once VDD Word register select one of four BOR modes. Two rises above VBOR, the Power-up Timer will execute a modes have been added to allow software or hardware 64ms Reset. control of the BOR enable. When BOREN<1:0>=01, the SBOREN bit of the PCON register enables/disables 12.3.5 BOR CALIBRATION the BOR, allowing it to be controlled in software. By selecting BOREN<1:0> = 10, the BOR is automatically The PIC12F683 stores the BOR calibration values in disabled in Sleep to conserve power and enabled on fuses located in the Calibration Word register (2008h). wake-up. In this mode, the SBOREN bit is disabled. The Calibration Word register is not erased when using See Register12-1 for the Configuration Word the specified bulk erase sequence in the definition. “PIC12F6XX/16F6XX Memory Programming Specifi- cation” (DS41204) and thus, does not require A brown-out occurs when VDD falls below VBOR for reprogramming. greater than parameter TBOR (see Section15.0 “Electrical Specifications”). The brown-out condition Note: Address 2008h is beyond the user pro- will reset the device. This will occur regardless of VDD gram memory space. It belongs to the slew rate. A Brown-out Reset may not occur if VDD falls special configuration memory space below VBOR for less than parameter TBOR. (2000h-3FFFh), which can be accessed only during programming. See On any Reset (Power-on, Brown-out Reset, Watchdog “PIC12F6XX/16F6XX Memory Program- Timer, etc.), the chip will remain in Reset until VDD rises ming Specification” (DS41204) for more above VBOR (see Figure12-3). If enabled, the information. Power-up Timer will be invoked by the Reset and keep the chip in Reset an additional 64ms. Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register. FIGURE 12-3: BROWN-OUT SITUATIONS VDD VBOR Internal Reset 64 ms(1) VDD VBOR Internal < 64 ms Reset 64 ms(1) VDD VBOR Internal Reset 64 ms(1) Note 1: 64ms delay only if PWRTE bit is programmed to ‘0’. © 2007 Microchip Technology Inc. DS41211D-page 87

PIC12F683 12.3.6 TIME-OUT SEQUENCE 12.3.7 POWER CONTROL (PCON) REGISTER On power-up, the time-out sequence is as follows: (cid:129) PWRT time-out is invoked after POR has expired. The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred (cid:129) OST is activated after the PWRT time-out has last. expired. Bit0 is BOR (Brown-out). BOR is unknown on The total time-out will vary based on oscillator Power-on Reset. It must then be set by the user and configuration and PWRTE bit status. For example, in EC checked on subsequent Resets to see if BOR = 0, mode with PWRTE bit erased (PWRT disabled), there indicating that a Brown-out has occurred. The BOR will be no time-out at all. Figure12-4, Figure12-5 and Status bit is a “don’t care” and is not necessarily Figure12-6 depict time-out sequences. The device can predictable if the brown-out circuit is disabled execute code from the INTOSC while OST is active by (BOREN<1:0> = 00 in the Configuration Word enabling Two-Speed Start-up or Fail-Safe Monitor (see register). Section3.7.2 “Two-Speed Start-up Sequence” and Section3.8 “Fail-Safe Clock Monitor”). Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a Since the time-outs occur from the POR pulse, if MCLR ‘1’ to this bit following a Power-on Reset. On a subse- is kept low long enough, the time-outs will expire. Then, quent Reset, if POR is ‘0’, it will indicate that a bringing MCLR high will begin execution immediately Power-on Reset has occurred (i.e., VDD may have (see Figure12-5). This is useful for testing purposes or gone too low). to synchronize more than one PIC12F683 device operating in parallel. For more information, see Section4.2.4 “Ultra Low-Power Wake-up” and Section12.3.4 Table12-5 shows the Reset conditions for some “Brown-Out Reset (BOR)”. special registers, while Table12-4 shows the Reset conditions for all the registers. TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS Power-up Brown-out Reset Wake-up from Oscillator Configuration Sleep PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP TPWRT + 1024 (cid:129) 1024 (cid:129)TOSC TPWRT + 1024 (cid:129) 1024 (cid:129)TOSC 1024 (cid:129)TOSC TOSC TOSC RC, EC, INTOSC TPWRT — TPWRT — — TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Value on Value on Name Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets(1) CONFIG(2) BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register12-1) for operation of all register bits. DS41211D-page 88 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset © 2007 Microchip Technology Inc. DS41211D-page 89

PIC12F683 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS Wake-up from Sleep MCLR Reset through Interrupt Register Address Power-on Reset WDT Reset Wake-up from Sleep through Brown-out Reset(1) WDT Time-out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu GPIO 05h --x0 x000 --x0 x000 --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2) PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2CON 12h -000 0000 -000 0000 -uuu uuuu CCPR1L 13h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 14h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 15h --00 0000 --00 0000 --uu uuuu WDTCON 18h ---0 1000 ---0 1000 ---u uuuu CMCON0 19h 0000 0000 0000 0000 uuuu uuuu CMCON1 20h ---- --10 ---- --10 ---- --uu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISIO 85h --11 1111 --11 1111 --uu uuuu PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu PCON 8Eh --01 --0x --0u --uu(1,5) --uu --uu OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu PR2 92h 1111 1111 1111 1111 1111 1111 WPU 95h --11 -111 --11 -111 uuuu uuuu IOC 96h --00 0000 --00 0000 --uu uuuu VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu EEDAT 9Ah 0000 0000 0000 0000 uuuu uuuu EEADR 9Bh 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table12-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. DS41211D-page 90 © 2007 Microchip Technology Inc.

PIC12F683 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Wake-up from Sleep MCLR Reset through Interrupt Register Address Power-on Reset WDT Reset Wake-up from Sleep through Brown-out Reset(1) WDT Time-out EECON1 9Ch ---- x000 ---- q000 ---- uuuu EECON2 9Dh ---- ---- ---- ---- ---- ---- ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ANSEL 9Fh -000 1111 -000 1111 -uuu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table12-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Status PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx --01 --0x MCLR Reset during Normal Operation 000h 000u uuuu --0u --uu MCLR Reset during Sleep 000h 0001 0uuu --0u --uu WDT Reset 000h 0000 uuuu --0u --uu WDT Wake-up PC + 1 uuu0 0uuu --uu --uu Brown-out Reset 000h 0001 1uuu --01 --10 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. © 2007 Microchip Technology Inc. DS41211D-page 91

PIC12F683 12.4 Interrupts For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be The PIC12F683 has multiple interrupt sources: three or four instruction cycles. The exact latency (cid:129) External Interrupt GP2/INT depends upon when the interrupt event occurs (see (cid:129) Timer0 Overflow Interrupt Figure12-8). The latency is the same for one or two-cycle instructions. Once in the Interrupt Service (cid:129) GPIO Change Interrupts Routine, the source(s) of the interrupt can be (cid:129) Comparator Interrupt determined by polling the interrupt flag bits. The (cid:129) A/D Interrupt interrupt flag bit(s) must be cleared in software before (cid:129) Timer1 Overflow Interrupt re-enabling interrupts to avoid multiple interrupt (cid:129) Timer2 Match Interrupt requests. (cid:129) EEPROM Data Write Interrupt Note1: Individual interrupt flag bits are set, (cid:129) Fail-Safe Clock Monitor Interrupt regardless of the status of their (cid:129) CCP Interrupt corresponding mask bit or the GIE bit. The Interrupt Control register (INTCON) and Peripheral 2: When an instruction that clears the GIE Interrupt Request Register 1 (PIR1) record individual bit is executed, any interrupts that were interrupt requests in flag bits. The INTCON register pending for execution in the next cycle also has individual and global interrupt enable bits. are ignored. The interrupts, which were ignored, are still pending to be serviced The Global Interrupt Enable bit, GIE of the INTCON when the GIE bit is set again. register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts For additional information on Timer1, Timer2, can be disabled through their corresponding enable comparators, ADC, data EEPROM or Enhanced CCP bits in the INTCON register and PIE1 register. GIE is modules, refer to the respective peripheral section. cleared on Reset. 12.4.1 GP2/INT INTERRUPT When an interrupt is serviced, the following actions occur automatically: The external interrupt on the GP2/INT pin is edge-triggered; either on the rising edge if the INTEDG (cid:129) The GIE is cleared to disable any further interrupt. bit of the OPTION register is set, or the falling edge, if (cid:129) The return address is pushed onto the stack. the INTEDG bit is clear. When a valid edge appears on (cid:129) The PC is loaded with 0004h. the GP2/INT pin, the INTF bit of the INTCON register is The Return from Interrupt instruction, RETFIE, exits set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must the interrupt routine, as well as sets the GIE bit, which be cleared by software in the Interrupt Service Routine re-enables unmasked interrupts. before re-enabling this interrupt. The GP2/INT interrupt The following interrupt flags are contained in the can wake-up the processor from Sleep, if the INTE bit INTCON register: was set prior to going into Sleep. See Section12.7 (cid:129) INT Pin Interrupt “Power-Down Mode (Sleep)” for details on Sleep and (cid:129) GPIO Change Interrupt Figure12-10 for timing of wake-up from Sleep through GP2/INT interrupt. (cid:129) Timer0 Overflow Interrupt The peripheral interrupt flags are contained in the PIR1 Note: The ANSEL and CMCON0 registers must register. The corresponding interrupt enable bit is be initialized to configure an analog contained in the PIE1 register. channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot The following interrupt flags are contained in the PIR1 generate an interrupt. register: (cid:129) EEPROM Data Write Interrupt (cid:129) A/D Interrupt (cid:129) Comparator Interrupt (cid:129) Timer1 Overflow Interrupt (cid:129) Timer2 Match Interrupt (cid:129) Fail-Safe Clock Monitor Interrupt (cid:129) CCP Interrupt DS41211D-page 92 © 2007 Microchip Technology Inc.

PIC12F683 12.4.2 TIMER0 INTERRUPT 12.4.3 GPIO INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set An input change on GPIO change sets the GPIF bit of the T0IF (INTCON<2>) bit. The interrupt can be the INTCON register. The interrupt can be enabled/disabled by setting/clearing the T0IE bit of the enabled/disabled by setting/clearing the GPIE bit of the INTCON register. See Section5.0 “Timer0 Module” INTCON register. Plus, individual pins can be for operation of the Timer0 module. configured through the IOC register. Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. FIGURE 12-7: INTERRUPT LOGIC IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 T0IF Wake-up (If in Sleep mode) TMR2IF T0IE TMR2IE INTF INTE Interrupt to CPU TMR1IF GPIF TMR1IE GPIE CMIF CMIE PEIE ADIF GIE ADIE EEIF EEIE OSFIF OSFIE CCP1IF CCP1IE © 2007 Microchip Technology Inc. DS41211D-page 93

PIC12F683 FIGURE 12-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF flag (5) Interrupt Latency (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section15.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. DS41211D-page 94 © 2007 Microchip Technology Inc.

PIC12F683 12.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved Note: The PIC12F683 normally does not require on the stack. Typically, users may wish to save key saving the PCLATH. However, if com- registers during an interrupt (e.g., W and STATUS puted GOTO’s are used in the ISR and the registers). This must be implemented in software. main code, the PCLATH must be saved and restored in the ISR. Since the lower 16 bytes of all banks are common in the PIC12F683 (see Figure2-2), temporary holding regis- ters, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, makes it easier to context save and restore. The same code shown in Example12-1 can be used to: (cid:129) Store the W register. (cid:129) Store the STATUS register. (cid:129) Execute the ISR code. (cid:129) Restore the Status (and Bank Select Bit register). (cid:129) Restore the W register. EXAMPLE 12-1: SAVING STATUS AND W REGISTERS IN RAM MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W © 2007 Microchip Technology Inc. DS41211D-page 95

PIC12F683 12.6 Watchdog Timer (WDT) 12.6.2 WDT CONTROL The WDT has the following features: The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. (cid:129) Operates from the LFINTOSC (31 kHz) When the WDTE bit in the Configuration Word register (cid:129) Contains a 16-bit prescaler is set, the SWDTEN bit of the WDTCON register has no (cid:129) Shares an 8-bit prescaler with Timer0 effect. If WDTE is clear, then the SWDTEN bit can be (cid:129) Time-out period is from 1 ms to 268 seconds used to enable and disable the WDT. Setting the bit will (cid:129) Configuration bit and software controlled enable it and clearing the bit will disable it. WDT is cleared under certain conditions described in The PSA and PS<2:0> bits of the OPTION register Table12-7. have the same function as in previous versions of the PIC12F683 Family of microcontrollers. See 12.6.1 WDT OSCILLATOR Section5.0 “Timer0 Module” for more information. The WDT derives its time base from the 31kHz LFINTOSC. The LTS bit of the OSCCON register does not reflect that the LFINTOSC is enabled. The value of WDTCON is ‘---0 1000’ on all Resets. This gives a nominal time base of 17ms. Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled). FIGURE 12-9: WATCHDOG TIMER BLOCK DIAGRAM 0 From Timer0 Clock Source Prescaler(1) 1 16-bit WDT Prescaler 8 PSA PS<2:0> 31kHz WDTPS<3:0> To Timer0 LFINTOSC Clock 0 1 PSA WDTE from Configuration Word register SWDTEN from WDTCON WDT Time-out Note 1: This is the shared Timer0/WDT prescaler. See Section5.0 “Timer0 Module” for more information. TABLE 12-7: WDT STATUS Conditions WDT WDTE = 0 CLRWDT Command Cleared Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST DS41211D-page 96 © 2007 Microchip Technology Inc.

PIC12F683 REGISTER 12-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note 1: If WDTE Configuration bit=1, then WDT is always enabled, irrespective of this control bit. If WDTE Configuration bit=0, then it is possible to turn WDT on/off with this control bit. TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Value on Value on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOR Resets WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register12-1 for operation of all Configuration Word register bits. © 2007 Microchip Technology Inc. DS41211D-page 97

PIC12F683 12.7 Power-Down Mode (Sleep) When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to The Power-down mode is entered by executing a wake-up through an interrupt event, the corresponding SLEEP instruction. interrupt enable bit must be set (enabled). Wake-up If the Watchdog Timer is enabled: occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at (cid:129) WDT will be cleared but keeps running. the instruction after the SLEEP instruction. If the GIE bit (cid:129) PD bit in the STATUS register is cleared. is set (enabled), the device executes the instruction (cid:129) TO bit is set. after the SLEEP instruction, then branches to the inter- (cid:129) Oscillator driver is turned off. rupt address (0004h). In cases where the execution of (cid:129) I/O ports maintain the status they had before SLEEP the instruction following SLEEP is not desirable, the was executed (driving high, low or high-impedance). user should have a NOP after the SLEEP instruction. For lowest current consumption in this mode, all I/O pins Note: If the global interrupts are disabled (GIE is should be either at VDD or VSS, with no external circuitry cleared) and any interrupt source has both drawing current from the I/O pin and the comparators its interrupt enable bit and the correspond- and CVREF should be disabled. I/O pins that are ing interrupt flag bits set, the device will high-impedance inputs should be pulled high or low immediately wake-up from Sleep. externally to avoid switching currents caused by floating The WDT is cleared when the device wakes up from inputs. The T0CKI input should also be at VDD or VSS for Sleep, regardless of the source of wake-up. lowest current consumption. The contribution from on-chip pull-ups on GPIO should be considered. 12.7.2 WAKE-UP USING INTERRUPTS The MCLR pin must be at a logic high level. When global interrupts are disabled (GIE cleared) and Note: It should be noted that a Reset generated any interrupt source has both its interrupt enable bit by a WDT time-out does not drive MCLR and interrupt flag bit set, one of the following will occur: pin low. (cid:129) If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will 12.7.1 WAKE-UP FROM SLEEP complete as a NOP. Therefore, the WDT and WDT The device can wake-up from Sleep through one of the prescaler and postscaler (if enabled) will not be following events: cleared, the TO bit will not be set and the PD bit will not be cleared. 1. External Reset input on MCLR pin. (cid:129) If the interrupt occurs during or after the 2. Watchdog Timer wake-up (if WDT was execution of a SLEEP instruction, the device will enabled). Immediately wake-up from Sleep. The SLEEP 3. Interrupt from GP2/INT pin, GPIO change or a instruction is executed. Therefore, the WDT and peripheral interrupt. WDT prescaler and postscaler (if enabled) will be The first event will cause a device Reset. The two latter cleared, the TO bit will be set and the PD bit will events are considered a continuation of program be cleared. execution. The TO and PD bits in the STATUS register Even if the flag bits were checked before executing a can be used to determine the cause of a device Reset. SLEEP instruction, it may be possible for flag bits to The PD bit, which is set on power-up, is cleared when become set before the SLEEP instruction completes. To Sleep is invoked. TO bit is cleared if WDT wake-up determine whether a SLEEP instruction executed, test occurred. the PD bit. If the PD bit is set, the SLEEP instruction The following peripheral interrupts can wake the device was executed as a NOP. from Sleep: To ensure that the WDT is cleared, a CLRWDT instruction 1. Timer1 interrupt. Timer1 must be operating as should be executed before a SLEEP instruction. See an asynchronous counter. Figure12-10 for more details. 2. ECCP Capture mode interrupt. 3. A/D conversion (when A/D clock source is FRC). 4. EEPROM write operation completion. 5. Comparator output changes state. 6. Interrupt-on-change. 7. External Interrupt from INT pin. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. DS41211D-page 98 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency(3) GIE bit (INTCON<7>) Processor in Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h Instruction Fetched Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) InEsxteruccuttioedn Inst(PC – 1) Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. 12.8 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. Note: The entire data EEPROM and Flash pro- gram memory will be erased when the code protection is turned off. See the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information. 12.9 ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2007 Microchip Technology Inc. DS41211D-page 99

PIC12F683 12.10 In-Circuit Serial Programming™ 12.11 In-Circuit Debugger The PIC12F683 microcontrollers can be serially Since in-circuit debugging requires access to three programmed while in the end application circuit. This is pins, MPLAB® ICD 2 development with a 14-pin device simply done with five connections for: is not practical. A special 14-pin PIC12F683 ICD device is used with MPLAB ICD 2 to provide separate clock, (cid:129) clock data and MCLR pins and frees all normally available (cid:129) data pins to the user. (cid:129) power A special debugging adapter allows the ICD device to (cid:129) ground be used in place of a PIC12F683 device. The (cid:129) programming voltage debugging adapter is the only source of the ICD device. This allows customers to manufacture boards with When the ICD pin on the PIC12F683 ICD device is held unprogrammed devices and then program the micro- low, the In-Circuit Debugger functionality is enabled. controller just before shipping the product. This also This function allows simple debugging functions when allows the most recent firmware or a custom firmware used with MPLAB ICD 2. When the microcontroller has to be programmed. this feature enabled, some of the resources are not The device is placed into a Program/Verify mode by available for general use. Table12-9 shows which holding the GP0 and GP1 pins low, while raising the features are consumed by the background debugger. MCLR (VPP) pin from VIL to VIHH. See the “PIC12F6XX/16F6XX Memory Programming TABLE 12-9: DEBUGGER RESOURCES Specification” (DS41204) for more information. GP0 Resource Description becomes the programming data and GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Stack 1 level Trigger inputs in Program/Verify mode. Program Memory Address 0h must be NOP A typical In-Circuit Serial Programming connection is 700h-7FFh shown in Figure12-11. For more information, see “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” (DS51331), available on FIGURE 12-11: TYPICAL IN-CIRCUIT Microchip’s web site (www.microchip.com). SERIAL PROGRAMMING CONNECTION FIGURE 12-12: 14-PIN ICD PINOUT To Normal Connections 14-Pin PDIP External In-Circuit Debug Device Connector * Signals PIC12F683 NC 1 14 ICDCLK +5V VDD D ICDMCLR 2 C 13 ICDDATA 0V VSS VDD 3 3-I 12 GND VPP MCLR/VPP/GP3 GP5 4 68 11 GP0 F CLK GP1 GP4 5 12 10 GP1 GP3 6 C 9 GP2 Data I/O GP0 ICD 7 PI 8 NC * * * To Normal Connections * Isolation devices (as required) DS41211D-page 100 © 2007 Microchip Technology Inc.

PIC12F683 13.0 INSTRUCTION SET SUMMARY TABLE 13-1: OPCODE FIELD DESCRIPTIONS The PIC12F683 instruction set is highly orthogonal and is comprised of three basic categories: Field Description (cid:129) Byte-oriented operations f Register file address (0x00 to 0x7F) (cid:129) Bit-oriented operations W Working register (accumulator) (cid:129) Literal and control operations b Bit address within an 8-bit file register Each PIC16 instruction is a 14-bit word divided into an k Literal field, constant data or label opcode, which specifies the instruction type and one or x Don’t care location (= 0 or 1). more operands, which further specify the operation of The assembler will generate code with x = 0. the instruction. The formats for each of the categories It is the recommended form of use for is presented in Figure13-1, while the various opcode compatibility with all Microchip software tools. fields are summarized in Table13-1. d Destination select; d = 0: store result in W, Table13-2 lists the instructions recognized by the d = 1: store result in file register f. MPASMTM assembler. Default is d = 1. For byte-oriented instructions, ‘f’ represents a file PC Program Counter register designator and ‘d’ represents a destination TO Time-out bit designator. The file register designator specifies which C Carry bit file register is to be used by the instruction. DC Digit carry bit The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is Z Zero bit placed in the W register. If ‘d’ is one, the result is placed PD Power-down bit in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field FIGURE 13-1: GENERAL FORMAT FOR designator, which selects the bit affected by the INSTRUCTIONS operation, while ‘f’ represents the address of the file in which the bit is located. Byte-oriented file register operations 13 8 7 6 0 For literal and control operations, ‘k’ represents an OPCODE d f (FILE #) 8-bit or 11-bit constant, or literal value. d = 0 for destination W One instruction cycle consists of four oscillator periods; d = 1 for destination f for an oscillator frequency of 4 MHz, this gives a f = 7-bit file register address nominal instruction execution time of 1μs. All instructions are executed within a single instruction Bit-oriented file register operations cycle, unless a conditional test is true, or the program 13 10 9 7 6 0 counter is changed as a result of an instruction. When OPCODE b (BIT #) f (FILE #) this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. b = 3-bit bit address f = 7-bit file register address All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a Literal and control operations hexadecimal digit. General 13.1 Read-Modify-Write Operations 13 8 7 0 OPCODE k (literal) Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) k = 8-bit immediate value operation. The register is read, the data is modified, and the result is stored according to either the instruc- CALL and GOTO instructions only tion, or the destination designator ‘d’. A read operation 13 11 10 0 is performed on a register even if the instruction writes OPCODE k (literal) to that register. k = 11-bit immediate value For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. © 2007 Microchip Technology Inc. DS41211D-page 101

PIC12F683 TABLE 13-2: PIC12F683 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP – No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call Subroutine 2 10 0kkk kkkk kkkk CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE – Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS41211D-page 102 © 2007 Microchip Technology Inc.

PIC12F683 13.2 Instruction Descriptions ADDLW Add literal and W BCF Bit Clear f Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: (W) + k → (W) Operation: 0 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the eight-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + (f) → (destination) Operation: 1 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set. with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: (W) .AND. (k) → (W) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the eight-bit literal Description: If bit ‘b’ in register ‘f’ is ‘1’, the next ‘k’. The result is placed in the W instruction is executed. register. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. DS41211D-page 103

PIC12F683 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 Operands: None 0 ≤ b < 7 Operation: 00h → WDT Operation: skip if (f<b>) = 1 0 → WDT prescaler, 1 → TO Status Affected: None 1 → PD Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Status Affected: TO, PD instruction is executed. If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the instruction is discarded and a NOP Watchdog Timer. It also resets the is executed instead, making this a prescaler of the WDT. 2-cycle instruction. Status bits TO and PD are set. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ f ≤ 127 Operation: (PC)+ 1→ TOS, d ∈ [0,1] k → PC<10:0>, Operation: (f) → (destination) (PCLATH<4:3>) → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’, the stack. The eleven-bit the result is stored back in immediate address is loaded into register ‘f’. PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) d ∈ [0,1] 1 → Z Operation: (f) - 1 → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’, cleared and the Z bit is set. the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1 → Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS41211D-page 104 © 2007 Microchip Technology Inc.

PIC12F683 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) - 1 → (destination); Operation: (f) + 1 → (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘1’, the next If the result is ‘1’, the next instruction is executed. If the instruction is executed. If the result is ‘0’, then a NOP is result is ‘0’, a NOP is executed executed instead, making it a instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 2047 Operands: 0 ≤ k ≤ 255 Operation: k → PC<10:0> Operation: (W) .OR. k → (W) PCLATH<4:3> → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’. The eleven-bit immediate value is The result is placed in the loaded into PC bits <10:0>. The W register. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f) + 1 → (destination) Operation: (W) .OR. (f) → (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Inclusive OR the W register with incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. © 2007 Microchip Technology Inc. DS41211D-page 105

PIC12F683 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) → (f) Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Move data from W register to Description: The contents of register f is register ‘f’. moved to a destination dependent Words: 1 upon the status of d. If d = 0, Cycles: 1 destination is W register. If d = 1, the destination is file register f Example: MOVW OPTION itself. d = 1 is useful to test a file F register since status flag Z is Before Instruction affected. OPTION= 0xFF Words: 1 W = 0x4F After Instruction Cycles: 1 OPTION= 0x4F Example: MOVF FSR, 0 W = 0x4F After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W NOP No Operation Syntax: [ label ] MOVLW k Syntax: [ label ] NOP Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W) Operation: No operation Status Affected: None Status Affected: None Description: The eight-bit literal ‘k’ is loaded into Description: No operation. W register. The “don’t cares” will Words: 1 assemble as ‘0’s. Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A DS41211D-page 106 © 2007 Microchip Technology Inc.

PIC12F683 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, Operation: k → (W); 1 → GIE TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is Description: The W register is loaded with the POPed and Top-of-Stack (TOS) is eight bit literal ‘k’. The program loaded in the PC. Interrupts are counter is loaded from the top of enabled by setting Global the stack (the return address). Interrupt Enable bit, GIE This is a two-cycle instruction. (INTCON<7>). This is a two-cycle Words: 1 instruction. Cycles: 2 Words: 1 Example: CALL TABLE;W contains Cycles: 2 table Example: RETFIE ;offset value TABLE (cid:129) ;W now has table value After Interrupt (cid:129) PC = TOS (cid:129) GIE= 1 ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; (cid:129) (cid:129) (cid:129) RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS → PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. © 2007 Microchip Technology Inc. DS41211D-page 107

PIC12F683 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 Operands: None d ∈ [0,1] Operation: 00h → WDT, Operation: See description below 0 → WDT prescaler, 1 → TO, Status Affected: C 0 → PD Description: The contents of register ‘f’ are Status Affected: TO, PD rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is placed in the W register. cleared. Time-out Status bit, TO If ‘d’ is ‘1’, the result is stored is set. Watchdog Timer and its back in register ‘f’. prescaler are cleared. The processor is put into Sleep C Register f mode with the oscillator stopped. Words: 1 Cycles: 1 Example: RLF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 RRF Rotate Right f through Carry SUBLW Subtract W from literal Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: k - (W) → (W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s Description: The contents of register ‘f’ are complement method) from the rotated one bit to the right through eight-bit literal ‘k’. The result is the Carry flag. If ‘d’ is ‘0’, the placed in the W register. result is placed in the W register. If ‘d’ is ‘1’, the result is placed C = 0 W > k back in register ‘f’. C = 1 W ≤ k C Register f DC = 0 W<3:0> > k<3:0> DC = 1 W<3:0> ≤ k<3:0> DS41211D-page 108 © 2007 Microchip Technology Inc.

PIC12F683 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 255 d ∈ [0,1] Operation: (W) .XOR. k → (W) Operation: (f) - (W) → (destination) Status Affected: Z Status Affected: C, DC, Z Description: The contents of the W register Description: Subtract (2’s complement method) are XOR’ed with the eight-bit W register from register ‘f’. If ‘d’ is literal ‘k’. The result is placed in ‘0’, the result is stored in the W the W register. register. If ‘d’ is ‘1’, the result is stored back in register ‘f. C = 0 W > f C = 1 W ≤ f DC = 0 W<3:0> > f<3:0> DC = 1 W<3:0> ≤ f<3:0> SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF f,d Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), Operation: (W) .XOR. (f) → (destination) (f<7:4>) → (destination<3:0>) Status Affected: Z Status Affected: None Description: Exclusive OR the contents of the Description: The upper and lower nibbles of W register with register ‘f’. If ‘d’ is register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is stored in the W ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. placed in register ‘f’. © 2007 Microchip Technology Inc. DS41211D-page 109

PIC12F683 NOTES: DS41211D-page 110 © 2007 Microchip Technology Inc.

PIC12F683 14.0 DEVELOPMENT SUPPORT 14.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- (cid:129) Integrated Development Environment controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: (cid:129) Assemblers/Compilers/Linkers (cid:129) A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) (cid:129) Simulators (cid:129) A full-featured editor with color-coded context - MPLAB SIM Software Simulator (cid:129) A multiple project manager (cid:129) Emulators (cid:129) Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator (cid:129) High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator (cid:129) Visual device initializer for easy register (cid:129) In-Circuit Debugger initialization - MPLAB ICD 2 (cid:129) Mouse over variable inspection (cid:129) Device Programmers (cid:129) Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer (cid:129) Extensive on-line help - PICkit™ 2 Development Programmer (cid:129) Integration of select third party tools, such as (cid:129) Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: (cid:129) Edit your source files (either assembly or C) (cid:129) One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) (cid:129) Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2007 Microchip Technology Inc. DS41211D-page 111

PIC12F683 14.2 MPASM Assembler 14.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: (cid:129) Support for the entire dsPIC30F instruction set (cid:129) Integration into MPLAB IDE projects (cid:129) Support for fixed-point and floating-point data (cid:129) User-defined macros to streamline (cid:129) Command line interface assembly code (cid:129) Rich directive set (cid:129) Conditional assembly for multi-purpose source files (cid:129) Flexible macro language (cid:129) Directives that allow complete control over the (cid:129) MPLAB IDE compatibility assembly process 14.6 MPLAB SIM Software Simulator 14.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcontrol- a comprehensive stimulus controller. Registers can be lers and the dsPIC30 and dsPIC33 family of digital sig- logged to files for further run-time analysis. The trace nal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 14.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: (cid:129) Efficient linking of single libraries instead of many smaller files (cid:129) Enhanced code maintainability by grouping related modules together (cid:129) Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41211D-page 112 © 2007 Microchip Technology Inc.

PIC12F683 14.7 MPLAB ICE 2000 14.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 14.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for simple, unified application. maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 14.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC® and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® and dsPIC® Flash microcontrollers with connects to the host PC via an RS-232 or USB cable. the easy-to-use, powerful graphical user interface of the The MPLAB PM3 has high-speed communications and MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, low- voltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2007 Microchip Technology Inc. DS41211D-page 113

PIC12F683 14.11 PICSTART Plus Development 14.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 14.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon- an easy-to-use interface for programming many of stration/development board series of circuits, Microchip Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN, includes a prototyping development board, twelve IrDA®, PowerSmart® battery management, SEEVAL® sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate Lite C compiler, and is designed to help get up to speed sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop and the latest “Product Selector Guide” (DS00148) for applications using Microchip’s powerful, mid-range the complete list of demonstration, development and Flash memory family of microcontrollers. evaluation kits. DS41211D-page 114 © 2007 Microchip Technology Inc.

PIC12F683 15.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ...............................................................................................-0.3V to +13.5V Voltage on all other pins with respect to VSS ...........................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin...................................................................................................................... 95 mA Maximum current into VDD pin......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin..............................................................................................25 mA Maximum current sunk by GPIO...................................................................................................................... 90 mA Maximum current sourced GPIO...................................................................................................................... 90 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. DS41211D-page 115

PIC12F683 FIGURE 15-1: PIC12F683 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 4.5 V) 4.0 ( D D V 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 C) ± 2% ° 60 ( e r u at r e p 25 ± 1% m e T 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41211D-page 116 © 2007 Microchip Technology Inc.

PIC12F683 15.1 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. VDD Supply Voltage 2.0 — 5.5 V FOSC < = 8 MHz: HFINTOSC, EC D001 2.0 — 5.5 V FOSC < = 4 MHz D001C 3.0 — 5.5 V FOSC < = 10 MHz D001D 4.5 — 5.5 V FOSC < = 20 MHz D002* VDR RAM Data Retention 1.5 — — V Device in Sleep mode Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See Section12.3.1 “Power-on Reset” ensure internal Power-on for details. Reset signal D004* SVDD VDD Rise Rate to ensure 0.05 — — V/ms See Section12.3.1 “Power-on Reset” internal Power-on Reset for details. signal * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. © 2007 Microchip Technology Inc. DS41211D-page 117

PIC12F683 15.2 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D010 Supply Current (IDD)(1, 2) — 11 16 μA 2.0 FOSC = 32kHz — 18 28 μA 3.0 LP Oscillator mode — 35 54 μA 5.0 D011* — 140 240 μA 2.0 FOSC = 1MHz — 220 380 μA 3.0 XT Oscillator mode — 380 550 μA 5.0 D012 — 260 360 μA 2.0 FOSC = 4MHz — 420 650 μA 3.0 XT Oscillator mode — 0.8 1.1 mA 5.0 D013* — 130 220 μA 2.0 FOSC = 1MHz — 215 360 μA 3.0 EC Oscillator mode — 360 520 μA 5.0 D014 — 220 340 μA 2.0 FOSC = 4MHz — 375 550 μA 3.0 EC Oscillator mode — 0.65 1.0 mA 5.0 D015 — 8 20 μA 2.0 FOSC = 31kHz — 16 40 μA 3.0 LFINTOSC mode — 31 65 μA 5.0 D016* — 340 450 μA 2.0 FOSC = 4MHz — 500 700 μA 3.0 HFINTOSC mode — 0.8 1.2 mA 5.0 D017 — 410 650 μA 2.0 FOSC = 8MHz — 700 950 μA 3.0 HFINTOSC mode — 1.30 1.65 mA 5.0 D018 — 230 400 μA 2.0 FOSC = 4MHz — 400 680 μA 3.0 EXTRC mode(3) — 0.63 1.1 mA 5.0 D019 — 2.6 3.25 mA 4.5 FOSC = 20MHz — 2.8 3.35 mA 5.0 HS Oscillator mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ. DS41211D-page 118 © 2007 Microchip Technology Inc.

PIC12F683 15.3 DC Characteristics: PIC12F683-I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020 Power-down Base — 0.05 1.2 μA 2.0 WDT, BOR, Comparators, VREF and Current(IPD)(2) — 0.15 1.5 μA 3.0 T1OSC disabled — 0.35 1.8 μA 5.0 — 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C D021 — 1.0 2.2 μA 2.0 WDT Current(1) — 2.0 4.0 μA 3.0 — 3.0 7.0 μA 5.0 D022 — 42 60 μA 3.0 BOR Current(1) — 85 122 μA 5.0 D023 — 32 45 μA 2.0 Comparator Current(1), both — 60 78 μA 3.0 comparators enabled — 120 160 μA 5.0 D024 — 30 36 μA 2.0 CVREF Current(1) (high range) — 45 55 μA 3.0 — 75 95 μA 5.0 D025* — 39 47 μA 2.0 CVREF Current(1) (low range) — 59 72 μA 3.0 — 98 124 μA 5.0 D026 — 4.5 7.0 μA 2.0 T1OSC Current(1), 32.768kHz — 5.0 8.0 μA 3.0 — 6.0 12 μA 5.0 D027 — 0.30 1.6 μA 3.0 A/D Current(1), no conversion in — 0.36 1.9 μA 5.0 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. © 2007 Microchip Technology Inc. DS41211D-page 119

PIC12F683 15.4 DC Characteristics: PIC12F683-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020E Power-down Base — 0.05 9 μA 2.0 WDT, BOR, Comparators, VREF and Current (IPD)(2) — 0.15 11 μA 3.0 T1OSC disabled — 0.35 15 μA 5.0 D021E — 1 17.5 μA 2.0 WDT Current(1) — 2 19 μA 3.0 — 3 22 μA 5.0 D022E — 42 65 μA 3.0 BOR Current(1) — 85 127 μA 5.0 D023E — 32 45 μA 2.0 Comparator Current(1), both — 60 78 μA 3.0 comparators enabled — 120 160 μA 5.0 D024E — 30 70 μA 2.0 CVREF Current(1) (high range) — 45 90 μA 3.0 — 75 120 μA 5.0 D025E* — 39 91 μA 2.0 CVREF Current(1) (low range) — 59 117 μA 3.0 — 98 156 μA 5.0 D026E — 4.5 25 μA 2.0 T1OSC Current(1), 32.768kHz — 5 30 μA 3.0 — 6 40 μA 5.0 D027E — 0.30 12 μA 3.0 A/D Current(1), no conversion in — 0.36 16 μA 5.0 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. DS41211D-page 120 © 2007 Microchip Technology Inc.

PIC12F683 15.5 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O Port: D030 with TTL buffer Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V D030A Vss — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V D031 with Schmitt Trigger buffer Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V D032 MCLR, OSC1 (RC mode)(1) VSS — 0.2 VDD V D033 OSC1 (XT and LP modes) VSS — 0.3 V D033A OSC1 (HS mode) VSS — 0.3 VDD V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V D040A 0.25 VDD + 0.8 — VDD V 2.0V ≤ VDD ≤ 4.5V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V 2.0V ≤ VDD ≤ 5.5V D042 MCLR 0.8 VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V D043A OSC1 (HS mode) 0.7 VDD — VDD V D043B OSC1 (RC mode) 0.9 VDD — VDD V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ± 0.1 ± 1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR(3) — ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD D063 OSC1 — ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration D070* IPUR GPIO Weak Pull-up Current 50 250 400 μA VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(5) D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) VOH Output High Voltage(5) D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.) * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. DS41211D-page 121

PIC12F683 15.5 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. D100 IULP Ultra Low-Power Wake-Up — 200 — nA See Application Note AN879, Current “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879) Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C D120A ED Byte Endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 5 6 ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40°C ≤ TA ≤ +85°C Cycles before Refresh(4) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Erase/Write 4.5 — 5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. DS41211D-page 122 © 2007 Microchip Technology Inc.

PIC12F683 15.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Typ Units Conditions No. TH01 θJA Thermal Resistance 84.6 °C/W 8-pin PDIP package Junction to Ambient 163.0 °C/W 8-pin SOIC package 52.4 °C/W 8-pin DFN-S 4x4x0.9 mm package 46.3 °C/W 8-pin DFN-S 6x5 mm package TH02 θJC Thermal Resistance 41.2 °C/W 8-pin PDIP package Junction to Case 38.8 °C/W 8-pin SOIC package 3.0 °C/W 8-pin DFN-S 4x4x0.9 mm package 2.6 °C/W 8-pin DFN-S 6x5 mm package TH03 TJ Junction Temperature 150 °C For derated power calculations TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD (NOTE 1) TH06 PI/O I/O Power Dissipation — W PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = (TJ - TA)/θJA (NOTE 2, 3) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. 3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (PDER). © 2007 Microchip Technology Inc. DS41211D-page 123

PIC12F683 15.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 15-3: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins 15 pF for OSC2 output DS41211D-page 124 © 2007 Microchip Technology Inc.

PIC12F683 15.8 AC Characteristics: PIC12F683 (Industrial, Extended) FIGURE 15-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode DC — 4 MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) 27 — (cid:129) μs LP Oscillator mode 250 — (cid:129) ns XT Oscillator mode 50 — (cid:129) ns HS Oscillator mode 50 — (cid:129) ns EC Oscillator mode Oscillator Period(1) — 30.5 — μs LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TosH, External CLKIN High, 2 — — μs LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 — (cid:129) ns LP oscillator TosF External CLKIN Fall 0 — (cid:129) ns XT oscillator 0 — (cid:129) ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. © 2007 Microchip Technology Inc. DS41211D-page 125

PIC12F683 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Freq. Sym Characteristic Min Typ† Max Units Conditions No. Tolerance OS06 TWARM Internal Oscillator Switch — — — 2 TOSC Slowest clock when running(3) OS07 TSC Fail-Safe Sample Clock — — 21 — ms LFINTOSC/64 Period(1) OS08 HFOSC Internal Calibrated ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C HFINTOSC Frequency(2) ±2% 7.84 8.0 8.16 MHz 2.5V ≤ VDD ≤ 5.5V, 0°C ≤ TA ≤ +85°C ±5% 7.60 8.0 8.40 MHz 2.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ +85°C (Ind.), -40°C ≤ TA ≤ +125°C (Ext.) OS09* LFOSC Internal Uncalibrated — 15 31 45 kHz LFINTOSC Frequency OS10* TIOSC HFINTOSC Oscillator — 5.5 12 24 μs VDD = 2.0V, -40°C to +85°C ST Wake-up from Sleep — 3.5 7 14 μs VDD = 3.0V, -40°C to +85°C Start-up Time — 3 6 11 μs VDD = 5.0V, -40°C to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1μF and 0.01μF values in parallel are recommended. 3: By design. DS41211D-page 126 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 15-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 Fosc OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. OS11 TOSH2CKL FOSC↑ to CLKOUT↓ (1) — — 70 ns VDD = 5.0V OS12 TOSH2CKH FOSC↑ to CLKOUT↑ (1) — — 72 ns VDD = 5.0V OS13 TCKL2IOV CLKOUT↓ to Port out valid(1) — — 20 ns OS14 TIOV2CKH Port input valid before CLKOUT↑(1) TOSC + 200 ns — — ns OS15* TOSH2IOV FOSC↑ (Q1 cycle) to Port out valid — 50 70 ns VDD = 5.0V OS16 TOSH2IOI FOSC↑ (Q2 cycle) to Port input invalid 50 — — ns VDD = 5.0V (I/O in hold time) OS17 TIOV2OSH Port input valid to FOSC↑ (Q2 cycle) 20 — — ns (I/O in setup time) OS18 TIOR Port output rise time(2) — 15 72 ns VDD = 2.0V — 40 32 VDD = 5.0V OS19 TIOF Port output fall time(2) — 28 55 ns VDD = 2.0V — 15 30 VDD = 5.0V OS20* TINP INT pin input high or low time 25 — — ns OS21* TGPP GPIO interrupt-on-change new input TCY — — ns level time * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. DS41211D-page 127

PIC12F683 FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR + VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33* (due to BOR) * 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. DS41211D-page 128 © 2007 Microchip Technology Inc.

PIC12F683 TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — μs VDD = 5V, -40°C to +85°C 5 — — μs VDD = 5V 31 TWDT Watchdog Timer Time-out 10 16 29 ms VDD = 5V, -40°C to +85°C Period (No Prescaler) 10 16 31 ms VDD = 5V 32 TOST Oscillation Start-up Timer — 1024 — TOSC (NOTE 3) Period(1, 2) 33* TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O High-impedance from — — 2.0 μs MCLR Low or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage 2.0 — 2.2 V (NOTE 4) 36* VHYST Brown-out Reset Hysteresis — 50 — mV 37* TBOR Brown-out Reset Minimum 100 — — μs VDD ≤ VBOR Detection Period * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1μF and 0.01μF values in parallel are recommended. © 2007 Microchip Technology Inc. DS41211D-page 129

PIC12F683 FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range — 32.768 — kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41211D-page 130 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: Refer to Figure15-3 for load conditions. TABLE 15-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP1 Input Period 3TCY + 40 — — ns N = prescale N value (1, 4 or 16) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. DS41211D-page 131

PIC12F683 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristics Min Typ† Max Units Comments No. CM01 VOS Input Offset Voltage — ± 5.0 ± 10 mV (VDD - 1.5)/2 CM02 VCM Input Common Mode Voltage 0 — VDD – 1.5 V CM03* CMRR Common Mode Rejection Ratio +55 — — dB CM04* TRT Response Time Falling — 150 600 ns (NOTE 1) Rising — 200 1000 ns CM05* TMC2COV Comparator Mode Change to — — 10 μs Output Valid * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD-1.5)/2-100mV to (VDD-1.5)/2+20mV. TABLE 15-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristics Min Typ† Max Units Comments No. CV01* CLSB Step Size(2) — VDD/24 — V Low Range (VRR = 1) — VDD/32 — V High Range (VRR = 0) CV02* CACC Absolute Accuracy — — ± 1/2 LSb Low Range (VRR = 1) — — ± 1/2 LSb High Range (VRR = 0) CV03* CR Unit Resistor Value (R) — 2k — Ω CV04* CST Settling Time(1) — — 10 μs * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section8.11 “Comparator Voltage Reference” for more information. DS41211D-page 132 © 2007 Microchip Technology Inc.

PIC12F683 TABLE 15-9: PIC12F683 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. AD01 NR Resolution — — 10 bits bit AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error — — ±1 LSb VREF = 5.12V AD07 EGN Gain Error — — ±1 LSb VREF = 5.12V AD06 VREF Reference Voltage(3) 2.2 — — V AD06A 2.7 VDD Absolute minimum to ensure 1LSb accuracy AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended — — 10 kΩ Impedance of Analog Voltage Source AD09* IREF VREF Input Current(3) 10 — 1000 μA During VAIN acquisition. Based on differential of VHOLD to VAIN. — — 50 μA During A/D conversion cycle. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. © 2007 Microchip Technology Inc. DS41211D-page 133

PIC12F683 TABLE 15-10: PIC12F683 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. AD130* TAD A/D Clock Period 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μs TOSC-based, VREF full range A/D Internal RC ADCS<1:0> = 11 (ADRC mode) Oscillator Period 3.0 6.0 9.0 μs At VDD = 2.5V 1.6 4.0 6.0 μs At VDD = 5.0V AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to new data in A/D (not including Result register. Acquisition Time)(1) AD132* TACQ Acquisition Time 11.5 — μs AD133* TAMP Amplifier Settling Time — — 5 μs AD134 TGO Q4 to A/D Clock Start — TOSC/2 — — — TOSC/2 + TCY — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section9.3 “A/D Acquisition Requirements” for minimum conditions. DS41211D-page 134 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 15-10: PIC12F683 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (TOSC/2(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. FIGURE 15-11: PIC12F683 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 A/D CLK A/D Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. © 2007 Microchip Technology Inc. DS41211D-page 135

PIC12F683 NOTES: DS41211D-page 136 © 2007 Microchip Technology Inc.

PIC12F683 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean+3σ) or (mean-3σ) respectively, where σ is a standard deviation, over each temperature range. FIGURE 16-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 3.5 Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst-case Temp) + 3σ 5.5V (-40°C to 125°C) 5.0V 2.5 A) 2.0 4.0V m (D D 1.5 I 3.0V 1.0 2.0V 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC © 2007 Microchip Technology Inc. DS41211D-page 137

PIC12F683 FIGURE 16-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-cas e Temp) + 3σ 5.5V (-40°C to 125°C) 5.0V 3.0 2.5 4.0V A) m 2.0 (D D I 3.0V 1.5 2.0V 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) Typical IDD vs. FOSC Over Vdd HS Mode 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-ca se Temp) + 3σ (-40°C to 125°C) 5.5V 3.0 5.0V 2.5 4.5V A) m 2.0 (D D I 1.5 4.0V 1.0 3.5V 3.0V 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC DS41211D-page 138 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) Maximum IDD vs. FOSC Over Vdd HS Mode 5.0 Typical: Statistical Mean @25°C 4.5 Maximum: Mean (Worst-case Temp) + 3σ 4.0 (-40°C to 125°C) 5.5V 3.5 5.0V 3.0 A) 4.5V m 2.5 (D D I 2.0 1.5 4.0V 3.5V 1.0 3.0V 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC FIGURE 16-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE) XT Mode 900 Typical: Statistical Mean @25°C 800 Maximum: Mean (Worst-ca se Temp) + 3σ (-40°C to 125°C) 700 600 A) 500 μ 4 MHz (D D 400 I 300 1 MHz 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41211D-page 139

PIC12F683 FIGURE 16-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,000 800 A) μ 4 MHz (D ID 600 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-7: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) EXTRC Mode 800 Typical: Statistical Mean @25°C 700 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 600 500 4 MHz A) μ 400 (D D I 300 1 MHz 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41211D-page 140 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-8: MAXIMUM IDD vs. VDD (EXTRC MODE) EXTRC Mode 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,000 4 MHz 800 A) μ (D ID 600 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-9: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz) LFINTOSC Mode, 31KHZ 80 Typical: Statistical Mean @25°C 70 Maximum: Mean (Worst-c ase Temp) + 3σ (-40°C to 125°C) 60 50 Maximum A) μ (D 40 D I 30 Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41211D-page 141

PIC12F683 FIGURE 16-10: IDD vs. VDD (LP MODE) LP Mode 70 Typical: Statistical Mean @25°C 60 Maximum: Mean (Worst-cas e Temp) + 3σ (-40°C to 125°C) 50 32 kHz Maximum 40 A) μ (D D 30 I 20 32 kHz Typical 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 1,600 Typical: Statistical Mean @25°C 5.5V 1,400 Maximum: Mean (Worst-c ase Temp) + 3σ (-40°C to 125°C) 5.0V 1,200 1,000 4.0V A) μ (D 800 D 3.0V I 600 2.0V 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC DS41211D-page 142 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 2,000 Typical: Statistical Mean @25°C 5.5V 1,800 Maximum: Mean (Worst-c ase Temp) + 3σ (-40°C to 125°C) 5.0V 1,600 1,400 1,200 4.0V A) μ (DD 1,000 3.0V I 800 600 2.0V 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC FIGURE 16-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 0.35 0.30 A) 0.25 μ (D P 0.20 I 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41211D-page 143

PIC12F683 FIGURE 16-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 Typical: Statistical Mean @25°C 16.0 MMaaxxiimmuumm:: MMeeaann +(W 3oσrst-case Temp) + 3σ (-40°C to 125°C) 14.0 Max. 125°C 12.0 A) 10.0 μ (D P 8.0 I 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-15: COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED) 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 140 (-40°C to 125°C) 120 Maximum A) 100 μ (PD 80 Typical I 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41211D-page 144 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-16: BOR IPD vs. VDD OVER TEMPERATURE 160 Typical: Statistical Mean @25°C 140 Maximum: Mean (Worst-ca se Temp) + 3σ (-40°C to 125°C) 120 100 Maximum A) μ (D 80 P I Typical 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-17: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE Typical 3.0 TTyyppicicaal:l: SSttaattisistticicaal l MMeeaann @@2255°°CC Maximum: Mean (Worst-case Temp) + 3σ 2.5 (-40°C to 125°C) 2.0 A) μ (D 1.5 P I 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41211D-page 145

PIC12F683 FIGURE 16-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 20.0 Max. 125°C 15.0 Maximum: Mean (Worst-case Temp) + 3σ A) μ (-40°C to 125°C) (D P I 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-19: WDT PERIOD vs. VDD OVER TEMPERATURE 30 Typical: Statistical Mean @25°C 28 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. (125°C) 26 Max. (85°C) 24 22 s) m e ( 20 m Ti Typical 18 16 14 Minimum 12 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41211D-page 146 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-20: WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V) Vdd = 5V 30 Typical: Statistical Mean @25°C 28 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 26 Maximum 24 22 s) m e ( 20 m Typical Ti 18 16 Minimum 14 12 10 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 16-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range 140 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 120 (-40°C to 125°C) 100 Max. 125°C 80 A) μ (D Max. 85°C IP 60 Typical 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41211D-page 147

PIC12F683 FIGURE 16-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) 180 Typical: Statistical Mean @25°C 160 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 140 120 Max. 125°C A) 100 μ (D Max. 85°C P 80 I Typical 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-23: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.6 0.5 Max. 85°C V) (L 0.4 O V 0.3 Typical 25°C 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) DS41211D-page 148 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-24: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 MaximTuympi:c aMl:e Santa (tiWstoicraslt -Mcaesaen T@em25p×)C + 3σ Maximum: Mea n(s-4 +0 ×3C to 125×C) (-40°C to 125°C) Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 16-25: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) © 2007 Microchip Technology Inc. DS41211D-page 149

PIC12F683 FIGURE 16-26: VOH vs. IOH OVER TE(MVDPDE =R 5AVT, -U40R×EC T(VOD 1D2 5=× C5).0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 16-27: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41211D-page 150 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-29: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 45.0 Typical: Statistical Mean @25°C 40.0 MMaaxxiimmuumm:: MMeeaa nn(- 4+(W0 3×oCrs tto-c 1a2s5e× TCe)mp) + 3σ (-40°C to 125°C) 35.0 Max. 125°C 30.0 A) 25.0 m (PD 20.0 I 15.0 Max. 85°C 10.0 5.0 Typ. 25°C 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41211D-page 151

PIC12F683 FIGURE 16-30: COMPARATOR RESPONSE TIME (RISING EDGE) 531 806 1000 900 800 Max. 125°C 700 S) n e ( 600 Note: VCM = VDD - 1.5V)/2 m Ti V+ input = VCM Max. 85°C e 500 V- input = Transition from VCM + 100MV to VCM - 20MV s n o p 400 s e R 300 200 Typ. 25°C Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) FIGURE 16-31: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 800 Max. 125°C 700 S) n 600 Note: VCM = VDD - 1.5V)/2 me ( V+ input = VCM Max. 85°C Ti 500 V- input = Transition from VCM - 100MV to VCM + 20MV e s n 400 o p s Re 300 Typ. 25°C 200 Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) DS41211D-page 152 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-32: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) LFINTOSC 31Khz 45,000 40,000 Max. -40°C 35,000 Typ. 25°C 30,000 z) H y ( 25,000 c n e qu 20,000 Min. 85°C e r F Min. 125°C 15,000 10,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 5,000 (-40°C to 125°C) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-33: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 125°C (-40°C to 125°C) 6 85°C s) μ 25°C e ( 4 m Ti -40°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41211D-page 153

PIC12F683 FIGURE 16-34: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C 14 Maximum: Mean (Worst-case Temp) + 3σ 85°C (-40°C to 125°C) 12 25°C 10 s) -40°C μ e ( 8 m Ti 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-35: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C 20 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 15 s) 85°C μ e ( m Ti 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41211D-page 154 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-36: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 10 9 Typical: Statistical Mean @25°C 8 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 7 85°C 6 s) 25°C μ e ( 5 m Ti -40°C 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 3 2 %) n ( 1 o ati br 0 ali m C -1 o e fr -2 g n a -3 h C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41211D-page 155

PIC12F683 FIGURE 16-38: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 3 %) n ( 2 o ati 1 r b Cali 0 m o -1 r e f ng -2 a h C -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 3 %) 2 n ( o 1 ati r alib 0 C m -1 o r e f -2 g n ha -3 C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD ( V) DS41211D-page 156 © 2007 Microchip Technology Inc.

PIC12F683 FIGURE 16-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 3 %) 2 n ( o 1 ati r b 0 ali C m -1 o r e f -2 g n ha -3 C -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD ( V) © 2007 Microchip Technology Inc. DS41211D-page 157

PIC12F683 NOTES: DS41211D-page 158 © 2007 Microchip Technology Inc.

PIC12F683 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 8-Lead PDIP Example XXXXXXXX 12F683 XXXXXNNN I/P e 3 017 YYWW 0415 8-Lead SOIC (3.90 mm) Example XXXXXXXX 12F683 e3 XXXXYYWW I/SN0415 NNN 017 8-Lead DFN (4x4x0.9 mm) Example XXXXXX 12F683 XXXXXX I/MD e3 YYWW 0415 NNN 017 8-Lead DFN-S (6x5 mm) Example XXXXXXX 12F683 XXXXXXX I/MF e3 XXYYWW 0415 NNN 017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PIC® device marking consists of Microchip part number, year code, week code and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2007 Microchip Technology Inc. DS41211D-page 159

PIC12F683 17.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L A1 c e eB b1 b Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-018B DS41211D-page 160 © 2007 Microchip Technology Inc.

PIC12F683 8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 b h α h c A A2 φ A1 L L1 β Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-057B © 2007 Microchip Technology Inc. DS41211D-page 161

PIC12F683 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e b N N L E K E2 EXPOSED PAD 1 2 2 1 NOTE 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW A3 A A1 NOTE 2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.80 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 4.00 BSC Exposed Pad Width E2 0.00 2.20 2.80 Overall Width E 4.00 BSC Exposed Pad Length D2 0.00 3.00 3.60 Contact Width b 0.25 0.30 0.35 Contact Length L 0.30 0.55 0.65 Contact-to-Exposed Pad K 0.20 – – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-131C DS41211D-page 162 © 2007 Microchip Technology Inc.

PIC12F683 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] PUNCH SINGULATED Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e D1 b L N N K E E2 E1 EXPOSED PAD NOTE 1 1 2 2 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW φ A A2 A1 A3 NOTE 2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – 0.85 1.00 Molded Package Thickness A2 – 0.65 0.80 Standoff A1 0.00 0.01 0.05 Base Thickness A3 0.20 REF Overall Length D 4.92 BSC Molded Package Length D1 4.67 BSC Exposed Pad Length D2 3.85 4.00 4.15 Overall Width E 5.99 BSC Molded Package Width E1 5.74 BSC Exposed Pad Width E2 2.16 2.31 2.46 Contact Width b 0.35 0.40 0.47 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – Model Draft Angle Top φ – – 12° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-113B © 2007 Microchip Technology Inc. DS41211D-page 163

PIC12F683 NOTES: DS41211D-page 164 © 2007 Microchip Technology Inc.

PIC12F683 APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM REVISION HISTORY OTHER PIC® DEVICES Revision A This discusses some of the issues in migrating from This is a new data sheet. other PIC devices to the PIC12F683 device. Revision B B.1 PIC16F676 to PIC12F683 Rewrites of the Oscillator and Special Features of the TABLE B-1: FEATURE COMPARISON CPU sections. General corrections to Figures and Feature PIC16F676 PIC12F683 formatting. Max Operating 20MHz 20MHz Revision C Speed Max Program 1024 2048 Revisions throughout document. Incorporated Golden Memory (Words) Chapters. SRAM (bytes) 64 128 Revision D A/D Resolution 10-bit 10-bit Data EEPROM 128 256 Replaced Package Drawings; Revised Product ID (Bytes) Section (SN package to 3.90 mm); Replaced PICmicro Timers (8/16-bit) 1/1 2/1 with PIC; Replaced Dev Tool Section. Oscillator Modes 8 8 Brown-out Reset Y Y Internal Pull-ups RA0/1/2/4/5 GP0/1/2/4/5, MCLR Interrupt-on-change RA0/1/2/3/4/5 GP0/1/2/3/4/5 Comparator 1 1 ECCP N N Ultra Low-Power N Y Wake-Up Extended WDT N Y Software Control N Y Option of WDT/BOR INTOSC 4MHz 32kHz- Frequencies 8MHz Clock Switching N Y Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. © 2007 Microchip Technology Inc. DS41211D-page 165

PIC12F683 NOTES: DS41211D-page 166 © 2007 Microchip Technology Inc.

PIC12F683 INDEX A Timer2........................................................................49 TMR0/WDT Prescaler................................................41 A/D Watchdog Timer (WDT)..............................................96 Specifications....................................................133, 134 Brown-out Reset (BOR)......................................................87 Absolute Maximum Ratings..............................................115 Associated..................................................................88 AC Characteristics Calibration..................................................................87 Industrial and Extended............................................125 Specifications...........................................................129 Load Conditions........................................................124 Timing and Characteristics.......................................128 ADC....................................................................................61 Acquisition Requirements...........................................67 C Associated registers....................................................69 C Compilers Block Diagram.............................................................61 MPLAB C18..............................................................112 Calculating Acquisition Time.......................................67 MPLAB C30..............................................................112 Channel Selection.......................................................61 Calibration Bits....................................................................85 Configuration...............................................................61 Capture Module. See Capture/Compare/PWM (CCP) Configuring Interrupt...................................................64 Capture/Compare/PWM (CCP)..........................................75 Conversion Clock........................................................62 Associated registers w/ Capture, Compare Conversion Procedure................................................64 and Timer1.........................................................81 GPIO Configuration.....................................................61 Associated registers w/ PWM and Timer2..................81 Internal Sampling Switch (RSS) IMPEDANCE................67 Capture Mode.............................................................76 Interrupts.....................................................................63 CCPx Pin Configuration..............................................76 Operation....................................................................63 Compare Mode...........................................................77 Operation During Sleep..............................................64 CCPx Pin Configuration......................................77 Reference Voltage (VREF)...........................................62 Software Interrupt Mode...............................76, 77 Result Formatting........................................................63 Special Event Trigger.........................................77 Source Impedance......................................................67 Timer1 Mode Selection.................................76, 77 Special Event Trigger..................................................64 Prescaler....................................................................76 Starting an A/D Conversion........................................63 PWM Mode.................................................................78 ADCON0 Register...............................................................65 Duty Cycle..........................................................79 ADRESH Register (ADFM = 0)...........................................66 Effects of Reset..................................................80 ADRESH Register (ADFM = 1)...........................................66 Example PWM Frequencies and ADRESL Register (ADFM = 0)............................................66 Resolutions, 20 MHZ..................................79 ADRESL Register (ADFM = 1)............................................66 Example PWM Frequencies and Analog Input Connection Considerations............................52 Resolutions, 8 MHz....................................79 Analog-to-Digital Converter. See ADC Operation in Sleep Mode....................................80 ANSEL Register..................................................................33 Setup for Operation............................................80 Assembler System Clock Frequency Changes....................80 MPASM Assembler...................................................112 PWM Period...............................................................79 B Setup for PWM Operation..........................................80 Timer Resources........................................................75 Block Diagrams CCP. See Capture/Compare/PWM (CCP) (CCP) Capture Mode Operation.................................76 CCP1CON Register............................................................75 ADC............................................................................61 Clock Sources ADC Transfer Function...............................................68 External Modes...........................................................21 Analog Input Model...............................................52, 68 EC......................................................................21 CCP PWM...................................................................78 HS......................................................................22 Clock Source...............................................................19 LP.......................................................................22 Comparator.................................................................51 OST....................................................................21 Compare.....................................................................77 RC......................................................................23 Crystal Operation........................................................22 XT.......................................................................22 External RC Mode.......................................................23 Internal Modes............................................................23 Fail-Safe Clock Monitor (FSCM).................................29 Frequency Selection...........................................25 GP1 Pin.......................................................................37 HFINTOSC.........................................................23 GP2 Pin.......................................................................37 INTOSC..............................................................23 GP3 Pin.......................................................................38 INTOSCIO..........................................................23 GP4 Pin.......................................................................38 LFINTOSC..........................................................25 GP5 Pin.......................................................................39 Clock Switching..................................................................27 In-Circuit Serial Programming Connections..............100 Code Examples Interrupt Logic.............................................................93 A/D Conversion..........................................................64 MCLR Circuit...............................................................86 Assigning Prescaler to Timer0....................................42 On-Chip Reset Circuit.................................................85 Assigning Prescaler to WDT.......................................42 PIC12F683....................................................................5 Changing Between Capture Prescalers.....................76 Resonator Operation...................................................22 Data EEPROM Read..................................................73 Timer1.........................................................................44 Data EEPROM Write..................................................73 © 2007 Microchip Technology Inc. DS41211D-page 167

PIC12F683 Indirect Addressing.....................................................18 F Initializing GPIO..........................................................31 Fail-Safe Clock Monitor......................................................29 Saving STATUS and W Registers in RAM.................95 Fail-Safe Condition Clearing.......................................29 Ultra Low-Power Wake-up Initialization......................35 Fail-Safe Detection.....................................................29 Write Verify.................................................................73 Fail-Safe Operation.....................................................29 Code Protection..................................................................99 Reset or Wake-up from Sleep....................................29 Comparator.........................................................................51 Firmware Instructions.......................................................101 C2OUT as T1 Gate.....................................................57 Fuses. See Configuration Bits Configurations.............................................................53 I/O Operating Modes...................................................53 G Interrupts.....................................................................55 General Purpose Register File.............................................8 Operation..............................................................51, 54 GPIO...................................................................................31 Operation During Sleep..............................................56 Additional Pin Functions.............................................32 Response Time...........................................................54 ANSEL Register.................................................32 Synchronizing COUT w/Timer1..................................57 Interrupt-on-Change...........................................32 Comparator Module Ultra Low-Power Wake-up............................32, 35 Associated registers....................................................59 Weak Pull-up......................................................32 Comparator Voltage Reference (CVREF) Associated Registers..................................................39 Response Time...........................................................54 GP0............................................................................36 Comparator Voltage Reference (CVREF)............................58 GP1............................................................................37 Effects of a Reset........................................................56 GP2............................................................................37 Specifications............................................................132 GP3............................................................................38 Comparators GP4............................................................................38 C2OUT as T1 Gate.....................................................45 GP5............................................................................39 Effects of a Reset........................................................56 Pin Descriptions and Diagrams..................................36 Specifications............................................................132 Specifications...........................................................127 Compare Module. See Capture/Compare/PWM (CCP) GPIO Register....................................................................31 CONFIG Register................................................................84 Configuration Bits................................................................83 I CPU Features.....................................................................83 ID Locations........................................................................99 Customer Change Notification Service.............................171 In-Circuit Debugger...........................................................100 Customer Notification Service...........................................171 In-Circuit Serial Programming (ICSP)...............................100 Customer Support.............................................................171 Indirect Addressing, INDF and FSR Registers...................18 D Instruction Format.............................................................101 Instruction Set...................................................................101 Data EEPROM Memory ADDLW.....................................................................103 Associated Registers..................................................74 ADDWF.....................................................................103 Code Protection....................................................71, 74 ANDLW.....................................................................103 Data Memory Organization...................................................7 ANDWF.....................................................................103 Map of the PIC12F683..................................................8 BCF..........................................................................103 DC and AC Characteristics BSF...........................................................................103 Graphs and Tables...................................................137 BTFSC......................................................................103 DC Characteristics BTFSS......................................................................104 Extended and Industrial............................................121 CALL.........................................................................104 Industrial and Extended............................................117 CLRF........................................................................104 Development Support.......................................................111 CLRW.......................................................................104 Device Overview...................................................................5 CLRWDT..................................................................104 E COMF.......................................................................104 DECF........................................................................104 EEADR Register.................................................................71 DECFSZ...................................................................105 EECON1 Register...............................................................72 GOTO.......................................................................105 EECON2 Register...............................................................72 INCF.........................................................................105 EEDAT Register..................................................................71 INCFSZ.....................................................................105 EEPROM Data Memory IORLW......................................................................105 Avoiding Spurious Write..............................................74 IORWF......................................................................105 Reading.......................................................................73 MOVF.......................................................................106 Write Verify.................................................................73 MOVLW....................................................................106 Writing.........................................................................73 MOVWF....................................................................106 Effects of Reset NOP..........................................................................106 PWM mode.................................................................80 RETFIE.....................................................................107 Electrical Specifications....................................................115 RETLW.....................................................................107 Enhanced Capture/Compare/PWM (ECCP) RETURN...................................................................107 Specifications............................................................131 RLF...........................................................................108 Errata....................................................................................3 RRF..........................................................................108 SLEEP......................................................................108 DS41211D-page 168 © 2007 Microchip Technology Inc.

PIC12F683 SUBLW.....................................................................108 Oscillator Switching SUBWF.....................................................................109 Fail-Safe Clock Monitor..............................................29 SWAPF.....................................................................109 Two-Speed Clock Start-up.........................................27 XORLW.....................................................................109 OSCTUNE Register............................................................24 XORWF.....................................................................109 P INTCON Register................................................................14 Internal Oscillator Block Packaging.........................................................................159 INTOSC Details.......................................................................160 Specifications............................................126, 127 Marking.....................................................................159 Internal Sampling Switch (RSS) IMPEDANCE........................67 PCL and PCLATH...............................................................18 Internet Address................................................................171 Computed GOTO.......................................................18 Interrupts.............................................................................92 Stack...........................................................................18 ADC............................................................................64 PCON Register.............................................................17, 88 Associated Registers..................................................94 PICSTART Plus Development Programmer.....................114 Comparator.................................................................55 PIE1 Register.....................................................................15 Context Saving............................................................95 Pin Diagram..........................................................................2 Data EEPROM Memory Write....................................72 Pinout Descriptions GP2/INT......................................................................92 PIC12F683...................................................................6 GPIO Interrupt-on-change..........................................93 PIR1 Register.....................................................................16 Interrupt-on-Change....................................................32 Power-Down Mode (Sleep).................................................98 Timer0.........................................................................93 Power-On Reset (POR)......................................................86 TMR1..........................................................................46 Power-up Timer (PWRT)....................................................86 INTOSC Specifications.............................................126, 127 Specifications...........................................................129 IOC Register.......................................................................34 Precision Internal Oscillator Parameters..........................127 Prescaler L Shared WDT/Timer0...................................................42 Load Conditions................................................................124 Switching Prescaler Assignment................................42 Program Memory Organization.............................................7 M Map and Stack for the PIC12F683...............................7 MCLR..................................................................................86 Programming, Device Instructions....................................101 Internal........................................................................86 R Memory Organization Data EEPROM Memory..............................................71 Reader Response.............................................................172 Microchip Internet Web Site..............................................171 Read-Modify-Write Operations.........................................101 Migrating from other PIC Devices.....................................165 Registers MPLAB ASM30 Assembler, Linker, Librarian...................112 ADCON0 (ADC Control 0)..........................................65 MPLAB ICD 2 In-Circuit Debugger...................................113 ADRESH (ADC Result High) with ADFM = 0)............66 MPLAB ICE 2000 High-Performance Universal ADRESH (ADC Result High) with ADFM = 1)............66 In-Circuit Emulator....................................................113 ADRESL (ADC Result Low) with ADFM = 0)..............66 MPLAB ICE 4000 High-Performance Universal ADRESL (ADC Result Low) with ADFM = 1)..............66 In-Circuit Emulator....................................................113 ANSEL (Analog Select)..............................................33 MPLAB Integrated Development Environment Software..111 CCP1CON (CCP1 Control)........................................75 MPLAB PM3 Device Programmer....................................113 CMCON0 (Comparator Control) Register...................56 MPLINK Object Linker/MPLIB Object Librarian................112 CMCON1 (Comparator Control) Register...................57 CONFIG (Configuration Word)...................................84 O EEADR (EEPROM Address)......................................71 OPCODE Field Descriptions.............................................101 EECON1 (EEPROM Control 1)..................................72 OPTION Register..........................................................13, 43 EECON2 (EEPROM Control 2)..................................72 OSCCON Register..............................................................20 EEDAT (EEPROM Data)............................................71 Oscillator GPIO...........................................................................31 Associated registers..............................................30, 48 INTCON (Interrupt Control)........................................14 Oscillator Module................................................................19 IOC (Interrupt-on-Change GPIO)...............................34 EC...............................................................................19 OPTION_REG (OPTION).....................................13, 43 HFINTOSC..................................................................19 OSCCON (Oscillator Control).....................................20 HS...............................................................................19 OSCTUNE (Oscillator Tuning)....................................24 INTOSC......................................................................19 PCON (Power Control Register).................................17 INTOSCIO...................................................................19 PCON (Power Control)...............................................88 LFINTOSC..................................................................19 PIE1 (Peripheral Interrupt Enable 1)..........................15 LP................................................................................19 PIR1 (Peripheral Interrupt Register 1)........................16 RC...............................................................................19 Reset Values..............................................................90 RCIO...........................................................................19 Reset Values (Special Registers)...............................91 XT...............................................................................19 STATUS.....................................................................12 Oscillator Parameters.......................................................126 T1CON.......................................................................47 Oscillator Specifications....................................................125 T2CON.......................................................................50 Oscillator Start-up Timer (OST) TRISIO (Tri-State GPIO)............................................32 Specifications............................................................129 VRCON (Voltage Reference Control).........................58 © 2007 Microchip Technology Inc. DS41211D-page 169

PIC12F683 WDTCON (Watchdog Timer Control)..........................97 INT Pin Interrupt.........................................................94 WPU (Weak Pull-Up GPIO)........................................34 Internal Oscillator Switch Timing................................26 Resets.................................................................................85 Reset, WDT, OST and Power-up Timer...................128 Brown-out Reset (BOR)..............................................85 Time-out Sequence on Power-up (Delayed MCLR)...89 MCLR Reset, Normal Operation.................................85 Time-out Sequence on Power-up (MCLR with VDD)..89 MCLR Reset, Sleep....................................................85 Timer0 and Timer1 External Clock...........................130 Power-on Reset (POR)...............................................85 Timer1 Incrementing Edge.........................................46 WDT Reset, Normal Operation...................................85 Two Speed Start-up....................................................28 WDT Reset, Sleep......................................................85 Wake-up from Sleep Through Interrupt......................99 Revision History................................................................165 Timing Parameter Symbology..........................................124 TRISIO Register.................................................................32 S Two-Speed Clock Start-up Mode........................................27 Sleep U Power-Down Mode.....................................................98 Wake-up......................................................................98 Ultra Low-Power Wake-up............................................32, 35 Wake-up Using Interrupts...........................................98 V Software Simulator (MPLAB SIM).....................................112 Special Event Trigger..........................................................64 Voltage Reference. See Comparator Voltage Special Function Registers...................................................8 Reference (CVREF) STATUS Register................................................................12 Voltage References Associated registers...................................................59 T VREF. SEE ADC Reference Voltage T1CON Register..................................................................47 W T2CON Register..................................................................50 Thermal Considerations....................................................123 Wake-up Using Interrupts...................................................98 Time-out Sequence.............................................................88 Watchdog Timer (WDT)......................................................96 Timer0.................................................................................41 Associated Registers..................................................97 Associated Registers..................................................43 Clock Source..............................................................96 External Clock.............................................................42 Modes.........................................................................96 Interrupt.................................................................13, 43 Period.........................................................................96 Operation..............................................................41, 44 Specifications...........................................................129 Specifications............................................................130 WDTCON Register.............................................................97 T0CKI..........................................................................42 WPU Register.....................................................................34 Timer1.................................................................................44 WWW Address.................................................................171 Associated registers....................................................48 WWW, On-Line Support.......................................................3 Asynchronous Counter Mode.....................................45 Reading and Writing...........................................45 Interrupt.......................................................................46 Modes of Operation....................................................44 Operation During Sleep..............................................46 Oscillator.....................................................................45 Prescaler.....................................................................45 Specifications............................................................130 Timer1 Gate Inverting Gate.....................................................45 Selecting Source...........................................45, 57 Synchronizing COUT w/Timer1..........................57 TMR1H Register.........................................................44 TMR1L Register..........................................................44 Timer2 Associated registers....................................................50 Timers Timer1 T1CON................................................................47 Timer2 T2CON................................................................50 Timing Diagrams A/D Conversion.........................................................135 A/D Conversion (Sleep Mode)..................................135 Brown-out Reset (BOR)............................................128 Brown-out Reset Situations........................................87 CLKOUT and I/O.......................................................127 Clock Timing.............................................................125 Comparator Output.....................................................51 Enhanced Capture/Compare/PWM (ECCP).............131 Fail-Safe Clock Monitor (FSCM).................................30 DS41211D-page 170 © 2007 Microchip Technology Inc.

PIC12F683 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to (cid:129) Distributor or Representative customers. Accessible by using your favorite Internet (cid:129) Local Sales Office browser, the web site contains the following informa- (cid:129) Field Application Engineer (FAE) tion: (cid:129) Technical Support (cid:129) Product Support – Data sheets and errata, appli- (cid:129) Development Systems Information Line cation notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, representa- documents, latest software releases and archived tive or field application engineer (FAE) for support. software Local sales offices are also available to help custom- (cid:129) General Technical Support – Frequently Asked ers. A listing of sales offices and locations is included in Questions (FAQ), technical support requests, the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com (cid:129) Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Micro- chip sales offices, distributors and factory repre- sentatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notifi- cation and follow the registration instructions. © 2007 Microchip Technology Inc. DS41211D-page 171

PIC12F683 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC12F683 Literature Number: DS41211D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41211D-page 172 © 2007 Microchip Technology Inc.

PIC12F683 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC12F683-E/P 301 = Extended Temp., PDIP Range package, 20 MHz, QTP pattern #301 b) PIC12F683-I/SN = Industrial Temp., SOIC package, 20 MHz Device: PIC12F683(1), PIC12F683T(2) VDD range 2.0V to 5.5V Temperature I = -40°C to +85°C(Industrial) Range: E = -40°C to +125°C (Extended) Package: P = Plastic DIP MD = Dual-Flat, No Leads (DFN-S, 4x4x0.9 mm) MF = Dual-Flat, No Leads (DFN-S, 6x5 mm) SN = 8-lead Small Outline (3.90 mm) Note1: F = Standard Voltage Range LF = Wide Voltage Range Pattern: 3-digit Pattern Code for QTP (blank otherwise) 2: T=in tape and reel PLCC, and TQFP packages only. © 2007 Microchip Technology Inc. DS41211D-page 173

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