PIC12F629/675 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers  2010 Microchip Technology Inc. DS41190G

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-160-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41190G-page 2  2010 Microchip Technology Inc.

PIC12F629/675 8-Pin Flash-Based 8-Bit CMOS Microcontroller High-Performance RISC CPU: Low-Power Features: • Only 35 Instructions to Learn • Standby Current: - All single-cycle instructions except branches - 1nA @ 2.0V, typical • Operating Speed: • Operating Current: - DC – 20MHz oscillator/clock input - 8.5A @ 32kHz, 2.0V, typical - DC – 200ns instruction cycle - 100A @ 1MHz, 2.0V, typical • Interrupt Capability • Watchdog Timer Current • 8-Level Deep Hardware Stack - 300nA @ 2.0V, typical • Direct, Indirect, and Relative Addressing modes • Timer1 Oscillator Current: - 4A @ 32kHz, 2.0V, typical Special Microcontroller Features: Peripheral Features: • Internal and External Oscillator Options - Precision Internal 4MHz oscillator factory • 6 I/O Pins with Individual Direction Control calibrated to ±1% • High Current Sink/Source for Direct LED Drive - External Oscillator support for crystals and • Analog Comparator module with: resonators - One analog comparator - 5s wake-up from Sleep, 3.0V, typical - Programmable on-chip comparator voltage • Power-Saving Sleep mode reference (CVREF) module • Wide Operating Voltage Range – 2.0V to 5.5V - Programmable input multiplexing from device • Industrial and Extended Temperature Range inputs • Low-Power Power-on Reset (POR) - Comparator output is externally accessible • Power-up Timer (PWRT) and Oscillator Start-up • Analog-to-Digital Converter module (PIC12F675): Timer (OST) - 10-bit resolution • Brown-out Detect (BOD) - Programmable 4-channel input • Watchdog Timer (WDT) with Independent - Voltage reference input Oscillator for Reliable Operation • Timer0: 8-Bit Timer/Counter with 8-Bit • Multiplexed MCLR/Input Pin Programmable Prescaler • Interrupt-on-Pin Change • Enhanced Timer1: • Individual Programmable Weak Pull-ups - 16-bit timer/counter with prescaler • Programmable Code Protection - External Gate Input mode • High Endurance Flash/EEPROM Cell - Option to use OSC1 and OSC2 in LP mode - 100,000 write Flash endurance as Timer1 oscillator, if INTOSC mode - 1,000,000 write EEPROM endurance selected - Flash/Data EEPROM Retention: > 40 years • In-Circuit Serial ProgrammingTM (ICSPTM) via two pins Program Data Memory Memory 10-bit A/D Timers Device I/O Comparators Flash SRAM EEPROM (ch) 8/16-bit (words) (bytes) (bytes) PIC12F629 1024 64 128 6 — 1 1/1 PIC12F675 1024 64 128 6 4 1 1/1 *8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.  2010 Microchip Technology Inc. DS41190G-page 3

PIC12F629/675 Pin Diagrams 8-pin PDIP, SOIC, DFN-S, DFN VDD 1 8 VSS 9 GP5/T1CKI/OSC1/CLKIN 2 62 7 GP0/CIN+/ICSPDAT F 2 GP4/T1G/OSC2/CLKOUT 3 1 6 GP1/CIN-/ICSPCLK C GP3/MCLR/VPP 4 PI 5 GP2/T0CKI/INT/COUT VDD 1 8 VSS 5 7 GP5/T1CKI/OSC1/CLKIN 2 6 7 GP0/AN0/CIN+/ICSPDAT F 2 GP4/AN3/T1G/OSC2/CLKOUT 3 C1 6 GP1/AN1/CIN-/VREF/ICSPCLK GP3/MCLR/VPP 4 PI 5 GP2/AN2/T0CKI/INT/COUT DS41190G-page 4  2010 Microchip Technology Inc.

PIC12F629/675 Table of Contents 1.0 Device Overview......................................................................................................................................................................... 7 2.0 Memory Organization.................................................................................................................................................................. 9 3.0 GPIO Port .................................................................................................................................................................................21 4.0 Timer0 Module.......................................................................................................................................................................... 29 5.0 Timer1 Module with Gate Control............................................................................................................................................. 32 6.0 Comparator Module.................................................................................................................................................................. 37 7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) ...................................................................................................43 8.0 Data EEPROM Memory ............................................................................................................................................................49 9.0 Special Features of the CPU ....................................................................................................................................................53 10.0 Instruction Set Summary ...........................................................................................................................................................71 11.0 Development Support ...............................................................................................................................................................81 12.0 Electrical Specifications ............................................................................................................................................................85 13.0 DC and AC Characteristics Graphs and Tables .....................................................................................................................107 14.0 Packaging Information ............................................................................................................................................................117 Appendix A: Data Sheet Revision History .........................................................................................................................................127 Appendix B: Device Differences .......................................................................................................................................................127 Appendix C: Device Migrations .........................................................................................................................................................128 Appendix D: Migrating from other PIC® Devices ..............................................................................................................................128 Index .................................................................................................................................................................................................129 On-Line Support ................................................................................................................................................................................133 Systems Information and Upgrade Hot Line .....................................................................................................................................133 Reader Response .............................................................................................................................................................................134 Product Identification System ...........................................................................................................................................................135 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010 Microchip Technology Inc. DS41190G-page 5

PIC12F629/675 NOTES: DS41190G-page 6  2010 Microchip Technology Inc.

PIC12F629/675 1.0 DEVICE OVERVIEW Sheet, and is highly recommended reading for a better understanding of the device architecture and operation This document contains device specific information for of the peripheral modules. the PIC12F629/675. Additional information may be The PIC12F629 and PIC12F675 devices are covered found in the PIC® Mid-Range Reference Manual by this Data Sheet. They are identical, except the (DS33023), which may be obtained from your local PIC12F675 has a 10-bit A/D converter. They come in Microchip Sales Representative or downloaded from 8-pin PDIP, SOIC, MLF-S and DFN packages. the Microchip web site. The Reference Manual should Figure1-1 shows a block diagram of the PIC12F629/ be considered a complementary document to this Data 675 devices. Table1-1 shows the pinout description. FIGURE 1-1: PIC12F629/675 BLOCK DIAGRAM 13 Data Bus 8 Program Counter Flash GP0/AN0/CIN+ Program Memory RAM GP1/AN1/CIN-/VREF 8-Level Stack GP2/AN2/T0CKI/INT/COUT 1K x 14 (13-bit) RegFiisleters GP3/MCLR/VPP GP4/AN3/T1G/OSC2/CLKOUT 64 x 8 Program GP5/T1CKI/OSC1/CLKIN Bus 14 9 ARdAdMr(1) Addr MUX Instruction Reg Direct Addr 7 Indirect 8 Addr FSR Reg STATUS Reg Internal 8 4 MHz Oscillator 3 MUX Instruction Decode & Control Power-up Timer ALU Timing Oscillator Generation Start-up Timer 8 OSC1/CLKIN Power-on OSC2/CLKOUT VDD, VSS Reset W Reg Watchdog Timer Brown-out Detect T1G T1CKI Timer0 Timer1 T0CKI Analog Analog to Digital Converter Comparator EEDATA (PIC12F675 only) and reference 128 bytes 8 DATA EEPROM EEADDR CIN- CIN+ COUT VREF AN0AN1AN2AN3 Note 1: Higher order bits are from STATUS register.  2010 Microchip Technology Inc. DS41190G-page 7

PIC12F629/675 TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTION Input Output Name Function Description Type Type GP0/AN0/CIN+/ICSPDAT GP0 TTL CMOS Bidirectional I/O w/ programmable pull-up and interrupt-on-change AN0 AN A/D Channel 0 input CIN+ AN Comparator input ICSPDAT TTL CMOS Serial programming I/O GP1/AN1/CIN-/VREF/ GP1 TTL CMOS Bidirectional I/O w/ programmable pull-up and ICSPCLK interrupt-on-change AN1 AN A/D Channel 1 input CIN- AN Comparator input VREF AN External voltage reference ICSPCLK ST Serial programming clock GP2/AN2/T0CKI/INT/COUT GP2 ST CMOS Bidirectional I/O w/ programmable pull-up and interrupt-on-change AN2 AN A/D Channel 2 input T0CKI ST TMR0 clock input INT ST External interrupt COUT CMOS Comparator output GP3/MCLR/VPP GP3 TTL Input port w/ interrupt-on-change MCLR ST Master Clear VPP HV Programming voltage GP4/AN3/T1G/OSC2/ GP4 TTL CMOS Bidirectional I/O w/ programmable pull-up and CLKOUT interrupt-on-change AN3 AN A/D Channel 3 input T1G ST TMR1 gate OSC2 XTAL Crystal/resonator CLKOUT CMOS FOSC/4 output GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O w/ programmable pull-up and interrupt-on-change T1CKI ST TMR1 clock OSC1 XTAL Crystal/resonator CLKIN ST External clock input/RC oscillator connection VSS VSS Power Ground reference VDD VDD Power Positive supply Legend: Shade = PIC12F675 only TTL = TTL input buffer, ST = Schmitt Trigger input buffer DS41190G-page 8  2010 Microchip Technology Inc.

PIC12F629/675 2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization The data memory (see Figure2-2) is partitioned into 2.1 Program Memory Organization two banks, which contain the General Purpose The PIC12F629/675 devices have a 13-bit program Registers and the Special Function Registers. The counter capable of addressing an 8K x 14 program Special Function Registers are located in the first 32 memory space. Only the first 1K x 14 (0000h-03FFh) locations of each bank. Register locations 20h-5Fh are for the PIC12F629/675 devices is physically imple- General Purpose Registers, implemented as static mented. Accessing a location above these boundaries RAM and are mapped across both banks. All other will cause a wrap-around within the first 1K x 14 space. RAM is unimplemented and returns ‘0’ when read. RP0 The Reset vector is at 0000h and the interrupt vector is (STATUS<5>) is the bank select bit. at 0004h (see Figure2-1). • RP0 = 0 Bank 0 is selected • RP0 = 1 Bank 1 is selected FIGURE 2-1: PROGRAM MEMORY MAP Note: The IRP and RP1 bits STATUS<7:6> are AND STACK FOR THE reserved and should always be maintained DSTEMP/675 as ‘0’s. PC<12:0> 2.2.1 GENERAL PURPOSE REGISTER CALL, RETURN 13 FILE RETFIE, RETLW The register file is organized as 64 x 8 in the Stack Level 1 PIC12F629/675 devices. Each register is accessed, Stack Level 2 either directly or indirectly, through the File Select Register FSR (see Section2.4 “Indirect Addressing, INDF and FSR Registers”). Stack Level 8 Reset Vector 000h Interrupt Vector 0004 0005 On-chip Program Memory 03FFh 0400h 1FFFh  2010 Microchip Technology Inc. DS41190G-page 9

PIC12F629/675 2.2.2 SPECIAL FUNCTION REGISTERS FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F629/675 The Special Function Registers are registers used by the CPU and peripheral functions for controlling the File File desired operation of the device (see Table2-1). These Address Address registers are static RAM. Indirect addr.(1) 00h Indirect addr.(1) 80h The special registers can be classified into two sets: TMR0 01h OPTION_REG 81h core and peripheral. The Special Function Registers PCL 02h PCL 82h associated with the “core” are described in this section. STATUS 03h STATUS 83h Those related to the operation of the peripheral FSR 04h FSR 84h features are described in the section of that peripheral GPIO 05h TRISIO 85h feature. 06h 86h 07h 87h 08h 88h 09h 89h PCLATH 0Ah PCLATH 8Ah INTCON 0Bh INTCON 8Bh PIR1 0Ch PIE1 8Ch 0Dh 8Dh TMR1L 0Eh PCON 8Eh TMR1H 0Fh 8Fh T1CON 10h OSCCAL 90h 11h 91h 12h 92h 13h 93h 14h 94h 15h WPU 95h 16h IOC 96h 17h 97h 18h 98h CMCON 19h VRCON 99h 1Ah EEDATA 9Ah 1Bh EEADR 9Bh 1Ch EECON1 9Ch 1Dh EECON2(1) 9Dh ADRESH(2) 1Eh ADRESL(2) 9Eh ADCON0(2) 1Fh ANSEL(2) 9Fh 20h A0h General Purpose accesses Registers 20h-5Fh 64 Bytes 5Fh DFh 60h E0h 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. 1: Not a physical register. 2: PIC12F675 only. DS41190G-page 10  2010 Microchip Technology Inc.

PIC12F629/675 TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOD Bank 0 00h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 20,61 01h TMR0 Timer0 Module’s Register xxxx xxxx 29 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19 03h STATUS IRP(2) RP1(2) RP0 TO PD Z DC C 0001 1xxx 14 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 20 05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx 21 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 19 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 15 0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 17 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit Timer1 xxxx xxxx 32 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit Timer1 xxxx xxxx 32 10h T1CON — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 35 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h CMCON — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 38 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH(3) Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result xxxx xxxx 44 1Fh ADCON0(3) ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 45,61 Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘0’. 3: PIC12F675 only.  2010 Microchip Technology Inc. DS41190G-page 11

PIC12F629/675 TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED) Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page POR, BOD Bank 1 80h INDF(1) Addressing this Location uses Contents of FSR to Address Data Memory 0000 0000 20,61 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 14,31 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19 83h STATUS IRP(2) RP1(2) RP0 TO PD Z DC C 0001 1xxx 14 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 20 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 21 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for Upper 5 bits of Program Counter ---0 0000 19 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 15 8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 16 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOD ---- --0x 18 8Fh — Unimplemented — — 90h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- 18 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 21 96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 23 97h — Unimplemented — — 98h — Unimplemented — — 99h VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 42 9Ah EEDATA Data EEPROM Data Register 0000 0000 49 9Bh EEADR — Data EEPROM Address Register -000 0000 49 9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 50 9Dh EECON2(1) EEPROM Control Register 2 ---- ---- 50 9Eh ADRESL(3) Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result xxxx xxxx 44 9Fh ANSEL(3) — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 46,61 Legend: — = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘0’. 3: PIC12F675 only. DS41190G-page 12  2010 Microchip Technology Inc.

PIC12F629/675 2.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register2-1, contains: as 000u u1uu (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the • the bank select bits for data memory (SRAM) STATUS register, because these instructions do not The STATUS register can be the destination for any affect any Status bits. For other instructions not affect- instruction, like any other register. If the STATUS ing any Status bits, see the “Instruction Set Summary”. register is the destination for an instruction that affects Note 1: Bits IRP and RP1 (STATUS<7:6>) are not the Z, DC or C bits, then the write to these three bits is used by the PIC12F629/675 and should disabled. These bits are set or cleared according to the be maintained as clear. Use of these bits device logic. Furthermore, the TO and PD bits are not is not recommended, since this may affect writable. Therefore, the result of an instruction with the upward compatibility with future products. STATUS register as destination may be different than intended. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. REGISTER 2-1: STATUS: STATUS REGISTER (ADDRESS: 03h OR 83h) Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing) 0 = Bank 0 (00h - 7Fh) 1 = Bank 1 (80h - FFh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT Time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) For borrow, the polarity is reversed. 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.  2010 Microchip Technology Inc. DS41190G-page 13

PIC12F629/675 2.2.2.2 OPTION Register Note: To achieve a 1:1 prescaler assignment for The OPTION register is a readable and writable TMR0, assign the prescaler to the WDT by register, which contains various control bits to setting PSA bit to ‘1’ (OPTION<3>). See configure: Section4.4 “Prescaler”. • TMR0/WDT prescaler • External GP2/INT interrupt • TMR0 • Weak pull-ups on GPIO REGISTER 2-2: OPTION_REG: OPTION REGISTER (ADDRESS: 81h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the TIMER0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS41190G-page 14  2010 Microchip Technology Inc.

PIC12F629/675 2.2.2.3 INTCON Register Note: Interrupt flag bits are set when an interrupt The INTCON register is a readable and writable condition occurs, regardless of the state of register, which contains the various enable and flag bits its corresponding enable bit or the global for TMR0 register overflow, GPIO port change and enable bit, GIE (INTCON<7>). User soft- external GP2/INT pin interrupts. ware should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GIE PEIE T0IE INTE GPIE T0IF INTF GPIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt bit 3 GPIE: Port Change Interrupt Enable bit(1) 1 = Enables the GPIO port change interrupt 0 = Disables the GPIO port change interrupt bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur bit 0 GPIF: Port Change Interrupt Flag bit 1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software) 0 = None of the GP5:GP0 pins have changed state Note 1: IOC register must also be enabled to enable an interrupt-on-change. 2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on Reset and should be initialized before clearing T0IF bit.  2010 Microchip Technology Inc. DS41190G-page 15

PIC12F629/675 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE (INTCON<6>) must be set to shown in Register2-4. enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 EEIE ADIE — — CMIE — — TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only) 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5-4 Unimplemented: Read as ‘0’ bit 3 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 2-1 Unimplemented: Read as ‘0’ bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS41190G-page 16  2010 Microchip Technology Inc.

PIC12F629/675 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt shown in Register2-5. condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 EEIF ADIF — — CMIF — — TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only) 1 = The A/D conversion is complete (must be cleared in software) 0 = The A/D conversion is not complete bit 5-4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 2-1 Unimplemented: Read as ‘0’ bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow  2010 Microchip Technology Inc. DS41190G-page 17

PIC12F629/675 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Detect (BOD) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON Register bits are shown in Register2-6. REGISTER 2-6: PCON: POWER CONTROL REGISTER (ADDRESS: 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-x — — — — — — POR BOD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOD: Brown-out Detect Status bit 1 = No Brown-out Detect occurred 0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs) 2.2.2.7 OSCCAL Register The Oscillator Calibration register (OSCCAL) is used to calibrate the internal 4 MHz oscillator. It contains 6 bits to adjust the frequency up or down to achieve 4 MHz. The OSCCAL register bits are shown in Register2-7. REGISTER 2-7: OSCCAL: OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h) R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 CAL5:CAL0: 6-bit Signed Oscillator Calibration bits 111111 = Maximum frequency 100000 = Center frequency 000000 = Minimum frequency bit 1-0 Unimplemented: Read as ‘0’ DS41190G-page 18  2010 Microchip Technology Inc.

PIC12F629/675 2.3 PCL and PCLATH 2.3.2 STACK The Program Counter (PC) is 13-bits wide. The low byte The PIC12F629/675 family has an 8-level deep x 13-bit comes from the PCL register, which is a readable and wide hardware stack (see Figure2-1). The stack space writable register. The high byte (PC<12:8>) is not is not part of either program or data space and the directly readable or writable and comes from PCLATH. Stack Pointer is not readable or writable. The PC is On any Reset, the PC is cleared. Figure2-3 shows the PUSHed onto the stack when a CALL instruction is two situations for the loading of the PC. The upper executed, or an interrupt causes a branch. The stack is example in Figure2-3 shows how the PC is loaded on POPed in the event of a RETURN, RETLW or a RETFIE a write to PCL (PCLATH<4:0>  PCH). The lower instruction execution. PCLATH is not affected by a example in Figure2-3 shows how the PC is loaded PUSH or POP operation. during a CALL or GOTO instruction (PCLATH<4:3>  The stack operates as a circular buffer. This means that PCH). after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first FIGURE 2-3: LOADING OF PC IN push. The tenth push overwrites the second push (and DIFFERENT SITUATIONS so on). PCH PCL Note 1: There are no Status bits to indicate Stack 12 8 7 0 Instruction with Overflow or Stack Underflow conditions. PC PCL as 2: There are no instructions/mnemonics Destination PCLATH<4:0> 8 called PUSH or POP. These are actions 5 ALU result that occur from the execution of the CALL, RETURN, RETLW and RETFIE PCLATH instructions, or the vectoring to an interrupt address. PCH PCL 12 11 10 8 7 0 PC GOTO, CALL PCLATH<4:3> 11 2 Opcode <10:0> PCLATH 2.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the PC (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note, “Implementing a Table Read” (AN556).  2010 Microchip Technology Inc. DS41190G-page 19

PIC12F629/675 2.4 Indirect Addressing, INDF and A simple program to clear RAM location 20h-2Fh using FSR Registers indirect addressing is shown in Example2-1. The INDF register is not a physical register. Addressing EXAMPLE 2-1: INDIRECT ADDRESSING the INDF register will cause indirect addressing. MOVLW 0x20 ;initialize pointer Indirect addressing is possible by using the INDF MOVWF FSR ;to RAM register. Any instruction using the INDF register NEXT CLRF INDF ;clear INDF register actually accesses data pointed to by the File Select INCF FSR ;inc pointer Register (FSR). Reading INDF itself indirectly will BTFSS FSR,4 ;all done? produce 00h. Writing to the INDF register indirectly GOTO NEXT ;no clear next results in a no operation (although Status bits may be CONTINUE ;yes continue affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure2-2. FIGURE 2-2: DIRECT/INDIRECT ADDRESSING PIC12F629/675 Direct Addressing Indirect Addressing RP1(1) RP0 6 From Opcode 0 IRP(1) 7 FSR Register 0 Bank Select Location Select Bank Select Location Select 00 01 10 11 00h 180h Data Not Used Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figure2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. DS41190G-page 20  2010 Microchip Technology Inc.

PIC12F629/675 3.0 GPIO PORT register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always There are as many as six general purpose I/O pins read ‘0’. available. Depending on which peripherals are enabled, some or all of the pins may not be available as Note: The ANSEL (9Fh) and CMCON (19h) general purpose I/O. In general, when a peripheral is registers (9Fh) must be initialized to enabled, the associated pin may not be used as a configure an analog channel as a digital general purpose I/O pin. input. Pins configured as analog inputs will read ‘0’. The ANSEL register is defined for Note: Additional information on I/O ports may be the PIC12F675. found in the PIC® Mid-Range Reference Manual, (DS33023). EXAMPLE 3-1: INITIALIZING GPIO BCF STATUS,RP0 ;Bank 0 3.1 GPIO and the TRISIO Registers CLRF GPIO ;Init GPIO GPIO is an 6-bit wide, bidirectional port. The MOVLW 07h ;Set GP<2:0> to MOVWF CMCON ;digital IO corresponding data direction register is TRISIO. BSF STATUS,RP0 ;Bank 1 Setting a TRISIO bit (= 1) will make the corresponding CLRF ANSEL ;Digital I/O GPIO pin an input (i.e., put the corresponding output MOVLW 0Ch ;Set GP<3:2> as inputs driver in a High-Impedance mode). Clearing a TRISIO MOVWF TRISIO ;and set GP<5:4,1:0> bit (= 0) will make the corresponding GPIO pin an ;as outputs output (i.e., put the contents of the output latch on the selected pin). The exception is GP3, which is input-only 3.2 Additional Pin Functions and its TRISIO bit will always read as ‘1’. Example3-1 shows how to initialize GPIO. Every GPIO pin on the PIC12F629/675 has an Reading the GPIO register reads the status of the pins, interrupt-on-change option and every GPIO pin, except whereas writing to it will write to the PORT latch. All GP3, has a weak pull-up option. The next two sections write operations are read-modify-write operations. describe these functions. Therefore, a write to a port implies that the port pins are 3.2.1 WEAK PULL-UP read, this value is modified, and then written to the PORT data latch. GP3 reads ‘0’ when MCLREN = 1. Each of the GPIO pins, except GP3, has an individually The TRISIO register controls the direction of the configurable weak internal pull-up. Control bits WPUx GPpins, even when they are being used as analog enable or disable each pull-up. Refer to Register3-3. inputs. The user must ensure the bits in the TRISIO Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU bit (OPTION<7>). REGISTER 3-1: GPIO: GPIO REGISTER (ADDRESS: 05h) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GPIO<5:0>: General Purpose I/O pin 1 = Port pin is >VIH 0 = Port pin is <VIL  2010 Microchip Technology Inc. DS41190G-page 21

PIC12F629/675 REGISTER 3-2: TRISIO: GPIO TRI-STATE REGISTER (ADDRESS: 85h) U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TRISIO<5:0>: General Purpose I/O Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output Note: TRISIO<3> always reads ‘1’. REGISTER 3-3: WPU: WEAK PULL-UP REGISTER (ADDRESS: 95h) U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPU5 WPU4 — WPU2 WPU1 WPU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPU<2:0>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global GPPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). DS41190G-page 22  2010 Microchip Technology Inc.

PIC12F629/675 3.2.2 INTERRUPT-ON-CHANGE This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the Each of the GPIO pins is individually configurable as an interrupt in the following manner: interrupt-on-change pin. Control bits IOC enable or disable the interrupt function for each pin. Refer to a) Any read or write of GPIO. This will end the Register3-4. The interrupt-on-change is disabled on a mismatch condition. Power-on Reset. b) Clear the flag bit GPIF. For enabled interrupt-on-change pins, the values are A mismatch condition will continue to set flag bit GPIF. compared with the old value latched on the last read of Reading GPIO will end the mismatch condition and GPIO. The ‘mismatch’ outputs of the last read are OR’d allow flag bit GPIF to be cleared. together to set, the GP Port Change Interrupt flag bit Note: If a change on the I/O pin should occur (GPIF) in the INTCON register. when the read operation is being executed (start of the Q2 cycle), then the GPIF inter- rupt flag may not getset. REGISTER 3-4: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOC<5:0>: Interrupt-on-Change GPIO Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.  2010 Microchip Technology Inc. DS41190G-page 23

PIC12F629/675 3.3 Pin Descriptions and Diagrams FIGURE 3-1: BLOCK DIAGRAM OF GP0 AND GP1 PINS Each GPIO pin is multiplexed with other functions. The Analog pins and their combined functions are briefly described Data Bus Input Mode here. For specific information about individual functions D Q VDD such as the comparator or the A/D, refer to the WR CK appropriate section in this Data Sheet. WPU Q Weak 3.3.1 GP0/AN0/CIN+ RD GPPU WPU Figure3-1 shows the diagram for this pin. The GP0 pin is configurable to function as one of the following: • a general purpose I/O D Q VDD • an analog input for the A/D (PIC12F675 only) WR CK • an analog input to the comparator PORT Q 3.3.2 GP1/AN1/CIN-/VREF I/O pin D Q Figure3-1 shows the diagram for this pin. The GP1 pin WR CK is configurable to function as one of the following: TRISIO Q VSS • as a general purpose I/O Analog RD Input Mode • an analog input for the A/D (PIC12F675 only) TRISIO • an analog input to the comparator • a voltage reference input for the A/D (PIC12F675 RD only) PORT D Q Q D WR CK Q IOC EN RD IOC Q D EN Interrupt-on-Change RD PORT To Comparator To A/D Converter DS41190G-page 24  2010 Microchip Technology Inc.

PIC12F629/675 3.3.3 GP2/AN2/T0CKI/INT/COUT 3.3.4 GP3/MCLR/VPP Figure3-2 shows the diagram for this pin. The GP2 pin Figure3-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: is configurable to function as one of the following: • a general purpose I/O • a general purpose input • an analog input for the A/D (PIC12F675 only) • as Master Clear Reset • the clock input for TMR0 FIGURE 3-3: BLOCK DIAGRAM OF GP3 • an external edge triggered interrupt • a digital output from the comparator Data Bus MCLRE Reset I/O pin FIGURE 3-2: BLOCK DIAGRAM OF GP2 Analog RD VSS TRISIO Data Bus Input Mode D Q VDD RD MCLRE VSS PORT WR CK Q Weak WPU D Q Q D RD GPPU WR CK Q IOC WPU EN Analog COUT Input RD Enable Mode IOC Q D VDD D Q EN PWORRT CK Q COUT 1 Interrupt-on-Change 0 I/O pin RD PORT D Q WR CK TRISIO Q VSS Analog Input Mode RD TRISIO RD PORT D Q Q D WR CK Q IOC EN RD IOC Q D EN Interrupt-on-Change RD PORT To TMR0 To INT To A/D Converter  2010 Microchip Technology Inc. DS41190G-page 25

PIC12F629/675 3.3.5 GP4/AN3/T1G/OSC2/CLKOUT 3.3.6 GP5/T1CKI/OSC1/CLKIN Figure3-4 shows the diagram for this pin. The GP4 pin Figure3-5 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: is configurable to function as one of the following: • a general purpose I/O • a general purpose I/O • an analog input for the A/D (PIC12F675 only) • a TMR1 clock input • a TMR1 gate input • a crystal/resonator connection • a crystal/resonator connection • a clock input • a clock output FIGURE 3-5: BLOCK DIAGRAM OF GP5 FIGURE 3-4: BLOCK DIAGRAM OF GP4 INTOSC Analog Mode Input Mode TMR1LPEN(1) CLK Data Bus Data Bus Modes(1) D Q VDD D Q VDD WR CK WWPRU CK Q Weak Q Weak WPU GPPU RD RD GPPU WPU WPU Oscillator Oscillator Circuit Circuit OSC1 OSC2 CLKOUT VDD D Q VDD Enable WR CK Q FOSC/4 1 PORT D Q WR CK 0 I/O pin I/O pin Q D Q PORT CLKOUT Enable WR CK VSS TRISIO Q VSS D Q INTOSC/ INTOSC WR CK RC/EC(2) RD Mode TRISIO Q TRISIO CLKOUT (2) RD Enable RD TRISIO Analog PORT Input Mode D Q RD Q D PORT WR CK Q IOC D Q EN Q D RD WR CK Q IOC IOC EN Q D RD IOC Q D EN Interrupt-on-Change EN Interrupt-on-Change RD PORT RD PORT To TMR1 or CLKGEN To TMR1 T1G To A/D Converter Note1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT Note 1: Timer1 LP Oscillator enabled Enable. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is by-passed. 2: With CLKOUT option. DS41190G-page 26  2010 Microchip Technology Inc.

PIC12F629/675 TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOD Resets 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u 19h CMCON — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 95h WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 --11 -111 96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.  2010 Microchip Technology Inc. DS41190G-page 27

PIC12F629/675 NOTES: DS41190G-page 28  2010 Microchip Technology Inc.

PIC12F629/675 4.0 TIMER0 MODULE Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module The Timer0 module timer/counter has the following will increment either on every rising or falling edge of features: pin GP2/T0CKI. The incrementing edge is determined • 8-bit timer/counter by the source edge (T0SE) control bit (OPTION_REG<4>). Clearing the T0SE bit selects the • Readable and writable rising edge. • 8-bit software programmable prescaler • Internal or external clock select Note: Counter mode has specific external clock requirements. Additional information on • Interrupt on overflow from FFh to 00h these requirements is available in the PIC® • Edge select for external clock Mid-Range Reference Manual, Figure4-1 is a block diagram of the Timer0 module and (DS33023). the prescaler shared with the WDT. 4.2 Timer0 Interrupt Note: Additional information on the Timer0 module is available in the PIC® Mid-Range A Timer0 interrupt is generated when the TMR0 Reference Manual, (DS33023). register timer/counter overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked 4.1 Timer0 Operation by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer mode is selected by clearing the T0CS bit Timer0 module Interrupt Service Routine before re- (OPTION_REG<5>). In Timer mode, the Timer0 enabling this interrupt. The Timer0 interrupt cannot module will increment every instruction cycle (without wake the processor from Sleep since the timer is shut- prescaler). If TMR0 is written, the increment is inhibited off during Sleep. for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. FIGURE 4-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER CLKOUT (= FOSC/4) Data Bus 0 8 1 SYNC 2 1 TMR0 Cycles T0CKI 0 pin 0 T0SE T0CS 8-bit Set Flag bit T0IF on Overflow Prescaler PSA 1 8 PSA PS0 - PS2 1 WDT Time-out Watchdog 0 Timer PSA WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.  2010 Microchip Technology Inc. DS41190G-page 29

PIC12F629/675 4.3 Using Timer0 with an External a small RC delay of 20 ns) and low for at least 2TOSC Clock (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. When no prescaler is used, the external clock input is Note: The ANSEL (9Fh) and CMCON (19h) the same as the prescaler output. The synchronization registers must be initialized to configure an of T0CKI, with the internal phase clocks, is accom- analog channel as a digital input. Pins plished by sampling the prescaler output on the Q2 and configured as analog inputs will read ‘0’. Q4 cycles of the internal phase clocks. Therefore, it is The ANSEL register is defined for the necessary for T0CKI to be high for at least 2TOSC (and PIC12F675. REGISTER 4-1: OPTION_REG: OPTION REGISTER (ADDRESS: 81h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of GP2/INT pin 0 = Interrupt on falling edge of GP2/INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on GP2/T0CK pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on GP2/T0CKI pin 0 = Increment on low-to-high transition on GP2/T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the TIMER0 module bit 2-0 PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS41190G-page 30  2010 Microchip Technology Inc.

PIC12F629/675 4.4 Prescaler EXAMPLE 4-1: CHANGING PRESCALER (TIMER0WDT) An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog BCF STATUS,RP0 ;Bank 0 Timer. For simplicity, this counter will be referred to as CLRWDT ;Clear WDT “prescaler” throughout this Data Sheet. The prescaler CLRF TMR0 ;Clear TMR0 and assignment is controlled in software by the control bit ; prescaler PSA (OPTION_REG<3>). Clearing the PSA bit will BSF STATUS,RP0 ;Bank 1 assign the prescaler to Timer0. Prescale values are selectable via the PS2:PS0 bits (OPTION_REG<2:0>). MOVLW b’00101111’ ;Required if desired The prescaler is not readable or writable. When MOVWF OPTION_REG ; PS2:PS0 is assigned to the Timer0 module, all instructions writing CLRWDT ; 000 or 001 to the TMR0 register (e.g., CLRF 1, MOVWF 1, ; BSF 1, x....etc.) will clear the prescaler. When MOVLW b’00101xxx’ ;Set postscaler to assigned to WDT, a CLRWDT instruction will clear the MOVWF OPTION_REG ; desired WDT rate BCF STATUS,RP0 ;Bank 0 prescaler along with the Watchdog Timer. 4.4.1 SWITCHING PRESCALER To change prescaler from the WDT to the TMR0 ASSIGNMENT module, use the sequence shown in Example4-2. This precaution must be taken even if the WDT is disabled. The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during EXAMPLE 4-2: CHANGING PRESCALER program execution). To avoid an unintended device (WDTTIMER0) Reset, the following instruction sequence (Example4- 1) must be executed when changing the prescaler CLRWDT ;Clear WDT and assignment from Timer0 to WDT. ; postscaler BSF STATUS,RP0 ;Bank 1 MOVLW b’xxxx0xxx’ ;Select TMR0, ; prescale, and ; clock source MOVWF OPTION_REG ; BCF STATUS,RP0 ;Bank 0 TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOD Resets 01h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.  2010 Microchip Technology Inc. DS41190G-page 31

PIC12F629/675 5.0 TIMER1 MODULE WITH GATE The Timer1 Control register (T1CON), shown in CONTROL Register5.1, is used to enable/disable Timer1 and select the various features of the Timer1 module. The PIC12F629/675 devices have a 16-bit timer. Note: Additional information on timer modules is Figure5-1 shows the basic block diagram of the Timer1 available in the PIC® Mid-Range Refer- module. Timer1 has the following features: ence Manual, (DS33023). • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • Synchronous or asynchronous operation • Interrupt on overflow from FFFFh to 0000h • Wake-up upon overflow (Asynchronous mode) • Optional external enable input (T1G) • Optional LP oscillator FIGURE 5-1: TIMER1 BLOCK DIAGRAM TMR1ON TMR1GE TMR1ON T1G Set Flag bit TMR1GE TMR1IF on Overflow TMR1 Synchronized 0 Clock Input TMR1H TMR1L 1 LP Oscillator T1SYNC OSC1 1 Synchronize Prescaler FOSC/4 1, 2, 4, 8 Detect Internal 0 OSC2 Clock 2 Sleep Input INTOSC T1CKPS<1:0> w/o CLKOUT TMR1CS T1OSCEN LP DS41190G-page 32  2010 Microchip Technology Inc.

PIC12F629/675 5.1 Timer1 Modes of Operation 5.2 Timer1 Interrupt Timer1 can operate in one of three modes: The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls • 16-bit timer with prescaler over, the Timer1 interrupt flag bit (PIR1<0>) is set. To • 16-bit synchronous counter enable the interrupt on rollover, you must set these bits: • 16-bit asynchronous counter • Timer1 interrupt Enable bit (PIE1<0>) In Timer mode, Timer1 is incremented on every • PEIE bit (INTCON<6>) instruction cycle. In Counter mode, Timer1 is • GIE bit (INTCON<7>). incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can The interrupt is cleared by clearing the TMR1IF in the be synchronized to the microcontroller system clock Interrupt Service Routine. or run asynchronously. Note: The TMR1H:TTMR1L register pair and the In counter and timer modules, the counter/timer clock TMR1IF bit should be cleared before can be gated by the T1G input. enabling interrupts. If an external clock oscillator is needed (and the 5.3 Timer1 Prescaler microcontroller is using the INTOSC w/o CLKOUT), Timer1 can use the LP oscillator as a clock source. Timer1 has four prescaler options allowing 1, 2, 4, or 8 Note: In Counter mode, a falling edge must be divisions of the clock input. The T1CKPS bits registered by the counter prior to the first (T1CON<5:4>) control the prescale counter. The incrementing rising edge. prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. FIGURE 5-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2010 Microchip Technology Inc. DS41190G-page 33

PIC12F629/675 REGISTER 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if T1G pin is low 0 = Timer1 is on bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1OSO/T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 DS41190G-page 34  2010 Microchip Technology Inc.

PIC12F629/675 5.4 Timer1 Operation in 5.5 Timer1 Oscillator Asynchronous Counter Mode A crystal oscillator circuit is built-in between pins OSC1 If control bit T1SYNC (T1CON<2>) is set, the external (input) and OSC2 (amplifier output). It is enabled by clock input is not synchronized. The timer continues to setting control bit T1OSCEN (T1CON<3>). The increment asynchronous to the internal phase clocks. oscillator is a low-power oscillator rated up to 37 kHz. It The timer will continue to run during Sleep and can will continue to run during Sleep. It is primarily intended generate an interrupt on overflow, which will wake-up for a 32 kHz crystal. Table9-2 shows the capacitor the processor. However, special precautions in selection for the Timer1 oscillator. software are needed to read/write the timer The Timer1 oscillator is shared with the system LP (Section5.4.1 “Reading and Writing Timer1 in oscillator. Thus, Timer1 can use this mode only when Asynchronous Counter Mode”). the system clock is derived from the internal oscillator. As with the system LP oscillator, the user must provide Note: The ANSEL (9Fh) and CMCON (19h) a software time delay to ensure proper oscillator registers must be initialized to configure an start-up. analog channel as a digital input. Pins configured as analog inputs will read ‘0’. While enabled, TRISIO4 and TRISIO5 are set. GP4 The ANSEL register is defined for the and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read PIC12F675. ‘1’. 5.4.1 READING AND WRITING TIMER1 IN Note: The oscillator requires a start-up and stabi- ASYNCHRONOUS COUNTER MODE lization time before use. Thus, T1OSCEN should be set and a suitable delay Reading TMR1H or TMR1L, while the timer is running observed prior to enabling Timer1. from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the 5.6 Timer1 Operation During Sleep user should keep in mind that reading the 16-bit timer Timer1 can only operate during Sleep when setup in in two 8-bit values itself, poses certain problems, since Asynchronous Counter mode. In this mode, an external the timer may overflow between the reads. crystal or clock source can be used to increment the For writes, it is recommended that the user simply stop counter. To setup the timer to wake the device: the timer and write the desired values. A write • Timer1 must be on (T1CON<0>) contention may occur by writing to the timer registers, while the register is incrementing. This may produce an • TMR1IE bit (PIE1<0>) must be set unpredictable value in the timer register. • PEIE bit (INTCON<6>) must be set Reading the 16-bit value requires some care. The device will wake-up on an overflow. If the GIE bit Examples 12-2 and 12-3 in the PIC® Mid-Range MCU (INTCON<7>) is set, the device will wake-up and jump Family Reference Manual (DS33023) show how to to the Interrupt Service Routine on an overflow. read and write Timer1 when it is running in Asynchronous mode. TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOD Resets 0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u 0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu 8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.  2010 Microchip Technology Inc. DS41190G-page 35

PIC12F629/675 NOTES: DS41190G-page 36  2010 Microchip Technology Inc.

PIC12F629/675 6.0 COMPARATOR MODULE The Comparator Control Register (CMCON), shown in Register6-1, contains the bits to control the The PIC12F629/675 devices have one analog comparator. comparator. The inputs to the comparator are multiplexed with the GP0 and GP1 pins. There is an on-chip Comparator Voltage Reference that can also be applied to an input of the comparator. In addition, GP2 can be configured as the comparator output. REGISTER 6-1: CMCON: COMPARATOR CONTROL REGISTER (ADDRESS: 19h) U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — COUT — CINV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 COUT: Comparator Output bit When CINV = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CINV = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 5 Unimplemented: Read as ‘0’ bit 4 CINV: Comparator Output Inversion bit 1 = Output inverted 0 = Output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110 or 101: 1 = VIN- connects to CIN+ 0 = VIN- connects to CIN- bit 2-0 CM2:CM0: Comparator Mode bits Figure6-2 shows the Comparator modes and CM2:CM0 bit settings  2010 Microchip Technology Inc. DS41190G-page 37

PIC12F629/675 6.1 Comparator Operation TABLE 6-1: OUTPUT STATE VS. INPUT CONDITIONS A single comparator is shown in Figure6-1, along with the relationship between the analog input levels and Input Conditions CINV COUT the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator VIN- > VIN+ 0 0 is a digital low level. When the analog input at VIN+ is VIN- < VIN+ 0 1 greater than the analog input VIN-, the output of the VIN- > VIN+ 1 1 comparator is a digital high level. The shaded areas of the output of the comparator in Figure6-1 represent VIN- < VIN+ 1 0 the uncertainty due to input offsets and response time. FIGURE 6-1: SINGLE COMPARATOR Note: To use CIN+ and CIN- pins as analog inputs, the appropriate bits must be programmed in the CMCON (19h) register. VIN+ + Output The polarity of the comparator output can be inverted VIN- – by setting the CINV bit (CMCON<4>). Clearing CINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table6-1. VIN- VIN+ Output Note: CINV bit (CMCON<4>) is clear. DS41190G-page 38  2010 Microchip Technology Inc.

PIC12F629/675 6.2 Comparator Configuration There are eight modes of operation for the comparator. The CMCON register, shown in Register6-1, is used to select the mode. Figure6-2 shows the eight possible modes. The TRISIO register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for a specified period of time. Refer to the specifications in Section12.0 “Electri- cal Specifications”. Note: Comparator interrupts should be disabled during a Comparator mode change. Other- wise, a false interrupt may occur. FIGURE 6-2: COMPARATOR I/O OPERATING MODES Comparator Reset (POR Default Value - low power) Comparator Off (Lowest power) CM2:CM0 = 000 CM2:CM0 = 111 GP1/CIN- A GP1/CIN- D Off (Read as ‘0’) Off (Read as ‘0’) GP0/CIN+ A GP0/CIN+ D GP2/COUT D GP2/COUT D Comparator without Output Comparator w/o Output and with Internal Reference CM2:CM0 = 010 CM2:CM0 = 100 GP1/CIN- A GP1/CIN- A COUT COUT GP0/CIN+ A GP0/CIN+ D GP2/COUT D GP2/COUT D From CVREF Module Comparator with Output and Internal Reference Multiplexed Input with Internal Reference and Output CM2:CM0 = 011 CM2:CM0 = 101 GP1/CIN- A GP1/CIN- A CIS = 0 COUT GP0/CIN+ D GP0/CIN+ A CIS = 1 COUT GP2/COUT D GP2/COUT D From CVREF Module From CVREF Module Comparator with Output Multiplexed Input with Internal Reference CM2:CM0 = 001 CM2:CM0 = 110 GP1/CIN- A GP1/CIN- A CIS = 0 COUT GP0/CIN+ A GP0/CIN+ A CIS = 1 COUT GP2/COUT D GP2/COUT D From CVREF Module A = Analog Input, ports always reads ‘0’ D = Digital Input CIS = Comparator Input Switch (CMCON<3>)  2010 Microchip Technology Inc. DS41190G-page 39

PIC12F629/675 6.3 Analog Input Connection range by more than 0.6V in either direction, one of the Considerations diodes is forward biased and a latch-up may occur. A maximum source impedance of 10k is A simplified circuit for an analog input is shown in recommended for the analog sources. Any external Figure6-3. Since the analog pins are connected to a component connected to an analog input pin, such as digital output, they have reverse biased diodes to VDD a capacitor or a Zener diode, should have very little and VSS. The analog input, therefore, must be between leakage current. VSS and VDD. If the input voltage deviates from this FIGURE 6-3: ANALOG INPUT MODE VDD Rs < 10K VT = 0.6V RIC AIN VA C5 PpIFN VT = 0.6V L±5ea00ka ngAe Vss Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to Various Junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage 6.4 Comparator Output The TRISIO<2> bit functions as an output enable/ disable for the GP2 pin while the comparator is in an The comparator output, COUT, is read through the Output mode. CMCON register. This bit is read-only. The comparator output may also be directly output to the GP2 pin in Note 1: When reading the GPIO register, all pins three of the eight possible modes, as shown in configured as analog inputs will read as a Figure6-2. When in one of these modes, the output on ‘0’. Pins configured as digital inputs will GP2 is asynchronous to the internal clock. Figure6-4 convert an analog input according to the shows the comparator output block diagram. TTL input specification. 2: Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified. FIGURE 6-4: MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM GP0/CIN+ GP1/CIN- To GP2/T0CKI pin To Data Bus Q D CVREF RD CMCON EN CINV CM2:CM0 Set CMIF bit Q D EN RD CMCON Reset DS41190G-page 40  2010 Microchip Technology Inc.

PIC12F629/675 6.5 Comparator Reference The following equations determine the output voltages: The comparator module also allows the selection of an VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD internally generated voltage reference for one of the VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x comparator inputs. The internal reference signal is VDD / 32) used for four of the eight Comparator modes. The VRCON register, Register6-2, controls the voltage 6.5.2 VOLTAGE REFERENCE reference module shown in Figure6-5. ACCURACY/ERROR 6.5.1 CONFIGURING THE VOLTAGE The full range of VSS to VDD cannot be realized due to REFERENCE the construction of the module. The transistors on the The voltage reference can output 32 distinct voltage top and bottom of the resistor ladder network levels, 16 in a high range and 16 in a low range. (Figure6-5) keep CVREF from approaching VSS or VDD. The Voltage Reference is VDD derived and there- fore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section12.0 “Electrical Specifications”. FIGURE 6-5: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN CVREF to Comparator Input VR3:VR0 6.6 Comparator Response Time While the comparator is enabled during Sleep, an inter- rupt will wake-up the device. If the device wakes up Response time is the minimum time, after selecting a from Sleep, the contents of the CMCON and VRCON new reference voltage or input source, before the registers are not affected. comparator output is ensured to have a valid level. If the internal reference is changed, the maximum delay 6.8 Effects of a Reset of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the A device Reset forces the CMCON and VRCON maximum delay of the comparators should be used registers to their Reset states. This forces the (Table12-7). comparator module to be in the Comparator Reset mode, CM2:CM0=000 and the voltage reference to its 6.7 Operation During Sleep off state. Thus, all potential inputs are analog inputs with the comparator and voltage reference disabled to Both the comparator and voltage reference, if enabled consume the smallest current possible. before entering Sleep mode, remain active during Sleep. This results in higher Sleep currents than shown in the power-down specifications. The additional cur- rent consumed by the comparator and the voltage ref- erence is shown separately in the specifications. To minimize power consumption while in Sleep mode, turn off the comparator, CM2:CM0 = 111, and voltage refer- ence, VRCON<7> = 0.  2010 Microchip Technology Inc. DS41190G-page 41

PIC12F629/675 REGISTER 6-2: VRCON: VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN — VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR3:VR0: CVREF value selection 0  VR [3:0]  15 When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD 6.9 Comparator Interrupts The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: The comparator interrupt flag is set whenever there is a) Any read or write of CMCON. This will end the a change in the output value of the comparator. mismatch condition. Software will need to maintain information about the status of the output bits, as read from CMCON<6>, to b) Clear flag bit CMIF. determine the actual change that has occurred. The A mismatch condition will continue to set flag bit CMIF. CMIF bit, PIR1<3>, is the comparator interrupt flag. Reading CMCON will end the mismatch condition, and This bit must be reset in software by clearing it to ‘0’. allow flag bit CMIF to be cleared. Since it is also possible to write a ‘1’ to this register, a Note: If a change in the CMCON register (COUT) simulated interrupt may be initiated. should occur when a read operation is The CMIE bit (PIE1<3>) and the PEIE bit (INT- being executed (start of the Q2 cycle), then CON<6>) must be set to enable the interrupt. In addi- the CMIF (PIR1<3>) interrupt flag may not tion, the GIE bit must also be set. If any of these bits are get set. cleared, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. TABLE 6-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other POR, BOD Resets 0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u 0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0 19h CMCON — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 99h VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module. DS41190G-page 42  2010 Microchip Technology Inc.

PIC12F629/675 7.0 ANALOG-TO-DIGITAL circuit. The output of the sample and hold is connected CONVERTER (A/D) MODULE to the input of the converter. The converter generates a binary result via successive approximation and stores (PIC12F675 ONLY) the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either The Analog-to-Digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary VDD or a voltage applied by the VREF pin. Figure7-1 shows the block diagram of the A/D on the PIC12F675. representation of that signal. The PIC12F675 has four analog inputs, multiplexed into one sample and hold FIGURE 7-1: A/D BLOCK DIAGRAM VDD VCFG = 0 VREF VCFG = 1 GP0/AN0 GP1/AN1/VREF ADC GP2/AN2 GO/DONE 10 GP4/AN3 ADFM CHS1:CHS0 10 ADON ADRESH ADRESL VSS 7.1 A/D Configuration and Operation controls the voltage reference selection. If VCFG is set, then the voltage on the VREF pin is the reference; There are two registers available to control the otherwise, VDD is the reference. functionality of the A/D module: 7.1.4 CONVERSION CLOCK 1. ADCON0 (Register7-1) 2. ANSEL (Register7-2) The A/D conversion cycle requires 11 TAD. The source of the conversion clock is software selectable via the 7.1.1 ANALOG PORT PINS ADCS bits (ANSEL<6:4>). There are seven possible The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO clock options: bits control the operation of the A/D port pins. Set the • FOSC/2 corresponding TRISIO bits to set the pin output driver • FOSC/4 to its high-impedance state. Likewise, set the • FOSC/8 corresponding ANS bit to disable the digital input buffer. • FOSC/16 • FOSC/32 Note: Analog voltages on any pin that is defined • FOSC/64 as a digital input may cause the input buffer to conduct excess current. • FRC (dedicated internal RC oscillator) For correct conversion, the A/D conversion clock 7.1.2 CHANNEL SELECTION (1/TAD) must be selected to ensure a minimum TAD of 1.6s. Table7-1 shows a few TAD calculations for There are four analog channels on the PIC12F675, selected frequencies. AN0 through AN3. The CHS1:CHS0 bits (ADCON0<3:2>) control which channel is connected to the sample and hold circuit. 7.1.3 VOLTAGE REFERENCE There are two options for the voltage reference to the A/D converter: either VDD is used, or an analog voltage applied to VREF is used. The VCFG bit (ADCON0<6>)  2010 Microchip Technology Inc. DS41190G-page 43

PIC12F629/675 TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES A/D Clock Source (TAD) Device Frequency Operation ADCS2:ADCS0 20 MHz 5 MHz 4 MHz 1.25 MHz 2 TOSC 000 100 ns(2) 400 ns(2) 500 ns(2) 1.6 s 4 TOSC 100 200 ns(2) 800 ns(2) 1.0 s(2) 3.2 s 8 TOSC 001 400 ns(2) 1.6 s 2.0 s 6.4 s 16 TOSC 101 800 ns(2) 3.2 s 4.0 s 12.8 s(3) 32 TOSC 010 1.6 s 6.4 s 8.0 s(3) 25.6 s(3) 64 TOSC 110 3.2 s 12.8 s(3) 16.0 s(3) 51.2 s(3) A/D RC x11 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4) 2 - 6 s(1,4) Legend:Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be performed during Sleep. 7.1.5 STARTING A CONVERSION previous conversion. After an aborted conversion, a 2TAD delay is required before another acquisition can The A/D conversion is initiated by setting the be initiated. Following the delay, an input acquisition is GO/DONE bit (ADCON0<1>). When the conversion is automatically started on the selected channel. complete, the A/D module: Note: The GO/DONE bit should not be set in the • Clears the GO/DONE bit same instruction that turns on the A/D. • Sets the ADIF flag (PIR1<6>) • Generates an interrupt (if enabled) 7.1.6 CONVERSION OUTPUT If the conversion must be aborted, the GO/DONE bit The A/D conversion can be supplied in two formats: left can be cleared in software. The ADRESH:ADRESL or right shifted. The ADFM bit (ADCON0<7>) controls registers will not be updated with the partially complete the output format. Figure7-2 shows the output formats. A/D conversion sample. Instead, the ADRESH:ADRESL registers will retain the value of the FIGURE 7-2: 10-BIT A/D RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB Bit 7 Bit 0 Bit 7 Bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB Bit 7 Bit 0 Bit 7 Bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result DS41190G-page 44  2010 Microchip Technology Inc.

PIC12F629/675 REGISTER 7-1: ADCON0: A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CHS1:CHS0: Analog Channel Select bits 00 = Channel 00 (AN0) 01 = Channel 01 (AN1) 10 = Channel 02 (AN2) 11 = Channel 03 (AN3) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: A/D Conversion Status bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current  2010 Microchip Technology Inc. DS41190G-page 45

PIC12F629/675 REGISTER 7-2: ANSEL: ANALOG SELECT REGISTER (ADDRESS: 9Fh) U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = Fosc/2 001 = Fosc/8 010 = Fosc/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = Fosc/4 101 = Fosc/16 110 = Fosc/64 bit 3-0 ANS3:ANS0: Analog Select bits (Between analog or digital function on pins AN<3:0>, respectively.) 1 = Analog input; pin is assigned as analog input(1) 0 = Digital I/O; pin is assigned to port or special function Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and inter- rupt-on-change. The corresponding TRISIO bit must be set to Input mode in order to allow external control of the voltage on the pin. DS41190G-page 46  2010 Microchip Technology Inc.

PIC12F629/675 7.2 A/D Acquisition Requirements is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), For the A/D converter to meet its specified accuracy, this acquisition must be done before the conversion the charge holding capacitor (CHOLD) must be allowed can be started. to fully charge to the input channel voltage level. The To calculate the minimum acquisition time, analog input model is shown in Figure7-3. The source Equation7-1 may be used. This equation assumes impedance (RS) and the internal sampling switch (RSS) that 1/2 LSb error is used (1024 steps for the A/D). impedance directly affect the time required to charge The 1/2 LSb error is the maximum error allowed for the capacitor CHOLD. The sampling switch (RSS) the A/D to meet its specified resolution. impedance varies over the device voltage (VDD), see Figure7-3. The maximum recommended imped- To calculate the minimum acquisition time, TACQ, see ance for analog sources is 10 k. As the impedance the PIC® Mid-Range Reference Manual (DS33023). EQUATION 7-1: ACQUISITION TIME TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [(Temperature -25°C)(0.05s/°C)] TC = CHOLD (RIC + RSS + RS) In(1/2047) = - 120pF (1k + 7k + 10k) In(0.0004885) = 16.47s TACQ = 2s + 16.47s + [(50°C -25C)(0.05s/C) = 19.72s Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. FIGURE 7-3: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V RS ANx RIC  1K SS RSS CHOLD VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE == 1D2A0C p cFapacitance VSS Legend: CPIN = input capacitance 6V VT = threshold voltage 5V I LEAKAGE = leakage current at the pin due to VDD4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5 6 7 891011 Sampling Switch (k)  2010 Microchip Technology Inc. DS41190G-page 47

PIC12F629/675 7.3 A/D Operation During Sleep When the A/D clock source is something other than RC, a SLEEP instruction causes the present conversion The A/D converter module can operate during Sleep. to be aborted, and the A/D module is turned off. The This requires the A/D clock source to be set to the ADON bit remains set. internal RC oscillator. When the RC clock source is selected, the A/D waits one instruction before starting 7.4 Effects of Reset the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise A device Reset forces all registers to their Reset state. from the conversion. When the conversion is complete, Thus the A/D module is turned off and any pending the GO/DONE bit is cleared, and the result is loaded conversion is aborted. The ADRESH:ADRESL into the ADRESH:ADRESL registers. If the A/D registers are unchanged. interrupt is enabled, the device awakens from Sleep. If the A/D interrupt is not enabled, the A/D module is turned off, although the ADON bit remains set. TABLE 7-2: SUMMARY OF A/D REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOD Resets 05h GPIO — — GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 --xx xxxx --uu uuuu 0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u 0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0 1Eh ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result xxxx xxxx uuuu uuuu 1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO ADON 00-- 0000 00-- 0000 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0 9Eh ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result xxxx xxxx uuuu uuuu 9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for A/D converter module. DS41190G-page 48  2010 Microchip Technology Inc.

PIC12F629/675 8.0 DATA EEPROM MEMORY The EEPROM data memory allows byte read and write. A byte write automatically erases the location and The EEPROM data memory is readable and writable writes the new data (erase before write). The EEPROM during normal operation (full VDD range). This memory data memory is rated for high erase/write cycles. The is not directly mapped in the register file space. write time is controlled by an on-chip timer. The write Instead, it is indirectly addressed through the Special time will vary with voltage and temperature as well as Function Registers. There are four SFRs used to read from chip to chip. Please refer to AC Specifications for and write this memory: exact limits. • EECON1 When the data memory is code-protected, the CPU • EECON2 (not a physically implemented register) may continue to read and write the data EEPROM • EEDATA memory. The device programmer can no longer access thismemory. • EEADR Additional information on the data EEPROM is EEDATA holds the 8-bit data for read/write, and available in the PIC® Mid-Range Reference Manual, EEADR holds the address of the EEPROM location (DS33023). being accessed. PIC12F629/675 devices have 128 bytes of data EEPROM with an address range from 0h to 7Fh. REGISTER 8-1: EEDAT: EEPROM DATA REGISTER (ADDRESS: 9Ah) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEDATn: Byte value to write to or read from data EEPROM REGISTER 8-2: EEADR: EEPROM ADDRESS REGISTER (ADDRESS: 9Bh) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Should be set to ‘0’ bit 6-0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation  2010 Microchip Technology Inc. DS41190G-page 49

PIC12F629/675 8.1 EEADR of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature The EEADR register can address up to a maximum of termination of a write operation. 128 bytes of data EEPROM. Only seven of the eight The WREN bit, when set, will allow a write operation. bits in the register (EEADR<6:0>) are required. The On power-up, the WREN bit is clear. The WRERR bit is MSb (bit 7) is ignored. set when a write operation is interrupted by a MCLR The upper bit should always be ‘0’ to remain upward Reset, or a WDT Time-out Reset during normal compatible with devices that have more data EEPROM operation. In these situations, following Reset, the user memory. can check the WRERR bit, clear it, and rewrite the location. The data and address will be cleared, 8.2 EECON1 and EECON2 Registers therefore, the EEDATA and EEADRregisters will need EECON1 is the control register with four low-order bits to be re-initialized. physically implemented. The upper four bits are non- Interrupt flag bit EEIF in the PIR1 register is set when implemented and read as ‘0’s. write is complete. This bit must be cleared in software. Control bits RD and WR initiate read and write, EECON2 is not a physical register. Reading EECON2 respectively. These bits cannot be cleared, only set, in will read all ‘0’s. The EECON2 register is used software. They are cleared in hardware at completion exclusively in the data EEPROM write sequence. REGISTER 8-3: EECON1: EEPROM CONTROL REGISTER (ADDRESS: 9Ch) U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 — — — — WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOD detect) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software). 0 = Does not initiate an EEPROM read DS41190G-page 50  2010 Microchip Technology Inc.

PIC12F629/675 8.3 Reading the EEPROM Data After a write sequence has been initiated, clearing the Memory WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. To read a data memory location, the user must write At the completion of the write cycle, the WR bit is the address to the EEADR register and then set cleared in hardware and the EE Write Complete control bit RD (EECON1<0>), as shown in Interrupt Flag bit (EEIF) is set. The user can either Example8-1. The data is available, in the very next enable this interrupt or poll this bit. The EEIF bit cycle, in the EEDATA register. Therefore, it can be (PIR<7>) register must be cleared by software. read in the next instruction. EEDATA holds this value until another read, or until it is written to by the user 8.5 Write Verify (during a write operation). Depending on the application, good programming EXAMPLE 8-1: DATA EEPROM READ practice may dictate that the value written to the data EEPROM should be verified (see Example8-3) to the BSF STATUS,RP0 ;Bank 1 desired value to be written. MOVLW CONFIG_ADDR ; MOVWF EEADR ;Address to read EXAMPLE 8-3: WRITE VERIFY BSF EECON1,RD ;EE Read MOVF EEDATA,W ;Move data to W BCF STATUS,RP0 ;Bank 0 : ;Any code BSF STATUS,RP0 ;Bank 1 READ 8.4 Writing to the EEPROM Data MOVF EEDATA,W ;EEDATA not changed Memory ;from previous write BSF EECON1,RD ;YES, Read the To write an EEPROM data location, the user must first ;value written write the address to the EEADR register and the data XORWF EEDATA,W to the EEDATA register. Then the user must follow a BTFSS STATUS,Z ;Is data the same specific sequence to initiate the write for each byte, as GOTO WRITE_ERR ;No, handle error shown in Example8-2. : ;Yes, continue EXAMPLE 8-2: DATA EEPROM WRITE 8.5.1 USING THE DATA EEPROM BSF STATUS,RP0 ;Bank 1 The data EEPROM is a high-endurance, byte BSF EECON1,WREN ;Enable write addressable array that has been optimized for the BCF INTCON,GIE ;Disable INTs storage of frequently changing information (e.g., MOVLW 55h ;Unlock write RequiredSequence MMMOOOVVVWLWFWF EAEEAEChCOONN22 ;;; pourpftoedgnar)tae. mdF revmaqoruiraeebn lteloysf t econhr a ntohgtahinneg r svdpaaeltucaei fsitc hawatitio lln astry ep Dicu1ap2ldl0ya teboder BSF EECON1,WR ;Start the write D120A. If this is not the case, an array refresh must be BSF INTCON,GIE ;Enable INTS performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to 8.6 Protection Against Spurious Write EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this There are conditions when the device may not want to codesegment. A cycle count is executed during the write to the data EEPROM memory. To protect against required sequence. Any number that is not equal to the spurious EEPROM writes, various mechanisms have required cycles to execute the required sequence will been built in. On power-up, WREN is cleared. Also, the prevent the data from being written into the EEPROM. Power-up Timer (72 ms duration) prevents EEPROMwrite. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental The write initiate sequence and the WREN bit together writes to data EEPROM due to errant (unexpected) help prevent an accidental write during: code execution (i.e., lost programs). The user should • brown-out keep the WREN bit clear at all times, except when • power glitch updating EEPROM. The WREN bit is not cleared byhardware. • software malfunction  2010 Microchip Technology Inc. DS41190G-page 51

PIC12F629/675 8.7 Data EEPROM Operation During Code Protect Data memory can be code protected by programming the CPD bit to ‘0’. When the data memory is code protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code protect the program memory when code protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations to ‘0’ will also help prevent data memory code protection from becoming breached. TABLE 8-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOD Resets 0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0 9Ah EEDATA EEPROM Data Register 0000 0000 0000 0000 9Bh EEADR — EEPROM Address Register -000 0000 -000 0000 9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000 9Dh EECON2(1) EEPROM Control Register 2 ---- ---- ---- ---- Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by data EEPROM module. Note 1: EECON2 is not a physical register. DS41190G-page 52  2010 Microchip Technology Inc.

PIC12F629/675 9.0 SPECIAL FEATURES OF THE The PIC12F629/675 has a Watchdog Timer that is CPU controlled by Configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that Certain special circuits that deal with the needs of real offer necessary delays on power-up. One is the time applications are what sets a microcontroller apart Oscillator Start-up Timer (OST), intended to keep the from other processors. The PIC12F629/675 family has chip in Reset until the crystal oscillator is stable. The a host of such features intended to: other is the Power-up Timer (PWRT), which provides a fixed delay of 72ms (nominal) on power-up only, • maximize system reliability designed to keep the part in Reset while the power • minimize cost through elimination of external supply stabilizes. There is also circuitry to reset the components device if a brown-out occurs, which can provide at least • provide power saving operating modes and offer a 72ms Reset. With these three functions on-chip, code protection most applications need no external Reset circuitry. These features are: The Sleep mode is designed to offer a very low current • Oscillator selection Power-down mode. The user can wake-up from Sleep through: • Reset - Power-on Reset (POR) • External Reset - Power-up Timer (PWRT) • Watchdog Timer wake-up - Oscillator Start-up Timer (OST) • An interrupt - Brown-out Detect (BOD) Several oscillator options are also made available to • Interrupts allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves • Watchdog Timer (WDT) power. A set of Configuration bits are used to select • Sleep various options (see Register9.2). • Code protection • ID Locations • In-Circuit Serial Programming  2010 Microchip Technology Inc. DS41190G-page 53

PIC12F629/675 9.1 Configuration Bits The Configuration bits can be programmed (read as Note: Address 2007h is beyond the user program ‘0’), or left unprogrammed (read as ‘1’) to select various memory space. It belongs to the special con- device configurations, as shown in Register9.2. These figuration memory space (2000h-3FFFh), bits are mapped in program memory location 2007h. which can be accessed only during program- ming. See PIC12F629/675 Programming Specification for more information. REGISTER 9-1: CONFIG: CONFIGURATION WORD (ADDRESS: 2007h) R/P-1 R/P-1 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 BG1 BG0 — — — CPD CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 bit 13 bit 0 Legend: P = Programmed using ICSP™ R = Readable bit Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown bit 13-12 BG1:BG0: Bandgap Calibration bits for BOD and POR voltage(1) 00 = Lowest bandgap voltage 11 = Highest bandgap voltage bit 11-9 Unimplemented: Read as ‘0’ bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit(3) 1 = Program Memory code protection is disabled 0 = Program Memory code protection is enabled bit 6 BODEN: Brown-out Detect Enable bit(4) 1 = BOD enabled 0 = BOD disabled bit 5 MCLRE: GP3/MCLR Pin Function Select bit(5) 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 110 = RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN 010 = HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing the device as spec- ified in the PIC12F629/675 Programming Specification. These bits are reflected in an export of the Configuration Word. Microchip Development Tools maintain all Calibration bits to factory settings. 2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased, including OSCCAL value, when the code protection is turned off. 4: Enabling Brown-out Detect does not automatically enable Power-up Timer. 5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. DS41190G-page 54  2010 Microchip Technology Inc.

PIC12F629/675 9.2 Oscillator Configurations FIGURE 9-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT, EC, 9.2.1 OSCILLATOR TYPES OR LP OSC CONFIGURATION) The PIC12F629/675 can be operated in eight different oscillator option modes. The user can program three Configuration bits (FOSC2 through FOSC0) to select Clock from one of these eight modes: External System OSC1 • LP Low-Power Crystal PIC12F629/675 • XT Crystal/Resonator Open OSC2(1) • HS High-Speed Crystal/Resonator Note 1: Functions as GP4 in EC Osc mode. • RC External Resistor/Capacitor (2 modes) • INTOSCInternal Oscillator (2 modes) • EC External Clock In TABLE 9-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Note: Additional information on oscillator config- urations is available in the PIC® Mid- Ranges Characterized: Range Reference Manual, (DS33023). Mode Freq. OSC1(C1) OSC2(C2) 9.2.2 CRYSTAL OSCILLATOR / CERAMIC XT 455 kHz 68-100 pF 68-100 pF RESONATORS 2.0 MHz 15-68 pF 15-68 pF 4.0 MHz 15-68 pF 15-68 pF In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish HS 8.0 MHz 10-68 pF 10-68 pF oscillation (see Figure9-1). The PIC12F629/675 16.0 MHz 10-22 pF 10-22 pF oscillator design requires the use of a parallel cut Note 1: Higher capacitance increases the stability crystal. Use of a series cut crystal may yield a of the oscillator but also increases the frequency outside of the crystal manufacturers start-up time. These values are for design specifications. When in XT, LP or HS modes, the guidance only. Since each resonator has device can have an external clock source to drive the its own characteristics, the user should OSC1 pin (see Figure9-2). consult the resonator manufacturer for appropriate values of external FIGURE 9-1: CRYSTAL OPERATION (OR components. CERAMIC RESONATOR) HS, XT OR LP OSC TABLE 9-2: CAPACITOR SELECTION FOR CONFIGURATION CRYSTAL OSCILLATOR OSC1 Mode Freq. OSC1(C1) OSC2(C2) C1(1) To Internal LP 32 kHz 68-100 pF 68-100 pF Logic XTAL RF(3) Sleep XT 100 kHz 68-150 pF 150-200 pF 2 MHz 15-30 pF 15-30 pF OSC2 4 MHz 15-30 pF 15-30 pF RS(2) C2(1) PIC12F629/675 HS 8 MHz 15-30 pF 15-30 pF 10 MHz 15-30 pF 15-30 pF Note 1: See Table9-1 and Table9-2 for recommended 20 MHz 15-30 pF 15-30 pF values of C1 and C2. 2: A series resistor may be required for AT strip cut Note 1: Higher capacitance increases the stability crystals. 3: RF varies with the Oscillator mode selected of the oscillator but also increases the (Approx. value = 10 M start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.  2010 Microchip Technology Inc. DS41190G-page 55

PIC12F629/675 9.2.3 EXTERNAL CLOCK IN 9.2.5 INTERNAL 4 MHZ OSCILLATOR For applications where a clock is already available When calibrated, the internal oscillator provides a fixed elsewhere, users may directly drive the PIC12F629/ 4 MHz (nominal) system clock. See Electrical 675 provided that this external clock source meets the Specifications, Section12.0 “Electrical Specifica- AC/DC timing requirements listed in Section12.0 tions”, for information on variation over voltage and “Electrical Specifications”. Figure9-2 shows how temperature. an external clock circuit should be configured. Two options are available for this Oscillator mode which allow GP4 to be used as a general purpose I/O 9.2.4 RC OSCILLATOR or to output FOSC/4. For applications where precise timing is not a 9.2.5.1 Calibrating the Internal Oscillator requirement, the RC oscillator option is available. The operation and functionality of the RC oscillator is A calibration instruction is programmed into the last dependent upon a number of variables. The RC location of program memory. This instruction is a oscillator frequency is a function of: RETLW XX, where the literal is the calibration value. The literal is placed in the OSCCAL register to set the • Supply voltage calibration of the internal oscillator. Example9-1 • Resistor (REXT) and capacitor (CEXT) values demonstrates how to calibrate the internal oscillator. • Operating temperature. For best operation, decouple (with capacitance) VDD The oscillator frequency will vary from unit to unit due and VSS as close to the device as possible. to normal process parameter variation. The difference Note: Erasing the device will also erase the pre- in lead frame capacitance between package types will programmed internal calibration value for also affect the oscillation frequency, especially for low the internal oscillator. The calibration value CEXT values. The user also needs to account for the must be saved prior to erasing part as tolerance of the external R and C components. specified in the PIC12F629/675 Program- Figure9-3 shows how the R/C combination is ming specification. Microchip Develop- connected. ment Tools maintain all Calibration bits to Two options are available for this Oscillator mode factory settings. which allow GP4 to be used as a general purpose I/O or to output FOSC/4. EXAMPLE 9-1: CALIBRATING THE INTERNAL OSCILLATOR FIGURE 9-3: RC OSCILLATOR MODE BSF STATUS, RP0 ;Bank 1 CALL 3FFh ;Get the cal value VDD MOVWF OSCCAL ;Calibrate PIC12F629/675 BCF STATUS, RP0 ;Bank 0 REXT GP5/OSC1/ Internal CLKIN Clock 9.2.6 CLKOUT CEXT The PIC12F629/675 devices can be configured to VSS provide a clock out signal in the INTOSC and RC oscillator modes. When configured, the oscillator FOSC/4 GP4/OSC2/CLKOUT frequency divided by four (FOSC/4) is output on the GP4/OSC2/CLKOUT pin. FOSC/4 can be used for test purposes or to synchronize other logic. DS41190G-page 56  2010 Microchip Technology Inc.

PIC12F629/675 9.3 Reset They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and The PIC12F629/675 differentiates between various PD bits are set or cleared differently in different Reset kinds of Reset: situations as indicated in Table9-4. These bits are a) Power-on Reset (POR) used in software to determine the nature of the Reset. b) WDT Reset during normal operation See Table9-7 for a full description of Reset states of all registers. c) WDT Reset during Sleep d) MCLR Reset during normal operation A simplified block diagram of the on-chip Reset Circuit is shown in Figure9-4. e) MCLR Reset during Sleep f) Brown-out Detect (BOD) The MCLR Reset path has a noise filter to detect and ignore small pulses. See Table12-4 in Electrical Some registers are not affected in any Reset condition; Specifications Section for pulse-width specification. their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • Power-on Reset • MCLR Reset • WDT Reset • WDT Reset during Sleep • Brown-out Detect (BOD) Reset FIGURE 9-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/ VPP pin SLEEP WDT WDT Module Time-out Reset VDD Rise Detect Power-on Reset VDD Brown-out Detect S Q BODEN OST/PWRT OST Chip_Reset 10-bit Ripple Counter R Q OSC1/ CLKIN pin PWRT On-chip(1) 10-bit Ripple Counter RC OSC Enable PWRT See Table9-3 for time-out situations. Enable OST Note 1: This is a separate oscillator from the INTOSC/EC oscillator.  2010 Microchip Technology Inc. DS41190G-page 57

PIC12F629/675 9.3.1 MCLR For additional information, refer to Application Note AN607, “Power-up Trouble Shooting”. PIC12F629/675 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore 9.3.3 POWER-UP TIMER (PWRT) small pulses. The Power-up Timer provides a fixed 72ms (nominal) It should be noted that a WDT Reset does not drive time-out on power-up only, from POR or Brown-out MCLR pin low. Detect. The Power-up Timer operates on an internal The behavior of the ESD protection on the MCLR pin RC oscillator. The chip is kept in Reset as long as has been altered from previous devices of this family. PWRT is active. The PWRT delay allows the VDD to Voltages applied to the pin that exceed its specification rise to an acceptable level. A Configuration bit, PWRTE can result in both MCLR Resets and excessive current can disable (if set) or enable (if cleared or beyond the device specification during the ESD event. programmed) the Power-up Timer. The Power-up For this reason, Microchip recommends that the MCLR Timer should always be enabled when Brown-out pin no longer be tied directly to VDD. The use of an RC Detect is enabled. network, as shown in Figure9-5, is suggested. The Power-up Time delay will vary from chip to chip An internal MCLR option is enabled by setting the and due to: MCLRE bit in the Configuration Word. When enabled, MCLR is internally tied to VDD. No internal pull-up • VDD variation option is available for the MCLR pin. • Temperature variation • Process variation. FIGURE 9-5: RECOMMENDED MCLR See DC parameters for details (Section12.0 “Electri- CIRCUIT cal Specifications”). VDD PIC12F629/675 9.3.4 OSCILLATOR START-UP TIMER (OST) R1 1 kor greater The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the MCLR PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. C1 The OST time-out is invoked only for XT, LP and HS 0.1 f modes and only on Power-on Reset or wake-up from (optional, not critical) Sleep. 9.3.2 POWER-ON RESET (POR) The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details (see Section12.0 “Electrical Specifications”). If the BOD is enabled, the maximum rise time specification does not apply. The BOD circuitry will keep the device in Reset until VDD reaches VBOD (see Section9.3.5 “Brown-Out Detect (BOD)”). Note: The POR circuit does not produce an internal Reset when VDD declines. When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. DS41190G-page 58  2010 Microchip Technology Inc.

PIC12F629/675 9.3.5 BROWN-OUT DETECT (BOD) On any Reset (Power-on, Brown-out, Watchdog, etc.), the chip will remain in Reset until VDD rises above The PIC12F629/675 members have on-chip Brown-out BVDD (see Figure9-6). The Power-up Timer will now Detect circuitry. A Configuration bit, BODEN, can be invoked, if enabled, and will keep the chip in Reset disable (if clear/programmed) or enable (if set) the an additional 72ms. Brown-out Detect circuitry. If VDD falls below VBOD for greater than parameter (TBOD) in Table12-4 (see Note: A Brown-out Detect does not enable the Section12.0 “Electrical Specifications”), the Power-up Timer if the PWRTE bit in the Brown-out situation will reset the device. This will occur Configuration Word is set. regardless of VDD slew-rate. A Reset is not guaranteed If VDD drops below BVDD while the Power-up Timer is to occur if VDD falls below VBOD for less than parameter running, the chip will go back into a Brown-out Detect (TBOD). and the Power-up Timer will be re-initialized. Once VDD rises above BVDD, the Power-up Timer will execute a 72ms Reset. FIGURE 9-6: BROWN-OUT SITUATIONS VDD VBOD Internal Reset 72 ms(1) VDD VBOD Internal <72 ms Reset 72 ms(1) VDD VBOD Internal Reset 72 ms(1) Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’. 9.3.6 TIME-OUT SEQUENCE 9.3.7 POWER CONTROL (PCON) STATUS REGISTER On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired. The power CONTROL/STATUS register, PCON Then, OST is activated. The total time-out will vary (address 8Eh) has two bits. based on oscillator configuration and PWRTE bit Bit 0 is BOD (Brown-out). BOD is unknown on Power- status. For example, in EC mode with PWRTE bit on Reset. It must then be set by the user and checked erased (PWRT disabled), there will be no time-out at on subsequent Resets to see if BOD = 0, indicating that all. Figure9-7, Figure9-8 and Figure9-9 depict time- a brown-out has occurred. The BOD Status bit is a out sequences. “don’t care” and is not necessarily predictable if the Since the time-outs occur from the POR pulse, if MCLR brown-out circuit is disabled (by setting BODEN bit = 0 is kept low long enough, the time-outs will expire. Then in the Configuration Word). bringing MCLR high will begin execution immediately Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on (see Figure9-8). This is useful for testing purposes or Reset and unaffected otherwise. The user must write a to synchronize more than one PIC12F629/675 device ‘1’ to this bit following a Power-on Reset. On a operating in parallel. subsequent Reset, if POR is ‘0’, it will indicate that a Table9-6 shows the Reset conditions for some special Power-on Reset must have occurred (i.e., VDD may registers, while Table9-7 shows the Reset conditions have gone too low). for all the registers.  2010 Microchip Technology Inc. DS41190G-page 59

PIC12F629/675 TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Brown-out Detect Wake-up Oscillator Configuration from Sleep PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 XT, HS, LP TPWRT + 1024•TOSC TPWRT + 1024•TOSC 1024•TOSC 1024•TOSC 1024•TOSC RC, EC, INTOSC TPWRT — TPWRT — — TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOD TO PD 0 u 1 1 Power-on Reset 1 0 1 1 Brown-out Detect u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown TABLE 9-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOD Resets(1) 03h STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu 8Eh PCON — — — — — — POR BOD ---- --0x ---- --uq Legend:u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation. TABLE 9-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during Sleep 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Detect 000h 0001 1uuu ---- --10 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu Legend:u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS41190G-page 60  2010 Microchip Technology Inc.

PIC12F629/675 TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERS • MCLR Reset during • Wake-up from Sleep normal operation through interrupt Power-on Register Address • MCLR Reset during Sleep • Wake-up from Sleep Reset • WDT Reset through WDT Time-out • Brown-out Detect(1) W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h — — — TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu GPIO 05h --xx xxxx --uu uuuu --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 000u uuuu uuqq(2) PIR1 0Ch 00-- 0--0 00-- 0--0 qq-- q--q(2,5) T1CON 10h -000 0000 -uuu uuuu -uuu uuuu CMCON 19h -0-0 0000 -0-0 0000 -u-u uuuu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISIO 85h --11 1111 --11 1111 --uu uuuu PIE1 8Ch 00-- 0--0 00-- 0--0 uu-- u--u PCON 8Eh ---- --0x ---- --uu(1,6) ---- --uu OSCCAL 90h 1000 00-- 1000 00-- uuuu uu-- WPU 95h --11 -111 --11 -111 uuuu uuuu IOC 96h --00 0000 --00 0000 --uu uuuu VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu EEDATA 9Ah 0000 0000 0000 0000 uuuu uuuu EEADR 9Bh -000 0000 -000 0000 -uuu uuuu EECON1 9Ch ---- x000 ---- q000 ---- uuuu EECON2 9Dh ---- ---- ---- ---- ---- ---- ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ANSEL 9Fh -000 1111 -000 1111 -uuu uuuu Legend:u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector(0004h). 4: See Table9-6 for Reset value for specific condition. 5: If wake-up was due to data EEPROM write completing, Bit 7 = 1; A/D conversion completing, Bit 6 = 1; Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a wake-up will cause these bits to = u. 6: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.  2010 Microchip Technology Inc. DS41190G-page 61

PIC12F629/675 FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41190G-page 62  2010 Microchip Technology Inc.

PIC12F629/675 9.4 Interrupts determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before The PIC12F629/675 has 7 sources of interrupt: re-enabling interrupts to avoid multiple interrupt • External Interrupt GP2/INT requests. • TMR0 Overflow Interrupt Note 1: Individual interrupt flag bits are set, • GPIO Change Interrupts regardless of the status of their • Comparator Interrupt corresponding mask bit or the GIE bit. • A/D Interrupt (PIC12F675 only) 2: When an instruction that clears the GIE • TMR1 Overflow Interrupt bit is executed, any interrupts that were pending for execution in the next cycle • EEPROM Data Write Interrupt are ignored. The interrupts which were The Interrupt Control register (INTCON) and Peripheral ignored are still pending to be serviced Interrupt register (PIR) record individual interrupt when the GIE bit is set again. requests in flag bits. The INTCON register also has individual and Global Interrupt Enable (GIE) bits. A Global Interrupt Enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register and PIE register. GIE is cleared on Reset. The return from interrupt instruction, RETFIE, exits interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: • INT pin interrupt • GP port change interrupt • TMR0 overflow interrupt The peripheral interrupt flags are contained in the special register PIR1. The corresponding interrupt enable bit is contained in special register PIE1. The following interrupt flags are contained in the PIR register: • EEPROM data write interrupt • A/D interrupt • Comparator interrupt • Timer1 overflow interrupt When an interrupt is serviced: • The GIE is cleared to disable any further interrupt • The return address is pushed onto the stack • The PC is loaded with 0004h Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid GP2/ INT recursive interrupts. For external interrupt events, such as the INT pin, or GP port change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure9-11). The latency is the same for one or two- cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be  2010 Microchip Technology Inc. DS41190G-page 63

PIC12F629/675 FIGURE 9-10: INTERRUPT LOGIC IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 T0IF Wake-up (If in Sleep mode) T0IE INTF INTE Interrupt to CPU TMR1IF GPIF TMR1IE GPIE CMIF CMIE PEIE ADIF (1) GIE ADIE EEIF EEIE Note 1: PIC12F675 only. DS41190G-page 64  2010 Microchip Technology Inc.

PIC12F629/675 9.4.1 GP2/INT INTERRUPT 9.4.3 GPIO INTERRUPT External interrupt on GP2/INT pin is edge-triggered; An input change on GPIO change sets the GPIF either rising if INTEDG bit (OPTION<6>) is set, of (INTCON<0>) bit. The interrupt can be enabled/ falling, if INTEDG bit is clear. When a valid edge disabled by setting/clearing the GPIE (INTCON<3>) appears on the GP2/INT pin, the INTF bit (INT- bit. Plus individual pins can be configured through the CON<1>) is set. This interrupt can be disabled by IOC register. clearing the INTE control bit (INTCON<4>). The INTF Note: If a change on the I/O pin should occur bit must be cleared in software in the Interrupt Service when the read operation is being executed Routine before re-enabling this interrupt. The GP2/INT (start of the Q2 cycle), then the GPIF interrupt can wake-up the processor from Sleep if the interrupt flag may not get set. INTE bit was set prior to going into Sleep. The status of the GIE bit decides whether or not the processor 9.4.4 COMPARATOR INTERRUPT branches to the interrupt vector following wake-up. See Section9.7 “Power-Down Mode (Sleep)” for details See Section6.9 “Comparator Interrupts” for on Sleep and Figure9-13 for timing of wake-up from description of comparator interrupt. Sleep through GP2/INT interrupt. 9.4.5 A/D CONVERTER INTERRUPT Note: The ANSEL (9Fh) and CMCON (19h) registers must be initialized to configure an After a conversion is complete, the ADIF flag (PIR<6>) analog channel as a digital input. Pins is set. The interrupt can be enabled/disabled by setting configured as analog inputs will read ‘0’. or clearing ADIE (PIE<6>). The ANSEL register is defined for the See Section7.0 “Analog-to-Digital Converter (A/D) PIC12F675. Module (PIC12F675 only)” for operation of the A/D converter interrupt. 9.4.2 TMR0 INTERRUPT An overflow (FFh  00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section4.0 “Timer0 Module”. FIGURE 9-11: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF Flag 5 Interrupt Latency 2 (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h) Instruction Inst (PC - 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2010 Microchip Technology Inc. DS41190G-page 65

PIC12F629/675 TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOD Resets 0Bh, 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000u 0Ch PIR1 EEIF ADIF — — CMIF — — TMR1IF 00-- 0--0 00-- 0--0 8Ch PIE1 EEIE ADIE — — CMIE — — TMR1IE 00-- 0--0 00-- 0--0 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. 9.5 Context Saving During Interrupts 9.6 Watchdog Timer (WDT) During an interrupt, only the return PC value is saved The Watchdog Timer is a free running, on-chip RC on the stack. Typically, users may wish to save key oscillator, which requires no external components. This registers during an interrupt (e.g., W register and RC oscillator is separate from the external RC oscillator STATUS register). This must be implemented in of the CLKIN pin and INTOSC. That means that the software. WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example, by Example9-2 stores and restores the STATUS and W execution of a SLEEP instruction). During normal registers. The user register, W_TEMP, must be defined operation, a WDT Time-out generates a device Reset. in both banks and must be defined at the same offset If the device is in Sleep mode, a WDT Time-out causes from the bank base address (i.e., W_TEMP is defined the device to wake-up and continue with normal at 0x20 in Bank 0 and it must also be defined at 0xA0 operation. The WDT can be permanently disabled by in Bank 1). The user register, STATUS_TEMP, must be programming the Configuration bit WDTE as clear defined in Bank 0. The Example9-2: (Section9.1 “Configuration Bits”). • Stores the W register • Stores the STATUS register in Bank 0 9.6.1 WDT PERIOD • Executes the ISR code The WDT has a nominal time-out period of 18 ms, (with • Restores the STATUS (and bank select bit no prescaler). The time-out periods vary with register) temperature, VDD and process variations from part to • Restores the W register part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 EXAMPLE 9-2: SAVING THE STATUS AND can be assigned to the WDT under software control by W REGISTERS IN RAM writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. MOVWF W_TEMP ;copy W to temp register, could be in either bank The CLRWDT and SLEEP instructions clear the WDT SWAPF STATUS,W ;swap status to be saved into W BCF STATUS,RP0 ;change to bank 0 regardless of and the prescaler, if assigned to the WDT, and prevent current bank it from timing out and generating a device Reset. MOVWF STATUS_TEMP ;save status to bank 0 register : The TO bit in the STATUS register will be cleared upon :(ISR) a Watchdog Timer Time-out. : SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into W, sets bank to original state 9.6.2 WDT PROGRAMMING MOVWF STATUS ;move W into STATUS register CONSIDERATIONS SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W It should also be taken in account that under worst- case conditions (i.e., VDD = Min., Temperature = Max., Max. WDT prescaler) it may take several seconds before a WDT Time-out occurs. DS41190G-page 66  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 9-12: WATCHDOG TIMER BLOCK DIAGRAM CLKOUT (= FOSC/4) Data Bus 0 8 1 SYNC 2 1 TMR0 Cycles T0CKI 0 pin 0 T0SE T0CS 8-bit Set Flag bit T0IF on Overflow Prescaler PSA 1 8 PSA PS0 - PS2 1 WDT Time-out Watchdog 0 Timer PSA WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register. TABLE 9-9: SUMMARY OF WATCHDOG TIMER REGISTERS Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOD Resets 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 2007h Config. bits CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.  2010 Microchip Technology Inc. DS41190G-page 67

PIC12F629/675 9.7 Power-Down Mode (Sleep) The first event will cause a device Reset. The two latter events are considered a continuation of program exe- The Power-down mode is entered by executing a cution. The TO and PD bits in the STATUS register can SLEEP instruction. be used to determine the cause of device Reset. The If the Watchdog Timer is enabled: PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT Wake-up occurred. • WDT will be cleared but keeps running • PD bit in the STATUS register is cleared When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device • TO bit is set to wake-up through an interrupt event, the correspond- • Oscillator driver is turned off ing interrupt enable bit must be set (enabled). Wake-up • I/O ports maintain the status they had before is regardless of the state of the GIE bit. If the GIE bit is Sleep was executed (driving high, low, or clear (disabled), the device continues execution at the high-impedance). instruction after the SLEEP instruction. If the GIE bit is For lowest current consumption in this mode, all I/O set (enabled), the device executes the instruction after pins should be either at VDD, or VSS, with no external the SLEEP instruction, then branches to the interrupt circuitry drawing current from the I/O pin and the com- address (0004h). In cases where the execution of the parators and CVREF should be disabled. I/O pins that instruction following SLEEP is not desirable, the user are high-impedance inputs should be pulled high or low should have an NOP after the SLEEP instruction. externally to avoid switching currents caused by float- Note: If the global interrupts are disabled (GIE is ing inputs. The T0CKI input should also be at VDD or cleared), but any interrupt source has both VSS for lowest current consumption. The contribution its interrupt enable bit and the correspond- from on-chip pull-ups on GPIO should be considered. ing interrupt flag bits set, the device will The MCLR pin must be at a logic high level (VIHMC). immediately wake-up from Sleep. The SLEEP instruction is completely executed. Note: It should be noted that a Reset generated by a WDT Time-out does not drive MCLR The WDT is cleared when the device wakes up from pin low. Sleep, regardless of the source of wake-up. 9.7.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin 2. Watchdog Timer Wake-up (if WDT was enabled) 3. Interrupt from GP2/INT pin, GPIO change, or a peripheral interrupt. FIGURE 9-13: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit Processor in (INTCON<7>) Sleep INSTRUCTION FLOW PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale). Approximately 1 s delay will be there for RC Osc mode. See Section 12 for wake-up from Sleep delay in INTOSC mode. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference. DS41190G-page 68  2010 Microchip Technology Inc.

PIC12F629/675 9.8 Code Protection FIGURE 9-14: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING If the code protection bit(s) have not been CONNECTION programmed, the on-chip program memory can be read out for verification purposes. To Normal Note: The entire data EEPROM and Flash Connections External program memory will be erased when the Connector PIC12F629/675 code protection is turned off. The INTOSC Signals calibration data is also erased. See +5V VDD PIC12F629/675 Programming Specifica- tion for more information. 0V VSS VPP GP3/MCLR/VPP 9.9 ID Locations CLK GP1 Four memory locations (2000h-2003h) are designated Data I/O GP0 as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are VDD readable and writable during Program/Verify. Only the Least Significant 7 bits of the ID locations are used. To Normal Connections 9.10 In-Circuit Serial Programming The PIC12F629/675 microcontrollers can be serially 9.11 In-Circuit Debugger programmed while in the end application circuit. This is simply done with two lines for clock and data, and three Since in-circuit debugging requires the loss of clock, other lines for: data and MCLR pins, MPLAB® ICD 2 development with • power an 8-pin device is not practical. A special 14-pin PIC12F675-ICD device is used with MPLAB ICD 2 to • ground provide separate clock, data and MCLR pins and frees • programming voltage all normally available pins to the user. This allows customers to manufacture boards with This special ICD device is mounted on the top of the unprogrammed devices, and then program the header and its signals are routed to the MPLAB ICD 2 microcontroller just before shipping the product. This connector. On the bottom of the header is an 8-pin also allows the most recent firmware or a custom socket that plugs into the user’s target via the 8-pin firmware to be programmed. stand-off connector. The device is placed into a Program/Verify mode by When the ICD pin on the PIC12F675-ICD device is holding the GP0 and GP1 pins low, while raising the held low, the In-Circuit Debugger functionality is MCLR (VPP) pin from VIL to VIHH (see Programming enabled. This function allows simple debugging Specification). GP0 becomes the programming data functions when used with MPLAB ICD 2. When the and GP1 becomes the programming clock. Both GP0 microcontroller has this feature enabled, some of the and GP1 are Schmitt Trigger inputs in this mode. resources are not available for general use. Table9-10 After Reset, to place the device into Programming/ shows which features are consumed by the Verify mode, the PC is at location 00h. A 6-bit background debugger: command is then supplied to the device. Depending on the command, 14-bits of program data are then TABLE 9-10: DEBUGGER RESOURCES supplied to or from the device, depending on whether the command was a load or a read. For complete I/O pins ICDCLK, ICDDATA details of serial programming, please refer to the Stack 1 level Programming Specifications. Program Memory Address 0h must be NOP A typical In-Circuit Serial Programming connection is 300h-3FEh shown in Figure9-14. For more information, see 8-Pin MPLAB ICD 2 Header Information Sheet (DS51292) available on Microchip’s web site (www.microchip.com).  2010 Microchip Technology Inc. DS41190G-page 69

PIC12F629/675 NOTES: DS41190G-page 70  2010 Microchip Technology Inc.

PIC12F629/675 10.0 INSTRUCTION SET SUMMARY For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to The PIC12F629/675 instruction set is highly orthogonal GPIO. This example would have the unintended result and is comprised of three basic categories: that the condition that sets the GPIF flag would be • Byte-oriented operations cleared. • Bit-oriented operations TABLE 10-1: OPCODE FIELD • Literal and control operations DESCRIPTIONS Each PIC12F629/675 instruction is a 14-bit word divided into an opcode, which specifies the instruction Field Description type, and one or more operands, which further specify f Register file address (0x00 to 0x7F) the operation of the instruction. The formats for each of W Working register (accumulator) the categories is presented in Figure10-1, while the various opcode fields are summarized in Table10-1. b Bit address within an 8-bit file register Table10-2 lists the instructions recognized by the k Literal field, constant data or label MPASMTM assembler. A complete description of x Don’t care location (= 0 or 1). each instruction is also available in the PIC® Mid- The assembler will generate code with x = 0. Range Reference Manual (DS33023). It is the recommended form of use for For byte-oriented instructions, ‘f’ represents a file compatibility with all Microchip software tools. register designator and ‘d’ represents a destination d Destination select; d = 0: store result in W, designator. The file register designator specifies which d = 1: store result in file register f. file register is to be used by the instruction. Default is d = 1. The destination designator specifies where the result of PC Program Counter the operation is to be placed. If ‘d’ is zero, the result is TO Time-out bit placed in the W register. If ‘d’ is one, the result is placed PD Power-down bit in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field FIGURE 10-1: GENERAL FORMAT FOR designator, which selects the bit affected by the INSTRUCTIONS operation, while ‘f’ represents the address of the file in which the bit is located. Byte-oriented file register operations For literal and control operations, ‘k’ represents an 8- 13 8 7 6 0 bit or 11-bit constant, or literal value. OPCODE d f (FILE #) One instruction cycle consists of four oscillator periods; d = 0 for destination W for an oscillator frequency of 4 MHz, this gives a normal d = 1 for destination f f = 7-bit file register address instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is Bit-oriented file register operations 13 10 9 7 6 0 changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the OPCODE b (BIT #) f (FILE #) second cycle executed as a NOP. b = 3-bit bit address f = 7-bit file register address Note: To maintain upward compatibility with future products, do not use the OPTION and TRISIO instructions. Literal and control operations General All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a 13 8 7 0 hexadecimal digit. OPCODE k (literal) k = 8-bit immediate value 10.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of CALL and GOTO instructions only the instruction performs a Read-Modify-Write (R-M-W) 13 11 10 0 operation. The register is read, the data is modified, OPCODE k (literal) and the result is stored according to either the instruc- k = 11-bit immediate value tion, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.  2010 Microchip Technology Inc. DS41190G-page 71

PIC12F629/675 TABLE 10-2: PIC12F629/675 INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW - Clear W 1 00 0001 0xxx xxxx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2 MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2 MOVWF f Move W to f 1 00 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2 BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLW k Move literal to W 1 11 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into Standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Note: Additional information on the mid-range instruction set is available in the PIC® Mid-Range MCU Family Ref- erence Manual (DS33023). DS41190G-page 72  2010 Microchip Technology Inc.

PIC12F629/675 10.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [label] ADDLW k Syntax: [label] BCF f,b Operands: 0  k  255 Operands: 0  f  127 0  b  7 Operation: (W) + k  (W) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: The contents of the W register are added to the eight-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared. and the result is placed in the W register. ADDWF Add W and f BSF Bit Set f Syntax: [label] ADDWF f,d Syntax: [label] BSF f,b Operands: 0  f  127 Operands: 0  f  127 d  0  b  7 Operation: (W) + (f)  (destination) Operation: 1  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set. with register ‘f’. If ‘d’ is 0, the result is stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’. ANDLW AND Literal with W BTFSS Bit Test f, Skip if Set Syntax: [label] ANDLW k Syntax: [label] BTFSS f,b Operands: 0  k  255 Operands: 0  f  127 0  b < 7 Operation: (W) .AND. (k)  (W) Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The contents of W register are AND’ed with the eight-bit literal Description: If bit ‘b’ in register ‘f’ is ‘0’, the next ‘k’. The result is placed in the W instruction is executed. register. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction. ANDWF AND W with f Syntax: [label] ANDWF f,d Operands: 0  f  127 d  Operation: (W) .AND. (f)  (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is 0, the result is stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.  2010 Microchip Technology Inc. DS41190G-page 73

PIC12F629/675 BTFSC Bit Test, Skip if Clear CLRWDT Clear Watchdog Timer Syntax: [label] BTFSC f,b Syntax: [ label ] CLRWDT Operands: 0  f  127 Operands: None 0  b  7 Operation: 00h  WDT Operation: skip if (f<b>) = 0 0  WDT prescaler, Status Affected: None 1  TO 1  PD Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. Status Affected: TO, PD If bit ‘b’, in register ‘f’, is ‘0’, the Description: CLRWDT instruction resets the next instruction is discarded, and Watchdog Timer. It also resets the a NOP is executed instead, making prescaler of the WDT. this a 2TCY instruction. Status bits TO and PD are set. CALL Call Subroutine COMF Complement f Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d Operands: 0  k  2047 Operands: 0  f  127 Operation: (PC)+ 1 TOS, d  [0,1] k  PC<10:0>, Operation: (f)  (destination) (PCLATH<4:3>)  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are Description: Call Subroutine. First, return complemented. If ‘d’ is 0, the address (PC + 1) is pushed onto result is stored in W. If ‘d’ is 1, the the stack. The eleven-bit immedi- result is stored back in register ‘f’. ate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. DECF Decrement f CLRF Clear f Syntax: [label] DECF f,d Syntax: [label] CLRF f Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) Operation: (f) - 1  (destination) 1  Z Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is 0, Description: The contents of register ‘f’ are the result is stored in the W cleared and the Z bit is set. register. If ‘d’ is 1, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS41190G-page 74  2010 Microchip Technology Inc.

PIC12F629/675 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is 0, the result incremented. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is 1, the result is placed back in 1, the result is placed back in register ‘f’. register ‘f’. If the result is 1, the next instruc- If the result is 1, the next instruc- tion is executed. If the result is 0, tion is executed. If the result is 0, then a NOP is executed instead, a NOP is executed instead, making making it a 2TCY instruction. it a 2TCY instruction. GOTO Unconditional Branch IORLW Inclusive OR Literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<4:3>  PC<12:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’. The eleven-bit immediate value is The result is placed in the W loaded into PC bits <10:0>. The register. upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two- cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: Inclusive OR the W register with incremented. If ‘d’ is 0, the result register ‘f’. If ‘d’ is 0, the result is is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is 1, 1, the result is placed back in the result is placed back in register ‘f’. register ‘f’.  2010 Microchip Technology Inc. DS41190G-page 75

PIC12F629/675 MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: (W)  (f) Operation: (f)  (dest) Status Affected: None Status Affected: Z Description: Move data from W register to Description: The contents of register f is register ‘f’. moved to a destination dependent Words: 1 upon the status of d. If d = 0, Cycles: 1 the destination is W register. If d = 1, the destination is file register f Example: MOVWF OPTION itself. d = 1 is useful to test a file Before Instruction register since status flag Z is OPTION= 0xFF affected. W = 0x4F Words: 1 After Instruction OPTION= 0x4F Cycles: 1 W = 0x4F Example: MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 NOP No Operation MOVLW Move literal to W Syntax: [ label ] NOP Syntax: [ label ] MOVLW k Operands: None Operands: 0  k  255 Operation: No operation Operation: k  (W) Status Affected: None Status Affected: None Description: No operation. Description: The eight-bit literal ‘k’ is loaded into Words: 1 W register. The “don’t cares” will assemble as ‘0’s. Cycles: 1 Words: 1 Example: NOP Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A DS41190G-page 76  2010 Microchip Technology Inc.

PIC12F629/675 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k Operands: None Operands: 0  k  255 Operation: TOS  PC, Operation: k  (W); 1  GIE TOS  PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is Description: The W register is loaded with the POPed and Top-of-Stack (TOS) is eight-bit literal ‘k’. The program loaded in the PC. Interrupts are counter is loaded from the top of enabled by setting Global the stack (the return address). Interrupt Enable bit, GIE This is a two-cycle instruction. (INTCON<7>). This is a two-cycle Words: 1 instruction. Cycles: 2 Words: 1 Example: CALL TABLE;W contains Cycles: 2 table Example: RETFIE ;offset value TABLE • ;W now has table value After Interrupt • PC = TOS • GIE= 1 ADDWF PCL;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS  PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction.  2010 Microchip Technology Inc. DS41190G-page 77

PIC12F629/675 SUBLW Subtract W from Literal RLF Rotate Left f through Carry Syntax: [ label ] SUBLW k Syntax: [ label ] RLF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s complement method) from the Description: The contents of register ‘f’ are rotated eight-bit literal ‘k’. The result is one bit to the left through the Carry placed in the W register. Flag. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is stored back in register ‘f’. C Register f SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d Operands: 0 f 127 RRF Rotate Right f through Carry d  [0,1] Syntax: [ label ] RRF f,d Operation: (f) - (W) destination) Operands: 0  f  127 Status C, DC, Z d  [0,1] Affected: Operation: See description below Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is Status Affected: C 0, the result is stored in the W Description: The contents of register ‘f’ are register. If ‘d’ is 1, the result is rotated one bit to the right through stored back in register ‘f’. the Carry Flag. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is placed back in register ‘f’. SWAPF Swap Nibbles in f C Register f Syntax: [ label ] SWAPF f,d Operands: 0  f  127 d  [0,1] Operation: (f<3:0>)  (destination<7:4>), SLEEP (f<7:4>)  (destination<3:0>) Syntax: [ label ] SLEEP Status Affected: None Operands: None Description: The upper and lower nibbles of Operation: 00h  WDT, register ‘f’ are exchanged. If ‘d’ is 0  WDT prescaler, 0, the result is placed in the W 1  TO, register. If ‘d’ is 1, the result is 0  PD placed in register ‘f’. Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. DS41190G-page 78  2010 Microchip Technology Inc.

PIC12F629/675 XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] XORLW k Syntax: [label] XORWF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: (W) .XOR. k W) Operation: (W) .XOR. (f) destination) Status Affected: Z Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit Description: Exclusive OR the contents of the literal ‘k’. The result is placed in W register with register ‘f’. If ‘d’ is the W register. 0, the result is stored in the W register. If ‘d’ is 1, the result is stored back in register ‘f’.  2010 Microchip Technology Inc. DS41190G-page 79

PIC12F629/675 NOTES: DS41190G-page 80  2010 Microchip Technology Inc.

PIC12F629/675 11.0 DEVELOPMENT SUPPORT 11.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software The MPLAB IDE software brings an ease of software and hardware development tools: development previously unseen in the 8/16/32-bit • Integrated Development Environment microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: - MPLAB® IDE Software • Compilers/Assemblers/Linkers • A single graphical interface to all debugging tools - MPLAB C Compiler for Various Device - Simulator Families - Programmer (sold separately) - HI-TECH C for Various Device Families - In-Circuit Emulator (sold separately) - MPASMTM Assembler - In-Circuit Debugger (sold separately) - MPLINKTM Object Linker/ • A full-featured editor with color-coded context MPLIBTM Object Librarian • A multiple project manager - MPLAB Assembler/Linker/Librarian for • Customizable data windows with direct edit of Various Device Families contents • Simulators • High-level source code debugging - MPLAB SIM Software Simulator • Mouse over variable inspection • Emulators • Drag and drop variables from source to watch - MPLAB REAL ICE™ In-Circuit Emulator windows • In-Circuit Debuggers • Extensive on-line help - MPLAB ICD 3 • Integration of select third party tools, such as - PICkit™ 3 Debug Express IAR C Compilers • Device Programmers The MPLAB IDE allows you to: - PICkit™ 2 Programmer • Edit your source files (either C or assembly) - MPLAB PM3 Device Programmer • One-touch compile or assemble, and download to • Low-Cost Demonstration/Development Boards, emulator and simulator tools (automatically Evaluation Kits, and Starter Kits updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS41190G-page 81

PIC12F629/675 11.2 MPLAB C Compilers for Various 11.5 MPLINK Object Linker/ Device Families MPLIB Object Librarian The MPLAB C Compiler code development systems The MPLINK Object Linker combines relocatable are complete ANSI C compilers for Microchip’s PIC18, objects created by the MPASM Assembler and the PIC24 and PIC32 families of microcontrollers and the MPLAB C18 C Compiler. It can link relocatable objects dsPIC30 and dsPIC33 families of digital signal control- from precompiled libraries, using directives from a lers. These compilers provide powerful integration linker script. capabilities, superior code optimization and ease of The MPLIB Object Librarian manages the creation and use. modification of library files of precompiled code. When For easy source level debugging, the compilers provide a routine from a library is called from a source file, only symbol information that is optimized to the MPLAB IDE the modules that contain that routine will be linked in debugger. with the application. This allows large libraries to be used efficiently in many different applications. 11.3 HI-TECH C for Various Device The object linker/library features include: Families • Efficient linking of single libraries instead of many The HI-TECH C Compiler code development systems smaller files are complete ANSI C compilers for Microchip’s PIC • Enhanced code maintainability by grouping family of microcontrollers and the dsPIC family of digital related modules together signal controllers. These compilers provide powerful • Flexible creation of libraries with easy module integration capabilities, omniscient code generation listing, replacement, deletion and extraction and ease of use. For easy source level debugging, the compilers provide 11.6 MPLAB Assembler, Linker and symbol information that is optimized to the MPLAB IDE Librarian for Various Device debugger. Families The compilers include a macro assembler, linker, pre- MPLAB Assembler produces relocatable machine processor, and one-step driver, and can run on multiple code from symbolic assembly language for PIC24, platforms. PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler 11.4 MPASM Assembler generates relocatable object files that can then be The MPASM Assembler is a full-featured, universal archived or linked with other relocatable object files and macro assembler for PIC10/12/16/18 MCUs. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for the entire device instruction set files, MAP files to detail memory usage and symbol • Support for fixed-point and floating-point data reference, absolute LST files that contain source lines • Command line interface and generated machine code and COFF files for • Rich directive set debugging. • Flexible macro language The MPASM Assembler features include: • MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS41190G-page 82  2010 Microchip Technology Inc.

PIC12F629/675 11.7 MPLAB SIM Software Simulator 11.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- MPLAB ICD 3 In-Circuit Debugger System is Micro- ing the PIC MCUs and dsPIC® DSCs on an instruction chip’s most cost effective high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash Digital Sig- examined or modified and stimuli can be applied from nal Controller (DSC) and microcontroller (MCU) a comprehensive stimulus controller. Registers can be devices. It debugs and programs PIC® Flash microcon- logged to files for further run-time analysis. The trace trollers and dsPIC® DSCs with the powerful, yet easy- buffer and logic analyzer display extend the power of to-use graphical user interface of MPLAB Integrated the simulator to record and track program execution, Development Environment (IDE). actions on I/O, most peripherals and internal registers. The MPLAB ICD 3 In-Circuit Debugger probe is The MPLAB SIM Software Simulator fully supports connected to the design engineer’s PC using a high- symbolic debugging using the MPLAB CCompilers, speed USB 2.0 interface and is connected to the target and the MPASM and MPLAB Assemblers. The soft- with a connector compatible with the MPLAB ICD 2 or ware simulator offers the flexibility to develop and MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 debug code outside of the hardware laboratory envi- supports all MPLAB ICD 2 headers. ronment, making it an excellent, economical software development tool. 11.10 PICkit 3 In-Circuit Debugger/ Programmer and 11.8 MPLAB REAL ICE In-Circuit PICkit 3 Debug Express Emulator System The MPLAB PICkit 3 allows debugging and MPLAB REAL ICE In-Circuit Emulator System is programming of PIC® and dsPIC® Flash Microchip’s next generation high-speed emulator for microcontrollers at a most affordable price point using Microchip Flash DSC and MCU devices. It debugs and the powerful graphical user interface of the MPLAB programs PIC® Flash MCUs and dsPIC® Flash DSCs Integrated Development Environment (IDE). The with the easy-to-use, powerful graphical user interface of MPLAB PICkit 3 is connected to the design engineer’s the MPLAB Integrated Development Environment (IDE), PC using a full speed USB interface and can be included with each kit. connected to the target via an Microchip debug (RJ-11) The emulator is connected to the design engineer’s PC connector (compatible with MPLAB ICD 3 and MPLAB using a high-speed USB 2.0 interface and is connected REAL ICE). The connector uses two device I/O pins to the target with either a connector compatible with in- and the reset line to implement in-circuit debugging and circuit debugger systems (RJ11) or with the new high- In-Circuit Serial Programming™. speed, noise tolerant, Low-Voltage Differential Signal The PICkit 3 Debug Express include the PICkit 3, demo (LVDS) interconnection (CAT5). board and microcontroller, hookup cables and CDROM The emulator is field upgradable through future firmware with user’s guide, lessons, tutorial, compiler and downloads in MPLAB IDE. In upcoming releases of MPLAB IDE software. MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers signifi- cant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a rugge- dized probe interface and long (up to three meters) inter- connection cables.  2010 Microchip Technology Inc. DS41190G-page 83

PIC12F629/675 11.11 PICkit 2 Development 11.13 Demonstration/Development Programmer/Debugger and Boards, Evaluation Kits, and PICkit 2 Debug Express Starter Kits The PICkit™ 2 Development Programmer/Debugger is A wide variety of demonstration, development and a low-cost development tool with an easy to use inter- evaluation boards for various PIC MCUs and dsPIC face for programming and debugging Microchip’s Flash DSCs allows quick application development on fully func- families of microcontrollers. The full featured tional systems. Most boards include prototyping areas for Windows® programming interface supports baseline adding custom circuitry and provide application firmware (PIC10F, PIC12F5xx, PIC16F5xx), midrange and source code for examination and modification. (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, The boards support a variety of features, including LEDs, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit temperature sensors, switches, speakers, RS-232 microcontrollers, and many Microchip Serial EEPROM interfaces, LCD displays, potentiometers and additional products. With Microchip’s powerful MPLAB Integrated EEPROM memory. Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcon- The demonstration and development boards can be trollers. In-Circuit-Debugging runs, halts and single used in teaching environments, for prototyping custom steps the program while the PIC microcontroller is circuits and for learning about various microcontroller embedded in the application. When halted at a break- applications. point, the file registers can be examined and modified. In addition to the PICDEM™ and dsPICDEM™ demon- The PICkit 2 Debug Express include the PICkit 2, demo stration/development board series of circuits, Microchip board and microcontroller, hookup cables and CDROM has a line of evaluation kits and demonstration software with user’s guide, lessons, tutorial, compiler and for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® MPLAB IDE software. evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. 11.12 MPLAB PM3 Device Programmer Also available are starter kits that contain everything The MPLAB PM3 Device Programmer is a universal, needed to experience the specified device. This usually CE compliant device programmer with programmable includes a single application and debug capability, all voltage verification at VDDMIN and VDDMAX for on one board. maximum reliability. It features a large LCD display Check the Microchip web page (www.microchip.com) (128 x 64) for menus and error messages and a modu- for the complete list of demonstration, development lar, detachable socket assembly to support various and evaluation kits. package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS41190G-page 84  2010 Microchip Technology Inc.

PIC12F629/675 12.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings† Ambient temperature under bias...........................................................................................................-40 to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ..................................................................................................... -0.3 to +6.5V Voltage on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V Voltage on all other pins with respect to VSS ...........................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin.....................................................................................................................300 mA Maximum current into VDD pin........................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin..............................................................................................25 mA Maximum current sunk by all GPIO................................................................................................................125 mA Maximum current sourced all GPIO................................................................................................................125 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD -  IOH} +  {(VDD-VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100  should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS.  2010 Microchip Technology Inc. DS41190G-page 85

PIC12F629/675 FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, -40°C  TA  +125°C 5.5 5.0 4.5 4.0 VDD (Volts) 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C  TA  +125°C 5.5 5.0 4.5 4.0 VDD (Volts) 3.5 3.0 2.5 2.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41190G-page 86  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C  TA  +125°C 5.5 5.0 4.5 4.0 VDD (Volts) 3.5 3.0 2.5 2.2 2.0 0 4 8 10 12 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency.  2010 Microchip Technology Inc. DS41190G-page 87

PIC12F629/675 12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. VDD Supply Voltage FOSC < = 4 MHz: D001 2.0 — 5.5 V PIC12F629/675 with A/D off D001A 2.2 — 5.5 V PIC12F675 with A/D on, 0°C to +125°C D001B 2.5 — 5.5 V PIC12F675 with A/D on, -40°C to +125°C D001C 3.0 — 5.5 V 4 MHZ < FOSC < = 10 MHz D001D 4.5 — 5.5 V D002 VDR RAM Data Retention 1.5* — — V Device in Sleep mode Voltage(1) D003 VPOR VDD Start Voltage to — VSS — V See section on Power-on Reset for details ensure internal Power-on Reset signal D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See section on Power-on Reset for details internal Power-on Reset signal D005 VBOD — 2.1 — V * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. DS41190G-page 88  2010 Microchip Technology Inc.

PIC12F629/675 12.2 DC Characteristics: PIC12F629/675-I (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +85C for industrial Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D010 Supply Current (IDD) — 9 16 A 2.0 FOSC = 32kHz — 18 28 A 3.0 LP Oscillator Mode — 35 54 A 5.0 D011 — 110 150 A 2.0 FOSC = 1MHz — 190 280 A 3.0 XT Oscillator Mode — 330 450 A 5.0 D012 — 220 280 A 2.0 FOSC = 4MHz — 370 650 A 3.0 XT Oscillator Mode — 0.6 1.4 mA 5.0 D013 — 70 110 A 2.0 FOSC = 1MHz — 140 250 A 3.0 EC Oscillator Mode — 260 390 A 5.0 D014 — 180 250 A 2.0 FOSC = 4MHz — 320 470 A 3.0 EC Oscillator Mode — 580 850 A 5.0 D015 — 340 450 A 2.0 FOSC = 4MHz — 500 700 A 3.0 INTOSC Mode — 0.8 1.1 mA 5.0 D016 — 180 250 A 2.0 FOSC = 4MHz — 320 450 A 3.0 EXTRC Mode — 580 800 A 5.0 D017 — 2.1 2.95 mA 4.5 FOSC = 20MHz — 2.4 3.0 mA 5.0 HS Oscillator Mode † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.  2010 Microchip Technology Inc. DS41190G-page 89

PIC12F629/675 12.3 DC Characteristics: PIC12F629/675-I (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +85C for industrial Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020 Power-down Base Current — 0.99 700 nA 2.0 WDT, BOD, Comparators, VREF, (IPD) — 1.2 770 nA 3.0 and T1OSC disabled — 2.9 995 nA 5.0 D021 — 0.3 1.5 A 2.0 WDT Current(1) — 1.8 3.5 A 3.0 — 8.4 17 A 5.0 D022 — 58 70 A 3.0 BOD Current(1) — 109 130 A 5.0 D023 — 3.3 6.5 A 2.0 Comparator Current(1) — 6.1 8.5 A 3.0 — 11.5 16 A 5.0 D024 — 58 70 A 2.0 CVREF Current(1) — 85 100 A 3.0 — 138 160 A 5.0 D025 — 4.0 6.5 A 2.0 T1 OSC Current(1) — 4.6 7.0 A 3.0 — 6.0 10.5 A 5.0 D026 — 1.2 775 nA 3.0 A/D Current(1) — 0.0022 1.0 A 5.0 † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. DS41190G-page 90  2010 Microchip Technology Inc.

PIC12F629/675 12.4 DC Characteristics: PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +125C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D010E Supply Current (IDD) — 9 16 A 2.0 FOSC = 32kHz — 18 28 A 3.0 LP Oscillator Mode — 35 54 A 5.0 D011E — 110 150 A 2.0 FOSC = 1MHz — 190 280 A 3.0 XT Oscillator Mode — 330 450 A 5.0 D012E — 220 280 A 2.0 FOSC = 4MHz — 370 650 A 3.0 XT Oscillator Mode — 0.6 1.4 mA 5.0 D013E — 70 110 A 2.0 FOSC = 1MHz — 140 250 A 3.0 EC Oscillator Mode — 260 390 A 5.0 D014E — 180 250 A 2.0 FOSC = 4MHz — 320 470 A 3.0 EC Oscillator Mode — 580 850 A 5.0 D015E — 340 450 A 2.0 FOSC = 4MHz — 500 780 A 3.0 INTOSC Mode — 0.8 1.1 mA 5.0 D016E — 180 250 A 2.0 FOSC = 4MHz — 320 450 A 3.0 EXTRC Mode — 580 800 A 5.0 D017E — 2.1 2.95 mA 4.5 FOSC = 20MHz — 2.4 3.0 mA 5.0 HS Oscillator Mode † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.  2010 Microchip Technology Inc. DS41190G-page 91

PIC12F629/675 12.5 DC Characteristics: PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C  TA  +125C for extended Conditions Param Device Characteristics Min Typ† Max Units No. VDD Note D020E Power-down Base Current — 0.00099 3.5 A 2.0 WDT, BOD, Comparators, VREF, (IPD) — 0.0012 4.0 A 3.0 and T1OSC disabled — 0.0029 8.0 A 5.0 D021E — 0.3 6.0 A 2.0 WDT Current(1) — 1.8 9.0 A 3.0 — 8.4 20 A 5.0 D022E — 58 70 A 3.0 BOD Current(1) — 109 130 A 5.0 D023E — 3.3 10 A 2.0 Comparator Current(1) — 6.1 13 A 3.0 — 11.5 24 A 5.0 D024E — 58 70 A 2.0 CVREF Current(1) — 85 100 A 3.0 — 138 165 A 5.0 D025E — 4.0 10 A 2.0 T1 OSC Current(1) — 4.6 12 A 3.0 — 6.0 20 A 5.0 D026E — 0.0012 6.0 A 3.0 A/D Current(1) — 0.0022 8.5 A 5.0 † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. DS41190G-page 92  2010 Microchip Technology Inc.

PIC12F629/675 12.6 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Input Low Voltage VIL I/O ports D030 with TTL buffer VSS — 0.8 V 4.5V  VDD  5.5V D030A VSS — 0.15 VDD V Otherwise D031 with Schmitt Trigger buffer VSS — 0.2 VDD V Entire range D032 MCLR, OSC1 (RC mode) VSS — 0.2 VDD V D033 OSC1 (XT and LP modes) VSS — 0.3 V (Note 1) D033A OSC1 (HS mode) VSS — 0.3 VDD V (Note 1) Input High Voltage VIH I/O ports — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A (0.25 VDD+0.8) — VDD V otherwise D041 with Schmitt Trigger buffer 0.8 VDD — VDD entire range D042 MCLR 0.8 VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V (Note 1) D043A OSC1 (HS mode) 0.7 VDD — VDD V (Note 1) D043B OSC1 (RC mode) 0.9 VDD — VDD V D070 IPUR GPIO Weak Pull-up Current 50* 250 400* A VDD = 5.0V, VPIN = VSS Input Leakage Current(3) D060 IIL I/O ports — 01 1 A VSS VPIN VDD, Pin at high-impedance D060A Analog inputs — 01 1 A VSS VPIN VDD D060B VREF — 01 1 A VSS VPIN VDD D061 MCLR(2) — 01 5 A VSS VPIN VDD D063 OSC1 — 01 5 A VSS VPIN VDD, XT, HS and LP osc configuration Output Low Voltage D080 VOL I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) D083 OSC2/CLKOUT (RC mode) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V (Ind.) IOL = 1.2 mA, VDD = 4.5V (Ext.) Output High Voltage D090 VOH I/O ports VDD - 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.) D092 OSC2/CLKOUT (RC mode) VDD - 0.7 — — V IOH = -1.3 mA, VDD = 4.5V (Ind.) IOH = -1.0 mA, VDD = 4.5V (Ext.) * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2010 Microchip Technology Inc. DS41190G-page 93

PIC12F629/675 12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15* pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins — — 50* pF Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40C  TA +85°C D120A ED Byte Endurance 10K 100K — E/W +85°C  TA +125°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write cycle time — 5 6 ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write 1M 10M — E/W -40C  TA +85°C Cycles before Refresh(1) Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40C  TA +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C  TA +125°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Erase/Write 4.5 — 5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Section8.5.1 “Using the Data EEPROM” for additional information. DS41190G-page 94  2010 Microchip Technology Inc.

PIC12F629/675 12.8 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-Impedance) V Valid L Low Z High-Impedance FIGURE 12-4: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL Pin CL Pin CL VSS VSS RL = 464 CL = 50 pF for all pins 15 pF for OSC2 output  2010 Microchip Technology Inc. DS41190G-page 95

PIC12F629/675 12.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED) FIGURE 12-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. FOSC External CLKIN Frequency(1) DC — 37 kHz LP Osc mode DC — 4 MHz XT mode DC — 20 MHz HS mode DC — 20 MHz EC mode Oscillator Frequency(1) 5 — 37 kHz LP Osc mode — 4 — MHz INTOSC mode DC — 4 MHz RC Osc mode 0.1 — 4 MHz XT Osc mode 1 — 20 MHz HS Osc mode 1 TOSC External CLKIN Period(1) 27 —  s LP Osc mode 50 —  ns HS Osc mode 50 —  ns EC Osc mode 250 —  ns XT Osc mode Oscillator Period(1) 27 200 s LP Osc mode — 250 — ns INTOSC mode 250 — — ns RC Osc mode 250 — 10,000 ns XT Osc mode 50 — 1,000 ns HS Osc mode 2 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC 3 TosL, External CLKIN (OSC1) High 2* — — s LP oscillator, TOSC L/H duty cycle TosH External CLKIN Low 20* — — ns HS oscillator, TOSC L/H duty cycle 100 * — — ns XT oscillator, TOSC L/H duty cycle 4 TosR, External CLKIN Rise — — 50* ns LP oscillator TosF External CLKIN Fall — — 25* ns XT oscillator — — 15* ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is “DC” (no clock) for all devices. DS41190G-page 96  2010 Microchip Technology Inc.

PIC12F629/675 TABLE 12-2: PRECISION INTERNAL OSCILLATOR PARAMETERS Param Freq. Sym Characteristic Min Typ† Max Units Conditions No. Tolerance F10 FOSC Internal Calibrated 1 3.96 4.00 4.04 MHz VDD = 3.5V, 25C INTOSC Frequency 2 3.92 4.00 4.08 MHz 2.5V VDD  5.5V 0C  TA  +85C 5 3.80 4.00 4.20 MHz 2.0V VDD  5.5V -40C  TA  +85C (IND) -40C  TA  +125C (EXT) F14 TIOSCST Oscillator Wake-up from — — 6 8 s VDD = 2.0V, -40C to +85C Sleep start-up time* — — 4 6 s VDD = 3.0V, -40C to +85C — — 3 5 s VDD = 5.0V, -40C to +85C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS41190G-page 97

PIC12F629/675 FIGURE 12-6: CLKOUT AND I/O TIMING Q4 Q1 Q2 Q3 OSC1 11 10 22 CLKOUT 23 13 12 19 18 14 16 I/O pin (Input) 17 15 I/O pin Old Value New Value (Output) 20, 21 TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 10 TosH2ckL OSC1 to CLOUT — 75 200 ns (Note 1) 11 TosH2ckH OSC1 to CLOUT — 75 200 ns (Note 1) 12 TckR CLKOUT rise time — 35 100 ns (Note 1) 13 TckF CLKOUT fall time — 35 100 ns (Note 1) 14 TckL2ioV CLKOUT to Port out valid — — 20 ns (Note 1) 15 TioV2ckH Port in valid before CLKOUT TOSC + 200 — — ns (Note 1) ns 16 TckH2ioI Port in hold after CLKOUT 0 — — ns (Note 1) 17 TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 * ns — — 300 ns 18 TosH2ioI OSC1 (Q2 cycle) to Port input 100 — — ns invalid (I/O in hold time) 19 TioV2osH Port input valid to OSC1 0 — — ns (I/O in setup time) 20 TioR Port output rise time — 10 40 ns 21 TioF Port output fall time — 10 40 ns 22 Tinp INT pin high or low time 25 — — ns 23 Trbp GPIO change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. Note 1:Measurements are taken in RC mode where CLKOUT output is 4xTOSC. DS41190G-page 98  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD BVDD (Device not in Brown-out Detect) (Device in Brown-out Detect) 35 Reset (due to BOD) 72 ms time-out(1) Note 1: 72 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.  2010 Microchip Technology Inc. DS41190G-page 99

PIC12F629/675 TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT DETECT REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C TBD TBD TBD ms Extended temperature 31 TWDT Watchdog Timer Time-out 10 17 25 ms VDD = 5V, -40°C to +85°C Period 10 17 30 ms Extended temperature (No Prescaler) 32 TOST Oscillation Start-up Timer — 1024TOSC — — TOSC = OSC1 period Period 33* TPWRT Power-up Timer Period 28* 72 132* ms VDD = 5V, -40°C to +85°C TBD TBD TBD ms Extended Temperature 34 TIOZ I/O High-impedance from — — 2.0 s MCLR Low or Watchdog Timer Reset BVDD Brown-out Detect Voltage 2.025 — 2.175 V Brown-out Hysteresis TBD — — — 35 TBOD Brown-out Detect Pulse Width 100* — — s VDD  BVDD (D005) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41190G-page 100  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 12-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 48 TMR0 or TMR1 TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* Tt0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4, ..., 256) N 45* Tt1H T1CKI High Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 46* Tt1L T1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, 15 — — ns with Prescaler Asynchronous 30 — — ns 47* Tt1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 (1, 2, 4, 8) N Asynchronous 60 — — ns Ft1 Timer1 oscillator input frequency range DC — 200* kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1 Delay from external clock edge to timer increment 2 TOSC* — 7 — TOSC* * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS41190G-page 101

PIC12F629/675 TABLE 12-6: COMPARATOR SPECIFICATIONS Standard Operating Conditions Comparator Specifications -40°C to +125°C (unless otherwise stated) Sym Characteristics Min Typ Max Units Comments VOS Input Offset Voltage —  5.0  10 mV VCM Input Common Mode Voltage 0 — VDD - 1.5 V CMRR Common Mode Rejection Ratio +55* — — db TRT Response Time(1) — 150 400* ns TMC2COV Comparator Mode Change to — — 10* s Output Valid * These parameters are characterized but not tested. Note1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD - 1.5V. TABLE 12-7: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions Voltage Reference Specifications -40°C to +125°C (unless otherwise stated) Sym Characteristics Min Typ Max Units Comments Resolution — VDD/24* — LSb Low Range (VRR = 1) — VDD/32 — LSb High Range (VRR = 0) Absolute Accuracy — —  1/2 LSb Low Range (VRR = 1) — — 1/2* LSb High Range (VRR = 0) Unit Resistor Value (R) — 2k* —  Settling Time(1) — — 10* s * These parameters are characterized but not tested. Note1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. DS41190G-page 102  2010 Microchip Technology Inc.

PIC12F629/675 TABLE 12-8: PIC12F675 A/D CONVERTER CHARACTERISTICS: Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 10 bits bit A02 EABS Total Absolute — — 1 LSb VREF = 5.0V Error* A03 EIL Integral Error — — 1 LSb VREF = 5.0V A04 EDL Differential Error — — 1 LSb No missing codes to 10 bits VREF = 5.0V A05 EFS Full Scale Range 2.2* — 5.5* V A06 EOFF Offset Error — — 1 LSb VREF = 5.0V A07 EGN Gain Error — — 1 LSb VREF = 5.0V A10 — Monotonicity — guaranteed(3) — — VSS  VAIN  VREF+ A20 VREF Reference Voltage 2.0 — — V A20A 2.5 VDD + 0.3 Absolute minimum to ensure 10-bit accuracy A21 VREF Reference V High VSS — VDD V (VDD or VREF) A25 VAIN Analog Input VSS — VREF V Voltage A30 ZAIN Recommended — — 10 k Impedance of Analog Voltage Source A50 IREF VREF Input 10 — 1000 A During VAIN acquisition. Current(2) Based on differential of VHOLD to VAIN. — — 10 A During A/D conversion cycle. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from External VREF or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.  2010 Microchip Technology Inc. DS41190G-page 103

PIC12F629/675 FIGURE 12-10: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 (TOSC/2)(1) 1 TCY 131 Q4 130 A/D CLK A/D DATA 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE SAMPLING STOPPED SAMPLE 132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 12-9: PIC12F675 A/D CONVERSION REQUIREMENTS Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D Clock Period 1.6 — — s TOSC based, VREF 3.0V 3.0* — — s TOSC based, VREF full range 130 TAD A/D Internal RC ADCS<1:0> = 11 (RC mode) Oscillator Period 3.0* 6.0 9.0* s At VDD = 2.5V 2.0* 4.0 6.0* s At VDD = 5.0V 131 TCNV Conversion Time — 11 — TAD Set GO bit to new data in A/D result (not including register Acquisition Time)(1) 132 TACQ Acquisition Time (Note 2) 11.5 — s 5* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 4.1mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). 134 TGO Q4 to A/D Clock — TOSC/2 — — If the A/D clock source is selected as Start RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section7.1 “A/D Configuration and Operation” for minimum conditions. DS41190G-page 104  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 12-11: PIC12F675 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO 134 (TOSC/2 + TCY)(1) 1 TCY 131 Q4 130 A/D CLK A/D DATA 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE SAMPLING STOPPED SAMPLE 132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D Clock Period 1.6 — — s VREF 3.0V 3.0* — — s VREF full range 130 TAD A/D Internal RC ADCS<1:0> = 11 (RC mode) Oscillator Period 3.0* 6.0 9.0* s At VDD = 2.5V 2.0* 4.0 6.0* s At VDD = 5.0V 131 TCNV Conversion Time — 11 — TAD (not including Acquisition Time)(1) 132 TACQ Acquisition Time (Note 2) 11.5 — s 5* — — s The minimum time is the amplifier settling time. This may be used if the “new” input voltage has not changed by more than 1 LSb (i.e., 4.1 mV @ 4.096V) from the last sampled voltage (as stored on CHOLD). 134 TGO Q4 to A/D Clock — TOSC/2 + TCY — — If the A/D clock source is selected Start as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section7.1 “A/D Configuration and Operation” for minimum conditions.  2010 Microchip Technology Inc. DS41190G-page 105

PIC12F629/675 NOTES: DS41190G-page 106  2010 Microchip Technology Inc.

PIC12F629/675 13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. “Typical” represents the mean of the distribution at 25°C. “Max” or “min” represents (mean+3) or (mean-3) respectively, where  is standard deviation, over the whole temperature range. FIGURE 13-1: TYPICAL IPD vs. VDD OVER TEMP (-40°C TO +25°C) Typical Baseline IPD 6.0E-09 5.0E-09 4.0E-09 ) -40 A (D 3.0E-09 0 P I 25 2.0E-09 1.0E-09 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-2: TYPICAL IPD vs. VDD OVER TEMP (+85°C) Typical Baseline IPD 3.5E-07 3.0E-07 2.5E-07 ) A 2.0E-07 ( D 85 P I 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2010 Microchip Technology Inc. DS41190G-page 107

PIC12F629/675 FIGURE 13-3: TYPICAL IPD vs. VDD OVER TEMP (+125°C) Typical Baseline IPD 4.0E-06 3.5E-06 3.0E-06 2.5E-06 ) A (D 2.0E-06 125 P I 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-4: MAXIMUM IPD vs. VDD OVER TEMP (-40°C TO +25°C) Maximum Baseline IPD 1.0E-07 9.0E-08 8.0E-08 7.0E-08 )6.0E-08 -40 A (D 5.0E-08 0 P I4.0E-08 25 3.0E-08 2.0E-08 1.0E-08 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) DS41190G-page 108  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 13-5: MAXIMUM IPD vs. VDD OVER TEMP (+85°C) Maximum Baseline IPD 9.0E-07 8.0E-07 7.0E-07 6.0E-07 ) A ( 5.0E-07 D 85 P 4.0E-07 I 3.0E-07 2.0E-07 1.0E-07 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-6: MAXIMUM IPD vs. VDD OVER TEMP (+125°C) Maximum Baseline IPD 9.0E-06 8.0E-06 7.0E-06 6.0E-06 ) A 5.0E-06 (D 125 P 4.0E-06 I 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2010 Microchip Technology Inc. DS41190G-page 109

PIC12F629/675 FIGURE 13-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical BOD IPD 130 120 110 -40 A) 100 0 u ( 90 25 D IP 80 85 125 70 60 50 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-8: TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical Comparator IPD 1.8E-05 1.6E-05 1.4E-05 1.2E-05 -40 ) 0 A 1.0E-05 ( D 25 P 8.0E-06 I 85 6.0E-06 125 4.0E-06 2.0E-06 0.0E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41190G-page 110  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 13-9: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C) Typical A/D IPD 5.0E-09 4.5E-09 4.0E-09 3.5E-09 A) 3.0E-09 -40 (D 2.5E-09 0 IP 2.0E-09 25 1.5E-09 1.0E-09 5.0E-10 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-10: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C) Typical A/D IPD 3.5E-07 3.0E-07 2.5E-07 A)2.0E-07 (D 85 IP 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V)  2010 Microchip Technology Inc. DS41190G-page 111

PIC12F629/675 FIGURE 13-11: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C) Typical A/D IPD 3.5E-06 3.0E-06 ) 2.5E-06 A ( D 2.0E-06 P I 125 1.5E-06 1.0E-06 5.0E-07 0.0E+00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-12: TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C), 32kHZ, C1 AND C2=50pF) Typical T1 IPD 1.20E-05 1.00E-05 -40 8.00E-06 ) 0 A (D 6.00E-06 25 P I 85 4.00E-06 125 2.00E-06 0.00E+00 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41190G-page 112  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 13-13: TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical CVREFIPD 160 140 -40 120 A) 0 u ( 100 25 D IP 85 80 125 60 40 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 13-14: TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C) Typical WDT IPD 16 14 12 -40 A) 10 0 u ( 8 25 D IP 6 85 4 125 2 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V)  2010 Microchip Technology Inc. DS41190G-page 113

PIC12F629/675 FIGURE 13-15: MAXIMUM AND MINIMUMINTOSC FREQ vs. TEMPERATURE WITH 0.1F AND 0.01F DECOUPLING (VDD = 3.5V) Internal Oscillator Frequency vs Temperature 4.20E+06 4.15E+06 ) z 4.10E+06 H y ( 4.05E+06 -3sigma c n 4.00E+06 average e u 3.95E+06 +3sigma q e 3.90E+06 r F 3.85E+06 3.80E+06 -40°C 0°C 25°C 85°C 125°C Temperature (°C) FIGURE 13-16: MAXIMUM AND MINIMUMINTOSC FREQ vs. VDD WITH 0.1F AND 0.01F DECOUPLING (+25°C) Internal Oscillator Frequency vs VDD 4.20E+06 4.15E+06 z) H 4.10E+06 cy ( 4.05E+06 -3sigma n e 4.00E+06 average u q 3.95E+06 +3sigma e r 3.90E+06 F 3.85E+06 3.80E+06 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V VDD (V) DS41190G-page 114  2010 Microchip Technology Inc.

PIC12F629/675 FIGURE 13-17: TYPICAL WDT PERIOD vs. VDD (-40C TO +125C) WDT Time-out 50 45 40 35 -40 ) S m 30 0 e ( 25 25 m Ti 20 85 15 125 10 5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V)  2010 Microchip Technology Inc. DS41190G-page 115

PIC12F629/675 NOTES: DS41190G-page 116  2010 Microchip Technology Inc.

PIC12F629/675 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 8-Lead PDIP (Skinny DIP) Example XXXXXXXX 12F629-I XXXXXNNN /017 e3 YYWW 0215 8-Lead SOIC Example XXXXXXXX 12F629-E XXXXYYWW /0215 e3 NNN 017 8-Lead DFN-S Example XXXXXXX 12F629 XXXXXXX -E/021e3 XXYYWW 0215 NNN 017 8-Lead DFN (4x4 mm) Example XXXXXX XXXXXX XXXXXX XXXX e3 YYWW 0610 NNN 017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2010 Microchip Technology Inc. DS41190G-page 117

PIC12F629/675 14.2 Package Details The following sections give the technical details of the packages. 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(cid:25)(cid:3) (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:24)(cid:29) 1(cid:28)!(cid:14)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)(cid:29) = = (cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)"(cid:16)#(cid:14)(cid:9)(cid:2)>(cid:7)#&(cid:11) . (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)-(cid:30)(cid:4) (cid:20)-(cid:3)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)(cid:29)(cid:4) (cid:20)(cid:3)<(cid:4) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:20)-(cid:23)< (cid:20)-?(cid:29) (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)&(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)&(cid:7)(cid:15)(cid:17)(cid:2)(cid:31)(cid:16)(cid:28)(cid:15)(cid:14) 9 (cid:20)(cid:30)(cid:30)(cid:29) (cid:20)(cid:30)-(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)(cid:29) 6(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) )(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)?(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 9(cid:10)*(cid:14)(cid:9)(cid:2)9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)*(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)+ (cid:14)1 = = (cid:20)(cid:23)-(cid:4) (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)/(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2(cid:2)1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<1 DS41190G-page 118  2010 Microchip Technology Inc.

PIC12F629/675 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e N E E1 NOTE1 1 2 3 α b h h c A A2 φ A1 L L1 β 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) = = (cid:30)(cid:20)(cid:5)(cid:29) (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)(cid:3) (cid:30)(cid:20)(cid:3)(cid:29) = = (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2)(cid:2)+ (cid:25)(cid:30) (cid:4)(cid:20)(cid:30)(cid:4) = (cid:4)(cid:20)(cid:3)(cid:29) : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), (cid:6)(cid:10)(cid:16)#(cid:14)#(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)>(cid:7)#&(cid:11) .(cid:30) -(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:23)(cid:20)(cid:24)(cid:4)(cid:2)1(cid:22), ,(cid:11)(cid:28)’%(cid:14)(cid:9)(cid:2)@(cid:10)(cid:12)&(cid:7)(cid:10)(cid:15)(cid:28)(cid:16)A (cid:11) (cid:4)(cid:20)(cid:3)(cid:29) = (cid:4)(cid:20)(cid:29)(cid:4) 3(cid:10)(cid:10)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:23)(cid:4) = (cid:30)(cid:20)(cid:3)(cid:5) 3(cid:10)(cid:10)&(cid:12)(cid:9)(cid:7)(cid:15)& 9(cid:30) (cid:30)(cid:20)(cid:4)(cid:23)(cid:2)(cid:26).3 3(cid:10)(cid:10)&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)B = <B 9(cid:14)(cid:28)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:8) (cid:4)(cid:20)(cid:30)(cid:5) = (cid:4)(cid:20)(cid:3)(cid:29) 9(cid:14)(cid:28)#(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:30) = (cid:4)(cid:20)(cid:29)(cid:30) (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)(cid:13)(cid:10)(cid:12) (cid:4) (cid:29)B = (cid:30)(cid:29)B (cid:6)(cid:10)(cid:16)#(cid:2)(cid:21)(cid:9)(cid:28)%&(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14)(cid:2)1(cid:10)&&(cid:10)’ (cid:5) (cid:29)B = (cid:30)(cid:29)B (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) +(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)&(cid:2),(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)&(cid:14)(cid:9)(cid:7)!&(cid:7)(cid:8)(cid:20) -(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)!(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)#(cid:2).(cid:30)(cid:2)#(cid:10)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)"#(cid:14)(cid:2)’(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)#(cid:2)%(cid:16)(cid:28)!(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)&(cid:9)"!(cid:7)(cid:10)(cid:15)!(cid:2)!(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)&(cid:2)(cid:14)$(cid:8)(cid:14)(cid:14)#(cid:2)(cid:4)(cid:20)(cid:30)(cid:29)(cid:2)’’(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)!(cid:7)#(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:4)(cid:29)(cid:5)1  2010 Microchip Technology Inc. DS41190G-page 119

PIC12F629/675 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:24)(cid:6)(cid:10)(cid:10)(cid:8)!(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19) (cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)""(cid:26)#$(cid:8)(cid:22)%&(cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28) !(cid:17)’(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS41190G-page 120  2010 Microchip Technology Inc.

PIC12F629/675 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)((cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6)*(cid:5)(cid:8)(cid:19)+((cid:20)(cid:8)(cid:21)(cid:8),-.(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:15)((cid:30)(cid:3) (cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) (cid:2) e D L b N N K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A A3 A1 NOTE2 6(cid:15)(cid:7)&! (cid:6)(cid:19)99(cid:19)(cid:6).(cid:13).(cid:26)(cid:22) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:2)9(cid:7)’(cid:7)&! (cid:6)(cid:19)7 7:(cid:6) (cid:6)(cid:25); 7"’)(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)(cid:31)(cid:7)(cid:15)! 7 < (cid:31)(cid:7)&(cid:8)(cid:11) (cid:14) (cid:30)(cid:20)(cid:3)(cid:5)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)8(cid:14)(cid:7)(cid:17)(cid:11)& (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)<(cid:29) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)&(cid:28)(cid:15)#(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:30) (cid:4)(cid:20)(cid:4)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)4(cid:15)(cid:14)!! (cid:25)- (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26).3 : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21) (cid:29)(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), : (cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)>(cid:7)#&(cid:11) . ?(cid:20)(cid:4)(cid:4)(cid:2)1(cid:22), .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) (cid:21)(cid:3) -(cid:20)(cid:24)(cid:4) (cid:23)(cid:20)(cid:4)(cid:4) (cid:23)(cid:20)(cid:30)(cid:4) .$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)#(cid:2)>(cid:7)#&(cid:11) .(cid:3) (cid:3)(cid:20)(cid:3)(cid:4) (cid:3)(cid:20)-(cid:4) (cid:3)(cid:20)(cid:23)(cid:4) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)>(cid:7)#&(cid:11) ) (cid:4)(cid:20)-(cid:29) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)(cid:23)< ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:2)9(cid:14)(cid:15)(cid:17)&(cid:11) 9 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)?(cid:4) (cid:4)(cid:20)(cid:5)(cid:29) ,(cid:10)(cid:15)&(cid:28)(cid:8)&(cid:27)&(cid:10)(cid:27).$(cid:12)(cid:10)!(cid:14)#(cid:2)(cid:31)(cid:28)# C (cid:4)(cid:20)(cid:3)(cid:4) = = (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:30)(cid:20) (cid:31)(cid:7)(cid:15)(cid:2)(cid:30)(cid:2) (cid:7)!"(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)#(cid:14)$(cid:2)%(cid:14)(cid:28)&"(cid:9)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2) (cid:28)(cid:9)(cid:18)((cid:2))"&(cid:2)’"!&(cid:2))(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)*(cid:7)&(cid:11)(cid:7)(cid:15)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)&(cid:8)(cid:11)(cid:14)#(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)’(cid:28)(cid:18)(cid:2)(cid:11)(cid:28) (cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)’(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)$(cid:12)(cid:10)!(cid:14)#(cid:2)&(cid:7)(cid:14)(cid:2))(cid:28)(cid:9)!(cid:2)(cid:28)&(cid:2)(cid:14)(cid:15)#!(cid:20) -(cid:20) (cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)(cid:7)!(cid:2)!(cid:28)*(cid:2)!(cid:7)(cid:15)(cid:17)"(cid:16)(cid:28)&(cid:14)#(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)#(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6).(cid:2)0(cid:30)(cid:23)(cid:20)(cid:29)(cid:6)(cid:20) 1(cid:22),2 1(cid:28)!(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)&(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)$(cid:28)(cid:8)&(cid:2) (cid:28)(cid:16)"(cid:14)(cid:2)!(cid:11)(cid:10)*(cid:15)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)!(cid:20) (cid:26).32 (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)’(cid:14)(cid:15)!(cid:7)(cid:10)(cid:15)((cid:2)"!"(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)*(cid:7)&(cid:11)(cid:10)"&(cid:2)&(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)((cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)’(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)"(cid:9)(cid:12)(cid:10)!(cid:14)!(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17),(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)(cid:3)1  2010 Microchip Technology Inc. DS41190G-page 121

PIC12F629/675 (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS41190G-page 122  2010 Microchip Technology Inc.

PIC12F629/675 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-131E Sheet 1 of 2  2010 Microchip Technology Inc. DS41190G-page 123

PIC12F629/675 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging MicrochipTechnologyDrawingC04-131E Sheet 2 of 2 DS41190G-page 124  2010 Microchip Technology Inc.

PIC12F629/675 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)((cid:10)(cid:6)(cid:12)$(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14))(cid:6)*(cid:5)(cid:8)(cid:19)+D(cid:20)(cid:8)(cid:21)(cid:8)/-/-(cid:23)%&(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:15)((cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) 3(cid:10)(cid:9)(cid:2)&(cid:11)(cid:14)(cid:2)’(cid:10)!&(cid:2)(cid:8)"(cid:9)(cid:9)(cid:14)(cid:15)&(cid:2)(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:14)(cid:2)#(cid:9)(cid:28)*(cid:7)(cid:15)(cid:17)!((cid:2)(cid:12)(cid:16)(cid:14)(cid:28)!(cid:14)(cid:2)!(cid:14)(cid:14)(cid:2)&(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)(cid:31)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)&(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)&(cid:14)#(cid:2)(cid:28)&(cid:2) (cid:11)&&(cid:12)255***(cid:20)’(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)’5(cid:12)(cid:28)(cid:8)4(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2010 Microchip Technology Inc. DS41190G-page 125

PIC12F629/675 NOTES: DS41190G-page 126  2010 Microchip Technology Inc.

PIC12F629/675 APPENDIX A: DATA SHEET APPENDIX B: DEVICE REVISION HISTORY DIFFERENCES Revision A The differences between the PIC12F629/675 devices listed in this data sheet are shown in TableB-1. This is a new data sheet. TABLE B-1: DEVICE DIFFERENCES Revision B Feature PIC12F629 PIC12F675 Added characterization graphs. A/D No Yes Updated specifications. Added notes to indicate Microchip programmers maintain all Calibration bits to factory settings and the PIC12F675 ANSEL register must be initialized to configure pins as digital I/O. Updated MLF-S package name to DFN-S. Revision C Revision D (01/2007) Updated Package Drawings; Replace PICmicro with PIC; Revised Product ID example (b). Revision E (03/2007) Replaced Package Drawings (Rev. AM); Replaced Development Support Section. Revision F (09/2009) Updated Registers to new format; Added information to the “Package Marking Information” (8-Lead DFN) and “Package Details” sections (8-Lead Dual Flat, No Lead Package (MD) 4X4X0.9 mm Body (DFN)); Added Land Patterns for SOIC (SN) and DFN-S (MF) packages; Updated Register 3-2; Added MD Package to the Product identification System chapter; Other minor corrections. Revision G (03/2010) Updated the Instruction Set Summary section, adding pages 76 and 77.  2010 Microchip Technology Inc. DS41190G-page 127

PIC12F629/675 APPENDIX C: DEVICE MIGRATIONS APPENDIX D: MIGRATING FROM OTHER PIC® This section is intended to describe the functional and DEVICES electrical specification differences when migrating between functionally similar devices (such as from a This discusses some of the issues in migrating from PIC16C74A to a PIC16C74B). other PIC devices to the PIC12F6XX family of devices. Not Applicable D.1 PIC12C67X to PIC12F6XX TABLE 1: FEATURE COMPARISON Feature PIC12C67X PIC12F6XX Max Operating Speed 10MHz 20MHz Max Program Memory 2048 bytes 1024 bytes A/D Resolution 8-bit 10-bit Data EEPROM 16 bytes 64 bytes Oscillator Modes 5 8 Brown-out Detect N Y Internal Pull-ups GP0/1/3 GP0/1/2/4/5 Interrupt-on-change GP0/1/3 GP0/1/2/3/4/5 Comparator N Y Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. Note: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/ or the oscillator mode may be required. DS41190G-page 128  2010 Microchip Technology Inc.

PIC12F629/675 INDEX Interrupts....................................................................42 Operation....................................................................38 A Operation During SLEEP............................................41 A/D......................................................................................43 Output.........................................................................40 Acquisition Requirements...........................................47 Reference...................................................................41 Block Diagram.............................................................43 Response Time..........................................................41 Calculating Acquisition Time.......................................47 Comparator Specifications................................................102 Configuration and Operation.......................................43 Comparator Voltage Reference Specifications.................102 Effects of a RESET.....................................................48 Configuration Bits...............................................................54 Internal Sampling Switch (Rss) Impedance................47 Configuring the Voltage Reference.....................................41 Operation During SLEEP............................................48 Crystal Operation................................................................55 PIC12F675 Converter Characteristics......................103 Customer Change Notification Service.............................133 Source Impedance......................................................47 Customer Notification Service..........................................133 Summary of Registers................................................48 Customer Support.............................................................133 Absolute Maximum Ratings................................................85 D AC Characteristics Industrial and Extended..............................................96 Data EEPROM Memory ADCON0 Associated Registers/Bits...........................................52 A/D Control register (ADDRESS Code Protection..........................................................52 1Fh)....................................................................45 EEADR Register.........................................................49 Additional Pin Functions.....................................................21 EECON1 Register......................................................49 Interrupt-on-Change....................................................23 EECON2 Register......................................................49 Weak Pull-up...............................................................21 EEDATA Register.......................................................49 Analog Input Connection Considerations............................40 Data Memory Organization...................................................9 Analog-to-Digital Converter. See A/D DC Characteristics Assembler Extended and Industrial..............................................93 MPASM Assembler.....................................................82 Industrial.....................................................................88 Development Support.........................................................81 B Device Differences............................................................127 Block Diagram Device Migrations.............................................................128 TMR0/WDT Prescaler.................................................29 Device Overview...................................................................7 Block Diagrams E Analog Input Mode......................................................40 Analog Input Model.....................................................47 EEADR — EEPROM Address Register (ADDRESS Comparator Output.....................................................40 9Bh)............................................................................49 Comparator Voltage Reference..................................41 EECON1 — EEPROM Control register (Address GP0 and GP1 Pins......................................................24 9Ch)............................................................................50 GP2.............................................................................25 EEPROM Data Memory GP3.............................................................................25 Reading......................................................................51 GP4.............................................................................26 Spurious Write............................................................51 GP5.............................................................................26 Write Verify.................................................................51 On-Chip Reset Circuit.................................................57 Writing........................................................................51 RC Oscillator Mode.....................................................56 Electrical Specifications......................................................85 Timer1.........................................................................32 Errata....................................................................................5 Watchdog Timer..........................................................67 F Brown-out Firmware Instructions.........................................................71 Associated Registers..................................................60 G Brown-out Detect (BOD).....................................................59 Brown-out Detect Timing and Characteristics.....................99 General Purpose Register File.............................................9 GPIO C Associated Registers..................................................27 C Compilers GPIO — GPIO register (ADDRESS MPLAB C18................................................................82 05H)............................................................................21 Calibrated Internal RC Frequencies....................................97 GPIO Port...........................................................................21 CLKOUT.............................................................................56 GPIO, TRISIO Registers.....................................................21 Code Examples I Changing Prescaler....................................................31 Data EEPROM Read..................................................51 ID Locations........................................................................69 Data EEPROM Write..................................................51 In-Circuit Debugger.............................................................69 Initializing GPIO..........................................................21 In-Circuit Serial Programming.............................................69 Saving STATUS and W Registers in RAM.................66 Indirect Addressing, INDF and FSR Registers...................20 Write Verify.................................................................51 Instruction Format...............................................................71 Code Protection..................................................................69 Instruction Set.....................................................................71 Comparator.........................................................................37 ADDLW.......................................................................73 Associated Registers..................................................42 ADDWF......................................................................73 Configuration...............................................................39 ANDLW.......................................................................73 Effects of a RESET.....................................................41 ANDWF......................................................................73 I/O Operating Modes...................................................39 MOVF.........................................................................76  2010 Microchip Technology Inc. DS41190G-page 129

PIC12F629/675 BCF.............................................................................73 Stack...........................................................................19 BSF.............................................................................73 Pin Descriptions and Diagrams..........................................24 BTFSC........................................................................74 Pinout Descriptions BTFSS........................................................................73 PIC12F629...................................................................8 CALL...........................................................................74 PIC12F675...................................................................8 CLRF...........................................................................74 Power Control/Status Register (PCON)..............................59 CLRW.........................................................................74 Power-Down Mode (SLEEP)..............................................68 CLRWDT.....................................................................74 Power-on Reset (POR).......................................................58 COMF.........................................................................74 Power-up Timer (PWRT)....................................................58 DECF..........................................................................74 Prescaler.............................................................................31 DECFSZ......................................................................75 Switching Prescaler Assignment................................31 GOTO.........................................................................75 Program Memory Organization.............................................9 INCF............................................................................75 Programming, Device Instructions......................................71 INCFSZ.......................................................................75 R IORLW........................................................................75 RC Oscillator.......................................................................56 IORWF........................................................................75 Reader Response.............................................................134 MOVLW......................................................................76 READ-MODIFY-WRITE OPERATIONS.............................71 MOVWF......................................................................76 Registers NOP............................................................................76 ANSEL (Analog Select)..............................................46 RETFIE.......................................................................77 CONFIG (Configuration Word)...................................54 RETLW.......................................................................77 EEADR (EEPROM Address)......................................50 RETURN.....................................................................77 EECON1 (EEPROM Control).....................................51 RLF.............................................................................78 EEDAT (EEPROM Data)............................................49 RRF.............................................................................78 INTCON (Interrupt Control).........................................15 SLEEP........................................................................78 IOCB (Interrupt-on-Change GPIO).............................24 SUBLW.......................................................................78 Maps SUBWF.......................................................................78 PIC12F629.........................................................10 SWAPF.......................................................................78 PIC12F675.........................................................10 XORLW.......................................................................79 OPTION_REG (Option)..................................14, 30, 31 XORWF.......................................................................79 OSCCAL (Oscillator Calibration)................................18 Summary Table...........................................................72 PCON (Power Control)...............................................18 Internal 4 MHz Oscillator.....................................................56 PIE1 (Peripheral Interrupt Enable 1)...........................16 Internal Sampling Switch (Rss) Impedance........................47 PIR1 (Peripheral Interrupt 1).......................................17 Internet Address................................................................133 STATUS.....................................................................14 Interrupts.............................................................................63 T1CON (Timer1 Control)............................................34 A/D Converter.............................................................65 VRCON (Voltage Reference Control).........................42 Comparator.................................................................65 WPU (Weak Pull-up)...................................................23 Context Saving............................................................66 RESET................................................................................57 GP2/INT......................................................................65 Revision History................................................................127 GPIO...........................................................................65 S Summary of Registers................................................66 TMR0..........................................................................65 Software Simulator (MPLAB SIM)......................................83 IOC — INTERRUPT-ON-CHANGE GPIO register Special Features of the CPU..............................................53 (ADDRESS 96h).................................................................23 Special Function Registers.................................................10 M Special Functions Registers Summary...............................11 STATUS — STATUS Register (ADDRESS MCLR..................................................................................58 03h or 83h).................................................................13 Memory Organization T Data EEPROM Memory..............................................49 Microchip Internet Web Site..............................................133 Time-out Sequence............................................................59 Migrating from other PICmicro Devices............................128 Timer0.................................................................................29 MPLAB ASM30 Assembler, Linker, Librarian.....................82 Associated Registers..................................................31 MPLAB Integrated Development Environment Software....81 External Clock.............................................................30 MPLAB PM3 Device Programmer.......................................84 Interrupt......................................................................29 MPLAB REAL ICE In-Circuit Emulator System...................83 Operation....................................................................29 MPLINK Object Linker/MPLIB Object Librarian..................82 T0CKI.........................................................................30 O Timer1 Associated Registers..................................................35 OPCODE Field Descriptions...............................................71 Asynchronous Counter Mode.....................................35 Oscillator Configurations.....................................................55 Reading and Writing...........................................35 Oscillator Start-up Timer (OST)..........................................58 Interrupt......................................................................33 P Modes of Operations..................................................33 Packaging.........................................................................117 Operation During SLEEP............................................35 Details.......................................................................118 Oscillator.....................................................................35 Marking.....................................................................117 Prescaler....................................................................33 PCL and PCLATH...............................................................19 Timer1 Module with Gate Control.......................................32 Computed GOTO........................................................19 Timing Diagrams DS41190G-page 130  2010 Microchip Technology Inc.

PIC12F629/675 CLKOUT and I/O.........................................................98 External Clock.............................................................96 INT Pin Interrupt..........................................................65 PIC12F675 A/D Conversion (Normal Mode).............104 PIC12F675 A/D Conversion Timing (SLEEP Mode)..........................................................105 RESET, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer..................................................99 Time-out Sequence on Power-up (MCLR not Tied to VDD)/ Case 1................................................................62 Case 2................................................................62 Time-out Sequence on Power-up (MCLR Tied to VDD)....................................................62 Timer0 and Timer1 External Clock...........................101 Timer1 Incrementing Edge..........................................33 Timing Parameter Symbology.............................................95 TRISIO — GPIO Tri-state REGISTER (Address 85H)............................................................................22 V Voltage Reference Accuracy/Error.....................................41 W Watchdog Timer Summary of Registers................................................67 Watchdog Timer (WDT)......................................................66 WPU — Weak pull-up Register (ADDRESS 95h).............................................................................22 WWW Address..................................................................133 WWW, On-Line Support.......................................................5  2010 Microchip Technology Inc. DS41190G-page 131

PIC12F629/675 NOTES: DS41190G-page 132  2010 Microchip Technology Inc.

PIC12F629/675 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. DS41190G-page 133

PIC12F629/675 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC12F629/675 Literature Number: DS41190G Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41190G-page 134  2010 Microchip Technology Inc.

PIC12F629/675 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC12F629 - E/P 301 = Extended Temp., PDIP Range package, 20 MHz, QTP pattern #301. b) PIC12F675 - I/SN = Industrial temp., SOIC package, 20 MHz. Device: PIC12F6XX: Standard VDD range PIC12F6XXT: (Tape and Reel) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package: P = PDIP SN = SOIC (Gull wing, 3.90 mm body) MF = MLF-S MD = 8-Lead Plastic Dual Flat, No Lead (4X4) (DFN) Pattern: 3-Digit Pattern Code for QTP (blank otherwise) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type.  2010 Microchip Technology Inc. DS41190G-page 135

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