PIC12F510/16F506 Data Sheet 8/14-Pin, 8-Bit Flash Microcontrollers © 2007 Microchip Technology Inc. DS41268D

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron, and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, ensure that your application meets with your specifications. PICmicro, PICSTART, PROMATE, rfPIC and SmartShunt are MICROCHIP MAKES NO REPRESENTATIONS OR registered trademarks of Microchip Technology Incorporated WARRANTIES OF ANY KIND WHETHER EXPRESS OR in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The QUALITY, PERFORMANCE, MERCHANTABILITY OR Embedded Control Solutions Company are registered FITNESS FOR PURPOSE. Microchip disclaims all liability trademarks of Microchip Technology Incorporated in the arising from this information and its use. Use of Microchip U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS41268D-page ii © 2007 Microchip Technology Inc.

PIC12F510/16F506 8/14-Pin, 8-Bit Flash Microcontroller Devices Included In This Data Sheet: • Selectable Oscillator Options: - INTOSC: 4/8MHz precision Internal • PIC16F506 oscillator • PIC12F510 - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator High-Performance RISC CPU: - LP: Power-saving, low-frequency crystal - HS: High-speed crystal/resonator • Only 33 Single-Word Instructions to Learn (PIC16F506 only) • All Single-Cycle Instructions except for Program - EC: High-speed external clock input Branches, which are Two-Cycle (PIC16F506 only) • 12-Bit Wide Instructions • Analog-to-Digital (A/D) Converter: • Two-Level Deep Hardware Stack - 8-bit resolution • Direct, Indirect and Relative Addressing modes - 4-input channels (1 channel is dedicated to for Data and Instructions conversion of the internal 0.6V absolute • 8-Bit Wide Data Path voltage reference) • 10 Special Function Hardware Registers • High Current Sink/Source for Direct LED Drive (PIC12F510) • 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit • 13 Special Function Hardware Registers Programmable Prescaler (PIC16F506) • Operating Speed: Low-Power Features/CMOS Technology: - DC – 8MHz Crystal Oscillator (PIC12F510) • Operating Current: - DC – 500ns instruction cycle (PIC12F510) - < 175μA @ 2V, 4MHz, typical - DC – 20MHz Crystal Oscillator (PIC16F506) - DC – 200ns instruction cycle (PIC16F506) • Standby Current: - 100nA @ 2V, typical Special Microcontroller Features: • Low-Power, High-Speed Flash Technology: - 100,000 cycle Flash endurance • 4 or 8MHz Selectable Precision Internal - > 40-year retention Oscillator: • Fully Static Design - Factory calibrated to ±1% • Wide Operating Voltage Range: 2.0V to 5.5V • In-Circuit Serial Programming™ (ICSP™) • Wide Temperature Range: • In-Circuit Debugging (ICD) Support - Industrial: -40°C to +85°C • Power-on Reset (POR) - Extended: -40°C to +125°C • Device Reset Timer (DRT): - Short DRT (1.125ms, typical) for INTOSC, Peripheral Features (PIC12F510): EXTRC and EC - DRT (18ms, typical) for HS, XT and LP • 6 I/O Pins: • Watchdog Timer (WDT) with Dedicated On-Chip - 5 I/O pins with individual direction control RC Oscillator for Reliable Operation - 1 input only pin • Programmable Code Protection • 1 Analog Comparator with Absolute Reference • Multiplexed MCLR Input Pin Peripheral Features (PIC16F506): • Selectable Internal Weak Pull-Ups on I/O Pins • Power-Saving Sleep mode • 12 I/O Pins: • Wake-up from Sleep on Pin Change - 11 I/O pins with individual direction control • Wake-up from Sleep on Comparator Change - 1 input only pin • 2 Analog Comparators with Absolute Reference and Programmable Reference © 2007 Microchip Technology Inc. DS41268D-page 1

PIC12F510/16F506 Program Memory Data Memory Timers Device I/O 8-bit Flash (words) SRAM (bytes) PIC16F506 1024 67 12 1 PIC12F510 1024 38 6 1 Pin Diagrams PDIP, SOIC and TSSOP VDD 1 14 VSS RB5/OSC1/CLKIN 2 13 RB0/AN0/C1IN+/ICSPDAT RB4/OSC2/CLKOUT 3 06 12 RB1/AN1/C1IN-/ICSPCLK 5 RB3/MCLR/VPP 4 6F 11 RB2/AN2/C1OUT RC5/T0CKI 5 C1 10 RC0/C2IN+ RC4/C2OUT 6 PI 9 RC1/C2IN- RC3 7 8 RC2/CVREF PDIP, SOIC, MSOP VDD 1 0 8 VSS GP5/OSC1/CLKIN 2 51 7 GP0/AN0/C1IN+/ICSPDAT F GP4/OSC2 3 2 6 GP1/AN1/C1IN-/ICSPCLK 1 GP3/MCLR/VPP 4 PIC 5 GP2/AN2/T0CKI/C1OUT DFN VDD 1 8 VSS 0 GP5/OSC1/CLKIN 2 51 7 GP0/AN0/C1IN+/ICSPDAT F GP4/OSC2 3 2 6 GP1/AN1/C1IN-/ICSPCLK 1 C GP3/MCLR/VPP 4 PI 5 GP2/AN2/T0CKI/C1OUTI DS41268D-page 2 © 2007 Microchip Technology Inc.

PIC12F510/16F506 Table of Contents 1.0 General Description......................................................................................................................................................................5 2.0 PIC12F510/16F506 Device Varieties ..........................................................................................................................................7 3.0 Architectural Overview.................................................................................................................................................................9 4.0 Memory Organization.................................................................................................................................................................15 5.0 I/O Port.......................................................................................................................................................................................27 6.0 TMR0 Module and TMR0 Register.............................................................................................................................................39 7.0 Comparator(s)............................................................................................................................................................................43 8.0 Comparator Voltage Reference Module (PIC16F506 only)........................................................................................................49 9.0 Analog-to-Digital (A/D) Converter...............................................................................................................................................51 10.0 Special Features Of The CPU....................................................................................................................................................55 11.0 Instruction Set Summary............................................................................................................................................................71 12.0 Development Support.................................................................................................................................................................79 13.0 Electrical Characteristics............................................................................................................................................................83 14.0 DC and AC Characteristics Graphs and Charts.........................................................................................................................97 15.0 Packaging.................................................................................................................................................................................105 Index..................................................................................................................................................................................................117 The Microchip Web Site.....................................................................................................................................................................119 Customer Change Notification Service..............................................................................................................................................119 Customer Support..............................................................................................................................................................................119 Reader Response..............................................................................................................................................................................120 Product Identification System............................................................................................................................................................121 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. DS41268D-page 3

PIC12F510/16F506 NOTES: DS41268D-page 4 © 2007 Microchip Technology Inc.

PIC12F510/16F506 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC12F510/16F506 devices from Microchip The PIC12F510/16F506 devices fit in applications Technology are low-cost, high-performance, 8-bit, fully- ranging from personal care appliances and security static, Flash-based CMOS microcontrollers. They systems to low-power remote transmitters/receivers. employ a RISC architecture with only 33 single-word/ The Flash technology makes customizing application single-cycle instructions. All instructions are single- programs (transmitter codes, appliance settings, cycle except for program branches, which take two receiver frequencies, etc.) extremely fast and conve- cycles. The PIC12F510/16F506 devices deliver nient. The small footprint packages, for through hole or performance in an order of magnitude higher than their surface mounting, make these microcontrollers perfect competitors in the same price category. The 12-bit wide for applications with space limitations. Low-cost, low- instructions are highly symmetrical, resulting in a power, high-performance, ease-of-use and I/O flexibil- typical 2:1 code compression over other 8-bit ity make the PIC12F510/16F506 devices very versa- microcontrollers in its class. The easy-to-use and easy- tile, even in areas where no microcontroller use has to-remember instruction set reduces development time been considered before (e.g., timer functions, logic and significantly. PLDs in larger systems and coprocessor applications). The PIC12F510/16F506 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator con- figurations to choose from (six on the PIC16F506), including INTOSC Internal Oscillator mode and the Power-Saving LP (Low-power) Oscillator mode. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC12F510/16F506 devices allow the customer to take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility. The PIC12F510/16F506 products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost development programmer and a full featured program- mer. All the tools are supported on IBM® PC and compatible machines. TABLE 1-1: PIC12F510/16F506 DEVICES PIC16F506 PIC12F510 Clock Maximum Frequency of Operation (MHz) 20 8 Memory Flash Program Memory (words) 1024 1024 Data Memory (bytes) 67 38 Peripherals Timer Module(s) TMR0 TMR0 Wake-up from Sleep on Pin Change Yes Yes Features I/O Pins 11 5 Input Only Pin 1 1 Internal Pull-ups Yes Yes In-Circuit Serial Programming Yes Yes Number of Instructions 33 33 Packages 14-pin PDIP, SOIC, 8-pin PDIP, SOIC, MSOP, TSSOP DFN The PIC12F510/16F506 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC12F510/16F506 devices use serial programming with data pin RB0/GP0 and clock pin RB1/GP1. © 2007 Microchip Technology Inc. DS41268D.-page 5

PIC12F510/16F506 NOTES: DS41268D.-page 6 © 2007 Microchip Technology Inc.

PIC12F510/16F506 2.0 PIC12F510/16F506 DEVICE 2.2 Serialized Quick Turn VARIETIES ProgrammingSM (SQTPSM) Devices A variety of packaging options are available. Depend- Microchip offers a unique programming service, where ing on application and production requirements, the a few user-defined locations in each device are proper device option can be selected using the programmed with different serial numbers. The serial information in this section. When placing orders, please numbers may be random, pseudo-random or use the PIC12F510/16F506 Product Identification sequential. System at the back of this data sheet to specify the Serial programming allows each device to have a correct part number. unique number, which can serve as an entry code, password or ID number. 2.1 Quick Turn Programming (QTP) Devices Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices, but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. © 2007 Microchip Technology Inc. DS41268D-page 7

PIC12F510/16F506 NOTES: DS41268D-page 8 © 2007 Microchip Technology Inc.

PIC12F510/16F506 3.0 ARCHITECTURAL OVERVIEW The ALU is 8 bits wide and capable of addition, subtrac- tion, shift and logical operations. Unless otherwise The high performance of the PIC12F510/16F506 mentioned, arithmetic operations are two’s comple- devices can be attributed to a number of architectural ment in nature. In two-operand instructions, one features commonly found in RISC microprocessors. operand is typically the W (working) register. The other The PIC12F510/16F506 devices use a Harvard archi- operand is either a file register or an immediate tecture in which program and data are accessed on constant. In single-operand instructions, the operand is separate buses. This improves bandwidth over tradi- either the W register or a file register. tional von Neumann architectures where program and The W register is an 8-bit working register used for ALU data are fetched on the same bus. Separating program operations. It is not an addressable register. and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction Depending on the instruction executed, the ALU may opcodes are 12 bits wide, making it possible to have all affect the values of the Carry (C), Digit Carry (DC) and single-word instructions. A 12-bit wide program mem- Zero (Z) bits in the STATUS register. The C and DC bits ory access bus fetches a 12-bit instruction in a single operate as a borrow and digit borrow out bit, respec- cycle. A two-stage pipeline overlaps fetch and execu- tively, in subtraction. See the SUBWF and ADDWF tion of instructions. Consequently, all instructions (33) instructions for examples. execute in a single cycle (200ns @ 20MHz, 1μs @ A simplified block diagram is shown in Figure3-1 for 4MHz) except for program branches. PIC12F510 with the corresponding device pins Table3-1 lists program memory (Flash) and data described in Table3-2. A simplified block diagram for memory (RAM) for the PIC12F510/16F506 devices. PIC16F506 is shown in Figure3-2 with the corresponding device pins described in Table3-3. TABLE 3-1: PIC12F510/16F506 MEMORY Memory Device Program Data PIC12F510 1024 x 12 38 x 8 PIC16F506 1024 x 12 67 x 8 The PIC12F510/16F506 devices can directly or indi- rectly address its register files and data memory. All Special Function Registers (SFRs), including the PC, are mapped in the data memory. The PIC12F510/ 16F506 devices have a highly orthogonal (symmetri- cal) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC12F510/16F506 devices simple, yet efficient. In addition, the learning curve is reduced significantly. The PIC12F510/16F506 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. © 2007 Microchip Technology Inc. DS41268D-page 9

PIC12F510/16F506 FIGURE 3-1: PIC12F510 SERIES BLOCK DIAGRAM 10-11 Data Bus 8 GPIO Program Counter Flash GP0/ICSPDAT 1K x 12 GP1/ICSPCLK RAM GP2 Program STACK 1 38 bytes GP3 Memory STACK 2 File GP4 Registers GP5 Program 12 Bus RAM Addr 9 Addr MUX Instruction Reg Direct Addr 5 Indirect 5-7 Addr FSR Reg STATUS Reg 8 3 MUX Device Reset Timer Instruction C1IN+ Power-on Decode & Reset ALU Comparator C1IN- Control C1OUT Watchdog 8 Timer Timing OSC1/CLKIN Generation Internal RC W Reg CVREF OSC2 Clock AN0 Timer0 8-bit ADC AN1 AN2 MCLR VDD, VSS T0CKI DS41268D-page 10 © 2007 Microchip Technology Inc.

PIC12F510/16F506 TABLE 3-2: PIN DESCRIPTIONS – PIC12F510 Output Name I/O/P Type Input Type Description Type GP0/AN0/C1IN+/ICSPDAT GP0 TTL CMOS Bidirectional I/O port. Can be software pro- grammed for internal weak pull-up and wake-up from Sleep on pin change. AN0 AN — ADC channel input. C1IN+ AN — Comparator input. ICSPDAT ST CMOS In-Circuit Serial Programming data pin. GP1/AN1/C1IN-/ICSPCLK GP1 TTL CMOS Bidirectional I/O port. Can be software pro- grammed for internal weak pull-up and wake-up from Sleep on pin change. AN1 AN — ADC channel input. C1IN- AN — Comparator input. ICSPCLK ST — In-Circuit Serial Programming clock pin. GP2/AN2/T0CKI/C1OUT GP2 TTL CMOS Bidirectional I/O port. AN2 AN — ADC channel input. T0CKI ST — Timer0 clock input. C1OUT — CMOS Comparator output. GP3/MCLR/VPP GP3 TTL — Standard TTL input. Can be software pro- grammed for internal weak pull-up and wake-up from Sleep on pin change. MCLR ST — MCLR input – weak pull-up always enabled in this mode. VPP HV — Programming Voltage input. GP4/OSC2 GP4 TTL CMOS Bidirectional I/O port. OSC2 — XTAL XTAL oscillator output pin. GP5/OSC1/CLKIN GP5 TTL CMOS Bidirectional I/O port. OSC1 XTAL — XTAL oscillator input pin. CLKIN ST — EXTRC Schmitt Trigger input. VDD VDD P — Positive supply for logic and I/O pins. VSS VSS P — Ground reference for logic and I/O pins. Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input, AN = Analog Voltage, HV = High Voltage © 2007 Microchip Technology Inc. DS41268D-page 11

PIC12F510/16F506 FIGURE 3-2: PIC16F506 SERIES BLOCK DIAGRAM 10 8 Data Bus PORTB Program Counter Flash RB0/ICSPDAT 1K x 12 RB1/ICSPCLK Program RAM RB2 Memory STACK 1 67 bytes RB3 STACK 2 File RB4 Registers RB5 Program 10 Bus RAM Addr 9 PORTC Addr MUX Instruction Reg RC0 Direct Addr 5 Indirect RC1 5-7 Addr RC2 RC3 FSR Reg RC4 RC5 STATUS Reg 8 C1IN+ 3 Co mparator 1 C1IN- Device Reset MUX C1OUT Timer Instruction 0.6V Reference Power-on Decode & Reset ALU C2IN+ Control Comparator 2 C2IN- Watchdog 8 Timer C2OUT OOSSCC21//CCLLKKOINUT GeTnimeriantgion InteCrlnoaclk RC W Reg CVREF CVREF CVREF Timer0 AN0 MCLR VDD, VSS 8-bit ADC AN1 AN2 T0CKI DS41268D-page 12 © 2007 Microchip Technology Inc.

PIC12F510/16F506 TABLE 3-3: PIN DESCRIPTIONS – PIC16F506 Output Name Function Input Type Description Type RB0/AN0/C1IN+/ICSPDAT RB0 TTL CMOS Bidirectional I/O port. Can be software pro- grammed for internal weak pull-up and wake-up from Sleep on pin change. AN0 AN — ADC channel input. C1IN+ AN — Comparator 1 input. ICSPDAT ST CMOS In-Circuit Serial Programming data pin. RB1/AN1/C1IN-/ICSPCLK RB1 TTL CMOS Bidirectional I/O port. Can be software pro- grammed for internal weak pull-up and wake-up from Sleep on pin change. AN1 AN — ADC channel input. C1IN- AN — Comparator 1 input. ICSPCLK ST — In-Circuit Serial Programming clock pin. RB2/AN2/C1OUT RB2 TTL CMOS Bidirectional I/O port. AN2 AN — ADC channel input. C1OUT — CMOS Comparator 1 output. RB3/MCLR/VPP RB3 TTL — Standard TTL input. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR ST — MCLR input – weak pull-up always enabled in this mode. VPP HV — Programming voltage input. RB4/OSC2/CLKOUT RB4 TTL CMOS Bidirectional I/O port. Can be software pro- grammed for internal weak pull-up and wake-up from Sleep on pin change. OSC2 — XTAL XTAL oscillator output pin. CLKOUT — CMOS EXTRC/INTOSC CLKOUT pin (FOSC/4). RB5/OSC1/CLKIN RB5 TTL CMOS Bidirectional I/O port. OSC1 XTAL — XTAL oscillator input pin. CLKIN ST — EXTRC/EC Schmitt Trigger input. RC0/C2IN+ RC0 TTL CMOS Bidirectional I/O port. C2IN+ AN — Comparator 2 input. RC1/C2IN- RC1 TTL CMOS Bidirectional I/O port. C2IN- AN — Comparator 2 input. RC2/CVREF RC2 TTL CMOS Bidirectional I/O port. CVREF — AN Programmable Voltage Reference output. RC3 RC3 TTL CMOS Bidirectional I/O port. RC4/C2OUT RC4 TTL CMOS Bidirectional I/O port. C2OUT — CMOS Comparator 2 output. RC5/T0CKI RC5 TTL CMOS Bidirectional I/O port. T0CKI ST — Timer0 clock input. VDD VDD P — Positive supply for logic and I/O pins. VSS VSS P — Ground reference for logic and I/O pins. Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input, AN = Analog Voltage, HV = High Voltage © 2007 Microchip Technology Inc. DS41268D-page 13

PIC12F510/16F506 3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining Cycle An instruction cycle consists of four Q cycles (Q1, Q2, The clock input (OSC1/CLKIN pin) is internally divided Q3 and Q4). The instruction fetch and execute are by four to generate four non-overlapping quadrature pipelined such that fetch takes one instruction cycle, clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC while decode and execute take another instruction is incremented every Q1 and the instruction is fetched cycle. However, due to the pipelining, each instruction from program memory and latched into the instruction effectively executes in one cycle. If an instruction register in Q4. It is decoded and executed during the causes the PC to change (e.g., GOTO), then two cycles following Q1 through Q4. The clocks and instruction are required to complete the instruction (Example3-1). execution flow is shown in Figure3-3 and Example3-1. A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Q3 Clock Q4 PC PC PC + 1 PC + 2 Fetch INST (PC) Execute INST (PC – 1) Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTB, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS41268D-page 14 © 2007 Microchip Technology Inc.

PIC12F510/16F506 4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE The PIC12F510/16F506 memories are organized into PIC12F510/16F506 program memory and data memory. For devices with more than 512 bytes of program memory, a paging PC<11:0> scheme is used. Program memory pages are accessed CALL, RETLW 10 using STATUS register bit PA0. For the PIC12F510 and PIC16F506, with data memory register files of more Stack Level 1 than 32 registers, a banking scheme is used. Data Stack Level 2 memory banks are accessed using the File Select Register (FSR). Reset Vector(1) 0000h 4.1 Program Memory Organization for the PIC12F510/16F506 On-chip Program Memory The PIC12F510/16F506 devices have a 10-bit y Program Counter (PC) capable of addressing a 2K x 12 or me program memory space. Mepac 512 Word 01FFh Only the first 1K x 12 (0000h-03FFh) are physically er S 0200h s implemented (see Figure4-1). Accessing a location U above these boundaries will cause a wraparound On-chip Program within the 1K x 12 space. The effective Reset vector Memory is a 0000h (see Figure4-1). Location 03FFh contains the internal clock oscillator calibration value. This 1024 Word 03FFh value should never be overwritten. 0400h 7FFh Note 1: Address 0000h becomes the effective Reset vector. Location 03FFh contains the MOVLW XX internal oscillator calibration value. © 2007 Microchip Technology Inc. DS41268D-page 15

PIC12F510/16F506 4.2 Data Memory Organization FIGURE 4-2: PIC12F510 REGISTER FILE MAP Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified FSR<5> 0 1 by its register file. The register file is divided into two File Address functional groups: Special Function Registers (SFRs) 00h INDF(1) 20h and General Purpose Registers (GPRs). 01h TMR0 The Special Function Registers include the TMR0 02h PCL Addresses register, the Program Counter (PCL), the STATUS register, the I/O registers (ports) and the File Select 03h STATUS map back to addresses in Register (FSR). In addition, Special Function Registers 04h FSR Bank 0. are used to control the I/O port configuration and 05h OSCCAL prescaler options. 06h GPIO The General Purpose Registers are used for data and control information under command of the instructions. 07h CM1C ON0 08h ADCON0 For the PIC12F510, the register file is composed of 10 Special Function Registers, 6 General Purpose 09h ADRES Registers and 32 General Purpose Registers accessed 0Ah General by banking (see Figure4-2). Purpose 0Fh Registers 2Fh For the PIC16F506, the register file is composed of 13 Special Function Registers, 3 General Purpose 10h 30h Registers and 64 General Purpose Registers, General General accessed by banking (see Figure4-3). Purpose Purpose Registers Registers 4.2.1 GENERAL PURPOSE REGISTER FILE 1Fh 3Fh The General Purpose Register file is accessed either Bank 0 Bank 1 directly or indirectly through the File Select Register (FSR). See Section4.8 “Indirect Data Addressing: Note 1: Not a physical register. INDF and FSR Registers”. FIGURE 4-3: PIC16F506 REGISTER FILE MAP FSR<6:5> 00 01 10 11 File Address 00h INDF(1) 20h 40h 60h 01h TMR0 02h PCL 03h STATUS 04h FSR 05h OSCCAL Addresses map back to 06h PORTB addresses in Bank 0. 07h PORTC 08h CM1CON0 09h ADCON0 0Ah ADRES 0Bh CM2CON0 0Ch VRCON 0Dh General Purpose 0Fh Registers 2Fh 4Fh 6Fh 10h General 30h General 50h General 70h General Purpose Purpose Purpose Purpose Registers Registers Registers Registers 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: Not a physical register. DS41268D-page 16 © 2007 Microchip Technology Inc.

PIC12F510/16F506 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (see Table4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY – PIC12F510 Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on Reset N/A TRIS I/O Control Registers (TRISGPIO) --11 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx 02h(1) PCL Low Order 8 bits of PC 1111 1111 03h STATUS GPWUF CWUF PA0 TO PD Z DC C 0001 1xxx 04h FSR Indirect Data Memory Address Pointer 110x xxxx 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 06h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 07h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 08h ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON 1111 1100 09h ADRES ADC Conversion Result xxxx xxxx Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused. Note 1: The upper byte of the Program Counter is not directly accessible. See Section4.6 “Program Counter” for an explanation of how to access these bits. © 2007 Microchip Technology Inc. DS41268D-page 17

PIC12F510/16F506 TABLE 4-2: SPECIAL FUNCTION REGISTER SUMMARY – PIC16F506 Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on Reset N/A TRIS I/O Control Registers (TRISB, TRISC) --11 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT Prescaler 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 01h TMR0 Timer0 Module Register xxxx xxxx 02h(1) PCL Low Order 8 bits of PC 1111 1111 03h STATUS RBWUF CWUF PA0 TO PD Z DC C 0001 1xxx 04h FSR Indirect Data Memory Address Pointer 100x xxxx 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — 1111 111- 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx 08h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 09h ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON 1111 1100 0Ah ADRES ADC Conversion Result xxxx xxxx 0Bh CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 0Ch VRCON VREN VROE VRR —(2) VR3 VR2 VR1 VR0 0011 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused. Note 1: The upper byte of the Program Counter is not directly accessible. See Section4.6 “Program Counter” for an explanation of how to access these bits. 2: Unimplemented bit VRCON<4> read as ‘1’. 4.3 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS regis- ter. These instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section11.0 “Instruction Set Summary”. DS41268D-page 18 © 2007 Microchip Technology Inc.

PIC12F510/16F506 REGISTER 4-1: STATUS: STATUS REGISTER (PIC12F510) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x GPWUF CWUF PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWUF: GPIO Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 CWUF: Comparator Reset bit 1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset bit 5 PA0: Program Page Preselect bit 1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred © 2007 Microchip Technology Inc. DS41268D-page 19

PIC12F510/16F506 REGISTER 4-2: STATUS: STATUS REGISTER (PIC16F506) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x RBWUF CWUF PA0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBWUF: PORTB Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 CWUF: Comparator Reset bit 1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset bit 5 PA0: Program Page Preselect bit 1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred DS41268D-page 20 © 2007 Microchip Technology Inc.

PIC12F510/16F506 4.4 OPTION Register The OPTION register is a 8-bit wide, write-only register, that contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits. Note1: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU/RBPU and GPWU/RBWU). 2: If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin. REGISTER 4-3: OPTION_REG: OPTION REGISTER (PIC12F510) W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWU: Enable Wake-up On Pin Change bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 6 GPPU: Enable Weak Pull-Ups bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 © 2007 Microchip Technology Inc. DS41268D-page 21

PIC12F510/16F506 REGISTER 4-4: OPTION_REG: OPTION REGISTER (PIC16F506) W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 6 RBPU: Enable Weak Pull-Ups bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS41268D-page 22 © 2007 Microchip Technology Inc.

PIC12F510/16F506 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4/8MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. After you move in the calibration constant, do not change the value. See Section10.2.5 “Internal 4/8MHz RC Oscillator”. REGISTER 4-5: OSCCAL: OSCILLATOR CALIBRATION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 CAL<6:0>: Oscillator Calibration bits 0111111 = Maximum frequency • • • 0000001 0000000 = Center frequency 1111111 • • • 1000000 = Minimum frequency bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. DS41268D-page 23

PIC12F510/16F506 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program The PC is set upon a Reset, which means that the PC Counter (PC) will contain the address of the next addresses the last location in the last page (i.e., the program instruction to be executed. The PC value is oscillator calibration instruction). After executing increased by one every instruction cycle, unless an MOVLW XX, the PC will roll over to location 00h and instruction changes the PC. begin executing user code. For a GOTO instruction, bits 8:0 of the PC are provided The STATUS register page preselect bits are cleared by the GOTO instruction word. The Program Counter upon a Reset, which means that page0 is preselected. (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS Therefore, upon a Reset, a GOTO instruction will register provides page information to bit 9 of the PC automatically cause the program to jump to page0 until (Figure4-4). the value of the page bits is altered. For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are 4.7 Stack provided by the instruction word. However, PC<8> The PIC12F510/16F506 devices have a two-deep, does not come from the instruction word, but is always 12-bit wide hardware PUSH/POP stack. cleared (Figure4-4). A CALL instruction will PUSH the current value of Instructions where the PCL is the destination or modify Stack 1 into Stack 2 and then PUSH the current PC PCL instructions include MOVWF PC, ADDWF PC and value, incremented by one, into Stack Level 1. If more BSF PC, 5. than two sequential CALLs are executed, only the Note: Because PC<8> is cleared in the CALL most recent two return addresses are stored. instruction or any modify PCL instruction, A RETLW instruction will POP the contents of Stack all subroutine calls or computed jumps are Level 1 into the PC and then copy Stack Level 2 limited to the first 256 locations of any contents into Stack Level 1. If more than two sequential program memory page (512 words long). RETLWs are executed, the stack will be filled with the address previously stored in Stack Level 2. FIGURE 4-4: LOADING OF PC BRANCH INSTRUCTIONS Note1: The W register will be loaded with the lit- eral value specified in the instruction. This GOTO Instruction is particularly useful for the implementa- tion of data look-up tables within the 9 8 7 0 program memory. PC PCL 2: There are no Status bits to indicate stack overflows or stack underflow conditions. Instruction Word 3: There are no instruction mnemonics PA0 called PUSH or POP. These are actions 7 0 that occur from the execution of the CALL and RETLW instructions. STATUS CALL or Modify PCL Instruction 9 8 7 0 PC PCL Instruction Word Reset to ‘0’ PA0 7 0 STATUS DS41268D-page 24 © 2007 Microchip Technology Inc.

PIC12F510/16F506 4.8 Indirect Data Addressing: INDF EXAMPLE 4-1: HOW TO CLEAR RAM and FSR Registers USING INDIRECT ADDRESSING The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is MOVLW 0x10 ;initialize pointer MOVWF FSR ;to RAM contained in the FSR register (FSR is a pointer). This is NEXT CLRF INDF ;clear INDF register indirect addressing. INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? 4.8.1 INDIRECT ADDRESSING EXAMPLE GOTO NEXT ;NO, clear next • Register file 07 contains the value 10h CONTINUE : ;YES, continue • Register file 08 contains the value 0Ah : • Load the value 07 into the FSR register • A read of the INDF register will return the value The FSR is a 5-bit wide register. It is used in conjunc- of10h tion with the INDF register to indirectly address the data • Increment the value of the FSR register by one memory area. (FSR = 08) The FSR<4:0> bits are used to select data memory • A read of the INDR register now will return the addresses 00h to 1Fh. value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce PIC16F506 – Uses FSR<6:5>. Selects from Bank 0 to Bank 3. FSR<7> is unimplemented, read as ‘1’. 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). A simple program to clear RAM locations 10h-1Fh PIC12F510 – Uses FSR<5>. Selects from Bank 0 to using indirect addressing is shown in Example4-1. Bank 1. FSR<7:6> are unimplemented, read as ‘11’. FIGURE 4-5: DIRECT/INDIRECT ADDRESSING (PIC12F510) Direct Addressing Indirect Addressing (FSR) (opcode) (FSR) 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Bank Select Location Select Bank Location Select Select 00 01 00h Addresses map back to addresses in Bank 0. Data 0Fh Memory(1) 10h 1Fh 3Fh Bank 0 Bank 1 Note 1: For register map detail, see Figure4-2. 2: Grey boxes are unimplemented and read as ‘1’. © 2007 Microchip Technology Inc. DS41268D-page 25

PIC12F510/16F506 FIGURE 4-6: DIRECT/INDIRECT ADDRESSING (PIC16F506) Direct Addressing Indirect Addressing (FSR) (opcode) (FSR) 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Bank Select Location Select Bank Location Select 00 01 10 11 00h Addresses map back to addresses in Bank 0. Data 0Fh Memory(1) 10h 1Fh 3Fh 5Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register map detail, see Figure4-3. DS41268D-page 26 © 2007 Microchip Technology Inc.

PIC12F510/16F506 5.0 I/O PORT 5.4 I/O Interfacing As with any other register, the I/O register(s) can be The equivalent circuit for an I/O port pin is shown in written and read under program control. However, read Figure5-1. All port pins, except RB3/GP3 which is instructions (e.g., MOVF PORTB, W) always read the I/O input only, may be used for both input and output oper- pins independent of the pin’s Input/Output modes. On ations. For input operations, these ports are non-latch- Reset, all I/O ports are defined as input (inputs are at ing. Any input must be present until read by an input high-impedance) since the I/O control registers are all instruction (e.g., MOVF PORTB, W). The outputs are set. latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the correspond- Note: On the PIC12F510, I/O PORTB is refer- ing direction control bit in TRIS must be cleared (= 0). enced as GPIO. On the PIC16F506, I/O For use as an input, the corresponding TRIS bit must PORTB is referenced as PORTB. be set. Any I/O pin (except RB3/GP3) can be programmed individually as input or output. 5.1 PORTB/GPIO FIGURE 5-1: PIC12F510/16F506 PORTB/GPIO is an 8-bit I/O register. Only the low- EQUIVALENT CIRCUIT order 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are unimplemented and read as ‘0’s. Please note that RB3/ FOR PIN DRIVE(2) GP3 is an input only pin. The Configuration Word can Data set several I/O’s to alternate functions. When acting as Bus alternate functions, the pins will read as ‘0’ during a port Data read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4 VDD VDD Bus (PIC16F506 only) can be configured with weak pull-up Interface and also for wake-up on change. The wake-up on P (1) change and weak pull-up functions are not pin select- able. If RB3/GP3/MCLR is configured as MCLR, weak pull-up is always on and wake-up on change for this pin N I/O pin is not enabled. D Q VSS VSS 5.2 PORTC (PIC16F506 Only) CK Q PORTC is an 8-bit I/O register. Only the low-order 6 bits are used (RC<5:0>). Bits 7 and 6 are unimplemented and read as ‘0’s. Reset 5.3 TRIS Registers Note 1: GP3/RB3 has protection diode to VSS only. 2: For pin specific information, see Figure5-2 The Output Driver Control register is loaded with the through Figure5-13. contents of the W register by executing the TRIS f instruction. A ‘1’ from a TRIS register bit puts the corre- sponding output driver in a High-Impedance mode. A ‘0’ puts the contents of the output data latch on the selected pins, enabling the output buffer. The exception is RB3/GP3, which are input only, and the T0CKI pin, which may be controlled by the OPTION register. See Register4-3. Note: A read of the port reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high but the external system is holding it low, a read of the port will indicate that the pin is low. Note: The TRIS registers are write-only and are set (output drivers disabled) upon Reset. © 2007 Microchip Technology Inc. DS41268D-page 27

PIC12F510/16F506 FIGURE 5-2: BLOCK DIAGRAM OF FIGURE 5-3: BLOCK DIAGRAM OF GP0/RB0 AND GP1/RB1 GP3/RB3 (With Weak Pull-up And Wake-up On GPPU Change) RBPU GPPU RBPU Data MCLRE Bus D Q Data WR Latch I/O Pin(1) Port CK Q Reset W Reg I/O Pin(1) D Q TRIS Latch TRIS ‘f’ CK Q Data Bus Reset RD Port ADC pin Ebl COMP pin Ebl Q D CK RD Port Mismatch Q D CK Mismatch ADC COMP Note 1: I/O pins have protection diodes to VDD and Note 1: GP3/MCLR pin has a protection diode to VSS VSS. only. DS41268D-page 28 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 5-4: BLOCK DIAGRAM OF GP2 FIGURE 5-5: BLOCK DIAGRAM OF RB2 C1OUT 0 I/O Pin(1) C1OUT 0 I/O Pin(1) Data Data Bus Bus D Q 1 D Q 1 Data Data WR Latch WR Latch Port Port CK Q CK Q C1OUTEN C1OUTEN W W Reg Reg D Q D Q TRIS TRIS Latch Latch TRIS ‘f’ TRIS ‘f’ CK Q CK Q Reset Reset T0CS ADC Pin Enable C1T0CS ADC Pin Enable RD Port T0CKI RD Port ADC ADC Note 1: I/O pins have protection diodes to VDD and Note 1: I/O pins have protection diodes to VDD and VSS. VSS. © 2007 Microchip Technology Inc. DS41268D-page 29

PIC12F510/16F506 FIGURE 5-6: BLOCK DIAGRAM OF RB4 FIGURE 5-7: BLOCK DIAGRAM OF GP4 RBPU Data Bus D Q Data I/O Data WR Latch Bus Port pin(1) D Q 0 CK Q Data WR Latch Port CK Q 1 I/O W pin(1) Reg D Q TRIS FOSC/4 W Latch Reg TRIS ‘f’ CK Q D Q TRIS Latch TRIS ‘f’ CK Q Reset INTOSC/RC Reset INTOSC/RC/EC CLKOUT Enable (Note 2) RD Port Oscillator OSC1 Circuit RD Port Oscillator OSC1 Circuit Note 1: I/O pins have protection diodes to VDD and VSS. Note 1: I/O pins have protection diodes to VDD and VSS. 2: Input mode is disabled when pin is used for oscillator. DS41268D-page 30 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 5-8: BLOCK DIAGRAM OF FIGURE 5-9: BLOCK DIAGRAM OF RB5/GP5 RC0/RC1 Data Bus Data D Q Bus Data D Q I/O WPoRrt Latch pin(1) Data I/O CK Q WR Latch Port pin(1) CK Q W Reg W D Q Reg TRIS D Q Latch TRIS TRIS ‘f’ CK Q Latch TRIS ‘f’ CK Q Reset (Note 2) Reset Comp Pin Enable RD Port Oscillator OSC2 Circuit RD Port COMP2 Note 1: I/O pins have protection diodes to VDD and VSS. 2: Input mode is disabled when pin is used for Note 1: I/O pins have protection diodes to VDD and VSS. oscillator. © 2007 Microchip Technology Inc. DS41268D-page 31

PIC12F510/16F506 FIGURE 5-10: BLOCK DIAGRAM OF RC2 FIGURE 5-11: BLOCK DIAGRAM OF RC3 VROE Data I/O Pin(1) Bus D Q Data CVREF 1 I/O PIN(1) WR Latch Port CK Q Data Bus D Q 0 Data W WR Latch Reg Port D Q CK Q TRIS Latch TRIS ‘f’ CK Q W Reg D Q TRIS Reset Latch TRIS ‘f’ CK Q Reset RD Port RD Port COMP2 Note 1: I/O pins have protection diodes to VDD and Note 1: I/O pins have protection diodes to VDD and VSS. VSS. DS41268D-page 32 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 5-12: BLOCK DIAGRAM OF RC4 FIGURE 5-13: BLOCK DIAGRAM OF RC5 C2OUT 0 I/O Pin(1) Data Data I/O Pin(1) Bus Bus D Q 1 D Q Data Data WR Latch WR Latch Port Port CK Q CK Q C2OUTEN W W Reg Reg D Q D Q TRIS TRIS Latch Latch TRIS ‘f’ TRIS ‘f’ CK Q CK Q T0CS Reset Reset RD Port RD Port T0CKI Note 1: I/O pins have protection diodes to VDD and Note 1: I/O pins have protection diodes to VDD and VSS. VSS. © 2007 Microchip Technology Inc. DS41268D-page 33

PIC12F510/16F506 TABLE 5-1: SUMMARY OF PORT REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets N/A TRISGPIO(1) — — I/O Control Register --11 1111 --11 1111 N/A TRISB(2) — — I/O Control Register --11 1111 --11 1111 N/A TRISC(2) — — I/O Control Register --11 1111 --11 1111 N/A OPTION(1) GPWU GPPU T0CS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A OPTION(2) RBWU RBPU T0CS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS(1) GPWUF CWUF PA0 TO PD Z DC C 0001 1xxx qq0q quuu(3) 03h STATUS(2) RBWUF CWUF PA0 TO PD Z DC C 0001 1xxx qq0q quuu(3) 06h GPIO(1) — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu 06h PORTB(2) — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu uuuu 07h PORTC(2) — — RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu Legend: – = unimplemented read as ‘0’, x = unknown, u = unchanged, q = depends on condition. Note 1: PIC12F510 only. 2: PIC16F506 only. 3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. TABLE 5-2: I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC16F506) Priority RB0 RB1 RB2 RB3 RB4 RB5 1 AN0/C1IN+ AN1/C1IN- AN2 Input/MCLR OSC2/CLKOUT OSC1/CLKIN 2 TRISB TRISB C1OUT — TRISB TRISB 3 — — TRISB — — — TABLE 5-3: I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC16F506) Priority RC0 RC1 RC2 RC3 RC4 RC5 1 C2IN+ C2IN- CVREF TRISC C2OUT T0CKI 2 TRISC TRISC TRISC — TRISC TRISC TABLE 5-4: I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC12F510) Priority GP0 GP1 GP2 GP3 GP4 GP5 1 AN0/C1IN+ AN1/C1IN- AN2 Input/MCLR OSC2 OSC1/CLKIN 2 TRISIO TRISIO C1OUT — TRISIO TRISIO 3 — — T0CKI — — — 4 — — TRISIO — — — DS41268D-page 34 © 2007 Microchip Technology Inc.

PIC12F510/16F506 TABLE 5-5: REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC12F510) GP0 GP0 GP1 GP1 GP2 GP2 GP3 GP4 GP5 CM1CON0 C1ON 0 1 0 1 0 1 — — — C1PREF — 0 — 1 — — — — — C1NREF — — — 0 — — — — — C1T0CS — — — — — 1 — — — C1OUTEN — — — — — 1 — — — CM2CON0 C2ON — — — — — — — — — C2PREF1 — — — — — — — — — C2PREF2 — — — — — — — — — C2NREF — — — — — — — — — C2OUTEN — — — — — — — — — VRCON0 VROE — — — — — — — — — VREN — — — — — — — — — OPTION T0CS — — — — — 0 — — — ADCON0 ANS<1:0> 00, 01 00, 01 00, 01, 10 00, 01, 10 00 00 — — — CONFIG MCLRE — — — — — — — — — INTOSC — — — — — — — — — LP — — — — — — — Disabled Disabled EXTRC — — — — — — — — Disabled XT — — — — — — — Disabled Disabled Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. 2: Shaded cells indicate the bit status does not affect the pins digital functionality. © 2007 Microchip Technology Inc. DS41268D-page 35

PIC12F510/16F506 TABLE 5-6: REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTB)(1), (2) RB0 RB0 RB0 RB1 RB1 RB2 RB2 RB3 RB4 RB5 CM1CON0 C1ON — 0 1 0 1 0 1 — — — C1PREF — — 0 — — — — — — — C1NREF — — — — 0 — — — — — C1T0CS — — — — — — — — — — C1OUTEN — — — — — — 1 — — — CM2CON0 C2ON 1 — — — — — — — — — C2PREF1 0 — — — — — — — — — C2PREF2 1 — — — — — — — — — C2NREF — — — — — — — — — — C2OUTEN — — — — — — — — — — OPTION T0CS — — — — — — — — — — ADCON0 ANS<1:0> 00, 01 00, 01 00, 01 00, 01, 10 00, 01, 10 00 00 — — — CONFIG MCLRE — — — — — — — 0 — — INTOSC — — — — — — — — — — LP — — — — — — — — Disabled Disabled EXTRC — — — — — — — — — Disabled XT — — — — — — — — Disabled Disabled EC — — — — — — — — — Disabled HS — — — — — — — — Disabled Disabled INTOSC CLKOUT — — — — — — — — Disabled Disabled EXTRC CLOCKOUT — — — — — — — — Disabled Disabled Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. 2: Shaded cells indicate the bit status does not affect the pins digital functionality. TABLE 5-7: REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTC)(1), (2) RC0 RC0 RC1 RC1 RC2 RC3 RC4 RC4 RC5 RC5 CM2CON0 C2ON 0 1 0 1 — — 0 1 — — C2PREF1 — 0 — — — — — — — — C2PREF2 — 0 — — — — — — — — C2NREF — — — 0 — — — — — — C2OUTEN — — — — — — — 1 — — VRCON0 VROE — — — — 0 — — — — — OPTION T0CS — — — — — — — — 0 — Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. 2: Shaded cells indicate the bit status does not affect the pins digital functionality. DS41268D-page 36 © 2007 Microchip Technology Inc.

PIC12F510/16F506 5.5 I/O Programming Considerations EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 5.5.1 BIDIRECTIONAL I/O PORTS I/O PORT (e.g., PIC16F506) Some instructions operate internally as read followed ;Initial PORTB Settings by write operations. For example, the BCF and BSF ;PORTB<5:3> Inputs instructions read the entire port into the CPU, execute ;PORTB<2:0> Outputs the bit operation and re-write the result. Caution must ; be used when these instructions are applied to a port ; PORTB latch PORTB pins ; ---------- ---------- where one or more pins are used as input/outputs. For BCF PORTB, 5 ;--01 -ppp --11 pppp example, a BSF operation on bit 5 of PORTB/GPIO will BCF PORTB, 4 ;--10 -ppp --11 pppp cause all eight bits of PORTB/GPIO to be read into the MOVLW 007h; CPU, bit 5 to be set and the PORTB/GPIO value to be TRIS PORTB ;--10 -ppp --11 pppp written to the output latches. If another bit of PORTB/ ; GPIO is used as a bidirectional I/O pin (say bit ‘0’) and Note: The user may have expected the pin values to it is defined as an input at this time, the input signal be ‘--00 pppp’. The 2nd BCF caused RB5 to present on the pin itself would be read into the CPU and be latched as the pin value (High). rewritten to the data latch of this particular pin, overwrit- ing the previous content. As long as the pin stays in the 5.5.2 SUCCESSIVE OPERATIONS ON I/O Input mode, no problem occurs. However, if bit ‘0’ is PORTS switched into Output mode later on, the content of the data latch may now be unknown. The actual write to an I/O port happens at the end of an Example5-1 shows the effect of two sequential instruction cycle. Whereas for reading, the data must Read-Modify-Write instructions (e.g., BCF, BSF, etc.) be valid at the beginning of the instruction cycle on an I/O port. (Figure5-14). Therefore, care must be exercised if a write followed by a read operation is carried out on the A pin actively outputting a high or a low should not be same I/O port. The sequence of instructions should driven from external devices at the same time in order allow the pin voltage to stabilize (load dependent) to change the level on this pin (“wired OR”, “wired before the next instruction causes the file to be read AND”). The resulting high output currents may damage into the CPU. Otherwise, the previous state of that pin the chip. may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-14: SUCCESSIVE I/O OPERATION (PIC16F506) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB followed by a Instruction read from PORTB. Fetched MOVWF PORTB MOVF PORTB, W NOP NOP Data setup time = (0.25 TCY – TPD) where:TCY = instruction cycle RB<5:0> TPD = propagation delay Therefore, at higher clock frequencies, a Port pin Port pin written here sampled here write followed by a read may be problematic. Instruction Executed MOVWF PORTB MOVF PORTB,W NOP (Write to PORTB) (Read PORTB) © 2007 Microchip Technology Inc. DS41268D-page 37

PIC12F510/16F506 NOTES: DS41268D-page 38 © 2007 Microchip Technology Inc.

PIC12F510/16F506 6.0 TMR0 MODULE AND TMR0 The second Counter mode uses the output of the com- REGISTER parator to increment Timer0. It can be entered in two different ways. The first way is selected by setting the The Timer0 module has the following features: T0CS bit (OPTION<5>), and clearing the C1T0CS bit (CM1CON0<4>) (C1OUTEN [CM1CON0<6>] does not • 8-bit timer/counter register, TMR0 affect this mode of operation). This enables an internal • Readable and writable connection between the comparator and the Timer0. • 8-bit software programmable prescaler The second way is selected by setting the T0CS bit • Internal or external clock select: (OPTION<5>), setting the C1T0CS bit (CM1CON0) - Edge select for external clock and clearing the C1OUTEN bit (CM1CON0<6>). This - External clock from either the T0CKI pin or allows the output of the comparator onto the T0CKI pin, from the output of the comparator while keeping the T0CKI input active. Therefore, any comparator change on the COUT pin is fed back into Figure6-1 is a simplified block diagram of the Timer0 the T0CKI input. The T0SE bit (OPTION<4>) deter- module. mines the source edge. Clearing the T0SE bit selects Timer mode is selected by clearing the T0CS bit the rising edge. Restrictions on the external clock input (OPTION<5>). In Timer mode, the Timer0 module will as discussed in Section6.1 “Using Timer0 With An increment every instruction cycle (without prescaler). If External Clock”. TMR0 register is written, the increment is inhibited for The prescaler may be used by either the Timer0 the following two cycles (Figure6-2 and Figure6-3). module or the Watchdog Timer, but not both. The The user can work around this by writing an adjusted prescaler assignment is controlled in software by the value to the TMR0 register. control bit PSA (OPTION<3>). Clearing the PSA bit will There are two types of Counter mode. The first Counter assign the prescaler to Timer0. The prescaler is not mode uses the T0CKI pin to increment Timer0. It is readable or writable. When the prescaler is assigned to selected by setting the T0CKI bit (OPTION<5>), setting the Timer0 module, prescale values of 1:2, 1:4,..., the C1T0CS bit (CM1CON0<4>) and setting the 1:256 are selectable. Section6.2 “Prescaler” details C1OUTEN bit (CM1CON0<6>). In this mode, Timer0 the operation of the prescaler. will increment either on every rising or falling edge of A summary of registers associated with the Timer0 pin T0CKI. The T0SE bit (OPTION<4>) determines the module is found in Table6-1. source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section6.1 “Using Timer0 With An External Clock”. FIGURE 6-1: TIMER0 BLOCK DIAGRAM T0CKI Pin Data Bus FOSC/4 0 PSOUT 8 Internal 1 1 Sync with Comparator 0 1 Internal TMR0 Reg Output Clocks PrPorgersacmalmera(2b)le 0 PSOUT T0SE(1) (2 TCY delay) Sync 3 C1T0CS(3) PS2, PS1, PS0(1) PSA(1) T0CS(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure6-5). 3: Bit C1T0CS is located in the CM1CON0 register, CM1CON0<4>. © 2007 Microchip Technology Inc. DS41268D-page 39

PIC12F510/16F506 FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 (Program Counter) PC - 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 (Program Counter) PC - 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 NT0 NT0 + 1 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets 01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu 07h CM1CON0(2) C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 uuuu uuuu 08h CM1CON0(3) C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 uuuu uuuu N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRISGPIO(1) — — I/O Control Register ---- 1111 --11 1111 Legend: Shaded cells not used by Timer0, – = unimplemented, x = unknown, u = unchanged. Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1. 2: For PIC12F510. 3: For PIC16F506. DS41268D-page 40 © 2007 Microchip Technology Inc.

PIC12F510/16F506 6.1 Using Timer0 With An External When a prescaler is used, the external clock input is Clock divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. When an external clock input is used for Timer0, it must For the external clock to meet the sampling require- meet certain requirements. The external clock require- ment, the ripple counter must be taken into account. ment is due to internal phase clock (TOSC) synchroniza- Therefore, it is necessary for T0CKI or the comparator tion. Also, there is a delay in the actual incrementing of output to have a period of at least 4TOSC (and a small Timer0 after synchronization. RC delay of 4Tt0H) divided by the prescaler value. The only requirement on T0CKI or the comparator output 6.1.1 EXTERNAL CLOCK high and low time is that they do not violate the SYNCHRONIZATION minimum pulse width requirement of Tt0H. Refer to When no prescaler is used, the external clock input is parameters 40, 41 and 42 in the electrical specification the same as the prescaler output. The synchronization of the desired device. of an external clock with the internal phase clocks is 6.1.2 TIMER0 INCREMENT DELAY accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks Since the prescaler output is synchronized with the (Figure6-4). Therefore, it is necessary for T0CKI or the internal clocks, there is a small delay from the time the comparator output to be high for at least 2TOSC (and a external clock edge occurs to the time the Timer0 small RC delay of 2Tt0H) and low for at least 2TOSC module is actually incremented. Figure6-4 shows the (and a small RC delay of 2Tt0H). Refer to the electrical delay from the external clock edge to the timer specification of the desired device. incrementing. FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output(2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4TOSC max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 6.2 Prescaler When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, An 8-bit counter is available as a prescaler for the MOVWF 1, BSF 1, x, etc.) will clear the prescaler. Timer0 module or as a postscaler for the Watchdog When assigned to WDT, a CLRWDT instruction will clear Timer (WDT), respectively (see Figure10-12). For sim- the prescaler along with the WDT. The prescaler is plicity, this counter is being referred to as “prescaler” neither readable nor writable. On a Reset, the throughout this data sheet. prescaler contains all ‘0’s. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice-versa. The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. © 2007 Microchip Technology Inc. DS41268D-page 41

PIC12F510/16F506 6.2.1 SWITCHING PRESCALER To change prescaler from the WDT to the Timer0 ASSIGNMENT module, use the sequence shown in Example6-2. This sequence must be used even if the WDT is disabled. A The prescaler assignment is fully under software CLRWDT instruction should be executed before control (i.e., it can be changed “on-the-fly” during pro- switching the prescaler. gram execution). To avoid an unintended device Reset, the following instruction sequence (Example6-1) must EXAMPLE 6-2: CHANGING PRESCALER be executed when changing the prescaler assignment (WDT→TIMER0) from Timer0 to the WDT. CLRWDT ;Clear WDT and EXAMPLE 6-1: CHANGING PRESCALER ;prescaler (TIMER0 → WDT) MOVLW ‘xxxx0xxx’ ;Select TMR0, new ;prescale value and CLRWDT ;Clear WDT ;clock source CLRF TMR0 ;Clear TMR0 & Prescaler OPTION MOVLW ‘00xx1111’b ;These 3 lines (5, 6, 7) OPTION ;are required only if ;desired CLRWDT ;PS<2:0> are 000 or 001 MOVLW ‘00xx1xxx’b ;Set Postscaler to OPTION ;desired WDT rate FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER T0CKI(2) Pin TCY (= FOSC/4) Data Bus 0 8 M 1 1 U Comparator 1 X M Sync Output U 2 TMR0 Reg 0 0 X Cycles T0SE(1) T0CS(1) PSA(1) C1T0CS(3) 0 8-bit Prescaler M U 1 X Watchdog 8 Timer 8-to-1 MUX PS<2:0>(1) PSA(1) 0 1 WDT Enable bit MUX PSA(1) WDT Time-Out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2: T0CKI is shared with pin GP2 on the PIC12F510 and shared with RC5 on the PIC16F506. 3: Bit C1T0CS is located in the CM1CON0 register. DS41268D-page 42 © 2007 Microchip Technology Inc.

PIC12F510/16F506 7.0 COMPARATOR(S) The PIC12F510 contains one analog comparator module. The PIC16F506 contains two comparators and a comparator voltage reference. REGISTER 7-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER (PIC12F510) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1OUT: Comparator Output bit 1 = VIN+ > VIN- 0 = VIN+ < VIN- bit 6 C1OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C1OUT pin 0 = Output of comparator is placed in the C1OUT pin bit 5 C1POL: Comparator Output Polarity bit(2) 1 = Output of comparator is not inverted 0 = Output of comparator is inverted bit 4 C1T0CS: Comparator TMR0 Clock Source bit(2) 1 = TMR0 clock source selected by T0CS control bit 0 = Comparator output used as TMR0 clock source bit 3 C1ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off bit 2 C1NREF: Comparator Negative Reference Select bit(2) 1 = C1IN- pin 0 = 0.6V internal reference bit 1 C1PREF: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C1IN- pin bit 0 C1WU: Comparator Wake-up On Change Enable bit(2) 1 = Wake-up On Comparator Change is disabled 0 = Wake-up On Comparator Change is enabled Note 1: Overrides T0CS bit for TRIS control of RB2. 2: When comparator is turned on, these control bits assert themselves. © 2007 Microchip Technology Inc. DS41268D-page 43

PIC12F510/16F506 REGISTER 7-2: CM1CON0: COMPARATOR C1 CONTROL REGISTER (PIC16F506) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1OUT: Comparator Output bit 1 = VIN+ > VIN- 0 = VIN+ < VIN- bit 6 C1OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C1OUT pin 0 = Output of comparator is placed in the C1OUT pin bit 5 C1POL: Comparator Output Polarity bit(2) 1 = Output of comparator is not inverted 0 = Output of comparator is inverted bit 4 C1T0CS: Comparator TMR0 Clock Source bit(2) 1 = TMR0 clock source selected by T0CS control bit 0 = Comparator output used as TMR0 clock source bit 3 C1ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off bit 2 C1NREF: Comparator Negative Reference Select bit(2) 1 = C1IN- pin 0 = 0.6V internal reference bit 1 C1PREF: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C1IN- pin bit 0 C1WU: Comparator Wake-up On Change Enable bit(2) 1 = Wake-up On Comparator Change is disabled 0 = Wake-up On Comparator Change is enabled Note 1: Overrides T0CS bit for TRIS control of RB2. 2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have precedence. DS41268D-page 44 © 2007 Microchip Technology Inc.

PIC12F510/16F506 REGISTER 7-3: CM2CON0: COMPARATOR C2 CONTROL REGISTER (PIC16F506) R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C2OUT: Comparator Output bit 1 = VIN+ > VIN- 0 = VIN+ < VIN- bit 6 C2OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C2OUT pin 0 = Output of comparator is placed in the C2OUT pin bit 5 C2POL: Comparator Output Polarity bit(2) 1 = Output of comparator not inverted 0 = Output of comparator inverted bit 4 C2PREF2: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C2IN- pin bit 3 C2ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off bit 2 C2NREF: Comparator Negative Reference Select bit(2) 1 = C2IN- pin 0 = CVREF bit 1 C2PREF1: Comparator Positive Reference Select bit(2) 1 = C2IN+ pin 0 = C2PREF2 controls analog input selection bit 0 C2WU: Comparator Wake-up on Change Enable bit(2) 1 = Wake-up on Comparator change is disabled 0 = Wake-up on Comparator change is enabled. Note 1: Overrides TOCS bit for TRIS control of RC4. 2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have precedence. © 2007 Microchip Technology Inc. DS41268D-page 45

PIC12F510/16F506 FIGURE 7-1: COMPARATOR 1 BLOCK DIAGRAM FOR PIC12F510/16F506 C1PREF To Data Bus C1IN- 0 X U RD_CM1CON0 M C1IN+ 1 C1WUF D Q Q3 * RD_CM1CON0 EN C1WU CL NRESET C1NREF C1ON(1) C1OUTEN C1IN- 1 + X C1 C1OUT U - M 0.6V 0 C1OUT (Internal Reference) C1POL Note 1: When C1ON = 0, the comparator, C1, will produce a ‘0’ output to the XOR Gate. FIGURE 7-2: COMPARATOR 2 BLOCK DIAGRAM (PIC16F506 ONLY) To Data Bus RD_CM2CON0 C2WUF D Q C2PREF1 C2PREF2 C2ON(1) Q3 * RD_CM2CON0 EN C2WU CL C2IN+ 1 NRESET X C1IN+ 1 U + X M C2 C2OUT U 0 M - C2OUTEN C2IN- 0 C2POL C2NREF C2OUT C2IN- 1 X U M CVREF 0 Note 1: When C2ON = 0, the comparator, C2, will produce a ‘0’ output to the XOR Gate. DS41268D-page 46 © 2007 Microchip Technology Inc.

PIC12F510/16F506 7.1 Comparator Operation A single comparator is shown in Figure7-3 along with Note: Analog levels on any pin that is defined as the relationship between the analog input levels and a digital input may cause the input buffer to the digital output. When the analog input at VIN+ is less consume more current than is specified. than the analog input VIN-, the output of the comparator is a digital low level. The shaded area of the output of 7.5 Comparator Wake-up Flag the comparator in Figure7-3 represent the uncertainty due to input offsets and response time. See Table13-1 The Comparator Wake-up Flag is set whenever all of the following conditions are met: for Common Mode Voltage. • C1WU = 0 (CM1CON0<0>) or FIGURE 7-3: SINGLE COMPARATOR C2WU = 0 (CM2CON0<0>) • CM1CON0 or CM2CON0 has been read to latch the last known state of the C1OUT and C2OUT bit (MOVF CM1CON0, W) VIN+ + Result • Device is in Sleep VIN- – • The output of a comparator has changed state The wake-up flag may be cleared in software or by another device Reset. 7.6 Comparator Operation During VIN- Sleep VIN+ When the comparator is enabled it is active. To mini- mize power consumption while in Sleep mode, turn off the comparator before entering Sleep. Result 7.7 Effects of Reset A Power-on Reset (POR) forces the CM2CON0 register to its Reset state. This forces the Comparator 7.2 Comparator Reference input pins to analog Reset mode. Device current is minimized when analog inputs are present at Reset An internal reference signal may be used depending on time. the comparator operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+, and 7.8 Analog Input Connection the digital output of the comparator is adjusted accord- Considerations ingly (Figure7-3). Please see Section8.0 “Compara- tor Voltage Reference Module (PIC16F506 only)” for A simplified circuit for an analog input is shown in internal reference specifications. Figure7-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD 7.3 Comparator Response Time and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this Response time is the minimum time after selecting a range by more than 0.6V in either direction, one of the new reference voltage or input source before the com- diodes is forward biased and a latch-up may occur. A parator output is to have a valid level. If the comparator maximum source impedance of 10kΩ is recom- inputs are changed, a delay must be used to allow the mended for the analog sources. Any external compo- comparator to settle to its new state. Please see nent connected to an analog input pin, such as a Table13-1 for comparator response time capacitor or a Zener diode, should have very little specifications. leakage current. 7.4 Comparator Output The comparator output is read through the CM1CON0 or CM2CON0 register. This bit is read-only. The comparator output may also be used externally, see Figure7-3. © 2007 Microchip Technology Inc. DS41268D-page 47

PIC12F510/16F506 FIGURE 7-4: ANALOG INPUT MODE VDD RS < 10K VT = 0.6V RIC AIN VA C5PpIFN VT = 0.6V I±L5E0A0KAnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the Pin RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 7-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR Resets 03h STATUS GPWUF CWUF PA0 TO PD Z DC C 0001 1xxx qq0q quuu 07h CM1CON0(1) C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 uuuu uuuu 08h CM1CON0(2) C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 uuuu uuuu 0Bh CM2CON0(2) C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 uuuu uuuu N/A TRISB(2) — — I/O Control Register --11 1111 --11 1111 N/A TRISC(2) — — I/O Control Register --11 1111 --11 1111 N/A TRISGPIO(1) — — I/O Control Register --11 1111 --11 1111 Legend: x = Unknown, u = Unchanged, – = Unimplemented, read as ‘0’, q = Depends on condition. Note 1: PIC12F510 only. 2: PIC16F506 only. DS41268D-page 48 © 2007 Microchip Technology Inc.

PIC12F510/16F506 8.0 COMPARATOR VOLTAGE 8.2 Voltage Reference Accuracy/Error REFERENCE MODULE The full range of VSS to VDD cannot be realized due to (PIC16F506 ONLY) construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure8-1) The comparator voltage reference module also allows keep CVREF from approaching VSS or VDD. The excep- the selection of an internally generated voltage refer- tion is when the module is disabled by clearing the ence for one of the C2 comparator inputs. The VRCON VREN bit (VRCON<7>). When disabled, the reference register (Register8-1) controls the voltage reference voltage is VSS when VR<3:0> is ‘0000’ and the VRR module shown in Figure8-1. (VRCON<5>) bit is set. This allows the comparator to detect a zero-crossing and not consume the CVREF 8.1 Configuring The Voltage module current. Reference The voltage reference is VDD derived and, therefore, The voltage reference can output 32 voltage levels; 16 the CVREF output changes with fluctuations in VDD. The in a high range and 16 in a low range. tested absolute accuracy of the comparator voltage reference can be found in Section13.2 “DC Charac- Equation8-1 determines the output voltages: teristics: PIC12F510/16F506 (Extended)”. EQUATION 8-1: VRR = 1 (low range): CVREF = (VR<3:0>/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR<3:0> x VDD/32) REGISTER 8-1: VRCON: VOLTAGE REFERENCE CONTROL REGISTER (PIC16F506 ONLY) R/W-0 R/W-0 R/W-1 U-1 R/W-1 R/W-1 R/W-1 R/W-1 VREN VROE VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’, except if denoted otherwise -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: CVREF Enable bit 1 = CVREF is powered on 0 = CVREF is powered down, no current is drawn bit 6 VROE: CVREF Output Enable bit(1) 1 = CVREF output is enabled 0 = CVREF output is disabled bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘1’ bit 3-0 VR<3:0> CVREF Value Selection bit When VRR = 1: CVREF= (VR<3:0>/24)*VDD When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD Note 1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the CVREF pin. 2: CVREF controls for ratio metric reference applies to Comparator 2 on the PIC16F506 only. © 2007 Microchip Technology Inc. DS41268D-page 49

PIC12F510/16F506 FIGURE 8-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD 8R VRR 16-1 Analog MUX VREN CVREF to Comparator 2 Input VR<3:0> RC2/CVREF VREN VROE VR<3:0> = 0000 VRR TABLE 8-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Value on Value on all Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR other Resets 0Ch VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 001- 1111 001- 1111 08h CM1CON0(1) C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 uuuu uuuu 0Bh CM2CON0(1) C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Note 1: PIC16F506 only. DS41268D-page 50 © 2007 Microchip Technology Inc.

PIC12F510/16F506 9.0 ANALOG-TO-DIGITAL (A/D) When the CHS<1:0> bits are changed during an ADC CONVERTER conversion, the new channel will not be selected until the current conversion is completed. This allows the The A/D Converter allows conversion of an analog current conversion to complete with valid results. All signal into an 8-bit digital signal. channel selection information will be lost when the device enters Sleep. 9.1 Clock Divisors TABLE 9-1: CHANNEL SELECT (ADCS) The ADC has 4 clock source settings ADCS<1:0>. BITS AFTER AN EVENT There are 3 divisor values 16, 8 and 4. The fourth set- ting is INTOSC with a divisor of 4. These settings will Event ADCS<1:0> allow a proper conversion when using an external MCLR 11 oscillator at speeds from 20MHz to 350kHz. Using an external oscillator at a frequency below 350kHz Conversion completed CS<1:0> (TAD > 50 μs) requires the ADC oscillator setting to be Conversion terminated CS<1:0> INTOSC/4 for valid ADC results. Power-on 11 The ADC requires 13 TAD periods to complete a Wake from Sleep 11 conversion. The divisor values do not affect the number of TAD periods required to perform a conversion. The 9.1.4 THE GO/DONE BIT divisor values determine the length of the TAD period. The GO/DONE bit is used to determine the status of a When the ADCS<1:0> bits are changed while an ADC conversion, to start a conversion and to manually halt a conversion is in process, the new ADC clock source will conversion in process. Setting the GO/DONE bit starts not be selected until the next conversion is started. This a conversion. When the conversion is complete, the clock source selection will be lost when the device ADC module clears the GO/DONE bit. A conversion enters Sleep. can be terminated by manually clearing the GO/DONE bit while a conversion is in process. Manual termination 9.1.1 VOLTAGE REFERENCE of a conversion may result in a partially converted There is no external voltage reference for the ADC. The result in ADRES. ADC reference voltage will always be VDD. The GO/DONE bit is cleared when the device enters 9.1.2 ANALOG MODE SELECTION Sleep, stopping the current conversion. The ADC does not have a dedicated oscillator, it runs off of the instruc- The ANS<1:0> bits are used to configure pins for tion clock. Therefore, no conversion can occur in sleep. analog input. Upon any Reset, ANS<1:0> defaults to The GO/DONE bit cannot be set when ADON is clear. 11. This configures pins AN0, AN1 and AN2 as analog inputs. Pins configured as analog inputs are not avail- able for digital output. Users should not change the ANS bits while a conversion is in process. ANS bits are active regardless of the condition of ADON. 9.1.3 ADC CHANNEL SELECTION The CHS bits are used to select the analog channel to be sampled by the ADC. The CHS<1:0> bits can be changed at any time without adversely effecting a con- version. To acquire an analog signal the CHS<1:0> selection must match one of the pin(s) selected by the ANS<1:0> bits. When the ADC is on (ADON = 1) and a channel is selected that is also being used by the comparator, then both the comparator and the ADC will see the analog voltage on the pin. Note: It is the users responsibility to ensure that use of the ADC and comparator simulta- neously on the same pin, does not adversely affect the signal being monitored or adversely effect device operation. © 2007 Microchip Technology Inc. DS41268D-page 51

PIC12F510/16F506 9.1.5 SLEEP This ADC does not have a dedicated ADC clock, and therefore, no conversion in Sleep is possible. If a conversion is underway and a Sleep command is executed, the GO/DONE and ADON bit will be cleared. This will stop any conversion in process and power- down the ADC module to conserve power. Due to the nature of the conversion process, the ADRES may con- tain a partial conversion. At least 1 bit must have been converted prior to Sleep to have partial conversion data in ADRES. The ADCS and CHS bits are reset to their default condition; ANS<1:0> = 11 and CHS<1:0> = 11. • For accurate conversions, TAD must meet the following: • 500ns < TAD < 50μs • TAD = 1/(FOSC/divisor) Shaded areas indicate TAD out of range for accurate conversions. If analog input is desired at these frequencies, use INTOSC/4 for the ADC clock source. TABLE 9-2: TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS ADCS 20(1) 16(1) 500 350 200 100 Source Divisor 8MHz 4MHz 1MHz 32 kHz <1:0> MHz MHz kHz kHz kHz kHz INTOSC 11 4 — — .5μs 1μs — — — — — — FOSC 10 4 .2μs .25μs .5μs 1μs 4μs 8μs 11μs 20μs 40μs 125μs FOSC 01 8 .4μs .5μs 1μs 2μs 8μs 16μs 23μs 40μs 80μs 250μs FOSC 00 16 .8μs 1μs 2μs 4μs 16μs 32μs 46μs 80μs 160μs 500μs Note 1: When operating with external oscillator frequencies of 16 MHz or higher, better ADC performance will result from selection of a suitable FOSC divisor value from Table9-2 than from use of the INTOSC/4 option for the ADC clock. TABLE 9-3: EFFECTS OF SLEEP ON ADCON0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON Entering Unchanged Unchanged 1 1 1 1 0 0 Sleep Wake or 1 1 1 1 1 1 0 0 Reset DS41268D-page 52 © 2007 Microchip Technology Inc.

PIC12F510/16F506 9.1.6 ANALOG CONVERSION RESULT shifts of the ‘leading one’ have taken place, the conver- REGISTER sion is complete; the ‘leading one’ has been shifted out and the GO/DONE bit is cleared. The ADRES register contains the results of the last conversion. These results are present during the sam- If the GO/DONE bit is cleared in software during a con- pling period of the next analog conversion process. version, the conversion stops. The data in ADRES is After the sampling period is over, ADRES is cleared the partial conversion result. This data is valid for the bit (=0). A ‘leading one’ is then right shifted into the weights that have been converted. The position of the ADRES to serve as an internal conversion complete ‘leading one’ determines the number of bits that have bit. As each bit weight, starting with the MSB, is con- been converted. The bits that were not converted verted, the leading one is shifted right and the con- before the GO/DONE was cleared are unrecoverable. verted bit is stuffed into ADRES. After a total of 9 right REGISTER 9-1: ADCON0: A/D CONTROL REGISTER (PIC12F510) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 ANS1 ANS0 ADCS1 ADCS0 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ANS<1:0>: ADC Analog Input Pin Select bits(1), (2) 00 = No pins configured for analog input 01 = AN2 configured as an analog input 10 = AN2 and AN0 configured as analog inputs 11 = AN2, AN1 and AN0 configured as analog inputs bit 5-4 ADCS<1:0>: ADC Conversion Clock Select bits 00 = FOSC/16 01 = FOSC/8 10 = FOSC/4 11 = INTOSC/4 bit 3-2 CHS<1:0>: ADC Channel Select bits 00 = Channel AN0 01 = Channel AN1 10 = Channel AN2 11 = 0.6V absolute voltage reference bit 1 GO/DONE: ADC Conversion Status bit(4) 1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC is done converting. 0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process terminates the current conversion. bit 0 ADON: ADC Enable bit 1 = ADC module is operating 0 = ADC module is shut-off and consumes no power Note 1: When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regard- less of the pin function previously defined. The only exception to this is the comparator, where the analog input to the comparator and the ADC will be active at the same time. It is the users responsibility to ensure that the ADC loading on the comparator input does not affect their application. 2: The ANS<1:0> bits are active regardless of the condition of ADON. 3: CHS<1:0> bits default to 11 after any Reset. 4: If the ADON bit is clear, the GO/DONE bit cannot be set. © 2007 Microchip Technology Inc. DS41268D-page 53

PIC12F510/16F506 REGISTER 9-2: ADRES REGISTER R-X R-X R-X R-X R-X R-X R-X R-X ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown EXAMPLE 9-1: PERFORMING AN EXAMPLE 9-2: CHANNEL SELECTION ANALOG-TO-DIGITAL CHANGE DURING CONVERSION CONVERSION ;Sample code operates out of BANK0 MOVLW 0xF1 ;configure A/D MOVWF ADCON0 MOVLW 0xF1 ;configure A/D BSF ADCON0, 1 ;start conversion MOVWF ADCON0 BSF ADCON0, 2 ;setup for read of BSF ADCON0, 1 ;start conversion ;channel 1 loop0 BTFSC ADCON0, 1;wait for ‘DONE’ loop0 BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop0 GOTO loop0 MOVF ADRES, W ;read result MOVF ADRES, W ;read result MOVWF result0 ;save result MOVWF result0 ;save result BSF ADCON0, 2 ;setup for read of BSF ADCON0, 1 ;start conversion ;channel 1 BSF ADCON0, 3 ;setup for read of BSF ADCON0, 1 ;start conversion BCF ADCON0, 2 ;channel 2 loop1 BTFSC ADCON0, 1;wait for ‘DONE’ loop1 BTFSC ADCON0, 1;wait for ‘DONE’ GOTO loop1 GOTO loop1 MOVF ADRES, W ;read result MOVF ADRES, W ;read result MOVWF result1 ;save result MOVWF result1 ;save result BSF ADCON0, 3 ;setup for read of BSF ADCON0, 1 ;start conversion BCF ADCON0, 2 ;channel 2 loop2 BTFSC ADCON0, 1;wait for ‘DONE’ BSF ADCON0, 1 ;start conversion GOTO loop2 loop2 BTFSC ADCON0, 1;wait for ‘DONE’ MOVF ADRES, W ;read result GOTO loop2 MOVWF result2 ;save result MOVF ADRES, W ;read result CLRF ADCON0 ;optional: returns MOVWF result2 ;save result ;pins to Digital mode and turns off ;the ADC module DS41268D-page 54 © 2007 Microchip Technology Inc.

PIC12F510/16F506 10.0 SPECIAL FEATURES OF THE 10.1 Configuration Bits CPU The PIC12F510/16F506 Configuration Words consist of 12 bits. Configuration bits can be programmed to What sets a microcontroller apart from other proces- select various device configurations. Three bits are for sors are special circuits that deal with the needs of real- the selection of the oscillator type; (two bits on the time applications. The PIC12F510/16F506 PIC12F510), one bit is the Watchdog Timer enable bit, microcontrollers have a host of such features intended one bit is the MCLR enable bit and one bit is for code to maximize system reliability, minimize cost through protection (Register10-1, Register10-2). elimination of external components, provide power- saving operating modes and offer code protection. These features are: • Oscillator Selection • Reset: - Power-on Reset (POR) - Device Reset Timer (DRT) - Wake-up from Sleep on Pin Change • Watchdog Timer (WDT) • Sleep • Code Protection • ID Locations • In-Circuit Serial Programming™ (ICSP™) • Clock Out The PIC12F510/16F506 devices have a Watchdog Timer, which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS (PIC16F506), XT or LP selectable oscillator options, there is always a delay, provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable. If using INTOSC, EXTRC or EC there is an 1.125ms (nominal) delay only on VDD power-up. With this timer on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through a change-on-input pin or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4/8MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options. © 2007 Microchip Technology Inc. DS41268D-page 55

PIC12F510/16F506 REGISTER 10-1: CONFIG: CONFIGURATION WORD REGISTER (PIC12F510)(1) — — — — — — — — bit 15 bit 8 — — IOSCFS MCLRE CP WDTE FOSC1 FOSC0 bit 7 bit 0 bit 15-6 Unimplemented: Read as ‘1’ bit 5 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8MHz INTOSC speed 0 = 4MHz INTOSC speed bit 4 MCLRE: Master Clear Enable bit 1 = GP3/MCLR pin functions as MCLR 0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD bit 3 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC<1:0>: Oscillator Selection bits 00 = LP oscillator with 18 ms DRT 01 = XT oscillator with 18 ms DRT 10 = INTOSC with 1.125 ms DRT (2) 11 = EXTRC with 1.125 ms DRT (2) Note 1: Refer to the “PIC12F510 Memory Programming Specification” (DS41257) to determine how to access the Configuration Word. 2: It is the responsibility of the application designer to ensure the use of the 1.125ms (nominal) DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability require- ments for this mode of operation. DS41268D-page 56 © 2007 Microchip Technology Inc.

PIC12F510/16F506 REGISTER 10-2: CONFIG: CONFIGURATION WORD REGISTER (PIC16F506)(1) — — — — — — — — bit 15 bit 8 — IOSCFS MCLRE CP WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 11-7 Unimplemented: Read as ‘1’ bit 6 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8MHz INTOSC speed 0 = 4MHz INTOSC speed bit 5 MCLRE: Master Clear Enable bit 1 = RB3/MCLR pin functions as MCLR 0 = RB3/MCLR pin functions as RB3, MCLR tied internally to VDD bit 4 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 000 = LP oscillator and 18 ms DRT 001 = XT oscillator and 18 ms DRT 010 = HS oscillator and 18 ms DRT 011 = EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1.125ms DRT(2) 100 = INTOSC with RB4 function on RB4/OSC2/CLKOUT and 1.125ms DRT(2) 101 = INTOSC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125ms DRT(2) 110 = EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1.125ms DRT (2) 111 = EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125ms DRT(2) Note 1: Refer to the “PIC16F506 Memory Programming Specification” (DS41258) to determine how to access the Configuration Word. 2: It is the responsibility of the application designer to ensure the use of the 1.125ms (nominal) DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability require- ments for this mode of operation. © 2007 Microchip Technology Inc. DS41268D-page 57

PIC12F510/16F506 10.2 Oscillator Configurations FIGURE 10-1: CRYSTAL OPERATION (OR CERAMIC 10.2.1 OSCILLATOR TYPES RESONATOR) The PIC12F510/16F506 devices can be operated in up (HS, XT OR LP OSC to six different oscillator modes. The user can program CONFIGURATION) up to three Configuration bits (FOSC<1:0> [PIC12F510], FOSC<2:0> [PIC16F506]). To select one C1(1) OSC1 PIC12F510 of these modes: PIC16F506 Sleep •LP: Low-Power Crystal XTAL RF(3) •XT: Crystal/Resonator To internal logic •HS: High-Speed Crystal/Resonator OSC2 RS(2) (PIC16F506 only) C2(1) •INTOSC: Internal 4/8MHz Oscillator •EXTRC: External Resistor/Capacitor Note 1: See Capacitor Selection tables for recommended values of C1 and C2. •EC: External High-Speed Clock Input 2: A series resistor (RS) may be required for AT (PIC16F506 only) strip cut crystals. 3: RF approx. value = 10MΩ. 10.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In HS (PIC16F506), XT or LP modes, a crystal or FIGURE 10-2: EXTERNAL CLOCK INPUT ceramic resonator is connected to the (GP5/RB5)/ OPERATION (HS, XT OR OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins LP OSC to establish oscillation (Figure10-1). The PIC12F510/ CONFIGURATION) 16F506 oscillator designs require the use of a parallel cut crystal. Use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. Clock from OSC1 When in HS (PIC16F506), XT or LP modes, the device PIC12F510 ext. system can have an external clock source drive the (GP5/ PIC16F506 RB5)/OSC1/CLKIN pin (Figure10-2). When the part is Open OSC2 used in this fashion, the output drive levels on the OSC2 pin are very weak. This pin should be left open and unloaded. Also, when using this mode, the external clock should observe the frequency limits for the clock TABLE 10-1: CAPACITOR SELECTION FOR mode chosen (HS, XT or LP). CERAMIC RESONATORS – PIC12F510/16F506(1) Note1: This device has been designed to per- form to the parameters of its data sheet. Osc. Resonator Cap. Range Cap. Range It has been tested to an electrical Type Freq. C1 C2 specification designed to determine its XT 4.0 MHz 30 pF 30 pF conformance with these parameters. HS(2) 16 MHz 10-47 pF 10-47 pF Due to process differences in the manufacture of this device, this device Note 1: These values are for design guidance may have different performance charac- only. Since each resonator has its own teristics than its earlier version. These characteristics, the user should consult differences may cause this device to the resonator manufacturer for perform differently in your application appropriate values of external than the earlier version of this device. components. 2: The user should verify that the device 2: PIC16F506 only. oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required. DS41268D-page 58 © 2007 Microchip Technology Inc.

PIC12F510/16F506 TABLE 10-2: CAPACITOR SELECTION FOR FIGURE 10-3: EXTERNAL PARALLEL CRYSTAL OSCILLATOR – RESONANT CRYSTAL PIC12F510/16F506(2) OSCILLATOR CIRCUIT Osc. Resonator Cap.Range Cap. Range +5V To Other Type Freq. C1 C2 Devices 10k LP 32kHz(1) 15pF 15pF 4.7k 74AS04 XT 200 kHz 47-68 pF 47-68 pF 74AS04 CLKIN 1 MHz 15 pF 15 pF PIC12F510 4 MHz 15 pF 15 pF PIC16F506 HS(3) 20 MHz 15-47 pF 15-47 pF 10k Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is XTAL recommended. 10k 2: These values are for design guidance only. Rs may be required to avoid over- 20 pF 20 pF driving crystals beyond the drive level specification. Since each crystal has its Figure10-4 shows a series resonant oscillator circuit. own characteristics, the user should con- This circuit is also designed to use the fundamental sult the crystal manufacturer for appropri- frequency of the crystal. The inverter performs a 180- ate values of external components. degree phase shift in a series resonant oscillator 3: PIC16F506 only. circuit. The 330Ω resistors provide the negative feedback to bias the inverters in their linear region. 10.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT FIGURE 10-4: EXTERNAL SERIES Either a prepackaged oscillator or a simple oscillator RESONANT CRYSTAL circuit with TTL gates can be used as an external OSCILLATOR CIRCUIT crystal oscillator circuit. Prepackaged oscillators To Other provide a wide operating range and better stability. A 330 330 Devices well-designed crystal oscillator will provide good perfor- mance with TTL gates. Two types of crystal oscillator 74AS04 74AS04 74AS04 circuits can be used: one with parallel resonance or one CLKIN with series resonance. 0.1 mF PIC12F510 Figure10-3 shows implementation of a parallel reso- XTAL PIC16F506 nant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a 10.2.4 EXTERNAL RC OSCILLATOR parallel oscillator requires. The 4.7kΩ resistor provides the negative feedback for stability. The 10kΩ potenti- For timing insensitive applications, the EXTRC device ometers bias the 74AS04 in the linear region. This option offers additional cost savings. The EXTRC oscil- circuit could be used for external oscillator designs. lator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal pro- cess parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure10-5 shows how the R/C combination is connected to the PIC12F510/16F506 devices. For REXT values below 5.0kΩ, the oscillator operation may become unstable or stop completely. For very high REXT values (e.g.,1MΩ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 5.0kΩ and 100kΩ. © 2007 Microchip Technology Inc. DS41268D-page 59

PIC12F510/16F506 Although the oscillator will operate with no external In addition, a calibration instruction is programmed into capacitor (CEXT = 0pF), we recommend using values the last address of memory, which contains the calibra- above 20pF for noise and stability reasons. With no tion value for the internal RC oscillator. This location is capacitance or small external capacitance, the oscilla- always uncode protected, regardless of the code-pro- tion frequency can vary dramatically due to changes in tect settings. This value is programmed as a MOVLW XX external capacitances, such as PCB trace capacitance instruction where XX is the calibration value, and is or package lead frame capacitance. placed at the Reset vector. This will load the W register with the calibration value upon Reset and the PC will Section13.0 “Electrical Characteristics”, shows RC then roll over to the users program at address 0x000. frequency variation from part-to-part due to normal The user then has the option of writing the value to the process variation. The variation is larger for larger val- OSCCAL Register (05h) or ignoring it. ues of R (since leakage current variation will affect RC frequency more for large R) and for smaller values of C OSCCAL, when written to with the calibration value, will (since variation of input capacitance will affect RC “trim” the internal oscillator to remove process variation frequency more). from the oscillator frequency. Also, see the Electrical Specifications section for Note: Erasing the device will also erase the pre- variation of oscillator frequency due to VDD for given programmed internal calibration value for REXT/CEXT values, as well as frequency variation due the internal oscillator. The calibration to operating temperature for given R, C and VDD value must be read prior to erasing the values. part so it can be reprogrammed correctly later. FIGURE 10-5: EXTERNAL RC For the PIC12F510/16F506 devices, only bits <7:1> of OSCILLATOR MODE OSCCAL are used for calibration. See Register4-5 for more information. VDD Note: The 0 bit of OSCCAL is unimplemented REXT Internal and should be written as ‘0’ when modify- OSC1 clock ing OSCCAL for compatibility with future devices. N CEXT PIC12F510 VSS PIC16F506 FOSC/4 OSC2/CLKOUT 10.2.5 INTERNAL 4/8MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4/8MHz (nominal) system clock (see Section13.0 “Electrical Characteristics” for information on variation over voltage and temperature). DS41268D-page 60 © 2007 Microchip Technology Inc.

PIC12F510/16F506 10.3 Reset The device differentiates between various kinds of Reset: • Power-on Reset (POR) • MCLR Reset during normal operation • MCLR Reset during Sleep • WDT Time-out Reset during normal operation • WDT Time-out Reset during Sleep • Wake-up from Sleep Reset on pin change • Wake-up from Sleep Reset on comparator change Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset. Most other registers are reset to “Reset state” on Power-on Reset (POR), MCLR, WDT or Wake-up from Sleep Reset on pin change or wake-up from Sleep Reset on comparator change. The exceptions are TO, PD, CWUF and RBWUF/GPWUF bits. They are set or cleared differently in different Reset situations. These bits are used in software to determine the nature of Reset. See Table10-4 for a full description of Reset states of all registers. TABLE 10-3: RESET CONDITIONS FOR REGISTERS – PIC12F510 MCLR Reset, WDT Time-out, Register Address Power-on Reset Wake-up On Pin Change, Wake-up on Comparator Change W — qqqq qqqu(1) qqqq qqqu(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx qq0q quuu(2) FSR 04h 110x xxxx 11uu uuuu OSCCAL 05h 1111 111- uuuu uuu- GPIO 06h --xx xxxx --uu uuuu CM1CON0 07h 1111 1111 uuuu uuuu ADCON0 08h 1111 1100 uu11 1100 ADRES 09h xxxx xxxx uuuu uuuu OPTION — 1111 1111 1111 1111 TRISIO — --11 1111 --11 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table10-5 for Reset value for specific conditions. © 2007 Microchip Technology Inc. DS41268D-page 61

PIC12F510/16F506 TABLE 10-4: RESET CONDITIONS FOR REGISTERS – PIC16F506 MCLR Reset, WDT Time-out, Register Address Power-on Reset Wake-up On Pin Change, Wake-up on Comparator Change W — qqqq qqqu(1) qqqq qqqu(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 10uq quuu(2) FSR 04h 100x xxxx 10uu uuuu OSCCAL 05h 1111 111- uuuu uuu- PORTB 06h --xx xxxx --uu uuuu PORTC 07h --xx xxxx --uu uuuu CM1CON0 08h 1111 1111 uuuu uuuu ADCON0 09h 1111 1100 uu11 1100 ADRES 0Ah xxxx xxxx uuuu uuuu CM2CON0 0Bh 1111 1111 uuuu uuuu VRCON 0Ch 0011 1111 uuuu uuuu OPTION — 1111 1111 1111 1111 TRISB — --11 1111 --11 1111 TRISC — --11 1111 --11 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table10-5 for Reset value for specific conditions. TABLE 10-5: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h PCL Addr: 02h Power-on Reset 0001 1xxx 1111 1111 MCLR Reset during normal operation 000u uuuu 1111 1111 MCLR Reset during Sleep 0001 0uuu 1111 1111 WDT Reset during Sleep 0000 0uuu 1111 1111 WDT Reset normal operation 0000 uuuu 1111 1111 Wake-up from Sleep Reset on pin change 1001 0uuu 1111 1111 Wake from Sleep Reset on Comparator 0101 0uuu 1111 1111 Change Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’. DS41268D-page 62 © 2007 Microchip Technology Inc.

PIC12F510/16F506 10.3.1 MCLR ENABLE A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure10-7. This Configuration bit, when unprogrammed (left in the ‘1’ state), enables the external MCLR function. When The Power-on Reset circuit and the Device Reset programmed, the MCLR function is tied to the internal Timer (see Section10.5 “Device Reset Timer VDD and the pin is assigned to be a I/O. See (DRT)”) circuit are closely related. On power-up, the Figure10-6. Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR, internal or FIGURE 10-6: MCLR SELECT external, to be high. After the time-out period, it will reset the Reset latch and thus end the on-chip Reset signal. GPWU/RBWU (GP3/RB3)/MCLR/VPP A power-up example where MCLR is held low is shown in Figure10-8. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. MCLRE Internal MCLR In Figure10-9, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be (GP3/RB3). The VDD is stable before the Start-up timer times out and there is no prob- 10.4 Power-on Reset (POR) lem in getting a proper Reset. However, Figure10-10 depicts a problem situation where VDD rises too slowly. The PIC12F510/16F506 devices incorporate an on- The time between when the DRT senses that MCLR is chip Power-on Reset (POR) circuitry, which provides high and when MCLR and VDD actually reach their full an internal chip Reset for most power-up situations. value, is too long. In this situation, when the start-up The on-chip POR circuit holds the chip in Reset until timer times out, VDD has not reached the VDD (min) VDD has reached a high enough level for proper oper- value and the chip may not function correctly. For such ation. The POR is active regardless of the state of the situations, we recommend that external RC circuits be MCLR enable bit. An internal weak pull-up resistor is used to achieve longer POR delay times (Figure10-9). implemented using a transistor (refer to Table13-3 for Note: When the devices start normal operation the pull-up resistor ranges). This will eliminate external (exit the Reset condition), device operat- RC components usually needed to create an external ing parameters (voltage, frequency, Power-on Reset. A maximum rise time for VDD is spec- temperature, etc.) must be met to ensure ified. See Section13.0 “Electrical Characteristics” operation. If these conditions are not met, for details. the device must be held in Reset until the When the devices start normal operation (exit the operating conditions are met. Reset condition), device operating parameters (volt- For additional information, refer to Application Notes age, frequency, temperature,...) must be met to ensure AN522, “Power-Up Considerations” (DS00522) and operation. If these conditions are not met, the devices AN607, “Power-up Trouble Shooting” (DS00607). must be held in Reset until the operating parameters are met. © 2007 Microchip Technology Inc. DS41268D-page 63

PIC12F510/16F506 FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) (GP3/RB3)/MCLR/VPP MCLR Reset S Q MCLRE R Q WDT Time-out WDT Reset Start-up Timer CHIP Reset (10 ms, 1.125ms Pin Change or 18 ms) Sleep Wake-up on pin Change Reset Comparator Change Wake-up on Comparator Change FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR Internal POR TDRT DRT Time-out Internal Reset DS41268D-page 64 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 10-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min. © 2007 Microchip Technology Inc. DS41268D-page 65

PIC12F510/16F506 10.5 Device Reset Timer (DRT) TABLE 10-6: TYPICAL DRT PERIODS On the PIC12F510/16F506 devices, the DRT runs any Oscillator Subsequent POR Reset time the device is powered up. DRT runs from Reset Configuration Resets and varies based on oscillator selection and Reset type LP 18ms 18ms (see Table10-6). XT 18ms 18ms The DRT operates from a free running on-chip oscilla- tor that is separate from INTOSC. The processor is HS(1) 18ms 18ms kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD minimum and for EC(1) 1.125ms 10μs the oscillator to stabilize. INTOSC 1.125ms 10μs Oscillator circuits, based on crystals or ceramic resona- EXTRC 1.125ms 10μs tors, require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the devices Note 1: PIC16F506 only in a Reset for a set period, as stated in Table10-6, after MCLR has reached a logic high (VIH MCLR) level. Note: It is the responsibility of the application Programming (GP3/RB3)/MCLR/VPP as MCLR and designer to ensure the use of the using an external RC network connected to the MCLR 1.125ms nominal DRT will result in input is not required in most cases. This allows savings acceptable operation. Refer to Electrical in cost-sensitive and/or space restricted applications, Specifications for VDD rise time and as well as allowing the use of the (GP3/RB3)/MCLR/ stability requirements for this mode of VPP pin as a general purpose input. operation. The DRT delays will vary from chip-to-chip due to VDD, 10.6.1 WDT PERIOD temperature and process variation. See AC parameters for details. The WDT has a nominal time-out period of 18ms (with The DRT will also be triggered upon a Watchdog Timer no prescaler). If a longer time-out period is desired, a time-out from Sleep. This is particularly important for prescaler with a divisor ratio of up to 1:128 can be applications using the WDT to wake from Sleep mode assigned to the WDT (under software control) by automatically. writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These Reset sources are POR, MCLR, WDT time-out, Wake- periods vary with temperature, VDD and part-to-part up on Pin Change and Wake-up on Comparator process variations (see DC specs). Change. See Section10.9.2 “Wake-up from Sleep Reset”, Notes 1, 2 and 3. Under worst-case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several 10.6 Watchdog Timer (WDT) seconds before a WDT time-out occurs. The Watchdog Timer (WDT) is a free running on-chip 10.6.2 WDT PROGRAMMING RC oscillator that does not require any external CONSIDERATIONS components. This RC oscillator is separate from the The CLRWDT instruction clears the WDT and the external RC oscillator of the (GP5/RB5)/OSC1/CLKIN postscaler, if assigned to the WDT, and prevents it from pin and the internal 4/8MHz oscillator. This means that timing out and generating a device Reset. the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP The SLEEP instruction resets the WDT and the instruction. During normal operation or Sleep, a WDT postscaler, if assigned to the WDT. This gives the maximum Sleep time before a WDT wake-up Reset. Reset or wake-up Reset generates a device Reset. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by program- ming the configuration WDTE as a ‘0’ (see Section10.1 “Configuration Bits”). Refer to the PIC12F510/16F506 Programming Specifications to determine how to access the Configuration Word. DS41268D-page 66 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 10-11: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure6-5) 0 M Watchdog 1 U PPoossttssccaalleerr Timer X 8-to-1 MUX PS<2:0> PSA WDTE To Timer0 (Figure6-4) 0 1 MUX PSA WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. TABLE 10-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets N/A OPTION(1) GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A OPTION(2) RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer. – = unimplemented, read as ‘0’, u = unchanged. Note 1: PIC12F510 only. 2: PIC16F506 only. © 2007 Microchip Technology Inc. DS41268D-page 67

PIC12F510/16F506 10.7 Time-out Sequence, Power-down FIGURE 10-13: BROWN-OUT and Wake-up from Sleep Status PROTECTION CIRCUIT 2 Bits (TO, PD, GPWUF/RBWUF) VDD VDD The TO, PD and (GPWUF/RBWUF) bits in the STATUS register can be tested to determine if a Reset condition R1 PIC12F510 has been caused by a power-up condition, a MCLR or PIC16F506 Watchdog Timer (WDT) Reset. Q1MCLR(2) TABLE 10-8: TO/PD/(GPWUF/RBWUF) R2 40k(1) STATUS AFTER RESET GPWUF/ CWUF TO PD Reset Caused By RBWUF Note 1: This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns 0 0 0 0 WDT wake-up from off when VDD is below a certain level such Sleep that: 0 0 0 u WDT time-out (not R1 from Sleep) VDD • = 0.7V R1 + R2 0 0 1 0 MCLR wake-up from 2: Pin must be configured as MCLR. Sleep 0 0 1 1 Power-up 0 0 u u MCLR not during FIGURE 10-14: BROWN-OUT Sleep PROTECTION CIRCUIT 3 0 1 1 0 Wake-up from Sleep VDD on pin change 1 0 1 0 Wake-up from Sleep MCP809 Bypass VDD on comparator VSS Capacitor VDD change RST Legend: u = unchanged MCLR PIC12F510 10.8 Reset on Brown-out PIC16F506 A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a Note: This brown-out protection circuit employs brown-out. Microchip Technology’s MCP809 microcon- troller supervisor. There are 7 different trip To reset PIC12F510/16F506 devices when a brown- point selections to accommodate 5V to 3V out occurs, external brown-out protection circuits may systems. be built, as shown in Figure10-12 and Figure10-13. FIGURE 10-12: BROWN-OUT PROTECTION CIRCUIT 1 VDD VDD 33k PIC12F510 PIC16F506 10k Q1 MCLR(2) 40k(1) Note 1: This circuit will activate Reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). 2: Pin must be configured as MCLR. DS41268D-page 68 © 2007 Microchip Technology Inc.

PIC12F510/16F506 10.9 Power-Down Mode (Sleep) A device may be powered down (Sleep) and later Note1: Caution: Right before entering Sleep, powered up (wake-up from Sleep Reset). read the comparator Configuration register(s) CM1CON0 and CM2CON0. 10.9.1 SLEEP When in Sleep, wake-up occurs when the comparator output bit C1OUT and The Power-Down mode is entered by executing a C2OUT change from the state they were SLEEP instruction. in at the last reading. If a wake-up on If enabled, the Watchdog Timer will be cleared but comparator change occurs and the pins keeps running, the TO bit (STATUS<4>) is set, the PD are not read before re-entering Sleep, a bit (STATUS<3>) is cleared and the oscillator driver is wake-up will occur immediately, even if turned off. The I/O ports maintain the status they had no pins change while in Sleep mode. before the SLEEP instruction was executed (driving 2: For 16F506 only. high, driving low or high-impedance). The WDT is cleared when the device wakes from Note: A device Reset generated by a WDT Sleep, regardless of the wake-up source. time-will not drive the MCLR pin low. For lowest current consumption while powered down, 10.10 Program Verification/Code all input pins should be at VDD or VSS and (GP3/RB3)/ Protection MCLR/VPP pin must be at a logic high level if MCLR is enabled. If the code protection bit has not been programmed, the on-chip program memory can be read out for 10.9.2 WAKE-UP FROM SLEEP RESET verification purposes. The device can wake-up from Sleep through one of the The first 64 locations and the last location (OSCCAL) following events: can be read, regardless of the code protection bit setting. 1. An external Reset input on (GP3/RB3)/MCLR/ VPP pin when configured as MCLR. The last memory location can be read regardless of the 2. A Watchdog Timer Time-out Reset (if WDT was code protection bit setting on the PIC12F510/16F506 enabled). devices. 3. A change-on-input pin GP0/RB0, GP1/RB1, 10.11 ID Locations GP3/RB3 or RB4 when wake-up on change is enabled. Four memory locations are designated as ID locations 4. A change in the comparator ouput bits, C1OUT where the user can store checksum or other code and C2OUT (if comparator wake-up is enabled). identification numbers. These locations are not These events cause a device Reset. The TO, PD, accessible during normal execution, but are readable CWUF and GPWUF/RBWUF bits can be used to deter- and writable during Program/Verify. mine the cause of device Reset. The TO bit is cleared Use only the lower 4 bits of the ID locations and always if a WDT time-out occurred (and caused wake-up). The set the upper 4 bits as ‘1’s. The upper 4 bits are PD bit, which is set on power-up, is cleared when unimplemented. SLEEP is invoked. The CWUF bit indicates a change in These locations can be read regardless of the code comparator output state while the device was in Sleep. protect setting. The GPWUF/RBWUF bit indicates a change in state while in Sleep at pins GP0/RB0, GP1/RB1, GP3/RB3 or RB4 (since the last file or bit operation on GP/RB port). Note: Caution: Right before entering Sleep, read the input pins. When in Sleep, wake- up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering Sleep, a wake-up will occur immediately even if no pins change while in Sleep mode. © 2007 Microchip Technology Inc. DS41268D-page 69

PIC12F510/16F506 10.12 In-Circuit Serial Programming™ FIGURE 10-15: TYPICAL IN-CIRCUIT (ICSP™) SERIAL PROGRAMMING CONNECTION The PIC12F510/16F506 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, To Normal and three other lines for power, ground and the External Connections PIC12F510 programming voltage. This allows customers to manu- Connector Signals PIC16F506 facture boards with unprogrammed devices and then program the microcontroller just before shipping the +5V VDD product. This also allows the most recent firmware, or 0V VSS a custom firmware, to be programmed. VPP MCLR/VPP The devices are placed into a Program/Verify mode by holding the GP1/RB1 and GP0/RB0 pins low while rais- CLK GP1/RB1 ing the MCLR (VPP) pin from VIL to VIHH (see program- Data I/O GP0/RB0 ming specification). GP1/RB1 becomes the programming clock and GP0/RB0 becomes the programming data. Both GP1/RB1 and GP0/RB0 are VDD Schmitt Trigger inputs in this mode. After Reset, a 6-bit command is supplied to the device. To Normal Connections Depending on the command and if the command was a Load or a Read, 14 bits of program data are then sup- plied to or from the device. For complete details of serial programming, please refer to the PIC12F510/16F506 Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure10-15. DS41268D-page 70 © 2007 Microchip Technology Inc.

PIC12F510/16F506 11.0 INSTRUCTION SET SUMMARY All instructions are executed within a single instruction cycle, unless a conditional test is true or the program The PIC16 instruction set is highly orthogonal and is counter is changed as a result of an instruction. In this comprised of three basic categories. case, the execution takes two instruction cycles. One • Byte-oriented operations instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4MHz, the normal • Bit-oriented operations instruction execution time is 1μs. If a conditional test is • Literal and control operations true or the program counter is changed as a result of an Each PIC16 instruction is a 12-bit word divided into an instruction, the instruction execution time is 2μs. opcode, which specifies the instruction type, and one Figure11-1 shows the three general formats that the or more operands which further specify the operation instructions can have. All examples in the figure use of the instruction. The formats for each of the catego- the following format to represent a hexadecimal ries is presented in Figure11-1, while the various number: opcode fields are summarized in Table11-1. 0xhhh For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination where ‘h’ signifies a hexadecimal digit. designator. The file register designator specifies which file register is to be used by the instruction. FIGURE 11-1: GENERAL FORMAT FOR INSTRUCTIONS The destination designator specifies where the result of the operation is to be placed. If ‘d’ is ‘0’, the result is Byte-oriented file register operations placed in the W register. If ‘d’ is ‘1’, the result is placed 11 6 5 4 0 in the file register specified in the instruction. OPCODE d f (FILE #) For bit-oriented instructions, ‘b’ represents a bit field d = 0 for destination W designator which selects the number of the bits d = 1 for destination f affected by the operation, while ‘f’ represents the f = 5-bit file register address number of the file in which the bit is located. Bit-oriented file register operations For literal and control operations, ‘k’ represents an 11 8 7 5 4 0 8or 9-bit constant or literal value. OPCODE b (BIT #) f (FILE #) TABLE 11-1: OPCODE FIELD b = 3-bit bit address DESCRIPTIONS f = 5-bit file register address Field Description Literal and control operations (except GOTO) f Register file address (0x00 to 0x7F) 11 8 7 0 W Working register (accumulator) OPCODE k (literal) b Bit address within an 8-bit file register k = 8-bit immediate value k Literal field, constant data or label x Don’t care location (= 0 or 1) Literal and control operations – GOTO instruction The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all 11 9 8 0 Microchip software tools. OPCODE k (literal) d Destination select; d = 0 (store result in W) k = 9-bit immediate value d = 1 (store result in file register ‘f’) Default is d = 1 label Label name TOS Top-of-Stack PC Program Counter WDT Watchdog Timer counter TO Time-out bit PD Power-down bit dest Destination, either the W register or the specified register file location [ ] Options ( ) Contents → Assigned to < > Register bit field ∈ In the set of italics User defined term (font is courier) © 2007 Microchip Technology Inc. DS41268D-page 71

PIC12F510/16F506 TABLE 11-2: INSTRUCTION SET SUMMARY Mnemonic, 12-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected ADDWF f, d Add W and f 1 0001 11df ffff C, DC, Z 1, 2, 4 ANDWF f, d AND W with f 1 0001 01df ffff Z 2, 4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW – Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2, 4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2, 4 INCF f, d Increment f 1 0010 10df ffff Z 2, 4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2, 4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2, 4 MOVF f, d Move f 1 0010 00df ffff Z 2, 4 MOVWF f Move W to f 1 0000 001f ffff None 1, 4 NOP – No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2, 4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2, 4 SUBWF f, d Subtract W from f 1 0000 10df ffff C, DC, Z 1, 2, 4 SWAPF f, d Swap f 1 0011 10df ffff None 2, 4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2, 4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2, 4 BTFSC f, b Bit Test f, Skip if Clear 1(2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1(2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call Subroutine 2 1001 kkkk kkkk None 1 CLRWDT – Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk Z MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION – Load OPTION register 1 0000 0000 0010 None RETLW k Return, place literal in W 2 1000 kkkk kkkk None SLEEP – Go into Standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the Program Counter will be forced to a ‘0’ by any instruction that writes to the PC except for GOTO. See Section4.6 “Program Counter”. 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS41268D-page 72 © 2007 Microchip Technology Inc.

PIC12F510/16F506 ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BCF f,b Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) + (f) → (dest) Operation: 0 → (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is cleared. and register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BSF Bit Set f Syntax: [ label ] ANDLW k Syntax: [ label ] BSF f,b Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 31 Operation: (W).AND. (k) → (W) 0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: Z Status Affected: None Description: The contents of the W register are AND’ed with the eight-bit literal ‘k’. Description: Bit ‘b’ in register ‘f’ is set. The result is placed in the W register. ANDWF AND W with f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] 0 ≤ b ≤ 7 Operation: (W) .AND. (f) → (dest) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of the W register are Description: If bit ‘b’ in register ‘f’ is ‘0’, then the AND’ed with register ‘f’. If ‘d’ is ‘0’, next instruction is skipped. the result is stored in the W register. If bit ‘b’ is ‘0’, then the next instruc- If ‘d’ is ‘1’, the result is stored back tion fetched during the current in register ‘f’. instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction. © 2007 Microchip Technology Inc. DS41268D-page 73

PIC12F510/16F506 BTFSS Bit Test f, Skip if Set CLRW Clear W Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRW Operands: 0 ≤ f ≤ 31 Operands: None 0 ≤ b < 7 Operation: 00h → (W); Operation: skip if (f<b>) = 1 1 → Z Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ is ‘1’, then the Description: The W register is cleared. Zero bit next instruction is skipped. (Z) is set. If bit ‘b’ is ‘1’, then the next instruc- tion fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. CALL Subroutine Call CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 255 Operands: None Operation: (PC) + 1→ Top-of-Stack; Operation: 00h → WDT; k → PC<7:0>; 0 → WDT prescaler (if assigned); (STATUS <6:5>) → PC<10:9>; 1 → TO; 0 → PC<8> 1 → PD Status Affected: None Status Affected: TO, PD Description: Subroutine call. First, return Description: The CLRWDT instruction resets the address (PC + 1) is PUSHed onto WDT. It also resets the prescaler, if the stack. The eight-bit immediate the prescaler is assigned to the address is loaded into PC WDT and not Timer0. Status bits bits <7:0>. The upper bits TO and PD are set. PC<10:9> are loaded from STATUS <6:5>, PC<8> is cleared. CALL is a two-cycle instruction. CLRF Clear f COMF Complement f Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 Operation: 00h → (f); d ∈ [0,1] 1 → Z Operation: (f) → (dest) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are cleared and the Z bit is set. complemented. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS41268D-page 74 © 2007 Microchip Technology Inc.

PIC12F510/16F506 DECF Decrement f INCF Increment f Syntax: [ label ] DECF f,d Syntax: [ label ] INCF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: (f) + 1 → (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, Description: The contents of register ‘f’ are the result is stored in the W incremented. If ‘d’ is ‘0’, the result register. If ‘d’ is ‘1’, the result is is placed in the W register. If ‘d’ is stored back in register ‘f’. ‘1’, the result is placed back in register ‘f’. DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: (f) – 1 → d; skip if result = 0 Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘0’, the next instruc- If the result is ‘0’, then the next tion, which is already fetched, is instruction, which is already discarded and a NOP is executed fetched, is discarded and a NOP is instead making it a two-cycle executed instead making it a instruction. two-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 511 Operands: 0 ≤ k ≤ 255 Operation: k → PC<8:0>; Operation: (W) .OR. (k) → (W) STATUS <6:5> → PC<10:9> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’. The 9-bit immediate value is The result is placed in the loaded into PC bits <8:0>. The W register. upper bits of PC are loaded from STATUS <6:5>. GOTO is a two- cycle instruction. © 2007 Microchip Technology Inc. DS41268D-page 75

PIC12F510/16F506 IORWF Inclusive OR W with f MOVWF Move W to f Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (W) → (f) Operation: (W).OR. (f) → (dest) Status Affected: None Status Affected: Z Description: Move data from the W register to Description: Inclusive OR the W register with register ‘f’. register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0 ≤ f ≤ 31 Operands: None d ∈ [0,1] Operation: No operation Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register ‘f’ are moved to destination ‘d’. If ‘d’ is ‘0’, destination is the W register. If ‘d’ is ‘1’, the destination is file register ‘f’. ‘d’ = 1 is useful as a test of a file register, since Status flag Z is affected. MOVLW Move Literal to W OPTION Load OPTION Register Syntax: [ label ] MOVLW k Syntax: [ label ] Option Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W) Operation: (W) → Option Status Affected: None Status Affected: None Description: The content of the W register is Description: The eight-bit literal ‘k’ is loaded loaded into the OPTION register. into the W register. The “don’t cares” will be assembled as ‘0’s. DS41268D-page 76 © 2007 Microchip Technology Inc.

PIC12F510/16F506 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] RETLW k Syntax: [label ] SLEEP Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W); Operation: 00h → WDT; TOS → PC 0 → WDT prescaler; 1 → TO; Status Affected: None 0 → PD Description: The W register is loaded with the Status Affected: TO, PD, RBWUF eight-bit literal ‘k’. The program counter is loaded from the top of Description: Time-out Status bit (TO) is set. The the stack (the return address). This Power-down Status bit (PD) is is a two-cycle instruction. cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See Section10.9 “Power-Down Mode (Sleep)” on Sleep for more details. RLF Rotate Left f through Carry SUBWF Subtract W from f Syntax: [ label ] RLF f,d Syntax: [label ] SUBWF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: See description below Operation: (f) – (W) → (dest) Status Affected: C Status Affected: C, DC, Z Description: The contents of register ‘f’ are Description: Subtract (2’s complement method) rotated one bit to the left through the W register from register ‘f’. If ‘d’ the Carry flag. If ‘d’ is ‘0’, the result is ‘0’, the result is stored in the W is placed in the W register. If ‘d’ is register. If ‘d’ is ‘1’, the result is ‘1’, the result is stored back in stored back in register ‘f’. register ‘f’. C register ‘f’ RRF Rotate Right f through Carry SWAPF Swap Nibbles in f Syntax: [ label ] RRF f,d Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31 d ∈ [0,1] d ∈ [0,1] Operation: See description below Operation: (f<3:0>) → (dest<7:4>); (f<7:4>) → (dest<3:0>) Status Affected: C Status Affected: None Description: The contents of register ‘f’ are rotated one bit to the right through Description: The upper and lower nibbles of the Carry flag. If ‘d’ is ‘0’, the result register ‘f’ are exchanged. If ‘d’ is is placed in the W register. If ‘d’ is ‘0’, the result is placed in W ‘1’, the result is placed back in register. If ‘d’ is ‘1’, the result is register ‘f’. placed in register ‘f’. C register ‘f’ © 2007 Microchip Technology Inc. DS41268D-page 77

PIC12F510/16F506 TRIS Load TRIS Register XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d Operands: f = 6 Operands: 0 ≤ f ≤ 31 Operation: (W) → TRIS register f d ∈ [0,1] Status Affected: None Operation: (W) .XOR. (f) → (dest) Description: TRIS register ‘f’ (f = 6 or 7) is Status Affected: Z loaded with the contents of the W Description: Exclusive OR the contents of the register W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. XORLW Exclusive OR literal with W Syntax: [label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. DS41268D-page 78 © 2007 Microchip Technology Inc.

PIC12F510/16F506 12.0 DEVELOPMENT SUPPORT 12.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers are supported with a full range of hardware and software development tools: The MPLAB IDE software brings an ease of software • Integrated Development Environment development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows® - MPLAB® IDE Software operating system-based application that contains: • Assemblers/Compilers/Linkers • A single graphical interface to all debugging tools - MPASMTM Assembler - Simulator - MPLAB C18 and MPLAB C30 C Compilers - Programmer (sold separately) - MPLINKTM Object Linker/ MPLIBTM Object Librarian - Emulator (sold separately) - MPLAB ASM30 Assembler/Linker/Library - In-Circuit Debugger (sold separately) • Simulators • A full-featured editor with color-coded context - MPLAB SIM Software Simulator • A multiple project manager • Emulators • Customizable data windows with direct edit of contents - MPLAB ICE 2000 In-Circuit Emulator • High-level source code debugging - MPLAB REAL ICE™ In-Circuit Emulator • Visual device initializer for easy register • In-Circuit Debugger initialization - MPLAB ICD 2 • Mouse over variable inspection • Device Programmers • Drag and drop variables from source to watch - PICSTART® Plus Development Programmer windows - MPLAB PM3 Device Programmer • Extensive on-line help - PICkit™ 2 Development Programmer • Integration of select third party tools, such as • Low-Cost Demonstration and Development HI-TECH Software C Compilers and IAR Boards and Evaluation Kits C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2007 Microchip Technology Inc. DS41268D-page 79

PIC12F510/16F506 12.2 MPASM Assembler 12.5 MPLAB ASM30 Assembler, Linker and Librarian The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. MPLAB ASM30 Assembler produces relocatable The MPASM Assembler generates relocatable object machine code from symbolic assembly language for files for the MPLINK Object Linker, Intel® standard HEX dsPIC30F devices. MPLAB C30 C Compiler uses the files, MAP files to detail memory usage and symbol assembler to produce its object file. The assembler reference, absolute LST files that contain source lines generates relocatable object files that can then be and generated machine code and COFF files for archived or linked with other relocatable object files and debugging. archives to create an executable file. Notable features of the assembler include: The MPASM Assembler features include: • Support for the entire dsPIC30F instruction set • Integration into MPLAB IDE projects • Support for fixed-point and floating-point data • User-defined macros to streamline • Command line interface assembly code • Rich directive set • Conditional assembly for multi-purpose source files • Flexible macro language • Directives that allow complete control over the • MPLAB IDE compatibility assembly process 12.6 MPLAB SIM Software Simulator 12.3 MPLAB C18 and MPLAB C30 The MPLAB SIM Software Simulator allows code C Compilers development in a PC-hosted environment by simulat- ing the PIC MCUs and dsPIC® DSCs on an instruction The MPLAB C18 and MPLAB C30 Code Development level. On any given instruction, the data areas can be Systems are complete ANSI C compilers for examined or modified and stimuli can be applied from Microchip’s PIC18 and PIC24 families of microcontrol- a comprehensive stimulus controller. Registers can be lers and the dsPIC30 and dsPIC33 family of digital sig- logged to files for further run-time analysis. The trace nal controllers. These compilers provide powerful buffer and logic analyzer display extend the power of integration capabilities, superior code optimization and the simulator to record and track program execution, ease of use not found with other compilers. actions on I/O, most peripherals and internal registers. For easy source level debugging, the compilers provide The MPLAB SIM Software Simulator fully supports symbol information that is optimized to the MPLAB IDE symbolic debugging using the MPLAB C18 and debugger. MPLAB C30 CCompilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator 12.4 MPLINK Object Linker/ offers the flexibility to develop and debug code outside MPLIB Object Librarian of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS41268D-page 80 © 2007 Microchip Technology Inc.

PIC12F510/16F506 12.7 MPLAB ICE 2000 12.9 MPLAB ICD 2 In-Circuit Debugger High-Performance Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a In-Circuit Emulator powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed The MPLAB ICE 2000 In-Circuit Emulator is intended USB interface. This tool is based on the Flash PIC to provide the product development engineer with a MCUs and can be used to develop for these and other complete microcontroller design tool set for PIC PIC MCUs and dsPIC DSCs. The MPLAB ICD2 utilizes microcontrollers. Software control of the MPLAB ICE the in-circuit debugging capability built into theFlash 2000 In-Circuit Emulator is advanced by the MPLAB devices. This feature, along with Microchip’s In-Circuit Integrated Development Environment, which allows Serial ProgrammingTM (ICSPTM) protocol, offers cost- editing, building, downloading and source debugging effective, in-circuit Flash debugging from the graphical from a single environment. user interface of the MPLAB Integrated Development The MPLAB ICE 2000 is a full-featured emulator Environment. This enables a designer to develop and system with enhanced trace, trigger and data monitor- debug source code by setting breakpoints, single step- ing features. Interchangeable processor modules allow ping and watching variables, and CPU status and the system to be easily reconfigured for emulation of peripheral registers. Running at full speed enables different processors. The architecture of the MPLAB testing hardware and applications in real time. MPLAB ICE 2000 In-Circuit Emulator allows expansion to ICD2 also serves as a development programmer for support new PIC microcontrollers. selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with 12.10 MPLAB PM3 Device Programmer advanced features that are typically found on more The MPLAB PM3 Device Programmer is a universal, expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were CE compliant device programmer with programmable chosen to best make these features available in a voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display simple, unified application. (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various 12.8 MPLAB REAL ICE In-Circuit package types. The ICSP™ cable assembly is included Emulator System as a standard item. In Stand-Alone mode, the MPLAB MPLAB REAL ICE In-Circuit Emulator System is PM3 Device Programmer can read, verify and program Microchip’s next generation high-speed emulator for PIC devices without a PC connection. It can also set Microchip Flash DSC® and MCU devices. It debugs and code protection in this mode. The MPLAB PM3 programs PIC® and dsPIC® Flash microcontrollers with connects to the host PC via an RS-232 or USB cable. the easy-to-use, powerful graphical user interface of the The MPLAB PM3 has high-speed communications and MPLAB Integrated Development Environment (IDE), optimized algorithms for quick programming of large included with each kit. memory devices and incorporates an SD/MMC card for file storage and secure data applications. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, low- voltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2007 Microchip Technology Inc. DS41268D-page 81

PIC12F510/16F506 12.11 PICSTART Plus Development 12.13 Demonstration, Development and Programmer Evaluation Boards The PICSTART Plus Development Programmer is an A wide variety of demonstration, development and easy-to-use, low-cost, prototype programmer. It evaluation boards for various PIC MCUs and dsPIC connects to the PC via a COM (RS-232) port. MPLAB DSCs allows quick application development on fully func- Integrated Development Environment software makes tional systems. Most boards include prototyping areas for using the programmer simple and efficient. The adding custom circuitry and provide application firmware PICSTART Plus Development Programmer supports and source code for examination and modification. most PIC devices in DIP packages up to 40 pins. The boards support a variety of features, including LEDs, Larger pin count devices, such as the PIC16C92X and temperature sensors, switches, speakers, RS-232 PIC17C76X, may be supported with an adapter socket. interfaces, LCD displays, potentiometers and additional The PICSTART Plus Development Programmer is CE EEPROM memory. compliant. The demonstration and development boards can be used in teaching environments, for prototyping custom 12.12 PICkit 2 Development Programmer circuits and for learning about various microcontroller The PICkit™ 2 Development Programmer is a low-cost applications. programmer and selected Flash device debugger with In addition to the PICDEM™ and dsPICDEM™ demon- an easy-to-use interface for programming many of stration/development board series of circuits, Microchip Microchip’s baseline, mid-range and PIC18F families of has a line of evaluation kits and demonstration software Flash memory microcontrollers. The PICkit 2 Starter Kit for analog filter design, KEELOQ® security ICs, CAN, includes a prototyping development board, twelve IrDA®, PowerSmart® battery management, SEEVAL® sequential lessons, software and HI-TECH’s PICC™ evaluation system, Sigma-Delta ADC, flow rate Lite C compiler, and is designed to help get up to speed sensing, plus many more. quickly using PIC® microcontrollers. The kit provides Check the Microchip web page (www.microchip.com) everything needed to program, evaluate and develop and the latest “Product Selector Guide” (DS00148) for applications using Microchip’s powerful, mid-range the complete list of demonstration, development and Flash memory family of microcontrollers. evaluation kits. DS41268D-page 82 © 2007 Microchip Technology Inc.

PIC12F510/16F506 13.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Ambient temperature under bias..........................................................................................................-40°C to +125°C Storage temperature............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS...............................................................................................................0 to +7.0V Voltage on MCLR with respect to VSS.............................................................................................................0 to +14V Voltage on all other pins with respect to VSS...............................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)..................................................................................................................................700mW Max. current out of VSS pin................................................................................................................................200mA Max. current into VDD pin...................................................................................................................................150mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20mA Output clamp current, IOK (VO < 0 or VO > VDD)...........................................................................................................±20mA Max. output current sunk by any I/O pin..............................................................................................................25mA Max. output current sourced by any I/O pin.........................................................................................................25mA Max. output current sourced by I/O port ............................................................................................................100mA Max. output current sunk by I/O port .................................................................................................................100mA Note1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL) †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. DS41268D-page 83

PIC12F510/16F506 FIGURE 13-1: VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C (PIC12F510) 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 25 Frequency (MHz) FIGURE 13-2: MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC12F510) LP e d XT o M r EXTRC o at INTOSC cill s O 0 200kHz 4MHz 8MHz 20MHz Frequency (MHz) DS41268D-page 84 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 13-3: VOLTAGE FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C (PIC16F506) 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 25 Frequency (MHz) FIGURE 13-4: MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC16F506) LP e XT d o M EXTRC r o INTOSC t a cill EC s O HS 0 200kHz 4MHz 8MHz 20MHz Frequency (MHz) © 2007 Microchip Technology Inc. DS41268D-page 85

PIC12F510/16F506 13.1 DC Characteristics: PIC12F510/16F506 (Industrial) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 40°C ≤ TA ≤ +85°C (industrial) Param Sym Characteristic Min Typ(1) Max Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure14-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section10.4 “Power-on Power-on Reset Reset (POR)” for details D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section10.4 “Power-on Power-on Reset Reset (POR)” for details D010 IDD Supply Current(3,4) — 175 275 μA FOSC = 4MHz, VDD = 2.0V — 0.625 1.1 mA FOSC = 4MHz, VDD = 5.0V — 250 450 μA FOSC = 8MHz, VDD = 2.0V — 1.0 1.5 mA FOSC = 8MHz, VDD = 5.0V — 1.4 2.0 mA FOSC = 20MHz, VDD = 5.0V — 11 15 μA FOSC = 32kHz, VDD = 2.0V — 38 52 μA FOSC = 32kHz, VDD = 5.0V D020 IPD Power-down Current(5) — 0.1 1.2 μA VDD = 2.0V — 0.35 2.4 μA VDD = 5.0V D022 IWDT WDT Current(5) — 1.0 3.0 μA VDD = 2.0V — 7.0 16.0 μA VDD = 5.0V D023 ICMP Comparator Current(5) — 15 22 μA VDD = 2.0V (per comparator) — 55 67 μA VDD = 5.0V (per comparator) D022 ICVREF CVREF Current(5) — 30 60 μA VDD = 2.0V (high range) — 75 125 μA VDD = 5.0V (high range) D023 IFVR Internal 0.6V Fixed Voltage — 85 120 μA VDD = 2.0V (0.6V reference and Reference Current(5) 1 comparator enabled) — 175 205 μA VDD = 5.0V (0.6V reference and 1 comparator enabled) D024 ΔIAD A/D Conversion Current(5) — 120 150 μA 2.0V — 200 250 μA 5.0V * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. 6: Does not include current through REXT. The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in kΩ. DS41268D-page 86 © 2007 Microchip Technology Inc.

PIC12F510/16F506 13.2 DC Characteristics: PIC12F510/16F506 (Extended) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 40°C ≤ TA ≤ +125°C (extended) Param Sym Characteristic Min Typ(1) Max Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure14-1 D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure — Vss — V See Section10.4 “Power-on Power-on Reset Reset (POR)” for details D004 SVDD VDD Rise Rate to ensure 0.05* — — V/ms See Section10.4 “Power-on Power-on Reset Reset (POR)” for details D010 IDD Supply Current(3,4) — 175 275 μA FOSC = 4MHz, VDD = 2.0V — 0.625 1.1 mA FOSC = 4MHz, VDD = 5.0V — 250 450 μA FOSC = 8MHz, VDD = 2.0V — 1.0 1.5 mA FOSC = 8MHz, VDD = 5.0V — 1.4 2.0 mA FOSC = 20MHz, VDD = 5.0V — 11 16 μA FOSC = 32kHz, VDD = 2.0V — 38 54 μA FOSC = 32kHz, VDD = 5.0V D020 IPD Power-down Current(5) — 0.1 9.0 μA VDD = 2.0V — 0.35 15.0 μA VDD = 5.0V D022 IWDT WDT Current(5) — 1.0 18 μA VDD = 2.0V — 7.0 22 μA VDD = 5.0V D023 ICMP Comparator Current(5) — 15 25 μA VDD = 2.0V (per comparator) — 55 75 μA VDD = 5.0V (per comparator) D022 ICVREF CVREF Current(5) — 30 65 μA VDD = 2.0V (high range) — 75 135 μA VDD = 5.0V (high range) D023 IFVR Internal 0.6V Fixed Voltage — 85 130 μA VDD = 2.0V (0.6V reference and Reference Current(5) 1 comparator enabled) — 175 220 μA VDD = 5.0V (0.6V reference and 1 comparator enabled) D024 ΔIAD A/D Conversion Current(5) — 120 150 μA 2.0V — 200 250 μA 5.0V * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. 5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep. 6: Does not include current through REXT. The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in kΩ. © 2007 Microchip Technology Inc. DS41268D-page 87

PIC12F510/16F506 13.3 DC Characteristics: PIC12F510/16F506 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports D030 with TTL buffer VSS — 0.8V V For 4.5 ≤ VDD ≤ 5.5V D030A VSS — 0.15VDD V otherwise D031 with Schmitt Trigger buffer VSS — 0.15VDD V D032 MCLR, T0CKI VSS — 0.15VDD V D033 OSC1 (in EXTRC), EC(1) VSS — 0.15 VDD V D033 OSC1 (in HS) VSS — 0.3VDD V D033 OSC1 (in XT and LP) VSS — 0.3 VDD V VIH Input High Voltage I/O ports — D040 with TTL buffer 2.0 — VDD V 4.5 ≤ VDD ≤ 5.5V D040A 0.25 VDD — VDD V Otherwise + 0.8V D041 with Schmitt Trigger buffer 0.85 VDD — VDD V For entire VDD range D042 MCLR, T0CKI 0.85VDD — VDD V D043 OSC1 (in EXTRC), EC(1) 0.85VDD — VDD V D043 OSC1 (in HS) 0.7VDD — VDD V D043 OSC1 (in XT and LP) 1.6 — VDD V D070 IPUR GPIO/PORTB Weak Pull-up Current 50 250 400 μA VDD = 5V, VPIN = VSS IIL Input Leakage Current(2), (3) D060 I/O ports — — ±1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D062 GP3/RB3/MCLR(5) 50 250 400 μA VDD = 5V D061A GP3/RB3/MCLR(4) — +0.7 ±5 μA VSS ≤ VPIN ≤ VDD D063 OSC1 — — ±5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration Output Low Voltage D080 VOL I/O ports/CLKOUT — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, –40°C to +85°C D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, –40°C to +125°C D083 OSC2 — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, –40°C to +85°C D083A — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, –40°C to +125°C Output High Voltage D090 VOH I/O ports/CLKOUT(3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, –40°C to +85°C D090A VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, –40°C to +125°C D092 OSC2 VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V, –40°C to +85°C D092A VDD – 0.7 — — V IOH = -1.0 mA, VDD = 4.5V, –40°C to +125°C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 CIO All I/O pins — — 50 pF † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F510/16F506 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: This specification applies when GP3/MCLR is configured as an input with the pull-up disabled. The leakage current for the GP3/RB3/ MCLR pin is higher than for the standard I/O port pins. 5: This specification applies when GP3/RB3/MCLR is configured as the MCLR Reset pin function with the weak pull-up always enabled. DS41268D-page 88 © 2007 Microchip Technology Inc.

PIC12F510/16F506 TABLE 13-1: COMPARATOR SPECIFICATIONS Sym Characteristics Min Typ Max Units Comments VOS Input Offset Voltage — ±3 ±10 mV (VDD - 1.5V)/2 VCM Input Common Mode Voltage 0 — VDD – 1.5 V CMRR Common Mode Rejection Ratio +55* — — dB TRT Response Time(1) — 150 400* ns Internal VIVRF Internal Voltage Reference 0.550 0.6 0.650 V * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD – 1.5V. TABLE 13-2: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Sym Characteristics Min Typ Max Units Comments CVRES Resolution — VDD/24* — LSb Low Range (VRR = 1) — VDD/32 — LSb High Range (VRR = 0) Absolute Accuracy — — ±1/2* LSb Low Range (VRR = 1) — — ±1/2* LSb High Range (VRR = 0) Unit Resistor Value (R) — 2K* — Ω — Settling Time(1) — — 10* μs * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. TABLE 13-3: A/D CONVERTER CHARACTERISTICS (PIC16F506/PIC12F510) Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8 bits bit A03 EIL Integral Error — — ± 1.5 LSb VDD = 5.0V A04 EDL Differential Error — — -1 < EDL ≤ 1.5 LSb No missing codes to 8 bits VDD = 5.0V A05 EFS Full-scale Range 2 — 5.5* V VDD A06 EOFF Offset Error — — ± 1.5 LSb VDD = 5.0V A07 EGN Gain Error -0.5 — +1.75 LSb VDD = 5.0V A10 — Monotonicity — guaranteed(1) — — VSS ≤ VAIN ≤ VDD A25 VAIN Analog Input Voltage VSS — VDD V A30 ZAIN Recommended Impedance — — 10 kΩ of Analog Voltage Source * These parameters are characterized but not tested. † Data in the “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only are not tested. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. © 2007 Microchip Technology Inc. DS41268D-page 89

PIC12F510/16F506 13.4 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase (pp) and their meanings: pp 2 To mc MCLR ck CLKOUT osc Oscillator cy Cycle Time os OSC1 drt Device Reset Timer t0 T0CKI io I/O port wdt Watchdog Timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (high-impedance) V Valid L Low Z High-impedance FIGURE 13-5: LOAD CONDITIONS Legend: Pin CL = 50pF for all pins except OSC2 Cl 15pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS FIGURE 13-6: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 DS41268D-page 90 © 2007 Microchip Technology Inc.

PIC12F510/16F506 TABLE 13-4: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Para Sym Characteristic Min Typ(1) Max Units Conditions No. 1A FOSC External CLKIN Frequency(2) DC — 4 MHz XT Oscillator mode DC — 20 MHz HS/EC Oscillator mode (PIC16F506 only) DC — 200 kHz LP Oscillator mode Oscillator Frequency(2) — — 4 MHz EXTRC Oscillator mode 0.1 — 4 MHz XT Oscillator mode 4 — 20 MHz HS/EC Oscillator mode (PIC16F506 only) — — 200 kHz LP Oscillator mode 1 TOSC External CLKIN Period(2) 250 — — ns XT Oscillator mode 50 — — ns HS/EC Oscillator mode (PIC16F506 only) 5 — — μs LP Oscillator mode Oscillator Period(2) 250 — — ns EXTRC Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 250 ns HS/EC Oscillator mode (PIC16F506 only) 5 — — μs LP Oscillator mode 2 TCY Instruction Cycle Time 200 4/FOSC — ns 3 TosL, Clock in (OSC1) Low or High 50* — — ns XT Oscillator TosH Time 2* — — μs LP Oscillator 10 — — ns HS/EC Oscillator (PIC16F506 only) 4 TosR, Clock in (OSC1) Rise or Fall — — 25* ns XT Oscillator TosF Time — — 50* ns LP Oscillator — — 15 ns HS/EC Oscillator (PIC16F506 only) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. © 2007 Microchip Technology Inc. DS41268D-page 91

PIC12F510/16F506 TABLE 13-5: CALIBRATED INTERNAL RC FREQUENCIES Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial), -40°C ≤ TA ≤ +125°C (extended) Param Freq. Sym Characteristic Min Typ(1) Max* Units Conditions No. Tolerance F10 FOSC Internal Calibrated INTOSC ±1% 7.92 8.00 8.08 MHz VDD = 3.5V TA = 25°C Frequency(1) ±2% 7.84 8.00 8.16 MHz 2.5V ≤ VDD ≤ 5.5V 0°C ≤ TA ≤ +85°C ±5% 7.60 8.00 8.40 MHz 2.0V ≤ VDD ≤ 5.5V -40°C ≤ TA ≤ +85°C (Ind.) -40°C ≤ TA ≤ +125°C (Ext.) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 13-7: I/O TIMING Q4 Q1 Q2 Q3 OSC1 I/O Pin (input) 17 19 18 I/O Pin Old Value New Value (output) 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50pF on I/O pins and CLKOUT. DS41268D-page 92 © 2007 Microchip Technology Inc.

PIC12F510/16F506 TABLE 13-6: TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Param Sym Characteristic Min Typ(1) Max Units No. 17 TOSH2IOV OSC1↑ (Q1 cycle) to Port out valid(2), (3) — — 100* ns 18 TOSH2IOI OSC1↑ (Q2 cycle) to Port input invalid 50 — — ns (I/O in hold time)(2) 19 TIOV2OSH Port input valid to OSC1↑ (I/O in setup time) 20 — — ns 20 TIOR Port output rise time(2), (3) — 10 25** ns 21 TIOF Port output fall time(2), (3) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure13-5 for loading conditions. FIGURE 13-8: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING VDD MCLR 30 Internal POR 32 32 32 DRT Timeout(2) Internal Reset Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT Reset only in XT, LP and HS modes. © 2007 Microchip Technology Inc. DS41268D-page 93

PIC12F510/16F506 TABLE 13-7: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Param Sym Characteristic Min Typ(1) Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2000* — — ns VDD = 5.0V 31 TWDT Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5.0V (Industrial) (No Prescaler) 9* 18* 40* ms VDD = 5.0V (Extended) 32 TDRT Device Reset Timer Period Standard 9* 18* 30* ms VDD = 5.0V (Industrial) 9* 18* 40* ms VDD = 5.0V (Extended) Short 0.5* 1.125* 2* ms VDD = 5.0V (Industrial) 0.5* 1.125* 2.5* ms VDD = 5.0V (Extended) 34 TIOZ I/O high-impedance from MCLR low — — 2000* ns * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 13-9: TIMER0 CLOCK TIMINGS T0CKI 40 41 42 TABLE 13-8: TIMER0 CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40°C ≤ TA ≤ +85°C (industrial) -40°C ≤ TA ≤ +125°C (extended) Parm Sym Characteristic Min Typ(1) Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS41268D-page 94 © 2007 Microchip Technology Inc.

PIC12F510/16F506 TABLE 13-9: PULL-UP RESISTOR RANGES VDD (Volts) Temperature (°C) Min Typ Max Units RB0 (GP0)/RB1 (GP1) 2.0 -40 73K 105K 186K Ω 25 73K 113K 187K Ω 85 82K 123K 190K Ω 125 86K 132k 190K Ω 5.5 -40 15K 21K 33K Ω 25 15K 22K 34K Ω 85 19K 26k 35K Ω 125 23K 29K 35K Ω RB3 (GP3) 2.0 -40 63K 81K 96K Ω 25 77K 93K 116K Ω 85 82K 96k 116K Ω 125 86K 100K 119K Ω 5.5 -40 16K 20k 22K Ω 25 16K 21K 23K Ω 85 24K 25k 28K Ω 125 26K 27K 29K Ω © 2007 Microchip Technology Inc. DS41268D-page 95

PIC12F510/16F506 NOTES: DS41268D-page 96 © 2007 Microchip Technology Inc.

PIC12F510/16F506 14.0 DC AND CHARACTERISTICS GRAPHS AND CHARTS. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean+3σ) or (mean - 3σ) respectively, where s is a standard deviation, over each temperature range. FIGURE 14-1: IDD vs. VDD OVER FOSC XT Mode 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-Case Temp) + 3σ Maximum (-40°C to 125°C) 1,000 4 MHz 800 A) Typical μ (D ID 600 4 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41268D-page 97

PIC12F510/16F506 FIGURE 14-2: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.35 0.30 A) 0.25 μ (D P 0.20 I 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 14-3: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 Typical: Statistical Mean @25°C 16.0 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 14.0 Max. 125°C 12.0 A) 10.0 μ (D P 8.0 I 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41268D-page 98 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 14-4: COMPARATOR IPD vs. VDD (COMPARATOR ENABLED) 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ Maximum (-40°C to 125°C) 60 Typical A) μ (PD 40 I 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 14-5: TYPICAL WDT IPD vs. VDD 9 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 7 (-40°C to 125°C) 6 A) 5 μ (PD 4 I 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41268D-page 99

PIC12F510/16F506 FIGURE 14-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 20.0 Max. 125°C 15.0 A) μ (D P I 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 14-7: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C 45 Max. 125°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 40 Max. 85°C 35 30 ms) Typical. 25°C e ( 25 m Ti 20 Min. -40°C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41268D-page 100 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 14-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.6 0.5 Max. 85°C V) (L 0.4 O V 0.3 Typical 25°C 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 14-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 MaximTuympi:c aMl:e Santa (tiWstoicraslt -MCeaasne @Te2m5p×)C + 3σ Maximum: Mea s( -+4 03×C to 125×C) (-40°C to 125°C) Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) © 2007 Microchip Technology Inc. DS41268D-page 101

PIC12F510/16F506 FIGURE 14-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 14-11: VOH vs. IOH OVER TE(MPERAT, URE (VDD = 5).0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) DS41268D-page 102 © 2007 Microchip Technology Inc.

PIC12F510/16F506 FIGURE 14-12: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 14-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc. DS41268D-page 103

PIC12F510/16F506 FIGURE 14-14: DEVICE RESET TIMER (HS, XT AND LP) vs. VDD Maximum (Sleep Mode all Peripherals Disabled) 45 40 35 30 Max. 125°C ms) 25 RT ( Max. 85°C D 20 15 Typical 25°C Min. -40°C 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Note: See Table13-7 if another clock mode is selected. DS41268D-page 104 © 2007 Microchip Technology Inc.

PIC12F510/16F506 15.0 PACKAGING 15.1 Package Marking Information 8-Lead PDIP Example XXXXXXXX 12F510/P XXXXXNNN 017 YYWW 0410 14-Lead PDIP Example XXXXXXXXXXXXXX PIC16F506-I/P XXXXXXXXXXXXXX 0410017 YYWWNNN 8-Lead SOIC (3.90 mm) Example XXXXXXXX PIC12F510-I XXXXYYWW /SN0410 NNN 017 8-Lead 2x3 DFN* Example X X X B E 0 Y W W 6 1 0 N N 1 7 TABLE 15-1: 8-LEAD 2X3 DFN (MC) TOP MARKING Part Number Marking PIC12F510(T)-I/MC BS0 PIC12F510-E/MC BT0 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PIC® device marking consists of Microchip part number, year code, week code and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2007 Microchip Technology Inc. DS41268D-page 105

PIC12F510/16F506 15.2 Package Marking Information (Cont’d) 14-Lead SOIC (3.90 mm) Example XXXXXXXXXXX PIC16F506 XXXXXXXXXXX -I/SL YYWWNNN 0410017 8-Lead MSOP Example XXXXXX 602/MS YWWNNN 310017 14-Lead TSSOP (4.4 mm) Example XXXXXXXX 16F506/ST YYWW 0410 NNN 017 DS41268D-page 106 © 2007 Microchip Technology Inc.

PIC12F510/16F506 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 1(cid:6)(cid:5)(cid:17)(cid:9) 23(cid:31)4"(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 8 (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) (cid:3)(cid:2)%%(cid:7)+(cid:29)(cid:31) -(cid:23)#(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) ( 9 9 (cid:3)(cid:27)(cid:2)% $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ((cid:27) (cid:3)(cid:2)(cid:2)* (cid:3)(cid:2) % (cid:3)(cid:2):* +(cid:11)(cid:9)(cid:14)(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) ((cid:2) (cid:3)%(cid:2)* 9 9 (cid:29)(cid:26)(cid:23)(cid:10)(cid:12)(cid:13)(cid:14)(cid:18)(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:26)(cid:23)(cid:10)(cid:12)(cid:13)(cid:14)(cid:18)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) " (cid:3)(cid:27):% (cid:3) (cid:2)% (cid:3) (cid:27)* $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) (cid:3)(cid:27)’% (cid:3)(cid:27)*% (cid:3)(cid:27)8% 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! (cid:3) ’8 (cid:3) <* (cid:3)’%% -(cid:5)#(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) 5 (cid:3)(cid:2)(cid:2)* (cid:3)(cid:2) % (cid:3)(cid:2)*% 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) (cid:3)%%8 (cid:3)%(cid:2)% (cid:3)%(cid:2)* 1##(cid:14)(cid:18)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22)(cid:2) (cid:3)%’% (cid:3)%<% (cid:3)%=% 5(cid:23)(cid:25)(cid:14)(cid:18)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) (cid:3)%(cid:2)’ (cid:3)%(cid:2)8 (cid:3)%(cid:27)(cid:27) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)>(cid:23)(cid:25)(cid:7)(cid:29)#(cid:11)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)(cid:7)(cid:28) (cid:14)+ 9 9 (cid:3)’ % (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:28)(cid:7)(cid:29)(cid:5)(cid:30)(cid:6)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:6)(cid:17)(cid:7)(cid:31)(cid:26)(cid:11)(cid:18)(cid:11)(cid:24)(cid:17)(cid:14)(cid:18)(cid:5)(cid:9)(cid:17)(cid:5)(cid:24)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)(cid:3)%(cid:2)%&(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) ’(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31),(cid:7)+(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?%(cid:2)8+ © 2007 Microchip Technology Inc. DS41268D-page 107

PIC12F510/16F506 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)(cid:17)(cid:18)(cid:3)(cid:4)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)(cid:9)(cid:20)(cid:8)(cid:21)(cid:8)(cid:22)(cid:23)(cid:23)(cid:8)(cid:24)(cid:13)(cid:10)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:9)(cid:15)(cid:17)(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 1(cid:6)(cid:5)(cid:17)(cid:9) 23(cid:31)4"(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 (cid:2)’ (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) (cid:3)(cid:2)%%(cid:7)+(cid:29)(cid:31) -(cid:23)#(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) ( 9 9 (cid:3)(cid:27)(cid:2)% $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ((cid:27) (cid:3)(cid:2)(cid:2)* (cid:3)(cid:2) % (cid:3)(cid:2):* +(cid:11)(cid:9)(cid:14)(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) ((cid:2) (cid:3)%(cid:2)* 9 9 (cid:29)(cid:26)(cid:23)(cid:10)(cid:12)(cid:13)(cid:14)(cid:18)(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:26)(cid:23)(cid:10)(cid:12)(cid:13)(cid:14)(cid:18)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) " (cid:3)(cid:27):% (cid:3) (cid:2)% (cid:3) (cid:27)* $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) (cid:3)(cid:27)’% (cid:3)(cid:27)*% (cid:3)(cid:27)8% 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! (cid:3)= * (cid:3)=*% (cid:3)==* -(cid:5)#(cid:7)(cid:17)(cid:23)(cid:7)(cid:29)(cid:14)(cid:11)(cid:17)(cid:5)(cid:6)(cid:30)(cid:7)(cid:4)(cid:12)(cid:11)(cid:6)(cid:14) 5 (cid:3)(cid:2)(cid:2)* (cid:3)(cid:2) % (cid:3)(cid:2)*% 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) (cid:3)%%8 (cid:3)%(cid:2)% (cid:3)%(cid:2)* 1##(cid:14)(cid:18)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22)(cid:2) (cid:3)%’* (cid:3)%<% (cid:3)%=% 5(cid:23)(cid:25)(cid:14)(cid:18)(cid:7)5(cid:14)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) (cid:3)%(cid:2)’ (cid:3)%(cid:2)8 (cid:3)%(cid:27)(cid:27) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)>(cid:23)(cid:25)(cid:7)(cid:29)#(cid:11)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)(cid:7)(cid:28) (cid:14)+ 9 9 (cid:3)’ % (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:28)(cid:7)(cid:29)(cid:5)(cid:30)(cid:6)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:6)(cid:17)(cid:7)(cid:31)(cid:26)(cid:11)(cid:18)(cid:11)(cid:24)(cid:17)(cid:14)(cid:18)(cid:5)(cid:9)(cid:17)(cid:5)(cid:24)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)(cid:3)%(cid:2)%&(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) ’(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31),(cid:7)+(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?%%*+ DS41268D-page 108 © 2007 Microchip Technology Inc.

PIC12F510/16F506 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)"(cid:24)(cid:6)(cid:10)(cid:10)(cid:8)#(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)"(cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)$$(cid:26)%&(cid:8)(cid:22)’((cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)"#(cid:17))(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) D e N E E1 NOTE1 1 2 3 b h α h c A A2 φ A1 L L1 β 1(cid:6)(cid:5)(cid:17)(cid:9) $2552$"-">(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 8 (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) (cid:2)(cid:3)(cid:27)=(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)4(cid:14)(cid:5)(cid:30)(cid:26)(cid:17) ( 9 9 (cid:2)(cid:3)=* $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ((cid:27) (cid:2)(cid:3)(cid:27)* 9 9 (cid:29)(cid:17)(cid:11)(cid:6)(cid:13)(cid:23)(cid:16)(cid:16)(cid:7)(cid:7)(cid:28) ((cid:2) %(cid:3)(cid:2)% 9 %(cid:3)(cid:27)* 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) " <(cid:3)%%(cid:7)+(cid:29)(cid:31) $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) (cid:3):%(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! ’(cid:3):%(cid:7)+(cid:29)(cid:31) (cid:31)(cid:26)(cid:11)(cid:19)(cid:16)(cid:14)(cid:18)(cid:7)@(cid:23)#(cid:17)(cid:5)(cid:23)(cid:6)(cid:11)(cid:12)A (cid:26) %(cid:3)(cid:27)* 9 %(cid:3)*% .(cid:23)(cid:23)(cid:17)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) 5 %(cid:3)’% 9 (cid:2)(cid:3)(cid:27)= .(cid:23)(cid:23)(cid:17)#(cid:18)(cid:5)(cid:6)(cid:17) 5(cid:2) (cid:2)(cid:3)%’(cid:7)>". .(cid:23)(cid:23)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14) (cid:2) %B 9 8B 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) %(cid:3)(cid:2)= 9 %(cid:3)(cid:27)* 5(cid:14)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) %(cid:3) (cid:2) 9 %(cid:3)*(cid:2) $(cid:23)(cid:12)(cid:13)(cid:7)!(cid:18)(cid:11)(cid:16)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14)(cid:7)-(cid:23)# (cid:3) *B 9 (cid:2)*B $(cid:23)(cid:12)(cid:13)(cid:7)!(cid:18)(cid:11)(cid:16)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14)(cid:7)+(cid:23)(cid:17)(cid:17)(cid:23)(cid:19) (cid:4) *B 9 (cid:2)*B (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:28)(cid:7)(cid:29)(cid:5)(cid:30)(cid:6)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:6)(cid:17)(cid:7)(cid:31)(cid:26)(cid:11)(cid:18)(cid:11)(cid:24)(cid:17)(cid:14)(cid:18)(cid:5)(cid:9)(cid:17)(cid:5)(cid:24)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)%(cid:3)(cid:2)*(cid:7)(cid:19)(cid:19)(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) ’(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31), +(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) >"., >(cid:14)(cid:16)(cid:14)(cid:18)(cid:14)(cid:6)(cid:24)(cid:14)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:21)(cid:7)(cid:10)(cid:9)(cid:10)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:21)(cid:7)(cid:16)(cid:23)(cid:18)(cid:7)(cid:5)(cid:6)(cid:16)(cid:23)(cid:18)(cid:19)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)#(cid:10)(cid:18)#(cid:23)(cid:9)(cid:14)(cid:9)(cid:7)(cid:23)(cid:6)(cid:12)(cid:20)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?%*=+ © 2007 Microchip Technology Inc. DS41268D-page 109

PIC12F510/16F506 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)"(cid:24)(cid:6)(cid:10)(cid:10)(cid:8)#(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)"(cid:30)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)$$(cid:26)%&(cid:8)(cid:22)’((cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)"#(cid:17))(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) DS41268D-page 110 © 2007 Microchip Technology Inc.

PIC12F510/16F506 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:8)*(cid:10)(cid:6)(cid:12)&(cid:8)(cid:30)(cid:26)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)+(cid:6),(cid:5)(cid:8)(cid:19)-)(cid:20)(cid:8)(cid:21)(cid:8)./(cid:22)/(cid:23)’((cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)(cid:15)*(cid:30)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 1(cid:6)(cid:5)(cid:17)(cid:9) $2552$"-">(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 8 (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) %(cid:3)*%(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)4(cid:14)(cid:5)(cid:30)(cid:26)(cid:17) ( %(cid:3)8% %(cid:3):% (cid:2)(cid:3)%% (cid:29)(cid:17)(cid:11)(cid:6)(cid:13)(cid:23)(cid:16)(cid:16)(cid:7) ((cid:2) %(cid:3)%% %(cid:3)%(cid:27) %(cid:3)%* (cid:31)(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ( %(cid:3)(cid:27)%(cid:7)>". 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! (cid:27)(cid:3)%%(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) " (cid:3)%%(cid:7)+(cid:29)(cid:31) "(cid:15)#(cid:23)(cid:9)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:13)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) !(cid:27) (cid:2)(cid:3) % 9 (cid:2)(cid:3)=* "(cid:15)#(cid:23)(cid:9)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) "(cid:27) (cid:2)(cid:3)*% 9 (cid:2)(cid:3):% (cid:31)(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) %(cid:3)(cid:2)8 %(cid:3)(cid:27)* %(cid:3) % (cid:31)(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) 5 %(cid:3) % %(cid:3)’% %(cid:3)*% (cid:31)(cid:23)(cid:6)(cid:17)(cid:11)(cid:24)(cid:17)?(cid:17)(cid:23)?"(cid:15)#(cid:23)(cid:9)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:13) C %(cid:3)(cid:27)% 9 9 (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:26)(cid:11)(cid:8)(cid:14)(cid:7)(cid:23)(cid:6)(cid:14)(cid:7)(cid:23)(cid:18)(cid:7)(cid:19)(cid:23)(cid:18)(cid:14)(cid:7)(cid:14)(cid:15)#(cid:23)(cid:9)(cid:14)(cid:13)(cid:7)(cid:17)(cid:5)(cid:14)(cid:7)(cid:22)(cid:11)(cid:18)(cid:9)(cid:7)(cid:11)(cid:17)(cid:7)(cid:14)(cid:6)(cid:13)(cid:9)(cid:3) (cid:3) (cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:5)(cid:9)(cid:7)(cid:9)(cid:11)(cid:25)(cid:7)(cid:9)(cid:5)(cid:6)(cid:30)(cid:10)(cid:12)(cid:11)(cid:17)(cid:14)(cid:13)(cid:3) ’(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31), +(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) >"., >(cid:14)(cid:16)(cid:14)(cid:18)(cid:14)(cid:6)(cid:24)(cid:14)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:21)(cid:7)(cid:10)(cid:9)(cid:10)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:21)(cid:7)(cid:16)(cid:23)(cid:18)(cid:7)(cid:5)(cid:6)(cid:16)(cid:23)(cid:18)(cid:19)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)#(cid:10)(cid:18)#(cid:23)(cid:9)(cid:14)(cid:9)(cid:7)(cid:23)(cid:6)(cid:12)(cid:20)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?(cid:2)(cid:27) + © 2007 Microchip Technology Inc. DS41268D-page 111

PIC12F510/16F506 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)"(cid:24)(cid:6)(cid:10)(cid:10)(cid:8)#(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)"(cid:4)(cid:20)(cid:8)(cid:21)(cid:8)(cid:30)(cid:6)$$(cid:26)%&(cid:8)(cid:22)’((cid:23)(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)"#(cid:17))(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) D N E E1 NOTE1 1 2 3 e h b α h c φ A A2 A1 L L1 β 1(cid:6)(cid:5)(cid:17)(cid:9) $2552$"-">(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 (cid:2)’ (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) (cid:2)(cid:3)(cid:27)=(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)4(cid:14)(cid:5)(cid:30)(cid:26)(cid:17) ( 9 9 (cid:2)(cid:3)=* $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ((cid:27) (cid:2)(cid:3)(cid:27)* 9 9 (cid:29)(cid:17)(cid:11)(cid:6)(cid:13)(cid:23)(cid:16)(cid:16)(cid:7)(cid:7)(cid:28) ((cid:2) %(cid:3)(cid:2)% 9 %(cid:3)(cid:27)* 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) " <(cid:3)%%(cid:7)+(cid:29)(cid:31) $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) (cid:3):%(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! 8(cid:3)<*(cid:7)+(cid:29)(cid:31) (cid:31)(cid:26)(cid:11)(cid:19)(cid:16)(cid:14)(cid:18)(cid:7)@(cid:23)#(cid:17)(cid:5)(cid:23)(cid:6)(cid:11)(cid:12)A (cid:26) %(cid:3)(cid:27)* 9 %(cid:3)*% .(cid:23)(cid:23)(cid:17)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) 5 %(cid:3)’% 9 (cid:2)(cid:3)(cid:27)= .(cid:23)(cid:23)(cid:17)#(cid:18)(cid:5)(cid:6)(cid:17) 5(cid:2) (cid:2)(cid:3)%’(cid:7)>". .(cid:23)(cid:23)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14) (cid:2) %B 9 8B 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) %(cid:3)(cid:2)= 9 %(cid:3)(cid:27)* 5(cid:14)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) %(cid:3) (cid:2) 9 %(cid:3)*(cid:2) $(cid:23)(cid:12)(cid:13)(cid:7)!(cid:18)(cid:11)(cid:16)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14)(cid:7)-(cid:23)# (cid:3) *B 9 (cid:2)*B $(cid:23)(cid:12)(cid:13)(cid:7)!(cid:18)(cid:11)(cid:16)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14)(cid:7)+(cid:23)(cid:17)(cid:17)(cid:23)(cid:19) (cid:4) *B 9 (cid:2)*B (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) (cid:28)(cid:7)(cid:29)(cid:5)(cid:30)(cid:6)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:6)(cid:17)(cid:7)(cid:31)(cid:26)(cid:11)(cid:18)(cid:11)(cid:24)(cid:17)(cid:14)(cid:18)(cid:5)(cid:9)(cid:17)(cid:5)(cid:24)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)%(cid:3)(cid:2)*(cid:7)(cid:19)(cid:19)(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) ’(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31), +(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) >"., >(cid:14)(cid:16)(cid:14)(cid:18)(cid:14)(cid:6)(cid:24)(cid:14)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:21)(cid:7)(cid:10)(cid:9)(cid:10)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:21)(cid:7)(cid:16)(cid:23)(cid:18)(cid:7)(cid:5)(cid:6)(cid:16)(cid:23)(cid:18)(cid:19)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)#(cid:10)(cid:18)#(cid:23)(cid:9)(cid:14)(cid:9)(cid:7)(cid:23)(cid:6)(cid:12)(cid:20)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?%<*+ DS41268D-page 112 © 2007 Microchip Technology Inc.

PIC12F510/16F506 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)-(cid:13)(cid:14)$(cid:26)(cid:8)"(cid:24)(cid:6)(cid:10)(cid:10)(cid:8)#(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:9)(cid:6)(cid:14)+(cid:6),(cid:5)(cid:8)(cid:19)-"(cid:20)(cid:8)(cid:28)-"#(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) D N E E1 NOTE1 1 2 e b c A A2 φ A1 L1 L 1(cid:6)(cid:5)(cid:17)(cid:9) $2552$"-">(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 8 (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) %(cid:3)<*(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)4(cid:14)(cid:5)(cid:30)(cid:26)(cid:17) ( 9 9 (cid:2)(cid:3)(cid:2)% $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ((cid:27) %(cid:3)=* %(cid:3)8* %(cid:3):* (cid:29)(cid:17)(cid:11)(cid:6)(cid:13)(cid:23)(cid:16)(cid:16)(cid:7) ((cid:2) %(cid:3)%% 9 %(cid:3)(cid:2)* 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) " ’(cid:3):%(cid:7)+(cid:29)(cid:31) $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) (cid:3)%%(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! (cid:3)%%(cid:7)+(cid:29)(cid:31) .(cid:23)(cid:23)(cid:17)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) 5 %(cid:3)’% %(cid:3)<% %(cid:3)8% .(cid:23)(cid:23)(cid:17)#(cid:18)(cid:5)(cid:6)(cid:17) 5(cid:2) %(cid:3):*(cid:7)>". .(cid:23)(cid:23)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14) (cid:2) %B 9 8B 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) %(cid:3)%8 9 %(cid:3)(cid:27) 5(cid:14)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) %(cid:3)(cid:27)(cid:27) 9 %(cid:3)’% (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)%(cid:3)(cid:2)*(cid:7)(cid:19)(cid:19)(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31), +(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) >"., >(cid:14)(cid:16)(cid:14)(cid:18)(cid:14)(cid:6)(cid:24)(cid:14)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:21)(cid:7)(cid:10)(cid:9)(cid:10)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:21)(cid:7)(cid:16)(cid:23)(cid:18)(cid:7)(cid:5)(cid:6)(cid:16)(cid:23)(cid:18)(cid:19)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)#(cid:10)(cid:18)#(cid:23)(cid:9)(cid:14)(cid:9)(cid:7)(cid:23)(cid:6)(cid:12)(cid:20)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?(cid:2)(cid:2)(cid:2)+ © 2007 Microchip Technology Inc. DS41268D-page 113

PIC12F510/16F506 !(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)01(cid:13)(cid:18)(cid:8)"1$(cid:13)(cid:18)+(cid:8)"(cid:24)(cid:6)(cid:10)(cid:10)(cid:8)#(cid:16)(cid:12)(cid:10)(cid:13)(cid:18)(cid:5)(cid:8)(cid:19)"0(cid:20)(cid:8)(cid:21)(cid:8)!’!(cid:8)(cid:24)(cid:24)(cid:8)(cid:25)(cid:26)(cid:7)(cid:27)(cid:8)(cid:28)0""#(cid:9)(cid:29) (cid:30)(cid:26)(cid:12)(cid:5)(cid:31) .(cid:23)(cid:18)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:19)(cid:23)(cid:9)(cid:17)(cid:7)(cid:24)(cid:10)(cid:18)(cid:18)(cid:14)(cid:6)(cid:17)(cid:7)#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)(cid:13)(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:9)(cid:21)(cid:7)#(cid:12)(cid:14)(cid:11)(cid:9)(cid:14)(cid:7)(cid:9)(cid:14)(cid:14)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)$(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30)(cid:7)(cid:29)#(cid:14)(cid:24)(cid:5)(cid:16)(cid:5)(cid:24)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:11)(cid:17)(cid:7) (cid:26)(cid:17)(cid:17)#,00(cid:25)(cid:25)(cid:25)(cid:3)(cid:19)(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#(cid:3)(cid:24)(cid:23)(cid:19)0#(cid:11)(cid:24)/(cid:11)(cid:30)(cid:5)(cid:6)(cid:30) D N E E1 NOTE1 1 2 e b c φ A A2 A1 L1 L 1(cid:6)(cid:5)(cid:17)(cid:9) $2552$"-">(cid:29) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:7)5(cid:5)(cid:19)(cid:5)(cid:17)(cid:9) $23 36$ $(7 3(cid:10)(cid:19)(cid:22)(cid:14)(cid:18)(cid:7)(cid:23)(cid:16)(cid:7)(cid:4)(cid:5)(cid:6)(cid:9) 3 (cid:2)’ (cid:4)(cid:5)(cid:17)(cid:24)(cid:26) (cid:14) %(cid:3)<*(cid:7)+(cid:29)(cid:31) 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7)4(cid:14)(cid:5)(cid:30)(cid:26)(cid:17) ( 9 9 (cid:2)(cid:3)(cid:27)% $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) ((cid:27) %(cid:3)8% (cid:2)(cid:3)%% (cid:2)(cid:3)%* (cid:29)(cid:17)(cid:11)(cid:6)(cid:13)(cid:23)(cid:16)(cid:16)(cid:7) ((cid:2) %(cid:3)%* 9 %(cid:3)(cid:2)* 6(cid:8)(cid:14)(cid:18)(cid:11)(cid:12)(cid:12)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) " <(cid:3)’%(cid:7)+(cid:29)(cid:31) $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) "(cid:2) ’(cid:3) % ’(cid:3)’% ’(cid:3)*% $(cid:23)(cid:12)(cid:13)(cid:14)(cid:13)(cid:7)(cid:4)(cid:11)(cid:24)/(cid:11)(cid:30)(cid:14)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) ! ’(cid:3):% *(cid:3)%% *(cid:3)(cid:2)% .(cid:23)(cid:23)(cid:17)(cid:7)5(cid:14)(cid:6)(cid:30)(cid:17)(cid:26) 5 %(cid:3)’* %(cid:3)<% %(cid:3)=* .(cid:23)(cid:23)(cid:17)#(cid:18)(cid:5)(cid:6)(cid:17) 5(cid:2) (cid:2)(cid:3)%%(cid:7)>". .(cid:23)(cid:23)(cid:17)(cid:7)((cid:6)(cid:30)(cid:12)(cid:14) (cid:2) %B 9 8B 5(cid:14)(cid:11)(cid:13)(cid:7)-(cid:26)(cid:5)(cid:24)/(cid:6)(cid:14)(cid:9)(cid:9) (cid:24) %(cid:3)%: 9 %(cid:3)(cid:27)% 5(cid:14)(cid:11)(cid:13)(cid:7);(cid:5)(cid:13)(cid:17)(cid:26) (cid:22) %(cid:3)(cid:2): 9 %(cid:3) % (cid:30)(cid:26)(cid:12)(cid:5)(cid:11)(cid:31) (cid:2)(cid:3) (cid:4)(cid:5)(cid:6)(cid:7)(cid:2)(cid:7)(cid:8)(cid:5)(cid:9)(cid:10)(cid:11)(cid:12)(cid:7)(cid:5)(cid:6)(cid:13)(cid:14)(cid:15)(cid:7)(cid:16)(cid:14)(cid:11)(cid:17)(cid:10)(cid:18)(cid:14)(cid:7)(cid:19)(cid:11)(cid:20)(cid:7)(cid:8)(cid:11)(cid:18)(cid:20)(cid:21)(cid:7)(cid:22)(cid:10)(cid:17)(cid:7)(cid:19)(cid:10)(cid:9)(cid:17)(cid:7)(cid:22)(cid:14)(cid:7)(cid:12)(cid:23)(cid:24)(cid:11)(cid:17)(cid:14)(cid:13)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:5)(cid:6)(cid:7)(cid:17)(cid:26)(cid:14)(cid:7)(cid:26)(cid:11)(cid:17)(cid:24)(cid:26)(cid:14)(cid:13)(cid:7)(cid:11)(cid:18)(cid:14)(cid:11)(cid:3) (cid:27)(cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)!(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)"(cid:2)(cid:7)(cid:13)(cid:23)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:5)(cid:6)(cid:24)(cid:12)(cid:10)(cid:13)(cid:14)(cid:7)(cid:19)(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:3)(cid:7)$(cid:23)(cid:12)(cid:13)(cid:7)(cid:16)(cid:12)(cid:11)(cid:9)(cid:26)(cid:7)(cid:23)(cid:18)(cid:7)#(cid:18)(cid:23)(cid:17)(cid:18)(cid:10)(cid:9)(cid:5)(cid:23)(cid:6)(cid:9)(cid:7)(cid:9)(cid:26)(cid:11)(cid:12)(cid:12)(cid:7)(cid:6)(cid:23)(cid:17)(cid:7)(cid:14)(cid:15)(cid:24)(cid:14)(cid:14)(cid:13)(cid:7)%(cid:3)(cid:2)*(cid:7)(cid:19)(cid:19)(cid:7)#(cid:14)(cid:18)(cid:7)(cid:9)(cid:5)(cid:13)(cid:14)(cid:3) (cid:3) !(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:5)(cid:6)(cid:30)(cid:7)(cid:11)(cid:6)(cid:13)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:5)(cid:6)(cid:30)(cid:7)#(cid:14)(cid:18)(cid:7)((cid:29)$"(cid:7))(cid:2)’(cid:3)*$(cid:3) +(cid:29)(cid:31), +(cid:11)(cid:9)(cid:5)(cid:24)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:3)(cid:7)-(cid:26)(cid:14)(cid:23)(cid:18)(cid:14)(cid:17)(cid:5)(cid:24)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:14)(cid:15)(cid:11)(cid:24)(cid:17)(cid:7)(cid:8)(cid:11)(cid:12)(cid:10)(cid:14)(cid:7)(cid:9)(cid:26)(cid:23)(cid:25)(cid:6)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:9)(cid:3) >"., >(cid:14)(cid:16)(cid:14)(cid:18)(cid:14)(cid:6)(cid:24)(cid:14)(cid:7)!(cid:5)(cid:19)(cid:14)(cid:6)(cid:9)(cid:5)(cid:23)(cid:6)(cid:21)(cid:7)(cid:10)(cid:9)(cid:10)(cid:11)(cid:12)(cid:12)(cid:20)(cid:7)(cid:25)(cid:5)(cid:17)(cid:26)(cid:23)(cid:10)(cid:17)(cid:7)(cid:17)(cid:23)(cid:12)(cid:14)(cid:18)(cid:11)(cid:6)(cid:24)(cid:14)(cid:21)(cid:7)(cid:16)(cid:23)(cid:18)(cid:7)(cid:5)(cid:6)(cid:16)(cid:23)(cid:18)(cid:19)(cid:11)(cid:17)(cid:5)(cid:23)(cid:6)(cid:7)#(cid:10)(cid:18)#(cid:23)(cid:9)(cid:14)(cid:9)(cid:7)(cid:23)(cid:6)(cid:12)(cid:20)(cid:3) $(cid:5)(cid:24)(cid:18)(cid:23)(cid:24)(cid:26)(cid:5)#-(cid:14)(cid:24)(cid:26)(cid:6)(cid:23)(cid:12)(cid:23)(cid:30)(cid:20)!(cid:18)(cid:11)(cid:25)(cid:5)(cid:6)(cid:30)(cid:31)%’?%8=+ DS41268D-page 114 © 2007 Microchip Technology Inc.

PIC12F510/16F506 APPENDIX A: REVISION HISTORY Revision A Original release. Revision B Page 3 – Special Microcontroller Features and Low- Power Features sections. PIC12F510 Pin Diagram. Section 3.0 – Figure 3-1, Figure 3-2, Table 3-2, Table 3-3. Section 4.0 – First paragraph, Section 4.2 - Figure references, Tables 4-1 and 4-2 (Note 1). Section 5.0 – Table 5-2, Table 5-6 Title. Section 6.0 Section 7.0 – First paragraph, Section 7.7, Register 7-1, Register 7-2, Register 7-3, Figure 7-1, Figure 7-2, Sections 7.4 through 7.7, Table 7-1. Section 8.0 – Sections 8.0 through 8.2, Figure 8-1, Table 8-1. Section 9.0 – Table 9-2, Register 9-1, Register 9-2, Table 9-3. Section 10.0 – Registers 10-1 and 10-2 (Note 1), Table 10-2 (Note 2), Section 10.2.5, Section 10.3, Table 10-3, Table 10-4, Table 10-5, Section 10.4, Section 10.5, Section 10.6.1, Section 10.9, 10.9.1, 10.9.2, Section 10.11. Section 13.0 – 13.1 DC Characteristics, 13.2 DC Characteristics, Table 13-1, Table 13-3, Table 13-4. Revision C (03/2007) Revised Table 3-2 GP3 and Legend; Revised Table 3- 3 RB3 and Legend; Updated Registers to new format; Revised Section 9.1; Revised Table 9-2; Revised 13.1 DC Characteristics D025; Revised Table 13-2 and Table 13-3 and Notes; Replaced Package Drawings (Rev. AN); Added DFN package; Replaced Develop- ment Support Section; Revised Product ID System. Revision D (11/2007) Revised Table 1-1; Table 4-1, Table 4-2; Figure 4-5; Register 7-1 (Note 1); Register 8-1; Figure 13-4; 13.1 - 13.3; Table 13-1, Table 13-3, Table 13-6, Table 13-7, Table 13-9; Figure 14-4, Figure 14-14; Section 14.0; Packaging; Product ID System. © 2007 Microchip Technology Inc. DS41268D-page 115

PIC12F510/16F506 NOTES: DS41268D-page 116 © 2007 Microchip Technology Inc.

PIC12F510/16F506 INDEX A M ALU.......................................................................................9 Memory Organization.........................................................15 Assembler Data Memory..............................................................16 MPASM Assembler.....................................................80 Program Memory (PIC12F510/16F506).....................15 Microchip Internet Web Site..............................................108 B MPLAB ASM30 Assembler, Linker, Librarian.....................80 Block Diagram MPLAB ICD 2 In-Circuit Debugger.....................................81 Comparator for the PIC12F510...................................46 MPLAB ICE 2000 High-Performance Universal Comparator for the PIC16F506...................................46 In-Circuit Emulator......................................................81 On-Chip Reset Circuit.................................................64 MPLAB ICE 4000 High-Performance Universal Timer0.........................................................................39 In-Circuit Emulator......................................................81 TMR0/WDT Prescaler.................................................42 MPLAB Integrated Development Environment Software....79 Watchdog Timer..........................................................67 MPLAB PM3 Device Programmer......................................81 Brown-Out Protection Circuit..............................................68 MPLINK Object Linker/MPLIB Object Librarian..................80 C O C Compilers OPTION Register................................................................20 MPLAB C18................................................................80 OSC Selection....................................................................55 MPLAB C30................................................................80 OSCCAL Register...............................................................22 Carry.....................................................................................9 Oscillator Configurations.....................................................58 Clocking Scheme................................................................14 Oscillator Types Code Protection............................................................55, 69 HS...............................................................................58 Configuration Bits................................................................55 LP...............................................................................58 Configuration Word (PIC12F510).......................................56 RC..............................................................................58 Configuration Word (PIC16F506).......................................57 XT...............................................................................58 Customer Change Notification Service.............................108 P Customer Notification Service...........................................108 Customer Support.............................................................108 PIC12F510/16F506 Device Varieties...................................7 PICSTART Plus Development Programmer.......................82 D POR DC.......................................................................................88 Device Reset Timer (DRT)...................................55, 66 DC Characteristics (Extended)...........................................87 PD...............................................................................68 DC Characteristics (Industrial)............................................86 Power-on Reset (POR)...............................................55 DC Characteristics (Industrial, Extended)...........................88 TO...............................................................................68 Development Support.........................................................79 PORTB...............................................................................27 Digit Carry.............................................................................9 Power-down Mode..............................................................69 Prescaler............................................................................41 E Program Counter................................................................23 Errata....................................................................................3 Q F Q cycles..............................................................................14 Family of Devices R PIC12F510/16F506.......................................................5 FSR.....................................................................................24 RC Oscillator.......................................................................59 Reader Response.............................................................109 I Read-Modify-Write..............................................................37 I/O Interfacing.....................................................................27 Register File Map I/O Ports..............................................................................27 PIC12F510.................................................................16 I/O Programming Considerations........................................37 PIC16F506.................................................................16 ID Locations..................................................................55, 69 Registers INDF....................................................................................24 Special Function.........................................................17 Indirect Data Addressing.....................................................24 Reset..................................................................................55 Instruction Cycle.................................................................14 Reset on Brown-Out...........................................................68 Instruction Flow/Pipelining..................................................14 S Instruction Set Summary.....................................................72 Internet Address................................................................108 Sleep............................................................................55, 69 Software Simulator (MPLAB SIM)......................................80 L Special Features of the CPU..............................................55 Loading of PC.....................................................................23 Special Function Registers.................................................17 Stack...................................................................................23 STATUS Register.....................................................9, 18, 51 © 2007 Microchip Technology Inc. DS41268D-page 117

PIC12F510/16F506 T Timer0 Timer0.........................................................................39 Timer0 (TMR0) Module...............................................39 TMR0 with External Clock...........................................41 Timing Diagrams and Specifications...................................91 Timing Parameter Symbology and Load Conditions...........91 TRIS Registers....................................................................27 W Wake-up from Sleep...........................................................69 Watchdog Timer (WDT)................................................55, 66 Period..........................................................................66 Programming Considerations.....................................66 WWW Address..................................................................108 WWW, On-Line Support........................................................3 Z Zero bit..................................................................................9 DS41268D-page 118 © 2007 Microchip Technology Inc.

PIC12F510/16F506 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://support.microchip.com • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. DS41268D-page 119

PIC12F510/16F506 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC12F510/16F506 Literature Number: DS41268D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41268D-page 120 © 2007 Microchip Technology Inc.

PIC12F510/16F506 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC16F506-E/P 301 = Extended Temp., PDIP Range package, QTP pattern #301 b) PIC16F506-I/SN = Industrial Temp., SOIC package c) PIC16F506T-E/P = Extended Temp., PDIP Device: PIC16F506 package, Tape and Reel PIC12F510 PIC16F506T(1) PIC12F510T(2) VDD range 2.0V to 5.5V Temperature I = -40°C to +85°C (Industrial) Range: E = -40°C to +125°C (Extended) Package: MC = 8L DFN 2x3 (DUAL Flatpack No-Leads)(3, 4) MS = Micro-Small Outline Package (MSOP)(3, 4) Note1: T = in tape and reel SOIC and TSSOP PSL == 1P4laLs Sticm (aPllD OIPu)t(l4in)e, 3.90 mm (SOIC)(4) packages only SN = 8L Small Outline, 3.90 mm Narrow (SOIC)(4) 2: T = in tape and reel SOIC and MSOP ST = Thin Shrink Small Outline (TSSOP)(4) packages only. 3: PIC12F510 only. 4: Pb-free. Pattern: QTP, SQTP Code or Special Requirements (blank otherwise) © 2007 Microchip Technology Inc. DS41268D-page 121

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