PIC12(L)F1840 8-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU Extreme Low-Power Management with PIC12LF1840 XLP • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Sleep mode: 20 nA @ 1.8V, typical • Operating Speed: • Watchdog Timer: 500 nA @ 1.8V, typical - DC – 32MHz oscillator/clock input • Timer1 Oscillator: 300 nA @ 32 kHz, 1.8V, typical - DC – 125ns instruction cycle • Operating Current: 30A/MHz @ 1.8V, typical • Interrupt Capability with Automatic Context Saving Analog Features • 16-Level Deep Hardware Stack with Optional • Analog-to-Digital Converter (ADC) module: Overflow/Underflow Reset - 10-bit resolution, 4 channels • Direct, Indirect and Relative Addressing modes: - Conversion available during Sleep - Two full 16-bit File Select Registers (FSRs) • Analog Comparator module: - FSRs can read program and data memory - One rail-to-rail analog comparator Flexible Oscillator Structure - Power mode control - Software controllable hysteresis • Precision 32MHz Internal Oscillator Block: • Voltage Reference module: - Factory calibrated to ± 1%, typical - Fixed Voltage Reference (FVR) with 1.024V, - Software selectable frequencies range of 2.048V and 4.096V output levels 31kHz to 32MHz - 5-bit rail-to-rail resistive DAC with positive • 31 kHz Low-Power Internal Oscillator and negative reference selection • Four Crystal modes up to 32MHz • Three External Clock modes up to 32MHz Peripheral Highlights • 4X Phase Lock Loop (PLL) • 5 I/O Pins and 1 Input-Only Pin: • Fail-Safe Clock Monitor: - High current sink/source 25mA/25mA - Allows for safe shutdown if peripheral clock - Programmable weak pull-ups stops - Programmable interrupt-on-change pins • Two-Speed Oscillator Start-up • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler • Reference Clock module: • Enhanced Timer1: - Programmable clock output frequency and - 16-bit timer/counter with prescaler duty-cycle - External Gate Input mode Special Microcontroller Features - Dedicated, low-power 32 kHz oscillator driver • Timer2: 8-Bit Timer/Counter with 8-Bit Period • Operating Voltage Range: Register, Prescaler and Postscaler - 2.3V-5.5V (PIC12F1840) • Enhanced CCP (ECCP) module: - 1.8V-3.6V (PIC12LF1840) - Software selectable time bases • Self-Reprogrammable under Software Control - Auto-shutdown and auto-restart • Power-on Reset (POR), Power-up Timer (PWRT) - PWM steering and Oscillator Start-up Timer (OST) • Master Synchronous Serial Port (MSSP) with SPI • Programmable Brown-out Reset (BOR) and I2CTM with: • Extended Watchdog Timer (WDT) - 7-bit address masking • In-Circuit Serial Programming™ (ICSP™) via - SMBus/PMBusTM compatibility Two Pins • Enhanced Universal Synchronous Asynchronous • In-Circuit Debug (ICD) via Two Pins Receiver Transmitter (EUSART) module: • Enhanced Low-Voltage Programming (LVP) - RS-232, RS-485 and LIN compatible • Programmable Code Protection - Auto-Baud Detect • Power-Saving Sleep mode • Capacitive Sensing (CPS) module (mTouchTM): - 4 input channels  2011-2015 Microchip Technology Inc. DS40001441F-page 1

PIC12(L)F1840 Peripheral Features (Continued) • Data Signal Modulator module: - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications PIC12(L)F1822/1840/PIC16(L)F182X/1847 Family Types Device Data Sheet Index Program MemoryFlash (words) Data EEPROM(bytes) Data SRAM(bytes) (2)I/O’s 10-bit ADC (ch) CapSense (ch) Comparators Timers(8/16-bit) EUSART 2MSSP (IC™/SPI) CCP (Full-Bridge)CCP (Half-Bridge)CCP SR Latch (1)Debug XLP EE PIC12(L)F1822 (1) 2K 256 128 6 4 4 1 2/1 1 1 0/1/0 Y I/H Y PIC12(L)F1840 (2) 4K 256 256 6 4 4 1 2/1 1 1 0/1/0 Y I/H Y PIC16(L)F1823 (1) 2K 256 128 12 8 8 2 2/1 1 1 1/0/0 Y I/H Y PIC16(L)F1824 (3) 4K 256 256 12 8 8 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1825 (4) 8K 256 1024 12 8 8 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1826 (5) 2K 256 256 16 12 12 2 2/1 1 1 1/0/0 Y I/H Y PIC16(L)F1827 (5) 4K 256 384 16 12 12 2 4/1 1 2 1/1/2 Y I/H Y PIC16(L)F1828 (3) 4K 256 256 18 12 12 2 4/1 1 1 1/1/2 Y I/H Y PIC16(L)F1829 (4) 8K 256 1024 18 12 12 2 4/1 1 2 1/1/2 Y I/H Y PIC16(L)F1847 (6) 8K 256 1024 16 12 12 2 4/1 1 2 1/1/2 Y I/H Y Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS41413 PIC12(L)F1822/PIC16(L)F1823 Data Sheet, 8/14-Pin Flash Microcontrollers. 2: DS41441 PIC12(L)F1840 Data Sheet, 8-Pin Flash Microcontrollers. 3: DS41419 PIC16(L)F1824/1828 Data Sheet, 28/40/44-Pin Flash Microcontrollers. 4: DS41440 PIC16(L)F1825/1829 Data Sheet, 14/20-Pin Flash Microcontrollers. 5: DS41391 PIC16(L)F1826/1827 Data Sheet, 18/20/28-Pin Flash Microcontrollers. 6: DS41453 PIC16(L)F1847 Data Sheet, 18/20/28-Pin Flash Microcontrollers. Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001441F-page 2  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 1: 8-PIN DIAGRAM FOR PIC12(L)F1840 PDIP, SOIC, DFN, UDFN VDD 1 P 8 VSS IC RA5 2 12 7 RA0/ICSPDAT (L RA4 3 )F 6 RA1/ICSPCLK 1 MCLR/VPP/RA3 4 84 5 RA2 0 Note 1: See Table1 for the location of all peripheral functions. TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1840) N F D U N/ I/O DIP/SOIC/DF ADC Reference Cap Sense Comparator SR Latch Timers ECCP EUSART MSSP Interrupt Modulator Pull-up Basic P n Pi 8- RA0 7 AN0 DACOUT CPS0 C1IN+ — — P1B TX SDO IOC MDOUT Y ICSPDAT CK SS(1) ICDDAT RA1 6 AN1 VREF CPS1 C1IN0- SRI — — RX SCL IOC MDMIN Y ICSPCLK DT SCK ICPCLK RA2 5 AN2 — CPS2 C1OUT SRQ T0CKI CCP1 — SDA INT/ MDCIN1 Y — P1A SDI IOC FLT0 RA3 4 — — — — — T1G(1) — — SS IOC — Y MCLR VPP RA4 3 AN3 — CPS3 C1IN1- — T1G P1B(1) TX(1) SDO(1) IOC MDCIN2 Y OSC2 T1OSO CK(1) CLKOUT CLKR RA5 2 — — — — SRNQ T1CKI CCP1(1) RX(1) — IOC — Y OSC1 T1OSI P1A(1) DT(1) CLKIN VDD 1 — — — — — — — — — — — — VDD VSS 8 — — — — — — — — — — — — VSS Note 1: Alternate pin function selected with the APFCON (Register12-1) register.  2011-2015 Microchip Technology Inc. DS40001441F-page 3

PIC12(L)F1840 Table of Contents 1.0 Device Overview..........................................................................................................................................................................6 2.0 Enhanced Mid-range CPU.........................................................................................................................................................10 3.0 Memory Organization.................................................................................................................................................................12 4.0 Device Configuration..................................................................................................................................................................32 5.0 Oscillator Module (with Fail-Safe Clock Monitor).......................................................................................................................38 6.0 Reference Clock Module............................................................................................................................................................56 7.0 Resets........................................................................................................................................................................................59 8.0 Interrupts....................................................................................................................................................................................67 9.0 Power-Down Mode (Sleep)........................................................................................................................................................77 10.0 Watchdog Timer (WDT).............................................................................................................................................................81 11.0 Data EEPROM and Flash Program Memory Control.................................................................................................................85 12.0 I/O Ports.....................................................................................................................................................................................98 13.0 Interrupt-on-Change.................................................................................................................................................................105 14.0 Fixed Voltage Reference (FVR)...............................................................................................................................................109 15.0 Temperature Indicator Module.................................................................................................................................................112 16.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................114 17.0 Digital-to-Analog Converter (DAC) Module..............................................................................................................................127 18.0 SR Latch...................................................................................................................................................................................131 19.0 Comparator Module..................................................................................................................................................................135 20.0 Timer0 Module.........................................................................................................................................................................143 21.0 Timer1 Module with Gate Control.............................................................................................................................................146 22.0 Timer2 Module.........................................................................................................................................................................157 23.0 Data Signal Modulator..............................................................................................................................................................161 24.0 Capture/Compare/PWM Modules............................................................................................................................................171 25.0 Master Synchronous Serial Port Module..................................................................................................................................192 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................247 27.0 Capacitive Sensing (CPS) Module...........................................................................................................................................276 28.0 In-Circuit Serial Programming™ (ICSP™)...............................................................................................................................284 29.0 Instruction Set Summary..........................................................................................................................................................288 30.0 Electrical Specifications............................................................................................................................................................302 31.0 DC and AC Characteristics Graphs and Charts.......................................................................................................................339 32.0 Development Support...............................................................................................................................................................376 33.0 Packaging Information..............................................................................................................................................................380 Appendix A: Data Sheet Revision History..........................................................................................................................................393 Appendix B: Migrating From Other PIC® Devices.............................................................................................................................393 The Microchip Web Site.....................................................................................................................................................................394 Customer Change Notification Service..............................................................................................................................................394 Customer Support..............................................................................................................................................................................394 Product Identification System.............................................................................................................................................................395 DS40001441F-page 4  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2011-2015 Microchip Technology Inc. DS40001441F-page 5

PIC12(L)F1840 1.0 DEVICE OVERVIEW The PIC12(L)F1840 are described within this data sheet. They are available in 8-pin packages. Figure1-1 shows a block diagram of the PIC12(L)F1840 devices. Table1-2 shows the pinout descriptions. Reference Table1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY 0 4 8 1 F Peripheral L) ( 2 1 C PI ADC ● Capacitive Sensing (CPS) Module ● Data EEPROM ● Digital-to-Analog Converter (DAC) ● Digital Signal Modulator (DSM) ● EUSART ● Fixed Voltage Reference (FVR) ● SR Latch ● Capture/Compare/PWM Modules ECCP1 ● Comparators C1 ● Master Synchronous Serial Ports MSSP ● Timers Timer0 ● Timer1 ● Timer2 ● DS40001441F-page 6  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 1-1: PIC12(L)F1840 BLOCK DIAGRAM Program Flash Memory RAM EEPROM CLKR Clock Reference OSC2/CLKOUT Timing Generation PORTA OSC1/CLKIN CPU INTRC Oscillator (Figure2-1) MCLR SR ADC Timer0 Timer1 DAC Comparators Latch 10-Bit ECCP1 MSSP Modulator EUSART FVR CapSense Note 1: See applicable chapters for more information on peripherals. 2: See Table1-1 for peripherals available on specific devices.  2011-2015 Microchip Technology Inc. DS40001441F-page 7

PIC12(L)F1840 TABLE 1-2: PIC12(L)F1840 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/CPS0/C1IN+/ RA0 TTL CMOS General purpose I/O. DACOUT/TX/CK/SDO/ AN0 AN — ADC Channel 0 input. SS(1)/P1B/MDOUT/ICSPDAT/ CPS0 AN — Capacitive sensing input 0. ICDDAT C1IN+ AN — Comparator C1 positive input. DACOUT — AN Digital-to-Analog Converter output. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. SDO — CMOS SPI data output. SS ST — Slave Select input. P1B — CMOS PWM output. MDOUT — CMOS Modulator output. ICSPDAT ST CMOS ICSP™ Data I/O. RA1/AN1/CPS1/VREF/C1IN0-/ RA1 TTL CMOS General purpose I/O. SRI/RX/DT/SCL/SCK/ AN1 AN — ADC Channel 1 input. MDMIN/ICSPCLK/ICDCLK CPS1 AN — Capacitive sensing input 1. VREF AN — ADC and DAC Positive Voltage Reference input. C1IN0- AN — Comparator C1 negative input. SRI ST — SR Latch input. RX ST — USART asynchronous input. DT ST CMOS USART synchronous data. SCL I2C™ OD I2C™ clock. SCK ST CMOS SPI clock. MDMIN ST — Modulator source input. ICSPCLK ST — Serial Programming Clock. RA2/AN2/CPS2/C1OUT/SRQ/ RA2 ST CMOS General purpose I/O. T0CKI/CCP1/P1A/FLT0/ AN2 AN — ADC Channel 2 input. SDA/SDI/INT/MDCIN1 CPS2 AN — Capacitive sensing input 2. C1OUT — CMOS Comparator C1 output. SRQ — CMOS SR Latch non-inverting output. T0CKI ST — Timer0 clock input. CCP1 ST CMOS Capture/Compare/PWM 1. P1A — CMOS PWM output. FLT0 ST — ECCP Auto-Shutdown Fault input. SDA I2C™ OD I2C™ data input/output. SDI CMOS — SPI data input. INT ST — External interrupt. MDCIN1 ST — Modulator Carrier Input 1. RA3/SS/T1G(1)/VPP/MCLR RA3 TTL — General purpose input. SS ST — Slave Select input. T1G ST — Timer1 Gate input. VPP HV — Programming voltage. MCLR ST — Master Clear with internal pull-up. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Alternate pin function selected with the APFCON (Register12-1) register. DS40001441F-page 8  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 1-2: PIC12(L)F1840 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RA4/AN3/CPS3/OSC2/ RA4 TTL CMOS General purpose I/O. CLKOUT/T1OSO/C1IN1-/CLKR/ AN3 AN — ADC Channel 3 input. SDO(1)/CK(1)/TX(1)/P1B(1)/ CPS3 AN — Capacitive sensing input 3. T1G/MDCIN2 OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. T1OSO XTAL XTAL Timer1 oscillator connection. C1IN1- AN — Comparator C1 negative input. CLKR — CMOS Clock Reference output. SDO — CMOS SPI data output. CK ST CMOS USART synchronous clock. TX — CMOS USART asynchronous transmit. P1B — CMOS PWM output. T1G ST — Timer1 Gate input. MDCIN2 ST — Modulator Carrier Input 2. RA5/CLKIN/OSC1/T1OSI/ RA5 TTL CMOS General purpose I/O. T1CKI/SRNQ/P1A(1)/CCP1(1)/ CLKIN CMOS — External clock input (EC mode). DT(1)/RX(1) OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). T1OSI XTAL XTAL Timer1 oscillator connection. T1CKI ST — Timer1 clock input. SRNQ — CMOS SR Latch inverting output. P1A — CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM 1. DT ST CMOS USART synchronous data. RX ST — USART asynchronous input. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™= Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Alternate pin function selected with the APFCON (Register12-1) register.  2011-2015 Microchip Technology Inc. DS40001441F-page 9

PIC12(L)F1840 2.0 ENHANCED MID-RANGE CPU Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read This family of devices contain an enhanced mid-range program and data memory. 8-bit CPU core. The CPU has 49 instructions. Interrupt • Automatic Interrupt Context Saving capability includes automatic context saving. The • 16-level Stack with Overflow and Underflow hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and • File Select Registers • Instruction Set FIGURE 2-1: CORE BLOCK DIAGRAM 15 CCCooonnnfffiiiggguuurrraaatttiiiooonnn 15 888 DDDaaatttaaa BBBuuusss PPPrrrooogggrrraaammm CCCooouuunnnttteeerrr Flash X U Program M Memory 1886 -LLLeeevvveeell lSS Sttaataccckkk RAM (((111335---bbbiiittt))) PPPrrrooogggrrraaammm 111444 Program Memory 12 RAM Addr BBBuuusss Read (PMR) AAAddddddrrr MMMUUUXXX IIInnnssstttrrruuuccctttiiiooonnn Rrreeeggg Indirect DDDiiirrreeecccttt AAAddddddrrr 777 Addr 5 12 12 15 BFFSSSRRR Rrreeeggg FFFSSSRRR 0rr eeRggeg FFFSSSRRR1 rrReeeggg 15 SSSTTTAAATTTUUUSSS Rrreeeggg 888 333 MMMUUUXXX Power-up Timer IIInnnssstttrrruuuccctttiiiooonnn Oscillator DDDeeecccooodddeee a &&nd Start-up Timer AAALLLUUU CCCooonnntttrrrooolll Power-on OSC1/CLKIN Reset 888 TTTiiimmmiiinnnggg Watchdog OSC2/CLKOUT GGGeeennneeerrraaatttiiiooonnn Timer W Reg Brown-out Reset IIInnnttteeerrrnnnaaalll OOOsssccciiillllllaaatttooorrr BBBllloooccckkk VVVDDDDDD VVVSSSSSS DS40001441F-page 10  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section8.5 “Automatic Context Saving”, for more information. 2.2 16-level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Under- flow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a soft- ware Reset. See Section3.5 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section3.6 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section29.0 “Instruction Set Summary” for more details.  2011-2015 Microchip Technology Inc. DS40001441F-page 11

PIC12(L)F1840 3.0 MEMORY ORGANIZATION The following features are associated with access and control of program memory and data memory: These devices contain the following types of memory: • PCL and PCLATH • Program Memory • Stack - Configuration Words • Indirect Addressing - Device ID - User ID 3.1 Program Memory Organization - Flash Program Memory The enhanced mid-range core has a 15-bit program • Data Memory counter capable of addressing a 32K x 14 program - Core Registers memory space. Table3-1 shows the memory sizes - Special Function Registers implemented for the PIC12(L)F1840 family. Accessing a - General Purpose RAM location above these boundaries will cause a - Common RAM wrap-around within the implemented memory space. • Data EEPROM memory(1) The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure3-1). Note1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address PIC12(L)F1840 4, 096 0FFFh DS40001441F-page 12  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 3-1: PROGRAM MEMORY MAP 3.1.1 READING PROGRAM MEMORY AS AND STACK FOR DATA PIC12(L)F1840 There are two methods of accessing constants in program memory. The first method is to use tables of PC<14:0> RETLW instructions. The second method is to set an FSR to point to the program memory. CALL, CALLW 15 RETURN, RETLW Interrupt, RETFIE 3.1.1.1 RETLW Instruction Stack Level 0 The RETLW instruction can be used to provide access Stack Level 1 to tables of constants. The recommended way to create such a table is shown in Example3-1. Stack Level 15 EXAMPLE 3-1: RETLW INSTRUCTION constants Reset Vector 0000h BRW ;Add Index in W to ;program counter to ;select data Interrupt Vector 0004h RETLW DATA0 ;Index0 data 0005h RETLW DATA1 ;Index1 data Page 0 RETLW DATA2 On-chip 07FFh RETLW DATA3 Program 0800h Memory Page 1 my_function 0FFFh ;… LOTS OF CODE… 1000h MOVLW DATA_INDEX Rollover to Page 0 call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. Rollover to Page 1 7FFFh  2011-2015 Microchip Technology Inc. DS40001441F-page 13

PIC12(L)F1840 3.1.1.2 Indirect Read with FSR 3.2.1 CORE REGISTERS The program memory can be accessed as data by The core registers contain the registers that directly setting bit 7 of the FSRxH register and reading the affect the basic operation. The core registers occupy matching INDFx register. The MOVIW instruction will the first 12 addresses of every data memory bank place the lower eight bits of the addressed word in the (addresses x00h/x08h through x0Bh/x8Bh). These W register. Writes to the program memory cannot be registers are listed below in Table3-2. For detailed performed via the INDF registers. Instructions that information, see Table3-5. access the program memory via the FSR require one extra instruction cycle to complete. Example3-2 TABLE 3-2: CORE REGISTERS demonstrates accessing the program memory via an FSR. The High directive will set bit<7> if a label points to a Addresses BANKx location in program memory. x00h or x80h INDF0 x01h or x81h INDF1 EXAMPLE 3-2: ACCESSING PROGRAM x02h or x82h PCL MEMORY VIA FSR x03h or x83h STATUS constants x04h or x84h FSR0L RETLW DATA0 ;Index0 data x05h or x85h FSR0H RETLW DATA1 ;Index1 data x06h or x86h FSR1L RETLW DATA2 RETLW DATA3 x07h or x87h FSR1H my_function x08h or x88h BSR ;… LOTS OF CODE… x09h or x89h WREG MOVLW LOW constants x0Ah or x8Ah PCLATH MOVWF FSR1L x0Bh or x8Bh INTCON MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 3.2 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure3-2): • 12 core registers • 20 Special Function Registers (SFR) • Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section3.6 “Indirect Addressing” for more information. DS40001441F-page 14  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 3.2.1.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register3-1, contains: as ‘000u u1uu’ (where u = unchanged). • the arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • the Reset status SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, like any other register. If the STATUS affect any Status bits. For other instructions not register is the destination for an instruction that affects affecting any Status bits (Refer to Section29.0 the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”). disabled. These bits are set or cleared according to the Note1: The C and DC bits operate as Borrow device logic. Furthermore, the TO and PD bits are not and Digit Borrow out bits, respectively, in writable. Therefore, the result of an instruction with the subtraction. STATUS register as destination may be different than intended. 3.3 Register Definitions: Status REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.  2011-2015 Microchip Technology Inc. DS40001441F-page 15

PIC12(L)F1840 3.3.1 SPECIAL FUNCTION REGISTER FIGURE 3-2: BANKED MEMORY PARTITIONING The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function 7-bit Bank Offset Memory Region Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the 00h operation of the peripherals are described in the appro- Core Registers priate peripheral chapter of this data sheet. (12 bytes) 0Bh 3.3.2 GENERAL PURPOSE RAM 0Ch There are up to 80bytes of GPR in each data memory Special Function Registers bank. The Special Function Registers occupy the 20 (20 bytes maximum) bytes after the core registers of every data memory 1Fh bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 20h 3.3.2.1 Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section3.6.2 “Linear Data Memory” for more information. General Purpose RAM (80 bytes maximum) 3.3.3 COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.3.4 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table3-3. DS40001441F-page 16  2011-2015 Microchip Technology Inc.

D TABLE 3-3: PIC12(L)F1840 MEMORY MAP, BANKS 0-7 P S 4 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 0 I 00 000h 080h 100h 180h 200h 280h 300h 380h C 14 Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers 41 (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) 1 F-p 00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh 2 ag 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch — 30Ch — 38Ch — ( e 1 00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh — L 7 00Eh — 08Eh — 10Eh — 18Eh — 20Eh — 28Eh — 30Eh — 38Eh — ) 00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh — F 010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h — 011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h — 391h IOCAP 1 012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h — 392h IOCAN 8 013h — 093h — 113h — 193h EEDATL 213h SSPMASK 293h CCP1CON 313h — 393h IOCAF 014h — 094h — 114h — 194h EEDATH 214h SSPSTAT 294h PWM1CON 314h — 394h — 4 015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSP1CON1 295h CCP1AS 315h — 395h — 0 016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h PSTR1CON 316h — 396h — 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h — 018h T1CON 098h OSCTUNE 118h DACCON0 198h — 218h — 298h — 318h — 398h — 019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h — 299h — 319h — 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah — 29Ah — 31Ah — 39Ah CLKRCON 01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh — 29Bh — 31Bh — 39Bh — 01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch MDCON 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh MDSRC 01Eh CPSCON0 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 31Eh — 39Eh MDCARL 01Fh CPSCON1 09Fh — 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh MDCARH 020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h General General General Purpose Purpose Purpose Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Register Register Register Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 80 Bytes 80 Bytes 80 Bytes 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh 070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h Accesses Accesses Accesses Accesses Accesses Accesses Accesses Common RAM 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh  2 Legend: = Unimplemented data memory locations, read as ‘0’. 01 Note 1: Available only on PIC12F1840. 1 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 3-3: PIC12(L)F1840 MEMORY MAP (CONTINUED) 20 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 1 1 -2 400h 480h 500h 580h 600h 680h 700h 780h 0 Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers 1 5 (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) M ic 40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh ro 40Ch 48Ch 50Ch 58Ch 60Ch 68Ch 70Ch 78Ch c Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented h ip Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ T 46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh e c 470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h h Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM n o (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses logy 47Fh 70h – 7Fh) 4FFh 70h – 7Fh) 57Fh 70h – 7Fh) 5FFh 70h – 7Fh) 67Fh 70h – 7Fh) 6FFh 70h – 7Fh) 77Fh 70h – 7Fh) 7FFh 70h – 7Fh) In c . BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 800h 880h 900h 980h A00h A80h B00h B80h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) 80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh 80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh 870h 8F0h 970h 9F0h A70h AF0h B70h BF0h Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 C00h C80h D00h D80h E00h E80h F00h Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) P C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh I C0Ch C8Ch D0Ch D8Ch E0Ch E8Ch F0Ch C Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 1 C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh 2 C70h CF0h D70h DF0h E70h EF0h F70h Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM ( D (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses L S 4 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 00 C7Fh CFFh D7Fh DFFh E7Fh EFFh F7Fh )F 0 144 Legend: = Unimplemented data memory locations, read as ‘0’ 1 1 F 8 -p a 4 g e 1 0 8

PIC12(L)F1840 TABLE 3-4: PIC12(L)F1840 MEMORY MAP, BANK 31 Bank 31 FA0h Unimplemented Read as ‘0’ FE3h FE4h STATUS_SHAD FE5h WREG_SHAD FE6h BSR_SHAD FE7h PCLATH_SHAD FE8h FSR0L_SHAD FE9h FSR0H_SHAD FEAh FSR1L_SHAD FEBh FSR1H_SHAD FECh — FEDh STKPTR FEEh TOSL FEFh TOSH Legend: = Unimplemented data memory locations, read as ‘0’.  2011-2015 Microchip Technology Inc. DS40001441F-page 19

PIC12(L)F1840 3.3.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table3-5 can be addressed from any Bank. TABLE 3-5: CORE FUNCTION REGISTERS SUMMARY Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR other Resets Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 xxxx xxxx uuuu uuuu x80h (not a physical register) x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory INDF1 xxxx xxxx uuuu uuuu x81h (not a physical register) x02h or PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x82h x03h or STATUS — — — TO PD Z DC C ---1 1000 ---q quuu x83h x04h or FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x84h x05h or FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x85h x06h or FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x86h x07h or FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x87h x08h or BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000 x88h x09h or WREG Working Register 0000 0000 uuuu uuuu x89h x0Ah or PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 x8Ah x0Bh or INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 x8Bh Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. DS40001441F-page 20  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 0 00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx 00Dh to — Unimplemented — — 010h 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 012h PIR2 OSFIF — C1IF EEIF BCL1IF — — — 0-00 0--- 0-00 0--- 013h — Unimplemented — — 014h — Unimplemented — — 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON TMR1CS1 TMR1CS0 T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu DONE 01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000 01Bh PR2 Timer2 Period Register 1111 1111 1111 1111 01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000 01Dh — Unimplemented — — 01Eh CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 00-- 0000 00-- 0000 01Fh CPSCON1 — — — — — — CPSCH<1:0> ---- --00 ---- --00 Bank 1 08Ch TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 08Dh to — Unimplemented — — 090h 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE — C1IE EEIE BCL1IE — — — 0-00 0--- 0-00 0--- 093h — Unimplemented — — 094h — Unimplemented — — 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111 096h PCON STKOVF STKUNF — — RMCLR RI POR BOR 00-- 11qq qq-- qquu 097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110 098h OSCTUNE — — TUN<5:0> --00 0000 --00 0000 099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00 09Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q 09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu 09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000 09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00 09Fh — Unimplemented — — Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC12F1840 only. 3: Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001441F-page 21

PIC12(L)F1840 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 2 10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu 10Dh to — Unimplemented — — 110h 111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100 112h CM1CON1 C1INTP C1INTN C1PCH<1:0> — — — C1NCH 0000 ---0 0000 ---0 113h — Unimplemented — — 114h — Unimplemented — — 115h CMOUT — — — — — — — MC1OUT ---- ---0 ---- ---0 116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000 118h DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — — 000- 00-- 000- 00-- 119h DACCON1 — — — DACR<4:0> ---0 0000 ---0 0000 11Ah SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 11Bh SRCON1 SRSPE SRSCKE Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E 0000 0000 0000 0000 11Ch — Unimplemented — — 11Dh APFCON RXDTSEL SDOSEL SSSEL --- T1GSEL TXCKSEL P1BSEL CCP1SEL 000- 0000 000- 0000 11Eh — Unimplemented — — 11Fh — Unimplemented — — Bank 3 18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 18Dh to — Unimplemented — — 190h 191h EEADRL EEPROM/Program Memory Address Register Low Byte 0000 0000 0000 0000 192h EEADRH —(3) EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000 193h EEDATL EEPROM/Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu 194h EEDATH — — EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu 195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000 196h EECON2 EEPROM control register 2 0000 0000 0000 0000 197h VREGCON(2) — — — — — — VREGPM Reserved ---- --01 ---- --01 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC12F1840 only. 3: Unimplemented, read as ‘1’. DS40001441F-page 22  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Bank 4 20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 20Dh to — Unimplemented — — 210h 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD ADD<7:0> 0000 0000 0000 0000 213h SSP1MSK MSK<7:0> 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 215h SSP1CON1 WCOL SSP1OV SSP1EN CKP SSP1M<3:0> 0000 0000 0000 0000 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h to — Unimplemented — — 21Fh Bank 5 28Ch to — Unimplemented — — 290h 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu 293h CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000 0000 0000 294h PWM1CON P1RSEN P1DC<6:0> 0000 0000 0000 0000 295h CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000 0000 0000 296h PSTR1CON — — — STR1SYNC Reserved Reserved STR1B STR1A ---0 rr01 ---0 rr01 297h to — Unimplemented — — 29Fh Bank 6 30Ch to — Unimplemented — — 31Fh Bank 7 38Ch to — Unimplemented — — 390h 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h to — Unimplemented — — 399h 39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 0011 0000 0011 0000 39Bh — Unimplemented — — 39Ch MDCON MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT 0010 ---0 0010 ---0 39Dh MDSRC MDMSODIS — — — MDMS<3:0> x--- xxxx u--- uuuu 39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> xxx- xxxx uuu- uuuu 39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> xxx- xxxx uuu- uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC12F1840 only. 3: Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001441F-page 23

PIC12(L)F1840 TABLE 3-6: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other POR, BOR Resets Banks 8-30 x0Ch/ — Unimplemented — — x8Ch — x1Fh/ x9Fh Bank 31 F8Ch — Unimplemented — — — FE3h FE4h STATUS_ — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FECh — Unimplemented — — FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111 FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuu FEFh TOSH — Top-of-Stack High byte -xxx xxxx -uuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: PIC12F1840 only. 3: Unimplemented, read as ‘1’. DS40001441F-page 24  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 3.4 PCL and PCLATH 3.4.2 COMPUTED GOTO The Program Counter (PC) is 15 bits wide. The low byte A computed GOTO is accomplished by adding an offset to comes from the PCL register, which is a readable and the program counter (ADDWF PCL). When performing a writable register. The high byte (PC<14:8>) is not directly table read using a computed GOTO method, care should readable or writable and comes from PCLATH. On any be exercised if the table location crosses a PCL memory Reset, the PC is cleared. Figure3-3 shows the five boundary (each 256-byte block). Refer to Application situations for the loading of the PC. Note AN556, “Implementing a Table Read” (DS00556). 3.4.3 COMPUTED FUNCTION CALLS FIGURE 3-3: LOADING OF PC IN DIFFERENT SITUATIONS A computed function CALL allows programs to maintain tables of functions and provide another way to execute 14 PCH PCL 0 Instruction with state machines or look-up tables. When performing a PC PCL as Destination table read using a computed function CALL, care should be exercised if the table location crosses a PCL 6 7 0 8 memory boundary (each 256-byte block). PCLATH ALU Result If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL 14 PCH PCL 0 PC GOTO, CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by com- 6 4 0 11 bining PCLATH and W to form the destination address. PCLATH OPCODE <10:0> A computed CALLW is accomplished by loading the W 14 PCH PCL 0 register with the desired address and executing CALLW. PC CALLW The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 6 7 0 8 PCLATH W 3.4.4 BRANCHING The branching instructions add an offset to the PC. 14 PCH PCL 0 PC BRW This allows relocatable code and code that crosses page boundaries. There are two forms of branching, 15 BRW and BRA. The PC will have incremented to fetch PC + W the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be 14 PCH PCL 0 crossed. PC BRA If using BRW, load the W register with the desired 15 unsigned address and execute BRW. The entire PC will PC + OPCODE <8:0> be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC+1+, 3.4.1 MODIFYING PCL the signed value of the operand of the BRA instruction. Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.  2011-2015 Microchip Technology Inc. DS40001441F-page 25

PIC12(L)F1840 3.5 Stack 3.5.1 ACCESSING THE STACK All devices have a 16-levelx15-bit wide hardware The stack is available through the TOSH, TOSL and stack (refer to Figures3-4 through and3-7). The stack STKPTR registers. STKPTR is the current value of the space is not part of either program or data space. The Stack Pointer. TOSH:TOSL register pair points to the PC is PUSHed onto the stack when CALL or CALLW TOP of the stack. Both registers are read/writable. TOS instructions are executed or an interrupt causes a is split into TOSH and TOSL due to the 15-bit size of the branch. The stack is POPed in the event of a RETURN, PC. To access the stack, adjust the value of STKPTR, RETLW or a RETFIE instruction execution. PCLATH is which will position TOSH:TOSL, then read/write to not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Words). This Note: Care should be taken when modifying the means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled. times, the seventeenth PUSH overwrites the value that During normal program operation, CALL, CALLW and was stored from the first PUSH. The eighteenth PUSH Interrupts will increment STKPTR while RETLW, overwrites the second PUSH (and so on). The RETURN, and RETFIE will decrement STKPTR. At any STKOVF and STKUNF flag bits will be set on an Over- time, STKPTR can be inspected to see how much flow/Underflow, regardless of whether the Reset is stack is left. The STKPTR always points at the currently enabled. used place on the stack. Therefore, a CALL or CALLW Note1: There are no instructions/mnemonics will increment the STKPTR and then write the PC, and called PUSH or POP. These are actions a return will unload the PC and then decrement the that occur from the execution of the STKPTR. CALL, CALLW, RETURN, RETLW and Reference Figure3-4 through Figure3-7 for examples RETFIE instructions or the vectoring to of accessing the stack. an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 Stack Reset Disabled TOSH:TOSL 0x0F STKPTR = 0x1F (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The 0x08 empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack 0x07 Overflow/Underflow Reset is enabled, the 0x06 TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is 0x05 disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x04 0x03 0x02 0x01 0x00 Stack Reset Enabled TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F (STVREN = 1) DS40001441F-page 26  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. 0x08 If a RETURN instruction is executed, the return address will be placed in the 0x07 Program Counter and the Stack Pointer 0x06 decremented to the empty state (0x1F). 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 Return Address STKPTR = 0x00 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an 0x0B interrupt, the stack looks like the figure on the left. A series of RETURN instructions 0x0A will repeatedly place the return addresses into the Program Counter and pop the stack. 0x09 0x08 0x07 TOSH:TOSL 0x06 Return Address STKPTR = 0x06 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address  2011-2015 Microchip Technology Inc. DS40001441F-page 27

PIC12(L)F1840 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address When the stack is full, the next CALL or 0x09 Return Address an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 0x08 Return Address so the stack will wrap and overwrite the return address at 0x00. If the Stack 0x07 Return Address Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will 0x06 Return Address not be overwritten. 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address TOSH:TOSL 0x00 Return Address STKPTR = 0x10 3.5.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.6 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory DS40001441F-page 28  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Reserved 0x7FFF Address Range 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.  2011-2015 Microchip Technology Inc. DS40001441F-page 29

PIC12(L)F1840 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing Indirect Addressing 4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0 0 0 0 0 Bank Select Location Select Bank Select Location Select 00000 00001 00010 11111 0x00 0x7F Bank 0 Bank 1 Bank 2 Bank 31 DS40001441F-page 30  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 3.6.2 LINEAR DATA MEMORY 3.6.3 PROGRAM FLASH MEMORY The linear data memory is the region from FSR To make constant data access easier, the entire address 0x2000 to FSR address 0x29AF. This region is program Flash memory is mapped to the upper half of a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is GPR memory in all the banks. set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the Unimplemented memory reads as 0x00. Use of the lower eight bits of each memory location is accessible linear data memory region allows buffers to be larger via INDF. Writing to the program Flash memory cannot than 80 bytes because incrementing the FSR beyond be accomplished via the FSR/INDF interface. All one bank will go directly to the GPR memory of the next instructions that access program Flash memory via the bank. FSR/INDF interface will require one additional The 16 bytes of common memory are not included in instruction cycle to complete. the linear data memory region. FIGURE 3-11: PROGRAM FLASH FIGURE 3-10: LINEAR DATA MEMORY MEMORY MAP MAP 7 FSRnH 0 7 FSRnL 0 7 FSRnH 0 7 FSRnL 0 1 0 0 1 Location Select 0x8000 0x0000 Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 Program 0x0EF Flash 0x120 Memory (low 8 Bank 2 bits) 0x16F 0xF20 Bank 30 0xFFFF 0x7FFF 0x29AF 0xF6F  2011-2015 Microchip Technology Inc. DS40001441F-page 31

PIC12(L)F1840 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. DS40001441F-page 32  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN BOREN<1:0> CPD bit 13 bit 8 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 =CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 =CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 =MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 =MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off.  2011-2015 Microchip Technology Inc. DS40001441F-page 33

PIC12(L)F1840 REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 =WDT enabled 10 =WDT enabled while running and disabled in Sleep 01 =WDT controlled by the SWDTEN bit in the WDTCON register 00 =WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. DS40001441F-page 34  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 LVP(1) DEBUG(2) — BORV STVREN PLLEN bit 13 bit 8 U-1 U-1 R-1 U-1 U-1 U-1 R/P-1 R/P-1 — — Reserved — — — WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(2) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 Unimplemented: Read as ‘1’ bit 10 BORV: Brown-out Reset Voltage Selection bit(3) 1 = Brown-out Reset voltage (Vbor), low trip point selected. 0 = Brown-out Reset voltage (Vbor), high trip point selected. bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-5 Unimplemented: Read as ‘1’ bit 4 Reserved: This location should be programmed to a ‘1’. bit 3-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified 00 = 000h to FFFh write-protected, no addresses may be modified Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. 2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 3: See Vbor parameter for specific trip point voltages.  2011-2015 Microchip Technology Inc. DS40001441F-page 35

PIC12(L)F1840 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section4.4 “Write Protection” for more information. 4.3.2 DATA EEPROM PROTECTION The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF1847/PIC12F/LF1840 Memory Programming Specification” (DS41439). DS40001441F-page 36  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 4.6 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. REGISTER 4-3: DEVID: DEVICE ID REGISTER R R R R R R DEV<8:3> bit 13 bit 8 R R R R R R R R DEV<2:0> REV<4:0> bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-5 DEV<8:0>: Device ID bits DEVID<13:0> Values Device DEV<8:0> REV<4:0> PIC12F1840 011 011 100 x xxxx PIC12LF1840 011 011 110 x xxxx bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision (see Table under DEV<8:0> above).  2011-2015 Microchip Technology Inc. DS40001441F-page 37

PIC12(L)F1840 5.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight FAIL-SAFE CLOCK MONITOR) clock modes. 1. ECL – External Clock Low-Power mode 5.1 Overview (0MHz to 0.5MHz) 2. ECM – External Clock Medium-Power mode The oscillator module has a wide variety of clock (0.5MHz to 4MHz) sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode in a wide range of applications while maximizing perfor- (4MHz to 32MHz) mance and minimizing power consumption. Figure5-1 4. LP – 32kHz Low-Power Crystal mode. illustrates a block diagram of the oscillator module. 5. XT – Medium Gain Crystal or Ceramic Resonator Clock sources can be supplied from external oscillators, Oscillator mode (up to 4 MHz) quartz crystal resonators, ceramic resonators and 6. HS – High Gain Crystal or Ceramic Resonator Resistor-Capacitor (RC) circuits. In addition, the system mode (4 MHz to 20 MHz) clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds 7. RC – External Resistor-Capacitor (RC). selectable via software. Additional clock features 8. INTOSC – Internal oscillator (31kHz to 32 MHz). include: Clock Source modes are selected by the FOSC<2:0> • Selectable system clock source between external bits in the Configuration Words. The FOSC bits or internal sources via software. determine the type of oscillator that will be used when • Two-Speed Start-up mode, which minimizes the device is first powered. latency between external oscillator start-up and The EC clock mode relies on an external logic level code execution. signal as the device clock source. The LP, XT, and HS • Fail-Safe Clock Monitor (FSCM) designed to clock modes require an external crystal or resonator to detect a failure of the external clock source (LP, be connected to the device. Each mode is optimized for XT, HS, EC or RC modes) and switch a different frequency range. The RC clock mode automatically to the internal oscillator. requires an external resistor and capacitor to set the • Oscillator Start-up Timer (OST) ensures stability oscillator frequency. of crystal oscillator sources. The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure5-1). A wide selection of device clock frequencies may be derived from these three clock sources. DS40001441F-page 38  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM External Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL Sleep OSC1 Oscillator Timer1 FOSC<2:0> = 100 T1OSC X CPU and T1OSO U Peripherals M T1OSCEN Enable T1OSI Oscillator IRCF<3:0> Internal Oscillator 16 MHz 8 MHz Internal Oscillator 4 MHz Block 2 MHz er 1 MHz Clock HFPLL 16 MHz scal 500 kHz UX Control (HFINTOSC) ost 250 kHz M P 125 kHz FOSC<2:0> SCS<1:0> 500 kHz Source 500 kHz 62.5 kHz (MFINTOSC) 31.25 kHz Clock Source Option for other modules 31 kHz 31 kHz Source 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules  2011-2015 Microchip Technology Inc. DS40001441F-page 39

PIC12(L)F1840 5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully clock source to function. Examples are: oscillator mod- static, stopping the external clock input will have the ules (EC mode), quartz crystal resonators or ceramic effect of halting the device while leaving all data intact. resonators (LP, XT and HS modes) and Resis- Upon restarting the external clock, the device will tor-Capacitor (RC) mode circuits. resume operation as if no time had elapsed. Internal clock sources are contained within the oscilla- FIGURE 5-2: EXTERNAL CLOCK (EC) tor module. The internal oscillator block has two inter- MODE OPERATION nal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16MHz High-Frequency Clock from OSC1/CLKIN Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) Ext. System and the 31kHz Low-Frequency Internal Oscillator PIC® MCU (LFINTOSC). OSC2/CLKOUT The system clock can be selected between external or FOSC/4 or I/O(1) internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section5.3 Note 1: Output depends upon CLKOUTEN bit of the “Clock Switching” for additional information. Configuration Words. 5.2.1 EXTERNAL CLOCK SOURCES 5.2.1.2 LP, XT, HS Modes An external clock source can be used as the device system clock by performing one of the following The LP, XT and HS modes support the use of quartz actions: crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure5-3). The three modes select • Program the FOSC<2:0> bits in the Configuration a low, medium or high gain setting of the internal Words to select an external clock source that will inverter-amplifier to support various resonator types be used as the default system clock upon a and speed. device Reset. • Write the SCS<1:0> bits in the OSCCON register LP Oscillator mode selects the lowest gain setting of the to switch the system clock source to: internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to - Timer1 oscillator during run-time, or drive only 32.768 kHz tuning-fork type crystals (watch - An external clock source determined by the crystals). value of the FOSC bits. XT Oscillator mode selects the intermediate gain See Section5.3 “Clock Switching”for more informa- setting of the internal inverter-amplifier. XT mode tion. current consumption is the medium of the three modes. This mode is best suited to drive resonators with a 5.2.1.1 EC Mode medium drive level specification. The External Clock (EC) mode allows an externally HS Oscillator mode selects the highest gain setting of the generated logic level signal to be the system clock internal inverter-amplifier. HS mode current consumption source. When operating in this mode, an external clock is the highest of the three modes. This mode is best source is connected to the OSC1 input. suited for resonators that require a high drive setting. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure5-2 shows the pin connections for EC Figure5-3 and Figure5-4 show typical circuits for mode. quartz crystal and ceramic resonators, respectively. EC mode has three power modes to select from through Configuration Words: • High power, 4-32MHz (FOSC = 111) • Medium power, 0.5-4MHz (FOSC = 110) • Low power, 0-0.5MHz (FOSC = 101) DS40001441F-page 40  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 5-3: QUARTZ CRYSTAL FIGURE 5-4: CERAMIC RESONATOR OPERATION (LP, XT OR OPERATION HS MODE) (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN OSC1/CLKIN C1 To Internal C1 To Internal Logic Logic QCruyasrttazl RF(2) Sleep RP(3) RF(2) Sleep C2 RS(1) OSC2/CLKOUT C2 Ceramic RS(1) OSC2/CLKOUT Resonator Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 2: The value of RF varies with the Oscillator mode selected (typically between 2M to 10M. 3: An additional parallel feedback resistor (RP) Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator according to type, package and operation. manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST) 2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts expected for the application. 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer 3: For oscillator design assistance, reference (PWRT) has expired (if configured), or a wake-up from the following Microchip Applications Notes: Sleep. During this time, the program counter does not • AN826, “Crystal Oscillator Basics and increment and program execution is suspended, Crystal Selection for rfPIC® and PIC® unless either FSCM or Two-Speed Start-Up are Devices” (DS00826) enabled. In this case, code will continue to execute at • AN849, “Basic PIC® Oscillator Design” the selected INTOSC frequency while the OST is (DS00849) counting. The OST ensures that the oscillator circuit, • AN943, “Practical PIC® Oscillator using a quartz crystal resonator or ceramic resonator, Analysis and Design” (DS00943) has started and is providing a stable system clock to the oscillator module. • AN949, “Making Your Oscillator Work” (DS00949) In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section5.4 “Two-Speed Clock Start-up Mode”).  2011-2015 Microchip Technology Inc. DS40001441F-page 41

PIC12(L)F1840 5.2.1.4 4x PLL Note 1: Quartz crystal characteristics vary The oscillator module contains a 4x PLL that can be according to type, package and used with both external and internal clock sources to manufacturer. The user should consult the provide a system clock source. The input frequency for manufacturer data sheets for specifications the 4x PLL must fall within specifications. See the PLL and recommended application. Clock Timing Specifications in Section30.0 2: Always verify oscillator performance over “Electrical Specifications”. the VDD and temperature range that is The 4x PLL may be enabled for use by one of two expected for the application. methods: 3: For oscillator design assistance, reference 1. Program the PLLEN bit in Configuration Words the following Microchip Applications Notes: to a ‘1’. • AN826, “Crystal Oscillator Basics and 2. Write the SPLLEN bit in the OSCCON register to Crystal Selection for rfPIC® and PIC® a ‘1’. If the PLLEN bit in Configuration Words is Devices” (DS00826) programmed to a ‘1’, then the value of SPLLEN • AN849, “Basic PIC® Oscillator Design” is ignored. (DS00849) 5.2.1.5 TIMER1 Oscillator • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) The Timer1 oscillator is a separate crystal oscillator • AN949, “Making Your Oscillator Work” that is associated with the Timer1 peripheral. It is opti- (DS00949) mized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI • TB097, “Interfacing a Micro Crystal device pins. MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) The Timer1 oscillator can be used as an alternate • AN1288, “Design Practices for system clock source and can be selected during Low-Power External Oscillators” run-time using clock switching. Refer to Section5.3 (DS01288) “Clock Switching” for more information. FIGURE 5-5: QUARTZ CRYSTAL 5.2.1.6 External RC Mode OPERATION (TIMER1 OSCILLATOR) The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while PIC® MCU keeping costs to a minimum when clock accuracy is not required. T1OSI The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The C1 To Internal Logic function of the OSC2/CLKOUT pin is determined by the 32.768 kHz CLKOUTEN bit in Configuration Words. Quartz Crystal Figure5-6 shows the external RC mode connections. C2 T1OSO DS40001441F-page 42  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 5-6: EXTERNAL RC MODES 5.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one VDD PIC® MCU of the following actions: REXT • Program the FOSC<2:0> bits in Configuration OSC1/CLKIN Internal Words to select the INTOSC clock source, which Clock will be used as the default system clock upon a CEXT device Reset. • Write the SCS<1:0> bits in the OSCCON register VSS to switch the system clock source to the internal oscillator during run-time. See Section5.3 FOSC/4 or I/O(1) OSC2/CLKOUT “Clock Switching”for more information. In INTOSC mode, OSC1/CLKIN is available for general Recommended values: 10 k  REXT  100 k, <3V purpose I/O. OSC2/CLKOUT is available for general 3 k  REXT  100 k, 3-5V purpose I/O or CLKOUT. CEXT > 20 pF, 2-5V The function of the OSC2/CLKOUT pin is determined Note 1: Output depends upon CLKOUTEN bit of the by the CLKOUTEN bit in Configuration Words. Configuration Words. The internal oscillator block has two independent oscillators and a dedicated Phase-Lock Loop, HFPLL The RC oscillator frequency is a function of the supply that can produce one of three internal system clock voltage, the resistor (REXT) and capacitor (CEXT) values sources. and the operating temperature. Other factors affecting 1. The HFINTOSC (High-Frequency Internal the oscillator frequency are: Oscillator) is factory calibrated and operates at • threshold voltage variation 16MHz. The HFINTOSC source is generated • component tolerances from the 500 kHz MFINTOSC source and the • packaging variations in capacitance dedicated Phase-Lock Loop, HFPLL. The The user also needs to take into account variation due frequency of the HFINTOSC can be to tolerance of external RC components used. user-adjusted via software using the OSCTUNE register (Register5-3). 2. The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register5-3). 3. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31kHz.  2011-2015 Microchip Technology Inc. DS40001441F-page 43

PIC12(L)F1840 5.2.2.1 HFINTOSC 5.2.2.3 Internal Oscillator Frequency Adjustment The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16MHz internal clock source. The The 500 kHz internal oscillator is factory calibrated. frequency of the HFINTOSC can be altered via This internal oscillator can be adjusted in software by software using the OSCTUNE register (Register5-3). writing to the OSCTUNE register (Register5-3). Since The output of the HFINTOSC connects to a postscaler the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in and multiplexer (see Figure5-1). One of multiple frequencies derived from the HFINTOSC can be the OSCTUNE register value will apply to both. selected via software using the IRCF<3:0> bits of the The default value of the OSCTUNE register is ‘0’. The OSCCON register. See Section5.2.2.7 “Internal value is a 6-bit two’s complement number. A value of Oscillator Clock Switch Timing” for more information. 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to The HFINTOSC is enabled by: the minimum frequency. • Configure the IRCF<3:0> bits of the OSCCON When the OSCTUNE register is modified, the oscillator register for the desired HF frequency, and frequency will begin shifting to the new frequency. Code • FOSC<2:0> = 100, or execution continues during this shift. There is no • Set the System Clock Source (SCS) bits of the indication that the shift has occurred. OSCCON register to ‘1x’. OSCTUNE does not affect the LFINTOSC frequency. A fast start-up oscillator allows internal circuits to power Operation of features that depend on the LFINTOSC up and stabilize before switching to HFINTOSC. clock source frequency, such as the Power-up Timer The High-Frequency Internal Oscillator Ready bit (PWRT), Watchdog Timer (WDT), Fail-Safe Clock (HFIOFR) of the OSCSTAT register indicates when the Monitor (FSCM) and peripherals, are not affected by the HFINTOSC is running. change in frequency. The High-Frequency Internal Oscillator Status Locked 5.2.2.4 LFINTOSC bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31kHz internal clock source. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the The output of the LFINTOSC connects to a multiplexer HFINTOSC is running within 0.5% of its final value. (see Figure5-1). Select 31kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See 5.2.2.2 MFINTOSC Section5.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also The Medium-Frequency Internal Oscillator the frequency for the Power-up Timer (PWRT), (MFINTOSC) is a factory calibrated 500kHz internal Watchdog Timer (WDT) and Fail-Safe Clock Monitor clock source. The frequency of the MFINTOSC can be (FSCM). altered via software using the OSCTUNE register (Register5-3). The LFINTOSC is enabled by selecting 31kHz (IRCF<3:0> bits of the OSCCON register=000) as the The output of the MFINTOSC connects to a postscaler system clock source (SCS bits of the OSCCON and multiplexer (see Figure5-1). One of nine register= 1x), or when any of the following are frequencies derived from the MFINTOSC can be enabled: selected via software using the IRCF<3:0> bits of the OSCCON register. See Section5.2.2.7 “Internal • Configure the IRCF<3:0> bits of the OSCCON Oscillator Clock Switch Timing” for more information. register for the desired LF frequency, and The MFINTOSC is enabled by: • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the • Configure the IRCF<3:0> bits of the OSCCON OSCCON register to ‘1x’ register for the desired HF frequency, and • FOSC<2:0> = 100, or Peripherals that use the LFINTOSC are: • Set the System Clock Source (SCS) bits of the • Power-up Timer (PWRT) OSCCON register to ‘1x’ • Watchdog Timer (WDT) The Medium Frequency Internal Oscillator Ready bit • Fail-Safe Clock Monitor (FSCM) (MFIOFR) of the OSCSTAT register indicates when the The Low-Frequency Internal Oscillator Ready bit MFINTOSC is running. (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. DS40001441F-page 44  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 5.2.2.5 Internal Oscillator Frequency 5.2.2.6 32 MHz Internal Oscillator Selection Frequency Selection The system clock speed can be selected via software The Internal Oscillator Block can be used with the 4x using the Internal Oscillator Frequency Select bits PLL associated with the External Oscillator Block to IRCF<3:0> of the OSCCON register. produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz inter- The output of the 16MHz HFINTOSC postscaler and nal clock source: LFINTOSC connects to a multiplexer (see Figure5-1). The Internal Oscillator Frequency Select bits • The FOSC bits in Configuration Words must be IRCF<3:0> of the OSCCON register select the set to use the INTOSC source as the device frequency output of the internal oscillators. One of the system clock (FOSC<2:0> = 100). following frequencies can be selected via software: • The SCS bits in the OSCCON register must be • 32 MHz (requires 4x PLL) cleared to use the clock determined by FOSC<2:0> in Configuration Words • 16 MHz (SCS<1:0>=00). • 8 MHz • The IRCF bits in the OSCCON register must be • 4 MHz set to the 8 MHz HFINTOSC set to use • 2 MHz (IRCF<3:0>=1110). • 1 MHz • The SPLLEN bit in the OSCCON register must be • 500 kHz (default after Reset) set to enable the 4xPLL, or the PLLEN bit of the • 250 kHz Configuration Words must be programmed to a • 125 kHz ‘1’. • 62.5 kHz Note: When using the PLLEN bit of the Configuration Words, the 4x PLL cannot • 31.25 kHz be disabled by software and the 8 MHz • 31 kHz (LFINTOSC) HFINTOSC option will no longer be Note: Following any Reset, the IRCF<3:0> bits available. of the OSCCON register are set to ‘0111’ and the frequency selection is set to The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register 500kHz. The user can modify the IRCF bits to select a different frequency. are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4x PLL with the internal oscillator. The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These dupli- cate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source.  2011-2015 Microchip Technology Inc. DS40001441F-page 45

PIC12(L)F1840 5.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. IRCF<3:0> bits of the OSCCON register are modified. 2. If the new clock is shut down, a clock start-up delay is started. 3. Clock switch circuitry waits for a falling edge of the current clock. 4. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. The new clock is now active. 6. The OSCSTAT register is updated as required. 7. Clock switch is complete. See Figure5-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table5-1. Start-up delay specifications are located in the oscillator tables of Section30.0 “Electrical Specifications” DS40001441F-page 46  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (FSCM and WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC Oscillator Delay(1) 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ LFINTOSC (Either FSCM or WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC   IRCF <3:0> 0 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Oscillator Delay(1) 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> = 0  0 System Clock Note 1: See Table5-1, Oscillator Switching Delays, for more information.  2011-2015 Microchip Technology Inc. DS40001441F-page 47

PIC12(L)F1840 5.3 Clock Switching 5.3.3 TIMER1 OSCILLATOR The system clock source can be switched between The Timer1 oscillator is a separate crystal oscillator external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal register. The following clock sources can be selected connected between the T1OSO and T1OSI device using the SCS bits: pins. • Default system oscillator determined by FOSC The Timer1 oscillator is enabled using the T1OSCEN bits in Configuration Words control bit in the T1CON register. See Section21.0 “Timer1 Module with Gate Control” for more • Timer1 32 kHz crystal oscillator information about the Timer1 peripheral. • Internal Oscillator Block (INTOSC) 5.3.4 TIMER1 OSCILLATOR READY 5.3.1 SYSTEM CLOCK SELECT (SCS) (T1OSCR) BIT BITS The user must ensure that the Timer1 oscillator is The System Clock Select (SCS) bits of the OSCCON ready to be used before it is selected as a system clock register selects the system clock source that is used for source. The Timer1 Oscillator Ready (T1OSCR) bit of the CPU and peripherals. the OSCSTAT register indicates whether the Timer1 • When the SCS bits of the OSCCON register = 00, oscillator is ready to be used. After the T1OSCR bit is the system clock source is determined by value of set, the SCS bits can be configured to select the Timer1 the FOSC<2:0> bits in the Configuration Words. oscillator. • When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table5-1. 5.3.2 OSCILLATOR START-UP TIMER STATUS (OSTS) BIT The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 oscillator. DS40001441F-page 48  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode provides additional power savings by minimizing the latency between external Two-Speed Start-up mode is configured by the oscillator start-up and code execution. In applications following settings: that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Words) = 1; Inter- Start-up will remove the external oscillator start-up nal/External Switchover bit (Two-Speed Start-up time from the time spent awake and can reduce the mode enabled). overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00. allows the application to wake-up from Sleep, perform • FOSC<2:0> bits in the Configuration Words a few instructions using the INTOSC internal oscillator configured for LP, XT or HS mode. block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after: Two-Speed Start-up provides benefits when the oscil- • Power-on Reset (POR) and, if enabled, after lator module is configured for LP, XT or HS modes. Power-up Timer (PWRT) has expired, or The Oscillator Start-up Timer (OST) is enabled for • Wake-up from Sleep. these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) 31kHz Sleep/POR MFINTOSC(1) 31.25kHz-500 kHz Oscillator Warm-up Delay (TWARM) HFINTOSC(1) 31.25kHz-16MHz Sleep/POR EC, RC(1) DC – 32MHz 2 cycles LFINTOSC EC, RC(1) DC – 32MHz 1 cycle of each Timer1 Oscillator Sleep/POR 32kHz-20MHz 1024 Clock Cycles (OST) LP, XT, HS(1) MFINTOSC(1) 31.25kHz-500kHz Any clock source 2s (approx.) HFINTOSC(1) 31.25kHz-16MHz Any clock source LFINTOSC(1) 31kHz 1 cycle of each Any clock source Timer1 Oscillator 32kHz 1024 Clock Cycles (OST) PLL inactive PLL active 16-32MHz 2ms (approx.) Note 1: PLL inactive.  2011-2015 Microchip Technology Inc. DS40001441F-page 49

PIC12(L)F1840 5.4.2 TWO-SPEED START-UP 5.4.3 CHECKING TWO-SPEED CLOCK SEQUENCE STATUS 1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT 2. Instructions begin execution by the internal register will confirm if the microcontroller is running oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the bits of the OSCCON register. FOSC<2:0> bits in the Configuration Words, or the internal oscillator. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. 6. System clock held low until the next falling edge of new clock (LP, XT or HS mode). 7. System clock is switched to external clock source. FIGURE 5-8: TWO-SPEED START-UP INTOSC TTOST OSC1 0 1 1022 1023 OSC2 Program Counter P C - N PC PC + 1 System Clock DS40001441F-page 50  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset, to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the SCS bits The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bits are the Oscillator Start-up Timer (OST) has expired. The changed, the OST is restarted. While the OST is FSCM is enabled by setting the FCMEN bit in the running, the device continues to operate from the Configuration Words. The FSCM is applicable to all INTOSC selected in OSCCON. When the OST times external Oscillator modes (LP, XT, HS, EC, Timer1 out, the Fail-Safe condition is cleared after successfully Oscillator and RC). switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the FIGURE 5-9: FSCM BLOCK DIAGRAM OSFIF flag will again become set by hardware. Clock Monitor 5.5.4 RESET OR WAKE-UP FROM SLEEP Latch External S Q The FSCM is designed to detect an oscillator failure Clock after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after LFINTOSC any type of Reset. The OST is not used with the EC or Oscillator ÷ 64 R Q RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When 31 kHz 488 Hz the FSCM is enabled, the Two-Speed Start-up is also (~32 s) (~2 ms) enabled. Therefore, the device will always be executing code while the OST is operating. Sample Clock Clock Failure Note: Due to the wide range of oscillator start-up Detected times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate 5.5.1 FAIL-SAFE DETECTION amount of time, the user should check the The FSCM module detects a failed oscillator by Status bits in the OSCSTAT register to comparing the external oscillator to the FSCM sample verify the oscillator start-up and that the clock. The sample clock is generated by dividing the system clock switchover has successfully LFINTOSC by 64. See Figure5-9. Inside the fail completed. detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2011-2015 Microchip Technology Inc. DS40001441F-page 51

PIC12(L)F1840 FIGURE 5-10: FSCM TIMING DIAGRAM Sample Clock System Oscillator Clock Failure Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Test Test Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS40001441F-page 52  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 5.6 Register Definitions: Oscillator Control REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 SPLLEN IRCF<3:0> — SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16MHz HF 1110 = 8MHz or 32 MHz HF(see Section5.2.2.1 “HFINTOSC”) 1101 = 4MHz HF 1100 = 2MHz HF 1011 = 1MHz HF 1010 = 500kHz HF(1) 1001 = 250kHz HF(1) 1000 = 125kHz HF(1) 0111 = 500kHz MF (default upon Reset) 0110 = 250kHz MF 0101 = 125kHz MF 0100 = 62.5kHz MF 0011 = 31.25kHz HF(1) 0010 = 31.25kHz MF 000x = 31kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words. Note 1: Duplicate frequency derived from HFINTOSC.  2011-2015 Microchip Technology Inc. DS40001441F-page 53

PIC12(L)F1840 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready bit 6 PLLR: 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS40001441F-page 54  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 000000 = Oscillator module is running at the factory-calibrated frequency. 000001 • • • 011110 011111 = Maximum frequency TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 53 OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 54 OSCTUNE — — TUN<5:0> 55 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 74 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 76 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 154 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 33 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.  2011-2015 Microchip Technology Inc. DS40001441F-page 55

PIC12(L)F1840 6.0 REFERENCE CLOCK MODULE 6.3 Conflicts with the CLKR Pin The reference clock module provides the ability to send There are two cases when the reference clock output a divided clock to the clock output pin of the device signal cannot be output to the CLKR pin, if: (CLKR) and provide a secondary internal clock source • LP, XT or HS Oscillator mode is selected. to the modulator module. This module is available in all • CLKOUT function is enabled. oscillator configurations and allows the user to select a greater range of clock sub-multiples to drive external Even if either of these cases are true, the module can devices in the application. The reference clock module still be enabled and the reference clock signal may be includes the following features: used in conjunction with the modulator module. • System clock is the source 6.3.1 OSCILLATOR MODES • Available in all oscillator configurations If LP, XT or HS oscillator modes are selected, the • Programmable clock divider OSC2/CLKR pin must be used as an oscillator input pin • Output enable to a port pin and the CLKR output cannot be enabled. See • Selectable duty cycle Section5.2 “Clock Source Types” for more • Slew rate control information on different oscillator modes. The reference clock module is controlled by the 6.3.2 CLKOUT FUNCTION CLKRCON register (Register6-1) and is enabled when setting the CLKREN bit. To output the divided The CLKOUT function has a higher priority than the clock signal to the CLKR port pin, the CLKROE bit reference clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configura- must be set. The CLKRDIV<2:0> bits enable the selection of eight different clock divider options. The tion Words, FOSC/4 will always be output on the port pin. Reference Section4.0 “Device Configuration” CLKRDC<1:0> bits can be used to modify the duty cycle of the output clock(1). The CLKRSLR bit controls for more information. slew rate limiting. 6.4 Operation During Sleep Note1: If the base clock rate is selected without a divider, the output clock will always As the reference clock module relies on the system have a duty cycle equal to that of the clock as its source, and the system clock is disabled in source clock, unless a 0% duty cycle is Sleep, the module does not function in Sleep, even if selected. If the clock divider is set to base an external clock source or the Timer1 clock source is clock/2, then 25% and 75% duty cycle configured as the system clock. The module outputs accuracy will be dependent upon the will remain in their current state until the device exits source clock. Sleep. For information on using the reference clock output with the modulator module, see Section23.0 “Data Signal Modulator”. 6.1 Slew Rate The slew rate limitation on the output port pin can be disabled. The slew rate limitation is removed by clearing the CLKRSLR bit in the CLKRCON register. 6.2 Effects of a Reset Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. DS40001441F-page 56  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 6.5 Register Definition: Reference Clock Control REGISTER 6-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CLKREN: Reference Clock Module Enable bit 1 = Reference clock module is enabled 0 = Reference clock module is disabled bit 6 CLKROE: Reference Clock Output Enable bit(3) 1 = Reference clock output is enabled on CLKR pin 0 = Reference clock output disabled on CLKR pin bit 5 CLKRSLR: Reference Clock Slew Rate Control Limiting Enable bit 1 = Slew rate limiting is enabled 0 = Slew rate limiting is disabled bit 4-3 CLKRDC<1:0>: Reference Clock Duty Cycle bits 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% bit 2-0 CLKRDIV<2:0> Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2(1) 000 = Base clock value(2) Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: To route CLKR to pin, CLKOUTEN of Configuration Words = 1 is required. CLKOUTEN of Configuration Words = 0 will result in FOSC/4. See Section6.3 “Conflicts with the CLKR Pin” for details.  2011-2015 Microchip Technology Inc. DS40001441F-page 57

PIC12(L)F1840 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CLKRCON CLKREN CLKROE CLKRSLR CLKRDC<1:0> CLKRDIV<2:0> 57 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. TABLE 6-2: SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 33 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. DS40001441F-page 58  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 7.0 RESETS There are multiple ways to reset this device: • Power-On Reset (POR) • Brown-Out Reset (BOR) • MCLR Reset • WDT Reset • RESET instruction • Stack Overflow • Stack Underflow • Programming mode exit To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure7-1. FIGURE 7-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Stack Overflow/Underflow Reset Pointer External Reset MCLRE MCLR Sleep WDT Time-out Device Power-on Reset Reset VDD Brown-out Reset BOR Enable PWRT Zero 64 ms LFINTOSC PWRTEN  2011-2015 Microchip Technology Inc. DS40001441F-page 59

PIC12(L)F1840 7.1 Power-On Reset (POR) 7.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for performance may require greater than minimum VDD. execution protection can be implemented. The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in conditions have been met. Configuration Words. The four operating modes are: 7.1.1 POWER-UP TIMER (PWRT) • BOR is always on • BOR is off when in Sleep The Power-up Timer provides a nominal 64ms time- out on POR or Brown-out Reset. • BOR is controlled by software • BOR is always off The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to Refer to Table7-1 for more information. rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words. Words. A VDD noise rejection filter prevents the BOR from The Power-up Timer starts after the release of the POR triggering on small events. If VDD falls below VBOR for and BOR. a duration greater than parameter TBORDC, the device For additional information, refer to Application Note will reset. See Figure7-2 for more information. AN607, “Power-up Trouble Shooting” (DS00607). TABLE 7-1: BOR OPERATING MODES Instruction Execution upon: BOREN<1:0> SBOREN Device Mode BOR Mode Release of POR or Wake-up from Sleep 11 X X Active Waits for BOR ready(1) (BORRDY = 1) Awake Active 10 X Waits for BOR ready (BORRDY = 1) Sleep Disabled 1 X Active Waits for BOR ready(1) (BORRDY = 1) 01 0 X Disabled Begins immediately (BORRDY = x) 00 X X Disabled Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 7.2.1 BOR IS ALWAYS ON 7.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device programmed to ‘01’, the BOR is controlled by the start-up will be delayed until the BOR is ready and VDD SBOREN bit of the BORCON register. The device start- is higher than the BOR threshold. up is not delayed by the BOR ready condition or the BOR protection is active during Sleep. The BOR does VDD level. not delay wake-up from Sleep. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the 7.2.2 BOR IS OFF IN SLEEP BORRDY bit of the BORCON register. When the BOREN bits of Configuration Words are BOR protection is unchanged by Sleep. programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. DS40001441F-page 60  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 7-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal < TPWRT Reset TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’. 7.3 Register Definitions: BOR Control REGISTER 7-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words.  2011-2015 Microchip Technology Inc. DS40001441F-page 61

PIC12(L)F1840 7.4 MCLR 7.9 Power-Up Timer The MCLR is an optional external input that can reset The Power-up Timer optionally delays device execution the device. The MCLR function is controlled by the after a BOR or POR event. This timer is typically used to MCLRE bit of Configuration Words and the LVP bit of allow VDD to stabilize before allowing the device to start Configuration Words (Table7-2). running. The Power-up Timer is controlled by the PWRTE bit of TABLE 7-2: MCLR CONFIGURATION Configuration Words. MCLRE LVP MCLR 7.10 Start-up Sequence 0 0 Disabled Upon the release of a POR or BOR, the following must 1 0 Enabled occur before the device will begin executing: x 1 Enabled 1. Power-up Timer runs to completion (if enabled). 7.4.1 MCLR ENABLED 2. Oscillator start-up timer runs to completion (if required for oscillator source). When MCLR is enabled and the pin is held low, the 3. MCLR must be released (if enabled). device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The total time-out will vary based on oscillator configu- ration and Power-up Timer configuration. See The device has a noise filter in the MCLR Reset path. Section5.0 “Oscillator Module (with Fail-Safe The filter will detect and ignore small pulses. Clock Monitor)” for more information. Note: A Reset does not drive the MCLR pin low. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long 7.4.2 MCLR DISABLED enough, the Power-up Timer and oscillator start-up When MCLR is disabled, the pin functions as a general timer will expire. Upon bringing MCLR high, the device purpose input and the internal weak pull-up is under will begin execution immediately (see Figure7-3). This software control. See Section12.2 “PORTA Registers” is useful for testing purposes or to synchronize more for more information. than one device operating in parallel. 7.5 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section10.0 “Watchdog Timer (WDT)” for more information. 7.6 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table7-4 for default conditions after a RESET instruction has occurred. 7.7 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word2. See Section3.5.2 “Overflow/Underflow Reset” for more information. 7.8 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. DS40001441F-page 62  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 7-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC  2011-2015 Microchip Technology Inc. DS40001441F-page 63

PIC12(L)F1840 7.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table7-3 and Table7-4 show the Reset conditions of these registers. TABLE 7-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RMCLR RI POR BOR TO PD Condition 0 0 1 1 0 x 1 1 Power-on Reset 0 0 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 0 x x 0 Illegal, PD is set on POR 0 0 1 1 u 0 1 1 Brown-out Reset u u u u u u 0 u WDT Reset u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u 1 0 Interrupt Wake-up from Sleep u u 0 u u u u u MCLR Reset during normal operation u u 0 u u u 1 0 MCLR Reset during Sleep u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu RESET Instruction Executed 0000h ---u uuuu uu-- u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS40001441F-page 64  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 7.12 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Reset Instruction Reset (RI) • Stack Overflow Reset (STKOVF) • Stack Underflow Reset (STKUNF) • MCLR Reset (RMCLR) The PCON register bits are shown in Register7-2. 7.13 Register Definitions: Power Control REGISTER 7-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF — — RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or set to ‘0’ by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or set to ‘0’ by firmware bit 5-4 Unimplemented: Read as ‘0’ bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)  2011-2015 Microchip Technology Inc. DS40001441F-page 65

PIC12(L)F1840 TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BORCON SBOREN BORFS — — — — — BORRDY 61 PCON STKOVF STKUNF — — RMCLR RI POR BOR 65 STATUS — — — TO PD Z DC C 15 WDTCON — — WDTPS<4:0> SWDTEN 83 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Resets. DS40001441F-page 66  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 8.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • Operation • Interrupt Latency • Interrupts During Sleep • INT Pin • Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure8-1. FIGURE 8-1: INTERRUPT LOGIC TMR0IF Wake-up TMR0IE (If in Sleep mode) INTF Peripheral Interrupts INTE (TMR1IF) PIR1<0> IOCIF (TMR1IE) PIE1<0> Interrupt IOCIE to CPU PEIE PIRn<7> GIE PIEn<7>  2011-2015 Microchip Technology Inc. DS40001441F-page 67

PIC12(L)F1840 8.1 Operation 8.2 Interrupt Latency Interrupts are disabled upon any device Reset. They Interrupt latency is defined as the time from when the are enabled by setting the following bits: interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous • GIE bit of the INTCON register interrupts is three or four instruction cycles. For • Interrupt Enable bit(s) for the specific interrupt asynchronous interrupts, the latency is three to five event(s) instruction cycles, depending on when the interrupt • PEIE bit of the INTCON register (if the Interrupt occurs. See Figure8-2 and Figure8-3 for more details. Enable bit of the interrupt event is contained in the PIEx register) The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See Section8.5 “Automatic Context Saving”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt operation, refer to its peripheral chapter. Note1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS40001441F-page 68  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 8-2: INTERRUPT LATENCY OSC1 Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC PC-1 PC PC+1 0004h 0005h Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC+1/FSR New PC/ PC PC-1 PC ADDR PC+1 0004h 0005h Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)  2011-2015 Microchip Technology Inc. DS40001441F-page 69

PIC12(L)F1840 FIGURE 8-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 (3) CLKOUT (4) INT pin (1) (1) (2) INTF (5) Interrupt Latency GIE INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section30.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001441F-page 70  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 8.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section9.0 “Power- Down Mode (Sleep)” for more details. 8.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 8.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • W register • STATUS register (except for TO and PD) • BSR register • FSR registers • PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.  2011-2015 Microchip Technology Inc. DS40001441F-page 71

PIC12(L)F1840 8.6 Register Definitions: Interrupt Control REGISTER 8-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register have been cleared by software. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001441F-page 72  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 8-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2011-2015 Microchip Technology Inc. DS40001441F-page 73

PIC12(L)F1840 REGISTER 8-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 OSFIE — C1IE EEIE BCL1IE — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 Unimplemented: Read as ‘0’ bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2-0 Unimplemented: Read as ‘0’ Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001441F-page 74  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: ADC Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2011-2015 Microchip Technology Inc. DS40001441F-page 75

PIC12(L)F1840 REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 OSFIF — C1IF EEIF BCL1IF — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 Unimplemented: Read as ‘0’ bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2-0 Unimplemented: Read as ‘0’ Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 145 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 74 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 76 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. DS40001441F-page 76  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 9.0 POWER-DOWN MODE (SLEEP) 9.1 Wake-up from Sleep The Power-Down mode is entered by executing a The device can wake-up from Sleep through one of the SLEEP instruction. following events: Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled exist: 2. BOR Reset, if enabled 1. WDT will be cleared but keeps running, if 3. POR Reset enabled for operation during Sleep. 4. Watchdog Timer, if enabled 2. PD bit of the STATUS register is cleared. 5. Any external interrupt 3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running 4. CPU clock is disabled. during Sleep (see individual peripheral for more 5. 31 kHz LFINTOSC is unaffected and peripherals information) that operate from it may continue operation in The first three events will cause a device Reset. The Sleep. last three events are considered a continuation of 6. Timer1 and peripherals that operate from program execution. To determine whether a device Timer1 continue operation in Sleep when the Reset or wake-up event occurred, refer to Section7.11 Timer1 clock source selected is: “Determining the Cause of a Reset”. • T1CKI When the SLEEP instruction is being executed, the next • Timer1 oscillator instruction (PC + 1) is prefetched. For the device to • CapSense oscillator wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will 7. ADC is unaffected, if the dedicated FRC oscillator occur regardless of the state of the GIE bit. If the GIE is selected. bit is disabled, the device continues execution at the 8. Capacitive Sensing oscillator is unaffected. instruction after the SLEEP instruction. If the GIE bit is 9. I/O ports maintain the status they had before enabled, the device executes the instruction after the SLEEP was executed (driving high, low or high- SLEEP instruction, the device will then call the Interrupt impedance). Service Routine. In cases where the execution of the 10. Resets other than WDT are not affected by instruction following SLEEP is not desirable, the user Sleep mode. should have a NOP after the SLEEP instruction. Refer to individual chapters for more details on The WDT is cleared when the device wakes up from peripheral operation during Sleep. Sleep, regardless of the source of wake-up. To minimize current consumption, the following conditions should be considered: • I/O pins should not be floating • External circuitry sinking current from I/O pins • Internal circuitry sourcing current from I/O pins • Current draw from pins with internal weak pull-ups • Modules using 31 kHz LFINTOSC • Modules using Timer1 oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section17.0 “Digital-to-Analog Converter (DAC) Module” and Section14.0 “Fixed Voltage Reference (FVR)” for more information on these modules.  2011-2015 Microchip Technology Inc. DS40001441F-page 77

PIC12(L)F1840 9.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execution of a SLEEP instruction When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit - SLEEP instruction will be completely and interrupt flag bit set, one of the following will occur: executed - Device will immediately wake-up from Sleep • If the interrupt occurs before the execution of a SLEEP instruction - WDT and WDT prescaler will be cleared - SLEEP instruction will execute as a NOP. - TO bit of the STATUS register will be set - WDT and WDT prescaler will not be cleared - PD bit of the STATUS register will be cleared. - TO bit of the STATUS register will not be set Even if the flag bits were checked before executing a - PD bit of the STATUS register will not be SLEEP instruction, it may be possible for flag bits to cleared. become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 9-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(2) T1OSC(3) Interrupt flag Interrupt Latency(4) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h IFnesttcrhuectdion Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC - 1) Sleep Inst(PC + 1) Forced NOP Forced NOP Inst(0004h) Note 1: XT, HS or LP Oscillator mode assumed. 2: CLKOUT is shown here for timing reference. 3: T1OSC; See Section30.0 “Electrical Specifications”. 4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. DS40001441F-page 78  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 9.2 Low-Power Sleep Mode 9.2.2 PERIPHERAL USAGE IN SLEEP The PIC12F1840 device contains an internal Low Some peripherals that can operate in Sleep mode will Dropout (LDO) voltage regulator, which allows the not operate properly with the Low-Power Sleep mode device I/O pins to operate at voltages up to 5.5V while selected. The LDO will remain in the normal power the internal device logic operates at a lower voltage. mode when those peripherals are enabled. The Low- The LDO and its associated reference circuitry must Power Sleep mode is intended for use with these remain active when the device is in Sleep mode. The peripherals: PIC12F1840 allows the user to optimize the operating • Brown-Out Reset (BOR) current in Sleep, depending on the application • Watchdog Timer (WDT) requirements. • External interrupt pin/Interrupt-on-change pins A Low-Power Sleep mode can be selected by setting • Timer1 (with external clock source) the VREGPM bit of the VREGCON register. With this • Comparator bit set, the LDO and reference circuitry are placed in a • ECCP (Capture mode) low-power state when the device is in Sleep. 9.2.1 SLEEP CURRENT VS. WAKE-UP Note: The PIC12LF1840 does not have a con- TIME figurable Low-Power Sleep mode. In the default operating mode, the LDO and reference PIC12LF1840 is an unregulated device circuitry remain in the normal configuration while in and is always in the lowest power state Sleep. The device is able to exit Sleep mode quickly when in Sleep, with no wake-up time pen- since all circuits remain active. In Low-Power Sleep alty. This device has a lower maximum mode, when waking up from Sleep, an extra delay time VDD and I/O voltage than the is required for these circuits to return to the normal PIC12F1840. See Section30.0 “Electri- configuration and stabilize. cal Specifications” for more information. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently.  2011-2015 Microchip Technology Inc. DS40001441F-page 79

PIC12(L)F1840 9.3 Register Definitions: Voltage Regulator Control REGISTER 9-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal-Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. Note 1: PIC12F1840 only. 2: See Section30.0 “Electrical Specifications”. TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 107 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 107 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 107 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 74 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 76 STATUS — — — TO PD Z DC C 15 VREGCON(1) — — — — — — VREGPM Reserved 80 WDTCON — — WDTPS<4:0> SWDTEN 83 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. Note 1: PIC12F1840 only. DS40001441F-page 80  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 10.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (nominal) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0>=01 SWDTEN 23-bit Programmable WDTE<1:0>=11 LFINTOSC WDT Time-out Prescaler WDT WDTE<1:0>=10 Sleep WDTPS<4:0>  2011-2015 Microchip Technology Inc. DS40001441F-page 81

PIC12(L)F1840 10.1 Independent Clock Source 10.3 Time-out Period The WDT derives its time base from the 31kHz The WDTPS bits of the WDTCON register set the LFINTOSC internal oscillator. Time intervals in this time-out period from 1ms to 256 seconds (nominal). chapter are based on a nominal interval of 1ms. See After a Reset, the default time-out period is two Section30.0 “Electrical Specifications” for the seconds. LFINTOSC tolerances. 10.4 Clearing the WDT 10.2 WDT Operating Modes The WDT is cleared when any of the following The Watchdog Timer module has four operating modes conditions occur: controlled by the WDTE<1:0> bits in Configuration • Any Reset Words. See Table10-1. • CLRWDT instruction is executed 10.2.1 WDT IS ALWAYS ON • Device enters Sleep • Device wakes up from Sleep When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on. • Oscillator fail • WDT is disabled WDT protection is active during Sleep. • OST is running 10.2.2 WDT IS OFF IN SLEEP See Table10-2 for more information. When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep. 10.5 Operation During Sleep WDT protection is not active during Sleep. When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes 10.2.3 WDT CONTROLLED BY SOFTWARE counting. When the WDTE bits of Configuration Words are set to When the device exits Sleep, the WDT is cleared ‘01’, the WDT is controlled by the SWDTEN bit of the again. The WDT remains clear until the OST, if WDTCON register. enabled, completes. See Section5.0 “Oscillator WDT protection is unchanged by Sleep. See Module (with Fail-Safe Clock Monitor)” for more Table10-1 for more details. information on the OST. When a WDT time-out occurs while the device is in TABLE 10-1: WDT OPERATING MODES Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits Device WDT WDTE<1:0> SWDTEN in the STATUS register are changed to indicate the Mode Mode event. See Section3.0 “Memory Organization” and 11 X X Active The STATUS register (Register3-1) for more information. Awake Active 10 X Sleep Disabled 1 X Active 01 0 X Disabled 00 X X Disabled TABLE 10-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0>=00 WDTE<1:0>=01 and SWDTEN = 0 WDTE<1:0>=10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) Unaffected DS40001441F-page 82  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 10.6 Register Definitions: Watchdog Control REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS<4:0> SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) • • • 10011 = Reserved. Results in minimum interval (1:32) 10010 = 1:8388608 (223) (Interval 256s nominal) 10001 = 1:4194304 (222) (Interval 128s nominal) 10000 = 1:2097152 (221) (Interval 64s nominal) 01111 = 1:1048576 (220) (Interval 32s nominal) 01110 = 1:524288 (219) (Interval 16s nominal) 01101 = 1:262144 (218) (Interval 8s nominal) 01100 = 1:131072 (217) (Interval 4s nominal) 01011 = 1:65536 (Interval 2s nominal) (Reset value) 01010 = 1:32768 (Interval 1s nominal) 01001 = 1:16384 (Interval 512ms nominal) 01000 = 1:8192 (Interval 256ms nominal) 00111 = 1:4096 (Interval 128ms nominal) 00110 = 1:2048 (Interval 64ms nominal) 00101 = 1:1024 (Interval 32ms nominal) 00100 = 1:512 (Interval 16ms nominal) 00011 = 1:256 (Interval 8ms nominal) 00010 = 1:128 (Interval 4ms nominal) 00001 = 1:64 (Interval 2ms nominal) 00000 = 1:32 (Interval 1ms nominal) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored.  2011-2015 Microchip Technology Inc. DS40001441F-page 83

PIC12(L)F1840 TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 53 STATUS — — — TO PD Z DC C 15 WDTCON — — WDTPS<4:0> SWDTEN 83 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 33 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer. DS40001441F-page 84  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 11.0 DATA EEPROM AND FLASH 11.1 EEADRL and EEADRH Registers PROGRAM MEMORY The EEADRH:EEADRL register pair can address up to CONTROL a maximum of 256bytes of data EEPROM or up to a maximum of 32K words of program memory. The data EEPROM and Flash program memory are readable and writable during normal operation (full VDD When selecting a program address value, the MSB of range). These memories are not directly mapped in the the address is written to the EEADRH register and the register file space. Instead, they are indirectly LSB is written to the EEADRL register. When selecting addressed through the Special Function Registers a EEPROM address value, only the LSB of the address (SFRs). There are six SFRs used to access these is written to the EEADRL register. memories: 11.1.1 EECON1 AND EECON2 REGISTERS • EECON1 EECON1 is the control register for EE memory • EECON2 accesses. • EEDATL Control bit EEPGD determines if the access will be a • EEDATH program or data memory access. When clear, any • EEADRL subsequent operations will operate on the EEPROM • EEADRH memory. When set, any subsequent operations will When interfacing the data memory block, EEDATL operate on the program memory. On Reset, EEPROM is holds the 8-bit data for read/write, and EEADRL holds selected by default. the address of the EEDATL location being accessed. Control bits RD and WR initiate read and write, These devices have 256 bytes of data EEPROM with respectively. These bits cannot be cleared, only set, in an address range from 0h to 0FFh. software. They are cleared in hardware at completion When accessing the program memory block, the of the read or write operation. The inability to clear the EEDATH:EEDATL register pair forms a 2-byte word WR bit in software prevents the accidental, premature that holds the 14-bit data for read/write, and the termination of a write operation. EEADRL and EEADRH registers form a 2-byte word The WREN bit, when set, will allow a write operation to that holds the 15-bit address of the program memory occur. On power-up, the WREN bit is clear. The location being read. WRERR bit is set when a write operation is interrupted The EEPROM data memory allows byte read and write. by a Reset during normal operation. In these situations, An EEPROM byte write automatically erases the following Reset, the user can check the WRERR bit location and writes the new data (erase before write). and execute the appropriate error handling routine. The write time is controlled by an on-chip timer. The Interrupt flag bit EEIF of the PIR2 register is set when write/erase voltages are generated by an on-chip write is complete. It must be cleared in the software. charge pump rated to operate over the voltage range of Reading EECON2 will read all ‘0’s. The EECON2 the device for byte or word operations. register is used exclusively in the data EEPROM write Depending on the setting of the Flash Program sequence. To enable writes, a specific pattern must be Memory Self Write Enable bits WRT<1:0> of the written to EECON2. Configuration Words, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.  2011-2015 Microchip Technology Inc. DS40001441F-page 85

PIC12(L)F1840 11.2 Using the Data EEPROM 11.2.2 WRITING TO THE DATA EEPROM MEMORY The data EEPROM is a high-endurance, byte addressable array that has been optimized for the To write an EEPROM data location, the user must first storage of frequently changing information (e.g., write the address to the EEADRL register and the data program variables or other data that are updated to the EEDATL register. Then the user must follow a often). When variables in one section change specific sequence to initiate the write for each byte. frequently, while variables in another section do not The write will not initiate if the above sequence is not change, it is possible to exceed the total number of followed exactly (write 55h to EECON2, write AAh to write cycles to the EEPROM without exceeding the EECON2, then set the WR bit) for each byte. Interrupts total number of write cycles to a single byte. Refer to should be disabled during this codesegment. Section30.0 “Electrical Specifications”. If this is the Additionally, the WREN bit in EECON1 must be set to case, then a refresh of the array must be performed. enable write. This mechanism prevents accidental For this reason, variables that change infrequently writes to data EEPROM due to errant (unexpected) (such as constants, IDs, calibration, etc.) should be code execution (i.e., lost programs). The user should stored in Flash program memory. keep the WREN bit clear at all times, except when 11.2.1 READING THE DATA EEPROM updating EEPROM. The WREN bit is not cleared byhardware. MEMORY After a write sequence has been initiated, clearing the To read a data memory location, the user must write the WREN bit will not affect this write cycle. The WR bit will address to the EEADRL register, clear the EEPGD and be inhibited from being set unless the WREN bit is set. CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next At the completion of the write cycle, the WR bit is cycle, in the EEDATL register; therefore, it can be read cleared in hardware and the EE Write Complete in the next instruction. EEDATL will hold this value until Interrupt Flag bit (EEIF) is set. The user can either another read or until it is written to by the user (during enable this interrupt or poll this bit. EEIF must be a write operation). cleared by software. 11.2.3 PROTECTION AGAINST SPURIOUS EXAMPLE 11-1: DATA EEPROM READ WRITE BANKSELEEADRL ; MOVLW DATA_EE_ADDR ; There are conditions when the user may not want to MOVWF EEADRL ;Data Memory write to the data EEPROM memory. To protect against ;Address to read spurious EEPROM writes, various mechanisms have BCF EECON1, CFGS ;Deselect Config space been built-in. On power-up, WREN is cleared. Also, the BCF EECON1, EEPGD;Point to DATA memory Power-up Timer (64ms duration) prevents EEPROM BSF EECON1, RD ;EE Read write. MOVF EEDATL, W ;W = EEDATL The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out Note: Data EEPROM can be read regardless of • Power Glitch the setting of the CPD bit. • Software Malfunction 11.2.4 DATA EEPROM OPERATION DURING CODE-PROTECT Data memory can be code-protected by programming the CPD bit in the Configuration Words to ‘0’. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. DS40001441F-page 86  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 EXAMPLE 11-2: DATA EEPROM WRITE BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATL ;Data Memory Value to write BCF EECON1, CFGS ;Deselect Configuration space BCF EECON1, EEPGD ;Point to DATA memory BSF EECON1, WREN ;Enable writes BCF INTCON, GIE ;Disable INTs. MOVLW 55h ; RequiredSequence MMMBOOOSVVVFWLWFWF E0EEEAEECACCOhOONNN221, WR ;;;;WWSerriit ttWeeR 5Ab5Aihht to begin write BSF INTCON, GIE ;Enable Interrupts BCF EECON1, WREN ;Disable writes BTFSC EECON1, WR ;Wait for write to complete GOTO $-2 ;Done FIGURE 11-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 EEADRH,EEADRL PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) EEDATH,EEDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC - 1) BSF EECON1,RD INSTR(PC + 1) Forced NOP INSTR(PC + 3) INSTR(PC + 4) executed here executed here executed here executed here executed here executed here RD bit EEDATH EEDATL Register  2011-2015 Microchip Technology Inc. DS40001441F-page 87

PIC12(L)F1840 11.3 Flash Program Memory Overview 11.3.1 READING THE FLASH PROGRAM MEMORY It is important to understand the Flash program memory structure for erase and programming To read a program memory location, the user must: operations. Flash program memory is arranged in 1. Write the Least and Most Significant address rows. A row consists of a fixed number of 14-bit bits to the EEADRH:EEADRL register pair. program memory words. A row is the minimum block 2. Clear the CFGS bit of the EECON1 register. size that can be erased by user software. 3. Set the EEPGD control bit of the EECON1 Flash program memory may only be written or erased register. if the destination address is in a segment of memory 4. Then, set control bit RD of the EECON1 register. that is not write-protected, as defined in bits WRT<1:0> Once the read control bit is set, the program memory of Configuration Words. Flash controller will use the second instruction cycle to After a row has been erased, the user can reprogram read the data. This causes the second instruction all or a portion of this row. Data to be written into the immediately following the “BSF EECON1,RD” instruction program memory row is written to 14-bit wide data write to be ignored. The data is available in the very next cycle, latches. These write latches are not directly accessible in the EEDATH:EEDATL register pair; therefore, it can to the user, but may be loaded via sequential writes to be read as two bytes in the following instructions. the EEDATH:EEDATL register pair. EEDATH:EEDATL register pair will hold this value until Note: If the user wants to modify only a portion another read or until it is written to by the user. of a previously programmed row, then the Note1: The two instructions following a program contents of the entire row must be read and saved in RAM prior to the erase. memory read are required to be NOPs. This prevents the user from executing a The number of data write latches may not be equivalent two-cycle instruction on the next to the number of row locations. During programming, instruction after the RD bit is set. user software may need to fill the set of write latches 2: Flash program memory can be read and initiate a programming operation multiple times in regardless of the setting of the CP bit. order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. The size of a program memory row and the number of program memory write latches may vary by device. See Table11-1 for details. TABLE 11-1: FLASH MEMORY ORGANIZATION BY DEVICE Erase Block Number of Device (Row) Size/ Write Latches/ Boundary Boundary PIC12(L)F1840 32 words, 32 words, EEADRL<4:0> EEADRL<4:0> = 00000 = 00000 DS40001441F-page 88  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 EXAMPLE 11-3: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI: PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select Bank for EEPROM registers MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address MOVLW PROG_ADDR_HI ; MOVWL EEADRH ; Store MSB of address BCF EECON1,CFGS ; Do not select Configuration Space BSF EECON1,EEPGD ; Select Program Memory BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (Figure 11-1) NOP ; Ignored (Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2011-2015 Microchip Technology Inc. DS40001441F-page 89

PIC12(L)F1840 11.3.2 ERASING FLASH PROGRAM The following steps should be completed to load the MEMORY write latches and program a block of program memory. These steps are divided into two parts. First, all write While executing code, program memory can only be latches are loaded with data except for the last program erased by rows. To erase a row: memory location. Then, the last write latch is loaded 1. Load the EEADRH:EEADRL register pair with and the programming sequence is initiated. A special the address of new row to be erased. unlock sequence is required to load a write latch with 2. Clear the CFGS bit of the EECON1 register. data or initiate a Flash programming operation. This 3. Set the EEPGD, FREE and WREN bits of the unlock sequence should not be interrupted. EECON1 register. 1. Set the EEPGD and WREN bits of the EECON1 4. Write 55h, then AAh, to EECON2 (Flash register. programming unlock sequence). 2. Clear the CFGS bit of the EECON1 register. 5. Set control bit WR of the EECON1 register to 3. Set the LWLO bit of the EECON1 register. When begin the erase operation. the LWLO bit of the EECON1 register is ‘1’, the 6. Poll the FREE bit in the EECON1 register to write sequence will only load the write latches determine when the row erase has completed. and will not initiate the write to Flash program memory. See Example11-4. 4. Load the EEADRH:EEADRL register pair with After the “BSF EECON1,WR” instruction, the processor the address of the location to be written. requires two cycles to set up the erase operation. The 5. Load the EEDATH:EEDATL register pair with user must place two NOP instructions after the WR bit is the program memory data to be written. set. The processor will halt internal operations for the 6. Write 55h, then AAh, to EECON2, then set the typical 2ms erase time. This is not Sleep mode as the WR bit of the EECON1 register (Flash clocks and peripherals will continue to run. After the programming unlock sequence). The write latch erase cycle, the processor will resume operation with is now loaded. the third instruction after the EECON1 write instruction. 7. Increment the EEADRH:EEADRL register pair 11.3.3 WRITING TO FLASH PROGRAM to point to the next location. MEMORY 8. Repeat steps 5 through 7 until all but the last Program memory is programmed using the following write latch has been loaded. steps: 9. Clear the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is 1. Load the starting address of the word(s) to be ‘0’, the write sequence will initiate the write to programmed. Flash program memory. 2. Load the write latches with data. 10. Load the EEDATH:EEDATL register pair with 3. Initiate a programming operation. the program memory data to be written. 4. Repeat steps 1 through 3 until all data is written. 11. Write 55h, then AAh, to EECON2, then set the Before writing to program memory, the word(s) to be WR bit of the EECON1 register (Flash written must be erased or previously unwritten. programming unlock sequence). The entire Program memory can only be erased one row at a time. latch block is now written to Flash program No automatic erase occurs upon the initiation of the memory. write. It is not necessary to load the entire write latch block Program memory can be written one or more words at with user program data. However, the entire write latch a time. The maximum number of words written at one block will be written to program memory. time is equal to the number of write latches. See An example of the complete write sequence for 32 Figure11-2 (block writes to program memory with 32 words is shown in Example11-5. The initial address is write latches) for more details. The write latches are loaded into the EEADRH:EEADRL register pair; the 32 aligned to the address boundary defined by EEADRL words of data are loaded using indirect addressing. as shown in Table11-1. Write operations do not cross these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF. DS40001441F-page 90  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 After the “BSF EECON1,WR” instruction, the processor continue to run. The processor does not stall when requires two cycles to set up the write operation. The LWLO = 1, loading the write latches. After the write user must place two NOP instructions after the WR bit is cycle, the processor will resume operation with the third set. The processor will halt internal operations for the instruction after the EECON1 WRITE instruction. typical 2ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will FIGURE 11-2: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 7 5 0 7 0 EEDATH EEDATA 6 8 First word of block Last word of block to be written to be written 14 14 14 14 EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 EEADRL<4:0> = 00010 EEADRL<4:0> = 11111 Buffer Register Buffer Register Buffer Register Buffer Register Program Memory EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF EEADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF EEADRH BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,FREE ; Specify an erase operation BSF EECON1,WREN ; Enable writes MOVLW 55h ; Start of required sequence to initiate erase MOVWF EECON2 ; Write 55h MOVLW 0AAh ; RequiredSequence MBNOSOVFPW F EEEECCOONN21 ,WR ;;;; WSAhrenaitylt teWis Rn A stAbtohir tub cettgoii onbn eseg rihanes reee r saaesrqeeu eingcneored as processor NOP ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts  2011-2015 Microchip Technology Inc. DS40001441F-page 91

PIC12(L)F1840 EXAMPLE 11-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; 1. The 64 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F ; BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL EEADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF EEADRH ; MOVF ADDRL,W ; MOVWF EEADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BSF EECON1,EEPGD ; Point to program memory BCF EECON1,CFGS ; Not configuration space BSF EECON1,WREN ; Enable writes BSF EECON1,LWLO ; Only Load Write Latches LOOP MOVIW FSR0++ ; Load first data byte into lower MOVWF EEDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF EEDATH ; MOVF EEADRL,W ; Check if lower bits of address are '00000' XORLW 0x1F ; Check if we're on the last of 32 addresses ANDLW 0x1F ; BTFSC STATUS,Z ; Exit if last of 32 words, GOTO START_WRITE ; MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write to complete. ; After write processor continues with 3rd instruction. INCF EEADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches START_WRITE BCF EECON1,LWLO ; No more loading latches - Actually start Flash program ; memory write MOVLW 55h ; Start of required write sequence: MOVWF EECON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0EEAEEACChOO NN21 ,WR ;;;; WSArenityt eWi RnA sAbthirtu cttoi obnesg ihne rwer iatree ignored as processor ; halts to begin write sequence NOP ; Processor will stop here and wait for write complete. ; after write processor continues with 3rd instruction BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts DS40001441F-page 92  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 11.4 Modifying Flash Program Memory 11.5 User ID, Device ID and Configuration Word Access When modifying existing data in a program memory row, and data within that row must be preserved, it must Instead of accessing program memory or EEPROM first be read and saved in a RAM image. Program data memory, the User ID’s, Device ID/Revision ID and memory is modified using the following steps: Configuration Words can be accessed when CFGS=1 1. Load the starting address of the row to be in the EECON1 register. This is the region that would modified. be pointed to by PC<15>=1, but not all addresses are accessible. Different access may exist for reads and 2. Read the existing data from the row into a RAM writes. Refer to Table11-2. image. 3. Modify the RAM image to contain the new data When read access is initiated on an address outside the to be written into program memory. parameters listed in Table11-2, the EEDATH:EEDATL register pair is cleared. 4. Load the starting address of the row to be rewritten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 8. Repeat steps 6 and 7 as many times as required to reprogram the erased row. TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS=1) Address Function Read Access Write Access 8000h-8003h User IDs Yes Yes 8006h Device ID/Revision ID Yes No 8007h-8008h Configuration Words 1 and 2 Yes No EXAMPLE 11-3: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL EEADRL ; Select correct Bank MOVLW PROG_ADDR_LO ; MOVWF EEADRL ; Store LSB of address CLRF EEADRH ; Clear MSB of address BSF EECON1,CFGS ; Select Configuration Space BCF INTCON,GIE ; Disable interrupts BSF EECON1,RD ; Initiate read NOP ; Executed (See Figure 11-1) NOP ; Ignored (See Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2011-2015 Microchip Technology Inc. DS40001441F-page 93

PIC12(L)F1840 11.6 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example11-6) to the desired value to be written. Example11-6 shows how to verify a write to EEPROM. EXAMPLE 11-6: EEPROM WRITE VERIFY BANKSELEEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL, W ; BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue DS40001441F-page 94  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 11.7 Register Definitions: EEPROM and Flash Control REGISTER 11-1: EEDATL: EEPROM DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u EEDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory REGISTER 11-2: EEDATH: EEPROM DATA HIGH BYTE REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — EEDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 EEDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 11-3: EEADRL: EEPROM ADDRESS REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address REGISTER 11-4: EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 —(1) EEADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address Note 1: Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001441F-page 95

PIC12(L)F1840 REGISTER 11-5: EECON1: EEPROM CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 EEPGD CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory bit 5 LWLO: Load Write Latches Only bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS=0 and EEPGD=0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM. bit 4 FREE: Program Flash Erase Enable bit If CFGS=1 (Configuration space) OR CFGS=0 and EEPGD=1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after comple- tion of erase). 0 = Performs a write operation on the next WR command. If EEPGD=0 and CFGS=0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle. bit 3 WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally. bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM bit 1 WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. bit 0 RD: Read Control bit 1 = Initiates a program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read. DS40001441F-page 96  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 EEPROM Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section11.2.2 “Writing to the Data EEPROM Memory” for more information. TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 96 EECON2 EEPROM Control Register 2 (not a physical register) 97* EEADRL EEADRL<7:0> 95 EEADRH —(1) EEADRH<6:0 95 EEDATL EEDATL<7:0> 95 EEDATH — — EEDATH<5:0> 95 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 74 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 76 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Data EEPROM module. * Page provides register information. Note 1: Unimplemented, read as ‘1’.  2011-2015 Microchip Technology Inc. DS40001441F-page 97

PIC12(L)F1840 12.0 I/O PORTS 12.1 Alternate Pin Function In general, when a peripheral is enabled, that pin may The Alternate Pin Function Control (APFCON) register not be used as a general purpose I/O pin. is used to steer specific peripheral input and output functions between different pins. The APFCON register The port has three registers for its operation. These is shown in Register12-1. For this device family, the registers are: following functions can be moved between different • TRISA register (data direction register) pins. • PORTA register (reads the levels on the pins of • RX/DT the device) • TX/CK • LATA register (output latch) • SDO PORTA has the following additional registers. They • SS (Slave Select) are: • T1G • ANSELA (analog select) • P1B • WPUA (weak pull-up) • CCP1/P1A The Data Latch (LATA register) is useful for These bits have no effect on the values of any TRIS read-modify-write operations on the value that the I/O register. PORT and TRIS overrides will be routed to the pins are driving. correct pin. The unselected pin will be unaffected. A write operation to the LATA register has the same affect as a write to the corresponding PORTA register. A read of the LATA register reads of the values held in the I/O PORT latches, while a read of the PORTA register reads the actual I/O pin value. The port has analog functions and has an ANSELA. register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure12-1. FIGURE 12-1: GENERIC I/O PORT OPERATION Read LATx TRISx D Q Write LATx Write PORTx CK VDD Data Register Data Bus I/O pin Read PORTx To digital peripherals VSS ANSELx To analog peripherals DS40001441F-page 98  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RXDTSEL: Pin Selection bit 1 = RX/DT function is on RA5 0 = RX/DT function is on RA1 bit 6 SDOSEL: Pin Selection bit 1 = SDO function is on RA4 0 = SDO function is on RA0 bit 5 SSSEL: Pin Selection bit 1 = SS function is on RA0 0 = SS function is on RA3 bit 4 Unimplemented: Read as ‘0’ bit 3 T1GSEL: Pin Selection bit 1 = T1G function is on RA3 0 = T1G function is on RA4 bit 2 TXCKSEL: Pin Selection bit 1 = TX/CK function is on RA4 0 = TX/CK function is on RA0 bit 1 P1BSEL: Pin Selection bit 1 = P1B function is on RA4 0 = P1B function is on RA0 bit 0 CCP1SEL: Pin Selection bit 1 = CCP1/P1A function is on RA5 0 = CCP1/P1A function is on RA2  2011-2015 Microchip Technology Inc. DS40001441F-page 99

PIC12(L)F1840 12.2 PORTA Registers 12.2.1 DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘1’. Example12-1 shows how to initialize PORTA. Reading the PORTA register (Register12-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). 12.2.2 DIRECTION CONTROL The TRISA register (Register12-3) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. 12.2.3 ANSELA REGISTER The ANSELA register (Register12-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. EXAMPLE 12-1: INITIALIZING PORTA BANKSEL PORTA ; CLRF PORTA ;Init PORTA BANKSEL LATA ;Data Latch CLRF LATA ; BANKSEL ANSELA ; CLRF ANSELA ;digital I/O BANKSEL TRISA ; MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs DS40001441F-page 100  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 12.2.4 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table12-1. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, comparator and CapSense inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode as shown in the priority list. TABLE 12-1: PORTA OUTPUT PRIORITY Pin Name Function Priority(1) RA0 ICSPDAT ICDDAT DACOUT MDOUT TX/CK SDO P1B RA1 ICSPCLK ICDCLK SCL RX/DT SCK RA2 SRQ C1OUT SDA CCP1/P1A RA3 No output priorities. Input only pin. RA4 OSC2 CLKOUT T1OSO CLKR TX/CK SDO P1B RA5 OSC1 T1OSI SRNQ RX/DT CCP1/P1A Note 1: Priority listed from highest to lowest.  2011-2015 Microchip Technology Inc. DS40001441F-page 101

PIC12(L)F1840 12.3 Register Definitions: PORTA REGISTER 12-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0 bit 5-4 TRISA<5:4>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 TRISA3: RA3 Port Tri-State Control bit This bit is always ‘1’ as RA3 is an input only bit 2-0 TRISA<2:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output DS40001441F-page 102  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented: Read as ‘0’ bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — ANSA4 — ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 3 Unimplemented: Read as ‘0’ bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.  2011-2015 Microchip Technology Inc. DS40001441F-page 103

PIC12(L)F1840 REGISTER 12-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(1, 2) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in configured as an output. TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 APFCON RXDTSEL SDOSEL SSSEL --- T1GSEL TXCKSEL P1BSEL CCP1SEL 99 LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 103 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 145 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 102 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 104 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. TABLE 12-3: SUMMARY OF CONFIGURATION WORD WITH PORTA Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> CPD CONFIG1 33 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. DS40001441F-page 104  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 13.0 INTERRUPT-ON-CHANGE 13.3 Interrupt Flags The PORTA pins can be configured to operate as The IOCAFx bits located in the IOCAF register are Interrupt-On-Change (IOC) pins. An interrupt can be status flags that correspond to the Interrupt-on-change generated by detecting a signal that has either a rising pins of PORTA. If an expected edge is detected on an edge or a falling edge. Any individual PORTA pin, or appropriately enabled pin, then the status flag for that pin combination of PORTA pins, can be configured to will be set, and an interrupt will be generated if the IOCIE generate an interrupt. The interrupt-on-change module bit is set. The IOCIF bit of the INTCON register reflects has the following features: the status of all IOCAFx bits. • Interrupt-on-Change enable (Master Switch) 13.4 Clearing Interrupt Flags • Individual pin configuration • Rising and falling edge detection The individual status flags, (IOCAFx bits), can be • Individual pin interrupt flags cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated Figure13-1 is a block diagram of the IOC module. status flag will be set at the end of the sequence, regardless of the value actually being written. 13.1 Enabling the Module In order to ensure that no detected edge is lost while To allow individual PORTA pins to generate an interrupt, clearing flags, only AND operations masking out known the IOCIE bit of the INTCON register must be set. If the changed bits should be performed. The following IOCIE bit is disabled, the edge detection on the pin will sequence is an example of what should be performed. still occur, but an interrupt will not be generated. EXAMPLE 13-1: CLEARING INTERRUPT 13.2 Individual Pin Configuration FLAGS (PORTA EXAMPLE) For each PORTA pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a MOVLW 0xff rising edge, the associated IOCAPx bit of the IOCAP XORWF IOCAF, W register is set. To enable a pin to detect a falling edge, ANDWF IOCAF, F the associated IOCANx bit of the IOCAN register is set. A pin can be configured to detect rising and falling 13.5 Operation in Sleep edges simultaneously by setting both the IOCAPx bit and the IOCANx bit of the IOCAP and IOCAN registers, The interrupt-on-change interrupt sequence will wake respectively. the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCAF register will be updated prior to the first instruction executed out of Sleep.  2011-2015 Microchip Technology Inc. DS40001441F-page 105

PIC12(L)F1840 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCANx D Q Q4Q1 CK Edge Detect R RAx Data Bus = S To Data Bus IOCAPx D Q 0 or 1 D Q IOCAFx CK write IOCAFx CK IOCIE R Q2 From all other IOCAFx individual IOC Interrupt Pin Detectors to CPU core Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q4 Q4 Q4Q1 Q4Q1 Q4Q1 Q4Q1 DS40001441F-page 106  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 13.6 Register Definitions: Interrupt-on-Change Control REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx=1 and a rising edge was detected on RAx, or when IOCANx=1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change.  2011-2015 Microchip Technology Inc. DS40001441F-page 107

PIC12(L)F1840 TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 107 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 107 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 107 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. DS40001441F-page 108  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 14.0 FIXED VOLTAGE REFERENCE 14.1 Independent Gain Amplifiers (FVR) The output of the FVR supplied to the ADC, Comparators, DAC and CPS module is routed through The Fixed Voltage Reference, or FVR, is a stable two independent programmable gain amplifiers. Each voltage reference, independent of VDD, with 1.024V, amplifier can be programmed for a gain of 1x, 2x or 4x, 2.048V or 4.096V selectable output levels. The output to produce the three possible voltage levels. of the FVR can be configured to supply a reference voltage to the following: The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings • ADC input channel for the reference supplied to the ADC module. Refer- • ADC positive reference ence Section16.0 “Analog-to-Digital Converter • Comparator positive input (ADC) Module” for additional information. • Digital-to-Analog Converter (DAC) The CDAFVR<1:0> bits of the FVRCON register are • Capacitive Sensing (CPS) module used to enable and configure the gain amplifier settings The FVR can be enabled by setting the FVREN bit of for the reference supplied to the Comparators, DAC, the FVRCON register. and CPS module. Reference Section17.0 “Digital-to- Analog Converter (DAC) Module”, Section19.0 “Comparator Module” and Section17.0 “Digital-to- Analog Converter (DAC) Module” for additional information. 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section30.0 “Electrical Specifications” for the minimum delay requirement. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 X1 X2 FVR_buffer1 X4 (To ADC Module) CDAFVR<1:0> 2 X1 X2 FVR_buffer2 X4 (To Comparators, DAC, CPS) + FVREN _ FVRRDY Any peripheral requiring the Fixed Reference (See Figure14-1)  2011-2015 Microchip Technology Inc. DS40001441F-page 109

PIC12(L)F1840 TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral Conditions Description HFINTOSC FOSC<2:0> = 100 and INTOSC is active and device is not in Sleep. IRCF<3:0> = 000x BOREN<1:0> = 11 BOR always enabled. BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled. LDO All PIC12F1840 devices, when The device runs off of the low-power regulator when in Sleep VREGPM = 1 and not in Sleep mode. DS40001441F-page 110  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 14.3 Register Definitions: FVR Control REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVREN FVRRDY(1) TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bits 11 =Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 =Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 =Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 =Comparator, DAC and CPS module Fixed Voltage Reference Peripheral output is off bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bits 11 =ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 =ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 =ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 =ADC Fixed Voltage Reference Peripheral output is off Note 1: FVRRDY is always ‘1’ on PIC12F1840 only. 2: Fixed Voltage Reference output cannot exceed VDD. 3: See Section15.0 “Temperature Indicator Module” for additional information. TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 111 Legend: Shaded cells are unused by the Fixed Voltage Reference module.  2011-2015 Microchip Technology Inc. DS40001441F-page 111

PIC12(L)F1840 15.0 TEMPERATURE INDICATOR FIGURE 15-1: TEMPERATURE CIRCUIT MODULE DIAGRAM This family of devices is equipped with a temperature circuit designed to measure the operating temperature VDD of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The TSEN output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A one- point calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point VOUT To ADC calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process. 15.1 Circuit Operation 15.2 Minimum Operating VDD Figure15-1 shows a simplified block diagram of the When the temperature circuit is operated in low range, temperature circuit. The proportional voltage output is the device may be operated at any operating voltage achieved by measuring the forward voltage drop across that is within specifications. multiple silicon junctions. When the temperature circuit is operated in high range, Equation15-1 describes the output characteristics of the device operating voltage, VDD, must be high the temperature indicator. enough to ensure that the temperature circuit is correctly biased. EQUATION 15-1: VOUT RANGES Table15-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT TABLE 15-1: RECOMMENDED VDD VS. Low Range: VOUT = VDD - 2VT RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 The temperature sense circuit is integrated with the 3.6V 1.8V Fixed Voltage Reference (FVR) module. See Section14.0 “Fixed Voltage Reference (FVR)” for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. DS40001441F-page 112  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 15.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section16.0 “Analog-to-Digital Converter (ADC) Module” for detailed information. Note: Every time the ADC MUX is changed to the temperature indicator output selection (CHS bit in the ADCCON0 register), wait 500 sec for the sampling capacitor to fully charge before sampling the temperature indicator output. 15.3.1 ADC ACQUISITION TIME To ensure accurate temperature measurements, the user must wait at least 200 usec after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 usec between sequential conversions of the temperature indicator output. TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 111 Legend: Shaded cells are unused by the temperature indicator module.  2011-2015 Microchip Technology Inc. DS40001441F-page 113

PIC12(L)F1840 16.0 ANALOG-TO-DIGITAL The ADC can generate an interrupt upon completion of CONVERTER (ADC) MODULE a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure16-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF = 00 ADPREF = 11 VREF ADPREF = 10 AN0 00000 AN1 00001 AN2 00010 AN3 00011 Ref+ Ref- ADC GO/DONE 10 Temp Indicator 11101 DAC_output 11110 0 = Left Justify ADFM FVR Buffer1 11111 1 = Right Justify ADON(1) 16 VSS ADRESH ADRESL CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. DS40001441F-page 114  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 16.1 ADC Configuration 16.1.4 CONVERSION CLOCK When configuring and using the ADC the following The source of the conversion clock is software functions must be considered: selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • Port configuration • FOSC/2 • Channel selection • FOSC/4 • ADC voltage reference selection • FOSC/8 • ADC conversion clock source • FOSC/16 • Interrupt control • FOSC/32 • Result formatting • FOSC/64 16.1.1 PORT CONFIGURATION • FRC (dedicated internal FRC oscillator) The ADC can be used to convert both analog and The time to complete one bit conversion is defined as digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD pin should be configured for analog by setting the periods as shown in Figure16-2. associated TRIS and ANSEL bits. Refer to For correct conversion, the appropriate TAD Section12.0 “I/O Ports” for more information. specification must be met. Refer to the ADC conversion Note: Analog voltages on any pin that is defined requirements in Section30.0 “Electrical as a digital input may cause the input Specifications” for more information. Table16-1 gives buffer to conduct excess current. examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the 16.1.2 CHANNEL SELECTION system clock frequency will change the There are seven channel selections available: ADC clock frequency, which may adversely affect the ADC result. • AN<3:0> pins • Temperature Indicator • DAC_output • FVR Buffer1 Output Refer to Section17.0 “Digital-to-Analog Converter (DAC) Module”, Section14.0 “Fixed Voltage Refer- ence (FVR)” and Section15.0 “Temperature Indica- tor Module” for more information on these channel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section16.2 “ADC Operation” for more information. 16.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • VREF+ pin • VDD See Section14.0 “Fixed Voltage Reference (FVR)” for more details on the Fixed Voltage Reference.  2011-2015 Microchip Technology Inc. DS40001441F-page 115

PIC12(L)F1840 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Clock Source Fosc/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s Fosc/4 100 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s Fosc/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3) Fosc/16 101 800 ns 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3) Fosc/32 010 1.0 s 1.6 s 2.0 s 4.0 s 8.0 s(3) 32.0 s(3) Fosc/64 110 2.0 s 3.2 s 4.0 s 8.0 s(3) 16.0 s(3) 64.0 s(3) FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 1.6 s for VDD. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TADTAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS40001441F-page 116  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 16.1.5 INTERRUPTS 16.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit ADC conversion result can be supplied in interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit conversion. The ADC Interrupt Flag is the ADIF bit in of the ADCON1 register controls the output format. the PIR1 register. The ADC Interrupt Enable is the Figure16-3 shows the two output formats. ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruc- tion is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execu- tion, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. FIGURE 16-3: 10-BIT ADC CONVERSION RESULT FORMAT ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit ADC Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit ADC Result  2011-2015 Microchip Technology Inc. DS40001441F-page 117

PIC12(L)F1840 16.2 ADC Operation 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This 16.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC To enable the ADC module, the ADON bit of the option. When the FRC oscillator source is selected, the ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be Analog-to-Digital conversion. executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device Note: The GO/DONE bit should not be set in the will wake-up from Sleep when the conversion same instruction that turns on the ADC. completes. If the ADC interrupt is disabled, the ADC Refer to Section16.2.6 “ADC Conver- module is turned off after the conversion completes, sion Procedure”. although the ADON bit remains set. 16.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than FRC, a SLEEP instruction causes the present When the conversion is complete, the ADC module will: conversion to be aborted and the ADC module is • Clear the GO/DONE bit turned off, although the ADON bit remains set. • Set the ADIF Interrupt Flag bit 16.2.5 SPECIAL EVENT TRIGGER • Update the ADRESH and ADRESL registers with new conversion result The Special Event Trigger of the CCPx/ECCPX module allows periodic ADC measurements without software 16.2.3 TERMINATING A CONVERSION intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to If a conversion must be terminated before completion, zero. the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with TABLE 16-2: SPECIAL EVENT TRIGGER the partially complete Analog-to-Digital conversion Device ECCP1 sample. Incomplete bits will match the last bit converted. PIC12(L)F1840 ECCP1 Note: A device Reset forces all registers to their Using the Special Event Trigger does not assure proper Reset state. Thus, the ADC module is ADC timing. It is the user’s responsibility to ensure that turned off and any pending conversion is the ADC timing requirements are met. terminated. Refer to Section24.0 “Capture/Compare/PWM Modules” for more information. DS40001441F-page 118  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 16.2.6 ADC CONVERSION PROCEDURE EXAMPLE 16-1: ADC CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. 1. Configure Port: ; • Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion register) ; are included. • Configure pin as analog (Refer to the ANSEL ; register) BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, Frc 2. Configure the ADC module: ;clock • Select ADC conversion clock MOVWF ADCON1 ;Vdd and Vss Vref • Configure voltage reference BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input • Select ADC input channel BANKSEL ANSEL ; • Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog 3. Configure ADC interrupt (optional): BANKSEL ADCON0 ; • Clear ADC interrupt flag MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On • Enable ADC interrupt CALL SampleTime ;Acquisiton delay • Enable peripheral interrupt BSF ADCON0,ADGO ;Start conversion • Enable global interrupt(1) BTFSC ADCON0,ADGO ;Is conversion done? 4. Wait the required acquisition time(2). GOTO $-1 ;No, test again BANKSEL ADRESH ; 5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits 6. Wait for ADC conversion to complete by one of MOVWF RESULTHI ;store in GPR space the following: BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits • Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section16.4 “ADC Acquisi- tion Requirements”.  2011-2015 Microchip Technology Inc. DS40001441F-page 119

PIC12(L)F1840 16.3 Register Definitions: ADC Control REGISTER 16-1: ADCON0: ADC CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 11111 =FVR (Fixed Voltage Reference) Buffer 1 Output(2) 11110 =DAC_output(1) 11101 =Temperature Indicator(3). 11100 =Reserved. No channel connected. • • • 00100 =Reserved. No channel connected. 00011 =AN3 00010 =AN2 00001 =AN1 00000 =AN0 bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information. 2: See Section14.0 “Fixed Voltage Reference (FVR)” for more information. 3: See Section15.0 “Temperature Indicator Module” for more information. DS40001441F-page 120  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 16-2: ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> — — ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits 111 =FRC (clock supplied from a dedicated RC oscillator) 110 =FOSC/64 101 =FOSC/16 100 =FOSC/4 011 =FRC (clock supplied from a dedicated RC oscillator) 010 =FOSC/32 001 =FOSC/8 000 =FOSC/2 bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits 11 = VREF is connected to internal Fixed Voltage Reference (FVR) module(1) 10 = VREF is connected to external VREF pin(1) 01 = Reserved 00 = VREF is connected to VDD Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section30.0 “Electrical Specifications” for details.  2011-2015 Microchip Technology Inc. DS40001441F-page 121

PIC12(L)F1840 REGISTER 16-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<1:0> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. DS40001441F-page 122  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 16-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result  2011-2015 Microchip Technology Inc. DS40001441F-page 123

PIC12(L)F1840 16.4 ADC Acquisition Requirements source impedance is decreased, the acquisition time may be decreased. After the analog input channel is For the ADC to meet its specified accuracy, the charge selected (or changed), an ADC acquisition must be holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate charge to the input channel voltage level. The Analog the minimum acquisition time, Equation16-1 may be Input model is shown in Figure16-4. The source used. This equation assumes that 1/2 LSb error is used impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the impedance directly affect the time required to charge maximum error allowed for the ADC to meet its the capacitor CHOLD. The sampling switch (RSS) specified resolution. impedance varies over the device voltage (VDD), refer to Figure16-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 16-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/511) = –12.5pF1k+7k+10k ln(0.001957) 1.72µs Therefore: TACQ = 2µs+1.72µs+50°C- 25°C0.05µs/°C = 4.97µs Note1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification. DS40001441F-page 124  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Sampling Input Switch VT  0.6V Rs pin RIC  1k SS Rss VA C5 PpIFN VT  0.6V I LEAKAGE(1) CHOLD = 12.5 pF VSS/VREF- 6V 5V RSS Legend: CHOLD = Sample/Hold Capacitance VDD4V 3V CPIN = Input Capacitance 2V I LEAKAGE = Leakage current at the pin due to various junctions 5 6 7891011 RIC = Interconnect Resistance Sampling Switch RSS = Resistance of Sampling Switch (k) SS = Sampling Switch VT = Threshold Voltage Note1: Refer to Section30.0 “Electrical Specifications”. FIGURE 16-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh 3FCh e od 3FBh C ut p ut O C D 03h A 02h 01h 00h Analog Input Voltage 0.5 LSB 1.5 LSB Zero-Scale VREF- Transition Full-Scale Transition VREF+  2011-2015 Microchip Technology Inc. DS40001441F-page 125

PIC12(L)F1840 TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS<4:0> GO/DONE ADON 120 ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 121 ADRESH ADC Result Register High 122, 123 ADRESL ADC Result Register Low 122, 123 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 189 DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — — 130 DACCON1 — — — DACR<4:0> 130 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 111 INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. DS40001441F-page 126  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 17.0 DIGITAL-TO-ANALOG 17.1 Output Voltage Selection CONVERTER (DAC) MODULE The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 The Digital-to-Analog Converter supplies a variable register. voltage reference, ratiometric with the input source, with 32 selectable output levels. The DAC output voltage is determined by the following equations: The input of the DAC can be connected to: • External VREF pins • VDD supply voltage • FVR Buffer2 The output of the DAC can be configured to supply a reference voltage to the following: • Comparator positive input • ADC input channel • DACOUT pin • Capacitive Sensing (CPS) module The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register. EQUATION 17-1: DAC OUTPUT VOLTAGE IF DACEN = 1  DACR4:0 VOUT = VSOURCE+–VSOURCE------------------------------ +VSOURCE-  5  2 IF DACEN = 0 & DACLPS = 1 & DACR[4:0] = 11111 VOUT = VSOURCE+ IF DACEN = 0 & DACLPS = 0 & DACR[4:0] = 00000 VOUT = VSOURCE– VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 17.2 Ratiometric Output Level 17.3 DAC Voltage Reference Output The DAC output value is derived using a resistor ladder The DAC can be output to the DACOUT pin by setting with each end of the ladder tied to a positive and the DACOE bit of the DACCON0 register to ‘1’. negative voltage reference input source. If the voltage Selecting the DAC reference voltage for output on the of either input source fluctuates, a similar fluctuation will DACOUT pin automatically overrides the digital output result in the DAC output value. buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been The value of the individual resistors within the ladder configured for DAC reference voltage output will can be found in Section30.0 “Electrical always return a ‘0’. Specifications”. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure17-2 shows an example buffering technique.  2011-2015 Microchip Technology Inc. DS40001441F-page 127

PIC12(L)F1840 FIGURE 17-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR BUFFER2 VSOURCE+ VDD DACR<4:0> 5 VREF R R DACPSS<1:0> 2 R DACEN DACLPS R R X 32 U DAC_output M Steps 1 (To Comparator, CPS and o- ADC Modules) 2-t R 3 R DACOUT R DACOE VSOURCE- VSS FIGURE 17-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC R Module + Voltage DACOUT – Buffered DAC Output Reference Output Impedance DS40001441F-page 128  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 17.4 Low-Power Voltage State This is also the method used to output the voltage level from the FVR to an output pin. See Section17.5 In order for the DAC module to consume the least “Operation During Sleep” for more information. amount of power, one of the two voltage reference input Reference Figure17-3 for output clamping examples. sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSOURCE+), or the 17.4.2 OUTPUT CLAMPED TO NEGATIVE negative voltage source, (VSOURCE-) can be disabled. VOLTAGE SOURCE The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the The DAC output voltage can be set to VSOURCE- with the least amount of power consumption by performing DACLPS bit in the DACCON0 register disables the the following: positive voltage source. • Clearing the DACEN bit in the DACCON0 register. 17.4.1 OUTPUT CLAMPED TO POSITIVE • Clearing the DACLPS bit in the DACCON0 register. VOLTAGE SOURCE • Configuring the DACR<4:0> bits to ‘00000’ in the The DAC output voltage can be set to VSOURCE+ with DACCON1 register. the least amount of power consumption by performing This allows the comparator to detect a zero-crossing the following: while not consuming additional current through the DAC • Clearing the DACEN bit in the DACCON0 register. module. • Setting the DACLPS bit in the DACCON0 register. Reference Figure17-3 for output clamping examples. • Configuring the DACPSS bits to the proper positive source. • Configuring the DACR<4:0> bits to ‘11111’ in the DACCON1 register. FIGURE 17-3: OUTPUT VOLTAGE CLAMPING EXAMPLES Output Clamped to Positive Voltage Source Output Clamped to Negative Voltage Source VSOURCE+ VSOURCE+ R R DACR<4:0> = 11111 R R DACEN = 0 DACEN = 0 DACLPS = 1 DAC Voltage Ladder DACLPS = 0 DAC Voltage Ladder (see Figure17-1) (see Figure17-1) R R DACR<4:0> = 00000 VSOURCE- VSOURCE- 17.5 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 17.6 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared.  2011-2015 Microchip Technology Inc. DS40001441F-page 129

PIC12(L)F1840 17.7 Register Definitions: DAC Control REGISTER 17-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 DACEN DACLPS DACOE — DACPSS<1:0> — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected bit 5 DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 11 = Reserved, do not use 10 = FVR Buffer2 output 01 = VREF pin 00 = VDD bit 1-0 Unimplemented: Read as ‘0’ REGISTER 17-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 111 DACCON0 DACEN DACLPS DACOE — DACPSS<1:0> — — 130 DACCON1 — — — DACR<4:0> 130 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module. DS40001441F-page 130  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 18.0 SR LATCH 18.2 Latch Output The module consists of a single SR latch with multiple The SRQEN and SRNQEN bits of the SRCON0 Set and Reset inputs as well as separate latch outputs. register control the Q and Q latch outputs. Both of the The SR latch module includes the following features: SR latch outputs may be directly output to an I/O pin at the same time. • Programmable input selection The applicable TRIS bit of the corresponding port must • SR latch output is available externally be cleared to enable the port pin output driver. • Separate Q and Q outputs • Firmware Set and Reset 18.3 Effects of a Reset The SR latch can be used in a variety of analog applications, including oscillator circuits, one-shot Upon any device Reset, the SR latch output is not circuit, hysteretic controllers, and analog timing initialized to a known state. The user’s firmware is applications. responsible for initializing the latch output before enabling the output pins. 18.1 Latch Operation The latch is a Set-Reset Latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be set or reset by: • Software control (SRPS and SRPR bits) • Comparator C1 output (sync_C1OUT) • SRI pin • Programmable clock (SRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to set or reset the SR latch, respectively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset oper- ation. The output from Comparator C1 can be used as the Set or Reset inputs of the SR latch. The output of the comparator can be synchronized to the Timer1 clock source. See Section19.0 “Comparator Module” and Section21.0 “Timer1 Module with Gate Control” for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR latch. An internal clock source is available that can periodically set or reset the SR latch. The SRCLK<2:0> bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to set or reset the SR latch, respectively.  2011-2015 Microchip Technology Inc. DS40001441F-page 131

PIC12(L)F1840 FIGURE 18-1: SR LATCH SIMPLIFIED BLOCK DIAGRAM SRLEN SRPS Pulse SRQEN Gen(2) SRI SRSPE S Q SRCLK SRQ SRSCKE sync_C1OUT(3) SRSC1E SR Latch(1) SRPR Pulse Gen(2) SRI SRRPE R Q SRCLK SRNQ SRRCKE SRLEN sync_C1OUT(3) SRNQEN SRRC1E Note 1: If R=1 and S=1 simultaneously, Q=0, Q=1 2: Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. TABLE 18-1: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 32 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 62.5kHz 39.0kHz 31.3kHz 7.81kHz 1.95kHz 110 256 125kHz 78.1kHz 62.5kHz 15.6kHz 3.90kHz 101 128 250kHz 156kHz 125kHz 31.25kHz 7.81kHz 100 64 500kHz 313kHz 250kHz 62.5kHz 15.6kHz 011 32 1MHz 625kHz 500kHz 125kHz 31.3 kHz 010 16 2MHz 1.25MHz 1MHz 250kHz 62.5kHz 001 8 4MHz 2.5MHz 2MHz 500kHz 125kHz 000 4 8MHz 5MHz 4MHz 1MHz 250kHz DS40001441F-page 132  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 18.4 Register Definitions: SR Latch Control REGISTER 18-1: SRCON0: SR LATCH CONTROL 0 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/S-0/0 R/S-0/0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared S = Bit is set only bit 7 SRLEN: SR Latch Enable bit 1 = SR Latch is enabled 0 = SR Latch is disabled bit 6-4 SRCLK<2:0>: SR Latch Clock Divider bits 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock bit 3 SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = External Q output is disabled If SRLEN = 0: SR Latch is disabled bit 2 SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = External Q output is disabled If SRLEN = 0: SR Latch is disabled bit 1 SRPS: Pulse Set Input of the SR Latch bit(1) 1 = Pulse set input for 1 Q-clock period 0 = No effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit(1) 1 = Pulse reset input for 1 Q-clock period 0 = No effect on Reset input. Note 1: Set only, always reads back ‘0’.  2011-2015 Microchip Technology Inc. DS40001441F-page 133

PIC12(L)F1840 REGISTER 18-2: SRCON1: SR LATCH CONTROL 1 REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRSPE SRSCKE Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SR latch is set when the SRI pin is high 0 = SRI pin has no effect on the set input of the SR latch bit 6 SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR latch is pulsed with SRCLK 0 = SRCLK has no effect on the set input of the SR latch bit 5 Reserved: Read as ‘0’. Maintain this bit clear. bit 4 SRSC1E: SR Latch C1 Set Enable bit 1 = SR latch is set when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the set input of the SR latch bit 3 SRRPE: SR Latch Peripheral Reset Enable bit 1 = SR latch is reset when the SRI pin is high 0 = SRI pin has no effect on the reset input of the SR latch bit 2 SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR latch is pulsed with SRCLK 0 = SRCLK has no effect on the reset input of the SR latch bit 1 Reserved: Read as ‘0’. Maintain this bit clear. bit 0 SRRC1E: SR Latch C1 Reset Enable bit 1 = SR latch is reset when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the reset input of the SR latch TABLE 18-2: SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 133 SRCON1 SRSPE SRSCKE Reserved SRSC1E SRRPE SRRCKE Reserved SRRC1E 134 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR Latch module. DS40001441F-page 134  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 19.0 COMPARATOR MODULE FIGURE 19-1: SINGLE COMPARATOR Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and VIN+ + providing a digital indication of their relative magnitudes. Output Comparators are very useful mixed signal building VIN- – blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • Independent comparator control VIN- • Programmable input selection VIN+ • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change Output • Wake-up from Sleep • Programmable Speed/Power optimization • PWM shutdown Note: The black areas of the output of the • Programmable and Fixed Voltage Reference comparator represents the uncertainty 19.1 Comparator Overview due to input offsets and response time. A single comparator is shown in Figure19-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The comparators available for this device are located in Table19-1. TABLE 19-1: COMPARATOR AVAILABILITY PER DEVICE Device C1 PIC12(L)F1840 ●  2011-2015 Microchip Technology Inc. DS40001441F-page 135

PIC12(L)F1840 FIGURE 19-2: COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM C1NCH C1ON(1) 2 Interrupt C1INTP det Set C1IF C1IN0- 0 MUX Interrupt C1INTN (2) det C1IN1- 1 C1POL C1VN - C1OUT C1(3) D Q MC1OUT To Data Bus + C1VP Q1 EN C1IN+ 0 MUX C1HYS DAC_output 1 (2) C1SP To ECCP PWM Logic FVR Buffer2 2 3 C1SYNC VSS C1ON C1OE TRIS bit C1OUT C1PCH<1:0> 0 2 D Q 1 (from Timer1) T1CLK To Timer1 or SR Latch sync_C1OUT Note 1: When C1ON = 0, the Comparator will produce a ‘0’ at the output. 2: When C1ON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging. DS40001441F-page 136  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 19.2 Comparator Control 19.2.3 COMPARATOR OUTPUT POLARITY The comparator has two control registers: CM1CON0 Inverting the output of the comparator is functionally and CM1CON1. equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by The CM1CON0 register (see Register19-1) contains setting the C1POL bit of the CM1CON0 register. Control and Status bits for the following: Clearing the C1POL bit results in a non-inverted output. • Enable Table19-2 shows the output state versus input • Output selection conditions, including polarity control. • Output polarity TABLE 19-2: COMPARATOR OUTPUT • Speed/Power selection STATE VS. INPUT • Hysteresis enable CONDITIONS • Output synchronization Input Condition C1POL C1OUT The CM1CON1 register (see Register19-2) contains C1VN > C1VP 0 0 Control bits for the following: C1VN < C1VP 0 1 • Interrupt enable C1VN > C1VP 1 1 • Interrupt edge polarity C1VN < C1VP 1 0 • Positive input channel selection • Negative input channel selection 19.2.4 COMPARATOR SPEED/POWER SELECTION 19.2.1 COMPARATOR ENABLE The trade-off between speed or power can be Setting the C1ON bit of the CM1CON0 register enables optimized during program execution with the C1SP the comparator for operation. Clearing the C1ON bit control bit. The default state for this bit is ‘1’ which disables the comparator resulting in minimum current selects the normal speed mode. Device power consumption. consumption can be optimized at the cost of slower 19.2.2 COMPARATOR OUTPUT comparator propagation delay by clearing the C1SP bit to ‘0’. SELECTION The output of the comparator can be monitored by reading either the C1OUT bit of the CM1CON0 register or the MC1OUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • C1OE bit of the CM1CON0 register must be set • Corresponding TRIS bit must be cleared • C1ON bit of the CM1CON0 register must be set Note1: The C1OE bit of the CM1CON0 register overrides the PORT data latch. Setting the C1ON bit of the CM1CON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.  2011-2015 Microchip Technology Inc. DS40001441F-page 137

PIC12(L)F1840 19.3 Comparator Hysteresis 19.5 Comparator Interrupt A selectable amount of separation voltage can be An interrupt can be generated upon a change in the added to the input pins of each comparator to provide a output value of the comparator for each comparator, a hysteresis function to the overall operation. Hysteresis rising edge detector and a Falling edge detector are is enabled by setting the C1HYS bit of the CM1CON0 present. register. When either edge detector is triggered and its See Section30.0 “Electrical Specifications” for associated enable bit is set (C1INTP and/or C1INTN more information. bits of the CM1CON1 register), the Corresponding Interrupt Flag bit (C1IF bit of the PIR2 register) will be 19.4 Timer1 Gate Operation set. To enable the interrupt, you must set the following bits: The output resulting from a comparator operation can be used as a source for gate control of Timer1. See • C1ON, C1POL and C1SP bits of the CM1CON0 Section21.6 “Timer1 Gate” for more information. register This feature is useful for timing the duration or interval • C1IE bit of the PIE2 register of an analog event. • C1INTP bit of the CM1CON1 register (for a rising It is recommended that the comparator output be edge detection) synchronized to Timer1. This ensures that Timer1 does • C1INTN bit of the CM1CON1 register (for a falling not increment while a change in the comparator is edge detection) occurring. • PEIE and GIE bits of the INTCON register 19.4.1 COMPARATOR OUTPUT The associated interrupt flag bit, C1IF bit of the PIR2 SYNCHRONIZATION register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still The output from comparator C1 can be synchronized be set at the end of the sequence. with Timer1 by setting the C1SYNC bit of the CM1CON0 register. Note: Although a comparator is disabled, an interrupt can be generated by changing Once enabled, the comparator output is latched on the the output polarity with the C1POL bit of falling edge of the Timer1 source clock. If a prescaler is the CM1CON0 register, or by switching used with Timer1, the comparator output is latched after the comparator on or off with the C1ON bit the prescaling function. To prevent a race condition, the of the CM1CON0 register. comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the 19.6 Comparator Positive Input rising edge of its clock source. See the Comparator Block Diagram (Figure19-2) and the Timer1 Block Selection Diagram (Figure21-1) for more information. Configuring the C1PCH<1:0> bits of the CM1CON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: • C1IN+ analog pin • DAC_output • FVR Buffer2 • VSS (Ground) See Section14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (C1ON = 0), all comparator inputs are disabled. DS40001441F-page 138  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 19.7 Comparator Negative Input 19.10 Analog Input Connection Selection Considerations The C1NCH bit of the CM1CON1 register directs one A simplified circuit for an analog input is shown in of two analog pins to the comparator inverting input. Figure19-3. Since the analog input pins share their connection with a digital input, they have reverse Note: To use C1IN+ and C1INx- pins as analog biased ESD protection diodes to VDD and VSS. The input, the appropriate bits must be set in analog input, therefore, must be between VSS and VDD. the ANSEL register and the correspond- If the input voltage deviates from this range by more ing TRIS bits must also be set to disable than 0.6V in either direction, one of the diodes is the output drivers. forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended 19.8 Comparator Response Time for the analog sources. Also, any external component The comparator output is indeterminate for a period of connected to an analog input pin, such as a capacitor or time after the change of an input source or the selection a Zener diode, should have very little leakage current to of a new reference voltage. This period is referred to as minimize inaccuracies introduced. the response time. The response time of the comparator differs from the settling time of the voltage reference. Note1: When reading a PORT register, all pins Therefore, both of these times must be considered when configured as analog inputs will read as a determining the total response time to a comparator ‘0’. Pins configured as digital inputs will input change. See the Comparator and Voltage convert as an analog input, according to Reference Specifications in Section30.0 “Electrical the input specification. Specifications” for more details. 2: Analog levels on any pin defined as a 19.9 Interaction with ECCP Logic digital input, may cause the input buffer to consume more current than is specified. The C1 comparator can be used as a general purpose comparator. The output can be brought out to the C1OUT pin. When the ECCP auto-shutdown is active it can use the comparator signal. If auto-restart is also enabled, the comparator can be configured as a closed loop analog feedback to the ECCP, thereby, creating an analog controlled PWM. Note: When the comparator module is first initialized the output state is unknown. Upon initialization, the user should verify the output state of the comparator prior to relying on the result, primarily when using the result in connection with other peripheral features, such as the ECCP Auto-Shutdown mode.  2011-2015 Microchip Technology Inc. DS40001441F-page 139

PIC12(L)F1840 FIGURE 19-3: ANALOG INPUT MODEL VDD Analog Input Rs < 10K pin VT  0.6V RIC To Comparator VA C5 PpIFN VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE= Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note 1: See Section30.0 “Electrical Specifications”. DS40001441F-page 140  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 19.11 Register Definitions: Comparator Control REGISTER 19-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-1/1 R/W-0/0 R/W-0/0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 C1OUT: Comparator Output bit If C1POL = 1 (inverted polarity): 1 = C1VP < C1VN 0 = C1VP > C1VN If C1POL = 0 (non-inverted polarity): 1 = C1VP > C1VN 0 = C1VP < C1VN bit 5 C1OE: Comparator Output Enable bit 1 = C1OUT is present on the C1OUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by C1ON. 0 = C1OUT is internal only bit 4 C1POL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 C1SP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode bit 1 C1HYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 C1SYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous.  2011-2015 Microchip Technology Inc. DS40001441F-page 141

PIC12(L)F1840 REGISTER 19-2: CM1CON1: COMPARATOR C1 CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 C1INTP C1INTN C1PCH<1:0> — — — C1NCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1INTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The C1IF interrupt flag will be set upon a positive going edge of the C1OUT bit 0 = No interrupt flag will be set on a positive going edge of the C1OUT bit bit 6 C1INTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The C1IF interrupt flag will be set upon a negative going edge of the C1OUT bit 0 = No interrupt flag will be set on a negative going edge of the C1OUT bit bit 5-4 C1PCH<1:0>: Comparator Positive Input Channel Select bits 10 = C1VP connects to FVR Voltage Reference 01 = C1VP connects to DAC Voltage Reference 00 = C1VP connects to C1IN+ pin bit 3-1 Unimplemented: Read as ‘0’ bit 0 C1NCH: Comparator Negative Input Channel Select bit 1 = C1VN connects to C1IN1- pin 0 = C1VN connects to C1IN0- pin REGISTER 19-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 — — — — — — — MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 MC1OUT: Mirror Copy of C1OUT bit TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 141 CM1CON1 C1INTP C1INTN C1PCH<1:0> — — — C1NCH 142 CMOUT — — — — — — — MC1OUT 142 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 74 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 76 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module. DS40001441F-page 142  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 20.0 TIMER0 MODULE 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment The Timer0 module is an 8-bit timer/counter with the on every rising or falling edge of the T0CKI pin or the following features: Capacitive Sensing Oscillator (CPSCLK) signal. • 8-bit timer/counter register (TMR0) 8-Bit Counter mode using the T0CKI pin is selected by • 8-bit prescaler (independent of Watchdog Timer) setting the TMR0CS bit in the OPTION_REG register to • Programmable internal or external clock source ‘1’ and resetting the T0XCS bit in the CPSCON0 register • Programmable external clock edge selection to ‘0’. • Interrupt on overflow 8-Bit Counter mode using the Capacitive Sensing • TMR0 can be used to gate Timer1 Oscillator (CPSCLK) signal is selected by setting the Figure20-1 is a block diagram of the Timer0 module. TMR0CS bit in the OPTION_REG register to ‘1’ and setting the T0XCS bit in the CPSCON0 register to ‘1’. 20.1 Timer0 Operation The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit The Timer0 module can be used as either an 8-bit timer in the OPTION_REG register. or an 8-bit counter. 20.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 20-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 0 1 2 TCY TMR0 0 From CPSCLK 1 TMR0SE TMR0CS 8-bit Set Flag bit TMR0IF on Overflow Prescaler PSA T0XCS Overflow to Timer1 8 PS<2:0>  2011-2015 Microchip Technology Inc. DS40001441F-page 143

PIC12(L)F1840 20.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 20.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 20.1.5 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS40001441F-page 144  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 20.2 Register Definitions: Option Register REGISTER 20-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUA latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 1 : 2 001 1 : 4 010 1 : 8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 282 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 145 TMR0 Timer0 Module Register 143* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information.  2011-2015 Microchip Technology Inc. DS40001441F-page 145

PIC12(L)F1840 21.0 TIMER1 MODULE WITH GATE • Gate Toggle mode CONTROL • Gate Single-pulse mode • Gate Value Status The Timer1 module is a 16-bit timer/counter with the • Gate Event Interrupt following features: Figure21-1 is a block diagram of the Timer1 module. • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 2-bit prescaler • Dedicated 32 kHz oscillator circuit • Optionally synchronized comparator out • Multiple Timer1 gate (count enable) sources • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Special Event Trigger (with ECCP) • Selectable Gate Source Polarity FIGURE 21-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1GSPM T1G 00 t1g_in 0 Data Bus From Timer0 01 0 T1GVAL D Q Overflow Single Pulse RD Comparator 1 Acq. Control 1 Q1 EN T1GCON 10 D Q 1 sync_C1OUT Reserved 11 TMR1ON RCK Q T1GGO/DONE Interrudpett STeMtR1GIF T1GTM T1GPOL TMR1GE TMR1ON Set flag bit To Comparator Module TMR1IF on TMR1(2) Overflow EN Synchronized 0 clock input TMR1H TMR1L T1CLK Q D 1 TMR1CS<1:0> T1SYNC T1OSO OUT Cap. Sensing T1OSC Oscillator 11 Prescaler Synchronize(3) 1 1, 2, 4, 8 det T1OSI EN 10 2 0 FOSC T1CKPS<1:0> Internal 01 T1OSCEN Clock IFnOteSrCn/a2l Sleep input FOSC/4 Clock Internal 00 (1) Clock T1CKI To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. DS40001441F-page 146  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 21.1 Timer1 Operation 21.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> and T1OSCEN bits of the T1CON which is accessed through the TMR1H:TMR1L register register are used to select the clock source for Timer1. pair. Writes to TMR1H or TMR1L directly update the Table21-2 displays the clock source selections. counter. 21.2.1 INTERNAL CLOCK SOURCE When used with an internal clock source, the module is a timer and increments on every instruction cycle. When the internal clock source is selected, the When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples can be used as either a timer or counter and of FOSC as determined by the Timer1 prescaler. increments on every selected edge of the external When the FOSC internal clock source is selected, the source. Timer1 register value will increment by four counts every Timer1 is enabled by configuring the TMR1ON and instruction clock cycle. Due to this condition, a 2LSB TMR1GE bits in the T1CON and T1GCON registers, error in resolution will occur when reading the Timer1 respectively. Table21-1 displays the Timer1 enable value. To utilize the full resolution of Timer1, an selections. asynchronous input signal must be used to gate the Timer1 clock input. TABLE 21-1: TIMER1 ENABLE The following asynchronous sources may be used: SELECTIONS • Asynchronous event on the T1G pin to Timer1 gate Timer1 TMR1ON TMR1GE • C1 comparator input to Timer1 gate Operation 0 0 Off 21.2.2 EXTERNAL CLOCK SOURCE 0 1 Off When the external clock source is selected, the Timer1 1 0 Always On module may work as a timer or a counter. 1 1 Count Enabled When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMR1H or TMR1L • Timer1 is disabled • Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. TABLE 21-2: CLOCK SOURCE SELECTIONS TMR1CS1 TMR1CS0 T1OSCEN Clock Source 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 1 x Capacitive Sensing Oscillator 1 0 0 External Clocking on T1CKI Pin 1 0 1 Osc.Circuit On T1OSI/T1OSO Pins  2011-2015 Microchip Technology Inc. DS40001441F-page 147

PIC12(L)F1840 21.3 Timer1 Prescaler should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the Timer1 has four prescaler options allowing 1, 2, 4 or 8 timer may overflow between the reads. divisions of the clock input. The T1CKPS bits of the For writes, it is recommended that the user simply stop T1CON register control the prescale counter. The the timer and write the desired values. A write prescale counter is not directly readable or writable; contention may occur by writing to the timer registers, however, the prescaler counter is cleared upon a write to while the register is incrementing. This may produce an TMR1H or TMR1L. unpredictable value in the TMR1H:TMR1L register pair. 21.4 Timer1 Oscillator 21.6 Timer1 Gate A dedicated low-power 32.768kHz oscillator circuit is Timer1 can be configured to count freely or the count built-in between pins T1OSI (input) and T1OSO can be enabled and disabled using Timer1 gate (amplifier output). This internal circuit is to be used in circuitry. This is also referred to as Timer1 Gate Enable. conjunction with an external 32.768kHz crystal. Timer1 gate can also be driven by multiple selectable The oscillator circuit is enabled by setting the sources. T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. 21.6.1 TIMER1 GATE ENABLE Note: The oscillator requires a start-up and The Timer1 Gate Enable mode is enabled by setting stabilization time before use. Thus, the TMR1GE bit of the T1GCON register. The polarity T1OSCEN should be set and a suitable of the Timer1 Gate Enable mode is configured using delay observed prior to using Timer1. A the T1GPOL bit of the T1GCON register. suitable delay similar to the OST delay can be implemented in software by When Timer1 Gate Enable mode is enabled, Timer1 clearing the TMR1IF bit then presetting will increment on the rising edge of the Timer1 clock the TMR1H:TMR1L register pair to source. When Timer1 Gate Enable mode is disabled, FC00h. The TMR1IF flag will be set when no incrementing will occur and Timer1 will hold the 1024 clock cycles have elapsed, thereby current count. See Figure21-3 for timing details. indicating that the oscillator is running and reasonably stable. TABLE 21-3: TIMER1 GATE ENABLE SELECTIONS 21.5 Timer1 Operation in T1CLK T1GPOL T1G Timer1 Operation Asynchronous Counter Mode  0 0 Counts If the control bit T1SYNC of the T1CON register is set,  0 1 Holds Count the external clock input is not synchronized. The timer increments asynchronously to the internal phase  1 0 Holds Count clocks. If the external clock source is selected then the  1 1 Counts timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up 21.6.2 TIMER1 GATE SOURCE the processor. However, special precautions in SELECTION software are needed to read/write the timer (see Timer1 gate source selections are shown in Table21-4. Section21.5.1 “Reading and Writing Timer1 in Source selection is controlled by the T1GSS bits of the Asynchronous Counter Mode”). T1GCON register. The polarity for each available Note: When switching from synchronous to source is also selectable. Polarity selection is asynchronous operation, it is possible to controlled by the T1GPOL bit of the T1GCON register. skip an increment. When switching from asynchronous to synchronous operation, TABLE 21-4: TIMER1 GATE SOURCES it is possible to produce an additional T1GSS Timer1 Gate Source increment. 00 Timer1 Gate Pin 21.5.1 READING AND WRITING TIMER1 IN 01 Overflow of Timer0 ASYNCHRONOUS COUNTER (TMR0 increments from FFh to 00h) MODE 10 Comparator 1 Output sync_C1OUT Reading TMR1H or TMR1L while the timer is running (optionally Timer1 synchronized output) from an external asynchronous clock will ensure a valid 11 Reserved read (taken care of in hardware). However, the user DS40001441F-page 148  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 21.6.2.1 T1G Pin Gate Operation 21.6.4 TIMER1 GATE SINGLE-PULSE MODE The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 When Timer1 Gate Single-Pulse mode is enabled, it is gate circuitry. possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the 21.6.2.2 Timer0 Overflow Gate Operation T1GSPM bit in the T1GCON register. Next, the When Timer0 increments from FFh to 00h, a T1GGO/DONE bit in the T1GCON register must be set. low-to-high pulse will automatically be generated and The Timer1 will be fully enabled on the next incrementing internally supplied to the Timer1 gate circuitry. edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other 21.6.2.3 Comparator C1 Gate Operation gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See The output resulting from a Comparator 1 operation can Figure21-5 for timing details. be selected as a source for Timer1 gate control. The Comparator 1 output (sync_C1OUT) can be If the Single-Pulse Gate mode is disabled by clearing the synchronized to the Timer1 clock or left asynchronous. T1GSPM bit in the T1GCON register, the T1GGO/DONE For more information see Section19.4.1 “Comparator bit should also be cleared. Output Synchronization”. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work 21.6.3 TIMER1 GATE TOGGLE MODE together. This allows the cycle times on the Timer1 gate When Timer1 Gate Toggle mode is enabled, it is source to be measured. See Figure21-6 for timing possible to measure the full-cycle length of a Timer1 details. gate signal, as opposed to the duration of a single level pulse. 21.6.5 TIMER1 GATE VALUE STATUS The Timer1 gate source is routed through a flip-flop that When Timer1 Gate Value Status is utilized, it is possible changes state on every incrementing edge of the to read the most current level of the gate control value. signal. See Figure21-4 for timing details. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 Timer1 Gate Toggle mode is enabled by setting the gate is not enabled (TMR1GE bit is cleared). T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This 21.6.6 TIMER1 GATE EVENT INTERRUPT is necessary in order to control which edge is measured. When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion Note: Enabling Toggle mode at the same time of a gate event. When the falling edge of T1GVAL as changing the gate polarity may result in occurs, the TMR1GIF flag bit in the PIR1 register will be indeterminate operation. set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared).  2011-2015 Microchip Technology Inc. DS40001441F-page 149

PIC12(L)F1840 21.7 Timer1 Interrupt 21.9 ECCP/CCP Capture/Compare Time Base The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls The CCP module uses the TMR1H:TMR1L register over, the Timer1 interrupt flag bit of the PIR1 register is pair as the time base when operating in Capture or set. To enable the interrupt on rollover, you must set Compare mode. these bits: In Capture mode, the value in the TMR1H:TMR1L • TMR1ON bit of the T1CON register register pair is copied into the CCPR1H:CCPR1L • TMR1IE bit of the PIE1 register register pair on a configured event. • PEIE bit of the INTCON register In Compare mode, an event is triggered when the value • GIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a The interrupt is cleared by clearing the TMR1IF bit in Special Event Trigger. the Interrupt Service Routine. For more information, see Section24.0 Note: The TMR1H:TMR1L register pair and the “Capture/Compare/PWM Modules”. TMR1IF bit should be cleared before enabling interrupts. 21.10 ECCP/CCP Special Event Trigger 21.8 Timer1 Operation During Sleep When the CCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. Timer1 can only operate during Sleep when setup in This special event does not cause a Timer1 interrupt. Asynchronous Counter mode. In this mode, an external The CCP module may still be configured to generate a crystal or clock source can be used to increment the CCP interrupt. counter. To set up the timer to wake the device: In this mode of operation, the CCPR1H:CCPR1L • TMR1ON bit of the T1CON register must be set register pair becomes the period register for Timer1. • TMR1IE bit of the PIE1 register must be set Timer1 should be synchronized and FOSC/4 should be • PEIE bit of the INTCON register must be set selected as the clock source in order to utilize the • T1SYNC bit of the T1CON register must be set Special Event Trigger. Asynchronous operation of • TMR1CS bits of the T1CON register must be Timer1 can cause a Special Event Trigger to be configured missed. • T1OSCEN bit of the T1CON register must be In the event that a write to TMR1H or TMR1L coincides configured with a Special Event Trigger from the CCP, the write will The device will wake-up on an overflow and execute take precedence. the next instructions. If the GIE bit of the INTCON For more information, see Section16.2.5 “Special register is set, the device will call the Interrupt Service Event Trigger”. Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 21-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001441F-page 150  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8  2011-2015 Microchip Technology Inc. DS40001441F-page 151

PIC12(L)F1840 FIGURE 21-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by TMR1GIF Cleared by software Set by hardware on software falling edge of T1GVAL DS40001441F-page 152  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 21-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by hardware on T1GGO/ Set by software falling edge of T1GVAL DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by hardware on Cleared by TMR1GIF Cleared by software falling edge of T1GVAL software  2011-2015 Microchip Technology Inc. DS40001441F-page 153

PIC12(L)F1840 21.11 Register Definitions: Timer1 Control REGISTER 21-1: T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 =Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 =Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 =Timer1 clock source is system clock (FOSC) 00 =Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop DS40001441F-page 154  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 21-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Reserved 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 01 = Timer0 overflow output 00 = Timer1 Gate pin  2011-2015 Microchip Technology Inc. DS40001441F-page 155

PIC12(L)F1840 TABLE 21-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 189 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 150* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 150* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 154 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 155 DONE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. DS40001441F-page 156  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 22.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP1 modules See Figure22-1 for a block diagram of Timer2. FIGURE 22-1: TIMER2 BLOCK DIAGRAM Prescaler Reset FOSC/4 TMRx TMRx Output 1:1, 1:4, 1:16, 1:64 2 Comparator Postscaler Sets Flag bit TMRxIF EQ 1:1 to 1:16 TxCKPS<1:0> PRx 4 TxOUTPS<3:0>  2011-2015 Microchip Technology Inc. DS40001441F-page 157

PIC12(L)F1840 22.1 Timer2 Operation 22.3 Timer2 Output The clock input to the Timer2 modules is the system The unscaled output of TMR2 is available primarily to instruction clock (FOSC/4). the CCP1 module, where it is used as a time base for operations in PWM mode. TMR2 increments from 00h on each clock edge. Timer2 can be optionally used as the shift clock source A 4-bit counter/prescaler on the clock input allows direct for the MSSP1 module operating in SPI mode. input, divide-by-4 and divide-by-16 prescale options. Additional information is provided in Section25.1 These options are selected by the prescaler control bits, “Master SSP (MSSP1) Module Overview” T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on 22.4 Timer2 Operation During Sleep each clock cycle. When the two values match, the comparator generates a match signal as the timer Timer2 cannot be operated while the processor is in output. This signal also resets the value of TMR2 to 00h Sleep mode. The contents of the TMR2 and PR2 on the next cycle and drives the output registers will remain unchanged while the processor is counter/postscaler (see Section22.2 “Timer2 in Sleep mode. Interrupt”). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMR2 register • a write to the T2CON register • Power-on Reset (POR) • Brown-out Reset (BOR) • MCLR Reset • Watchdog Timer (WDT) Reset • Stack Overflow Reset • Stack Underflow Reset • RESET Instruction Note: TMR2 is not cleared when T2CON is written. 22.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register. DS40001441F-page 158  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 22.5 Register Definitions: Timer2 Control REGISTER 22-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer Output Postscaler Select bits 1111 =1:16 Postscaler 1110 =1:15 Postscaler 1101 =1:14 Postscaler 1100 =1:13 Postscaler 1011 =1:12 Postscaler 1010 =1:11 Postscaler 1001 =1:10 Postscaler 1000 =1:9 Postscaler 0111 =1:8 Postscaler 0110 =1:7 Postscaler 0101 =1:6 Postscaler 0100 =1:5 Postscaler 0011 =1:4 Postscaler 0010 =1:3 Postscaler 0001 =1:2 Postscaler 0000 =1:1 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 11 =Prescaler is 64 10 =Prescaler is 16 01 =Prescaler is 4 00 =Prescaler is 1  2011-2015 Microchip Technology Inc. DS40001441F-page 159

PIC12(L)F1840 TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 189 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 PR2 Timer2 Module Period Register 157* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 159 TMR2 Holding Register for the 8-bit TMR2 Register 157* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. DS40001441F-page 160  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 23.0 DATA SIGNAL MODULATOR The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical “AND” operation of both the carrier and modulator signals and then provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. Using this method, the DSM can generate the following types of Key Modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • Carrier Synchronization • Carrier Source Polarity Select • Carrier Source Pin Disable • Programmable Modulator Data • Modulator Source Pin Disable • Modulated Output Polarity Select • Slew Rate Control Figure23-1 shows a Simplified Block Diagram of the Data Signal Modulator peripheral.  2011-2015 Microchip Technology Inc. DS40001441F-page 161

PIC12(L)F1840 FIGURE 23-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCH<3:0> MDEN VSS 0000 MDCIN1 0001 EN MDCIN2 0010 Data Signal CLKR 0011 Modulator CCP1 0100 0101 CARH Reserved * No Channel * MDCHPOL Selected * 1111 D SYNC MDMS<3:0> Q 1 MDBIT 0000 MDMIN 0001 CCP1 0010 Reserved 0011 0 Reserved 0100 Reserved 0101 Comparator C1 0110 MOD MDCHSYNC Reserved 0111 MSSP1 SDO1 1000 MDOUT Reserved 1001 EUSART 1010 MDOPOL MDOE Reserved 0011 No Channel * * Selected 1111 D MDCL<3:0> SYNC Q 1 VSS 0000 MDCIN1 0001 MDCIN2 0010 CLKR 0011 0 CCP1 0100 0101 CARL MDCLSYNC Reserved * No Channel * Selected * MDCLPOL 1111 DS40001441F-page 162  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 23.1 DSM Operation 23.3 Carrier Signal Sources The DSM module can be enabled by setting the MDEN The carrier high signal and carrier low signal can be bit in the MDCON register. Clearing the MDEN bit in the supplied from the following sources: MDCON register, disables the DSM module by auto- • CCP1 Signal matically switching the carrier high and carrier low sig- • Reference Clock Module Signal nals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON • External Signal on MDCIN1 pin register. This not only assures that the DSM module is • External Signal on MDCIN2 pin inactive, but that it is also consuming the least amount • VSS of current. The carrier high signal is selected by configuring the The values used to select the carrier high, carrier low, MDCH <3:0> bits in the MDCARH register. The carrier and modulator sources held by the Modulation Source, low signal is selected by configuring the MDCL <3:0> Modulation High Carrier, and Modulation Low Carrier bits in the MDCARL register. control registers are not affected when the MDEN bit is cleared and the DSM module is disabled. The values 23.4 Carrier Synchronization inside these registers remain unchanged while the DSM is inactive. The sources for the carrier high, car- During the time when the DSM switches between rier low and modulator signals will once again be carrier high and carrier low signal sources, the carrier selected when the MDEN bit is set and the DSM data in the modulated output signal can become module is again enabled and active. truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When The modulated output signal can be disabled without synchronization is enabled, the carrier pulse that is shutting down the DSM module. The DSM module will being mixed at the time of the transition is allowed to remain active and continue to mix signals, but the out- transition low before the DSM switches over to the next put value will not be sent to the MDOUT pin. During the carrier source. time that the output is disabled, the MDOUT pin will remain low. The modulated output can be disabled by Synchronization is enabled separately for the carrier clearing the MDOE bit in the MDCON register. high and carrier low signal sources. Synchronization for the carrier high signal can be enabled by setting the 23.2 Modulator Signal Sources MDCHSYNC bit in the MDCARH register. Synchronization for the carrier low signal can be The modulator signal can be supplied from the enabled by setting the MDCLSYNC bit in the MDCARL following sources: register. • CCP1 Signal Figure23-1 through Figure23-5 show timing diagrams • MSSP1 SDO1 Signal (SPI mode only) of using various synchronization methods. • Comparator C1 Signal • EUSART TX Signal • External Signal on MDMIN pin • MDBIT bit in the MDCON register The modulator signal is selected by configuring the MDMS <3:0> bits in the MDSRC register.  2011-2015 Microchip Technology Inc. DS40001441F-page 163

PIC12(L)F1840 FIGURE 23-2: ON OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 EXAMPLE 23-1: NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier CARH CARL CARH CARL State FIGURE 23-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier CARH both CARL CARH both CARL State DS40001441F-page 164  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 23-4: CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier CARH CARL CARH CARL State FIGURE 23-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH CARL CARH CARL State  2011-2015 Microchip Technology Inc. DS40001441F-page 165

PIC12(L)F1840 23.5 Carrier Source Polarity Select 23.11 Operation in Sleep Mode The signal provided from any selected input source for The DSM module is not affected by Sleep mode. The the carrier high and carrier low signals can be inverted. DSM can still operate during Sleep, if the Carrier and Inverting the signal for the carrier high source is Modulator input sources are also still operable during enabled by setting the MDCHPOL bit of the MDCARH Sleep. register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL 23.12 Effects of a Reset register. Upon any device Reset, the DSM module is disabled. 23.6 Carrier Source Pin Disable The user’s firmware is responsible for initializing the module before enabling the output. The registers are Some peripherals assert control over their reset to their default values. corresponding output pin when they are enabled. For example, when the CCP1 module is enabled, the output of CCP1 is connected to the CCP1 pin. This default connection to a pin can be disabled by setting the MDCHODIS bit in the MDCARH register for the carrier high source and the MDCLODIS bit in the MDCARL register for the carrier low source. 23.7 Programmable Modulator Data The MDBIT of the MDCON register can be selected as the source for the modulator signal. This gives the user the ability to program the value used for modulation. 23.8 Modulator Source Pin Disable The modulator source default connection to a pin can be disabled by setting the MDMSODIS bit in the MDSRC register. 23.9 Modulated Output Polarity The modulated output signal provided on the MDOUT pin can also be inverted. Inverting the modulated output signal is enabled by setting the MDOPOL bit of the MDCON register. 23.10 Slew Rate Control The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register. DS40001441F-page 166  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 23.13 Register Definitions: Modulation Control REGISTER 23-1: MDCON: MODULATION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R-0/0 U-0 U-0 R/W-0/0 MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output enabled 0 = Modulator pin output disabled bit 5 MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting enabled 0 = MDOUT pin slew rate limiting disabled bit 4 MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted bit 3 MDOUT: Modulator Output bit Displays the current output value of the Modulator module.(1) bit 2-1 Unimplemented: Read as ‘0’ bit 0 MDBIT: Allows software to manually set modulation source input to module(2) 1 = Modulator uses High Carrier source 0 = Modulator uses Low Carrier source Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. 2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.  2011-2015 Microchip Technology Inc. DS40001441F-page 167

PIC12(L)F1840 REGISTER 23-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-x/u U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDMSODIS — — — MDMS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDMSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 MDMS<3:0> Modulation Source Selection bits 1111 = Reserved. No channel connected. 1110 = Reserved. No channel connected. 1101 = Reserved. No channel connected. 1100 = Reserved. No channel connected. 1011 = Reserved. No channel connected. 1010 = EUSART TX output. 1001 = Reserved. No channel connected. 1000 = MSSP1 SDO output 0111 = Reserved. No channel connected. 0110 = Comparator 1 output 0101 = Reserved. No channel connected. 0100 = Reserved. No channel connected. 0011 = Reserved. No channel connected. 0010 = CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source DS40001441F-page 168  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 23-3: MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled bit 6 MDCHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted bit 5 MDCHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator Output is not synchronized to the high time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCH<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. • • • 0101 = Reserved. No channel connected. 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal (CLKR) 0010 = MDCIN2 port pin 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.  2011-2015 Microchip Technology Inc. DS40001441F-page 169

PIC12(L)F1840 REGISTER 23-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER R/W-x/u R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is enabled bit 6 MDCLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted bit 5 MDCLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator Output is not synchronized to the low time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 MDCL<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. • • • 0101 = Reserved. No channel connected. 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = Reserved. No channel connected. 0001 = MDCIN1 port pin 0000 = VSS Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page MDCARH MDCHODIS MDCHPOL MDCHSYNC — MDCH<3:0> 169 MDCARL MDCLODIS MDCLPOL MDCLSYNC — MDCL<3:0> 170 MDCON MDEN MDOE MDSLR MDOPOL MDOUT — — MDBIT 167 MDSRC MDMSODIS — — — MDMS<3:0> 168 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in the Data Signal Modulator mode. DS40001441F-page 170  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 24.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This device contains one Enhanced Capture/Compare/ PWM module (ECCP1). The Half-Bridge ECCP module has two available I/O pins. See Table24-1. TABLE 24-1: PWM RESOURCES Device Name ECCP1 PIC12(L)F1840 Enhanced PWM Half-Bridge  2011-2015 Microchip Technology Inc. DS40001441F-page 171

PIC12(L)F1840 24.1 Capture Mode 24.1.2 TIMER1 MODE RESOURCE Capture mode makes use of the 16-bit Timer1 Timer1 must be running in Timer mode or Synchronized resource. When an event occurs on the CCP1 pin, the Counter mode for the CCP1 module to use the capture 16-bit CCPR1H:CCPR1L register pair captures and feature. In Asynchronous Counter mode, the capture stores the 16-bit value of the TMR1H:TMR1L register operation may not work. pair, respectively. An event is defined as one of the See Section21.0 “Timer1 Module with Gate Control” following and is configured by the CCP1M<3:0> bits of for more information on configuring Timer1. the CCP1CON register: 24.1.3 SOFTWARE INTERRUPT MODE • Every falling edge • Every rising edge When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the • Every 4th rising edge CCP1IE interrupt enable bit of the PIE1 register clear to • Every 16th rising edge avoid false interrupts. Additionally, the user should When a capture is made, the Interrupt Request Flag bit clear the CCP1IF interrupt flag bit of the PIR1 register CCP1IF of the PIR1 register is set. The interrupt flag following any change in Operating mode. must be cleared in software. If another capture occurs Note: Clocking Timer1 from the system clock before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new (FOSC) should not be used in Capture mode. In order for Capture mode to captured value. recognize the trigger event on the CCP1 Figure24-1 shows a simplified diagram of the Capture pin, Timer1 must be clocked from the operation. instruction clock (FOSC/4) or from an external clock source. 24.1.1 CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured 24.1.4 CCP1 PRESCALER as an input by setting the associated TRIS control bit. There are four prescaler settings specified by the Also, the CCP1 pin function can be moved to CCP1M<3:0> bits of the CCP1CON register. alternative pins using the APFCON register. Refer to Whenever the CCP1 module is turned off, or the CCP1 Section12.1 “Alternate Pin Function” for more module is not in Capture mode, the prescaler counter details. is cleared. Any Reset will clear the prescaler counter. Note: If the CCP1 pin is configured as an output, Switching from one capture prescaler to another does not a write to the port can cause a capture clear the prescaler and may generate a false interrupt. To condition. avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the FIGURE 24-1: CAPTURE MODE prescaler. Example24-1 demonstrates the code to OPERATION BLOCK perform this function. DIAGRAM EXAMPLE 24-1: CHANGING BETWEEN Set Flag bit CCP1IF CAPTURE PRESCALERS (PIR1 register) Prescaler  1, 4, 16 BANKSELCCP1CON ;Set Bank bits to point CCP1 CCPR1H CCPR1L ;to CCP1CON pin CLRF CCP1CON ;Turn CCP1 module off MOVLW NEW_CAPT_PS;Load the W reg with and Capture Edge Detect Enable ;the new prescaler ;move value and CCP1 ON TMR1H TMR1L MOVWF CCP1CON ;Load CCP1CON with this CCP1M<3:0> ;value System Clock (FOSC) DS40001441F-page 172  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 24.1.5 CAPTURE DURING SLEEP 24.1.6 ALTERNATE PIN LOCATIONS Capture mode depends upon the Timer1 module for This module incorporates I/O pins that can be moved to proper operation. There are two options for driving the other locations with the use of the alternate pin function Timer1 module in Capture mode. It can be driven by the register, APFCON. To determine which pins can be instruction clock (FOSC/4), or by an external clock source. moved and what their default locations are upon a reset, see Section12.1 “Alternate Pin Function” for When Timer1 is clocked by FOSC/4, Timer1 will not more information. increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL 99 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 189 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) 172 CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) 172 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 74 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 76 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 154 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 155 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 150* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 150* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode. * Page provides register information.  2011-2015 Microchip Technology Inc. DS40001441F-page 173

PIC12(L)F1840 24.2 Compare Mode 24.2.2 TIMER1 MODE RESOURCE Compare mode makes use of the 16-bit Timer1 In Compare mode, Timer1 must be running in either resource. The 16-bit value of the CCPR1H:CCPR1L Timer mode or Synchronized Counter mode. The register pair is constantly compared against the 16-bit compare operation may not work in Asynchronous value of the TMR1H:TMR1L register pair. When a Counter mode. match occurs, one of the following events can occur: See Section21.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. • Toggle the CCP1 output • Set the CCP1 output Note: Clocking Timer1 from the system clock • Clear the CCP1 output (FOSC) should not be used in Capture mode. In order for Capture mode to • Generate a Special Event Trigger recognize the trigger event on the CCP1 • Generate a Software Interrupt pin, TImer1 must be clocked from the The action on the pin is based on the value of the instruction clock (FOSC/4) or from an CCP1M<3:0> control bits of the CCP1CON register. At external clock source. the same time, the interrupt flag CCP1IF bit is set. All Compare modes can generate an interrupt. 24.2.3 SOFTWARE INTERRUPT MODE Figure24-2 shows a simplified diagram of the When Generate Software Interrupt mode is chosen Compare operation. (CCP1M<3:0>=1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON FIGURE 24-2: COMPARE MODE register). OPERATION BLOCK 24.2.4 SPECIAL EVENT TRIGGER DIAGRAM When Special Event Trigger mode is chosen CCP1M<3:0> (CCP1M<3:0>=1011), the CCP1 module does the Mode Select following: Set CCP1IF Interrupt Flag • Resets Timer1 (PIR1) CCP1 4 • Starts an ADC conversion if ADC is enabled Pin CCPR1H CCPR1L The CCP1 module does not assert control of the CCP1 Q S Output Comparator pin in this mode. Logic Match R The Special Event Trigger output of the CCP1 occurs TMR1H TMR1L immediately upon a match between the TMR1H, TRIS TMR1L register pair and the CCPR1H, CCPR1L Output Enable register pair. The TMR1H, TMR1L register pair is not Special Event Trigger reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an ADC conversion (if the ADC module is enabled). This allows the 24.2.1 CCP1 PIN CONFIGURATION CCPR1H, CCPR1L register pair to effectively provide a The user must configure the CCP1 pin as an output by 16-bit programmable period register for Timer1. clearing the associated TRIS bit. Note1: The Special Event Trigger from the CCP1 Also, the CCP1 pin function can be moved to module does not set interrupt flag bit alternative pins using the APFCON register. Refer to TMR1IF of the PIR1 register. Section12.1 “Alternate Pin Function” for more 2: Removing the match condition by details. changing the contents of the CCPR1H Note: Clearing the CCP1CON register will force and CCPR1L register pair, between the the CCP1 compare output latch to the clock edge that generates the Special default low level. This is not the PORT I/O Event Trigger and the clock edge that data latch. generates the Timer1 Reset, will preclude the Reset from occurring. 24.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. DS40001441F-page 174  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 24.2.6 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section12.1 “Alternate Pin Function” for more information. TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL 99 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 189 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) 172 CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) 172 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 74 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 76 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 154 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 155 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 150* TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 150* TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode. * Page provides register information.  2011-2015 Microchip Technology Inc. DS40001441F-page 175

PIC12(L)F1840 24.3 PWM Overview FIGURE 24-3: CCP1 PWM OUTPUT SIGNAL Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between Period fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is Pulse Width considered the on state and the low portion of the signal TMR2 = PR2 is considered the off state. The high portion, also known TMR2 = CCPR1H:CCP1CON<5:4> as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which TMR2 = 0 lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which FIGURE 24-4: SIMPLIFIED PWM BLOCK shortens the pulse width, supplies less power. The DIAGRAM PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. CCP1CON<5:4> PWM resolution defines the maximum number of steps Duty Cycle Registers that can be present in a single PWM period. A higher CCPR1L resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the on CCPR1H(2) (Slave) time to the off time and is expressed in percentages, CCP1 where 0% is fully off and 100% is fully on. A lower duty Comparator R Q cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. S TMR2 (1) Figure24-3 shows a typical waveform of the PWM TRIS signal. Comparator 24.3.1 STANDARD PWM OPERATION Clear Timer, toggle CCP1 pin and latch duty cycle The standard PWM mode generates a Pulse-Width PR2 Modulation (PWM) signal on the CCP1 pin with up to 10 Note 1: The 8-bit timer TMR2 register is concatenated bits of resolution. The period, duty cycle, and resolution with the 2-bit internal system clock (FOSC), or are controlled by the following registers: 2 bits of the prescaler, to create the 10-bit time • PR2 registers base. • T2CON registers 2: In PWM mode, CCPR1H is a read-only register. • CCPR1L registers • CCP1CON registers Figure24-4 shows a simplified block diagram of PWM operation. Note1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCP1 pin. 2: Clearing the CCP1CON register will relinquish control of the CCP1 pin. DS40001441F-page 176  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 24.3.2 SETUP FOR PWM OPERATION When TMR2 is equal to PR2, the following three events occur on the next increment cycle: The following steps should be taken when configuring the CCP1 module for standard PWM operation: • TMR2 is cleared 1. Disable the CCP1 pin output driver by setting • The CCP1 pin is set. (Exception: If the PWM duty the associated TRIS bit. cycle=0%, the pin will not be set.) 2. Load the PR2 register with the PWM period • The PWM duty cycle is latched from CCPR1L into value. CCPR1H. 3. Configure the CCP1 module for the PWM mode by loading the CCP1CON register with the Note: The Timer postscaler (see Section22.1 “Timer2 Operation”) is not used in the appropriate values. determination of the PWM frequency. 4. Load the CCPR1L register and the DC1B1 bits of the CCP1CON register, with the PWM duty 24.3.4 PWM DUTY CYCLE cycle value. The PWM duty cycle is specified by writing a 10-bit 5. Configure and start Timer2: value to multiple registers: CCPR1L register and • Clear the TMR2IF interrupt flag bit of the DC1B<1:0> bits of the CCP1CON register. The PIR1 register. See Note below. CCPR1L contains the eight MSbs and the DC1B<1:0> • Configure the T2CKPS bits of the T2CON bits of the CCP1CON register contain the two LSbs. register with the Timer prescale value. CCPR1L and DC1B<1:0> bits of the CCP1CON • Enable the Timer by setting the TMR2ON register can be written to at any time. The duty cycle bit of the T2CON register. value is not latched into CCPR1H until after the period 6. Enable PWM output pin: completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H • Wait until the Timer overflows and the register is read-only. TMR2IF bit of the PIR1 register is set. See Note below. Equation24-2 is used to calculate the PWM pulse • Enable the CCP1 pin output driver by width. clearing the associated TRIS bit. Equation24-3 is used to calculate the PWM duty cycle Note: In order to send a complete duty cycle and ratio. period on the first PWM output, the above steps must be included in the setup EQUATION 24-2: PULSE WIDTH sequence. If it is not critical to start with a complete PWM signal on the first output, Pulse Width = CCPR1L:CCP1CON<5:4>  then step 6 may be ignored. TOSC  (TMR2 Prescale Value) 24.3.3 PWM PERIOD The PWM period is specified by the PR2 register of EQUATION 24-3: DUTY CYCLE RATIO Timer2. The PWM period can be calculated using the formula of Equation24-1. CCPR1L:CCP1CON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------- 4PR2+1 EQUATION 24-1: PWM PERIOD PWM Period = PR2+14TOSC The CCPR1H register and a 2-bit internal latch are (TMR2 Prescale Value) used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. Note 1: TOSC = 1/FOSC The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure24-4).  2011-2015 Microchip Technology Inc. DS40001441F-page 177

PIC12(L)F1840 24.3.5 PWM RESOLUTION EQUATION 24-4: PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution log4PR2+1 Resolution = ------------------------------------------ bits will result in 1024 discrete duty cycles, whereas an 8-bit log2 resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is Note: If the pulse width value is greater than the 255. The resolution is a function of the PR2 register period the assigned PWM pin(s) will value as shown by Equation24-4. remain unchanged. TABLE 24-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency 1.95 kHz 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz Timer Prescale 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 24-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 TABLE 24-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 DS40001441F-page 178  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 24.3.6 OPERATION IN SLEEP MODE 24.3.9 ALTERNATE PIN LOCATIONS In Sleep mode, the TMR2register will not increment This module incorporates I/O pins that can be moved to and the state of the module will not change. If the CCP1 other locations with the use of the alternate pin function pin is driving a value, it will continue to drive that value. register, APFCON. To determine which pins can be When the device wakes up, TMR2 will continue from its moved and what their default locations are upon a previous state. reset, see Section12.1 “Alternate Pin Function” for more information. 24.3.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section5.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 24.3.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. TABLE 24-7: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL 99 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 189 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 PR2 Timer2 Period Register 157* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 159 TMR2 Timer2 Module Register 157 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information.  2011-2015 Microchip Technology Inc. DS40001441F-page 179

PIC12(L)F1840 24.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A and P1B. The polarity of the PWM pins The enhanced PWM mode generates a Pulse-Width is configurable and is selected by setting the bits Modulation (PWM) signal on up to two different output CCP1M<3:0> in the CCP1CON register appropriately. pins with up to ten bits of resolution. The period, duty Figure24-5 shows an example of a simplified block cycle, and resolution are controlled by the following diagram of the Enhanced PWM module. registers: Table24-8 shows the pin assignments for various • PR2 registers Enhanced PWM modes. • T2CON registers • CCPR1L registers Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the • CCP1CON registers CCP1 pin. The ECCP modules have the following additional PWM 2: Clearing the CCP1CON register will registers which control Auto-shutdown, Auto-restart, relinquish control of the CCP1 pin. Dead-band Delay and PWM Steering modes: 3: Any pin not used in the enhanced PWM • CCP1AS registers mode is available for alternate pin • PSTR1CON registers functions, if applicable. • PWM1CON registers 4: To prevent the generation of an The enhanced PWM module can generate the following incomplete waveform when the PWM is three PWM Output modes: first enabled, the ECCP module waits • Single PWM until the start of a new PWM period before generating a PWM signal. • Half-Bridge PWM • Single PWM with PWM Steering Mode To select an Enhanced PWM Output mode, the P1M bits of the CCP1CON register must be configured appropriately. FIGURE 24-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE DC1B<1:0> P1M<1:0> CCP1M<3:0> Duty Cycle Registers 2 4 CCPR1L Output Controller CCPR1H (Slave) CCP1/P1A CCP1/P1A Comparator R Q TRISx TMR2 (1) S P1B P1B TRISx Comparator Clear Timer, toggle PWM pin and latch duty cycle PR2 PWM1CON Note 1: The 8-bit timer TMR1 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. DS40001441F-page 180  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 24-8: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode P1M<1:0> CCP1/P1A P1B Single 00 Yes(1) Yes(1) Half-Bridge 10 Yes Yes Note 1: PWM Steering enables outputs in Single mode. FIGURE 24-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Pulse PR2+1 P1M<1:0> Signal 0 Width Period 00 (Single Output) P1A Modulated Delay Delay P1A Modulated 10 (Half-Bridge) P1B Modulated Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>) FIGURE 24-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) P1M<1:0> Signal 0 Pulse PR2+1 Width Period 00 (Single Output) P1A Modulated P1A Modulated Delay Delay 10 (Half-Bridge) P1B Modulated Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWM1CON<6:0>)  2011-2015 Microchip Technology Inc. DS40001441F-page 181

PIC12(L)F1840 24.4.1 HALF-BRIDGE MODE Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must In Half-Bridge mode, two pins are used as outputs to be cleared to configure P1A and P1B as outputs. drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM FIGURE 24-8: EXAMPLE OF HALF- output signal is output on the P1B pin (see Figure24-9). BRIDGE PWM OUTPUT This mode can be used for Half-Bridge applications, as shown in Figure24-9, or for Full-Bridge applications, Period Period where four power switches are being modulated with two PWM signals. Pulse Width In Half-Bridge mode, the programmable dead-band delay P1A(2) can be used to prevent shoot-through current in Half- td Bridge power devices. The value of the P1DC<6:0> bits td of the PWM1CON register sets the number of instruction P1B(2) cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output (1) (1) (1) remains inactive during the entire cycle. See Section24.4.4 “Programmable Dead-Band Delay td = Dead-Band Delay Mode” for more details of the dead-band delay Note 1: At this time, the TMR2 register is equal to the operations. PR2 register. 2: Output signals are shown as active-high. FIGURE 24-9: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A - Load FET Driver + P1B - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET FET Driver Driver P1A Load FET FET Driver Driver P1B DS40001441F-page 182  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 24.4.2 ENHANCED PWM AUTO- • Drive logic ‘1’ SHUTDOWN MODE • Drive logic ‘0’ The PWM mode supports an Auto-Shutdown mode that • Tri-state (high-impedance) will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This Note1: The auto-shutdown condition is a level- mode is used to help prevent the PWM from damaging based signal, not an edge-based signal. the application. As long as the level is present, the auto- shutdown will persist. The auto-shutdown sources are selected using the CCP1AS<2:0> bits of the CCP1AS register. A shutdown 2: Writing to the CCP1ASE bit is disabled while an auto-shutdown condition event may be generated by: persists. • A logic ‘0’ on the FLT0 pin 3: Once the auto-shutdown condition has • Comparator C1 been removed and the PWM restarted • Setting the CCP1ASE bit in firmware (either through firmware or auto-restart) A shutdown condition is indicated by the CCP1ASE the PWM signal will always restart at the (Auto-Shutdown Event Status) bit of the CCP1AS beginning of the next PWM period. register. If the bit is a ‘0’, the PWM pins are operating 4: Prior to an auto-shutdown event caused normally. If the bit is a ‘1’, the PWM outputs are in the by a comparator output or FLT0 pin shutdown state. event, a software shutdown can be When a shutdown event occurs, two things happen: triggered in firmware by setting the CCP1ASE bit of the CCP1AS register to The CCP1ASE bit is set to ‘1’. The CCP1ASE will ‘1’. The Auto-Restart feature tracks the remain set until cleared in firmware or an auto-restart active status of a shutdown caused by a occurs (see Section24.4.3 “Auto-Restart Mode”). comparator output or FLT0 pin event only. The enabled PWM pins are asynchronously placed in If it is enabled at this time, it will immedi- their shutdown states. The PWM output pins are ately clear this bit and restart the ECCP grouped into pairs [P1A] and [P1B. The state of each pin module at the beginning of the next PWM pair is determined by the PSS1AC and PSS1BD bits of period. the CCP1AS register. Each pin pair may be placed into one of three states: FIGURE 24-10: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (P1RSEN = 0) Missing Pulse Missing Pulse (Auto-Shutdown) (CCP1ASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCP1ASE bit PWM Shutdown Shutdown Resumes Event Occurs Event Clears CCP1ASE Cleared by Firmware  2011-2015 Microchip Technology Inc. DS40001441F-page 183

PIC12(L)F1840 24.4.3 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto- shutdown condition has been removed. Auto-restart is enabled by setting the P1RSEN bit in the PWM1CON register. If auto-restart is enabled, the CCP1ASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCP1ASE bit will be cleared via hardware and normal operation will resume. FIGURE 24-11: PWM AUTO-SHUTDOWN WITH AUTO-RESTART (P1RSEN = 1) Missing Pulse Missing Pulse (Auto-Shutdown) (CCP1ASE not clear) Timer Timer Timer Timer Timer Overflow Overflow Overflow Overflow Overflow PWM Period PWM Activity Start of PWM Period ShutdownEvent CCP1ASE bit PWM Shutdown Resumes Event Occurs Shutdown CCP1ASE Event Clears Cleared by Hardware DS40001441F-page 184  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 24.4.4 PROGRAMMABLE DEAD-BAND FIGURE 24-12: EXAMPLE OF HALF- DELAY MODE BRIDGE PWM OUTPUT In half-bridge applications where all power switches are Period Period modulated at the PWM frequency, the power switches Pulse Width normally require more time to turn off than to turn on. If both the upper and lower power switches are switched P1A(2) at the same time (one turned on, and the other turned td off), both switches may be on for a short period of time td until one switch completely turns off. During this brief P1B(2) interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge (1) (1) (1) supply. To avoid this potentially destructive shoot- through current from flowing during switching, turning td = Dead-Band Delay on either of the power switches is normally delayed to allow the other switch to completely turn off. Note 1: At this time, the TMR2 register is equal to the PR2 register. In Half-Bridge mode, a digitally programmable dead- band delay is available to avoid shoot-through current 2: Output signals are shown as active-high. from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure24-12 for illustration. The lower seven bits of the associated PWM1CON register (Register24-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 24-13: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + P1A V - Load FET Driver + P1B V - V-  2011-2015 Microchip Technology Inc. DS40001441F-page 185

PIC12(L)F1840 24.4.5 PWM STEERING MODE 24.4.5.1 Steering Synchronization In Single Output mode, PWM steering allows any of the The STR1SYNC bit of the PSTR1CON register gives PWM pins to be the modulated signal. Additionally, the the user two selections of when the steering event will same PWM signal can be simultaneously available on happen. When the STR1SYNC bit is ‘0’, the steering multiple pins. event will happen at the end of the instruction that writes to the PSTR1CON register. In this case, the Once the Single Output mode is selected output signal at the output pins may be an incomplete (CCP1M<3:2>=11 and P1M<1:0>=00 of the PWM waveform. This operation is useful when the user CCP1CON register), the user firmware can bring out firmware needs to immediately remove a PWM signal the same PWM signal to one or two output pins by from the pin. setting the appropriate STR1 bits of the PSTR1CON register, as shown in Table24-8. When the STR1SYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will Note: The associated TRIS bits must be set to always produce a complete PWM waveform. output (‘0’) to enable the pin output driver Figures 24-15 and 24-16 illustrate the timing diagrams in order to see the PWM signal on the pin. of the PWM steering depending on the STR1SYNC While the PWM Steering mode is active, the setting. CCP1M<1:0> bits of the CCP1CON register determine 24.4.6 START-UP CONSIDERATIONS the polarity of the output pins. The PWM auto-shutdown operation also applies to When any PWM mode is used, the application PWM Steering mode as described in Section24.4.2 hardware must use the proper external pull-up and/or “Enhanced PWM Auto-Shutdown Mode”. An auto- pull-down resistors on the PWM output pins. shutdown event will only affect pins that have PWM The CCP1M<1:0> bits of the CCP1CON register allow outputs enabled. the user to choose whether the PWM output signals are active-high or active-low for each of the PWM output FIGURE 24-14: SIMPLIFIED STEERING pins (P1A and P1B). The PWM output polarities must BLOCK DIAGRAM be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the STR1A PWM pin output drivers are enable is not recommended since it may result in damage to the P1A Signal P1A pin application circuits. CCP1M1 1 The P1A and P1B output latches may not be in the PORT Data 0 proper states when the PWM module is initialized. TRIS STR1B Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to P1B pin the application circuit. The Enhanced PWM modes CCP1M0 1 must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM PORT Data 0 pin output drivers. The completion of a full PWM cycle TRIS is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. Note 1: Port outputs are configured as shown when Note: When the microcontroller is released from the CCP1CON register bits P1M<1:0>=00 Reset, all of the I/O pins are in the high- and CCP1M<3:2>=11. impedance state. The external circuits 2: Single PWM output requires setting at least must keep the power switch devices in the one of the STR1 bits. Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). DS40001441F-page 186  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 24-15: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STR1SYNC = 0) PWM Period PWM STR1 P1<B:A> PORT Data PORT Data P1n = PWM FIGURE 24-16: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STR1SYNC = 1) PWM STR1 P1<B:A> PORT Data PORT Data P1n = PWM  2011-2015 Microchip Technology Inc. DS40001441F-page 187

PIC12(L)F1840 24.4.7 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register, APFCON. To determine which pins can be moved and what their default locations are upon a reset, see Section12.1 “Alternate Pin Function” for more information. TABLE 24-9: SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL 99 CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 189 CCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 190 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 PR2 Timer2 Period Register 157* PSTR1CON — — — STR1SYNC Reserved Reserved STR1B STR1A 191 PWM1CON P1RSEN P1DC<6:0> 191 T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 159 TMR2 Timer2 Module Register 157 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. DS40001441F-page 188  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 24.5 Register Definitions: CCP Control REGISTER 24-1: CCP1CON: CCP1 CONTROL REGISTER R/W-00 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 P1M<1:0> DC1B<1:0> CCP1M<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 P1M<1:0>: Enhanced PWM Output Configuration bits Capture mode: Unused Compare mode: Unused PWM mode: If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B assigned as port pins(1) If CCP1M<3:2> = 11: 11 = Reserved 10 = Half-Bridge output; P1A, P1B modulated with dead-band control 01 = Reserved 00 = Single output; P1A modulated; P1B assigned as port pins bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP1 Mode Select bits 1011 = Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts ADC conversion if ADC module is enabled) 1010 = Compare mode: generate software interrupt only; ECCP1 pin reverts to I/O state 1001 = Compare mode: initialize ECCP1 pin high; clear output on compare match (set CCP1IF) 1000 = Compare mode: initialize ECCP1 pin low; set output on compare match (set CCP1IF) 0111 = Capture mode: every 16th rising edge 0110 = Capture mode: every 4th rising edge 0101 = Capture mode: every rising edge 0100 = Capture mode: every falling edge 0011 = Reserved 0010 = Compare mode: toggle output on match 0001 = Reserved 0000 = Capture/Compare/PWM off (resets ECCP1 module) PWM mode: 1111 = PWM mode: P1A active-low; P1B active-low 1110 = PWM mode: P1A active-low; P1B active-high 1101 = PWM mode: P1A active-high; P1B active-low 1100 = PWM mode: P1A active-high; P1B active-high  2011-2015 Microchip Technology Inc. DS40001441F-page 189

PIC12(L)F1840 REGISTER 24-2: CCP1AS: CCP1 AUTO-SHUTDOWN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP1ASE: CCP1 Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCP1 outputs are in shutdown state 0 = CCP1 outputs are operating bit 6-4 CCP1AS<2:0>: CCP1 Auto-Shutdown Source Select bits 111 =VIL on FLT0 pin or Comparator C1 low(1) 110 =Reserved 101 =VIL on FLT0 pin or Comparator C1 low(1) 100 =VIL on FLT0 pin 011 =Either Comparator C1 output low(1) 010 =Reserved 001 =Comparator C1 output low(1) 000 =Auto-shutdown is disabled bit 3-2 PSS1AC<1:0>: Pin P1A Shutdown State Control bits 1x = Pin P1A tri-state 01 = Drive pin P1A to ‘1’ 00 = Drive pin P1A to ‘0’ bit 1-0 PSS1BD<1:0>: Pin P1B Shutdown State Control bits 1x = Pin P1B tri-state 01 = Drive pin P1B to ‘1’ 00 = Drive pin P1B to ‘0’ Note 1: If C1SYNC is enabled, the shutdown will be delayed by Timer1. DS40001441F-page 190  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 24-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 P1RSEN P1DC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCP1ASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCP1ASE must be cleared in software to restart the PWM bit 6-0 P1DC<6:0>: PWM Delay Count bits P1DC1 =Number of FOSC/4 (4*TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. REGISTER 24-4: PSTR1CON: PWM STEERING CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 — — — STR1SYNC Reserved Reserved STR1B STR1A bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STR1SYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3-2 Reserved: Read as ‘0’. Maintain these bits clear. bit 1 STR1B: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1B pin is assigned to port pin bit 0 STR1A: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2>=11 and P1M<1:0>=00.  2011-2015 Microchip Technology Inc. DS40001441F-page 191

PIC12(L)F1840 25.0 MASTER SYNCHRONOUS SERIAL PORT MODULE 25.1 Master SSP (MSSP1) Module Overview The Master Synchronous Serial Port (MSSP1) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP1 module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) The SPI interface supports the following modes and features: • Master mode • Slave mode • Clock Parity • Slave Select Synchronization (Slave mode only) • Daisy-chain connection of slave devices Figure25-1 is a block diagram of the SPI interface module. FIGURE 25-1: MSSP1 BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSP1BUF Reg SDI SSP1SR Reg SDO bit 0 Shift Clock SS SS Control 2 (CKP, CKE) Enable Clock Select Edge Select SSP1M<3:0> 4 ( T M R 2 O u tp u t ) 2 SCK Edge Prescaler TOSC Select 4, 16, 64 Baud rate generator TRIS bit (SSP1ADD) DS40001441F-page 192  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 The I2C interface supports the following modes and features: • Master mode • Slave mode • Byte NACKing (Slave mode) • Limited Multi-master support • 7-bit and 10-bit addressing • Start and Stop interrupts • Interrupt masking • Clock stretching • Bus collision detection • General call address matching • Address masking • Address Hold and Data Hold modes • Selectable SDA hold times Figure25-2 is a block diagram of the I2C interface module in Master mode. Figure25-3 is a diagram of the I2C interface module in Slave mode. FIGURE 25-2: MSSP1 BLOCK DIAGRAM (I2C™ MASTER MODE) Internal data bus [SSP1M 3:0] Read Write SSP1BUF Baud rate generator (SSP1ADD) SDA Shift SDA in Clock SSP1SR ct e Enable (RCEN) GMeSnSbetAararcttk ebn i(otS,w SSletPod1pgC ebOitL,NS2b) Clock Cntl arbitrate/BCOL det d off clock source) SCL ceive Clock (Hol e R Start bit detect, Stop bit detect SCL in Write collision detect Set/Reset: S, P, SSP1STAT, WCOL, SSP1OV Clock arbitration Reset SEN, PEN (SSP1CON2) Bus Collision State counter for Set SSP1IF, BCL1IF end of XMIT/RCV Address Match detect  2011-2015 Microchip Technology Inc. DS40001441F-page 193

PIC12(L)F1840 FIGURE 25-3: MSSP1 BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSP1BUF Reg SCL Shift Clock SSP1SR Reg SDA MSb LSb SSP1MSK Reg Match Detect Addr Match SSP1ADD Reg Start and Set, Reset Stop bit Detect S, P bits (SSP1STAT Reg) DS40001441F-page 194  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.2 SPI Mode Overview During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master The Serial Peripheral Interface (SPI) bus is a device is sending out the MSb from its shift register (on synchronous serial data communication bus that its SDO pin) and the slave device is reading this bit and operates in Full-Duplex mode. Devices communicate saving it as the LSb of its shift register, that the slave in a master/slave environment where the master device device is also sending out the MSb from its shift register initiates the communication. A slave device is (on its SDO pin) and the master device is reading this controlled through a Chip Select known as Slave bit and saving it as the LSb of its shift register. Select. After eight bits have been shifted out, the master and The SPI bus specifies four signal connections: slave have exchanged register values. • Serial Clock (SCK) If there is more data to exchange, the shift registers are • Serial Data Out (SDO) loaded with new data and the process repeats itself. • Serial Data In (SDI) Whether the data is meaningful or not (dummy data), • Slave Select (SS) depends on the application software. This leads to Figure25-1 shows the block diagram of the MSSP1 three scenarios for data transmission: module when operating in SPI mode. • Master sends useful data and slave sends dummy The SPI bus operates with a single master device and data. one or more slave devices. When multiple slave • Master sends useful data and slave sends useful devices are used, an independent Slave Select data. connection is required from the master device to each • Master sends dummy data and slave sends useful slave device. data. Figure25-4 shows a typical connection between a Transmissions may involve any number of clock master device and multiple slave devices. cycles. When there is no more data to be transmitted, The master selects only one slave at a time. Most slave the master stops sending the clock signal and it devices have tri-state outputs so their output signal deselects the slave. appears disconnected from the bus when they are not Every slave device connected to the bus that has not selected. been selected through its slave select line must Transmissions involve two shift registers, eight bits in disregard the clock and transmission signals and must size, one in the master and one in the slave. With either not transmit out any data of its own. the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure25-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register.  2011-2015 Microchip Technology Inc. DS40001441F-page 195

PIC12(L)F1840 FIGURE 25-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS General I/O General I/O SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS 25.2.1 SPI MODE REGISTERS The MSSP1 module has five registers for SPI mode operation. These are: • MSSP1 STATUS register (SSP1STAT) • MSSP1 Control register 1 (SSP1CON1) • MSSP1 Control register 3 (SSP1CON3) • MSSP1 Data Buffer register (SSP1BUF) • MSSP1 Address register (SSP1ADD) • MSSP1 Shift register (SSP1SR) (Not directly accessible) SSP1CON1 and SSP1STAT are the control and STATUS registers in SPI mode operation. The SSP1CON1 register is readable and writable. The lower 6 bits of the SSP1STAT are read-only. The upper two bits of the SSP1STAT are read/write. In one SPI master mode, SSP1ADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section25.7 “Baud Rate Generator”. SSP1SR is the shift register used for shifting data in and out. SSP1BUF provides indirect access to the SSP1SR register. SSP1BUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSP1SR and SSP1BUF together create a buffered receiver. When SSP1SR receives a complete byte, it is transferred to SSP1BUF and the SSP1IF interrupt is set. During transmission, the SSP1BUF is not buffered. A write to SSP1BUF will write to both SSP1BUF and SSP1SR. DS40001441F-page 196  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.2.2 SPI MODE OPERATION When the application software is expecting to receive valid data, the SSP1BUF should be read before the When initializing the SPI, several options need to be next byte of data to transfer is written to the SSP1BUF. specified. This is done by programming the appropriate The Buffer Full bit, BF of the SSP1STAT register, control bits (SSP1CON1<5:0> and SSP1STAT<7:6>). indicates when SSP1BUF has been loaded with the These control bits allow the following to be specified: received data (transmission is complete). When the • Master mode (SCK1 is the clock output) SSP1BUF is read, the BF bit is cleared. This data may • Slave mode (SCK1 is the clock input) be irrelevant if the SPI is only a transmitter. Generally, the MSSP1 interrupt is used to determine when the • Clock Polarity (Idle state of SCK1) transmission/reception has completed. If the interrupt • Data Input Sample Phase (middle or end of data method is not going to be used, then software polling output time) can be done to ensure that a write collision does not • Clock Edge (output data on rising/falling edge of occur. SCK1) The SSP1SR is not directly readable or writable and • Clock Rate (Master mode only) can only be accessed by addressing the SSP1BUF • Slave Select mode (Slave mode only) register. Additionally, the SSP1STAT register indicates To enable the serial port, SSP1 Enable bit, SSP1EN of the various Status conditions. the SSP1CON1 register must be set. To reset or reconfigure SPI mode, clear the SSP1EN bit, re-initialize the SSP1CONx registers and then set the SSP1EN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Master mode) must have corresponding TRIS bit cleared • SCK (Slave mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSP1 consists of a transmit/receive shift register (SSP1SR) and a buffer register (SSP1BUF). The SSP1SR shifts the data in and out of the device, MSb first. The SSP1BUF holds the data that was written to the SSP1SR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSP1BUF register. Then, the Buffer Full Detect bit, BF of the SSP1STAT register, and the interrupt flag bit, SSP1IF, are set. This double-buffering of the received data (SSP1BUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSP1BUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL, of the SSP1CON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSP1BUF register to complete successfully.  2011-2015 Microchip Technology Inc. DS40001441F-page 197

PIC12(L)F1840 FIGURE 25-5: SPI MASTER/SLAVE CONNECTION SPI Master SSP1M<3:0> = 00xx SPI Slave SSP1M<3:0> = 010x = 1010 SDO SDI Serial Input Buffer Serial Input Buffer (BUF) (SSP1BUF) SDI SDO Shift Register Shift Register (SSP1SR) (SSP1SR) MSb LSb MSb LSb Serial Clock SCK SCK Slave Select General I/O SS Processor 1 (optional) Processor 2 DS40001441F-page 198  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.2.3 SPI MASTER MODE The clock polarity is selected by appropriately programming the CKP bit of the SSP1CON1 register The master can initiate the data transfer at any time and the CKE bit of the SSP1STAT register. This then, because it controls the SCK line. The master would give waveforms for SPI communication as determines when the slave (Processor 2, Figure25-5) shown in Figure25-6, Figure25-8, Figure25-9 and is to broadcast data by the software protocol. Figure25-10, where the MSB is transmitted first. In In Master mode, the data is transmitted/received as Master mode, the SPI clock rate (bit rate) is user soon as the SSP1BUF register is written to. If the SPI programmable to be one of the following: is only going to receive, the SDO output could be • FOSC/4 (or TCY) disabled (programmed as an input). The SSP1SR register will continue to shift in the signal present on the • FOSC/16 (or 4 * TCY) SDI pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY) received, it will be loaded into the SSP1BUF register as • Timer2 output/2 if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSP1ADD + 1)) appropriately set). Figure25-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSP1BUF is loaded with the received data is shown. FIGURE 25-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSP1BUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 0) SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (CKE = 1) SDI (SMP = 0) bit 7 bit 0 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSP1IF SSP1SR to SSP1BUF  2011-2015 Microchip Technology Inc. DS40001441F-page 199

PIC12(L)F1840 25.2.4 SPI SLAVE MODE 25.2.5 SLAVE SELECT SYNCHRONIZATION In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last The Slave Select can also be used to synchronize bit is latched, the SSP1IF interrupt flag bit is set. communication. The Slave Select line is held high until Before enabling the module in SPI Slave mode, the clock the master device is ready to communicate. When the line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a be observed by reading the SCK pin. The Idle state is new transmission is starting. determined by the CKP bit of the SSP1CON1 register. If the slave fails to receive the communication properly, While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the the external clock source on the SCK pin. This external Slave Select line returns to a high state. The slave is clock must meet the minimum high and low times as then ready to receive a new transmission when the specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will While in Sleep mode, the slave can transmit/receive eventually become out of sync with the master. If the data. The shift register is clocked from the SCK pin slave misses a bit, it will always be one bit off in future input and when a byte is received, the device will transmissions. Use of the Slave Select line allows the generate an interrupt. If enabled, the device will slave and master to align themselves at the beginning wake-up from Sleep. of each transmission. 25.2.4.1 Daisy-Chain Configuration The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled The SPI bus can sometimes be connected in a (SSP1CON1<3:0> = 0100). daisy-chain configuration. The first slave output is con- nected to the second slave input, the second slave When the SS pin is low, transmission and reception are output is connected to the third slave input, and so on. enabled and the SDO pin is driven. The final slave output is connected to the master input. When the SS pin goes high, the SDO pin is no longer Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down first group of clock pulses. The whole chain acts as resistors may be desirable depending on the one large communication shift register. The application. daisy-chain feature only requires a single Slave Select line from the master device. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSP1CON1<3:0> = Figure25-7 shows the block diagram of a typical 0100), the SPI module will reset if the SS daisy-chain connection when operating in SPI mode. pin is set to VDD. In a daisy-chain configuration, only the most recent 2: When the SPI is used in Slave mode with byte on the bus is required by the slave. Setting the CKE set; the user must enable SS pin BOEN bit of the SSP1CON3 register will enable writes control. to the SSP1BUF register, even if the previous byte has not been read. This allows the software to ignore data 3: While operated in SPI Slave mode the that may not apply to it. SMP bit of the SSP1STAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSP1EN bit. DS40001441F-page 200  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-7: SPI DAISY-CHAIN CONNECTION SCK SCK SPI Master SDO SDI SPI Slave SDI SDO #1 General I/O SS SCK SDI SPI Slave SDO #2 SS SCK SDI SPI Slave SDO #3 SS FIGURE 25-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Shift register SSP1SR and bit count are reset SSP1BUF to SSP1SR SDO bit 7 bit 6 bit 7 bit 6 bit 0 SDI bit 0 bit 7 bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF  2011-2015 Microchip Technology Inc. DS40001441F-page 201

PIC12(L)F1840 FIGURE 25-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE=0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active FIGURE 25-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSP1BUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active DS40001441F-page 202  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the In SPI Master mode, module clocks may be operating transmission/reception will remain in that state until the at a different speed than when in Full-Power mode; in device wakes. After the device returns to Run mode, the case of the Sleep mode, all clocks are halted. the module will resume transmitting and receiving data. Special care must be taken by the user when the In SPI Slave mode, the SPI Transmit/Receive Shift MSSP1 clock is much faster than the system clock. register operates asynchronously to the device. This In Slave mode, when MSSP1 interrupts are enabled, allows the device to be placed in Sleep mode and data after the master completes sending data, an MSSP1 to be shifted into the SPI Transmit/Receive Shift interrupt will wake the controller from Sleep. register. When all eight bits have been received, the MSSP1 interrupt flag bit will be set and if enabled, will If an exit from Sleep mode is not desired, MSSP1 wake the device. interrupts should be disabled. TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL 99 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 196* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 243 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 245 SSP1STAT SMP CKE D/A P S R/W UA BF 242 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode. * Page provides register information. Note 1: PIC12(L)F1840 only.  2011-2015 Microchip Technology Inc. DS40001441F-page 203

PIC12(L)F1840 25.3 I2C MODE OVERVIEW FIGURE 25-11: I2C MASTER/ SLAVE CONNECTION The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master VDD devices initiate the communication. A Slave device is controlled through addressing. SCL SCL The I2C bus specifies two signal connections: VDD • Serial Clock (SCL) Master Slave • Serial Data (SDA) SDA SDA Figure25-11 shows the block diagram of the MSSP1 module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal, supply voltage. Pulling the line to ground is considered which holds the SDA line low to indicate to the a logical zero and letting the line float is considered a transmitter that the slave device has received the logical one. transmitted data and is ready to receive more. Figure25-11 shows a typical connection between two The transition of a data bit is always performed while processors configured as master and slave devices. the SCL line is held low. Transitions that occur while the The I2C bus can operate with one or more master SCL line is held high are used to indicate Start and Stop devices and one or more slave devices. bits. There are four potential modes of operation for a given If the master intends to write to the slave, then it repeat- device: edly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the • Master Transmit mode master device is in Master Transmit mode and the (master is transmitting data to a slave) slave is in Slave Receive mode. • Master Receive mode If the master intends to read from the slave, then it (master is receiving data from a slave) repeatedly receives a byte of data from the slave, and • Slave Transmit mode responds after each byte with an ACK bit. In this (slave is transmitting data to a master) example, the master device is in Master Receive mode • Slave Receive mode and the slave is Slave Transmit mode. (slave is receiving data from the master) On the last byte of data communicated, the master To begin communication, a master device starts out in device may end the transmission by sending a Stop bit. Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is intends to communicate with. This is followed by a indicated by a low-to-high transition of the SDA line single Read/Write bit, which determines whether the while the SCL line is held high. master intends to transmit to or receive data from the In some cases, the master may want to maintain slave device. control of the bus and re-initiate another transmission. If the requested slave exists on the bus, it will respond If so, the master device may send another Start bit in with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive The master then continues in either Transmit mode or mode. Receive mode and the slave continues in the The I2C bus specifies three message protocols; complement, either in Receive mode or Transmit mode, respectively. • Single message where a master writes data to a slave. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and • Single message where a master reads data from data bytes are sent out, Most Significant bit (MSb) first. a slave. The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a out as a logical zero when it intends to write data to the combination of writes and reads, to one or more slave. slaves. DS40001441F-page 204  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 When one device is transmitting a logical one, or letting 25.3.2 ARBITRATION the line float, and a second device is transmitting a Each master device must monitor the bus for Start and logical zero, or holding the line low, the first device can Stop bits. If the device detects that the bus is busy, it detect that the line is not a logical one. This detection, cannot begin a new message until the bus returns to an when used on the SCL line, is called clock stretching. Idle state. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on However, two master devices may try to initiate a the SDA line, it is called arbitration. Arbitration ensures transmission on or about the same time. When this that there is only one master device communicating at occurs, the process of arbitration begins. Each any single time. transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first 25.3.1 CLOCK STRETCHING transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the When a slave device has not completed processing SDA line. data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device For example, if one transmitter holds the SDA line to a may hold the SCL clock line low after receiving or send- logical one (lets it float) and a second transmitter holds ing a bit, indicating that it is not yet ready to continue. it to a logical zero (pulls it low), the result is that the The master that is communicating with the slave will SDA line will be low. The first transmitter then observes attempt to raise the SCL line in order to transfer the that the level of the line is different than expected and next bit, but will detect that the clock line has not yet concludes that another transmitter is communicating. been released. Because the SCL connection is The first transmitter to notice this difference is the one open-drain, the slave has the ability to hold that line low that loses arbitration and must stop driving the SDA until it is ready to continue communicating. line. If this transmitter is also a master device, it also Clock stretching allows receivers that cannot keep up must stop driving the SCL line. It then can monitor the with a transmitter to control the flow of incoming data. lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitra- tion. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.  2011-2015 Microchip Technology Inc. DS40001441F-page 205

PIC12(L)F1840 25.4 I2C MODE OPERATION TABLE 25-2: I2C BUS TERMS All MSSP1 I2C communication is byte oriented and TERM Description shifted out MSb first. Six SFR registers and two Transmitter The device which shifts data out interrupt flags interface the module with the PIC® onto the bus. microcontroller and user software. Two pins, SDA and Receiver The device which shifts data in SCL, are exercised by the module to communicate from the bus. with other external I2C devices. Master The device that initiates a transfer, generates clock signals and 25.4.1 BYTE FORMAT terminates a transfer. All communication in I2C is done in 9-bit segments. A Slave The device addressed by the byte is sent from a master to a slave or vice-versa, master. followed by an Acknowledge bit sent back. After the Multi-master A bus with more than one device 8th falling edge of the SCL line, the device outputting that can initiate data transfers. data on the SDA changes that pin to an input and Arbitration Procedure to ensure that only one reads in an acknowledge value on the next clock master at a time controls the bus. pulse. Winning arbitration ensures that The clock signal, SCL, is provided by the master. Data the message is not corrupted. is valid to change while the SCL signal is low, and Synchronization Procedure to synchronize the sampled on the rising edge of the clock. Changes on clocks of two or more devices on the SDA line while the SCL line is high define special the bus. conditions on the bus, explained below. Idle No master is controlling the bus, 25.4.2 DEFINITION OF I2C TERMINOLOGY and both SDA and SCL lines are high. There is language and terminology in the description Active Any time one or more master of I2C communication that have definitions specific to devices are controlling the bus. I2C. That word usage is defined below and may be Addressed Slave device that has received a used in the rest of this document without explana- tion. This table was adapted from the Philips I2CTM Slave matching address and is actively being clocked by a master. specification. Matching Address byte that is clocked into a 25.4.3 SDA AND SCL PINS Address slave that matches the value Selection of any I2C mode with the SSP1EN bit set, stored in SSP1ADD. forces the SCL and SDA pins to be open-drain. These Write Request Slave receives a matching pins should be set by the user to inputs by setting the address with R/W bit clear, and is appropriate TRIS bits. ready to clock in data. Read Request Master sends an address byte with Note: Data is tied to output zero when an I2C the R/W bit set, indicating that it mode is enabled. wishes to clock data out of the Slave. This data is the next and all 25.4.4 SDA HOLD TIME following bytes until a Restart or The hold time of the SDA pin is selected by the SDAHT Stop. bit of the SSP1CON3 register. Hold time is the time Clock Stretching When a device on the bus hold SDA is held valid after the falling edge of SCL. Setting SCL low to stall communication. the SDAHT bit selects a longer 300ns minimum hold Bus Collision Any time the SDA line is sampled time and may help on buses with large capacitance. low by the module while it is out- putting and expected high state. DS40001441F-page 206  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.4.5 START CONDITION 25.4.7 RESTART CONDITION The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid. transition of SDA from a high to a low state while SCL A master can issue a Restart if it wishes to hold the line is high. A Start condition is always generated by bus after terminating the current transfer. A Restart the master and signifies the transition of the bus from has the same effect on the slave that a Start would, an Idle to an Active state. Figure25-12 shows wave resetting all slave logic and preparing it to clock in an forms for Start and Stop conditions. address. The master may want to address the same or A bus collision can occur on a Start condition if the another slave. Figure25-13 shows the wave form for a module samples the SDA line low before asserting it Restart condition. low. This does not conform to the I2C Specification that In 10-bit Addressing Slave mode a Restart is required states no bus collision can occur on a Start. for the master to clock data out of the addressed slave. Once a slave has been fully addressed, match- 25.4.6 STOP CONDITION ing both high and low address bytes, the master can A Stop condition is a transition of the SDA line from issue a Restart and the high address byte with the low-to-high state while the SCL line is high. R/W bit set. The slave logic will then hold the clock and prepare to clock out data. Note: At least one SCL low time must appear After a full match with R/W clear in 10-bit mode, a prior before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL match flag is set and maintained. Until a Stop line stays high, only the Start condition is condition, a high address with R/W clear, or high detected. address match fails. 25.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSP1CON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 25-12: I2C START AND STOP CONDITIONS SDA SCL S P Change of Change of Data Allowed Data Allowed Start Stop Condition Condition FIGURE 25-13: I2C RESTART CONDITION Sr Change of Change of Data Allowed Data Allowed Restart Condition  2011-2015 Microchip Technology Inc. DS40001441F-page 207

PIC12(L)F1840 25.4.9 ACKNOWLEDGE SEQUENCE 25.5 I2C SLAVE MODE OPERATION The 9th SCL pulse for any transferred byte in I2C is The MSSP1 Slave mode operates in one of four dedicated as an Acknowledge. It allows receiving modes selected in the SSP1M bits of SSP1CON1 devices to respond back to the transmitter by pulling register. The modes can be divided into 7-bit and the SDA line low. The transmitter must release control 10-bit Addressing mode. 10-bit Addressing modes of the line during this time to shift in the response. The operate the same as 7-bit with some additional Acknowledge (ACK) is an active-low signal, pulling the overhead for handling the larger addresses. SDA line low indicated to the transmitter that the Modes with Start and Stop bit interrupts operate the device has received the transmitted data and is ready same as the other modes with SSP1IF additionally to receive more. getting set upon detection of a Start, Restart, or Stop The result of an ACK is placed in the ACKSTAT bit of condition. the SSP1CON2 register. 25.5.1 SLAVE MODE ADDRESSES Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to The SSP1ADD register (Register25-6) contains the the transmitter. The ACKDT bit of the SSP1CON2 Slave mode address. The first byte received after a register is set/cleared to determine the response. Start or Restart condition is compared against the Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the AHEN and DHEN bits of the SSP1CON3 register are value is loaded into the SSP1BUF register and an clear. interrupt is generated. If the value does not match, the module goes idle and no indication is given to the There are certain conditions where an ACK will not be software that anything happened. sent by the slave. If the BF bit of the SSP1STAT regis- ter or the SSP1OV bit of the SSP1CON1 register are The SSP Mask register (Register25-5) affects the set when a byte is received. address matching process. See Section25.5.9 “SSP1 Mask Register” for more information. When the module is addressed, after the 8th falling edge of SCL on the bus, the ACKTIM bit of the 25.5.1.1 I2C Slave 7-bit Addressing Mode SSP1CON3 register is set. The ACKTIM bit indicates In 7-bit Addressing mode, the LSb of the received data the acknowledge time of the active bus. The ACKTIM byte is ignored when determining if there is an address Status bit is only active when the AHEN bit or DHEN match. bit is enabled. 25.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb’s of the 10-bit address and stored in bits 2 and 1 of the SSP1ADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSP1ADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSP1ADD. Even if there is not an address match; SSP1IF and UA are set, and SCL is held low until SSP1ADD is updated to receive a high byte again. When SSP1ADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001441F-page 208  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.5.2 SLAVE RECEPTION 25.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte Slave device reception with AHEN and DHEN set is clear, the R/W bit of the SSP1STAT register is operate the same as without these options with extra cleared. The received address is loaded into the interrupts and clock stretching added after the 8th SSP1BUF register and acknowledged. falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK When the overflow condition exists for a received the receive address or data byte, rather than the address, then not Acknowledge is given. An overflow hardware. This functionality adds support for PMBus™ condition is defined as either bit BF of the SSP1STAT that was not present on previous versions of this register is set, or bit SSP1OV of the SSP1CON1 module. register is set. The BOEN bit of the SSP1CON3 register modifies this operation. For more information This list describes the steps that need to be taken by see Register25-4. slave software to use these options for I2C communication. Figure25-16 displays a module using An MSSP1 interrupt is generated for each transferred both address and data holding. Figure25-17 includes data byte. Flag bit, SSP1IF, must be cleared by soft- the operation with the SEN bit of the SSP1CON2 ware. register set. When the SEN bit of the SSP1CON2 register is set, 1. S bit of SSP1STAT is set; SSP1IF is set if SCL will be held low (clock stretch) following each interrupt on Start detect is enabled. received byte. The clock must be released by setting the CKP bit of the SSP1CON1 register, except 2. Matching address with R/W bit clear is clocked sometimes in 10-bit mode. See Section25.2.3 “SPI in. SSP1IF is set and CKP cleared after the 8th Master Mode” for more detail. falling edge of SCL. 3. Slave clears the SSP1IF. 25.5.2.1 7-bit Addressing Reception 4. Slave can look at the ACKTIM bit of the This section describes a standard sequence of events SSP1CON3 register to determine if the SSP1IF for the MSSP1 module configured as an I2C Slave in was after or before the ACK. 7-bit Addressing mode. All decisions made by hard- 5. Slave reads the address value from SSP1BUF, ware or software and their effect on reception. clearing the BF flag. Figure25-14 and Figure25-15 is used as a visual 6. Slave sets ACK value clocked out to the master reference for this description. by setting ACKDT. This is a step by step process of what typically must 7. Slave releases the clock by setting CKP. be done to accomplish I2C communication. 8. SSP1IF is set after an ACK, not after a NACK. 1. Start bit detected. 9. If SEN=1 the slave hardware will stretch the 2. S bit of SSP1STAT is set; SSP1IF is set if clock after the ACK. interrupt on Start detect is enabled. 10. Slave clears SSP1IF. 3. Matching address with R/W bit clear is received. Note: SSP1IF is still set after the 9th falling edge 4. The slave pulls SDA low sending an ACK to the of SCL even if there is no clock stretching master, and sets SSP1IF bit. and BF has been cleared. Only if NACK is 5. Software clears the SSP1IF bit. sent to Master is SSP1IF not set 6. Software reads received address from 11. SSP1IF set and CKP cleared after 8th falling SSP1BUF clearing the BF flag. edge of SCL for a received data byte. 7. If SEN=1; Slave software sets CKP bit to 12. Slave looks at ACKTIM bit of SSP1CON3 to release the SCL line. determine the source of the interrupt. 8. The master clocks out a data byte. 13. Slave reads the received data from SSP1BUF 9. Slave drives SDA low sending an ACK to the clearing BF. master, and sets SSP1IF bit. 14. Steps 7-14 are the same for each received data 10. Software clears SSP1IF. byte. 11. Software reads the received byte from 15. Communication is ended by either the slave SSP1BUF clearing BF. sending an ACK=1, or the master sending a Stop condition. If a Stop is sent and Interrupt on 12. Steps 8-12 are repeated for all received bytes Stop Detect is disabled, the slave will only know from the master. by polling the P bit of the SSTSTAT register. 13. Master sends Stop condition, setting P bit of SSP1STAT, and the bus goes idle.  2011-2015 Microchip Technology Inc. DS40001441F-page 209

PIC12(L)F1840 FIGURE 25-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=0, DHEN=0) s Bus Master sendStop condition 1 P SSP1IF set on 9thfalling edge of SCL = K 9 C A D0 8 e Master eceiving Data D4D3D2D1 4567 eared by software SSP1OV set becausSSP1BUF is still full. ACK is not sent. e to R D5 3 Cl v F From Sla D7D6K 12 First byte of data is available in SSP1BU C 9 A D0 8 D1 7 ad e a D2 6 ware F is r Receiving Dat D5D4D3 345 Cleared by soft SSP1BU D6 2 D7 1 K 9 C A 8 A1 7 2 6 A s s dre A3 5 d A ng A4 4 vi ecei A5 3 R A6 2 A7 1 S V F O A L 1I 1 D C P F P S S S B S S S DS40001441F-page 210  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-15: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) Bus Master sends Stop condition P SSP1IF set on 9thfalling edge of SCL SCL is not heldlow becauseACK=1 K C 9 A D0 8 e Receive Data D7D6D5D4D3D2D1 1234567 Cleared by software First byte of data is available in SSP1BUF SSP1OV set becausSSP1BUF is still full. ACK is not sent. CKP is written to ‘’ in software,1releasing SCL N E S K AC 9 D0 8 ’1 o ‘ Data D2D1 67 KP is set t oftware, Receive D7D6D5D4D3 12345 Clock is held low until C Cleared by software SSP1BUF is read CKP is written to ‘’ in s1releasing SCL N E S K C A 9 0 = W R/ 8 A1 7 2 6 A s s dre A3 5 d e A A4 4 v ei ec A5 3 R 6 2 A A7 1 S V F O P SDA SCL SSP1I BF SSP1 CK  2011-2015 Microchip Technology Inc. DS40001441F-page 211

PIC12(L)F1840 FIGURE 25-16: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=1) Master sendsStop condition = 1 P No interruptafter not ACKfrom Slave CK 9 A are T to Received DataCKD7D6D5D4D3D2D1D0 912345678 Cleared by software a is read from SSP1BUF Slave softwsets ACKDnot ACK CKP set by software, SCL is released ACKTIM set by hardwareon 8th falling edge of SCL A at D D0 8 g Receiving Data D6D5D4D3D2D1 234567 SP1IF is set on h falling edge of CL, after ACK When DHEN = :1CKP is cleared byhardware on 8th fallinedge of SCL KTIM cleared bydware in 9th ng edge of SCL D7 1 S9tS ACharrisi K 9 ce C n A e Au Dq ses SCK se aA eleor Master Rto slave f Receiving Address A6A5A4A3A2A1 2345678 If AHEN=:1SSP1IF is set Address isread from SSBUF Slave softwareclears ACKDT to ACK the receivedbyte When AHEN = :1CKP is cleared by hardwareand SCL is stretched ACKTIM set by hardwareon 8th falling edge of SCL A7 1 S M SDA SCL SSP1IF BF ACKDT CKP ACKTI S P DS40001441F-page 212  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN= 1, AHEN=1, DHEN=1) Master sendsStop condition P No interrupt afterif not ACKfrom Slave CKP is not clearedif not ACK K 9 C A D0 8 s d D1 7 enK Receive Data D6D5D4D3D2 23456 SSP1BUF can beread any time beforenext byte is loaded Slave snot AC Set by software,release SCL D7 1 K C 9 A D0 8 F e K sequence Receive Data D7D6D5D4D3D2D1 1245673 Cleared by software Received data isavailable on SSP1BU When DHEN = ;1on the 8th falling edgeof SCL of a receiveddata byte, CKP is cleared ACKTIM is cleared by hardwaron 9th rising edge of SCL C A ster releasesA to slave for ACK 9 aD MS 8 s R/W = 0 Receiving Address A6A5A4A3A2A1 342567 Received address is loaded into SSP1BUF Slave software clearACKDT to ACKthe received byte When AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared KTIM is set by hardware8th falling edge of SCL A7 1 ACon S M TI SDA SCL P1IF BF CKDT CKP ACK S P S A S  2011-2015 Microchip Technology Inc. DS40001441F-page 213

PIC12(L)F1840 25.5.3 SLAVE TRANSMISSION 25.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set A master device can transmit a read request to a and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list SSP1STAT register is set. The received address is below outlines what software for a slave will need to loaded into the SSP1BUF register, and an ACK pulse do to accomplish a standard transmission. is sent by the slave on the ninth bit. Figure25-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and and the SCL pin is held low (see Section25.5.6 SCL. “Clock Stretching” for more detail). By stretching the 2. S bit of SSP1STAT is set; SSP1IF is set if clock, the master will be unable to assert another clock interrupt on Start detect is enabled. pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by data. the Slave setting SSP1IF bit. The transmit data must be loaded into the SSP1BUF 4. Slave hardware generates an ACK and sets register which also loads the SSP1SR register. Then SSP1IF. the SCL pin should be released by setting the CKP bit 5. SSP1IF bit is cleared by user. of the SSP1CON1 register. The eight data bits are 6. Software reads the received address from shifted out on the falling edge of the SCL input. This SSP1BUF, clearing BF. ensures that the SDA signal is valid during the SCL 7. R/W is set so CKP was automatically cleared high time. after the ACK. The ACK pulse from the master-receiver is latched on 8. The slave software loads the transmit data into the rising edge of the ninth SCL input pulse. This ACK SSP1BUF. value is copied to the ACKSTAT bit of the SSP1CON2 register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCL, allowing the mas- transfer is complete. In this case, when the not ACK is ter to clock the data out of the slave. latched by the slave, the slave goes idle and waits for 10. SSP1IF is set after the ACK response from the another occurrence of the Start bit. If the SDA line was master is loaded into the ACKSTAT register. low (ACK), the next transmit data must be loaded into 11. SSP1IF bit is cleared. the SSP1BUF register. Again, the SCL pin must be 12. The slave software checks the ACKSTAT bit to released by setting bit CKP. see if the master wants to clock out more data. An MSSP1 interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be byte. The SSP1IF bit must be cleared by software and stretched. the SSP1STAT register is used to determine the status 2: ACKSTAT is the only bit updated on the of the byte. The SSP1IF bit is set on the falling edge of rising edge of SCL (9th) rather than the the ninth clock pulse. falling. 25.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted A slave receives a Read request and begins shifting byte. data out on the SDA line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not and the SBCDE bit of the SSP1CON3 register is set, held, but SSP1IF is still set. the BCL1IF bit of the PIRx register is set. Once a bus 15. The master sends a Restart condition or a Stop. collision is detected, the slave goes idle and waits to be 16. The slave is no longer addressed. addressed again. User software can use the BCL1IF bit to handle a slave bus collision. DS40001441F-page 214  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=0) sn do enditi er scon P stp ao MSt K C 9 A Transmitting Data D7D6D5D4D3D2D1D0 12345678 BF is automatically cleared after 8th fallingedge of SCL CKP is not held for not ACK Masters not ACKis copied to ACKSTAT c ati m o ut A K AC 9 D0 8 1 D 7 a Dat D2 6 Transmitting D7D6D5D4D3 12345 Cleared by software Data to transmit isloaded into SSPBUF Set by software c ati m o ut A 1CK =A 9 W R/ 8 eceiving Address A5A4A3A2A1 34567 Received addressis read from SSPBUF When R/W is setSCL is alwaysheld low after 9th SCLfalling edge R/W is copied from the matching address byte Indicates an address has been received R 6 A 2 7 A 1 S T A SDA SCL SSPIF BF CKP ACKST R/W D/A S P  2011-2015 Microchip Technology Inc. DS40001441F-page 215

PIC12(L)F1840 25.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSP1CON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure25-19 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. Bus starts Idle. 2. Master sends Start condition; the S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSP1IF interrupt is generated. 4. Slave software clears SSP1IF. 5. Slave software reads ACKTIM bit of SSP1CON3 register, and R/W and D/A of the SSP1STAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSP1BUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSP1CON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSP1IF after the ACK if the R/W bit is set. 11. Slave software clears SSP1IF. 12. Slave loads value to transmit to the master into SSP1BUF setting the BF bit. Note: SSP1BUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit, releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSP1CON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus, allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001441F-page 216  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-19: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN=1) endsdition sn aster op co P MSt K C A 9 0 D 8 Transmitting Data D6D5D4D3D2D1 234567 BF is automatically cleared after 8th fallingedge of SCL Master’s ACKresponse is copiedto SSP1STAT CKP not cleared after not ACK 7 D 1 c ati m o AutK C A 9 D0 8 1 a D 7 at D 2 ence omaticTransmitting D7D6D5D4D3D 123456 Cleared by software Data to transmit isloaded into SSP1BUF Set by software,releases SCL KTIM is cleared9th rising edge of SCL DAequ Aut ACon Ss K Master releases to slave for ACK W=1AC 9 When R/W = ;1CKP is alwayscleared after ACK R/ 8 UF K Receiving Address A7A6A5A4A3A2A1 1234567 Received addressis read from SSP1B Slave clearsACKDT to ACaddress When AHEN = ;1CKP is cleared by hardwareafter receiving matchingaddress. ACKTIM is set on 8th fallingedge of SCL S SDA SCL P1IF BF KDT TAT CKP TIM R/W D/A S C S K S A K C C A A  2011-2015 Microchip Technology Inc. DS40001441F-page 217

PIC12(L)F1840 25.5.4 SLAVE MODE 10-BIT ADDRESS 25.5.5 10-BIT ADDRESSING WITH ADDRESS OR RECEPTION DATA HOLD This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or for the MSSP1 module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only 10-bit Addressing mode. difference is the need to update the SSP1ADD register using the UA bit. All functionality, specifically when the Figure25-20 is used as a visual reference for this CKP bit is cleared and SCL line is held low are the description. same. Figure25-21 can be used as a reference of a This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set. slave software to accomplish I2C communication. Figure25-22 shows a standard waveform for a slave 1. Bus starts Idle. transmitter in 10-bit Addressing mode. 2. Master sends Start condition; S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. 3. Master sends matching high address with R/W bit clear; UA bit of the SSP1STAT register is set. 4. Slave sends ACK and SSP1IF is set. 5. Software clears the SSP1IF bit. 6. Software reads received address from SSP1BUF clearing the BF flag. 7. Slave loads low address into SSP1ADD, releasing SCL. 8. Master sends matching low address byte to the slave; UA bit is set. Note: Updates to the SSP1ADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSP1IF is set. Note: If the low address does not match, SSP1IF and UA are still set so that the slave soft- ware can set SSP1ADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSP1IF. 11. Slave reads the received matching address from SSP1BUF clearing BF. 12. Slave loads high address into SSP1ADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSP1IF is set. 14. If SEN bit of SSP1CON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSP1IF. 16. Slave reads the received byte from SSP1BUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001441F-page 218  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-20: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=1, AHEN=0, DHEN=0) endsdition er scon P stp ao MSt K C 9 A 0 8 D ata D1 7 dBUF D 2 6 a1 Receive D6D5D4D3D 2345 SCL is held lowwhile CKP = 0 Data is refrom SSP Set by software,releasing SCLyte D7 1 d b e v K cei Receive Data D6D5D4D3D2D1D0AC 92345678 Cleared by software Receive address isread from SSP1BUF When SEN = ;1CKP is cleared after9th falling edge of re D7 1 K C e A 9 Byt A0 8 DD ess A1 7 P1A Receive Second Addr A6A5A4A3A2 23456 Software updates SSand releases SCL A7 1 K C 9 A o ve First Address Byte 0A9A811 345678 Set by hardwareon 9th falling edge If address matchesSSP1ADD it is loaded intSSP1BUF When UA = ;1SCL is held low ei 1 2 c e R 1 1 S A L F F A P D C 1I B U K S S P C S S  2011-2015 Microchip Technology Inc. DS40001441F-page 219

PIC12(L)F1840 FIGURE 25-21: I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN=0, AHEN=1, DHEN=0) a Receive Data D7D6D5 12 Received datis read from SSP1BUF K C 9 A D0 8 D1 7 s D,se Receive Data D6D5D4D3D2 23456 eared by software Update of SSP1ADclears UA and releaSCL CKP with software ases SCL D7 1 Cl Set rele A U K C 9 A 0 A 8 Receive Second Address Byte A6A5A4A3A2A1 345672 ed by software SSP1BUF can beread anytime beforethe next received byte ate to SSP1ADD isallowed until 9thng edge of SCL A7 1 Clear Updnot falli A U K C 9 A 0 = W 8 R/ e eive First Address Byte A9A8110 34567 Set by hardwareon 9th falling edge Slave software clearsACKDT to ACKthe received byte If when AHEN=;1on the 8th falling edgeof SCL of an addressbyte, CKP is cleared ACKTIM is set by hardwaron 8th falling edge of SCL ec 1 2 R 1 1 S F T M SDA SCL SSP1I BF ACKD UA CKP ACKTI DS40001441F-page 220  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN=0, AHEN=0, DHEN=0) ends dition er scon P MastStop K = 1 ds AC 9 en D0 8 K Master snot ACK Transmitting Data Byte D7D6D5D4D3D2D1 1723456 Data to transmit isloaded into SSP1BUF Set by softwarereleases SCL Masters not ACis copied K C A 9 e 8 aster sends estart event Receive First Address Byt A9A811110 1672345Sr Set by hardware Received address isread from SSP1BUF High address is loadedback into SSP1ADD When R/W = ;1CKP is cleared on9th falling edge of SCL R/W is copied from thematching address byte MR K yte AC 9 s B A0 8 ed eiving Second Addres A6A5A4A3A2A1 672345 Cleared by software After SSP1ADD isupdated, UA is clearand SCL is released c Re A7 1 K = 0 AC 9 W 8 Receiving AddressR/ A9A811110 1672345 Set by hardware SSP1BUF loadedwith received address UA indicates SSP1ADDmust be updated Indicates an addresshas been received S AT T S SDA SCL P1IF BF UA CKP ACK R/W D/A S S  2011-2015 Microchip Technology Inc. DS40001441F-page 221

PIC12(L)F1840 25.5.6 CLOCK STRETCHING Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSP1CON1 register is used to con- trol stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 25.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSP1STAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSP1BUF with data to transfer to the master. If the SEN bit of SSP1CON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSP1BUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSP1BUF was loaded before the 9th fall- ing edge of SCL. It is now always cleared for read requests. 25.5.6.2 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSP1ADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 25.5.6.3 Byte NACKing When AHEN bit of SSP1CON3 is set; CKP is cleared by hardware after the 8th falling edge of SCL for a received matching address byte. When DHEN bit of SSP1CON3 is set; CKP is cleared after the 8th falling edge of SCL for received data. Stretching after the 8th falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. DS40001441F-page 222  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.5.7 CLOCK SYNCHRONIZATION AND released SCL. This ensures that a write to the CKP bit THE CKP BIT will not violate the minimum high time requirement for SCL (see Figure25-23). Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. There- fore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have FIGURE 25-23: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX ‚ – 1 SCL Master device CKP asserts clock Master device releases clock WR SSP1CON1  2011-2015 Microchip Technology Inc. DS40001441F-page 223

PIC12(L)F1840 25.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as the first byte after the Start condition usually it would in 7-bit mode. determines which device will be the slave addressed by the master device. The exception is the general call If the AHEN bit of the SSP1CON3 register is set, just address which can address all devices. When this as with any other address reception, the slave address is used, all devices should, in theory, respond hardware will stretch the clock after the 8th falling with an acknowledge. edge of SCL. The slave must then set its ACKDT value and release the clock with communication The general call address is a reserved address in the progressing as it would normally. I2C protocol, defined as address 0x00. When the GCEN bit of the SSP1CON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSP1ADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSP1BUF and respond. Figure25-24 shows a General Call reception sequence. FIGURE 25-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 Receiving Data ACK SDA General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 S SSPIF BF (SSPSTAT<0>) Cleared by software SSPBUF is read GCEN (SSP1CON2<7>) ’1’ 25.5.9 SSP1 MASK REGISTER An SSP1 Mask (SSP1MSK) register (Register25-5) is available in I2C Slave mode as a mask for the value held in the SSP1SR register during an address comparison operation. A zero (‘0’) bit in the SSP1MSK register has the effect of making the corresponding bit of the received address a “don’t care.” This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP1 operation until written with a mask value. The SSP1 Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSP1 mask has no effect during the reception of the first (high) byte of the address. DS40001441F-page 224  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.6 I2C MASTER MODE 25.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the The master device generates all of the serial clock appropriate SSPM bits in the SSP1CON1 register and pulses and the Start and Stop conditions. A transfer is by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will not be released. controls when necessary to drive the pins low. In Master Transmitter mode, serial data is output Master mode of operation is supported by interrupt through SDA, while SCL outputs the serial clock. The generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. from a Reset or when the MSSP1 module is disabled. Control of the I2C bus may be taken when the P bit is In this case, the R/W bit will be logic ‘0’. Serial data is set, or the bus is Idle. transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and In Firmware Controlled Master mode, user code Stop conditions are output to indicate the beginning conducts all I2C bus operations based on Start and and the end of a serial transfer. Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted con- other communication is done by the user software tains the slave address of the transmitting device directly manipulating the SDA and SCL lines. (7bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave The following events will cause the SSP1 Interrupt Flag address followed by a ‘1’ to indicate the receive bit. bit, SSP1IF, to be set (SSP1 interrupt, if enabled): Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After • Start condition detected each byte is received, an Acknowledge bit is transmit- • Stop condition detected ted. Start and Stop conditions indicate the beginning • Data transfer byte transmitted/received and end of transmission. • Acknowledge transmitted/received A Baud Rate Generator is used to set the clock • Repeated Start generated frequency output on SCL. See Section25.7 “Baud Note 1: The MSSP1 module, when configured in Rate Generator” for more detail. I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSP1BUF register to initiate transmission before the Start condition is complete. In this case, the SSP1BUF will not be written to and the WCOL bit will be set, indicating that a write to the SSP1BUF did not occur 2: When in Master mode, Start/Stop detec- tion is masked and an interrupt is gener- ated when the SEN/PEN bit is cleared and the generation is complete.  2011-2015 Microchip Technology Inc. DS40001441F-page 225

PIC12(L)F1840 25.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure25-25). FIGURE 25-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX ‚ – 1 SCL deasserted but slave holds SCL allowed to transition high SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG 03h 02h 01h 00h (hold off) 03h 02h Value SCL is sampled high, reload takes place and BRG starts its count BRG Reload 25.6.3 WCOL STATUS FLAG If the user writes the SSP1BUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSP1BUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower 5 bits of SSP1CON2 is disabled until the Start condition is complete. DS40001441F-page 226  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, CONDITION TIMING leaving the SDA line held low and the Start condition is complete. To initiate a Start condition (Figure25-26), the user sets the Start Enable bit, SEN bit of the SSP1CON2 register. If the SDA and SCL pins are sampled high, Note 1: If at the beginning of the Start condition, the Baud Rate Generator is reloaded with the contents the SDA and SCL pins are already sam- of SSP1ADD<7:0> and starts its count. If SCL and pled low, or if during the Start condition, SDA are both sampled high when the Baud Rate the SCL line is sampled low before the Generator times out (TBRG), the SDA pin is driven low. SDA line is driven low, a bus collision The action of the SDA being driven low while SCL is occurs, the Bus Collision Interrupt Flag, high is the Start condition and causes the S bit of the BCL1IF, is set, the Start condition is SSP1STAT1 register to be set. Following this, the aborted and the I2C module is reset into Baud Rate Generator is reloaded with the contents of its Idle state. SSP1ADD<7:0> and resumes its count. When the 2: The Philips I2C Specification states that a Baud Rate Generator times out (TBRG), the SEN bit of bus collision cannot occur on a Start. the SSP1CON2 register will be automatically cleared FIGURE 25-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSP1STAT<3>) At completion of Start bit, SDA = 1, hardware clears SEN bit SCL = 1 and sets SSP1IF bit TBRG TBRG Write to SSP1BUF occurs here SDA 1st bit 2nd bit TBRG SCL S TBRG  2011-2015 Microchip Technology Inc. DS40001441F-page 227

PIC12(L)F1840 25.6.5 I2C MASTER MODE REPEATED cally cleared and the Baud Rate Generator will not be START CONDITION TIMING reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, A Repeated Start condition (Figure25-27) occurs when the S bit of the SSP1STAT register will be set. The the RSEN bit of the SSP1CON2 register is SSP1IF bit will not be set until the Baud Rate Generator programmed high and the master state machine is no has timed out. longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Note1: If RSEN is programmed while any other Baud Rate Generator is loaded and begins counting. event is in progress, it will not take effect. The SDA pin is released (brought high) for one Baud 2: A bus collision during the Repeated Start Rate Generator count (TBRG). When the Baud Rate condition occurs if: Generator times out, if SDA is sampled high, the SCL • SDA is sampled low when SCL pin will be deasserted (brought high). When SCL is goes from low-to-high. sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled • SCL goes low before SDA is high for one TBRG. This action is then followed by asserted low. This may indicate assertion of the SDA pin (SDA=0) for one TBRG while that another master is attempting to SCL is high. SCL is asserted low. Following this, the transmit a data ‘1’. RSEN bit of the SSP1CON2 register will be automati- FIGURE 25-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSP1CON2 occurs here At completion of Start bit, SDA = 1, SDA = 1, hardware clears RSEN bit SCL (no change) SCL = 1 and sets SSP1IF TBRG TBRG TBRG SDA 1st bit Write to SSP1BUF occurs here TBRG SCL Sr TBRG Repeated Start DS40001441F-page 228  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.6.6 I2C MASTER MODE TRANSMISSION 25.6.6.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSP1CON2 other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an writing a value to the SSP1BUF register. This action will Acknowledge (ACK=0) and is set when the slave set the Buffer Full flag bit, BF, and allow the Baud Rate does not Acknowledge (ACK=1). A slave sends an Generator to begin counting and start the next trans- Acknowledge when it has recognized its address mission. Each bit of address/data will be shifted out (including a general call), or when the slave has onto the SDA pin after the falling edge of SCL is properly received its data. asserted. SCL is held low for one Baud Rate Generator 25.6.6.4 Typical transmit sequence: rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it 1. The user generates a Start condition by setting is held that way for TBRG. The data on the SDA pin the SEN bit of the SSP1CON2 register. must remain stable for that duration and some hold 2. SSP1IF is set by hardware on completion of the time after the next falling edge of SCL. After the eighth Start. bit is shifted out (the falling edge of the eighth clock), 3. SSP1IF is cleared by software. the BF flag is cleared and the master releases SDA. 4. The MSSP1 module will wait the required start This allows the slave device being addressed to time before any other operation takes place. respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received prop- 5. The user loads the SSP1BUF with the slave erly. The status of ACK is written into the ACKSTAT bit address to transmit. on the rising edge of the ninth clock. If the master 6. Address is shifted out the SDA pin until all eight receives an Acknowledge, the Acknowledge Status bit, bits are transmitted. Transmission begins as ACKSTAT, is cleared. If not, the bit is set. After the ninth soon as SSP1BUF is written to. clock, the SSP1IF bit is set and the master clock (Baud 7. The MSSP1 module shifts in the ACK bit from Rate Generator) is suspended until the next data byte the slave device and writes its value into the is loaded into the SSP1BUF, leaving SCL low and SDA ACKSTAT bit of the SSP1CON2 register. unchanged (Figure25-28). 8. The MSSP1 module generates an interrupt at After the write to the SSP1BUF, each bit of the address the end of the ninth clock cycle by setting the will be shifted out on the falling edge of SCL until all SSP1IF bit. seven address bits and the R/W bit are completed. On 9. The user loads the SSP1BUF with eight bits of the falling edge of the eighth clock, the master will data. release the SDA pin, allowing the slave to respond with 10. Data is shifted out the SDA pin until all eight bits an Acknowledge. On the falling edge of the ninth clock, are transmitted. the master will sample the SDA pin to see if the address 11. The MSSP1 module shifts in the ACK bit from was recognized by a slave. The status of the ACK bit is the slave device and writes its value into the loaded into the ACKSTAT Status bit of the SSP1CON2 ACKSTAT bit of the SSP1CON2 register. register. Following the falling edge of the ninth clock transmission of the address, the SSP1IF is set, the BF 12. Steps 8-11 are repeated for all transmitted data flag is cleared and the Baud Rate Generator is turned bytes. off until another write to the SSP1BUF takes place, 13. The user generates a Stop or Restart condition holding SCL low and allowing SDA to float. by setting the PEN or RSEN bits of the SSP1CON2 register. Interrupt is generated 25.6.6.1 BF Status Flag once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSP1STAT register is set when the CPU writes to SSP1BUF and is cleared when all eight bits are shifted out. 25.6.6.2 WCOL Status Flag If the user writes the SSP1BUF when a transmit is already in progress (i.e., SSP1SR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission.  2011-2015 Microchip Technology Inc. DS40001441F-page 229

PIC12(L)F1840 FIGURE 25-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) ACKSTAT in SSP1CON2 = 1 P ared by software K e C 9 Cl > A 6 2< D0 8 e N n slave, clear ACKSTAT bit SSP1CO Transmitting Data or Second Halfof 10-bit Address D6D5D4D3D2D1 234567 Cleared by software service routifrom SSP1 interrupt SSP1BUF is written by software om D7 1 1IF Fr w SP o S = 0 SCL held lwhile CPUsponds to CK re = 0 A W 9 are R/W A1 ess and R/ 78 d by hardw ave A2 addr 6 eare P1CON2<0> SEN = 1dition begins SEN = 0 Transmit Address to Sl A7A6A5A4A3 SSP1BUF written with 7-bit start transmit 12345 Cleared by software SSP1BUF written After Start condition, SEN cl Sn Write SStart co S T<0>) A T S 1 1IF SSP SDA SCL SSP BF ( SEN PEN R/W DS40001441F-page 230  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.6.7 I2C MASTER MODE RECEPTION 25.6.7.4 Typical Receive Sequence: Master mode reception (Figure25-29) is enabled by 1. The user generates a Start condition by setting programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSP1CON2 register. SSP1CON2 register. 2. SSP1IF is set by hardware on completion of the Note: The MSSP1 module must be in an Idle Start. state before the RCEN bit is set or the 3. SSP1IF is cleared by software. RCEN bit will be disregarded. 4. User writes SSP1BUF with the slave address to transmit and the R/W bit set. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes 5. Address is shifted out the SDA pin until all eight (high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as SSP1SR. After the falling edge of the eighth clock, the soon as SSP1BUF is written to. receive enable flag is automatically cleared, the con- 6. The MSSP1 module shifts in the ACK bit from tents of the SSP1SR are loaded into the SSP1BUF, the the slave device and writes its value into the BF flag bit is set, the SSP1IF flag bit is set and the Baud ACKSTAT bit of the SSP1CON2 register. Rate Generator is suspended from counting, holding 7. The MSSP1 module generates an interrupt at SCL low. The MSSP1 is now in Idle state awaiting the the end of the ninth clock cycle by setting the next command. When the buffer is read by the CPU, SSP1IF bit. the BF flag bit is automatically cleared. The user can 8. User sets the RCEN bit of the SSP1CON2 then send an Acknowledge bit at the end of reception register and the master clocks in a byte from the by setting the Acknowledge Sequence Enable, ACKEN slave. bit of the SSP1CON2 register. 9. After the 8th falling edge of SCL, SSP1IF and 25.6.7.1 BF Status Flag BF are set. 10. Master clears SSP1IF and reads the received In receive operation, the BF bit is set when an address byte from SSP1UF, clears BF. or data byte is loaded into SSP1BUF from SSP1SR. It 11. Master sets ACK value sent to slave in ACKDT is cleared when the SSP1BUF register is read. bit of the SSP1CON2 register and initiates the 25.6.7.2 SSP1OV Status Flag ACK by setting the ACKEN bit. 12. Masters ACK is clocked out to the slave and In receive operation, the SSP1OV bit is set when eight SSP1IF is set. bits are received into the SSP1SR and the BF flag bit is already set from a previous reception. 13. User clears SSP1IF. 14. Steps 8-13 are repeated for each received byte 25.6.7.3 WCOL Status Flag from the slave. If the user writes the SSP1BUF when a receive is 15. Master sends a not ACK or Stop to end already in progress (i.e., SSP1SR is still shifting in a communication. data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).  2011-2015 Microchip Technology Inc. DS40001441F-page 231

PIC12(L)F1840 FIGURE 25-29: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) pt Write to SSP1CON2<4>to start Acknowledge sequenceSDA = ACKDT (SSP1CON2<5>) = 0 Set ACKEN, start Acknowledge sequenceACK from MasterMaster configured as a receiverSDA = ACKDT = SDA = ACKDT = 10by programming SSP1CON2<3> (RCEN = )1PEN bit = 1RCEN = , startRCEN cleared1RCEN clearedwritten hereom Slavenext receiveautomaticallyautomatically Receiving Data from SlaveReceiving Data from SlaveACKD0D2D5D2D5D3D4D6D7D3D4D6D7D1D1ACKD0WACK Bus masterACK is not sentterminatestransfer9967895876512343124PSet SSP1IF at endData shifted in on falling edge of CLKof receiveSet SSP1IF interruat end of Acknow-Set SSP1IF interruptSet SSP1IF interruptledge sequenceat end of receiveat end of Acknowledgesequence Set P bit Cleared by softwareCleared by softwareCleared by software(SSP1STAT<4>)Cleared insoftwareand SSP1IF Last bit is shifted into SSP1SR andcontents are unloaded into SSP1BUF SSP1OV is set becauseSSP1BUF is still full Master configured as a receiverRCEN clearedACK from MasterRCEN clearedSDA\ = ACKDT = automatically0by programming SSP1CON2<3> (RCEN = )automatically1 K fr R/ 8 AC A1 7 e, Write to SSP1CON2<0>(SEN = ),1begin Start condition SEN = 0Write to SSP1BUF occurs herstart XMIT Transmit Address to Slave A7A6A5A4A3A2SDA 361245SCLS SSP1IF Cleared by softwareSDA = , SCL = 01while CPU responds to SSP1IF BF (SSP1STAT<0>) SSP1OV ACKEN RCEN DS40001441F-page 232  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.6.8 ACKNOWLEDGE SEQUENCE 25.6.9 STOP CONDITION TIMING TIMING A Stop bit is asserted on the SDA pin at the end of a An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSP1CON2 register. At the end of a SSP1CON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set, are presented on the SDA pin. If the user wishes to gen- the master will assert the SDA line low. When the SDA erate an Acknowledge, then the ACKDT bit should be line is sampled low, the Baud Rate Generator is cleared. If not, the user should set the ACKDT bit before reloaded and counts down to ‘0’. When the Baud Rate starting an Acknowledge sequence. The Baud Rate Generator times out, the SCL pin will be brought high Generator then counts for one rollover period (TBRG) and one TBRG (Baud Rate Generator rollover count) and the SCL pin is deasserted (pulled high). When the later, the SDA pin will be deasserted. When the SDA SCL pin is sampled high (clock arbitration), the Baud pin is sampled high while SCL is high, the P bit of the Rate Generator counts for TBRG. The SCL pin is then SSP1STAT register is set. A TBRG later, the PEN bit is pulled low. Following this, the ACKEN bit is automatically cleared and the SSP1IF bit is set (Figure25-31). cleared, the Baud Rate Generator is turned off and the 25.6.9.1 WCOL Status Flag MSSP1 module then goes into Idle mode (Figure25-30). If the user writes the SSP1BUF when a Stop sequence is in progress, then the WCOL bit is set and the 25.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does If the user writes the SSP1BUF when an Acknowledge not occur). sequence is in progress, then WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 25-30: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, ACKEN automatically cleared write to SSP1CON2 ACKEN = 1, ACKDT = 0 TBRG TBRG SDA D0 ACK SCL 8 9 SSP1IF Cleared in SSP1IF set at Cleared in software the end of receive software SSP1IF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period.  2011-2015 Microchip Technology Inc. DS40001441F-page 233

PIC12(L)F1840 FIGURE 25-31: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSP1CON2, SCL = 1 for TBRG, followed by SDA = 1 for TBRG set PEN after SDA sampled high. P bit (SSP1STAT<4>) is set. Falling edge of PEN bit (SSP1CON2<2>) is cleared by 9th clock hardware and the SSP1IF bit is set TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 25.6.10 SLEEP OPERATION 25.6.13 MULTI -MASTER COMMUNICATION, While in Sleep mode, the I2C slave module can receive BUS COLLISION AND BUS ARBITRATION addresses or data and when an address match or complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus from Sleep (if the MSSP1 interrupt is enabled). arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the 25.6.11 EFFECTS OF A RESET master outputs a ‘1’ on SDA, by letting SDA float high A Reset disables the MSSP1 module and terminates and another master asserts a ‘0’. When the SCL pin the current transfer. floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is 25.6.12 MULTI-MASTER MODE ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCL1IF, and reset In Multi-Master mode, the interrupt generation on the the I2C port to its Idle state (Figure25-32). detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is MSSP1 module is disabled. Control of the I2C bus may cleared, the SDA and SCL lines are deasserted and the be taken when the P bit of the SSP1STAT register is SSP1BUF can be written to. When the user services set, or the bus is Idle, with both the S and P bits clear. the bus collision Interrupt Service Routine and if the I2C When the bus is busy, enabling the SSP interrupt will bus is free, the user can resume communication by generate the interrupt when the Stop condition occurs. asserting a Start condition. In multi-master operation, the SDA line must be If a Start, Repeated Start, Stop or Acknowledge monitored for arbitration to see if the signal level is the condition was in progress when the bus collision expected output level. This check is performed by occurred, the condition is aborted, the SDA and SCL hardware with the result placed in the BCL1IF bit. lines are deasserted and the respective control bits in the SSP1CON2 register are cleared. When the user The states where arbitration can be lost are: services the bus collision Interrupt Service Routine and • Address Transfer if the I2C bus is free, the user can resume • Data Transfer communication by asserting a Start condition. • A Start Condition The master will continue to monitor the SDA and SCL • A Repeated Start Condition pins. If a Stop condition occurs, the SSP1IF bit will be set. • An Acknowledge Condition A write to the SSP1BUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSP1STAT register, or the bus is Idle and the S and P bits are cleared. DS40001441F-page 234  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Sample SDA. While SCL is high, Data changes SDA line pulled low data does not match what is driven while SCL = 0 by another source by the master. Bus collision has occurred. SDA released by master SDA SCL Set bus collision interrupt (BCL1IF) BCL1IF  2011-2015 Microchip Technology Inc. DS40001441F-page 235

PIC12(L)F1840 25.6.13.1 Bus Collision During a Start If the SDA pin is sampled low during this count, the Condition BRG is reset and the SDA line is asserted early (Figure25-35). If, however, a ‘1’ is sampled on the SDA During a Start condition, a bus collision occurs if: pin, the SDA pin is asserted low at the end of the BRG a) SDA or SCL are sampled low at the beginning of count. The Baud Rate Generator is then reloaded and the Start condition (Figure25-33). counts down to zero; if the SCL pin is sampled as ‘0’ b) SCL is sampled low before SDA is asserted low during this time, a bus collision does not occur. At the (Figure25-34). end of the BRG count, the SCL pin is asserted low. During a Start condition, both the SDA and the SCL Note: The reason that bus collision is not a fac- pins are monitored. tor during a Start condition is that no two bus masters can assert a Start condition If the SDA pin is already low, or the SCL pin is already at the exact same time. Therefore, one low, then all of the following occur: master will always assert SDA before the • the Start condition is aborted, other. This condition does not cause a bus • the BCL1IF flag is set and collision because the two masters must be • the MSSP1 module is reset to its Idle state allowed to arbitrate the first address fol- (Figure25-33). lowing the Start condition. If the address is The Start condition begins with the SDA and SCL pins the same, arbitration must be allowed to deasserted. When the SDA pin is sampled high, the continue into the data portion, Repeated Baud Rate Generator is loaded and counts down. If the Start or Stop conditions. SCL pin is sampled low while SDA is high, a bus colli- sion occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 25-33: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSP1IF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start SEN cleared automatically because of bus collision. condition if SDA = 1, SCL = 1 SSP1 module reset into Idle state. SEN SDA sampled low before Start condition. Set BCL1IF. S bit and SSP1IF set because BCL1IF SDA = 0, SCL = 1. SSP1IF and BCL1IF are cleared by software S SSP1IF SSP1IF and BCL1IF are cleared by software DS40001441F-page 236  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 25-34: BUS COLLISION DURING START CONDITION (SCL=0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start SCL sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software S ’0’ ’0’ SSP1IF ’0’ ’0’ FIGURE 25-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Set SSP1IF Less than TBRG TBRG SDA SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDA = 1, SCL = 1 BCL1IF ’0’ S SSP1IF SDA = 0, SCL = 1, Interrupts cleared set SSP1IF by software  2011-2015 Microchip Technology Inc. DS40001441F-page 237

PIC12(L)F1840 25.6.13.2 Bus Collision During a Repeated If SDA is low, a bus collision has occurred (i.e., another Start Condition master is attempting to transmit a data ‘0’, Figure25-36). If SDA is sampled high, the BRG is reloaded and begins During a Repeated Start condition, a bus collision counting. If SDA goes from high-to-low before the BRG occurs if: times out, no bus collision occurs because no two a) A low level is sampled on SDA when SCL goes masters can assert SDA at exactly the same time. from low level to high level (Case 1). If SCL goes from high-to-low before the BRG times out b) SCL goes low before SDA is asserted low, and SDA has not already been asserted, a bus collision indicating that another master is attempting to occurs. In this case, another master is attempting to transmit a data ‘1’ (Case 2). transmit a data ‘1’ during the Repeated Start condition, When the user releases SDA and the pin is allowed to see Figure25-37. float high, the BRG is loaded with SSP1ADD and If, at the end of the BRG time-out, both SCL and SDA counts down to zero. The SCL pin is then deasserted are still high, the SDA pin is driven low and the BRG is and when sampled high, the SDA pin is sampled. reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. FIGURE 25-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN BCL1IF Cleared by software S ’0’ SSP1IF ’0’ FIGURE 25-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL SCL goes low before SDA, BCL1IF set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN ’0’ S SSP1IF DS40001441F-page 238  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.6.13.3 Bus Collision During a Stop The Stop condition begins with SDA asserted low. Condition When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), Bus collision occurs during a Stop condition if: the Baud Rate Generator is loaded with SSP1ADD and a) After the SDA pin has been deasserted and counts down to 0. After the BRG times out, SDA is allowed to float high, SDA is sampled low after sampled. If SDA is sampled low, a bus collision has the BRG has timed out (Case 1). occurred. This is due to another master attempting to b) After the SCL pin is deasserted, SCL is sampled drive a data ‘0’ (Figure25-38). If the SCL pin is sampled low before SDA goes high (Case 2). low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure25-39). FIGURE 25-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCL1IF SDA SDA asserted low SCL PEN BCL1IF P ’0’ SSP1IF ’0’ FIGURE 25-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, Assert SDA set BCL1IF SCL PEN BCL1IF P ’0’ SSP1IF ’0’  2011-2015 Microchip Technology Inc. DS40001441F-page 239

PIC12(L)F1840 TABLE 25-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Reset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 73 PIE2 OSFIE — C1IE EEIE BCL1IE — — — 74 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 75 PIR2 OSFIF — C1IF EEIF BCL1IF — — — 76 SSP1ADD ADD<7:0> 246 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 196* SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 243 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 244 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 245 SSP1MSK MSK<7:0> 246 SSP1STAT SMP CKE D/A P S R/W UA BF 242 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode. * Page provides register information. DS40001441F-page 240  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 25.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP1 is The MSSP1 module has a Baud Rate Generator being operated in. available for clock generation in both I2C and SPI Table25-4 demonstrates clock rates based on Master modes. The Baud Rate Generator (BRG) instruction cycles and the BRG value loaded into reload value is placed in the SSP1ADD register SSP1ADD. (Register25-6). When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting EQUATION 25-1: down. Once the given operation is complete, the internal clock FOSC will automatically stop counting and the clock pin will FCLOCK = ------------------------------------------------- SSPxADD+14 remain in its last state. An internal signal “Reload” in Figure25-40 triggers the value from SSP1ADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 25-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSP1M<3:0> SSP1ADD<7:0> SSP1M<3:0> Reload Reload SCL Control SSP1CLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSP1ADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 25-4: MSSP1 CLOCK RATE W/BRG FCLOCK FOSC FCY BRG Value (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note 1: Refer to the I/O port electrical and timing specifications in Table30-4 and Figure30-7 to ensure the system is designed to support the I/O requirements.  2011-2015 Microchip Technology Inc. DS40001441F-page 241

PIC12(L)F1840 25.8 Register Definitions: MSSP Control REGISTER 25-1: SSPSTAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I 2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I 2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I 2 C Slave mode: 1 = Read 0 = Write In I 2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I 2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I 2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty DS40001441F-page 242  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 25-2: SSP1CON1: SSP1 CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WCOL SSP1OV SSP1EN CKP SSP1M<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSP1OV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register (must be cleared in software). 0 = No overflow In I 2 C mode: 1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSP1OV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSP1EN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I 2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I 2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I 2 C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1101 = Reserved 1100 = Reserved 1011 = I2C firmware controlled Master mode (slave idle) 1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5) 1001 = Reserved 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register. 2: When enabled, these pins must be properly configured as input or output. 3: When enabled, the SDA and SCL pins must be configured as inputs. 4: SSP1ADD values of 0, 1 or 2 are not supported for I2C mode. 5: SSP1ADD value of ‘0’ is not supported. Use SSP1M = 0000 instead.  2011-2015 Microchip Technology Inc. DS40001441F-page 243

PIC12(L)F1840 REGISTER 25-3: SSP1CON2: SSP1 CONTROL REGISTER 2 R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled). DS40001441F-page 244  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 25-4: SSP1CON3: SSP1 CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSP1STAT register already set, SSP1OV bit of the SSP1CON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSP1OV bit only if the BF bit = 0. 0 = SSP1BUF is only updated when SSP1OV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSP1CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSP1CON1 register and SCL is held low. 0 = Data holding is disabled Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSP1OV is still set when a new byte is received and BF=1, but hardware continues to write the most recent byte to SSP1BUF. 2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. 3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.  2011-2015 Microchip Technology Inc. DS40001441F-page 245

PIC12(L)F1840 REGISTER 25-5: SSP1MSK: SSP1 MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSP1ADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSP1M<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 25-6: SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care.” 10-Bit Slave mode — Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care.” DS40001441F-page 246  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer • Half-duplex synchronous master independent of device program execution. The • Half-duplex synchronous slave EUSART, also known as a Serial Communications • Programmable clock polarity in synchronous Interface (SCI), can be configured as a full-duplex modes asynchronous system or half-duplex synchronous • Sleep operation system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT The EUSART module implements the following terminals and personal computers. Half-Duplex additional features, making it ideally suited for use in Synchronous mode is intended for communications Local Interconnect Network (LIN) bus systems: with peripheral devices, such as A/D or D/A integrated • Automatic detection and calibration of the baud rate circuits, serial EEPROMs or other microcontrollers. • Wake-up on Break reception These devices typically do not have internal clocks for • 13-bit Break character transmit baud rate generation and require the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure26-1 and Figure26-2. FIGURE 26-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXREG Register TXIF 8 MSb LSb TX/CK pin (8) • • • 0 Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT SPEN Baud Rate Generator FOSC ÷ n TX9 BRG16 n + 1 Multiplier x4 x16 x64 TX9D SYNC 1 X 0 0 0 SPBRGH SPBRGL BRGH X 1 1 0 0 BRG16 X 1 0 1 0  2011-2015 Microchip Technology Inc. DS40001441F-page 247

PIC12(L)F1840 FIGURE 26-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN OERR RCIDL RX/DT pin MSb RSR Register LSb Panind BCuoffnetrrol DRaetcaovery Stop (8) 7 • • • 1 0 START Baud Rate Generator FOSC RX9 ÷ n BRG16 n + 1 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 FIFO SPBRGH SPBRGL BRGH X 1 1 0 0 FERR RX9D RCREG Register BRG16 X 1 0 1 0 8 Data Bus RCIF Interrupt RCIE The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register26-1, Register26-2 and Register26-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output. DS40001441F-page 248  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.1 EUSART Asynchronous Mode 26.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard non-return-to-zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the implemented with two levels: a VOH mark state which previous character has been completely flushed from represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXREG is immediately represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains consecutively transmitted data bits of the same value all or part of a previous character, the new character stay at the output level of that bit without returning to a data is held in the TXREG until the Stop bit of the neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending transmission port idles in the Mark state. Each character character in the TXREG is then transferred to the TSR transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits or nine data bits and is always terminated by one or and Stop bit sequence commences immediately more Stop bits. The Start bit is always a space and the following the transfer of the data to the TSR from the Stop bits are always marks. The most common data TXREG. format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 26.1.1.3 Transmit Data Polarity 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system The polarity of the transmit data can be controlled with oscillator. See Table26-5 for examples of baud rate the SCKP bit of the BAUDCON register. The default configurations. state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the The EUSART transmits and receives the LSb first. The transmit data resulting in low true idle and data bits. The EUSART’s transmitter and receiver are functionally SCKP bit controls transmit data polarity in independent, but share the same data format and baud Asynchronous mode only. In Synchronous mode, the rate. Parity is not supported by the hardware, but can SCKP bit has a different function. See Section26.5.1.2 be implemented in software and stored as the ninth “Clock Polarity”. data bit. 26.1.1.4 Transmit Interrupt Flag 26.1.1 EUSART ASYNCHRONOUS TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no The EUSART transmitter block diagram is shown in character is being held for transmission in the TXREG. Figure26-1. The heart of the transmitter is the serial In other words, the TXIF bit is only clear when the TSR Transmit Shift Register (TSR), which is not directly is busy with a character and a new character has been accessible by software. The TSR obtains its data from queued for transmission in the TXREG. The TXIF flag bit the transmit buffer, which is the TXREG register. is not cleared immediately upon writing TXREG. TXIF 26.1.1.1 Enabling the Transmitter becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following The EUSART transmitter is enabled for asynchronous the TXREG write will return invalid results. The TXIF bit operations by configuring the following three control is read-only, it cannot be set or cleared by software. bits: The TXIF interrupt can be enabled by setting the TXIE • TXEN = 1 interrupt enable bit of the PIE1 register. However, the • SYNC = 0 TXIF flag bit will be set whenever the TXREG is empty, • SPEN = 1 regardless of the state of TXIE enable bit. All other EUSART control bits are assumed to be in To use interrupts when transmitting data, set the TXIE their default state. bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character Setting the TXEN bit of the TXSTA register enables the of the transmission to the TXREG. transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set.  2011-2015 Microchip Technology Inc. DS40001441F-page 249

PIC12(L)F1840 26.1.1.5 TSR Status 26.1.1.7 Asynchronous Transmission Set-up: The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH, SPBRGL register pair and status of the TSR register. This is a read-only bit. The the BRGH and BRG16 bits to achieve the desired TRMT bit is set when the TSR register is empty and is baud rate (see Section26.4 “EUSART Baud cleared when a character is transferred to the TSR Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 poll this bit to determine the TSR status. control bit. A set ninth data bit will indicate that Note: The TSR register is not mapped in data the eight Least Significant data bits are an memory, so it is not available to the user. address when the receiver is set for address detection. 26.1.1.6 Transmitting 9-Bit Characters 4. Set SCKP bit if inverted transmit is desired. The EUSART supports 9-bit character transmissions. 5. Enable the transmission by setting the TXEN When the TX9 bit of the TXSTA register is set, the control bit. This will cause the TXIF interrupt bit EUSART will shift nine bits out for each character to be set. transmitted. The TX9D bit of the TXSTA register is the 6. If interrupts are desired, set the TXIE interrupt ninth, and Most Significant, data bit. When transmitting enable bit of the PIE1 register. An interrupt will 9-bit data, the TX9D data bit must be written before occur immediately provided that the GIE and writing the eight Least Significant bits into the TXREG. PEIE bits of the INTCON register are also set. All nine bits of data will be transferred to the TSR shift 7. If 9-bit transmission is selected, the ninth bit register immediately after the TXREG is written. should be loaded into the TX9D data bit. A special 9-bit Address mode is available for use with 8. Load 8-bit data into the TXREG register. This multiple receivers. See Section26.1.2.7 “Address will start the transmission. Detection” for more information on the address mode. FIGURE 26-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer 1 TCY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg. (Transmit Shift Reg. Empty Flag) DS40001441F-page 250  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 26-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 Word 2 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 TXIF bit 1 TCY Word 1 Word 2 (Transmit Buffer Reg. Empty Flag) 1 TCY TRMT bit Word 1 Word 2 (Transmit Shift Transmit Shift Reg. Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 259 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 258 SPBRGL BRG<7:0> 260* SPBRGH BRG<15:8> 260* TXREG EUSART Transmit Data Register 249* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 257 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission. * Page provides register information.  2011-2015 Microchip Technology Inc. DS40001441F-page 251

PIC12(L)F1840 26.1.2 EUSART ASYNCHRONOUS 26.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure26-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts the baud rate, whereas the serial Receive Shift character reception, without generating an error, and Register (RSR) operates at the bit rate. When all eight resumes looking for the falling edge of the Start bit. If or nine bits of the character have been shifted in, they the Start bit zero verification succeeds then the data are immediately transferred to a two character recovery circuit counts a full bit time to the center of the First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. start of a third character before software must start This repeats until all data bits have been sampled and servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always Access to the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this 26.1.2.1 Enabling the Receiver character, otherwise the framing error is cleared for this character. See Section26.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no additional receiver circuitry of the EUSART. Clearing the SYNC bit characters will be received until the overrun of the TXSTA register configures the EUSART for condition is cleared. See Section26.1.2.5 asynchronous operation. Setting the SPEN bit of the “Receive Overrun Error” for more RCSTA register enables the EUSART. The programmer information on overrun errors. must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. 26.1.2.3 Receive Interrupts Note1: If the RX/DT function is on an analog pin, The RCIF interrupt flag bit of the PIR1 register is set the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is cleared for the receiver to function. an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE, Interrupt Enable bit of the PIE1 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS40001441F-page 252  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.1.2.4 Receive Framing Error 26.1.2.7 Address Detection Each character in the receive FIFO buffer has a A special Address Detection mode is available for use corresponding framing error Status bit. A framing error when multiple receivers share the same transmission indicates that a Stop bit was not seen at the expected line, such as in RS-485 systems. Address detection is time. The framing error status is accessed via the enabled by setting the ADDEN bit of the RCSTA FERR bit of the RCSTA register. The FERR bit register. represents the status of the top unread character in the Address detection requires 9-bit character reception. receive FIFO. Therefore, the FERR bit must be read When address detection is enabled, only characters before reading the RCREG. with the ninth data bit set will be transferred to the The FERR bit is read-only and only applies to the top receive FIFO buffer, thereby setting the RCIF interrupt unread character in the receive FIFO. A framing error bit. All other characters will be ignored. (FERR = 1) does not preclude reception of additional Upon receiving an address character, user software characters. It is not necessary to clear the FERR bit. determines if the address matches its own. Upon Reading the next character from the FIFO buffer will address match, user software must disable address advance the FIFO to the next character and the next detection by clearing the ADDEN bit before the next corresponding framing error. Stop bit occurs. When user software detects the end of The FERR bit can be forced clear by clearing the SPEN the message, determined by the message protocol bit of the RCSTA register which resets the EUSART. used, software places the receiver back into the Clearing the CREN bit of the RCSTA register does not Address Detection mode by setting the ADDEN bit. affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. 26.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 26.1.2.6 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG.  2011-2015 Microchip Technology Inc. DS40001441F-page 253

PIC12(L)F1840 26.1.2.8 Asynchronous Reception Set-up: 26.1.2.9 9-bit Address Detection Mode Set-up 1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section26.4 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH, SPBRGL register pair 2. Clear the ANSEL bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section26.4 “EUSART The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”). operation. 2. Clear the ANSEL bit for the RX pin (if applicable). 4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit. PIE1 register and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the 6. Enable reception by setting the CREN bit. PIE1 register and the GIE and PEIE bits of the 7. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 26-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg Rcv Buffer Reg. Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS40001441F-page 254  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 26-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 259 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 RCREG EUSART Receive Data Register 252* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 258 SPBRGL BRG<7:0> 260* SPBRGH BRG<15:8> 260* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 257 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Reception. * Page provides register information.  2011-2015 Microchip Technology Inc. DS40001441F-page 255

PIC12(L)F1840 26.2 Clock Accuracy with The first (preferred) method uses the OSCTUNE Asynchronous Operation register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution The factory calibrates the internal oscillator block changes to the system clock source. See Section5.2.2 output (INTOSC). However, the INTOSC frequency “Internal Clock Sources” for more information. may drift as VDD or temperature changes, and this The other method adjusts the value in the Baud Rate directly affects the asynchronous baud rate. Two Generator. This can be done automatically with the methods may be used to adjust the baud rate clock, but Auto-Baud Detect feature (see Section26.4.1 both require a reference clock source of some kind. “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. DS40001441F-page 256  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.3 Register Definitions: EUSART Control REGISTER 26-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode.  2011-2015 Microchip Technology Inc. DS40001441F-page 257

PIC12(L)F1840 REGISTER 26-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-x/x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001441F-page 258  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 26-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care  2011-2015 Microchip Technology Inc. DS40001441F-page 259

PIC12(L)F1840 26.4 EUSART Baud Rate Generator EXAMPLE 26-1: CALCULATING BAUD (BRG) RATE ERROR The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. FOSC Desired Baud Rate = ------------------------------------------------------------------------ By default, the BRG operates in 8-bit mode. Setting the 64[SPBRGH:SPBRGL]+1 BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL: mode. FOSC The SPBRGH, SPBRGL register pair determines the --------------------------------------------- Desired Baud Rate period of the free running baud rate timer. In X = ---------------------------------------------–1 64 Asynchronous mode the multiplier of the baud rate 16000000 period is determined by both the BRGH bit of the TXSTA ------------------------ 9600 register and the BRG16 bit of the BAUDCON register. In = ------------------------–1 64 Synchronous mode, the BRGH bit is ignored. = 25.042 = 25 Table26-3 contains the formulas for determining the baud rate. Example26-1 provides a sample calculation 16000000 Calculated Baud Rate = --------------------------- for determining the baud rate and baud rate error. 6425+1 Typical baud rates and error values for various = 9615 asynchronous modes have been computed for your convenience and are shown in Table26-3. It may be Calc. Baud Rate–Desired Baud Rate Error = -------------------------------------------------------------------------------------------- advantageous to use the high baud rate (BRGH = 1), Desired Baud Rate or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 9615–9600 error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16% 9600 baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. DS40001441F-page 260  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 26-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care, n = value of SPBRGH, SPBRGL register pair. TABLE 26-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 259 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 258 SPBRGL BRG<7:0> 260* SPBRGH BRG<15:8> 260* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 257 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information.  2011-2015 Microchip Technology Inc. DS40001441F-page 261

PIC12(L)F1840 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 DS40001441F-page 262  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — —  2011-2015 Microchip Technology Inc. DS40001441F-page 263

PIC12(L)F1840 TABLE 26-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % value value value value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — DS40001441F-page 264  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.4.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the auto-baud detection will occur on the byte BRG is reversed. Rather than the BRG clocking the following the Break character (see incoming RX signal, the RX signal is timing the BRG. Section26.4 “EUSART Baud Rate The Baud Rate Generator is used to time the period of Generator (BRG)”). a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCON register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure26-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1. counting up using the BRG counter clock as shown in Upon completion of the auto-baud Table26-6. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy, at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL accumulated value totaling the proper BRG period is register pair. left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag TABLE 26-6: BRG COUNTER CLOCK RATES is set. The value in the RCREG needs to be read to BRG Base BRG ABD clear the RCIF interrupt. RCREG content should be BRG16 BRGH Clock Clock discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the 0 0 FOSC/64 FOSC/512 SPBRGL register did not overflow by checking for 00h 0 1 FOSC/16 FOSC/128 in the SPBRGH register. 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table26-6. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, SPBRGL and a 16-bit counter, independent of the BRG16 bit setting. SPBRGH registers are both used as a 16-bit While calibrating the baud rate period, the SPBRGH counter, independent of BRG16 setting. FIGURE 26-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2011-2015 Microchip Technology Inc. DS40001441F-page 265

PIC12(L)F1840 26.4.2 AUTO-BAUD OVERFLOW 26.4.3.1 Special Considerations During the course of automatic baud detection, the Break Character ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register When the wake-up is enabled the function works pair. After the ABDOVF bit has been set, the counter independent of the low time on the data stream. If the continues to count until the fifth rising edge is detected WUE bit is set and a valid non-zero character is on the RX pin. Upon detecting the fifth RX edge, the received, the low time from the Start bit to the first rising hardware will set the RCIF interrupt flag and clear the edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a ABDEN bit of the BAUDCON register. The RCIF flag can be subsequently cleared by reading the RCREG fragmented character and subsequent characters can register. The ABDOVF flag of the BAUDCON register result in framing or overrun errors. can be cleared by software directly. Therefore, the initial character in the transmission must To terminate the auto-baud process before the RCIF be all ‘0’s. This must be ten or more bit times, 13-bit flag is set, clear the ABDEN bit then clear the ABDOVF times recommended for LIN bus, or any number of bit bit of the BAUDCON register. The ABDOVF bit will times for standard RS-232 devices. remain set if the ABDEN bit is not cleared first. Oscillator Start-up Time Oscillator start-up time must be considered, especially 26.4.3 AUTO-WAKE-UP ON BREAK in applications using oscillators with longer start-up During Sleep mode, all clocks to the EUSART are intervals (i.e., LP, XT or HS/PLL mode). The Sync suspended. Because of this, the Baud Rate Generator Break (or wake-up signal) character must be of is inactive and a proper character reception cannot be sufficient length, and be followed by a sufficient performed. The Auto-Wake-up feature allows the interval, to allow enough time for the selected oscillator controller to wake-up due to activity on the RX/DT line. to start and provide proper initialization of the EUSART. This feature is available only in Asynchronous mode. WUE Bit The Auto-Wake-up feature is enabled by setting the The wake-up event causes a receive interrupt by WUE bit of the BAUDCON register. Once set, the normal setting the RCIF bit. The WUE bit is cleared in receive sequence on RX/DT is disabled, and the hardware by a rising edge on RX/DT. The interrupt EUSART remains in an Idle state, monitoring for a condition is then cleared in software by reading the wake-up event independent of the CPU mode. A RCREG register and discarding its contents. wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break To ensure that no actual data is lost, check the RCIDL or a wake-up signal character for the LIN protocol.) bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not The EUSART module generates an RCIF interrupt occurring, the WUE bit may then be set just prior to coincident with the wake-up event. The interrupt is entering the Sleep mode. generated synchronously to the Q clocks in normal CPU operating modes (Figure26-7), and asynchronously if the device is in Sleep mode (Figure26-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS40001441F-page 266  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 26-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit set by user Auto Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 26-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set.  2011-2015 Microchip Technology Inc. DS40001441F-page 267

PIC12(L)F1840 26.4.4 BREAK CHARACTER SEQUENCE 26.4.5 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced EUSART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by 12 ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the Received data To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is bits of the TXSTA register. The Break character assumed to have been initialized to the expected baud transmission is then initiated by a write to the TXREG. rate. The value of data written to TXREG will be ignored and A Break character has been received when; all ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte • RCREG = 00h following the Break character (typically, the Sync The second method uses the Auto-Wake-up feature character in the LIN specification). described in Section26.4.3 “Auto-Wake-up on The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an transmit operation is active or idle, just as it does during RCIF interrupt, and receive the next data byte followed normal transmission. See Figure26-9 for the timing of by another interrupt. the Break character sequence. Note that following a Break character, the user will 26.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus Sleep mode. master. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 26-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit) DS40001441F-page 268  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.5 EUSART Synchronous Mode Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising Synchronous serial communications are typically used edge of each clock. in systems with a single master and one or more slaves. The master device contains the necessary cir- 26.5.1.3 Synchronous Master Transmission cuitry for baud rate generation and supplies the clock Data is transferred out of the device on the RX/DT pin. for all devices in the system. Slave devices can take The RX/DT and TX/CK pin output drivers are advantage of the master clock by eliminating the inter- automatically enabled when the EUSART is configured nal clock generation circuitry. for synchronous master transmit operation. There are two signal lines in Synchronous mode: a A transmission is initiated by writing a character to the bidirectional data line and a clock line. Slaves use the TXREG register. If the TSR still contains all or part of a external clock supplied by the master to shift the serial previous character the new character data is held in the data into and out of their respective receive and TXREG until the last bit of the previous character has transmit shift registers. Since the data line is been transmitted. If this is the first character, or the bidirectional, synchronous operation is half-duplex previous character has been completely flushed from only. Half-duplex refers to the fact that master and the TSR, the data in the TXREG is immediately slave devices can receive and transmit data but not transferred to the TSR. The transmission of the both simultaneously. The EUSART can operate as character commences immediately following the either a master or slave device. transfer of the data to the TSR from the TXREG. Start and Stop bits are not used in synchronous Each data bit changes on the leading edge of the transmissions. master clock and remains valid until the subsequent leading clock edge. 26.5.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART Note: The TSR register is not mapped in data for synchronous master operation: memory, so it is not available to the user. • SYNC = 1 26.5.1.4 Synchronous Master Transmission • CSRC = 1 Set-up: • SREN = 0 (for transmit); SREN = 1 (for receive) 1. Initialize the SPBRGH, SPBRGL register pair • CREN = 0 (for transmit); CREN = 1 (for receive) and the BRGH and BRG16 bits to achieve the • SPEN = 1 desired baud rate (see Section26.4 “EUSART Baud Rate Generator (BRG)”). Setting the SYNC bit of the TXSTA register configures 2. Enable the synchronous master serial port by the device for synchronous operation. Setting the CSRC setting bits SYNC, SPEN and CSRC. bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA 3. Disable Receive mode by clearing bits SREN register ensures that the device is in the Transmit mode, and CREN. otherwise the device will be configured to receive. Setting 4. Enable Transmit mode by setting the TXEN bit. the SPEN bit of the RCSTA register enables the 5. If 9-bit transmission is desired, set the TX9 bit. EUSART. 6. If interrupts are desired, set the TXIE bit of the 26.5.1.1 Master Clock PIE1 register and the GIE and PEIE bits of the INTCON register. Synchronous data transfers use a separate clock line, 7. If 9-bit transmission is selected, the ninth bit which is synchronous with the data. A device should be loaded in the TX9D bit. configured as a master transmits the clock on the 8. Start transmission by loading data to the TXREG TX/CK line. The TX/CK pin output driver is register. automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. 26.5.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock.  2011-2015 Microchip Technology Inc. DS40001441F-page 269

PIC12(L)F1840 FIGURE 26-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 26-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 26-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 259 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 258 SPBRGL BRG<7:0> 260* SPBRGH BRG<15:8> 260* TXREG EUSART Transmit Data Register 249* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 257 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission. * Page provides register information. DS40001441F-page 270  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.5.1.5 Synchronous Master Reception buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit Data is received at the RX/DT pin. The RX/DT pin can only be cleared by clearing the overrun condition. output driver is automatically disabled when the If the overrun error occurred when the SREN bit is set EUSART is configured for synchronous master receive and CREN is clear then the error is cleared by reading operation. RCREG. If the overrun occurred when the CREN bit is In Synchronous mode, reception is enabled by setting set then the error condition is cleared by either clearing either the Single Receive Enable bit (SREN of the the CREN bit of the RCSTA register or by clearing the RCSTA register) or the Continuous Receive Enable bit SPEN bit which resets the EUSART. (CREN of the RCSTA register). 26.5.1.8 Receiving 9-bit Characters When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a The EUSART supports 9-bit character reception. When single character. The SREN bit is automatically cleared the RX9 bit of the RCSTA register is set the EUSART at the completion of one character. When CREN is set, will shift 9-bits into the RSR for each character clocks are continuously generated until CREN is received. The RX9D bit of the RCSTA register is the cleared. If CREN is cleared in the middle of a character ninth, and Most Significant, data bit of the top unread the CK clock stops immediately and the partial charac- character in the receive FIFO. When reading 9-bit data ter is discarded. If SREN and CREN are both set, then from the receive FIFO buffer, the RX9D data bit must SREN is cleared at the completion of the first character be read before reading the eight Least Significant bits and CREN takes precedence. from the RCREG. To initiate reception, set either SREN or CREN. Data is 26.5.1.9 Synchronous Master Reception sampled at the RX/DT pin on the trailing edge of the Set-up: TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is 1. Initialize the SPBRGH, SPBRGL register pair for received into the RSR, the RCIF bit is set and the char- the appropriate baud rate. Set or clear the acter is automatically transferred to the two character BRGH and BRG16 bits, as required, to achieve receive FIFO. The Least Significant eight bits of the top the desired baud rate. character in the receive FIFO are available in RCREG. 2. Clear the ANSEL bit for the RX pin (if applicable). The RCIF bit remains set as long as there are unread 3. Enable the synchronous master serial port by characters in the receive FIFO. setting bits SYNC, SPEN and CSRC. Note: If the RX/DT function is on an analog pin, 4. Ensure bits CREN and SREN are clear. the corresponding ANSEL bit must be 5. If interrupts are desired, set the RCIE bit of the cleared for the receiver to function. PIE1 register and the GIE and PEIE bits of the INTCON register. 26.5.1.6 Slave Clock 6. If 9-bit reception is desired, set bit RX9. Synchronous data transfers use a separate clock line, 7. Start reception by setting the SREN bit or for which is synchronous with the data. A device configured continuous reception, set the CREN bit. as a slave receives the clock on the TX/CK line. The 8. Interrupt flag bit RCIF will be set when reception TX/CK pin output driver is automatically disabled when of a character is complete. An interrupt will be the device is configured for synchronous slave transmit generated if the enable bit RCIE was set. or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge 9. Read the RCSTA register to get the ninth bit (if of each clock. One data bit is transferred for each clock enabled) and determine if any error occurred cycle. Only as many clock cycles should be received as during reception. there are data bits. 10. Read the 8-bit received data by reading the RCREG register. Note: If the device is configured as a slave and 11. If an overrun error occurs, clear the error by the TX/CK function is on an analog pin, the either clearing the CREN bit of the RCSTA corresponding ANSEL bit must be register or by clearing the SPEN bit which resets cleared. the EUSART. 26.5.1.7 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO  2011-2015 Microchip Technology Inc. DS40001441F-page 271

PIC12(L)F1840 FIGURE 26-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 26-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 259 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 RCREG EUSART Receive Data Register 252* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 258 SPBRGL BRG<7:0> 260* SPBRGH BRG<15:8> 260* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 257 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception. * Page provides register information. DS40001441F-page 272  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in TXREG register. • CSRC = 0 3. The TXIF bit will not be set. • SREN = 0 (for transmit); SREN = 1 (for receive) 4. After the first character has been shifted out of • CREN = 0 (for transmit); CREN = 1 (for receive) TSR, the TXREG register will transfer the second • SPEN = 1 character to the TSR and the TXIF bit will now be Setting the SYNC bit of the TXSTA register configures the set. device for synchronous operation. Clearing the CSRC bit 5. If the PEIE and TXIE bits are set, the interrupt of the TXSTA register configures the device as a slave. will wake the device from Sleep and execute the Clearing the SREN and CREN bits of the RCSTA register next instruction. If the GIE bit is also set, the ensures that the device is in the Transmit mode, program will call the Interrupt Service Routine. otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the 26.5.2.2 Synchronous Slave Transmission EUSART. Set-up: 26.5.2.1 EUSART Synchronous Slave 1. Set the SYNC and SPEN bits and clear the CSRC bit. Transmit 2. Clear the ANSEL bit for the CK pin (if applicable). The operation of the Synchronous Master and Slave 3. Clear the CREN and SREN bits. modes are identical (see Section26.5.1.3 “Synchronous Master Transmission”), except in the 4. If interrupts are desired, set the TXIE bit of the case of the Sleep mode. PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant eight bits to the TXREG register. TABLE 26-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 259 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 258 TXREG EUSART Transmit Data Register 249* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 257 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. * Page provides register information.  2011-2015 Microchip Technology Inc. DS40001441F-page 273

PIC12(L)F1840 26.5.2.3 EUSART Synchronous Slave 26.5.2.4 Synchronous Slave Reception Reception Set-up: The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the modes is identical (Section26.5.1.5 “Synchronous CSRC bit. Master Reception”), with the following exceptions: 2. Clear the ANSEL bit for both the CK and DT pins • Sleep (if applicable). • CREN bit is always set, therefore the receiver is 3. If interrupts are desired, set the RCIE bit of the never idle PIE1 register and the GIE and PEIE bits of the INTCON register. • SREN bit, which is a “don’t care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. A character may be received while in Sleep mode by 5. Set the CREN bit to enable reception. setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data 6. The RCIF bit will be set when reception is to the RCREG register. If the RCIE enable bit is set, the complete. An interrupt will be generated if the interrupt generated will wake the device from Sleep RCIE bit was set. and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCSTA register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 26-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 259 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 75 RCREG EUSART Receive Data Register 252* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 258 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 257 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. * Page provides register information. DS40001441F-page 274  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 26.6 EUSART Operation During Sleep 26.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the To transmit during Sleep, all the following conditions system clock and therefore cannot generate the must be met before entering Sleep mode: necessary signals to run the Transmit or Receive Shift • RCSTA and TXSTA Control registers must be registers during Sleep. configured for synchronous slave transmission Synchronous Slave mode uses an externally generated (see Section26.5.2.2 “Synchronous Slave clock to run the Transmit and Receive Shift registers. Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing 26.6.1 SYNCHRONOUS RECEIVE DURING the output data to the TXREG, thereby filling the SLEEP TSR and transmit buffer. To receive during Sleep, all the following conditions • If interrupts are desired, set the TXIE bit of the must be met before entering Sleep mode: PIE1 register and the PEIE bit of the INTCON reg- ister. • RCSTA and TXSTA Control registers must be • Interrupt enable bits TXIE of the PIE1 register and configured for Synchronous Slave Reception (see PEIE of the INTCON register must set. Section26.5.2.4 “Synchronous Slave Reception Set-up:”). Upon entering Sleep mode, the device will be ready to • If interrupts are desired, set the RCIE bit of the accept clocks on TX/CK pin and transmit data on the PIE1 register and the GIE and PEIE bits of the RX/DT pin. When the data word in the TSR has been INTCON register. completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and • The RCIF interrupt flag must be cleared by read- the TXIF flag will be set. Thereby, waking the processor ing RCREG to unload any pending characters in from Sleep. At this point, the TXREG is available to the receive buffer. accept another character for transmission, which will Upon entering Sleep mode, the device will be ready to clear the TXIF flag. accept data and clocks on the RX/DT and TX/CK pins, Upon waking from Sleep, the instruction following the respectively. When the data word has been completely SLEEP instruction will be executed. If the Global clocked in by the external device, the RCIF interrupt Interrupt Enable (GIE) bit is also set then the Interrupt flag bit of the PIR1 register will be set. Thereby, waking Service Routine at address 0004h will be called. the processor from Sleep. Upon waking from Sleep, the instruction following the 26.6.3 ALTERNATE PIN LOCATIONS SLEEP instruction will be executed. If the Global Inter- This module incorporates I/O pins that can be moved to rupt Enable (GIE) bit of the INTCON register is also set, other locations with the use of the alternate pin function then the Interrupt Service Routine at address 004h will register, APFCON. To determine which pins can be be called. moved and what their default locations are upon a Reset, see Section12.1 “Alternate Pin Function” for more information.  2011-2015 Microchip Technology Inc. DS40001441F-page 275

PIC12(L)F1840 27.0 CAPACITIVE SENSING (CPS) MODULE The Capacitive Sensing (CPS) module allows for an interaction with an end user without a mechanical interface. In a typical application, the CPS module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the CPS module. The CPS module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: • Analog MUX for monitoring multiple inputs • Capacitive sensing oscillator • Multiple current ranges • Multiple voltage reference modes • Multiple timer resources • Software control • Operation during Sleep FIGURE 27-1: CAPACITIVE SENSING BLOCK DIAGRAM Timer0 Module Set TMR0CS T0XCS TMR0IF FOSC/4 0 Overflow T0CKI 0 TMR0 1 CPSCH<3:0> 1 CPSON(1) CPSRNG<1:0> CPSON Capacitive Sensing Timer1 Module Oscillator T1CS<1:0> CPSOSC CPS0 FOSC CPS1 CPSCLK FOSC/4 CPS2 Ref- 0 DAC_output RInetf.. T1OSC/ EN TMR1H:TMR1L CPS3 1 CPSOUT T1CKI 0 T1GSEL<1:0> Ref+ FVR T1G 1 Buffer2 Timer1 Gate Control Logic sync_C1OUT CPSRM Note 1: If CPSON=0, disabling capacitive sensing, no channel is selected. DS40001441F-page 276  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 27-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) (2) + - S Q CPSCLK CPSx Analog Pin (1) (2) R - + Internal References 0 0 Ref- Ref+ 1 DAC_output 1 FVR Buffer2 CPSRM Note 1: Module Enable and Current mode selections are not shown. 2: Comparators remain active in Noise Detection mode.  2011-2015 Microchip Technology Inc. DS40001441F-page 277

PIC12(L)F1840 27.1 Analog MUX 27.3 Voltage References The CPS module can monitor up to four inputs. See The capacitive sensing oscillator uses voltage Register27-2 for details. To determine if a frequency references to provide two voltage thresholds for change has occurred the user must: oscillation. The upper voltage threshold is referred to as Ref+ and the lower voltage threshold is referred to • Select the appropriate CPS pin by setting the as Ref-. appropriate CPSCH bits of the CPSCON1 register. • Set the corresponding ANSEL bit. The user can elect to use Fixed Voltage References, which are internal to the capacitive sensing oscillator, • Set the corresponding TRIS bit. or variable voltage references, which are supplied by • Run the software algorithm. the Fixed Voltage Reference (FVR) module and the Selection of the CPSx pin while the module is enabled Digital-to-Analog Converter (DAC) module. will cause the capacitive sensing oscillator to be on the When the Fixed Voltage References are used, the VSS CPSx pin. Failure to set the corresponding ANSEL and voltage determines the lower threshold level (Ref-) and TRIS bits can cause the capacitive sensing oscillator to the VDD voltage determines the upper threshold level stop, leading to false frequency readings. (Ref+). 27.2 Capacitive Sensing Oscillator When the variable voltage references are used, the DAC voltage determines the lower threshold level The capacitive sensing oscillator consists of a constant (Ref-) and the FVR voltage determines the upper current source and a constant current sink, to produce threshold level (Ref+). An advantage of using these a triangle waveform. The CPSOUT bit of the reference sources is that oscillation frequency remains CPSCON0 register shows the status of the capacitive constant with changes in VDD. sensing oscillator, whether it is a sinking or sourcing Different oscillation frequencies can be obtained current. The oscillator is designed to drive a capacitive through the use of these variable voltage references. load (single PCB pad) and at the same time, be a clock The more the upper voltage reference level is lowered source to either Timer0 or Timer1. The oscillator has and the more the lower voltage reference level is several different current settings as defined by CPS- raised, the higher the capacitive sensing oscillator RNG<1:0> of the CPSCON0 register. The different cur- frequency becomes. rent settings for the oscillator serve two purposes: Selection between the voltage references is controlled • Maximize the number of counts in a timer for a by the CPSRM bit of the CPSCON0 register. Setting fixed time base. this bit selects the variable voltage references and • Maximize the count differential in the timer during clearing this bit selects the Fixed Voltage References. a change in frequency. Please see Section14.0 “Fixed Voltage Reference (FVR)” and Section17.0 “Digital-to-Analog Converter (DAC) Module” for more information on configuring the variable voltage levels. DS40001441F-page 278  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 27.4 Current Ranges The remaining mode is a Noise Detection mode that resides within the high range. The Noise Detection The capacitive sensing oscillator can operate in one of mode is unique in that it disables the sinking and seven different power modes. The power modes are sourcing of current on the analog pin but leaves the rest separated into two ranges; the low range and the high of the oscillator circuitry active. This reduces the range. oscillation frequency on the analog pin to zero and also When the oscillator’s low range is selected, the fixed greatly reduces the current consumed by the oscillator internal voltage references of the capacitive sensing module. oscillator are being used. When the oscillator’s high When noise is introduced onto the pin, the oscillator is range is selected, the variable voltage references driven at the frequency determined by the noise. This supplied by the FVR and DAC modules are being used. produces a detectable signal at the comparator output, Selection between the voltage references is controlled indicating the presence of activity on the pin. by the CPSRM bit of the CPSCON0 register. See Figure27-2 shows a more detailed drawing of the Section27.3 “Voltage References” for more current sources and comparators associated with the information. oscillator. Within each range there are three distinct Power modes; low, medium and high. Current consumption is dependent upon the range and mode selected. Selecting Power modes within each range is accomplished by configuring the CPSRNG <1:0> bits in the CPSCON0 register. See Table27-1 for proper Power mode selection. TABLE 27-1: CURRENT RANGE MODE SELECTION CPSRM Range CPSRNG<1:0> Current Range(1) 00 Noise Detection 01 Low 1 Variable 10 Medium 11 High 00 Off 01 Low 0 Fixed 10 Medium 11 High Note 1: See Power-Down Currents (IPD) in Section30.0 “Electrical Specifications” for more information.  2011-2015 Microchip Technology Inc. DS40001441F-page 279

PIC12(L)F1840 27.5 Timer Resources 27.7 Software Control To measure the change in frequency of the capacitive The software portion of the CPS module is required to sensing oscillator, a fixed time base is required. For the determine the change in frequency of the capacitive period of the fixed time base, the capacitive sensing sensing oscillator. This is accomplished by the oscillator is used to clock either Timer0 or Timer1. The following: frequency of the capacitive sensing oscillator is equal • Setting a fixed time base to acquire counts on to the number of counts in the timer divided by the Timer0 or Timer1. period of the fixed time base. • Establishing the nominal frequency for the capacitive sensing oscillator. 27.6 Fixed Time Base • Establishing the reduced frequency for the capac- To measure the frequency of the capacitive sensing itive sensing oscillator due to an additional capac- oscillator, a fixed time base is required. Any timer itive load. resource or software loop can be used to establish the • Set the frequency threshold. fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. 27.7.1 NOMINAL FREQUENCY (NO CAPACITIVE LOAD) Note: The fixed time base can not be generated by the timer resource that the capacitive To determine the nominal frequency of the capacitive sensing oscillator is clocking. sensing oscillator: • Remove any extra capacitive load on the selected 27.6.1 TIMER0 CPSx pin. To select Timer0 as the timer resource for the CPS • At the start of the fixed time base, clear the timer module: resource. • Set the T0XCS bit of the CPSCON0 register. • At the end of the fixed time base save the value in the timer resource. • Clear the TMR0CS bit of the OPTION_REG register. The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the When Timer0 is chosen as the timer resource, the given time base. The frequency of the capacitive capacitive sensing oscillator will be the clock source for sensing oscillator is equal to the number of counts on Timer0. Refer to Section20.0 “Timer0 Module” for in the timer, divided by the period of the fixed time base. additional information. 27.7.2 REDUCED FREQUENCY 27.6.2 TIMER1 (ADDITIONAL CAPACITIVE LOAD) To select Timer1 as the timer resource for the CPS The extra capacitive load will cause the frequency of the module, set the TMR1CS<1:0> of the T1CON register to ‘11’. When Timer1 is chosen as the timer resource, capacitive sensing oscillator to decrease. To determine the capacitive sensing oscillator will be the clock the reduced frequency of the capacitive sensing source for Timer1. Because the Timer1 module has a oscillator: gate control, developing a time base for the frequency • Add a typical capacitive load on the selected measurement can be simplified by using the Timer0 CPSx pin. overflow flag. • Use the same fixed time base as the nominal It is recommend that the Timer0 overflow flag, in frequency measurement. conjunction with the Toggle mode of the Timer1 Gate, • At the start of the fixed time base, clear the timer be used to develop the fixed time base required by the resource. software portion of the CPS module. Refer to • At the end of the fixed time base, save the value Section21.6 “Timer1 Gate” for additional information. in the timer resource. The value of the timer resource is the number of TABLE 27-2: TIMER1 ENABLE FUNCTION oscillations of the capacitive sensing oscillator with an TMR1ON TMR1GE Timer1 Operation additional capacitive load. The frequency of the capac- itive sensing oscillator is equal to the number of counts 0 0 Off on in the timer, divided by the period of the fixed time 0 1 Off base. This frequency should be less than the value 1 0 On obtained during the nominal frequency measurement. 1 1 Count Enabled by input DS40001441F-page 280  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 27.7.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for CPS module. Note: For more information on general capacitive sensing refer to Application Notes: • AN1101, “Introduction to Capacitive Sensing” (DS01101) • AN1102, “Layout and Physical Design Guidelines for Capacitive Sensing” (DS01102) 27.8 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: Timer0 does not operate when in Sleep, and therefore, cannot be used for capacitive sense measurements in Sleep.  2011-2015 Microchip Technology Inc. DS40001441F-page 281

PIC12(L)F1840 27.9 Register Definitions: Capacitive Sensing Control REGISTER 27-1: CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSON: CPS Module Enable bit 1 = CPS module is enabled 0 = CPS module is disabled bit 6 CPSRM: Capacitive Sensing Reference Mode bit 1 = Capacitive Sensing module is in Variable Voltage Reference mode. 0 = Capacitive Sensing module is in Fixed Voltage Reference mode. bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CPSRNG<1:0>: Capacitive Sensing Current Range bit If CPSRM = 1 (variable voltage reference mode):(2) 11 = Oscillator is in High Current Range. 10 = Oscillator is in Medium Current Range. 01 = Oscillator is in Low Current Range. 00 = Oscillator is on. Noise detection mode. If CPSRM = 0 (Fixed Voltage Reference mode):(1) 11 = Oscillator is in High Current Range. 10 = Oscillator is in Medium Current Range. 01 = Oscillator is in Low Current Range. 00 = Oscillator is off. bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out of the pin) 0 = Oscillator is sinking current (Current flowing into the pin) bit 0 T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1: The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator, CPSCLK 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0: Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4 DS40001441F-page 282  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 REGISTER 27-2: CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 — — — — — — CPSCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 CPSCH<1:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 11 = channel 3, (CPS3) 10 = channel 2, (CPS2) 01 = channel 1, (CPS1) 00 = channel 0, (CPS0) TABLE 27-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 103 CPSCON0 CPSON CPSRM — — CPSRNG<1:0> CPSOUT T0XCS 282 CPSCON1 — — — — — — CPSCH<1:0> 283 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 145 T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON 154 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 102 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the CPS module.  2011-2015 Microchip Technology Inc. DS40001441F-page 283

PIC12(L)F1840 28.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16F/LF1847/PIC12F/LF1840 Memory Programming Specification”, (DS41439). 28.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure28-1 for example circuit. FIGURE 28-1: VPP LIMITER EXAMPLE CIRCUIT RJ11-6PIN 1 6 VPP 2 5 VDD 3 4 VSS 4 3 ICSP_DATA 5 2 ICSP_CLOCK 6 1 NC RJ11-6PIN To MPLAB® ICD 2 R1 To Target Board 270 Ohm LM431BCMX 23 AA U1 K1 6 A NC4 7 A NC5 VREF 8 R2 R3 10k 1% 24k 1% DS40001441F-page 284  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 28.2 Low-Voltage Programming Entry Note: The MPLAB ICD 2 produces a VPP Mode voltage greater than the maximum VPP specification of the PIC12(L)F1840. The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. MCLR is brought to VIL. 2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section7.4 “MCLR” for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. 28.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6 connector) configuration. See Figure28-2. FIGURE 28-2: ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT 2 4 6 NC VDD ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect  2011-2015 Microchip Technology Inc. DS40001441F-page 285

PIC12(L)F1840 Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1inch spacing. Refer to Figure28-3. FIGURE 28-3: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 1 = VPP/MCLR 2 2 = VDD Target 3 4 3 = VSS (ground) 5 4 = ICSPDAT 6 5 = ICSPCLK 6 = No Connect * The 6-pin header (0.100" spacing) accepts 0.025" square pins. DS40001441F-page 286  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure28-4 for more information. FIGURE 28-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming VDD Device to be Signals Programmed VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required).  2011-2015 Microchip Technology Inc. DS40001441F-page 287

PIC12(L)F1840 29.0 INSTRUCTION SET SUMMARY 29.1 Read-Modify-Write Operations Each instruction is a 14-bit word containing the Any instruction that specifies a file register as part of operation code (opcode) and all required operands. the instruction performs a Read-Modify-Write (R-M-W) The opcodes are broken into three broad categories. operation. The register is read, the data is modified, and the result is stored according to either the • Byte Oriented instruction, or the destination designator ‘d’. A read • Bit Oriented operation is performed on a register even if the • Literal and Control instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 29-1: OPCODE FIELD DESCRIPTIONS Table29-3 lists the instructions recognized by the MPASMTM assembler. Field Description All instructions are executed within a single instruction f Register file address (0x00 to 0x7F) cycle, with the following exceptions, which may take W Working register (accumulator) two or three cycles: b Bit address within an 8-bit file register • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two k Literal field, constant data or label cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1). • Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0. BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for • One additional instruction cycle will be used when compatibility with all Microchip software tools. any instruction references an indirect file register d Destination select; d = 0: store result in W, and the file select register is pointing to program d = 1: store result in file register f. memory. Default is d = 1. One instruction cycle consists of four oscillator cycles; n FSR or INDF number. (0-1) for an oscillator frequency of 4 MHz, this gives a mm Pre-post increment-decrement mode nominal instruction execution rate of 1 MHz. selection All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a TABLE 29-2: ABBREVIATION hexadecimal digit. DESCRIPTIONS Field Description PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit DS40001441F-page 288  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 7 6 0 OPCODE k (literal) k = 7-bit immediate value MOVLB instruction only 13 5 4 0 OPCODE k (literal) k = 5-bit immediate value BRA instruction only 13 9 8 0 OPCODE k (literal) k = 9-bit immediate value FSR Offset instructions 13 7 6 5 0 OPCODE n k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 3 2 1 0 OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE  2011-2015 Microchip Technology Inc. DS40001441F-page 289

PIC12(L)F1840 TABLE 29-3: PIC12(L)F1840 INSTRUCTION SET Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2 ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2 ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2 LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2 LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0000 00xx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 2 INCF f, d Increment f 1 00 1010 dfff ffff Z 2 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 2 MOVWF f Move W to f 1 00 0000 1fff ffff 2 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2 SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 2 BIT-ORIENTED SKIP OPERATIONS BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2 LITERAL OPERATIONS ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLB k Move literal to BSR 1 00 0000 001k kkkk MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk MOVLW k Move literal to W 1 11 0000 kkkk kkkk SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. DS40001441F-page 290  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 29-3: PIC12(L)F1840 INSTRUCTION SET (CONTINUED) Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BRA k Relative Branch 2 11 001k kkkk kkkk BRW – Relative Branch with W 2 00 0000 0000 1011 CALL k Call Subroutine 2 10 0kkk kkkk kkkk CALLW – Call Subroutine with W 2 00 0000 0000 1010 GOTO k Go to address 2 10 1kkk kkkk kkkk RETFIE k Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 0100 kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 INHERENT OPERATIONS CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD NOP – No Operation 1 00 0000 0000 0000 OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010 RESET – Software device Reset 1 00 0000 0000 0001 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD TRIS f Load TRIS register with W 1 00 0000 0110 0fff C-COMPILER OPTIMIZED ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3 modifier, mm k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2 MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3 modifier, mm k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See Table in the MOVIW and MOVWI instruction descriptions.  2011-2015 Microchip Technology Inc. DS40001441F-page 291

PIC12(L)F1840 29.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k Operands: -32  k  31 Operands: 0  k  255 n  [ 0, 1] Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: The contents of W register are Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The the contents of the FSRnH:FSRnL result is placed in the W register. register pair. FSRn is limited to the range 0000h - FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 d 0,1 Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWF Add W and f ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d} Operands: 0  f  127 Operands: 0  f  127 d 0,1 d [0,1] Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7> (f<7:1>)  dest<6:0>, Status Affected: C, DC, Z (f<0>)  C, Description: Add the contents of the W register Status Affected: C, Z with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted result is stored back in register ‘f’. one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in reg- ister ‘f’. ADDWFC ADD W and CARRY bit to f register f C Syntax: [ label ] ADDWFC f {,d} Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. DS40001441F-page 292  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b [ label ] BRA $+k Operands: 0  f  127 Operands: -256label-PC+1255 0  b < 7 -256  k  255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k  PC Status Affected: None Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Description: Add the signed 9-bit literal ‘k’ to the instruction is executed. PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next mented to fetch the next instruction, instruction is discarded and a NOP is the new address will be PC+1+k. executed instead, making this a This instruction is a 2-cycle instruc- 2-cycle instruction. tion. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W)  PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incre- mented to fetch the next instruction, the new address will be PC+1+(W). This instruction is a 2-cycle instruc- tion. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set.  2011-2015 Microchip Technology Inc. DS40001441F-page 293

PIC12(L)F1840 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<6:3>)  PC<14:11> 1  TO Status Affected: None 1  PD Description: Call Subroutine. First, return address Status Affected: TO, PD (PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch- The 11-bit immediate address is dog Timer. It also resets the prescaler loaded into PC bits <10:0>. The upper of the WDT. Status bits TO and PD bits of the PC are loaded from are set. PCLATH. CALL is a 2-cycle instruc- tion. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: (PC) +1  TOS, (W)  PC<7:0>, Operation: (f)  (destination) (PCLATH<6:0>) PC<14:8> Status Affected: Z Description: The contents of register ‘f’ are com- Status Affected: None plemented. If ‘d’ is ‘0’, the result is Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is return address (PC + 1) is pushed stored back in register ‘f’. onto the return stack. Then, the con- tents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the and the Z bit is set. result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS40001441F-page 294  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre- mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. is placed back in register ‘f’. If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is NOP is executed instead, making it a executed instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<6:3>  PC<14:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The 11-bit immediate value is loaded into result is placed in the W register. PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis- mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is is placed back in register ‘f’. placed back in register ‘f’.  2011-2015 Microchip Technology Inc. DS40001441F-page 295

PIC12(L)F1840 LSLF Logical Left Shift MOVF Move f Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d Operands: 0  f  127 Operands: 0  f  127 d [0,1] d  [0,1] Operation: (f<7>)  C Operation: (f)  (dest) (f<6:0>)  dest<7:1> Status Affected: Z 0  dest<0> Description: The contents of register f is moved to Status Affected: C, Z a destination dependent upon the Description: The contents of register ‘f’ are shifted status of d. If d = 0, destination is W one bit to the left through the Carry flag. register. If d = 1, the destination is file A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, register f itself. d = 1 is useful to test a the result is placed in W. If ‘d’ is ‘1’, the file register since status flag Z is result is stored back in register ‘f’. affected. Words: 1 C register f 0 Cycles: 1 Example: MOVF FSR, 0 After Instruction LSRF Logical Right Shift W = value in FSR register Syntax: [ label ] LSRF f {,d} Z = 1 Operands: 0  f  127 d [0,1] Operation: 0  dest<7> (f<7:1>)  dest<6:0>, (f<0>)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 0 register f C DS40001441F-page 296  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 MOVIW Move INDFn to W MOVLP Move literal to PCLATH Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k [ label ] MOVIW --FSRn Operands: 0  k  127 [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- Operation: k  PCLATH [ label ] MOVIW k[FSRn] Status Affected: None Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the mm  [00,01, 10, 11] PCLATH register. -32  k  31 Operation: INDFn  W Effective address is determined by MOVLW Move literal to W • FSR + 1 (preincrement) Syntax: [ label ] MOVLW k • FSR - 1 (predecrement) • FSR + k (relative offset) Operands: 0  k  255 After the Move, the FSR value will be Operation: k  (W) either: • FSR + 1 (all increments) Status Affected: None • FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg- • Unchanged ister. The “don’t cares” will assemble as Status Affected: Z ‘0’s. Words: 1 Mode Syntax mm Cycles: 1 Preincrement ++FSRn 00 Example: MOVLW 0x5A Predecrement --FSRn 01 After Instruction W = 0x5A Postincrement FSRn++ 10 Postdecrement FSRn-- 11 MOVWF Move W to f Syntax: [ label ] MOVWF f Description: This instruction is used to move data between W and one of the indirect Operands: 0  f  127 registers (INDFn). Before/after this Operation: (W)  (f) move, the pointer (FSRn) is updated by Status Affected: None pre/post incrementing/decrementing it. Description: Move data from W register to register Note: The INDFn registers are not ‘f’. physical registers. Any instruction that Words: 1 accesses an INDFn register actually accesses the register at the address Cycles: 1 specified by the FSRn. Example: MOVWF OPTION_REG Before Instruction FSRn is limited to the range 0000h - OPTION_REG = 0xFF FFFFh. Incrementing/decrementing it W = 0x4F beyond these bounds will cause it to After Instruction wrap-around. OPTION_REG = 0x4F W = 0x4F MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0  k  15 Operation: k  BSR Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR).  2011-2015 Microchip Technology Inc. DS40001441F-page 297

PIC12(L)F1840 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] NOP Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn Operands: None [ label ] MOVWI FSRn++ Operation: No operation [ label ] MOVWI FSRn-- [ label ] MOVWI k[FSRn] Status Affected: None Operands: n  [0,1] Description: No operation. mm  [00,01, 10, 11] Words: 1 -32  k  31 Cycles: 1 Operation: W  INDFn Example: NOP Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be Load OPTION_REG Register either: OPTION with W • FSR + 1 (all increments) • FSR - 1 (all decrements) Syntax: [ label ] OPTION Unchanged Operands: None Status Affected: None Operation: (W)  OPTION_REG Status Affected: None Mode Syntax mm Description: Move data from W register to Preincrement ++FSRn 00 OPTION_REG register. Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: 1 Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Description: This instruction is used to move data Before Instruction between W and one of the indirect OPTION_REG = 0xFF registers (INDFn). Before/after this W = 0x4F move, the pointer (FSRn) is updated by After Instruction pre/post incrementing/decrementing it. OPTION_REG = 0x4F W = 0x4F Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually RESET Software Reset accesses the register at the address specified by the FSRn. Syntax: [ label ] RESET Operands: None FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it Operation: Execute a device Reset. Resets the beyond these bounds will cause it to RI flag of the PCON register. wrap-around. Status Affected: None The increment/decrement operation on Description: This instruction provides a way to FSRn WILL NOT affect any Status bits. execute a hardware Reset by soft- ware. DS40001441F-page 298  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] RETFIE Syntax: [ label ] RETURN Operands: None Operands: None Operation: TOS  PC, Operation: TOS  PC 1  GIE Status Affected: None Status Affected: None Description: Return from subroutine. The stack is Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS) and Top-of-Stack (TOS) is loaded in is loaded into the program counter. the PC. Interrupts are enabled by This is a 2-cycle instruction. setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d Operands: 0  k  255 Operands: 0  f  127 Operation: k  (W); d  [0,1] TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the eight bit literal ‘k’. The program counter is Description: The contents of register ‘f’ are rotated loaded from the top of the stack (the one bit to the left through the Carry return address). This is a 2-cycle flag. If ‘d’ is ‘0’, the result is placed in instruction. the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 C Register f Cycles: 2 Example: CALL TABLE;W contains table Words: 1 ;offset value Cycles: 1 • ;W now has table value TABLE • Example: RLF REG1,0 • Before Instruction ADDWF PC ;W = offset REG1 = 1110 0110 RETLW k1 ;Begin table C = 0 RETLW k2 ; After Instruction • REG1 = 1110 0110 • W = 1100 1100 • C = 1 RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8  2011-2015 Microchip Technology Inc. DS40001441F-page 299

PIC12(L)F1840 SUBLW Subtract W from literal RRF Rotate Right f through Carry Syntax: [ label ] SUBLW k Syntax: [ label ] RRF f,d Operands: 0 k 255 Operands: 0  f  127 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s com- plement method) from the 8-bit literal Description: The contents of register ‘f’ are rotated ‘k’. The result is placed in the W regis- one bit to the right through the Carry ter. flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is C = 0 W  k placed back in register ‘f’. C = 1 W  k C Register f DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d Operands: None Operands: 0 f 127 d  [0,1] Operation: 00h  WDT, 0  WDT prescaler, Operation: (f) - (W) destination) 1  TO, Status Affected: C, DC, Z 0  PD Description: Subtract (2’s complement method) W Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is stored in the W register. If ‘d’ is cleared. Time-out Status bit, TO is ‘1’, the result is stored back in register set. Watchdog Timer and its pres- ‘f. caler are cleared. The processor is put into Sleep mode C = 0 W  f with the oscillator stopped. C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d} Operands: 0  f  127 d  [0,1] Operation: (f) – (W) – (B) dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s comple- ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001441F-page 300  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f<3:0>)  (destination<7:4>), Status Affected: Z (f<7:4>)  (destination<3:0>) Description: The contents of the W register are Status Affected: None XOR’ed with the 8-bit literal ‘k’. The Description: The upper and lower nibbles of regis- result is placed in the W register. ter ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. XORWF Exclusive OR W with f TRIS Load TRIS Register with W Syntax: [ label ] XORWF f,d Syntax: [ label ] TRIS f Operands: 0  f  127 Operands: 5  f  7 d  [0,1] Operation: (W)  TRIS register ‘f’ Operation: (W) .XOR. (f) destination) Status Affected: None Status Affected: Z Description: Move data from W register to TRIS Description: Exclusive OR the contents of the W register. register with register ‘f’. If ‘d’ is ‘0’, the When ‘f’ = 5, TRISA is loaded. result is stored in the W register. If ‘d’ When ‘f’ = 6, TRISB is loaded. is ‘1’, the result is stored back in regis- When ‘f’ = 7, TRISC is loaded. ter ‘f’.  2011-2015 Microchip Technology Inc. DS40001441F-page 301

PIC12(L)F1840 30.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias.......................................................................................................-40°C to +125°C Storage temperature........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC12F1840 ............................................................................. -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC12LF1840 ........................................................................... -0.3V to +4.0V Voltage on MCLR with respect to Vss .................................................................................................-0.3V to +9.0V Voltage on all other pins with respect to VSS ............................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)...............................................................................................................................800 mW Maximum current out of VSS pin, -40°C  TA  +85°C for industrial............................................................... 170 mA Maximum current out of VSS pin, -40°C  TA  +125°C for extended.............................................................. 70 mA Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 170 mA Maximum current into VDD pin, -40°C  TA  +125°C for extended................................................................. 70 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA Maximum output current sunk by any I/O pin....................................................................................................25 mA Maximum output current sourced by any I/O pin...............................................................................................25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS40001441F-page 302  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 30-1: PIC12F1840 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C 5.5 ) V ( D D V 2.5 2.3 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies. FIGURE 30-2: PIC12LF1840 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C V) 3.6 ( D D V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies.  2011-2015 Microchip Technology Inc. DS40001441F-page 303

PIC12(L)F1840 FIGURE 30-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 ± 3% C) ° 60 ( e r u at r e p 25 ± 2% m e T 0 ± 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001441F-page 304  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 30.1 DC Characteristics: Supply Voltage Standard Operating Conditions (unless otherwise stated) PIC12LF1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage (VDDMIN, VDDMAX) 1.8 — 3.6 V FOSC  16MHz: 2.5 — 3.6 V FOSC  32MHz D001 2.3 — 5.5 V FOSC  16MHz: 2.5 — 5.5 V FOSC  32MHz D002* VDR RAM Data Retention Voltage(1) 1.5 — — V Device in Sleep mode D002* 1.7 — — V Device in Sleep mode D002A* VPOR Power-on Reset Release Voltage — 1.6 — V D002B* VPORR* Power-on Reset Rearm Voltage — 0.8 — V D002B* — 1.5 — V D003 VADFVR Fixed Voltage Reference Voltage for 1.024V, VDD  2.5V ADC -8 — 6 % 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003A VCDAFVR Fixed Voltage Reference Voltage for 1.024V, VDD  2.5V Comparator and DAC -11 — 7 % 2.048V, VDD  2.5V 4.096V, VDD  4.75V D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section7.1 “Power-On Reset Power-on Reset signal (POR)” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.  2011-2015 Microchip Technology Inc. DS40001441F-page 305

PIC12(L)F1840 FIGURE 30-4: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR(1) POR REARM VSS TVLOW(2) TPOR(3) Note 1: When NPOR is low, the device is held in Reset. 2: TPOR 1s typical. 3: TVLOW 2.7s typical. DS40001441F-page 306  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 30.2 DC Characteristics: Supply Current (IDD) Standard Operating Conditions (unless otherwise stated) PIC12LF1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D010 — 5.0 12 A 1.8 FOSC = 32kHz — 7.4 25 A 3.0 LP Oscillator -40°C  TA  +85°C D010 — 17 28 A 2.3 FOSC = 32kHz — 19 38 A 3.0 LP Oscillator -40°C  TA  +85°C — 22 45 A 5.0 D010A — 5.0 21 A 1.8 FOSC = 32kHz LP Oscillator — 7.4 25 A 3.0 -40°C  TA  +125°C D010A — 17 60 A 2.3 FOSC = 32kHz LP Oscillator — 19 70 A 3.0 -40°C  TA  +125°C — 22 80 A 5.0 D011 — 60 95 A 1.8 FOSC = 1MHz XT Oscillator — 119 180 A 3.0 D011 — 110 200 A 2.3 FOSC = 1MHz XT Oscillator — 150 300 A 3.0 — 183 360 A 5.0 D012 — 165 240 A 1.8 FOSC = 4MHz XT Oscillator — 309 430 A 3.0 D012 — 240 400 A 2.3 FOSC = 4MHz XT Oscillator — 332 500 A 3.0 — 392 600 A 5.0 D013 — 34 120 A 1.8 FOSC = 1MHz External Clock (ECM), — 69 200 A 3.0 Medium-Power mode D013 — 70 150 A 2.3 FOSC = 1MHz External Clock (ECM), — 105 210 A 3.0 Medium-Power mode — 136 250 A 5.0 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k  2011-2015 Microchip Technology Inc. DS40001441F-page 307

PIC12(L)F1840 30.2 DC Characteristics: Supply Current (IDD) (Continued) Standard Operating Conditions (unless otherwise stated) PIC12LF1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D014 — 118 210 A 1.8 FOSC = 4MHz External Clock (ECM), — 222 380 A 3.0 Medium-Power mode D014 — 172 250 A 2.3 FOSC = 4MHz External Clock (ECM), — 290 380 A 3.0 Medium-Power mode — 350 480 A 5.0 D015 — 6.5 20 A 1.8 FOSC = 31kHz LFINTOSC — 9.0 31 A 3.0 -40°C  TA  +85°C D015 — 18 45 A 2.3 FOSC = 31kHz LFINTOSC — 24 50 A 3.0 -40°C  TA  +85°C — 25 60 A 5.0 D016 — 103 190 A 1.8 FOSC = 500kHz MFINTOSC — 124 220 A 3.0 D016 — 132 200 A 2.3 FOSC = 500kHz MFINTOSC — 165 250 A 3.0 — 210 300 A 5.0 D017 — 0.5 0.9 mA 1.8 FOSC = 8MHz HFINTOSC — 0.8 1.3 mA 3.0 D017 — 0.7 0.9 mA 2.3 FOSC = 8MHz HFINTOSC — 0.9 1.3 mA 3.0 — 1.0 1.5 mA 5.0 D018 — 0.7 1.2 mA 1.8 FOSC = 16MHz HFINTOSC — 1.2 1.8 mA 3.0 D018 — 0.9 1.5 mA 2.3 FOSC = 16MHz HFINTOSC — 1.2 2.0 mA 3.0 — 1.3 2.1 mA 5.0 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k DS40001441F-page 308  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 30.2 DC Characteristics: Supply Current (IDD) (Continued) Standard Operating Conditions (unless otherwise stated) PIC12LF1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Device Min. Typ† Max. Units No. Characteristics VDD Note Supply Current (IDD)(1, 2) D019 — 1.3 3.0 mA 3.0 FOSC = 32MHz HFINTOSC (Note 3) — 2.3 4.0 mA 3.6 D019 — 2.2 3.8 mA 3.0 FOSC = 32MHz HFINTOSC (Note 3) — 2.4 4.1 mA 5.0 D020 — 1.3 2.5 mA 3.0 FOSC = 32MHz HS Oscillator (Note 4) — 1.7 3.0 mA 3.6 D020 — 1.4 2.5 mA 3.0 FOSC = 32MHz HS Oscillator (Note 4) — 1.8 3.0 mA 5.0 D021 — 185 300 A 1.8 FOSC = 4MHz EXTRC (Note 5) — 390 480 A 3.0 D021 — 290 400 A 2.3 FOSC = 4MHz EXTRC (Note 5) — 415 550 A 3.0 — 495 600 A 5.0 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz internal oscillator with 4x PLL enabled. 4: 8MHz crystal oscillator with 4x PLL enabled. 5: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k  2011-2015 Microchip Technology Inc. DS40001441F-page 309

PIC12(L)F1840 30.3 DC Characteristics: Power-Down Base Current (IPD) Standard Operating Conditions (unless otherwise stated) PIC12LF1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D022 — 0.02 1.0 8.0 A 1.8 WDT, BOR, FVR and T1OSC — 0.03 2.0 9.0 A 3.0 disabled, all peripherals inactive D022 — 0.2 1.3 10 A 2.3 WDT, BOR, FVR and T1OSC — 0.3 2.0 12 A 3.0 disabled, all peripherals inactive, Low-power regulator active — 0.5 6.0 15 A 5.0 VREGPM = 1 D023 — 0.5 6.0 14 A 1.8 WDT Current (Note 1) — 0.8 7.0 17 A 3.0 D023 — 0.5 6 15 A 2.3 WDT Current — 0.8 7 20 A 3.0 VREGPM = 1 (Note 1) — 0.9 8 22 A 5.0 D023A — 8.5 23 25 A 1.8 FVR Current (Note 1) — 8.5 24 27 A 3.0 D023A — 18 26 30 A 2.3 FVR Current — 19 27 37 A 3.0 VREGPM = 0 (Note 1) — 20 29 45 A 5.0 D024 — 8.0 17 20 A 3.0 BOR Current (Note 1) D024 — 8.0 17 30 A 3.0 BOR Current — 9.0 20 40 A 5.0 VREGPM = 1 (Note 1) D025 — 0.3 5 9 A 1.8 T1OSC Current (Note 1) — 0.5 9 12 A 3.0 D025 — 1.1 6 10 A 2.3 T1OSC Current — 1.3 9 20 A 3.0 VREGPM = 1 (Note 1) — 1.4 10 25 A 5.0 D026 — 0.1 1.0 9 A 1.8 ADC Current (Note 1, 3) — 0.1 2.0 10 A 3.0 No conversion in progress D026 — 0.2 3.0 10 A 2.3 ADC Current — 0.4 4.0 11 A 3.0 No conversion in progress VREGPM = 1 (Note 1, 3) — 0.5 6.0 16 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. 3: ADC clock source is FRC. DS40001441F-page 310  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 30.3 DC Characteristics: Power-Down Base Current (IPD) (Continued) Standard Operating Conditions (unless otherwise stated) PIC12LF1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Standard Operating Conditions (unless otherwise stated) PIC12F1840 Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Conditions Param Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note Power-down Base Current (IPD)(2) D026A* — 250 — — A 1.8 ADC Current (Note 1, 3) — 250 — — A 3.0 Conversion in progress D026A* — 280 — — A 2.3 ADC Current — 280 — — A 3.0 Conversion in progress VREGPM = 1 (Note 1, 3) — 280 — — A 5.0 D027 — 3 12 15 A 1.8 Cap Sense, Low Power — 4 15 18 A 3.0 CPSRM = 0, CPSRNG = 01 (Note 1) D027 — 6.3 13 16 A 2.3 Cap Sense, Low Power — 8.5 18 20 A 3.0 CPSRM = 0, CPSRNG = 01 VREGPM = 1 (Note 1) — 12.8 23 25 A 5.0 D027A — 6.0 15 20 A 1.8 Cap Sense, Medium Power — 8.0 18 25 A 3.0 CPSRM = 0, CPSRNG = 10 (Note 1) D027A — 9.5 20 25 A 2.3 Cap Sense, Medium Power — 13 28 30 A 3.0 CPSRM = 0, CPSRNG = 10 VREGPM = 1 (Note 1) — 17 32 35 A 5.0 D027B — 15 35 40 A 1.8 Cap Sense, High Power — 39 60 75 A 3.0 CPSRM = 0, CPSRNG = 11 (Note 1) D027B — 20 40 45 A 2.3 Cap Sense, High Power — 42 68 80 A 3.0 CPSRM = 0, CPSRNG = 11 VREGPM = 1 (Note 1) — 49 72 86 A 5.0 D028 — 4.8 15 20 A 1.8 Comparator, — 4.9 17 23 A 3.0 Low Power, CxSP = 0 (Note 1) D028 — 4.9 16 21 A 2.3 Comparator, — 5.0 17 23 A 3.0 Low Power, CxSP = 0 VREGPM = 1 (Note 1) — 5.2 18 24 A 5.0 D028A — 27 50 60 A 1.8 Comparator, — 28 55 70 A 3.0 Normal Power, CxSP = 1 (Note 1) D028A — 27 52 62 A 2.3 Comparator, — 28 55 65 A 3.0 Normal Power, CxSP = 1 VREGPM = 1 (Note 1) — 29 57 75 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. 3: ADC clock source is FRC.  2011-2015 Microchip Technology Inc. DS40001441F-page 311

PIC12(L)F1840 30.4 DC Characteristics: I/O Ports Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O PORT: D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V D030A — — 0.15VDD V 1.8V  VDD  4.5V D031 with Schmitt Trigger buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C™ levels — — 0.3VDD V with SMBus levels — — 0.8 V 2.7V  VDD  5.5V D032 MCLR, OSC1 (RC mode) — — 0.2VDD V (Note 1) D033 OSC1 (HS mode) — — 0.3VDD V VIH Input High Voltage I/O PORT: D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V D040A 0.25VDD + — — V 1.8V  VDD  4.5V 0.8 D041 with Schmitt Trigger buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C™ levels 0.7VDD — — V with SMBus levels 2.1 — — V 2.7V  VDD  5.5V D042 MCLR 0.8VDD — — V D043A OSC1 (HS mode) 0.7VDD — — V D043B OSC1 (RC mode) 0.9VDD — — V VDD > 2.0V (Note 1) IIL Input Leakage Current(2) D060 I/O Ports — ± 5 ± 125 nA VSS  VPIN  VDD, Pin at high impedance, 85°C — ± 5 ± 1000 nA VSS  VPIN  VDD, Pin at high impedance, 125°C D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD, Pin at high impedance, 85°C IPUR Weak Pull-up Current D070* 25 100 200 A VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(4) D080 I/O Ports IOL = 8 mA, VDD = 5V — — 0.6 V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V VOH Output High Voltage(4) D090 I/O Ports IOH = 3.5 mA, VDD = 5V VDD - 0.7 — — V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode. DS40001441F-page 312  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 30.4 DC Characteristics: I/O Ports (Continued) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature-40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: Including OSC2 in CLKOUT mode.  2011-2015 Microchip Technology Inc. DS40001441F-page 313

PIC12(L)F1840 30.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial -40°C  TA  +125°C for extended Param Sym. Characteristic Min. Typ† Max. Units Conditions No. Program Memory High-Voltage Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V (Note 2) D111 IDDVPP Programming/Erase Current on VPP, — — 10 mA High Voltage Programming D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V D114 IPPPGM Programming/Erase Current on VPP, — 1.0 — mA Low Voltage Programming D115 IDDPGM Programming/Erase Current on VDD, — 5.0 — mA High or Low Voltage Programming Data EEPROM Memory D116 ED Byte Endurance 100K — — E/W -40C to +85C D117 VDRW VDD for Read/Write VDDMIN — VDDMAX V D118 TDEW Erase/Write Cycle Time — 4.0 5.0 ms D119 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D120 TREF Number of Total Erase/Write Cycles 1M 10M — E/W -40°C to +85°C before Refresh Program Flash Memory D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1) D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Required only if single-supply programming is disabled. DS40001441F-page 314  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 30.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 89.3 C/W 8-pin PDIP package 149.5 C/W 8-pin SOIC package 56.7 C/W 8-pin DFN package 39.4 C/W 8-pin UDFN 3X3mm package TH02 JC Thermal Resistance Junction to Case 43.1 C/W 8-pin PDIP package 39.9 C/W 8-pin SOIC package 9.0 C/W 8-pin DFN package 40.3 C/W 8-pin UDFN 3X3mm package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature.  2011-2015 Microchip Technology Inc. DS40001441F-page 315

PIC12(L)F1840 30.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDIx sc SCKx do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 30-5: LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins, 15 pF for OSC2 output DS40001441F-page 316  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 30.8 AC Characteristics: PIC12(L)F1840-I/E FIGURE 30-6: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 30-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz External Clock (ECL) DC — 4 MHz External Clock (ECM) DC — 32 MHz External Clock (ECH) Oscillator Frequency(1) — 32.768 — kHz LP Oscillator 0.1 — 4 MHz XT Oscillator 1 — 4 MHz HS Oscillator 1 — 20 MHz HS Oscillator, VDD > 2.7V DC — 4 MHz RC Oscillator, VDD > 2.0V OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator 250 —  ns XT Oscillator 50 —  ns HS Oscillator 50 —  ns External Clock (EC) Oscillator Period(1) — 30.5 — s LP Oscillator 250 — 10,000 ns XT Oscillator 50 — 1,000 ns HS Oscillator 250 — — ns RC Oscillator OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TosH, External CLKIN High, 2 — — s LP oscillator TosL External CLKIN Low 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, External CLKIN Rise, 0 — — ns LP oscillator TosF External CLKIN Fall 0 — — ns XT oscillator 0 — — ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.  2011-2015 Microchip Technology Inc. DS40001441F-page 317

PIC12(L)F1840 TABLE 30-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS08 HFOSC Internal Calibrated HFINTOSC 2% — 16.0 — MHz 0°C  TA  +60°C, VDD  2.5V Frequency (Note 1) 3% — 16.0 — MHz 60°C  TA  +85°C, VDD  2.5V 5% — 16.0 — MHz -40°C  TA  +125°C OS08A MFOSC Internal Calibrated MFINTOSC 2% — 500 — MHz 0°C  TA  +60°C, VDD  2.5V Frequency (Note 1) 3% — 500 — kHz 60°C  TA  +85°C, VDD  2.5V 5% — 500 — kHz -40°C  TA  +125°C OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz (Note 2) OS10* TIOSC ST HFINTOSC — — 5 8 s Wake-up from Sleep Start-up Time — — — — MFINTOSC Wake-up from Sleep Start-up Time — — 20 30 s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 2: See Figure31-64 and Figure31-65, LFINTOSC Frequency Characteristics over VDD and Temperature. TABLE 30-3: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % * These parameters are characterized but not tested. † Data in “Typ” column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001441F-page 318  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 30-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 TABLE 30-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TosH2ckL FOSC to CLKOUT (Note 1) — — 70 ns VDD = 3.3-5.0V OS12 TosH2ckH FOSC to CLKOUT (Note 1) — — 72 ns VDD = 3.3-5.0V OS13 TckL2ioV CLKOUT to Port out valid (Note 1) — — 20 ns OS14 TioV2ckH Port input valid before CLKOUT TOSC + 200 ns — — ns (Note 1) OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V (I/O in setup time) OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns (I/O in setup time) OS18* TioR Port output rise time — 40 72 ns VDD = 1.8V — 15 32 VDD = 3.3-5.0V OS19* TioF Port output fall time — 28 55 ns VDD = 1.8V — 15 30 VDD = 3.3-5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Tioc Interrupt-on-change new input level 25 — — ns time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.  2011-2015 Microchip Technology Inc. DS40001441F-page 319

PIC12(L)F1840 FIGURE 30-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. FIGURE 30-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33(1) (due to BOR) Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’. 2ms delay if PWRTE = 0. DS40001441F-page 320  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 30-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V, Time-out Period 1:16 Prescaler used 32 TOST Oscillator Start-up Timer Period — 1024 — Tosc (Note 1) 33* TPWRT Power-up Timer Period, PWRTE=0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low — — 2.0 s or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage (Note 2) 2.55 2.70 2.85 V BORV = 0, PIC12(L)F1840 2.35 2.45 2.58 V BORV = 1, PIC12F1840 1.80 1.90 2.00 V PIC12LF1840 37* VHYST Brown-out Reset Hysteresis 0 25 75 mV -40°C to +85°C 38* TBORDC Brown-out Reset DC Response 1 3 35 s VDD  VBOR Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended.  2011-2015 Microchip Technology Inc. DS40001441F-page 321

PIC12(L)F1840 FIGURE 30-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 TABLE 30-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = prescale value 20 or TCY + 40 N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value Period 30 or TCY + 40 N Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz (oscillator enabled by setting bit T1OSCEN) 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001441F-page 322  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 30-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP (Capture mode) CC01 CC02 CC03 Note: Refer to Figure30-5 for load conditions. TABLE 30-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C  TA  +125°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. CC01* TccL CCP Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP Input Period 3TCY + 40 — — ns N = prescale value N * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 30-8: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — ±1 ±1.7 LSb VREF = 3.0V AD03 EDL Differential Error — ±1 ±1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V AD05 EGN Gain Error — ±1 ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage (Note 4) 1.8 — VDD V VREF = (VREF+ minus VREF-) AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01 F capacitor is Analog Voltage Source present on input pin. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. 4: ADC Reference Voltage (Ref+) is the selected reference input, VREF+ pin, VDD pin or the FVR Buffer1. When the FVR is selected as the reference input, the FVR Buffer1 output selection must be 2.048V or 4.096V (ADFVR<1:0> = 1x).  2011-2015 Microchip Technology Inc. DS40001441F-page 323

PIC12(L)F1840 TABLE 30-9: ADC CONVERSION REQUIREMENTS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD ADC Clock Period 1.0 — 9.0 s FOSC-based ADC Internal RC Oscillator 1.0 2.0 6.0 s ADCS<2:0> = x11 (ADC FRC mode) Period AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion Acquisition Time) (Note 1) complete AD132* TACQ Acquisition Time — 5.0 — s * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. FIGURE 30-12: ADC CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (TOSC/2(1)) 1 TCY AD131 Q4 AD130 ADC CLK ADC Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. DS40001441F-page 324  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 30-13: ADC CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO AD134 (TOSC/2 + TCY(1)) 1 TCY AD131 Q4 AD130 ADC CLK ADC Data 7 6 5 4 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.  2011-2015 Microchip Technology Inc. DS40001441F-page 325

PIC12(L)F1840 TABLE 30-10: COMPARATOR SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 VIOFF Input Offset Voltage — ±7.5 ±60 mV CxSP = 1 VICM = VDD/2 CM02 VICM Input Common Mode Voltage 0 — VDD V CM03 CMRR Common Mode Rejection Ratio — 50 — dB CM04A Response Time Rising Edge — 400 800 ns CxSP = 1 CM04B Response Time Falling Edge — 200 400 ns CxSP = 1 TRESP(1) CM04C Response Time Rising Edge — 1200 — ns CxSP = 0 CM04D Response Time Falling Edge — 550 — ns CxSP = 0 CM05 TMC2OV Comparator Mode Change to — — 10 s Output Valid* CM06 CHYSTER Comparator Hysteresis — 45 — mV CxHYS = 1, CxSP = 1 (Note 2) * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. 2: Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled. TABLE 30-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA  25°C Param Sym. Characteristics Min. Typ. Max. Units Comments No. DAC01 CLSB Step Size — VDD/32 — V DAC02 CACC Absolute Accuracy — —  1/2 LSb VDD = 3.0V, TA = +25°C DAC03 CR Unit Resistor Value (R) — 5K —  DAC04* CST Settling Time (Note 1) — — 10 s * Parameter(s) characterized but not tested. Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’. DS40001441F-page 326  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 30-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 US122 Note: Refer to Figure30-5 for load conditions. TABLE 30-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns Clock high to data-out valid 1.8-5.5V — 100 ns US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns (Master mode) 1.8-5.5V — 50 ns US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns 1.8-5.5V — 50 ns FIGURE 30-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure30-5 for load conditions. TABLE 30-13: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Symbol Characteristic Min. Max. Units Conditions No. US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK  (DT hold time) 10 — ns US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns  2011-2015 Microchip Technology Inc. DS40001441F-page 327

PIC12(L)F1840 FIGURE 30-16: SPI MASTER MODE TIMING (CKE=0, SMP = 0) SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SP79 SCKx (CKP = 1) SP79 SP78 SP80 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-5 for load conditions. FIGURE 30-17: SPI MASTER MODE TIMING (CKE=1, SMP = 1) SSx SP81 SCKx (CKP = 0) SP71 SP72 SP79 SP73 SCKx (CKP = 1) SP80 SP78 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-5 for load conditions. DS40001441F-page 328  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 30-18: SPI SLAVE MODE TIMING (CKE=0) SSx SP70 SCKx SP83 (CKP = 0) SP71 SP72 SP78 SP79 SCKx (CKP = 1) SP79 SP78 SP80 SDOx MSb bit 6 - - - - - -1 LSb SP75, SP76 SP77 SDIx MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure30-5 for load conditions. FIGURE 30-19: SPI SLAVE MODE TIMING (CKE=1) SP82 SSx SP70 SCKx SP83 (CKP = 0) SP71 SP72 SCKx (CKP = 1) SP80 SDOx MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDIx MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure30-5 for load conditions.  2011-2015 Microchip Technology Inc. DS40001441F-page 329

PIC12(L)F1840 TABLE 30-14: SPI MODE REQUIREMENTS Param Symbol Characteristic Min. Typ† Max. Units Conditions No. SP70* TSSL2SCH, SS to SCK or SCK input 2.25 TCY — — ns TSSL2SCL SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns TDIV2SCL SP74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns TSCL2DIL SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns 1.8-5.5V — 25 50 ns SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns (Master mode) 1.8-5.5V — 25 50 ns SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns TSCL2DOV SCK edge 1.8-5.5V — — 145 ns SP81* TDOV2SCH, SDO data output setup to SCK edge Tcy — — ns TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge — — 50 ns SP83* TSCH2SSH, SSafter SCK edge 1.5TCY + 40 — — ns TSCL2SSH * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001441F-page 330  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 30-20: I2C™ BUS START/STOP BITS TIMING SCLx SP91 SP93 SP90 SP92 SDAx Start Stop Condition Condition Note: Refer to Figure30-5 for load conditions. TABLE 30-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol Characteristic Min. Typ. Max. Units Conditions No. SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Setup time 400 kHz mode 600 — — repeated Start condition SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first Hold time 400 kHz mode 600 — — clock pulse is generated SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — SP93* THD:STO Stop condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested.  2011-2015 Microchip Technology Inc. DS40001441F-page 331

PIC12(L)F1840 FIGURE 30-21: I2C™ BUS DATA TIMING SP103 SP100 SP102 SP101 SCLx SP90 SP106 SP107 SP91 SP92 SDAx In SP110 SP109 SP109 SDAx Out Note: Refer to Figure30-5 for load conditions. I TABLE 30-16: I2C™ BUS DATA REQUIREMENTS Param. Symbol Characteristic Min. Max. Units Conditions No. SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz SSP module 1.5TCY — — SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz SSP module 1.5TCY — — SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from 10-400 pF SP103* TF SDA and SCL fall 100 kHz mode — 250 ns time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from 10-400 pF SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2) time 400 kHz mode 100 — ns SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1) clock 400 kHz mode — — ns SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free 400 kHz mode 1.3 — s before a new transmission can start SP111 CB Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT=1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001441F-page 332  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 30-17: CAP SENSE OSCILLATOR SPECIFICATIONS Param. Symbol Characteristic Min. Typ† Max. Units Conditions No. CS01 ISRC Current Source High — -8 — A Medium — -1.5 — A Low — -0.3 — A CS02 ISNK Current Sink High — 7.5 — A Medium — 1.5 — A Low — 0.25 — A CS03 VCTH Cap Threshold — 0.8 — V CS04 VCTL Cap Threshold — 0.4 — V CS05 VCHYST Cap Hysteresis High — 525 — mV (VCTH - VCTL) Medium — 375 — mV Low — 300 — mV † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 30-22: CAP SENSE OSCILLATOR VCTH VCTL ISRC ISNK Enabled Enabled  2011-2015 Microchip Technology Inc. DS40001441F-page 333

PIC12(L)F1840 30.9 High Temperature Operation Note1: Writes are not allowed for Flash This section outlines the specifications for the following program memory above 125°C. devices operating in the high temperature range between -40°C and 150°C.(2) 2: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 • PIC12F1840(4) hours. Any design in which the total oper- When the value of any parameter is identical for both ating time from 125°C to 150°C will be the 125°C Extended and the 150°C High Temp. greater than 1,000 hours is not warranted temperature ranges, then that value will be found in the without prior written approval from standard specification tables shown earlier in this Microchip Technology Inc. chapter, under the fields listed for the 125°C Extended 3: The temperature range indicator in the temperature range. If the value of any parameter is catalog part number and device marking unique to the 150°C High Temp. temperature range, is “H” for -40°C to 150°C. then it will be listed here, in this section of the data Example: PIC12F1840T-H/SN indicates sheet. the device is shipped in a Tape and Reel If a Silicon Errata exists for the product and it lists a configuration, in the SOIC package, and modification to the 125°C Extended temperature range is rated for operation from -40°C to value, one that is also shared at the 150°C High Temp. 150°C. temperature range, then that modified value will apply 4: The low voltage version of this device, to both temperature ranges. PIC12LF1840, is not released for operation above +125°C. 5: Errata Sheet DS80538 lists various mask revisions. 150°C operation applies only to revisions A5 and later. 6: The Capacitive Sensing module (CPS) should not be used in high temperature devices. Function and its parametrics are not warranted. 7: Only SOIC (SN) and DFN (MF) packages will be offered, not PDIP or UQFN. TABLE 30-18: ABSOLUTE MAXIMUM RATINGS Parameter Condition Value Max. Current: VDD Source 15 mA Max. Current: VSS Sink 15 mA Max. Current: Pin Source 5 mA Max. Current: Pin Sink 5 mA Max. Storage Temperature — -65°C to 155°C Max. Junction Temperature — +155°C Ambient Temperature under Bias — -40°C to +150°C Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001441F-page 334  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 30-23: PIC12F1840 VOLTAGE FREQUENCY GRAPH, -40°C  TA +150°C 5.5 ) V ( D D V 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table30-1 for each Oscillator mode’s supported frequencies. FIGURE 30-24: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 150 ± 10% 125 C) n ° 85 o e ( ati ur er at p r O pe 25 o ± 5% m N e T 0 -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2011-2015 Microchip Technology Inc. DS40001441F-page 335

PIC12(L)F1840 TABLE 30-19: DC CHARACTERISTICS FOR PIC12F1840-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1840 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristics Min. Typ. Max. Units Condition No. D001 VDD Supply Voltage 2.5 — 5.5 V FOSC  32 MHz (Note 2) D002* VDR RAM Data Retention Voltage(1) 2.1 — 5.5 V Device in Sleep mode D003 VADFVR Fixed Voltage Reference -10 — 8 % 1.024V, VDD  2.5V Voltage for ADC 2.048V, VDD  2.5V 4.096V, VDD  4.75V D003A VCDAFVR Fixed Voltage Reference -13 — 9 % 1.024V, VDD  2.5V Voltage for ADC 2.048V, VDD  2.5V 4.096V, VDD  4.75V * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. DS40001441F-page 336  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 TABLE 30-20: MEMORY PROGRAMMING REQUIREMENTS FOR PIC12F1840-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1840 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. Data EEPROM Memory D116 ED Byte Endurance 50K — — E/W -40°C to +150°C D118 TDEW Erase/Write Cycle Time — — 6.0 ms -40°C to +150°C D119 TRETD Data Retention — 20 — Years  50K Programming cycles Program Flash Memory D121 EP Cell Endurance — — — — Programming the Flash memory above +125°C is not permitted D124 TRETD Data Retention — 20 — Years TABLE 30-21: OSCILLATOR PARAMETERS FOR PIC12F1840-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1840 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Frequency Sym. Characteristic Min. Typ. Max. Units Conditions No. Tolerance OS08 HFOSC Int. Calibrated HFINTOSC ±5% — 16.0 — MHz -40°C TA 125°C Freq.(1) VDD 2.5V ±10% — 16.0 — MHz -40°C TA 150°C VDD 2.5V OS08A MFOSC Int. Calibrated MFINTOSC ±5% — 500 — kHz -40°C TA 125°C Freq.(1) VDD 2.5V ±10% — 500 — kHz -40°C TA 150°C VDD 2.5V OS09 LFOSC Internal LFINTOSC Freq. ±35% — 31 — kHz -40°C TA 150°C VDD 2.5V † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended. TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS FOR PIC12F1840-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1840 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. 31 TWDTLP Low-Power Watchdog Timer 8 16 30 ms VDD = 3.3V-5V Time-out Period (No Prescaler) 1:16 Prescaler used 35 VBOR Brown-out Reset Voltage(1) 2.50 2.70 2.90 V BORV = 0 — — — — BORV = 1 † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended.  2011-2015 Microchip Technology Inc. DS40001441F-page 337

PIC12(L)F1840 TABLE 30-23: A/D CONVERTER (ADC) CHARACTERISTICS FOR PIC12F1840-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1840 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. AD04 EOFF Offset Error — — 3.5 LSB No missing codes VREF = 3.0V † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input. TABLE 30-24: COMPARATOR SPECIFICATIONS FOR PIC12F1840-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1840 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. CM01 VIOFF Input Offset Voltage — — ±70 mV High-Power mode, VICM = VDD/2 TABLE 30-25: CAP SENSE OSCILLATOR SPECIFICATIONS FOR PIC12F1840-H (High Temp.) Standard Operating Conditions: (unless otherwise stated) PIC12F1840 Operating Temperature: -40°C  TA  +150°C for High Temperature Param Sym. Characteristic Min. Typ. Max. Units Conditions No. All All All — — — — This module is not intended for use in high temperature devices. DS40001441F-page 338  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 31.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each temperature range.  2011-2015 Microchip Technology Inc. DS40001441F-page 339

PIC12(L)F1840 FIGURE 31-1: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC12LF1840 ONLY 25 Max: 85°C + 3(cid:305) Max. 20 Typical: 25°C 15 A) μ ( D D I 10 Typical 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-2: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC12F1840 ONLY 40 Max: 85°C + 3(cid:305) 35 Max. Typical: 25°C 30 25 Typical A) (μ 20 D D I 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 340  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC12LF1840 ONLY 500 450 Typical: 25°C 4 MHz EXTRC 400 350 4 MHz XT 300 A) (μ 250 D D I 200 1 MHz XT 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC12LF1840 ONLY 600 500 Max: 85°C + 3(cid:305) 4 MHz EXTRC 400 4 MHz XT A) μ ( 300 D D I 1 MHz XT 200 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 341

PIC12(L)F1840 FIGURE 31-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC12F1840 ONLY 4 MHz EXTRC Typical: 25°C 500 4 MHz XT 400 A) 300 μ ( D D 1 MHz XT I 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC12F1840 ONLY 600 Max: 85°C + 3(cid:305) 4 MHz EXTRC 500 4 MHz XT 400 1 MHz XT A) 300 μ ( D D I 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 342  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-7: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC12LF1840 ONLY 16 Max: 85°C + 3(cid:305) 14 Typical: 25°C Max. 12 10 A) μ 8 ( D D I 6 Typical 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-8: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz, PIC12F1840 ONLY 40 Max: 85°C + 3(cid:305) 35 Typical: 25°C Max. 30 Typical 25 A) μ (D 20 D I 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 343

PIC12(L)F1840 FIGURE 31-9: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC12LF1840 ONLY 70 Max: 85°C + 3(cid:305) 60 Typical: 25°C 50 Max. 40 Typical A) μ ( D D 30 I 20 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-10: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 500 kHz, PIC12F1840 ONLY 70 60 Max. 50 A) 40 μ Typical ( D D I 30 20 Max: 85°C + 3(cid:305) 10 Typical: 25°C 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 344  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-11: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC12LF1840 ONLY 350 300 Typical: 25°C 4 MHz 250 200 A) μ ( D D 150 I 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-12: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC12LF1840 ONLY 400 350 Max: 85°C + 3(cid:305) 4 MHz 300 250 A) (μ 200 D D I 150 1 MHz 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 345

PIC12(L)F1840 FIGURE 31-13: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC12F1840 ONLY 400 4 MHz 350 Typical: 25°C 300 250 A) μ ( 200 D D I 150 1 MHz 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-14: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC12F1840 ONLY 450 4 MHz 400 Max: 85°C + 3(cid:305) 350 300 A) 250 μ ( D D 200 I 1 MHz 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 346  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-15: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC12LF1840 ONLY 2.5 Typical: 25°C 32 MHz 2.0 1.5 A) m ( D 16 MHz D I 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-16: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC12LF1840 ONLY 3.0 2.5 Max: 85°C + 3(cid:305) 32 MHz 2.0 A) m 1.5 ( DD 16 MHz I 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 347

PIC12(L)F1840 FIGURE 31-17: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC12F1840 ONLY 2.5 Typical: 25°C 32 MHz 2.0 1.5 A) 16 MHz m ( D D 1.0 I 8 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-18: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE, PIC12F1840 ONLY 2.5 Max: 85°C + 3(cid:305) 32 MHz 2.0 16 MHz 1.5 A) m ( D ID 1.0 8 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 348  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-19: IDD, LFINTOSC, FOSC = 31 kHz, PIC12LF1840 ONLY 30 Max: 85°C + 3(cid:305) Max. 25 Typical: 25°C 20 A) μ ( D 15 D I Typical 10 5 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-20: IDD, LFINTOSC, FOSC = 31 kHz, PIC12F1840 ONLY 35 Max. 30 25 Typical A) 20 μ ( D D I 15 10 Max: 85°C + 3(cid:305) 5 Typical: 25°C 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 349

PIC12(L)F1840 FIGURE 31-21: IDD, MFINTOSC, FOSC = 500 kHz, PIC12LF1840 ONLY 200 180 Max: 85°C + 3(cid:305) Max. Typical: 25°C 160 Typical 140 120 A) μ 100 ( D D I 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-22: IDD, MFINTOSC, FOSC = 500 kHz, PIC12F1840 ONLY 300 Max. Max: 85°C + 3(cid:305) 250 Typical: 25°C Typical 200 A) (μ 150 D D I 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 350  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-23: IDD TYPICAL, HFINTOSC, PIC12LF1840 ONLY 3.0 Typical: 25°C 2.5 2.0 32 MHz (4x PLL) A) m ( 1.5 D D I 16 MHz 1.0 8 MHz 4 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-24: IDD MAXIMUM, HFINTOSC, PIC12LF1840 ONLY 5.0 4.5 Max: 85°C + 3(cid:305) 4.0 3.5 32 MHz (4x PLL) 3.0 A) m ( 2.5 D D I 2.0 16 MHz 1.5 8 MHz 1.0 4 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 351

PIC12(L)F1840 FIGURE 31-25: IDD TYPICAL, HFINTOSC, PIC12F1840 ONLY 3.0 32 MHz (4x PLL) 2.5 Typical: 25°C 2.0 A) m 1.5 16 MHz ( D ID 8 MHz 1.0 4 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-26: IDD MAXIMUM, HFINTOSC, PIC12F1840 ONLY 4.5 32 MHz (4x PLL) 4.0 Max: 85°C + 3(cid:305) 3.5 3.0 A) 2.5 m 16 MHz ( D 2.0 D I 8 MHz 1.5 1.0 4 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 352  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-27: IDD TYPICAL, HS OSCILLATOR, PIC12LF1840 ONLY 1.8 32 MHz 1.6 Typical: 25°C 1.4 1.2 A) 1.0 m ( 0.8 8 MHz D D I 0.6 4 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-28: IDD MAXIMUM, HS OSCILLATOR, PIC12LF1840 ONLY 2.5 Max: 85°C + 3(cid:305) 2.0 32 MHz 1.5 A) m ( DD 1.0 8 MHz I 4 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 353

PIC12(L)F1840 FIGURE 31-29: IDD TYPICAL, HS OSCILLATOR, PIC12F1840 ONLY 2.0 32 MHz 1.8 Typical: 25°C 1.6 1.4 1.2 A) 1.0 8 MHz m (D 0.8 D I 4 MHz 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-30: IDD MAXIMUM, HS OSCILLATOR, PIC12F1840 ONLY 2.5 32 MHz Max: 85°C + 3(cid:305) 2.0 1.5 A) m 8 MHz ( D D 1.0 I 4 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 354  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-31: IPD BASE, SLEEP MODE, PIC12LF1840 ONLY 445500 MMax: 8855°°CC + 33(cid:305) Max. 400 Typical: 25°C 350 300 A)A) 225500 nn (( DD P 200 I 150 100 Typical 50 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-32: IPD BASE, LOW-POWER SLEEP MODE, VREGPM = 1, PIC12F1840 ONLY 660000 MMaaxx.. Max: 85°C + 3(cid:305) 500 Typical: 25°C 400 A)A) nn (( 330000 DD PP I Typical 200 100 00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 355

PIC12(L)F1840 FIGURE 31-33: IPD, WATCHDOG TIMER (WDT), PIC12LF1840 ONLY 11..44 Max: 85°C + 3(cid:305) 1.2 Typical: 25°C Max. 1.0 00.88 A)A μμ TTyyppiiccaall (( PDPD 00..66 II 0.4 0.2 00..00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-34: IPD, WATCHDOG TIMER (WDT), PIC12F1840 ONLY 11..22 Max: 85°C + 3(cid:305) 1.0 Typical: 25°C Max. 0.8 A)A μμ TTyyppiiccaall (( 00..66 DD PP II 0.4 0.2 00..00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001441F-page 356  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12LF1840 ONLY 2255 MMaaxx.. Typical 20 15 A)A μμ (( DD PP II 1100 Max: 85°C + 3(cid:305) 5 Typical: 25°C 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12F1840 ONLY 3300 25 Max. 20 A) Typical μμ (( 1155 DD PP II 10 5 Max: 85°C + 3(cid:305) Typical: 25°C 00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 357

PIC12(L)F1840 FIGURE 31-37: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12LF1840 ONLY 1122 Max. Max: 85°C + 3(cid:305) 10 Typical: 25°C 8 Typical A)A) 66 μμ (( DD P I 4 2 00 11.66 11.88 22.00 22.22 22.44 22.66 22.88 33.00 33.22 33.44 33.66 33.88 VDD(V) FIGURE 31-38: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12F1840 ONLY 1144 MMaaxx. MMaax: 8855°°CC ++ 33(cid:305)(cid:305) 12 Typical: 25°C 10 Typical 8 A)A) μμ (( DD 66 PP II 4 2 00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001441F-page 358  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-39: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC12LF1840 ONLY 66..00 Max: 85°C + 3(cid:305) 5.0 Typical: 25°C Max. 4.0 A)A μμ 33..00 (( DD PP II TTyyppiiccaall 2.0 1.0 00..00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 31-40: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC12F1840 ONLY 1122 Max: 85°C + 3(cid:305) 10 Typical: 25°C Max. 8 A) ((μμ 66 TTyyppiiccaall DD PP II 4 2 00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 359

PIC12(L)F1840 FIGURE 31-41: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC12F1840 ONLY 6 5 4 V) (H 3 O V 125°C Typical 2 -40°C Graph represents 1 3(cid:305)Limits 0 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 IOH(mA) FIGURE 31-42: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC12F1840 ONLY 5 125°C Graph represents 4 3(cid:305)Limits 3 V) ( L O Typical V 2 -40°C 1 0 0 10 20 30 40 50 60 70 80 90 100 IOL(mA) DS40001441F-page 360  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-43: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V 3.5 Graph represents 3.0 3(cid:305)Limits 2.5 V) 2.0 ( H O 125°C V 1.5 Typical 1.0 -40°C 0.5 0.0 -15 -13 -11 -9 -7 -5 -3 -1 IOH(mA) FIGURE 31-44: VOL vs. IOL, OVER TEMPERATURE, VDD = 3.0V 3.0 125°C Graph represents 2.5 3(cid:305)Limits Typical 2.0 -40°C V) ( 1.5 L O V 1.0 0.5 0.0 0 5 10 15 20 25 30 35 40 IOL(mA)  2011-2015 Microchip Technology Inc. DS40001441F-page 361

PIC12(L)F1840 FIGURE 31-45: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC12LF1840 ONLY 2.0 Graph represents 1.8 3(cid:305)Limits 1.6 1.4 125°C 1.2 V) (H 1.0 O Typical V 0.8 0.6 -40°C 0.4 0.2 0.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH(mA) FIGURE 31-46: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC12LF1840 ONLY 1.8 Graph represents 1.6 3(cid:305)Limits 1.4 125°C 1.2 Typical V) 1.0 ( -40°C L O V 0.8 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 10 IOL(mA) DS40001441F-page 362  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-47: POR RELEASE VOLTAGE 1.70 1.68 Max. 1.66 1.64 Typical ) 1.62 V ge ( 1.60 Min. a t ol 1.58 V 1.56 1.54 Max: Typical + 3(cid:305) Typical: 25°C 1.52 Min: Typical -3(cid:305) 1.50 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-48: POR REARM VOLTAGE, PIC12F1840 ONLY 1.54 1.52 Max: Typical + 3(cid:305) Typical: 25°C 1.50 Min: Typical -3(cid:305) Max. 1.48 ) 1.46 V e ( g 1.44 a Typical t ol 1.42 V 1.40 Min. 1.38 1.36 1.34 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001441F-page 363

PIC12(L)F1840 FIGURE 31-49: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC12LF1840 ONLY 2.00 Max. 1.95 ) V ge ( 1.90 Typical a t ol V 1.85 Min. Max: Typical + 3(cid:305) Min: Typical -3(cid:305) 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-50: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC12LF1840 ONLY 60 50 Max. Max: Typical + 3(cid:305) 40 Typical: 25°C Min: Typical -3(cid:305) ) V m Typical e ( 30 g a t ol V 20 Min. 10 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) DS40001441F-page 364  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-51: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC12F1840 ONLY 2.60 2.55 Max. 2.50 ) Typical V ge ( 2.45 a t ol V Min. 2.40 Max: Typical + 3(cid:305) 2.35 Min: Typical -3(cid:305) 2.30 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-52: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC12F1840 ONLY 70 Max. 60 Max: Typical + 3(cid:305) 50 Typical: 25°C Min: Typical -3(cid:305) ) V 40 m Typical e ( g a 30 t ol V 20 Min. 10 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001441F-page 365

PIC12(L)F1840 FIGURE 31-53: BROWN-OUT RESET VOLTAGE, BORV = 0 2.80 2.75 Max. ) 2.70 V e ( Typical g a t ol 2.65 V Min. Max: Typical + 3(cid:305) 2.60 Min: Typical -3(cid:305) 2.55 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) DS40001441F-page 366  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-54: LOW POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0 2.50 Max. Max: Typical + 3(cid:305) 2.40 Min: Typical -3(cid:305) 2.30 Typical ) V 2.20 e ( g a olt 2.10 V 2.00 Min. 1.90 1.80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 31-55: LOW POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0 45 40 Max: Typical + 3(cid:305) Max. Typical: 25°C 35 Min: Typical -3(cid:305) Typical 30 ) V m 25 Min. e ( g 20 a t ol V 15 10 5 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)  2011-2015 Microchip Technology Inc. DS40001441F-page 367

PIC12(L)F1840 FIGURE 31-56: WDT TIME-OUT PERIOD 24 22 Max. 20 ) s 18 m Typical e ( m 16 Ti Min. 14 Max: Typical + 3(cid:305)(-40°C to +125°C) 12 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-57: PWRT PERIOD 100 Max: Typical + 3(cid:305)(-40°C to +125°C) Typical: statistical mean @ 25°C 90 Min: Typical -3(cid:305)(-40°C to +125°C) Max. 80 ) s m e ( 70 Typical m Ti 60 Min. 50 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 368  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-58: FVR STABILIZATION PERIOD 40 Max: Typical + 3(cid:305) 35 Max. Typical: statistical mean @ 25°C 30 Typical 25 ) s u e ( 20 m Ti 15 Note: 10 The FVR Stabilization Period applies when: 1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices. 2) when exiting sleep mode with VREGPM = 1for PIC12/16Fxxxx devices 5 In all other cases, the FVR is stable when released from RESET. 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 369

PIC12(L)F1840 FIGURE 31-59: COMPARATOR HYSTERESIS, NORMAL-POWER MODE, CxSP = 1, CxHYS = 1 80 70 Max. 60 Typical ) V m 50 ( s si 40 e r Min. e t ys 30 H 20 Max: Typical + 3(cid:305) Typical: 25°C 10 Min: Typical -3(cid:305) 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-60: COMPARATOR HYSTERESIS, LOW-POWER MODE, CxSP = 0, CxHYS = 1 16 14 Max. 12 Typical ) V m 10 ( s si 8 e r e t s 6 y H Min. 4 Max: Typical + 3(cid:305) 2 Typical: 25°C Min: Typical -3(cid:305) 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 370  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-61: COMPARATOR RESPONSE TIME, NORMAL-POWER MODE, CxSP = 1 350 300 250 Max. s) 200 n e ( Typical m 150 Ti 100 Max: Typical + 3(cid:305) 50 Typical: 25°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-62: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER MODE, CxSP = 1 400 350 Graph represents 3(cid:305)Limits 300 250 ) ns 125°C e ( 200 m Ti 150 Typical 100 -40°C 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 371

PIC12(L)F1840 FIGURE 31-63: COMPARATOR INPUT OFFSET AT 25°C, NORMAL-POWER MODE, CxSP = 1, PIC12F1840 ONLY 50 40 30 Max. 20 ) V 10 m Typical e ( 0 g ta Min. ol -10 V et -20 s f Of -30 Max: Typical + 3(cid:305) Typical: 25°C -40 Min: Typical -3(cid:305) -50 0.0 1.0 2.0 3.0 4.0 5.0 Common Mode Voltage (V) DS40001441F-page 372  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-64: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC12LF1840 ONLY 36 34 Max. 32 30 ) Typical z H (k 28 y c n e 26 Min. u q e Fr 24 Max: Typical + 3(cid:305)(-40°C to +125°C) 22 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 31-65: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC12F1840 ONLY 36 34 Max. 32 30 z) Typical H k ( 28 y c n ue 26 Min. q e r F 24 Max: Typical + 3(cid:305)(-40°C to +125°C) 22 Typical: statistical mean @ 25°C Min: Typical -3(cid:305)(-40°C to +125°C) 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 373

PIC12(L)F1840 FIGURE 31-66: CAP SENSE CURRENT SINK/SOURCE CHARACTERISTICS, FIXED VOLTAGE REFERENCE (CPSRM = 0), HIGH CURRENT RANGE (CPSRNG = 11) 20 15 Sink Typical Sink Max. 10 5 Sink Min. A) u ( 0 N PI I -5 Source Min. -10 Source Max. Source Typical Max: Typical + 3(cid:305) -15 Typical: Min: Typical -3(cid:305) -20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 31-67: CAP SENSE CURRENT SINK/SOURCE CHARACTERISTICS, FIXED VOLTAGE REFERENCE (CPSRM = 0), MEDIUM CURRENT RANGE (CPSRNG = 10) 5 Max: Typical + 3(cid:305) 4 Typical: Min: Typical -3(cid:305) 3 Sink Max. Sink Typical 2 A) 1 Sink Min. u ( 0 N PI I -1 Source Min. -2 Source Typical Source Max. -3 -4 -5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001441F-page 374  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 FIGURE 31-68: CAP SENSE CURRENT SINK/SOURCE CHARACTERISTICS, FIXED VOLTAGE REFERENCE (CPSRM = 0), LOW CURRENT RANGE (CPSRNG = 01) 0.8 0.6 Sink Max. Sink Typical 0.4 0.2 Sink Min. A) 0.0 u ( -0.2 N Source Min. PI I -0.4 Source Typical -0.6 Source Max. -0.8 Max: Typical + 3(cid:305) -1.0 Typical: Min: Typical -3(cid:305) -1.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2011-2015 Microchip Technology Inc. DS40001441F-page 375

PIC12(L)F1840 32.0 DEVELOPMENT SUPPORT 32.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker DS40001441F-page 376  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 32.2 MPLAB XC Compilers 32.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 32.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 32.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process  2011-2015 Microchip Technology Inc. DS40001441F-page 377

PIC12(L)F1840 32.6 MPLAB X SIM Software Simulator 32.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 32.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 32.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 32.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001441F-page 378  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 32.11 Demonstration/Development 32.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.  2011-2015 Microchip Technology Inc. DS40001441F-page 379

PIC12(L)F1840 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX 12F1840 XXXXXNNN /P017 YYWW 1212 8-Lead SOIC (3.90 mm) Example 12F1840 /SN1212 NNN 017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC® designator e( 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS40001441F-page 380  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 33.2 Package Marking Information 8-Lead DFN (3x3x0.9 mm) Example 8-Lead UDFN (3x3x0.5 mm) XXXX MFQ0 YYWW 1212 NNN 017 PIN 1 PIN 1 TABLE 33-1: 8-LEAD 3X3 DFN (MF) TOP MARKING Part Number Marking PIC12F1840T-E/MF MFQ0 PIC12F1840T-I/MF MFR0 PIC12LF1840T-E/MF MFS0 PIC12LF1840T-I/MF MFT0 TABLE 33-2: 8-LEAD 3X3 UDFN (RF) TOP MARKING Part Number Marking PIC12F1840T-I/RF DAC0 PIC12F1840T-E/RF DAD0 PIC12LF1840T-I/RF DAJ0 PIC12LF1840T-E/RF DAK0  2011-2015 Microchip Technology Inc. DS40001441F-page 381

PIC12(L)F1840 33.3 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 DS40001441F-page 382  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2  2011-2015 Microchip Technology Inc. DS40001441F-page 383

PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001441F-page 384  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2015 Microchip Technology Inc. DS40001441F-page 385

PIC12(L)F1840 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS40001441F-page 386  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2015 Microchip Technology Inc. DS40001441F-page 387

PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001441F-page 388  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2015 Microchip Technology Inc. DS40001441F-page 389

PIC12(L)F1840 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.10 C 1 2 2X 0.10 C TOP VIEW 0.05 C A1 C A SEATING PLANE 8X (A3) 0.05 C SIDE VIEW 0.10 C A B D2 1 2 L 0.10 C A B E2 NOTE 1 K N e 8X b e 0.10 C A B 2 BOTTOM VIEW Microchip Technology Drawing C04-254A Sheet 1 of 2 DS40001441F-page 390  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Terminals N 8 Pitch e 0.65 BSC Overall Height A 0.45 0.50 0.55 Standoff A1 0.00 0.02 0.05 Terminal Thickness A3 0.065 REF Overall Width E 3.00 BSC Exposed Pad Width E2 1.40 1.50 1.60 Overall Length D 3.00 BSC Exposed Pad Length D2 2.20 2.30 2.40 Terminal Width b 0.25 0.30 0.35 Terminal Length L 0.35 0.45 0.55 Terminal-to-Exposed-Pad K 0.20 - - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-254A Sheet 2 of 2  2011-2015 Microchip Technology Inc. DS40001441F-page 391

PIC12(L)F1840 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C X2 E Y2 X1 G1 G2 SILK SCREEN Y1 RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.65 BSC Optional Center Pad Width X2 1.60 Optional Center Pad Length Y2 2.40 Contact Pad Spacing C 2.90 Contact Pad Width (X8) X1 0.35 Contact Pad Length (X8) Y1 0.85 Contact Pad to Contact Pad (X6) G1 0.20 Contact Pad to Center Pad (X8) G2 0.30 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2254A DS40001441F-page 392  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM REVISION HISTORY OTHER PIC® DEVICES Revision A (02/2011) This section provides comparisons when migrating Original release of this data sheet. from other similar PIC® devices to the PIC12(L)F1840 family of devices. Revision B (05/2011) B.1 PIC12F683 to PIC12(L)F1840 Updated ‘Special Microcontroller Features’ and TABLE B-1: FEATURE COMPARISON ‘Low-Power Features’ sections; Updated Section 30.3, ‘DC Characteristics: PIC12(L)F1840-I/E Feature PIC12F683 PIC12(L)F1840 (Power-down)’; Updated the Packaging Information Max. Operating 20MHz 32MHz section. Speed Max. Program 2K 4K Revision C (12/2012) Memory (Words) Updated electrical specifications and added character- Max. SRAM (Bytes) 128 256 ization data. Max. EEPROM 256 256 (Bytes) Revision D (11/2013) ADC Resolution 10-bit 10-bit Updated electrical specification section; Other minor Timers (8/16-bit) 2/1 2/1 corrections. Brown-out Reset Y Y Internal Pull-ups GP<5:4>, RA<5:0> Revision E (05/2014) GP<2:0> Updated with new 8-lead UDFN 3x3x0.5mm package. Interrupt-on-change GP<5:0> RA<5:0>, Edge Selectable Updated Product Identification System page and added new specifications for new packages. Comparator 1 1 EUSART N Y Updated Equation 16-1. Updated Figures 5-7, 16-4, 19-2, 21-1, 25-24, 27-1, 27-2, 30-9. Removed Figure Extended WDT N Y 31-54. Updated Registers 12-6, 24-2. Updated Software Control Y Y Sections 15.3, 16.1.2, 17.0, 19.6, 21.0, 24.4.2, 25.6, Option of WDT/BOR 27.0, 27.1, 30.5, 30.6, 33.2. Updated Tables 3-3, 7-5, INTOSC 31 kHz - 31kHz - 12-1, 25-4, 30-5, 30-8, 30-10, 30-11, 30-14, 30-17. Frequencies 8 MHz 32MHz Revision F (4/2015) Clock Switching Y Y Capacitive Sensing N Y Added Section 30.9: High Temperature Operation in CCP/ECCP 1/0 0/1 the Electrical Specifications section. Enhanced PIC16 N Y CPU MSSPx/SSPx N Y Reference Clock N Y Data Signal N Y Modulator SR Latch N Y Voltage Reference N Y DAC N Y  2011-2015 Microchip Technology Inc. DS40001441F-page 393

PIC12(L)F1840 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following information: • Field Application Engineer (FAE) • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is • General Technical Support – Frequently Asked included in the back of this document. Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://www.microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. DS40001441F-page 394  2011-2015 Microchip Technology Inc.

PIC12(L)F1840 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC12F1840T - I/MF 301 Option Range Tape and Reel, Industrial temperature, DFN package, QTP pattern #301 Device: PIC12F1840, PIC12LF1840 b) PIC12F1840 - I/P Industrial temperature PDIP package Tape and Reel Blank = Standard packaging (tube or tray) c) PIC12F1840 - E/SN Option: T = Tape and Reel(1) Extended temperature, SOIC package Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Note 1: Tape and Reel identifier only appears in Package:(2) MF = Micro Lead Frame (DFN) 3x3x0.9mm the catalog part number description. This RF = Micro Lead Frame (UDFN) 3x3x0.5mm identifier is used for ordering purposes and P = Plastic DIP is not printed on the device package. SN = SOIC, 8-Lead Check with your Microchip Sales Office for package availability with the Tape and Reel option. Pattern: QTP, SQTP, Code or Special Requirements 2: Small form-factor packaging options may (blank otherwise) be available. Please check www.microchip.com/packaging for small- form factor package availability, or contact your local Sales Office.  2011-2015 Microchip Technology Inc. DS40001441F-page 395

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2011-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-249-7 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS40001441F-page 396  2011-2015 Microchip Technology Inc.

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