PIC12(L)F1571/2 8-Pin MCU with High-Precision 16-Bit PWMs Description: PIC12(L)F1571/2 microcontrollers combine the capabilities of 16-bit PWMs with Analog to suit a variety of applications. These devices deliver three 16-bit PWMs with independent timers for applications where high resolution is needed, such as LED lighting, stepper motors, power supplies and other general purpose applications. The core independent peripherals (16-bit PWMs, Complementary Waveform Generator), Enhanced Universal Synchronous Asynchronous Receiver Transceiver (EUSART) and Analog (ADCs, Comparator and DAC) enable closed-loop feedback and communication for use in multiple market segments. The EUSART peripheral enables the communication for applications such as LIN. Core Features: eXtreme Low-Power (XLP) Features: • C Compiler Optimized RISC Architecture • Sleep mode: 20 nA @ 1.8V, Typical • Only 49 Instructions • Watchdog Timer: 260 nA @ 1.8V, Typical • Operating Speed: • Operating Current: - DC – 32 MHz clock input - 30 A/MHz @ 1.8V, typical - 125 ns minimum instruction cycle Digital Peripherals: • Interrupt Capability • 16-Level Deep Hardware Stack • 16-Bit PWM: • Two 8-Bit Timers - Three 16-bit PWMs with independent timers • One 16-Bit Timer - Multiple Output modes (Edge-Aligned, • Three Additional 16-Bit Timers available using the Center-Aligned, Set and Toggle on 16-Bit PWMs Register Match) • Power-on Reset (POR) - User settings for phase, duty cycle, period, • Power-up Timer (PWRT) offset and polarity • Low-Power Brown-out Reset (LPBOR) - 16-bit timer capability • Programmable Watchdog Timer (WDT) up to 256s - Interrupts generated based on timer matches with Offset, Duty Cycle, Period and Phase • Programmable Code Protection registers Memory: • Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control • Up to 3.5 Kbytes Flash Program Memory - Multiple signal sources • Up to 256 Bytes Data SRAM Memory • Enhanced Universal Synchronous Asynchronous • Direct, Indirect and Relative Addressing modes Receiver Transceiver (EUSART): • High-Endurance Flash Data Memory (HEF) - Supports LIN applications - 128 bytes if nonvolatile data storage - 100k erase/write cycles Device I/O Port Features: Operating Characteristics: • Six I/Os • Operating Voltage Range: • Individually Selectable Weak Pull-ups - 1.8V to 3.6V (PIC12LF1571/2) • Interrupt-On-Change Pins Option with Edge-Selectable Option - 2.3V to 5.5V (PIC12F1571/2) • Temperature Range: - Industrial: -40°C to +85°C - Extended: -40°C to +125°C • Internal Voltage Reference module • In-Circuit Serial Programming™ (ICSP™) via Two Pins  2013-2015 Microchip Technology Inc. DS40001723D-page 1

PIC12(L)F1571/2 Analog Peripherals: Clocking Structure: • 10-Bit Analog-to-Digital Converter (ADC): • Precision Internal Oscillator: - Up to four external channels - Factory calibrated ±1%, typical - Conversion available during Sleep - Software-selectable clock speeds from • Comparator: 31 kHz to 32 MHz - Low-Power/High-Speed modes • External Oscillator Block with: - Fixed Voltage Reference at (non)inverting - Resonator modes up to 20 MHz input(s) - Two External Clock modes up to 32 MHz - Comparator outputs externally accessible • Fail-Safe Clock Monitor - Synchronization with Timer1 clock source • Digital Oscillator Input Available - Software hysteresis enable • 5-Bit Digital-to-Analog Converter (DAC): - 5-bit resolution, rail-to-rail - Positive reference selection - Unbuffered I/O pin output - Internal connections to ADCs and comparators • Voltage Reference: - Fixed voltage reference with 1.024V, 2.048V and 4.096V output levels PIC12(L)F1571/2 FAMILY TYPES h Device Data Sheet Index ogram Memory Flas(K words) Data SRAM (bytes) High-EnduranceFlash (bytes) I/O Pins 8-Bit/16-Bit Timers Comparators 16-Bit PWM 10-Bit ADC (ch) 5-Bit DAC CWG EUSART (1)Debug XLP r P PIC12(L)F1571 A 1 128 128 6 2/4(2) 1 3 4 1 1 0 I Y PIC12(L)F1572 A 2 256 128 6 2/4(2) 1 3 4 1 1 1 I Y Note 1: I – Debugging integrated on chip. 2: Three additional 16-bit timers available when not using the 16-bit PWM outputs. Data Sheet Index: (Unshaded devices are described in this document.) A DS40001723 PIC12(L)F1571/2 Data Sheet, 8-Pin Flash, 8-Bit MCU with High-Precision 16-Bit PWM. DS40001723D-page 2  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 PIN DIAGRAMS Pin Diagram – 8-Pin PDIP, SOIC, DFN, MSOP, UDFN VDD 1 8 VSS 1 2 7 7 RA5 2 5 5 7 RA0/ICSPDAT 1 1 F F L) L) RA4 3 2( 2( 6 RA1/ICSPCLK 1 1 C C RA3/MCLR/VPP 4 PI PI 5 RA2 Note: See Table1 for location of all peripheral functions. TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1571/2) N F D U N/ F D I/O SOIC/MSOP/ ADC Reference Comparator Timers PWM (2)EUSART CWG Interrupt Pull-up Basic P/ DI P n Pi 8- RA0 7 AN0 DAC1OUT C1IN+ — PWM2 TX(2) CWG1B IOC Y ICSPDAT CK(2) ICDDAT RA1 6 AN1 VREF+ C1IN0- — PWM1 RX(2) — IOC Y ICSPCLK DT(2) ICDCLK RA2 5 AN2 — C1OUT T0CKI PWM3 — CWG1FLT IOC Y — CWG1A INT RA3 4 — — — T1G(1) — — — IOC Y MCLR VPP RA4 3 AN3 — C1IN1- T1G PWM2(1) TX(1,2) CWG1B(1) IOC Y CLKOUT CK(1,2) RA5 2 — — — T1CKI PWM1(1) RX(1,2) CWG1A(1) IOC Y CLKIN DT(1,2) VDD 1 — — — — — — — — — VDD Vss 8 — — — — — — — — — VSS Note 1: Alternate pin function selected with the APFCON (Register11-1) register. 2: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 3

PIC12(L)F1571/2 Table of Contents 1.0 Device Overview..........................................................................................................................................................................7 2.0 Enhanced Mid-Range CPU........................................................................................................................................................13 3.0 Memory Organization.................................................................................................................................................................15 4.0 Device Configuration..................................................................................................................................................................41 5.0 Oscillator Module........................................................................................................................................................................47 6.0 Resets........................................................................................................................................................................................59 7.0 Interrupts....................................................................................................................................................................................69 8.0 Power-Down Mode (Sleep)........................................................................................................................................................83 9.0 Watchdog Timer (WDT).............................................................................................................................................................87 10.0 Flash Program Memory Control.................................................................................................................................................91 11.0 I/O Ports...................................................................................................................................................................................109 12.0 Interrupt-On-Change................................................................................................................................................................119 13.0 Fixed Voltage Reference (FVR)...............................................................................................................................................123 14.0 Temperature Indicator Module.................................................................................................................................................127 15.0 Analog-to-Digital Converter (ADC) Module..............................................................................................................................129 16.0 5-Bit Digital-to-Analog Converter (DAC) Module......................................................................................................................143 17.0 Comparator Module..................................................................................................................................................................147 18.0 Timer0 Module.........................................................................................................................................................................155 19.0 Timer1 Module with Gate Control.............................................................................................................................................159 20.0 Timer2 Module.........................................................................................................................................................................171 21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)...............................................................175 22.0 16-Bit Pulse-Width Modulation (PWM) Module........................................................................................................................203 23.0 Complementary Waveform Generator (CWG) Module............................................................................................................231 24.0 In-Circuit Serial Programming™ (ICSP™)...............................................................................................................................243 25.0 Instruction Set Summary..........................................................................................................................................................245 26.0 Electrical Specifications............................................................................................................................................................259 27.0 DC and AC Characteristics Graphs and Charts.......................................................................................................................283 28.0 Development Support...............................................................................................................................................................305 29.0 Packaging Information..............................................................................................................................................................309 Appendix A: Data Sheet Revision History..........................................................................................................................................327 The Microchip Web Site.....................................................................................................................................................................329 Customer Change Notification Service..............................................................................................................................................329 Customer Support..............................................................................................................................................................................329 Product Identification System.............................................................................................................................................................331 DS40001723D-page 4  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2013-2015 Microchip Technology Inc. DS40001723D-page 5

PIC12(L)F1571/2 NOTES: DS40001723D-page 6  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 1.0 DEVICE OVERVIEW 1.1 Register and Bit Naming Conventions The PIC12(L)F1571/2 devices are described within this data sheet. The block diagram of these devices is shown 1.1.1 REGISTER NAMES in Figure1-1, the available peripherals are shown in Table1-1 and the pinout descriptions are shown in When there are multiple instances of the same Table1-2. peripheral in a device, the peripheral control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance and control identifier. The TABLE 1-1: DEVICE PERIPHERAL control registers section will show just one instance of SUMMARY all the register names with an ‘x’ in the place of the 1 2 peripheral instance number. This naming convention 57 57 may also be applied to peripherals when there is only 1 1 F F one instance of that peripheral in the device to maintain Peripheral L) L) compatibility with other devices in the family that 2( 2( 1 1 contain more than one. C C PI PI 1.1.2 BIT NAMES Analog-to-Digital Converter (ADC) ● ● There are two variants for bit names: Complementary Wave Generator ● ● • Short name: Bit function abbreviation (CWG) • Long name: Peripheral abbreviation + short name Digital-to-Analog Converter (DAC) ● ● Enhanced Universal ● 1.1.2.1 Short Bit Names Synchronous/Asynchronous Short bit names are an abbreviation for the bit function. Receiver/Transmitter (EUSART) For example, some peripherals are enabled with the Fixed Voltage Reference (FVR) ● ● EN bit. The bit names shown in the registers are the Temperature Indicator ● ● short name variant. Comparators Short bit names are useful when accessing bits in C C1 ● ● programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For PWM Modules example, the enable bit, EN, in the COG1CON0 regis- PWM1 ● ● ter can be set in C programs with the instruction, PWM2 ● ● COG1CON0bits.EN = 1. PWM3 ● ● Short names are generally not useful in assembly Timers programs because the same name may be used by different peripherals in different bit positions. When this Timer0 ● ● occurs, during the include file generation, all instances Timer1 ● ● of that short bit name are appended with an Timer2 ● ● underscore, plus the name of the register in which the bit resides, to avoid naming contentions.  2013-2015 Microchip Technology Inc. DS40001723D-page 7

PIC12(L)F1571/2 1.1.2.2 Long Bit Names 1.1.3 REGISTER AND BIT NAMING EXCEPTIONS Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is 1.1.3.1 Status, Interrupt and Mirror Bits unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit Status, interrupt enables, interrupt flags and mirror bits is the COG1 prefix, G1, appended with the enable bit are contained in registers that span more than one short name, EN, resulting in the unique bit name G1EN. peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant. Long bit names are useful in both C and assembly pro- grams. For example, in C, the COG1CON0 enable bit 1.1.3.2 Legacy Peripherals can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN There are some peripherals that do not strictly adhere instruction. to these naming conventions. Peripherals that have existed for many years and are present in almost every 1.1.2.3 Bit Fields device are the exceptions. These exceptions were necessary to limit the adverse impact of the new Bit fields are two or more adjacent bits in the same conventions on legacy code. Peripherals that do register. Bit fields adhere only to the short bit naming adhere to the new convention will include a table in the convention. For example, the three Least Significant registers section indicating the long name prefix for bits of the COG1CON0 register contain the mode each peripheral instance. Peripherals that fall into the control bits. The short name for this field is MD. There exception category will not have this table. These is no long bit name variant. Bit field access is only peripherals include, but are not limited to, the following: possible in C programs. The following example demonstrates a C program instruction for setting the • EUSART COG1 to the Push-Pull mode: • MSSP COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name, MD2, and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ~(1<<G1MD1) ANDWF COG1CON0,F MOVLW 1<<G1MD2 | 1<<G1MD0 IORWF COG1CON0,F Example 2: BSF COG1CON0,G1MD2 BCF COG1CON0,G1MD1 BSF COG1CON0,G1MD0 DS40001723D-page 8  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 1-1: PIC12(L)F1571/2 BLOCK DIAGRAM Rev. 10-000039E 9/12/2013 Program Flash Memory RAM PORTA CLKOUT Timing Generation CPU CLKIN INTRC Oscillator (Note 3) MCLR Temp ADC TMR2 TMR1 TMR0 C1 DAC FVR Indicator 10-bit CWG1 PWM3 PWM2 PWM1 EUSART(4) Note 1: See applicable chapters for more information on peripherals. 2: See Table1-1 for peripherals available on specific devices. 3: See Figure2-1. 4: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 9

PIC12(L)F1571/2 TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION Input Output Name Function Description Type Type RA0/AN0/C1IN+/DACOUT/ RA0 General purpose I/O. TX(2)/CK(2)/CWG1B/PWM2/ AN0 ADC channel input. ICSPDAT/ICDDAT C1IN+ Comparator positive input. DACOUT Digital-to-Analog Converter output. TX USART asynchronous transmit. (3) (4) CK USART synchronous clock. CWG1B CWG complementary output. PWM2 PWM output. ICSPDAT ICSP™ data I/O. ICDDAT In-circuit debug data. RA1/AN1/VREF+/C1IN0-/RX(2)/ RA1 General purpose I/O. DT(2)/PWM1/ICSPCLK/ICDCLK AN1 ADC channel input. VREF+ ADC Voltage Reference input. C1IN0- Comparator negative input. RX (3) (4) USART asynchronous input. DT USART synchronous data. PWM1 PWM output. ICSPCLK ICSP programming clock. ICDCLK In-circuit debug clock. RA2/AN2/C1OUT/T0CKI/ RA2 General purpose I/O. CWG1FLT/CWG1A/PWM3/INT AN2 ADC channel input. C1OUT Comparator output. T0CKI Timer0 clock input. (3) (4) CWG1FLT Complementary Waveform Generator Fault input. CWG1A CWG complementary output. PWM3 PWM output. INT External interrupt. RA3/VPP/T1G(1)/MCLR RA3 General purpose input with IOC and WPU. VPP Programming voltage. (3) (4) T1G Timer1 gate input. MCLR Master Clear with internal pull-up. RA4/AN3/C1IN1-/T1G/TX(1,2)/ RA4 General purpose I/O. CK(1,2)/CWG1B(1)/PWM2(1)/ AN3 ADC channel input. CLKOUT C1IN1- Comparator negative input. T1G Timer1 gate input. TX (3) (4) USART asynchronous transmit. CK USART synchronous clock. CWG1B CWG complementary output. PWM2 PWM output. CLKOUT FOSC/4 output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Alternate pin function selected with the APFCON (Register11-1) register. 2: PIC12(L)F1572 only. 3: Input type is selected by the port. 4: Output type is selected by the port. DS40001723D-page 10  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION (CONTINUED) Input Output Name Function Description Type Type RA5/T1CKI/RX(1,2)/DT(1,2)/ RA5 General purpose I/O. CWG1A(1)/PWM1(1)/CLKIN T1CKI Timer1 clock input. RX USART asynchronous input. DT (3) (4) USART synchronous data. CWG1A CWG complementary output. PWM1 PWM output. CLKIN External Clock input (EC mode). VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain TTL= TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Alternate pin function selected with the APFCON (Register11-1) register. 2: PIC12(L)F1572 only. 3: Input type is selected by the port. 4: Output type is selected by the port.  2013-2015 Microchip Technology Inc. DS40001723D-page 11

PIC12(L)F1571/2 NOTES: DS40001723D-page 12  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 2.0 ENHANCED MID-RANGE CPU • Automatic Interrupt Context Saving • 16-Level Stack with Overflow and Underflow This family of devices contains an enhanced mid-range • File Select Registers 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The • Instruction Set hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. FIGURE 2-1: CORE BLOCK DIAGRAM Rev.10-000055A 7/30/2013 15 Configuration 15 DataBus 8 ProgramCounter Flash X U Program M Memory 16-LevelStack RAM (15-bit) 14 Program ProgramMemory 12 RAMAddr Bus Read(PMR) AddrMUX InstructionReg Indirect DirectAddr 7 12 Addr 5 12 BSRReg 15 FSR0Reg 15 FSR1Reg STATUSReg 8 3 MUX Power-up Instruction Timer Decodeand Power-on Control Reset 8 ALU Watchdog CLKIN Timing Timer CLKOUT Generation BrRowesne-otut WReg Internal Oscillator VDD VSS Block  2013-2015 Microchip Technology Inc. DS40001723D-page 13

PIC12(L)F1571/2 2.1 Automatic Interrupt Context 2.3 File Select Registers Saving There are two 16-bit File Select Registers (FSR). FSRs During interrupts, certain registers are automatically can access all file registers and program memory, saved in shadow registers and restored when returning which allows one Data Pointer for all memory. When an from the interrupt. This saves stack space and user FSR points to program memory, there is one additional code. See Section 7.5“Automatic Context Saving”, instruction cycle in instructions using INDF to allow the for more information. data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to 2.2 16-Level Stack with Overflow and access contiguous data larger than 80 bytes. There arealso new instructions to support the FSRs. See Underflow Section 3.6“Indirect Addressing” for more details. These devices have a hardware stack memory, 15 bits wide and 16 words deep. A Stack Overflow or Underflow 2.4 Instruction Set will set the appropriate bit (STKOVF or STKUNF) in the There are 49 instructions for the enhanced mid- PCON register, and if enabled, will cause a Software range CPU to support the features of the CPU. See Reset. See Section 3.5“Stack” for more details. Section 25.0“Instruction Set Summary” for more details. DS40001723D-page 14  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 3.0 MEMORY ORGANIZATION 3.1 Program Memory Organization These devices contain the following types of memory: The enhanced mid-range core has a 15-bit Program Counter (PC) capable of addressing a 32K x 14 program • Program Memory: memory space. Table3-1 shows the memory sizes - Configuration Words implemented. Accessing a location above these bound- - Device ID aries will cause a wraparound within the implemented - User ID memory space. The Reset vector is at 0000h and the - Flash Program Memory interrupt vector is at 0004h (see Figure3-1). • Data Memory: 3.2 High-Endurance Flash - Core Registers - Special Function Registers This device has a 128-byte section of high-endurance - General Purpose RAM Program Flash Memory (PFM) in lieu of data - Common RAM EEPROM. This area is especially well-suited for non- volatile data storage that is expected to be updated The following features are associated with access and frequently over the life of the end product. See control of program memory and data memory: Section 10.2“Flash Program Memory Overview” • PCL and PCLATH for more information on writing data to PFM. See • Stack Section 3.2.1.2“Indirect Read with FSR” for more information about using the FSR registers to read byte • Indirect Addressing data stored in PFM. TABLE 3-1: DEVICE SIZES AND ADDRESSES Program Memory Last Program Memory High-Endurance Flash Device Space (Words) Address Memory Address Range(1) PIC12(L)F1571 1,024 03FFh 0380h-03FFh PIC12(L)F1572 2,048 07FFh 0780h-07FFh Note 1: High-endurance Flash applies to the low byte of each address in the range.  2013-2015 Microchip Technology Inc. DS40001723D-page 15

PIC12(L)F1571/2 FIGURE 3-1: PROGRAM MEMORY MAP FIGURE 3-2: PROGRAM MEMORY MAP AND STACK FOR AND STACK FOR PIC12(L)F1571 PIC12(L)F1572 Rev.107-0/3000/024001D3 Rev.107-0/3000/024001C3 PC<14:0> PC<14:0> CALL, CALLW RETURN, RETLW 15 CALL, CALLW Interrupt,RETFIE RETURN, RETLW 15 Interrupt,RETFIE StackLevel0 StackLevel0 StackLevel1 StackLevel1 StackLevel15 StackLevel15 ResetVector 0000h ResetVector 0000h InterruptVector 0004h InterruptVector 0004h On-chip 0005h Program Page0 On-chip 0005h Memory 03FFh Program Page0 Memory 07FFh RollovertoPage0 0400h RollovertoPage0 0800h RollovertoPage0 7FFFh RollovertoPage0 7FFFh DS40001723D-page 16  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 3.2.1 READING PROGRAM MEMORY AS 3.2.1.2 Indirect Read with FSR DATA The program memory can be accessed as data by There are two methods of accessing constants in pro- setting bit 7 of the FSRnH register and reading the gram memory. The first method is to use tables of matching INDFn register. The MOVIW instruction will RETLW instructions. The second method is to set an place the lower eight bits of the addressed word in the FSR to point to the program memory. W register. Writes to the program memory cannot be performed via the INDFn registers. Instructions that 3.2.1.1 RETLW Instruction access the program memory via the FSR require one extra instruction cycle to complete. Example3-2 The RETLW instruction can be used to provide access demonstrates accessing the program memory via an to tables of constants. The recommended way to create FSR. such a table is shown in Example3-1. The HIGH operator will set bit<7> if a label points to a EXAMPLE 3-1: RETLW INSTRUCTION location in program memory. constants EXAMPLE 3-2: ACCESSING PROGRAM BRW ;Add Index in W to ;program counter to MEMORY VIA FSR ;select data constants RETLW DATA0 ;Index0 data DW DATA0 ;First constant RETLW DATA1 ;Index1 data DW DATA1 ;Second constant RETLW DATA2 DW DATA2 RETLW DATA3 DW DATA3 my_function ;… LOTS OF CODE… my_function MOVLW DATA_INDEX ;… LOTS OF CODE… ADDLW LOW constants MOVLW DATA_INDEX MOVWF FSR1L call constants MOVLW HIGH constants ;MSb is set ;… THE CONSTANT IS IN W automatically MOVWF FSR1H The BRW instruction makes this type of table very BTFSC STATUS,C ;carry from ADDLW? simple to implement. If your code must remain portable INCF FSR1H,f ;yes with previous generations of microcontrollers, then the MOVIW 0[FSR1] BRW instruction is not available, so the older table read ;THE PROGRAM MEMORY IS IN W method must be used.  2013-2015 Microchip Technology Inc. DS40001723D-page 17

PIC12(L)F1571/2 3.3 Data Memory Organization 3.3.1 CORE REGISTERS The data memory is partitioned in 32 memory banks The core registers contain the registers that directly with 128 bytes in a bank. Each bank consists of affect the basic operation. The core registers occupy (Figure3-3): the first 12 addresses of every data memory bank (addresses: x00h/x08h through x0Bh/x8Bh). These • 12 Core Registers registers are listed below in Table3-2. For detailed • 20 Special Function Registers (SFR) information, see Table3-9. • Up to 80 bytes of General Purpose RAM (GPR) • 16 bytes of Common RAM TABLE 3-2: CORE REGISTERS The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented Addresses BANKx memory will read as ‘0’. All data memory can be x00h or x80h INDF0 accessed either directly (via instructions that use the file x01h or x81h INDF1 registers) or indirectly via the two File Select Registers x02h or x82h PCL (FSR). See Section 3.6“Indirect Addressing” for x03h or x83h STATUS more information. x04h or x84h FSR0L Data memory uses a 12-bit address. The upper five bits x05h or x85h FSR0H of the address define the bank address and the lower x06h or x86h FSR1L seven bits select the registers/RAM in that bank. x07h or x87h FSR1H x08h or x88h BSR x09h or x89h WREG x0Ah or x8Ah PCLATH x0Bh or x8Bh INTCON DS40001723D-page 18  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 3.3.1.1 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register The STATUS register, shown in Register3-1, contains: as ‘000u u1uu’ (where u = unchanged). • The arithmetic status of the ALU It is recommended, therefore, that only BCF, BSF, • The Reset status SWAPF and MOVWF instructions are used to alter the The STATUS register can be the destination for any STATUS register, because these instructions do not instruction, like any other register. If the STATUS affect any Status bits. For other instructions not affecting register is the destination for an instruction that affects any Status bits, refer to Section 25.0“Instruction Set the Z, DC or C bits, then the write to these three bits is Summary”). disabled. These bits are set or cleared according to the Note1: The C and DC bits operate as Borrow device logic. Furthermore, the TO and PD bits are not and Digit Borrow out bits, respectively, in writable. Therefore, the result of an instruction with the subtraction. STATUS register as destination may be different than intended. REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-Down bit 1 = After power-down or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2013-2015 Microchip Technology Inc. DS40001723D-page 19

PIC12(L)F1571/2 3.3.2 SPECIAL FUNCTION REGISTER FIGURE 3-3: BANKED MEMORY PARTITIONING The Special Function Registers are registers used by the application to control the desired operation of Rev.10-000041A peripheral functions in the device. The Special Function 7/30/2013 Registers occupy the 20 bytes after the core registers of every data memory bank (addresses: x0Ch/x8Ch 7-bitBankOffset MemoryRegion through x1Fh/x9Fh). The registers associated with the 00h operation of the peripherals are described in the CoreRegisters appropriate peripheral chapter of this data sheet. (12bytes) 0Bh 3.3.3 GENERAL PURPOSE RAM 0Ch There are up to 80 bytes of GPR in each data memory SpecialFunctionRegisters bank. The Special Function Registers occupy the (20bytesmaximum) 20bytes after the core registers of every data memory 1Fh bank (addresses: x0Ch/x8Ch through x1Fh/x9Fh). 20h 3.3.3.1 Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplifyaccess to large memory structures. See Section 3.6.2 “Linear Data Memory” for more GeneralPurposeRAM information. (80bytesmaximum) 3.3.4 COMMON RAM There are 16 bytes of common RAM accessible from all banks. 3.3.5 DEVICE MEMORY MAPS The memory maps for PIC12(L)F1571/2 are as shown 6Fh in Table3-3 through Table3-8. 70h CommonRAM (16bytes) 7Fh DS40001723D-page 20  2013-2015 Microchip Technology Inc.

 TABLE 3-3: PIC12(L)F1571 MEMORY MAP, BANK 0-7 2 0 1 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 3 -20 000h 080h 100h 180h 200h 280h 300h 380h 1 5 M Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers ic (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) ro c 00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh h ip 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA T e 00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh — c hn 00Eh — 08Eh — 10Eh — 18Eh — 20Eh — 28Eh — 30Eh — 38Eh — o lo 00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh — g y 010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h — Inc 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h — 291h — 311h — 391h IOCAP . 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h — 292h — 312h — 392h IOCAN 013h PIR3 093h PIE3 113h — 193h PMDATL 213h — 293h — 313h — 393h IOCAF 014h — 094h — 114h — 194h PMDATH 214h — 294h — 314h — 394h — 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h — 295h — 315h — 395h — 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h — 296h — 316h — 396h — 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h — 297h — 317h — 397h — 018h T1CON 098h OSCTUN E 118h DACxCON0 198h — 218h — 298h — 318h — 398h — 019h T1GCON 099h OSCCON 119h DACxCON1 199h — 219h — 299h — 319h — 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah — 21Ah — 29Ah — 31Ah — 39Ah — 01Bh PR2 09Bh ADRESL 11Bh — 19Bh — 21Bh — 29Bh — 31Bh — 39Bh — 01Ch T2CON 09Ch ADRESH 11Ch — 19Ch — 21Ch — 29Ch — 31Ch — 39Ch — 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh — 21Dh — 29Dh — 31Dh — 39Dh — 01Eh — 09Eh ADCON1 11Eh — 19Eh — 21Eh — 29Eh — 31Eh — 39Eh — 01Fh — 09Fh ADCON2 11Fh — 19Fh — 21Fh — 29Fh — 31Fh — 39Fh — 020h 0A0h General Purpose 120h 1A0h 220h 2A0h 320h 3A0h Register General Purpose 0BFh 48 Bytes Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented P Register 0C0h Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ I 80 Bytes Unimplemented C Read as ‘0’ 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh 1 070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h 2 Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM ( Common RAM (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses L D 70h-7Fh) 70h-7Fh) 70h-7Fh) 70h-7Fh) 70h-7Fh) 70h-7Fh) 70h-7Fh) S4 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh )F 0 0 0 Legend: = Unimplemented data memory locations, read as ‘0’. 1 1 7 Note1: PIC12F1571 only. 5 2 3 D 7 -pa 1 g e / 2 2 1

D TABLE 3-4: PIC12(L)F1572 MEMORY MAP, BANK 0-7 P S 400 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 IC 0 17 000h 080h 100h 180h 200h 280h 300h 380h 1 2 3D Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers 2 -p (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) ( age 00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh L 22 00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA )F 00Dh — 08Dh — 10Dh — 18Dh — 20Dh — 28Dh — 30Dh — 38Dh — 1 00Eh — 08Eh — 10Eh — 18Eh — 20Eh — 28Eh — 30Eh — 38Eh — 5 00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh — 7 010h — 090h — 110h — 190h — 210h — 290h — 310h — 390h — 1 011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h — 291h — 311h — 391h IOCAP / 012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h — 292h — 312h — 392h IOCAN 2 013h PIR3 093h PIE3 113h — 193h PMDATL 213h — 293h — 313h — 393h IOCAF 014h — 094h — 114h — 194h PMDATH 214h — 294h — 314h — 394h — 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h — 295h — 315h — 395h — 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h — 296h — 316h — 396h — 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h — 297h — 317h — 397h — 018h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h — 318h — 398h — 019h T1GCON 099h OSCCON 119h DAC1CON1 199h RCREG 219h — 299h — 319h — 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah — 29Ah — 31Ah — 39Ah — 01Bh PR2 09Bh ADRESL 11Bh — 19Bh SPBRG 21Bh — 29Bh — 31Bh — 39Bh — 01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch — 31Ch — 39Ch — 01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh — 31Dh — 39Dh — 01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh — 31Eh — 39Eh — 01Fh — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh — 020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h General General General Purpose Purpose Purpose Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented  Register Register Register Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 20 80 Bytes 80 Bytes 80 Bytes 1 3 -2 06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh 0 1 070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h 5 M Accesses Accesses Accesses Accesses Accesses Accesses Accesses ic Common RAM 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh ro ch 07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh ip T Legend: = Unimplemented data memory locations, read as ‘0’. e ch Note1: PIC12F1572 only. n o lo g y In c .

 TABLE 3-5: PIC12(L)F1571/2 MEMORY MAP, BANK 8-23 2 0 1 BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15 3 -20 400h Core Registers 480h Core Registers 500h Core Registers 580h Core Registers 600h Core Registers 680h Core Registers 700h Core Registers 780h Core Registers 15 40Bh (Table3-2) 48Bh (Table3-2) 50Bh (Table3-2) 58Bh (Table3-2) 60Bh (Table3-2) 68Bh (Table3-2) 70Bh (Table3-2) 78Bh (Table3-2) M ic 40Ch — 48Ch — 50Ch — 58Ch — 60Ch — 68Ch — 70Ch — 78Ch — ro 40Dh — 48Dh — 50Dh — 58Dh — 60Dh — 68Dh — 70Dh — 78Dh — ch 40Eh — 48Eh — 50Eh — 58Eh — 60Eh — 68Eh — 70Eh — 78Eh — ip T 40Fh — 48Fh — 50Fh — 58Fh — 60Fh — 68Fh — 70Fh — 78Fh — e 410h — 490h — 510h — 590h — 610h — 690h — 710h — 790h — c h 411h — 491h — 511h — 591h — 611h — 691h CWG1DBR 711h — 791h — n o 412h — 492h — 512h — 592h — 612h — 692h CWG1DBF 712h — 792h — lo g 413h — 493h — 513h — 593h — 613h — 693h CWG1CON0 713h — 793h — y In 414h — 494h — 514h — 594h — 614h — 694h CWG1CON1 714h — 794h — c 415h — 495h — 515h — 595h — 615h — 695h CWG1CON2 715h — 795h — . 416h — 496h — 516h — 596h — 616h — 696h — 716h — 796h — 417h — 497h — 517h — 597h — 617h — 697h — 717h — 797h — 418h — 498h — 518h — 598h — 618h — 698h — 718h — 798h — 419h — 499h — 519h — 599h — 619h — 699h — 719h — 799h — 41Ah — 49Ah — 51Ah — 59Ah — 61Ah — 69Ah — 71Ah — 79Ah — 41Bh — 49Bh — 51Bh — 59Bh — 61Bh — 69Bh — 71Bh — 79Bh — 41Ch — 49Ch — 51Ch — 59Ch — 61Ch — 69Ch — 71Ch — 79Ch — 41Dh — 49Dh — 51Dh — 59Dh — 61Dh — 69Dh — 71Dh — 79Dh — 41Eh — 49Eh — 51Eh — 59Eh — 61Eh — 69Eh — 71Eh — 79Eh — 41Fh — 49Fh — 51Fh — 59Fh — 61Fh — 69Fh — 71Fh — 79Fh — 420h 4A0h 520h 5A0h 620h 6A0h 720h 7A0h Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh 470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh P 47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh I C BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23 1 800h 880h 900h 980h A00h A80h B00h B80h 2 Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers ( (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) L D 80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh S 80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch ) 4 F 00 Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented 0 Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ 1 1 72 86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh 5 3D 870h 8F0h 970h 9F0h A70h AF0h B70h BF0h 7 -pag A7c0che-s7sFehs A7c0che-s7sFehs A7c0che-s7sFehs A7c0che-s7sFehs A7c0che-s7sFehs A7c0che-s7sFehs A7c0che-s7sFehs A7c0che-s7sFehs 1 e 2 87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh /2 3 Legend: = Unimplemented data memory locations, read as ‘0’.

D TABLE 3-6: PIC12(L)F1571/2 MEMORY MAP, BANK 24-31 P S 400 BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31 IC 0 1 C00h C80h D00h D80h E00h E80h F00h F80h 7 1 2 Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers 3D (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) (Table3-2) 2 -p C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh F8Bh ( ag C0Ch — C8Ch — D0Ch — D8Ch E0Ch — E8Ch — F0Ch — F8Ch L e 2 C0Dh — C8Dh — D0Dh — E0Dh — E8Dh — F0Dh — ) 4 C0Eh — C8Eh — D0Eh — E0Eh — E8Eh — F0Eh — F C0Fh — C8Fh — D0Fh — E0Fh — E8Fh — F0Fh — 1 C10h — C90h — D10h — E10h — E90h — F10h — 5 C11h — C91h — D11h — E11h — E91h — F11h — 7 C12h — C92h — D12h — E12h — E92h — F12h — 1 C13h — C93h — D13h — E13h — E93h — F13h — / C14h — C94h — D14h — E14h — E94h — F14h — 2 C15h — C95h — D15h — E15h — E95h — F15h — C16h — C96h — D16h — E16h — E96h — F16h — C17h — C97h — D17h — E17h — E97h — F17h — C18h — C98h — D18h — See Table3-7 for E18h — E98h — F18h — See Table3-7 for Register Mapping Register Mapping C19h — C99h — D19h — Details E19h — E99h — F19h — Details C1Ah — C9Ah — D1Ah — E1Ah — E9Ah — F1Ah — C1Bh — C9Bh — D1Bh — E1Bh — E9Bh — F1Bh — C1Ch — C9Ch — D1Ch — E1Ch — E9Ch — F1Ch — C1Dh — C9Dh — D1Dh — E1Dh — E9Dh — F1Dh — C1Eh — C9Eh — D1Eh — E1Eh — E9Eh — F1Eh — C1Fh — C9Fh — D1Fh — E1Fh — E9Fh — F1Fh — C20h CA0h D20h E20h EA0h F20h Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh  C70h CF0h D70h DF0h E70h EF0h F70h FF0h 2 Accesses Accesses Accesses Accesses Accesses Accesses Accesses Accesses 01 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 70h-7Fh 3 -2 CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh 0 1 5 Legend: = Unimplemented data memory locations, read as ‘0’. M ic ro c h ip T e c h n o lo g y In c .

PIC12(L)F1571/2 TABLE 3-7: PIC12(L)F1571/2 MEMORY TABLE 3-8: PIC12(L)F1571/2 MEMORY MAP, BANK 27 MAP, BANK 31 Bank 31 Bank 31 D8Ch — F8Ch D8Dh — D8Eh PWMEN Unimplemented D8Fh PWMLD Read as ‘0’ D90h PWMOUT D91h PWM1PHL FE3h D92h PWM1PHH FE4h STATUS_SHAD D93h PWM1DCL FE5h WREG_SHAD D94h PWM1DCH FE6h BSR_SHAD D95h PWM1PRL FE7h PCLATH_SHAD D96h PWM1PRH FE8h FSR0L_SHAD D97h PWM1OFL FE9h FSR0H_SHAD D98h PWM1OFH FEAh FSR1L_SHAD D99h PWM1TMRL FEBh FSR1H_SHAD D9Ah PWM1TMRH FECh — D9Bh PWM1CON FEDh STKPTR D9Ch PWM1INTE FEEh TOSL D9Dh PWM1INTF FEFh TOSH D9Eh PWM1CLKCON D9Fh PWM1LDCON DA0h PWM1OFCON Legend: = Unimplemented data memory locations, DA1h PWM2PHL read as ‘0’. DA2h PWM2PHH DA3h PWM2DCL DA4h PWM2DCH DA5h PWM2PRL DA6h PWM2PRH DA7h PWM2OFL DA8h PWM2OFH DA9h PWM2TMRL DAAh PWM2TMRH DABh PWM2CON DACh PWM2INTE DADh PWM2INTF DAEh PWM2CLKCON DAFh PWM2LDCON DB0h PWM2OFCON DB1h PWM3PHL DB2h PWM3PHH DB3h PWM3DCL DB4h PWM3DCH DB5h PWM2PRL DB6h PWM3PRH DB7h PWM3OFL DB8h PWM3OFH DB9h PWM3TMRL DBAh PWM3TMRH DBBh PWM3CON DBCh PWM3INTE DBDh PWM3INTF DBEh PWM3CLKCON DBFh PWM3LDCON DC0h PWM3OFCON DC1h — DEFh Legend: = Unimplemented data memory locations, read as ‘0’.  2013-2015 Microchip Technology Inc. DS40001723D-page 25

PIC12(L)F1571/2 3.3.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table3-9 can be addressed from any bank. TABLE 3-9: CORE FUNCTION REGISTERS SUMMARY Value on Value on All Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR Other Resets Bank 0-31 x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory INDF0 xxxx xxxx uuuu uuuu x80h (not a physical register) x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory INDF1 xxxx xxxx uuuu uuuu x81h (not a physical register) x02h or PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x82h x03h or STATUS — — — TO PD Z DC C ---1 1000 ---q quuu x83h x04h or FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x84h x05h or FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x85h x06h or FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x86h x07h or FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x87h x08h or BSR — — — BSR<4:0> ---0 0000 ---0 0000 x88h x09h or WREG Working Register 0000 0000 uuuu uuuu x89h x0Ah or PCLATH — Write Buffer for the Upper 7 bits of the Program Counter -000 0000 -000 0000 x8Ah x0Bh or INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 x8Bh Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented, read as ‘0’; r = reserved. Shaded locations are unimplemented, read as ‘0’. DS40001723D-page 26  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR Resets Bank 0 00Ch PORTA — — RA<5:0> --xx xxxx --xx xxxx 00Dh — Unimplemented — — 00Eh — Unimplemented — — 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF RCIF(2) TXIF(2) — — TMR2IF TMR1IF 0000 --00 0000 --00 012h PIR2 — — C1IF — — — — — --0- ---- --0- ---- 013h PIR3 — PWM3IF PWM2IF PWM1IF — — — — -000 ---- -000 ---- 014h — Unimplemented — — 015h TMR0 Holding Register for the 8-Bit Timer0 Count xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Count xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Count xxxx xxxx uuuu uuuu 018h T1CON TMR1CS<1:0> T1CKPS<1:0> — T1SYNC — TMR1ON 0000 -0-0 uuuu -u-u 019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu DONE 01Ah TMR2 Timer2 Module Register 0000 0000 0000 0000 01Bh PR2 Timer2 Period Register 1111 1111 1111 1111 01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000 01Dh — Unimplemented — — 01Eh — Unimplemented — — 01Fh — Unimplemented — — Bank 1 08Ch TRISA — — TRISA<5:4> —(2) TRISA<2:0> --11 1111 --11 1111 08Dh — Unimplemented — — 08Eh — Unimplemented — — 08Fh — Unimplemented — — 090h — Unimplemented — — 091h PIE1 TMR1GIE ADIE RCIE(2) TXIE(2) — — TMR2IE TMR1IE 0000 --00 0000 --00 092h PIE2 — — C1IE — — — — — --0- ---- --0- ---- 093h PIE3 — PWM3IE PWM2IE PWM1IE — — — — -000 ---- -000 ---- 094h — Unimplemented — — 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111 096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu 097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110 098h OSCTUNE — — TUN<5:0> --00 0000 --00 0000 099h OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 0011 1-00 0011 1-00 09Ah OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS -0q0 0q00 -qqq qqqq 09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu 09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu 09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000 09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00 09Fh ADCON2 TRIGSEL<3:0> — — — — 0000 ---- 0000 ---- Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only. 2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.  2013-2015 Microchip Technology Inc. DS40001723D-page 27

PIC12(L)F1571/2 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR Resets Bank 2 10Ch LATA — — LATA<5:4> — LATA<2:0> --xx -xxx --uu -uuu 10Dh — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 0000 -100 0000 -100 112h CM1CON1 C1INTP C1INTN C1PCH<1:0> — C1NCH<2:0> 0000 -000 0000 -000 113h — Unimplemented — — 114h — Unimplemented — — 115h CMOUT — — — — — — — MC1OUT ---- ---0 ---- ---0 116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 0q00 0000 0q00 0000 118h DAC1CON0 DACEN — DACOE — DACPSS<1:0> — — 0-0- 00-- 0-0- 00-- 119h DAC1CON1 — — — DACR<4:0> ---0 0000 ---0 0000 11Ah to — Unimplemented — — 11Ch 11Dh APFCON RXDTSEL CWGASEL CWGBSEL — T1GSEL TXCKSEL P2SEL P1SEL 000- 0000 000- 0000 11Eh — Unimplemented — — 11Fh — Unimplemented — — Bank 3 18Ch ANSELA — — — ANSA4 — ANSA<2:0> ---1 -111 ---1 -111 18Dh — Unimplemented — — 18Eh — Unimplemented — — 18Fh — Unimplemented — — 190h — Unimplemented — — 191h PMADRL Flash Program Memory Address Register Low Byte 0000 0000 0000 0000 192h PMADRH —(3) Flash Program Memory Address Register High Byte 1000 0000 1000 0000 193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu 194h PMDATH — — Flash Program Memory Read Data Register High Byte --xx xxxx --uu uuuu 195h PMCON1 —(3) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000 196h PMCON2 Flash Program Memory Control Register 2 0000 0000 0000 0000 197h VREGCON(1) — — — — — — VREGPM Reserved ---- --01 ---- --01 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 0000 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only. 2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’. DS40001723D-page 28  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR Resets Bank 4 20Ch WPUA — — WPUA<5:0> --11 1111 --11 1111 20Dh — Unimplemented — — 20Eh to — Unimplemented — — 21Fh Bank 5 28Ch ODCONA — — ODA<5:4> — ODA<2:0> --11 -111 --11 -111 28Dh to — Unimplemented — — 29Fh Bank 6 30Ch SLRCONA — — SLRA<5:4> — SLRA<2:0> --11 -111 --11 -111 30Dh to — Unimplemented — — 31Fh Bank 7 38Ch INLVLA — — INLVLA<5:0> --11 1111 --11 1111 38Dh to — Unimplemented — — 390h 391h IOCAP — — IOCAP<5:0> --00 0000 --00 0000 392h IOCAN — — IOCAN<5:0> --00 0000 --00 0000 393h IOCAF — — IOCAF<5:0> --00 0000 --00 0000 394h to — Unimplemented — — 39Fh Bank 8 40Ch to — Unimplemented — — 41Fh Bank 9 48Ch to — Unimplemented — — 49Fh Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only. 2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.  2013-2015 Microchip Technology Inc. DS40001723D-page 29

PIC12(L)F1571/2 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR Resets Bank 10 50Ch to — Unimplemented — — 51Fh Bank 11 58Ch to — Unimplemented — — 59Fh Bank 12 60Ch to — Unimplemented — — 61Fh Bank 13 68Ch to — Unimplemented — — 690h 691h CWG1DBR — — CWG1DBR<5:0> --00 0000 --00 0000 692h CWG1DBF — — CWG1DBF<5:0> --xx xxxx --xx xxxx 693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 0000 0--0 0000 0--0 694h CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0> — G1IS<2:0> 0000 -000 0000 -000 695h CWG1CON2 G1ASE G1ARSEN — — — G1ASDSC1 G1ASDSFLT — 00-- -00- 00-- -00- 696h to — Unimplemented — — 69Fh Banks 14-26 x0Ch/ x8Ch — — Unimplemented — — x1Fh/ x9Fh Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only. 2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’. DS40001723D-page 30  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR Resets Bank 27 D8Ch — Unimplemented — — D8Dh — Unimplemented — — D8Eh PWMEN — — — — — PWM3EN_A PWM2EN_A PWM1EN_A ---- -000 ---- -000 D8Fh PWMLD — — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A ---- -000 ---- -000 D90h PWMOUT — — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A ---- -000 ---- -000 D91h PWM1PHL PH<7:0> xxxx xxxx uuuu uuuu D92h PWM1PHH PH<15:8> xxxx xxxx uuuu uuuu D93h PWM1DCL DC<7:0> xxxx xxxx uuuu uuuu D94h PWM1DCH DC<15:8> xxxx xxxx uuuu uuuu D95h PWM1PRL PR<7:0> xxxx xxxx uuuu uuuu D96h PWM1PRH PR<15:8> xxxx xxxx uuuu uuuu D97h PWM1OFL OF<7:0> xxxx xxxx uuuu uuuu D98h PWM1OFH OF<15:8> xxxx xxxx uuuu uuuu D99h PWM1TMRL TMR<7:0> xxxx xxxx uuuu uuuu D9Ah PWM1TMRH TMR<15:8> xxxx xxxx uuuu uuuu D9Bh PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL PWM1MODE<1:0> — — 0000 00-- 0000 00-- D9Ch PWM1INTE — — — — PWM1OFIE PWM1PHIE PWM1DCIE PWM1PRIE ---- 000 ---- 000 D9Dh PWM1INTF — — — — PWM1OFIF PWM1PHIF PWM1DCIF PWM1PRIF ---- 000 ---- 000 D9Eh PWM1CLKCON — PWM1PS<2:0> — — PWM1CS<1:0> -000 -000 -000 --00 D9Fh PWM1LDCON PWM1LDA PWM1LDT — — — — PWM1LDS<1:0> 00-- -000 00-- --00 DA0h PWM1OFCON — PWM1OFM<1:0> PWM1OFO — — PWM1OFS<1:0> -000 -000 -000 --00 DA1h PWM2PHL PH<7:0> xxxx xxxx uuuu uuuu DA2h PWM2PHH PH<15:8> xxxx xxxx uuuu uuuu DA3h PWM2DCL DC<7:0> xxxx xxxx uuuu uuuu DA4h PWM2DCH DC<15:8> xxxx xxxx uuuu uuuu DA5h PWM2PRL PR<7:0> xxxx xxxx uuuu uuuu DA6h PWM2PRH PR<15:8> xxxx xxxx uuuu uuuu DA7h PWM2OFL OF<7:0> xxxx xxxx uuuu uuuu DA8h PWM2OFH OF<15:8> xxxx xxxx uuuu uuuu DA9h PWM2TMRL TMR<7:0> xxxx xxxx uuuu uuuu DAAh PWM2TMRH TMR<15:8> xxxx xxxx uuuu uuuu DABh PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL PWM2MODE<1:0> — — 0000 00-- 0000 00-- DACh PWM2INTE — — — — PWM2OFIE PWM2PHIE PWM2DCIE PWM2PRIE ---- 000 ---- 000 DADh PWM2INTF — — — — PWM2OFIF PWM2PHIF PWM2DCIF PWM2PRIF ---- 000 ---- 000 DAEh PWM2CLKCON — PWM2PS<2:0> — — PWM2CS<1:0> -000 -000 -000 --00 DAFh PWM2LDCON PWM2LDA PWM2LDT — — — — PWM2LDS<1:0> 00-- -000 00-- --00 Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only. 2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.  2013-2015 Microchip Technology Inc. DS40001723D-page 31

PIC12(L)F1571/2 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR Resets Bank 27 (Continued) DB0h PWM2OFCON — PWM2OFM<1:0> PWM2OFO — — PWM2OFS<1:0> -000 -000 -000 --00 DB1h PWM3PHL PH<7:0> xxxx xxxx uuuu uuuu DB2h PWM3PHH PH<15:8> xxxx xxxx uuuu uuuu DB3h PWM3DCL DC<7:0> xxxx xxxx uuuu uuuu DB4h PWM3DCH DC<15:8> xxxx xxxx uuuu uuuu DB5h PWM3PRL PR<7:0> xxxx xxxx uuuu uuuu DB6h PWM3PRH PR<15:8> xxxx xxxx uuuu uuuu DB7h PWM3OFL OF<7:0> xxxx xxxx uuuu uuuu DA8h PWM3OFH OF<15:8> xxxx xxxx uuuu uuuu DA9h PWM3TMRL TMR<7:0> xxxx xxxx uuuu uuuu DBAh PWM3TMRH TMR<15:8> xxxx xxxx uuuu uuuu DBBh PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL PWM3MODE<1:0> — — 0000 00-- 0000 00-- DBCh PWM3INTE — — — — PWM3OFIE PWM3PHIE PWM3DCIE PWM3PRIE ---- 000 ---- 000 DBDh PWM3INTF — — — — PWM3OFIF PWM3PHIF PWM3DCIF PWM3PRIF ---- 000 ---- 000 DBEh PWM3CLKCON — PWM3PS<2:0> — — PWM3CS<1:0> -000 -000 -000 --00 DBFh PWM3LDCON PWM3LDA PWM3LDT — — — — PWM3LDS<1:0> 00-- -000 00-- --00 DC0h PWM3OFCON — PWM3OFM<1:0> PWM3OFO — — PWM3OFS<1:0> -000 -000 -000 --00 Bank 28-30 58Ch to — Unimplemented — — 59Fh Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only. 2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’. DS40001723D-page 32  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on Value on Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR, BOR Resets Bank 31 F8Ch — — Unimplemented — — FE3h FE4h STATUS_ — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow xxxx xxxx uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEAh FSR1L_ Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu SHAD FEBh FSR1H_ Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FECh — Unimplemented — — FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111 FEEh TOSL Top-of-Stack Low Byte xxxx xxxx uuuu uuuu FEFh TOSH — Top-of-Stack High Byte -xxx xxxx -uuu uuuu Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented; r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC12F1571/2 only. 2: PIC12(L)F1572 only. 3: Unimplemented, read as ‘1’.  2013-2015 Microchip Technology Inc. DS40001723D-page 33

PIC12(L)F1571/2 3.4 PCL and PCLATH 3.4.2 COMPUTED GOTO The Program Counter (PC) is 15 bits wide. The low byte A computed GOTO is accomplished by adding an offset to comes from the PCL register, which is a readable and the Program Counter (ADDWF PCL). When performing a writable register. The high byte (PC<14:8>) is not directly table read using a computed GOTO method, care should readable or writable and comes from PCLATH. On any be exercised if the table location crosses a PCL memory Reset, the PC is cleared. Figure3-4 shows the five boundary (each 256-byte block). Refer to Application situations for the loading of the PC. Note AN556, “Implementing a Table Read” (DS00556). 3.4.3 COMPUTED FUNCTION CALLs FIGURE 3-4: LOADING OF PC IN DIFFERENT SITUATIONS A computed function CALL allows programs to maintain tables of functions and provides another way to execute state machines or look-up tables. When per- Rev.10-000042A 7/30/2013 forming a table read using a computed function CALL, 14 PCH PCL 0 Instruction care should be exercised if the table location crosses a PC withPCLas PCL memory boundary (each 256-byte block). Destination 7 8 If using the CALL instruction, the PCH<2:0> and PCL 6 0 PCLATH ALUresult registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed CALLs by 14 PCH PCL 0 GOTO, PC CALL combining PCLATH and W to form the destination address. A computed CALLW is accomplished by 4 11 6 0 loading the W register with the desired address and PCLATH OPCODE<10:0> executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 14 PCH PCL 0 PC CALLW 3.4.4 BRANCHING The branching instructions add an offset to the PC. 7 8 6 0 This allows relocatable code and code that crosses PCLATH W page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch 14 PCH PCL 0 the next instruction in both cases. When using either PC BRW branching instruction, a PCL memory boundary may be 15 crossed. PC+W If using BRW, load the W register with the desired 14 PCH PCL 0 unsigned address and execute BRW. The entire PC will PC BRA be loaded with the address, PC + 1 + W. 15 If using BRA, the entire PC will be loaded with PC + 1+, PC+OPCODE<8:0> the signed value of the operand of the BRA instruction. 3.4.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the Program Counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the Program Counter will change to the values contained in the PCLATH register and those being written to the PCL register. DS40001723D-page 34  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 3.5 Stack 3.5.1 ACCESSING THE STACK All devices have a 16-level x 15-bit wide hardware The stack is available through the TOSH, TOSL and stack (refer to Figures3-5 through3-8). The stack STKPTR registers. STKPTR is the current value of the space is not part of either program or data space. The Stack Pointer. The TOSH:TOSL register pair points to PC is PUSHed onto the stack when CALL or CALLW the top of the stack. Both registers are read/writable. instructions are executed, or an interrupt causes a TOS is split into TOSH and TOSL due to the 15-bit size branch. The stack is POPed in the event of a RETURN, of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then RETLW or RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. read/write to TOSH:TOSL. The STKPTR is 5 bits to allow detection of overflow and underflow. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0’ (Configuration Words). This Note: Care should be taken when modifying the means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled. times, the seventeenth PUSH overwrites the value that During normal program operation, CALL, CALLW and was stored from the first PUSH. The eighteenth PUSH interrupts will increment STKPTR while RETLW, overwrites the second PUSH (and so on). The RETURN and RETFIE will decrement STKPTR. At any STKOVF and STKUNF flag bits will be set on an time, the STKPTR can be inspected to see how much overflow/underflow, regardless of whether the Reset is stack is left. The STKPTR always points at the currently enabled. used place on the stack. Therefore, a CALL or CALLW Note1: There are no instructions/mnemonics will increment the STKPTR and then write the PC, and called PUSH or POP. These are actions a return will unload the PC and then decrement the that occur from the execution of the STKPTR. CALL, CALLW, RETURN, RETLW and Reference Figure3-5 through Figure3-8 for examples RETFIE instructions or the vectoring to of accessing the stack. an interrupt address. FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 Rev.10-000043A 7/30/2013 StackResetDisabled TOSH:TOSL 0x0F STKPTR=0x1F (STVREN=0) 0x0E 0x0D 0x0C 0x0B InitialStackConfiguration: 0x0A AfterReset,thestackisempty.The 0x09 emptystackisinitializedsotheStack 0x08 Pointerispointingat0x1F.IftheStack Overflow/UnderflowResetisenabled,the 0x07 TOSH/TOSL register will return ‘0’.Ifthe 0x06 StackOverflow/UnderflowResetis disabled,theTOSH/TOSLregisterwill 0x05 returnthecontentsofstackaddress 0x04 0x0F. 0x03 0x02 0x01 0x00 StackResetEnabled TOSH:TOSL 0x1F 0x0000 STKPTR=0x1F (STVREN=1)  2013-2015 Microchip Technology Inc. DS40001723D-page 35

PIC12(L)F1571/2 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 Rev.10-000043B 7/30/2013 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 Thisfigureshowsthestackconfiguration afterthefirstCALL orasingleinterrupt. 0x08 IfaRETURNinstructionisexecuted,the 0x07 returnaddresswillbeplacedinthe ProgramCounterandtheStackPointer 0x06 decrementedtotheemptystate(0x1F). 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 ReturnAddress STKPTR=0x00 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 Rev.10-000043C 7/30/2013 0x0F 0x0E 0x0D 0x0C AftersevenCALLsorsixCALLsandan 0x0B interrupt,thestacklookslikethefigureon theleft.AseriesofRETURNinstructionswill 0x0A repeatedlyplacethereturnaddressesinto 0x09 theProgramCounterandpopthestack. 0x08 0x07 TOSH:TOSL 0x06 ReturnAddress STKPTR=0x06 0x05 ReturnAddress 0x04 ReturnAddress 0x03 ReturnAddress 0x02 ReturnAddress 0x01 ReturnAddress 0x00 ReturnAddress DS40001723D-page 36  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 Rev.10-000043D 7/30/2013 0x0F ReturnAddress 0x0E ReturnAddress 0x0D ReturnAddress 0x0C ReturnAddress 0x0B ReturnAddress 0x0A ReturnAddress Whenthestackisfull,thenextCALLor aninterruptwillsettheStackPointerto 0x09 ReturnAddress 0x10.Thisisidenticaltoaddress0x00so 0x08 ReturnAddress thestackwillwrapandoverwritethe returnaddressat0x00.IftheStack 0x07 ReturnAddress Overflow/UnderflowResetisenabled,a 0x06 ReturnAddress Resetwilloccurandlocation0x00will notbeoverwritten. 0x05 ReturnAddress 0x04 ReturnAddress 0x03 ReturnAddress 0x02 ReturnAddress 0x01 ReturnAddress TOSH:TOSL 0x00 ReturnAddress STKPTR=0x10 3.5.2 OVERFLOW/UNDERFLOW RESET 3.6 Indirect Addressing If the STVREN bit in the Configuration Words is The INDFn registers are not physical registers. Any programmed to ‘1’, the device will be reset if the stack instruction that accesses an INDFn register actually is PUSHed beyond the sixteenth level or POPed accesses the register at the address specified by the beyond the first level, setting the appropriate bits File Select Registers (FSR). If the FSRn address (STKOVF or STKUNF, respectively) in the PCON specifies one of the two INDFn registers, the read will register. return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair, FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2013-2015 Microchip Technology Inc. DS40001723D-page 37

PIC12(L)F1571/2 FIGURE 3-9: INDIRECT ADDRESSING Rev.10-000044A 7/30/2013 0x0000 0x0000 Traditional DataMemory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear DataMemory 0x29AF 0x29B0 Reserved 0x7FFF FSR 0x8000 Address 0x0000 Range Program FlashMemory 0xFFFF 0x7FFF Note: Notallmemoryregionsarecompletelyimplemented.Consultdevicememorytablesformemorylimits. DS40001723D-page 38  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 3.6.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address, 0x000, to FSR address, 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Rev. 10-000056A 7/31/2013 Direct Addressing Indirect Addressing From Opcode 4 BSR 0 6 0 7 FSRxH 0 7 FSRxL 0 0000 Bank Select Location Select Bank Select Location Select 00000 00001 00010 11111 0x00 0x7F Bank 0 Bank 1 Bank 2 Bank 31  2013-2015 Microchip Technology Inc. DS40001723D-page 39

PIC12(L)F1571/2 3.6.2 LINEAR DATA MEMORY 3.6.3 PROGRAM FLASH MEMORY The linear data memory is the region from FSR To make constant data access easier, the entire address, 0x2000, to FSR address, 0x29AF. This region Program Flash Memory is mapped to the upper half of is a virtual region that points back to the 80-byte blocks the FSR address space. When the MSb of FSRnH is of GPR memory in all the banks. set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the Unimplemented memory reads as 0x00. Use of the lower eight bits of each memory location are accessible linear data memory region allows buffers to be larger via INDF. Writing to the Program Flash Memory cannot than 80 bytes because incrementing the FSR beyond be accomplished via the FSR/INDF interface. All one bank will go directly to the GPR memory of the next instructions that access Program Flash Memory via the bank. FSR/INDF interface will require one additional The 16 bytes of common memory are not included in instruction cycle to complete. the linear data memory region. FIGURE 3-12: PROGRAM FLASH FIGURE 3-11: LINEAR DATA MEMORY MEMORY MAP MAP Rev. 10-000057A 7/31/2013 Rev. 10-000058A 7/31/2013 7 FSRnH 0 7 FSRnL 0 7 FSRnH 0 7 FSRnL 0 1 001 Location Select Location Select 0x8000 0x2000 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF Program Flash 0x120 Memory Bank 2 (low 8 bits) 0x16F 0xF20 Bank 30 0x7FFF 0xF6F 0xFFFF 0x29AF DS40001723D-page 40  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 4.0 DEVICE CONFIGURATION Note: The DEBUG bit in the Configuration Words is managed automatically by device Device configuration consists of Configuration Words, development tools, including debuggers code protection and Device ID. and programmers. For normal device operation, this bit should be maintained as 4.1 Configuration Words a ‘1’. There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h.  2013-2015 Microchip Technology Inc. DS40001723D-page 41

PIC12(L)F1571/2 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 U-1 U-1 R/P-1 R/P-1 R/P-1 U-1 — — CLKOUTEN BOREN<1:0>(1) — bit 13 bit 8 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 CP(2) MCLRE PWRTE(1) WDTE<1:0> — FOSC<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after bulk erase bit 13-12 Unimplemented: Read as ‘1’ bit 11 CLKOUTEN: Clock Out Enable bit 1 = Off – CLKOUT function is disabled; I/O or oscillator function on CLKOUT pin 0 = On – CLKOUT function is enabled on CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = On – Brown-out Reset is enabled; the SBOREN bit is ignored 10 = Sleep – Brown-out Reset is enabled while running and disabled in Sleep; the SBOREN bit is ignored 01 = SBODEN – Brown-out Reset is controlled by the SBOREN bit in the BORCON register 00 = Off – Brown-out Reset is disabled; the SBOREN bit is ignored bit 8 Unimplemented: Read as ‘1’ bit 7 CP: Flash Program Memory Code Protection bit(2) 1 = Off– Code protection is off; program memory can be read and written 0 = On– Code protection is on; program memory cannot be read or written externally bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1 (On): This bit is ignored. MCLR/VPP pin function is MCLR; weak pull-up is enabled. If LVP bit = 0 (Off): 1 = On – MCLR/VPP pin function is MCLR; weak pull-up is enabled 0 = Off – MCLR/VPP pin function is a digital input, MCLR is internally disabled; weak pull-up is under control of pin’s WPU control bit bit 5 PWRTE: Power-up Timer Enable bit(1) 1 = Off – PWRT is disabled 0 = On – PWRT is enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bits 11 = On – WDT is enabled; SWDTEN is ignored 10 = Sleep – WDT is enabled while running and disabled in Sleep; SWDTEN is ignored 01 = SWDTEN – WDT is controlled by the SWDTEN bit in the WDTCON register 00 = Off – WDT is disabled; SWDTEN is ignored bit 2 Unimplemented: Read as ‘1’ bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = ECH – External Clock, High-Power mode: CLKI on CLKI 10 = ECM – External Clock, Medium Power mode: CLKI on CLKI 01 = ECL – External Clock, Low-Power mode: CLKI on CLKI 00 = INTOSC– I/O function on CLKI Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer. 2: Once enabled, code-protect can only be disabled by bulk erasing the device. DS40001723D-page 42  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 LVP(1) DEBUG(2) LPBOREN BORV(3) STVREN PLLEN bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1 — — — — — — WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after bulk erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = On– Low-voltage programming is enabled, MCLR/VPP pin function is MCLR; MCLRE Configuration bit is ignored 0 = Off– High voltage on MCLR/VPP must be used for programming bit 12 DEBUG: Debugger Mode bit(2) 1 = Off– In-Circuit Debugger is disabled; ICSPCLK and ICSPDAT are general purpose I/O pins 0 = On– In-Circuit Debugger is enabled; ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOREN: Low-Power Brown-out Reset Enable bit 1 = Off– Low-power Brown-out Reset is disabled 0 = On– Low-power Brown-out Reset is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(3) 1 = Low – Brown-out Reset voltage (VBOR), low trip point selected 0 = High– Brown-out Reset voltage (VBOR), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = On– Stack overflow or underflow will cause a Reset 0 = Off– Stack overflow or underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = On– 4xPLL is enabled 0 = Off– 4xPLL is disabled bit 7-2 Unimplemented: Read as ‘1’ bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 2 kW Flash Memory (PIC12F1572): 11 = Off – Write protection is off 10 = Boot – 000h to 1FFh is write-protected, 200h to 7FFh may be modified by PMCON control 01 = Half – 000h to 3FFh is write-protected, 400h to 7FFh may be modified by PMCON control 00 = All – 000h to 7FFh is write-protected, no addresses may be modified by PMCON control 1 kW Flash Memory (PIC12(L)F1571): 11 = Off – Write protection is off 10 = Boot – 000h to 0FFh is write-protected, 100h to 3FFh may be modified by PMCON control 01 = Half – 000h to 1FFh is write-protected, 200h to 3FFh may be modified by PMCON control 00 = All – 000h to 3FFh is write-protected, no addresses may be modified by PMCON control Note 1: This bit cannot be programmed to ‘0’ when programming mode is entered via LVP. 2: The DEBUG bit in Configuration Words is managed automatically by device development tools, including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 3: See VBOR parameter for specific trip point voltages.  2013-2015 Microchip Technology Inc. DS40001723D-page 43

PIC12(L)F1571/2 4.3 Code Protection 4.5 User ID Code protection allows the device to be protected from Four memory locations (8000h-8003h) are designated as unauthorized access. Internal access to the program ID locations where the user can store checksum or other memory is unaffected by any code protection setting. code identification numbers. These locations are readable and writable during normal execution. See 4.3.1 PROGRAM MEMORY PROTECTION Section 10.4“User ID, Device ID and Configuration The entire program memory space is protected from Word Access” for more information on accessing external reads and writes by the CP bit in the these memory locations. For more information on Configuration Words. When CP = 0, external reads and checksum calculation, see the “PIC12(L)F1571/2 writes of program memory are inhibited and a read will Memory Programming Specification” (DS40001713). return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. 4.6 Device ID and Revision ID Writing the program memory is dependent upon the The 14-bit Device ID word is located at 8006h and the write protection setting. See Section 4.4“Write 14-bit Revision ID is located at 8005h. These locations Protection” for more information. are read-only and cannot be erased or modified. See Section 10.4“User ID, Device ID and Configuration 4.4 Write Protection Word Access” for more information on accessing Write protection allows the device to be protected from these memory locations. unintended self-writes. Applications, such as boot- Development tools, such as device programmers and loader software, can be protected while allowing other debuggers, may be used to read the Device ID and regions of the program memory to be modified. Revision ID. The WRT<1:0> bits in the Configuration Words define the size of the program memory block that is protected. DS40001723D-page 44  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 4.7 Register Definitions: Device ID REGISTER 4-3: DEVICEID: DEVICE ID REGISTER(1) R R R R R R DEV<13:8> bit 13 bit 8 R R R R R R R R DEV<7:0> bit 7 bit 0 Legend: R = Readable bit ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 13-0 DEV<13:0>: Device ID bits Refer to Table4-1 to determine what these bits will read on which device. A value of 3FFFh is invalid. Note 1: This location cannot be written. REGISTER 4-4: REVISIONID: REVISION ID REGISTER(1) R R R R R R REV<13:8> bit 13 bit 8 R R R R R R R R REV<7:0> bit 7 bit 0 Legend: R = Readable bit ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 13-0 REV<13:0>: Revision ID bits These bits are used to identify the device revision. Note 1: This location cannot be written. TABLE 4-1: DEVICE ID VALUES DEVICE Device ID Revision ID PIC12F1571 3051h 2xxxh PIC12LF1571 3053h 2xxxh PIC12F1572 3050h 2xxxh PIC12LF1572 3052h 2xxxh  2013-2015 Microchip Technology Inc. DS40001723D-page 45

PIC12(L)F1571/2 NOTES: DS40001723D-page 46  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 5.0 OSCILLATOR MODULE The oscillator module can be configured in one of the following clock modes: 5.1 Overview 1. ECL – External Clock Low-Power mode (0MHz to 0.5MHz) The oscillator module has a wide variety of clock 2. ECM – External Clock Medium Power mode sources and selection features that allow it to be used in (0.5MHz to 4MHz) a wide range of applications, while maximizing perfor- 3. ECH – External Clock High-Power mode mance and minimizing power consumption. Figure5-1 (4MHz to 32MHz) illustrates a block diagram of the oscillator module. 4. INTOSC – Internal Oscillator (31kHz to 32 MHz) Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Clock Source modes are selected by the FOSC<1:0> Resistor-Capacitor (RC) circuits. In addition, the system bits in the Configuration Words. The FOSC bits deter- clock source can be supplied from one of two internal mine the type of oscillator that will be used when the oscillators and PLL circuits, with a choice of speeds device is first powered. selectable via software. Additional clock features The ECH, ECM, and ECL Clock modes rely on an include: external logic level signal as the device clock source. • Selectable system clock source between external The INTOSC internal oscillator block produces low, or internal sources via software medium and high-frequency clock sources, designated • Oscillator Start-up Timer (OST) ensures stability as LFINTOSC, MFINTOSC and HFINTOSC (see of crystal oscillator sources Internal Oscillator Block, Figure5-1). A wide selection of device clock frequencies may be derived from these three clock sources.  2013-2015 Microchip Technology Inc. DS40001723D-page 47

PIC12(L)F1571/2 FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM Rev. 10-000155A 10/11/2013 FOSC<1:0> 2 Reserved 01 Sleep CLKIN 0 FOSC(1) 00 4x PLL(2) 1 to CPU and Peripherals PLLEN INTOSC 1x SPLLEN 2 16 MHz SCS<1:0> 8 MHz 4 MHz HFPLL HFINTOSC(1) 2 MHz 16 MHz er 1 MHz al *500 kHz c s 500 kHz MFINTOSC(1) Pre *250 kHz Oscillator *125 kHz 62.5 kHz *31.25 kHz *31 kHz Internal Oscillator Block 4 IRCF<3:0> 31 kHz LFINTOSC(1) to WDT, PWRT, and Oscillator other Peripherals to Peripherals 600 kHz FRC(1) to ADC and Oscillator other Peripherals * Available with more than one IRCF selection Note 1: See Section5.2 “Clock Source Types”. 2: ST Buffer is high-speed type when using T1CKI. 3: If FOSC<1:0> = 00, 4x PLL can only be used if IRCF<3:0> = 1110. DS40001723D-page 48  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 5.2 Clock Source Types 5.2.1.1 EC Mode Clock sources can be classified as external or internal. The External Clock (EC) mode allows an externally generated logic level signal to be the system clock External clock sources rely on external circuitry for the source. When operating in this mode, an external clock clock source to function. source is connected to the CLKIN input. CLKOUT is Internal clock sources are contained within the available for general purpose I/Os or CLKOUT. oscillator module. The internal oscillator block has two Figure5-2 shows the pin connections for EC mode. internal oscillators and a dedicated Phase-Locked EC mode has three power modes to select from through Loop (HFPLL) that are used to generate three internal the FOSCx bits in the Configuration Words: system clock sources: the 16 MHz High-Frequency • ECH – High power, 4-20MHz Internal Oscillator (HFINTOSC), 500 kHz Medium Frequency Internal Oscillator (MFINTOSC) and the • ECM – Medium power, 0.5-4MHz 31kHz Low-Frequency Internal Oscillator (LFINTOSC). • ECL – Low power, 0-0.5MHz The system clock can be selected between external or The Oscillator Start-up Timer (OST) is disabled when internal clock sources via the System Clock Select EC mode is selected. Therefore, there is no delay in (SCS<1:0>) bits in the OSCCON register. See operation after a Power-on Reset (POR) or wake-up Section 5.3“Clock Switching” for additional from Sleep. Because the PIC® MCU design is fully information. static, stopping the external clock input will have the effect of halting the device while leaving all data intact. 5.2.1 EXTERNAL CLOCK SOURCES Upon restarting the external clock, the device will An external clock source can be used as the device resume operation as if no time had elapsed. system clock by performing one of the following actions: FIGURE 5-2: EXTERNAL CLOCK (EC) MODE OPERATION • Program the FOSC<1:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a Clock from CLKIN device Reset. Ext. System • Write the SCS<1:0> bits in the OSCCON register PIC® MCU to switch the system clock source to: FOSC/4 or - Timer1 oscillator during run time, or I/O(1) CLKOUT - An external clock source determined by the value of the FOSCx bits. Note 1: Output depends upon CLKOUTEN bit of See Section 5.3“Clock Switching” for more the Configuration Words. information.  2013-2015 Microchip Technology Inc. DS40001723D-page 49

PIC12(L)F1571/2 5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 HFINTOSC The device may be configured to use the internal oscil- The High-Frequency Internal Oscillator (HFINTOSC) is lator block as the system clock by performing one of the a factory calibrated 16 MHz internal clock source. The following actions: frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register5-3). • Program the FOSC<1:0> bits in the Configuration Words to select the INTOSC clock source, which The output of the HFINTOSC connects to a postscaler will be used as the default system clock upon a and multiplexer (see Figure5-1). One of multiple device Reset. frequencies derived from the HFINTOSC can be • Write the SCS<1:0> bits in the OSCCON register selected via software using the IRCF<3:0> bits of the to switch the system clock source to the internal OSCCON register. See Section 5.2.2.8“Internal oscillator during run time. See Oscillator Clock Switch Timing” for more information. Section 5.3“Clock Switching”for more The HFINTOSC is enabled by: information. • Configuring the IRCF<3:0> bits of the OSCCON In INTOSC mode, CLKIN is available for general register for the desired HF frequency, and purpose I/O. CLKOUT is available for general purpose • Setting FOSC<1:0> = 00, or I/O or CLKOUT. • Setting the System Clock Source x (SCSx) bits of The function of the OSC2/CLKOUT pin is determined the OSCCON register to ‘1x’. by the CLKOUTEN bit in the Configuration Words. A fast start-up oscillator allows internal circuits to power The internal oscillator block has two independent up and stabilize before switching to HFINTOSC. oscillators and a dedicated Phase-Locked Loop, The High-Frequency Internal Oscillator Ready bit HFPLL, that can produce one of three internal system (HFIOFR) of the OSCSTAT register indicates when the clock sources. HFINTOSC is running. 1. The HFINTOSC (High-Frequency Internal The High-Frequency Internal Oscillator Status Locked Oscillator) is factory calibrated and operates at bit (HFIOFL) of the OSCSTAT register indicates when 16MHz. The HFINTOSC source is generated the HFINTOSC is running within 2% of its final value. from the 500 kHz MFINTOSC source and the dedicated Phase-Locked Loop, HFPLL. The The High-Frequency Internal Oscillator Stable bit frequency of the HFINTOSC can be (HFIOFS) of the OSCSTAT register indicates when the user-adjusted via software using the OSCTUNE HFINTOSC is running within 0.5% of its final value. register (Register5-3). 5.2.2.2 MFINTOSC 2. The MFINTOSC (Medium Frequency Internal Oscillator) is factory calibrated and operates at The Medium Frequency Internal Oscillator (MFINTOSC) 500kHz. The frequency of the MFINTOSC can is a factory calibrated 500 kHz internal clock source. be user-adjusted via software using the The frequency of the MFINTOSC can be altered via OSCTUNE register (Register5-3). software using the OSCTUNE register (Register5-3). 3. The LFINTOSC (Low-Frequency Internal The output of the MFINTOSC connects to a postscaler Oscillator) is uncalibrated and operates at and multiplexer (see Figure5-1). One of nine 31kHz. frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.8“Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configuring the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • Setting FOSC<1:0> = 00, or • Setting the System Clock Source x (SCSx) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running. DS40001723D-page 50  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 5.2.2.3 Internal Oscillator Frequency 5.2.2.5 FRC Adjustment The FRC clock is an uncalibrated, nominal 600 kHz The 500 kHz internal oscillator is factory calibrated. peripheral clock source. This internal oscillator can be adjusted in software by The FRC is automatically turned on by the peripherals writing to the OSCTUNE register (Register5-3). Since requesting the FRC clock. the HFINTOSC and MFINTOSC clock sources are The FRC clock will continue to run during Sleep. derived from the 500 kHz internal oscillator, a change in the OSCTUNE register value will apply to both. 5.2.2.6 Internal Oscillator Frequency The default value of the OSCTUNE register is ‘0’. The Selection value is a 6-bit two’s complement number. A value of The system clock speed can be selected via software 1Fh will provide an adjustment to the maximum using the Internal Oscillator Frequency Select bits frequency. A value of 20h will provide an adjustment to IRCF<3:0> of the OSCCON register. the minimum frequency. The postscaler outputs of the 16 MHz HFINTOSC, When the OSCTUNE register is modified, the oscillator 500kHz MFINTOSC and 31 kHz LFINTOSC output frequency will begin shifting to the new frequency. Code connect to a multiplexer (see Figure5-1). The Internal execution continues during this shift. There is no Oscillator Frequency Select bits, IRCF<3:0> of the indication that the shift has occurred. OSCCON register, select the frequency output of the OSCTUNE does not affect the LFINTOSC frequency. internal oscillators. One of the following frequencies Operation of features that depends on the LFINTOSC can be selected via software: clock source frequency, such as the Power-up Timer • 32 MHz (requires 4x PLL) (PWRT), Watchdog Timer (WDT) and peripherals, are not affected by the change in frequency. • 16 MHz • 8 MHz 5.2.2.4 LFINTOSC • 4 MHz The Low-Frequency Internal Oscillator (LFINTOSC) is • 2 MHz an uncalibrated 31 kHz internal clock source. • 1 MHz The output of the LFINTOSC connects to a multiplexer • 500 kHz (default after Reset) (see Figure5-1). Select 31 kHz, via software, using • 250 kHz the IRCF<3:0> bits of the OSCCON register. See • 125 kHz Section 5.2.2.8“Internal Oscillator Clock Switch • 62.5 kHz Timing” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), • 31.25 kHz Watchdog Timer (WDT) and Fail-Safe Clock Monitor • 31 kHz (LFINTOSC) (FSCM). Note: Following any Reset, the IRCF<3:0> bits The LFINTOSC is enabled by selecting 31 kHz of the OSCCON register are set to ‘0111’ (IRCF<3:0> (OSCCON<6:3>) = 0000) as the system and the frequency selection is set to clock source (SCS<1:0> (OSCCON<1:0>) = 1x) or 500kHz. The user can modify the IRCFx when any of the following are enabled: bits to select a different frequency. • Configure the IRCF<3:0> bits of the OSCCON The IRCF<3:0> bits of the OSCCON register allow register for the desired LF frequency, and duplicate selections for some frequencies. These dupli- • Set FOSC<1:0> = 00, or cate choices can offer system design trade-offs. Lower • Set the System Clock Source x (SCSx) bits of the power consumption can be obtained when changing OSCCON register to ‘1x’ oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes Peripherals that use the LFINTOSC are: that use the same oscillator source. • Power-up Timer (PWRT) • Watchdog Timer (WDT) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running.  2013-2015 Microchip Technology Inc. DS40001723D-page 51

PIC12(L)F1571/2 5.2.2.7 32 MHz Internal Oscillator 5.2.2.8 Internal Oscillator Clock Switch Frequency Selection Timing The internal oscillator block can be used with the When switching between the HFINTOSC, MFINTOSC 4xPLL associated with the external oscillator block to and the LFINTOSC, the new oscillator may already be produce a 32 MHz internal system clock source. The shut down to save power (see Figure5-3). If this is the following settings are required to use the 32 MHz case, there is a delay after the IRCF<3:0> bits of the internal clock source: OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will • The FOSCx bits in the Configuration Words must reflect the current active status of the HFINTOSC, be set to use the INTOSC source as the device MFINTOSC and LFINTOSC oscillators. The sequence system clock (FOSC<1:0> = 00). of a frequency selection is as follows: • The SCSx bits in the OSCCON register must be cleared to use the clock determined by 1. IRCF<3:0> bits of the OSCCON register are FOSC<1:0> in the Configuration Words modified. (SCS<1:0>=00). 2. If the new clock is shut down, a clock start-up • The IRCFx bits in the OSCCON register must be delay is started. set to the 8 MHz HFINTOSC to use 3. Clock switch circuitry waits for a falling edge of (IRCF<3:0>=1110). the current clock. • The SPLLEN bit in the OSCCON register must be 4. The current clock is held low and the clock set to enable the 4x PLL or the PLLEN bit of the switch circuitry waits for a rising edge in the new Configuration Words must be programmed to a clock. ‘1’. 5. The new clock is now active. Note: When using the PLLEN bit of the 6. The OSCSTAT register is updated as required. Configuration Words, the 4x PLL cannot 7. Clock switch is complete. be disabled by software and the 8 MHz See Figure5-3 for more details. HFINTOSC option will no longer be available. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay The 4x PLL is not available for use with the internal before the new frequency is selected. Clock switching oscillator when the SCSx bits of the OSCCON register time delays are shown in Table5-1. are set to ‘1x’. The SCSx bits must be set to ‘00’ to use Start-up delay specifications are located in the the 4x PLL with the internal oscillator. oscillator tables of Section 26.0“Electrical Specifications”. DS40001723D-page 52  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 5-3: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ LFINTOSC (WDT disabled) MFINTOSC HFINTOSC/ MFINTOSC Oscillator Delay(1) 2-Cycle Sync Running LFINTOSC IRCF<3:0> 0 = 0 System Clock HFINTOSC/ LFINTOSC (WDT enabled) MFINTOSC HFINTOSC/ MFINTOSC 2-Cycle Sync Running LFINTOSC IRCF <3:0> 0 = 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Turns Off unless WDT is Enabled LFINTOSC Oscillator Delay(1) 2-Cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> = 0  0 System Clock Note 1: See Table5-1 (Oscillator Switching Delays) for more information.  2013-2015 Microchip Technology Inc. DS40001723D-page 53

PIC12(L)F1571/2 5.3 Clock Switching 5.4 Clock Switching Before Sleep The system clock source can be switched between When clock switching from an old clock to a new clock external and internal clock sources via software using is requested, just prior to entering Sleep mode, it is the System Clock Select (SCSx) bits of the OSCCON necessary to confirm that the switch is complete before register. The following clock sources can be selected the SLEEP instruction is executed. Failure to do so may using the SCSx bits: result in an incomplete switch and consequential loss of the system clock altogether. Clock switching is • Default system oscillator determined by FOSCx confirmed by monitoring the clock status bits in the bits in the Configuration Words OSCSTAT register. Switch confirmation can be accom- • Timer1 32 kHz crystal oscillator plished by sensing that the ready bit for the new clock is • Internal Oscillator Block (INTOSC) set or the ready bit for the old clock is cleared. For example, when switching between the internal oscillator 5.3.1 SYSTEM CLOCK SELECT (SCSx) with the PLL and the internal oscillator without the PLL, BITS monitor the PLLR bit. When PLLR is set, the switch to The System Clock Select (SCSx) bits of the OSCCON 32MHz operation is complete. Conversely, when PLLR register select the system clock source that is used for is cleared, the switch from 32 MHz operation to the the CPU and peripherals. selected internal clock is complete. • When the SCSx bits of the OSCCON register = 00, the system clock source is determined by the value of the FOSC<1:0> bits in the Configuration Words. • When the SCSx bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. • When the SCSx bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCSx bits of the OSCCON register are always cleared. Note: Any automatic clock switch does not update the SCSx bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table5-1. TABLE 5-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) 31kHz Sleep/POR MFINTOSC(1) 31.25kHz-500 kHz Oscillator Warm-up Delay (TWARM)(2) HFINTOSC(1) 31.25kHz-16MHz Sleep/POR EC(1) DC – 32MHz 2 cycles LFINTOSC EC(1) DC – 32MHz 1 cycle of each MFINTOSC(1) 31.25kHz-500kHz Any Clock Source 2s (approx.) HFINTOSC(1) 31.25kHz-16MHz Any Clock Source LFINTOSC(1) 31kHz 1 cycle of each PLL Inactive PLL Active 16-32MHz 2ms (approx.) Note 1: PLL inactive. 2: See Section 26.0“Electrical Specifications”. DS40001723D-page 54  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 5.5 Register Definitions: Oscillator Control REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0 SPLLEN IRCF<3:0> — SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements). If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16MHz HF 1110 = 8MHz or 32 MHz HF (see Section 5.2.2.1“HFINTOSC”) 1101 = 4MHz HF 1100 = 2MHz HF 1011 = 1MHz HF 1010 = 500kHz HF(1) 1001 = 250kHz HF(1) 1000 = 125kHz HF(1) 0111 = 500kHz MF (default upon Reset) 0110 = 250kHz MF 0101 = 125kHz MF 0100 = 62.5kHz MF 0011 = 31.25kHz HF(1) 0010 = 31.25kHz MF 000x = 31kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<1:0> in Configuration Words Note 1: Duplicate frequency derived from HFINTOSC.  2013-2015 Microchip Technology Inc. DS40001723D-page 55

PIC12(L)F1571/2 REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER U-0 R-0/q R-q/q R-0/q R-0/q R-q/q R-0/q R-0/q — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit q = Conditional bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC<1:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<1:0> = 00) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS40001723D-page 56  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency 000001 = • • • 011110 = 011111 = Maximum frequency TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 55 OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 56 OSCTUNE — — TUN<5:0> 57 T1CON TMR1CS<1:0> T1CKPS<1:0> — T1SYNC — TMR1ON 167 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — — — CLKOUTEN BOREN<1:0> — CONFIG1 42 7:0 CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.  2013-2015 Microchip Technology Inc. DS40001723D-page 57

PIC12(L)F1571/2 NOTES: DS40001723D-page 58  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 6.0 RESETS To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR There are multiple ways to reset this device: or POR event. • Power-on Reset (POR) A simplified block diagram of the On-Chip Reset Circuit • Brown-out Reset (BOR) is shown in Figure6-1. • Low-Power Brown-out Reset (LPBOR) • MCLR Reset • WDT Reset • RESET instruction • Stack Overflow • Stack Underflow • Programming mode exit FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Rev. 10-000006A 8/14/2013 ICSP™ Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE VPP/MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD BOR Active(1) Brown-out R Power-up Reset Timer LFINTOSC LPBOR PWRTE Reset Note 1: See Table6-1 for BOR active conditions.  2013-2015 Microchip Technology Inc. DS40001723D-page 59

PIC12(L)F1571/2 6.1 Power-on Reset (POR) 6.2 Brown-out Reset (BOR) The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for performance may require greater than minimum VDD. execution protection can be implemented. The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in the conditions have been met. Configuration Words. The four operating modes are: 6.1.1 POWER-UP TIMER (PWRT) • BOR is always on • BOR is off when in Sleep The Power-up Timer provides a nominal 64ms time-out on a POR or Brown-out Reset. • BOR is controlled by software • BOR is always off The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to Refer to Table6-1 for more information. rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by enabled by clearing the PWRTE bit in the Configuration configuring the BORV bit in the Configuration Words. Words. A VDD noise rejection filter prevents the BOR from trig- The Power-up Timer starts after the release of the POR gering on small events. If VDD falls below VBOR for a and BOR. duration greater than parameter, TBORDC, the device For additional information, refer to Application Note will reset. See Figure6-2 for more information. AN607, “Power-up Trouble Shooting” (DS00000607). TABLE 6-1: BOR OPERATING MODES Instruction Execution upon: BOREN<1:0> SBOREN Device Mode BOR Mode Release of POR or Wake-up from Sleep Waits for BOR ready(1) 11 X X Active (BORRDY = 1) Awake Active Waits for BOR ready 10 X Sleep Disabled (BORRDY = 1) Waits for BOR ready(1) 1 X Active 01 (BORRDY = 1) 0 X Disabled Begins immediately 00 X X Disabled (BORRDY = x) Note 1: In these specific cases, “release of POR” and “wake-up from Sleep”, there is no delay in start-up. The BOR ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. DS40001723D-page 60  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 6.2.1 BOR IS ALWAYS ON BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. When the BORENx bits of the Configuration Words are programmed to ‘11’, the BOR is always on. The device 6.2.3 BOR CONTROLLED BY SOFTWARE start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. When the BORENx bits of the Configuration Words are programmed to ‘01’, the BOR is controlled by the BOR protection is active during Sleep. The BOR does SBOREN bit of the BORCON register. The device not delay wake-up from Sleep. start-up is not delayed by the BOR ready condition or 6.2.2 BOR IS OFF IN SLEEP the VDD level. BOR protection begins as soon as the BOR circuit is When the BORENx bits of the Configuration Words are ready. The status of the BOR circuit is reflected in the programmed to ‘10’, the BOR is on, except in Sleep. BORRDY bit of the BORCON register. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is unchanged by Sleep. FIGURE 6-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal < TPWRT Reset TPWRT(1) VDD VBOR Internal Reset TPWRT(1) Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.  2013-2015 Microchip Technology Inc. DS40001723D-page 61

PIC12(L)F1571/2 6.3 Register Definitions: BOR Control REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS(1) — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN<1:0> in Configuration Words = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN <1:0> in Configuration Words  01: SBOREN is read/write, but has no effect on the BOR. bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers Sleep/wake-up/operating cases) 0 = Band gap operates normally and may turn off If BOREN<1:0> = 11 (Always On) or BOREN<1:0> = 00 (Always Off): BORFS is read/write, but has no effect on the BOR. bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in the Configuration Words. DS40001723D-page 62  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 6.4 Low-Power Brown-out Reset 6.6 Watchdog Timer (WDT) Reset (LPBOR) The Watchdog Timer generates a Reset if the firmware The Low-Power Brown-out Reset (LPBOR) operates does not issue a CLRWDT instruction within the like the BOR to detect low-voltage conditions on the time-out period. The TO and PD bits in the STATUS VDD pin. When too low of a voltage is detected, the register are changed to indicate the WDT Reset. See device is held in Reset. When this occurs, a register bit Section 9.0“Watchdog Timer (WDT)” for more (BOR) is changed to indicate that a BOR Reset has information. occurred. The BOR bit in PCON is used for both BOR and the LPBOR. Refer to Register6-2. 6.7 RESET Instruction The LPBOR Voltage Threshold (VLPBOR) has a wider A RESET instruction will cause a device Reset. The RI tolerance than the BOR (VBOR), but requires much bit in the PCON register will be set to ‘0’. See Table6-4 less current (LPBOR current) to operate. The LPBOR for default conditions after a RESET instruction has is intended for use when the BOR is configured as dis- occurred. abled (BOREN<1:0> = 00) or disabled in Sleep mode (BOREN<1:0>= 10). 6.8 Stack Overflow/Underflow Reset Refer to Figure6-1 to see how the LPBOR interacts with other modules. The device can reset when the Stack overflows or underflows. The STKOVF or STKUNF bits of the PCON 6.4.1 ENABLING LPBOR register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in the Configuration The LPBOR is controlled by the LPBOR bit of the Words. See Section 3.5.2“Overflow/Underflow Configuration Words. When the device is erased, the Reset” for more information. LPBOR module defaults to disabled. 6.9 Programming Mode Exit 6.5 MCLR Upon exit of Programming mode, the device will The MCLR is an optional external input that can reset behave as if a POR had just occurred. the device. The MCLR function is controlled by the MCLRE and LVP bits of the Configuration Words 6.10 Power-up Timer (Table6-2). The Power-up Timer optionally delays device execution TABLE 6-2: MCLR CONFIGURATION after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start MCLRE LVP MCLR running. 0 0 Disabled The Power-up Timer is controlled by the PWRTE bit of 1 0 Enabled the Configuration Words. x 1 Enabled 6.11 Start-up Sequence 6.5.1 MCLR ENABLED Upon the release of a POR or BOR, the following must When MCLR is enabled and the pin is held low, the occur before the device will begin executing: device is held in Reset. The MCLR pin is connected to 1. Power-up Timer runs to completion (if enabled). VDD through an internal weak pull-up. 2. MCLR must be released (if enabled). The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Note: A Reset does not drive the MCLR pin low. Section 5.0“Oscillator Module” for more information. The Power-up Timer runs independently of a MCLR 6.5.2 MCLR DISABLED Reset. If MCLR is kept low long enough, the Power-up When MCLR is disabled, the pin functions as a general Timer will expire. Upon bringing MCLR high, the device purpose input and the internal weak pull-up is under soft- will begin execution after 10 FOSC cycles (see ware control. See Section 11.3“PORTA Registers” for Figure6-3). This is useful for testing purposes or to more information. synchronize more than one device operating in parallel.  2013-2015 Microchip Technology Inc. DS40001723D-page 63

PIC12(L)F1571/2 FIGURE 6-3: RESET START-UP SEQUENCE Rev.10-000032A VDD 7/30/2013 InternalPOR Power-upTimer TPWRT MCLR InternalRESET Int.Oscillator FOSC BeginExecution codeexecution(1) codeexecution(1) InternalOscillator,PWRTEN=0 InternalOscillator,PWRTEN=1 VDD InternalPOR Power-upTimer TPWRT MCLR InternalRESET Ext.Clock(EC) FOSC BeginExecution codeexecution(1) codeexecution(1) ExternalClock(ECmodes),PWRTEN=0 ExternalClock(ECmodes),PWRTEN=1 VDD InternalPOR Power-upTimer TPWRT MCLR InternalRESET OscStart-UpTimer TOST TOST Ext.Oscillator FOSC BeginExecution code code execution(1) execution(1) ExternalOscillators,PWRTEN=0,IESO=0 ExternalOscillators,PWRTEN=1,IESO=0 VDD InternalPOR Power-upTimer TPWRT MCLR InternalRESET OscStart-UpTimer TOST TOST Ext.Oscillator Int.Oscillator FOSC BeginExecution codeexecution(1) codeexecution(1) ExternalOscillators,PWRTEN=0,IESO=1 ExternalOscillators,PWRTEN=1,IESO=1 Note1: Codeexecutionbegins10FOSCcyclesaftertheFOSCclockisreleased. DS40001723D-page 64  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 6.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table6-3 and Table6-4 show the Reset conditions of these registers. TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is Set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is Set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during Normal Operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu RESET Instruction Executed 0000h ---u uuuu uu-- u0uu Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged; x = unknown; - = unimplemented bit, reads as ‘0’. Note1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address is pushed on the stack and the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.  2013-2015 Microchip Technology Inc. DS40001723D-page 65

PIC12(L)F1571/2 6.13 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • RESET Instruction Reset (RI) • MCLR Reset (RMCLR) • Watchdog Timer Reset (RWDT) • Stack Underflow Reset (STKUNF) • Stack Overflow Reset (STKOVF) The PCON register bits are shown in Register6-2. 6.14 Register Definitions: Power Control REGISTER 6-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u STKOVF STKUNF — RWDT RMCLR RI POR BOR bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Reset Flag bit 1 = A Stack Overflow Reset occurred 0 = A Stack Overflow Reset has not occurred or is cleared by firmware bit 6 STKUNF: Stack Underflow Reset Flag bit 1 = A Stack Underflow Reset occurred 0 = A Stack Underflow Reset has not occurred or is cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or is set by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or is set by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) DS40001723D-page 66  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BORCON SBOREN BORFS — — — — — BORRDY 62 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 66 STATUS — — — TO PD Z DC C 19 WDTCON — — WDTPS<4:0> SWDTEN 89 Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. TABLE 6-6: SUMMARY OF CONFIGURATION WORD WITH RESETS Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — — — CLKOUTEN BOREN<1:0> — CONFIG1 42 7:0 CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0> 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN CONFIG2 43 7:0 — — — — — — WRT<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.  2013-2015 Microchip Technology Inc. DS40001723D-page 67

PIC12(L)F1571/2 NOTES: DS40001723D-page 68  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 7.0 INTERRUPTS Many peripherals produce interrupts. Refer to the corresponding chapters for details. The interrupt feature allows certain events to preempt A block diagram of the interrupt logic is shown in normal program flow. Firmware is used to determine Figure7-1. the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for interrupts: • Operation • Interrupt Latency • Interrupts during Sleep • INT Pin • Automatic Context Saving FIGURE 7-1: INTERRUPT LOGIC Rev.10-000010A 1/13/2014 TMR0IF Wake-up TMR0IE (IfinSleepmode) INTF PeripheralInterrupts INTE (TMR1IF) PIR1<0> IOCIF (TMR1IE) PIE1<0> Interrupt IOCIE toCPU PEIE PIRn<7> GIE PIEn<7>  2013-2015 Microchip Technology Inc. DS40001723D-page 69

PIC12(L)F1571/2 7.1 Operation The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved Interrupts are disabled upon any device Reset. They context from the shadow registers and setting the GIE are enabled by setting the following bits: bit. • GIE bit of the INTCON register For additional information on a specific interrupt’s • Interrupt enable bit(s) for the specific interrupt operation, refer to its peripheral chapter. event(s) Note1: Individual interrupt flag bits are set, • PEIE bit of the INTCON register (if the interrupt regardless of the state of any other enable bit of the interrupt event is contained in the enable bits. PIE1, PIE2 and PIE3 registers) 2: All interrupts will be ignored while the GIE The INTCON, PIR1, PIR2 and PIR3 registers record bit is cleared. Any interrupt occurring individual interrupts via interrupt flag bits. Interrupt flag while the GIE bit is clear will be serviced bits will be set, regardless of the status of the GIE, PEIE when the GIE bit is set again. and individual interrupt enable bits. The following events happen when an interrupt event 7.2 Interrupt Latency occurs while the GIE bit is set: Interrupt latency is defined as the time from when the • Current prefetched instruction is flushed interrupt event occurs to the time code execution at the • GIE bit is cleared interrupt vector begins. The latency for synchronous • Current Program Counter (PC) is pushed onto the interrupts is three or four instruction cycles. For stack asynchronous interrupts, the latency is three to five • Critical registers are automatically saved to the instruction cycles, depending on when the interrupt shadow registers (See “Section 7.5“Automatic occurs. See Figure7-2 and Figure7-3 for more details. Context Saving”.”) • PC is loaded with the interrupt vector, 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. DS40001723D-page 70  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 7-2: INTERRUPT LATENCY Fosc Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC PC-1 PC PC+1 0004h 0005h Execute 1-Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC+1/FSR New PC/ PC PC-1 PC ADDR PC+1 0004h 0005h Execute 2-Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3-Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) Interrupt GIE PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h Execute 3-Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)  2013-2015 Microchip Technology Inc. DS40001723D-page 71

PIC12(L)F1571/2 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) INT Pin (1) (1) INTF (4) Interrupt Latency(2) GIE INSTRUCTION FLOW PC PC PC + 1 PC + 1 0004h 0005h Instruction Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Instruction Inst (PC – 1) Inst (PC) Forced NOP Forced NOP Inst (0004h) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: For minimum width of INT pulse, refer to AC specifications in Section 26.0“Electrical Specifications”. 4: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001723D-page 72  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 7.3 Interrupts During Sleep 7.5 Automatic Context Saving Some interrupts can be used to wake from Sleep. To Upon entering an interrupt, the return PC address is wake from Sleep, the peripheral must be able to saved on the stack. Additionally, the following registers operate without the system clock. The interrupt source are automatically saved in the shadow registers: must have the appropriate Interrupt Enable bit(s) set • W register prior to entering Sleep. • STATUS register (except for TO and PD) On waking from Sleep, if the GIE bit is also set, the • BSR register processor will branch to the interrupt vector. Otherwise, • FSR registers the processor will continue executing instructions after the • PCLATH register SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to Upon exiting the Interrupt Service Routine, these the ISR. Refer to Section 8.0“Power-Down Mode registers are automatically restored. Any modifications (Sleep)” for more details. to these registers during the ISR will be lost. If modifi- cations to any of these registers are desired, the 7.4 INT Pin corresponding shadow register should be modified and the value will be restored when exiting the ISR. The The INT pin can be used to generate an asynchronous shadow registers are available in Bank 31 and are edge-triggered interrupt. This interrupt is enabled by readable and writable. Depending on the user’s setting the INTE bit of the INTCON register. The application, other registers may also need to be saved. INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.  2013-2015 Microchip Technology Inc. DS40001723D-page 73

PIC12(L)F1571/2 7.6 Register Definitions: Interrupt Control REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE(1) PEIE(2) TMR0IE INTE IOCIE TMR0IF INTF IOCIF(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 GIE: Global Interrupt Enable bit(1) 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit(2) 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-On-Change Enable bit 1 = Enables the Interrupt-On-Change 0 = Disables the Interrupt-On-Change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register has not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-On-Change Interrupt Flag bit(3) 1 = When at least one of the Interrupt-On-Change pins changed state 0 = None of the Interrupt-On-Change pins have changed state Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 3: The IOCIF Flag bit is read-only and cleared when all the Interrupt-On-Change flags in the IOCxF registers have been cleared by software. DS40001723D-page 74  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit(1) 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit(1) 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3-2 Unimplemented: Read as ‘0’ bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC12(L)F1572 only. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2013-2015 Microchip Technology Inc. DS40001723D-page 75

PIC12(L)F1571/2 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 — — C1IE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4-0 Unimplemented: Read as ‘0’ Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001723D-page 76  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 — PWM3IE PWM2IE PWM1IE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6 PWM3IE: PWM3 Interrupt Enable bit 1 = Enables the PWM3 interrupt 0 = Disables the PWM3 interrupt bit 5 PWM2IE: PWM2 Interrupt Enable bit 1 = Enables the PWM2 interrupt 0 = Disables the PWM2 interrupt bit 4 PWM1IE: PWM1 Interrupt Enable bit 1 = Enables the PWM1 interrupt 0 = Disables the PWM1 interrupt bit 3-0 Unimplemented: Read as ‘0’ Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.  2013-2015 Microchip Technology Inc. DS40001723D-page 77

PIC12(L)F1571/2 REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: ADC Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 3-2 Unimplemented: Read as ‘0’ bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note 1: PIC12(L)F1572 only. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001723D-page 78  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0 — — C1IF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5 C1IF: Numerically Controlled Oscillator Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4-0 Unimplemented: Read as ‘0’ Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.  2013-2015 Microchip Technology Inc. DS40001723D-page 79

PIC12(L)F1571/2 REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 R-0/0 R-0/0 R-0/0 U-0 U-0 U-0 U-0 — PWM3IF(1) PWM2IF(1) PWM1IF(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6 PWM3IF: PWM3 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 PWM2IF: PWM2 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 PWM1IF: PWM1 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending bit 3-0 Unimplemented: Read as ‘0’ Note 1: These bits are read-only. They must be cleared by addressing the Flag registers inside the module. 2: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001723D-page 80  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 157 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIE2 — — C1IE — — — — — 76 PIE3 — PWM3IE PWM2IE PWM1IE — — — — 77 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 PIR2 — — C1IF — — — — — 79 PIR3 — PWM3IF PWM2IF PWM1IF — — — — 80 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. Note 1: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 81

PIC12(L)F1571/2 NOTES: DS40001723D-page 82  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 8.0 POWER-DOWN MODE (SLEEP) The first three events will cause a device Reset. The last three events are considered a continuation of program The Power-Down mode is entered by executing a execution. To determine whether a device Reset or wake- SLEEP instruction. up event occurred, refer to Section 6.12“Determining Upon entering Sleep mode, the following conditions exist: the Cause of a Reset”. 1. WDT will be cleared but keeps running if When the SLEEP instruction is being executed, the next enabled for operation during Sleep. instruction (PC + 1) is prefetched. For the device to 2. PD bit of the STATUS register is cleared. wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will 3. TO bit of the STATUS register is set. occur regardless of the state of the GIE bit. If the GIE 4. CPU clock is disabled. bit is disabled, the device continues execution at the 5. 31 kHz LFINTOSC is unaffected and peripherals instruction after the SLEEP instruction. If the GIE bit is that operate from it may continue operation in enabled, the device executes the instruction after the Sleep. SLEEP instruction, the device will then call the Interrupt 6. Timer1 and peripherals that operate from Service Routine. In cases where the execution of the Timer1 continue operation in Sleep when the instruction following SLEEP is not desirable, the user Timer1 clock source selected is: should have a NOP after the SLEEP instruction. • LFINTOSC The WDT is cleared when the device wakes up from • T1CKI Sleep, regardless of the source of wake-up. • Timer1 oscillator 7. ADC is unaffected if the dedicated FRC oscillator 8.1.1 WAKE-UP USING INTERRUPTS is selected. When global interrupts are disabled (GIE cleared) and 8. I/O ports maintain the status they had before any interrupt source has both its interrupt enable bit SLEEP was executed (driving high, low or and interrupt flag bit set, one of the following will occur: high-impedance). • If the interrupt occurs before the execution of a 9. Resets other than WDT are not affected by Sleep mode. SLEEP instruction: - SLEEP instruction will execute as a NOP. Refer to individual chapters for more details on peripheral operation during Sleep. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set To minimize current consumption, the following conditions should be considered: - PD bit of the STATUS register will not be cleared. • I/O pins should not be floating • If the interrupt occurs during or after the • External circuitry sinking current from I/O pins • Internal circuitry sourcing current from I/O pins execution of a SLEEP instruction: • Current draw from pins with internal weak pull-ups - SLEEP instruction will be completely • Modules using 31 kHz LFINTOSC executed • CWG module using HFINTOSC - Device will immediately wake-up from Sleep I/O pins that are high-impedance inputs should be - WDT and WDT prescaler will be cleared pulled to VDD or VSS externally to avoid switching - TO bit of the STATUS register will be set currents caused by floating inputs. - PD bit of the STATUS register will be cleared Examples of internal circuitry that might be Even if the flag bits were checked before executing a sourcing current include the FVR module. See SLEEP instruction, it may be possible for flag bits to Section 13.0 “Fixed Voltage Reference (FVR)” become set before the SLEEP instruction completes. To for more information on this module. determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction 8.1 Wake-up from Sleep was executed as a NOP. The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin if enabled. 2. BOR Reset if enabled. 3. POR Reset. 4. Watchdog Timer if enabled. 5. Any external interrupt. 6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)  2013-2015 Microchip Technology Inc. DS40001723D-page 83

PIC12(L)F1571/2 FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) CLKOUT(2) TOST(3) Interrupt Flag Interrupt Latency(4) GIE bit Processor in (INTCON reg.) Sleep Instruction Flow PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h Instruction Fetched Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) IEnxsetrcuuctteiodn Inst(PC – 1) Sleep Inst(PC + 1) Forced NOP Forced NOP Inst(0004h) Note1: External Clock. High, Medium, Low mode assumed. 2: CLKOUT is shown here for timing reference. 3: TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (if available). 4: GIE = 1 assumed. In this case, after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. 8.2 Low-Power Sleep Mode 8.2.2 PERIPHERAL USAGE IN SLEEP This device contains an internal Low Dropout (LDO) Some peripherals that can operate in Sleep mode will voltage regulator, which allows the device I/O pins to not operate properly with the Low-Power Sleep mode operate at voltages up to 5.5V while the internal device selected. The LDO will remain in the normal power logic operates at a lower voltage. The LDO and its mode when those peripherals are enabled. The Low- associated reference circuitry must remain active when Power Sleep mode is intended for use with these the device is in Sleep mode. peripherals: Low-Power Sleep mode allows the user to optimize the • Brown-out Reset (BOR) operating current in Sleep. Low-Power Sleep mode can • Watchdog Timer (WDT) be selected by setting the VREGPM bit of the • External interrupt pin/Interrupt-On-Change pins VREGCON register, which puts the LDO and reference • Timer1 (with external clock source) circuitry in a low-power state whenever the device is in The Complementary Waveform Generator (CWG) Sleep. module can utilize the HFINTOSC oscillator as either a clock source or as an input source. Under certain 8.2.1 SLEEP CURRENT VS. WAKE-UP conditions, when the HFINTOSC is selected for use TIME with the CWG module, the HFINTOSC will remain In the default operating mode, the LDO and reference active during Sleep. This will have a direct effect on circuitry remain in the normal configuration while in the Sleep mode current. Sleep. The device is able to exit Sleep mode quickly Please refer to section Section 23.10“Operation since all circuits remain active. In Low-Power Sleep During Sleep” for more information. mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal Note: The PIC12LF1571/2 does not have a configuration and stabilize. configurable Low-Power Sleep mode. PIC12LF1571/2 is an unregulated device The Low-Power Sleep mode is beneficial for applica- and is always in the lowest power state tions that stay in Sleep mode for long periods of time. when in Sleep with no wake-up time penalty. The normal mode is beneficial for applications that This device has a lower maximum VDD and need to wake from Sleep quickly and frequently. I/O voltage than the PIC12F1571/2. See Section 26.0“Electrical Specifications” for more information. DS40001723D-page 84  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 8.3 Register Definitions: Voltage Regulator Control REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up. 0 = Normal power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up. bit 0 Reserved: Read as ‘1’, maintain this bit set Note 1: PIC12F1571/2 only. 2: See Section 26.0“Electrical Specifications” TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Register on Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 122 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 121 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 121 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIE2 — — C1IE — — — — — 76 PIE3 — PWM3IE PWM2IE PWM1IE — — — — 77 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 PIR2 — — C1IF — — — — — 79 PIR3 — PWM3IF PWM2IF PWM1IF — — — — 80 STATUS — — — TO PD Z DC C 19 WDTCON — — WDTPS<4:0> SWDTEN 89 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. Note 1: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 85

PIC12(L)F1571/2 NOTES: DS40001723D-page 86  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 9.0 WATCHDOG TIMER (WDT) The WDT has the following features: • Independent clock source The Watchdog Timer is a system timer that generates • Multiple operating modes: a Reset if the firmware does not issue a CLRWDT - WDT is always on instruction within the time-out period. The Watchdog Timer is typically used to recover the system from - WDT is off when in Sleep unexpected events. - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (nominal) • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM Rev. 10-000141A 7/30/2013 WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 LFINTOSC 23-(cid:37)it Programmable WDT Prescaler WDT Time-out WDTE<1:0> = 10 Sleep WDTPS<4:0>  2013-2015 Microchip Technology Inc. DS40001723D-page 87

PIC12(L)F1571/2 9.1 Independent Clock Source 9.3 Time-out Period The WDT derives its time base from the 31kHz The WDTPS<4:0> bits of the WDTCON register set the LFINTOSC internal oscillator. Time intervals in this time-out period from 1 ms to 256 seconds (nominal). chapter are based on a nominal interval of 1ms. See After a Reset, the default time-out period is two Section 26.0“Electrical Specifications” for the seconds. LFINTOSC tolerances. 9.4 Clearing the WDT 9.2 WDT Operating Modes The WDT is cleared when any of the following conditions The Watchdog Timer module has four operating modes occur: controlled by the WDTE<1:0> bits in the Configuration • Any Reset Words. See Table9-1. • CLRWDT instruction is executed 9.2.1 WDT IS ALWAYS ON • Device enters Sleep • Device wakes up from Sleep When the WDTEx bits of the Configuration Words are set to ‘11’, the WDT is always on. WDT protection is • Oscillator fails active during Sleep. • WDT is disabled • Oscillator Start-up Timer (OST) is running 9.2.2 WDT IS OFF IN SLEEP See Table9-2 for more information. When the WDTEx bits of the Configuration Words are set to ‘10’, the WDT is on, except in Sleep. WDT 9.5 Operation During Sleep protection is not active during Sleep. When the device enters Sleep, the WDT is cleared. If 9.2.3 WDT CONTROLLED BY SOFTWARE the WDT is enabled during Sleep, the WDT resumes When the WDTEx bits of the Configuration Words are counting. When the device exits Sleep, the WDT is set to ‘01’, the WDT is controlled by the SWDTEN bit of cleared again. the WDTCON register. The WDT remains clear until the OST, if enabled, com- WDT protection is unchanged by Sleep. See Table9-1 pletes. See Section 5.0“Oscillator Module” for more for more details. information on the OST. When a WDT time-out occurs while the device is in TABLE 9-1: WDT OPERATING MODES Sleep, no Reset is generated. Instead, the device Device WDT wakes up and resumes operation. The TO and PD bits WDTE<1:0> SWDTEN Mode Mode in the STATUS register are changed to indicate the event. The RWDT bit in the PCON register can also be 11 X X Active used. See Section 3.0“Memory Organization” for Awake Active more information. 10 X Sleep Disabled 1 X Active 01 0 X Disabled 00 X X Disabled TABLE 9-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0>=00 WDTE<1:0>=01 and SWDTEN = 0 WDTE<1:0>=10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF<3:0> bits) Unaffected DS40001723D-page 88  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 9.6 Register Definitions: Watchdog Control REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0 — — WDTPS<4:0> SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved; results in minimum interval (1:32) • • • 10011 = Reserved; results in minimum interval (1:32) 10010 = 1:8388608 (223) (Interval 256s nominal) 10001 = 1:4194304 (222) (Interval 128s nominal) 10000 = 1:2097152 (221) (Interval 64s nominal) 01111 = 1:1048576 (220) (Interval 32s nominal) 01110 = 1:524288 (219) (Interval 16s nominal) 01101 = 1:262144 (218) (Interval 8s nominal) 01100 = 1:131072 (217) (Interval 4s nominal) 01011 = 1:65536 (Interval 2s nominal) (Reset value) 01010 = 1:32768 (Interval 1s nominal) 01001 = 1:16384 (Interval 512ms nominal) 01000 = 1:8192 (Interval 256ms nominal) 00111 = 1:4096 (Interval 128ms nominal) 00110 = 1:2048 (Interval 64ms nominal) 00101 = 1:1024 (Interval 32ms nominal) 00100 = 1:512 (Interval 16ms nominal) 00011 = 1:256 (Interval 8ms nominal) 00010 = 1:128 (Interval 4ms nominal) 00001 = 1:64 (Interval 2ms nominal) 00000 = 1:32 (Interval 1ms nominal) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 1x: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.  2013-2015 Microchip Technology Inc. DS40001723D-page 89

PIC12(L)F1571/2 TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 55 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 66 STATUS — — — TO PD Z DC C 19 WDTCON — — WDTPS<4:0> SWDTEN 89 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer. TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page CONFIG1 13:8 — — — — CLKOUTEN BOREN<1:0> — 42 7:0 CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer. DS40001723D-page 90  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 10.0 FLASH PROGRAM MEMORY 10.1 PMADRL and PMADRH Registers CONTROL The PMADRH:PMADRL register pair can address up to a maximum of 16K words of program memory. When The Flash program memory is readable and writable selecting a program address value, the MSB of the during normal operation over the full VDD range. address is written to the PMADRH register and the LSB Program memory is indirectly addressed using Special is written to the PMADRL register. Function Registers (SFRs). The SFRs used to access program memory are: 10.1.1 PMCON1 AND PMCON2 • PMCON1 REGISTERS • PMCON2 PMCON1 is the control register for Flash program • PMDATL memory accesses. • PMDATH Control bits, RD and WR, initiate read and write, • PMADRL respectively. These bits cannot be cleared, only set, in • PMADRH software. They are cleared by hardware at completion When accessing the program memory, the of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the termination of a write operation. PMADRH:PMADRL register pair forms a 2-byte word The WREN bit, when set, will allow a write operation to that holds the 15-bit address of the program memory occur. On power-up, the WREN bit is clear. The location being read. WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. pump. The Flash program memory can be protected in two The PMCON2 register is a write-only register. Attempting ways; by code protection (CP bit in the Configuration to read the PMCON2 register will return all ‘0’s. Words) and write protection (WRT<1:0> bits in the To enable writes to the program memory, a specific Configuration Words). pattern (the unlock sequence), must be written to the Code protection (CP = 0) disables access, reading and PMCON2 register. The required unlock sequence writing, to the Flash program memory via external prevents inadvertent writes to the program memory device programmers. Code protection does not affect write latches and Flash program memory. the self-write and erase functionality. Code protection can only be reset by a device programmer performing 10.2 Flash Program Memory Overview a bulk erase to the device, clearing all Flash program memory, Configuration bits and User IDs.(1) It is important to understand the Flash program memory structure for erase and programming operations. Flash Write protection prohibits self-write and erase to a program memory is arranged in rows. A row consists of portion or all of the Flash program memory as defined a fixed number of 14-bit program memory words. A row by the bits WRT<1:0>. Write protection does not affect is the minimum size that can be erased by user software. a device programmers ability to read, write or erase the After a row has been erased, the user can reprogram device. all or a portion of this row. Data to be written into the Note 1: Code protection of the entire Flash program memory row is written to 14-bit wide data write program memory array is enabled by latches. These write latches are not directly accessible clearing the CP bit of the Configuration to the user, but may be loaded via sequential writes to Words. the PMDATH:PMDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations.  2013-2015 Microchip Technology Inc. DS40001723D-page 91

PIC12(L)F1571/2 See Table10-1 for erase row size and the number of FIGURE 10-1: FLASH PROGRAM write latches for Flash program memory. MEMORY READ FLOWCHART TABLE 10-1: FLASH MEMORY Rev.10-000046A ORGANIZATION BY DEVICE 7/30/2013 Write Row Erase Start Device Latches ReadOperation (words) (words) PIC12(L)F1571 16 16 PIC12(L)F1572 Select ProgramorConfigurationMemory (CFGS) 10.2.1 READING THE FLASH PROGRAM MEMORY Select To read a program memory location, the user must: WordAddress 1. Write the desired address to the (PMADRH:PMADRL) PMADRH:PMADRL register pair. 2. Clear the CFGS bit of the PMCON1 register. 3. Then, set control bit, RD, of the PMCON1 register. InitiateReadoperation (RD=1) Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction Instructionfetchedignored to be ignored. The data is available in the very next cycle NOP executionforced in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. The PMDATH:PMDATL register pair will hold this value Instructionfetchedignored until another read or until it is written to by the user. NOPexecutionforced Note: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a Datareadnowin 2-cycle instruction on the next instruction PMDATH:PMDATL after the RD bit is set. End ReadOperation DS40001723D-page 92  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Flash ADDR PC PC + 1 PMADRH,PMADRL PPCC ++ 33 PC + 4 PC + 5 Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4) INSTR(PC + 1) INSTR(PC + 2) INSTR(PC – 1) BSF PMCON1,RD Instruction Ignored, Instruction Ignored, INSTR(PC + 3) INSTR(PC + 4) Executed Here Executed Here Forced NOP Forced NOP Executed Here Executed Here Executed Here Executed Here RD bit PMDATH PMDATL Register EXAMPLE 10-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL PMADRL ; Select Bank for PMCON registers MOVLW PROG_ADDR_LO ; MOVWF PMADRL ; Store LSB of address MOVLW PROG_ADDR_HI ; MOVWF PMADRH ; Store MSB of address BCF PMCON1,CFGS ; Do not select Configuration Space BSF PMCON1,RD ; Initiate read NOP ; Ignored (Figure 10-2) NOP ; Ignored (Figure 10-2) MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location  2013-2015 Microchip Technology Inc. DS40001723D-page 93

PIC12(L)F1571/2 10.2.2 FLASH MEMORY UNLOCK FIGURE 10-3: FLASH PROGRAM SEQUENCE MEMORY UNLOCK SEQUENCE FLOWCHART The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write Rev.10-000047A 7/30/2013 programming or erasing. The sequence must be exe- cuted and completed without interruption to successfully complete any of the following operations: Start • Row erase UnlockSequence • Load program memory write latches • Write of program memory write latches to program memory Write0x55to • Write of program memory write latches to User PMCON2 IDs The unlock sequence consists of the following steps: 1. Write 55h to PMCON2 Write0xAAto PMCON2 2. Write AAh to PMCON2 3. Set the WR bit in PMCON1 4. NOP instruction Initiate WriteorEraseoperation 5. NOP instruction (WR=1) Once the WR bit is set, the processor will always force two NOP instructions. When an erase row or program row operation is being performed, the processor will stall Instructionfetchedignored internal operations (typical 2 ms), until the operation is NOPexecutionforced complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next Instructionfetchedignored NOP executionforced instruction. Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is End completed. UnlockSequence DS40001723D-page 94  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 10.2.3 ERASING FLASH PROGRAM FIGURE 10-4: FLASH PROGRAM MEMORY MEMORY ERASE FLOWCHART While executing code, program memory can only be erased by rows. To erase a row: 1. Load the PMADRH:PMADRL register pair with Rev.10-000048A 7/30/2013 any address within the row to be erased. 2. Clear the CFGS bit of the PMCON1 register. Start 3. Set the FREE and WREN bits of the PMCON1 EraseOperation register. 4. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). DisableInterrupts 5. Set control bit, WR, of the PMCON1 register to (GIE=0) begin the erase operation. See Example10-2. After the “BSF PMCON1,WR” instruction, the processor Select ProgramorConfigurationMemory requires two cycles to set up the erase operation. The (CFGS) user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the SelectRowAddress clocks and peripherals will continue to run. After the (PMADRH:PMADRL) erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. SelectEraseOperation (FREE=1) EnableWrite/EraseOperation (WREN=1) UnlockSequence (SeeNote1) CPUstallswhile Eraseoperationcompletes (2mstypical) DisableWrite/EraseOperation (WREN=0) Re-enableInterrupts (GIE=1) End EraseOperation Note 1: See Figure10-3.  2013-2015 Microchip Technology Inc. DS40001723D-page 95

PIC12(L)F1571/2 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL PMADRL MOVF ADDRL,W ; Load lower 8 bits of erase address boundary MOVWF PMADRL MOVF ADDRH,W ; Load upper 6 bits of erase address boundary MOVWF PMADRH BCF PMCON1,CFGS ; Not configuration space BSF PMCON1,FREE ; Specify an erase operation BSF PMCON1,WREN ; Enable writes MOVLW 55h ; Start of required sequence to initiate erase MOVWF PMCON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0PPAMMACChOO NN21 ,WR ;;;; WSNreOitPt eWi RnA sAbthirtu cttoi obnesg ianr ee rfaosreced as processor starts NOP ; row erase of program memory. ; ; The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts DS40001723D-page 96  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 10.2.4 WRITING TO FLASH PROGRAM 1. Set the WREN bit of the PMCON1 register. MEMORY 2. Clear the CFGS bit of the PMCON1 register. Program memory is programmed using the following 3. Set the LWLO bit of the PMCON1 register. steps: When the LWLO bit of the PMCON1 register is ‘1’, the write sequence will only load the write 1. Load the address in PMADRH:PMADRL of the latches and will not initiate the write to Flash row to be programmed. program memory. 2. Load each write latch with data. 4. Load the PMADRH:PMADRL register pair with 3. Initiate a programming operation. the address of the location to be written. 4. Repeat Steps 1 through 3 until all data is written. 5. Load the PMDATH:PMDATL register pair with Before writing to program memory, the word(s) to be the program memory data to be written. written must be erased or previously unwritten. Pro- 6. Execute the unlock sequence gram memory can only be erased one row at a time. No (Section10.2.2 “Flash Memory Unlock automatic erase occurs upon the initiation of the write. Sequence”). The write latch is now loaded. Program memory can be written one or more words at 7. Increment the PMADRH:PMADRL register pair a time. The maximum number of words written at one to point to the next location. time is equal to the number of write latches. See 8. Repeat Steps 5 through 7 until all but the last Figure10-5 (row writes to program memory with write latch has been loaded. 16write latches) for more details. 9. Clear the LWLO bit of the PMCON1 register. The write latches are aligned to the Flash row When the LWLO bit of the PMCON1 register is address boundary defined by the upper 11 bits of ‘0’, the write sequence will initiate the write to PMADRH:PMADRL (PMADRH<6:0>:PMADRL<7:4>), Flash program memory. with the lower 4 bits of PMADRL (PMADRL<3:0>) 10. Load the PMDATH:PMDATL register pair with determining the write latch being loaded. Write opera- the program memory data to be written. tions do not cross these boundaries. At the completion 11. Execute the unlock sequence of a program memory write operation, the data in the (Section10.2.2 “Flash Memory Unlock write latches is reset to contain 0x3FFF. Sequence”). The entire program memory latch The following steps should be completed to load the content is now written to Flash program write latches and program a row of program memory. memory. These steps are divided into two parts. First, each write Note: The program memory write latches are latch is loaded with data from the PMDATH:PMDATL reset to the blank state (0x3FFF) at the using the unlock sequence with LWLO = 1. When the completion of every write or erase last word to be loaded into the write latch is ready, the operation. As a result, it is not necessary LWLO bit is cleared and the unlock sequence to load all the program memory write executed. This initiates the programming operation, latches. Unloaded latches will remain in writing all the latches into Flash program memory. the blank state. Note: The special unlock sequence is required An example of the complete write sequence is shown in to load a write latch with data or initiate a Example10-3. The initial address is loaded into the Flash programming operation. If the PMADRH:PMADRL register pair; the data is loaded unlock sequence is interrupted, writing to using Indirect Addressing. the latches or program memory will not be initiated.  2013-2015 Microchip Technology Inc. DS40001723D-page 97

D FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES P S 40 I 00 7 6 0 7 4 3 0 7 5 0 7 0 Rev.107-0/2050/020041B3 C 1 72 PMADRH PMADRL - - PMDATH PMDATL 1 3D 2 -p - rA r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c3 c2 c1 c0 6 8 ( ag L e 9 ) 8 F 14 1 5 ProgramMemoryWriteLatches 7 11 4 1 14 14 14 14 / 2 WriteLatch#0 WriteLatch#1 WriteLatch#14 WriteLatch#15 00h 01h 0Eh 0Fh PMADRL<3:0> 14 14 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 000Eh 000Fh 001h 0010h 0011h 001Eh 001Fh 002h 0020h 0021h 002Eh 002Fh CFGS=0  7FEh 7FE0h 7FE1h 7FEEh 7FEFh 2 0 1 Row 7FFh 7FF0h 7FF1h 7FFEh 7FFFh 3 -2 Address 01 PMADRH<6:0>: Decode FlashProgramMemory 5 M PMADRL<7:4> ic ro c hip 800h 8000h-8003h 8004h–8005h 8006h 8007h–8008h 8009h-801Fh T e DEVICEID Configuration ch CFGS=1 USERID0-3 reserved Dev/Rev Words reserved n o lo ConfigurationMemory g y In c .

PIC12(L)F1571/2 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words Enable Write/Erase to be written into Program or Operation (WREN = 1) Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Load the value to write (PMDATH:PMDATL) Update the word counter Write Latches to Flash Disable Interrupts (word_cnt--) (LWLO = 0) (GIE = 0) Unlock Sequence Select Program or Config. Memory Last word to Yes F(Figiguurere1 x0--x3) (CFGS) write ? No CPU stalls while Write Select Row Address operation completes (PMADRH:PMADRL) (2ms typical) Unlock Sequence F(Figiguurere1 x0--x3) Select Write Operation (FREE = 0) Disable No delay when writing to Write/Erase Operation Program Memory Latches (WREN = 0) Load Write Latches Only (LWLO = 1) Re-enable Interrupts (GIE = 1) Increment Address (PMADRH:PMADRL++) End Write Operation  2013-2015 Microchip Technology Inc. DS40001723D-page 99

PIC12(L)F1571/2 EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR ; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, ; stored in little endian format ; 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL ; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) ; BCF INTCON,GIE ; Disable ints so required sequences will execute properly BANKSEL PMADRH ; Bank 3 MOVF ADDRH,W ; Load initial address MOVWF PMADRH ; MOVF ADDRL,W ; MOVWF PMADRL ; MOVLW LOW DATA_ADDR ; Load initial data address MOVWF FSR0L ; MOVLW HIGH DATA_ADDR ; Load initial data address MOVWF FSR0H ; BCF PMCON1,CFGS ; Not configuration space BSF PMCON1,WREN ; Enable writes BSF PMCON1,LWLO ; Only Load Write Latches LOOP MOVIW FSR0++ ; Load first data byte into lower MOVWF PMDATL ; MOVIW FSR0++ ; Load second data byte into upper MOVWF PMDATH ; MOVF PMADRL,W ; Check if lower bits of address are '00000' XORLW 0x1F ; Check if we're on the last of 16 addresses ANDLW 0x1F ; BTFSC STATUS,Z ; Exit if last of 16 words, GOTO START_WRITE ; MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0PPAMMACChOO NN21 ,WR ;;;; SWNerOitPt WeiR n AsbAtihrtu cttoi obnesg ianr ew rfiotreced as processor ; loads program memory write latches NOP ; INCF PMADRL,F ; Still loading latches Increment address GOTO LOOP ; Write next latches START_WRITE BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program ; memory write MOVLW 55h ; Start of required write sequence: MOVWF PMCON2 ; Write 55h RequiredSequence MMBNOOSOVVFPLW WF 0PPAMMACChOO NN21 ,WR ;;;; SWNerOitPt WeiR n AsbAtihrtu cttoi obnesg ianr ew rfiotreced as processor writes ; all the program memory write latches simultaneously NOP ; to program memory. ; After NOPs, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction BCF PMCON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts DS40001723D-page 100  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 10.3 Modifying Flash Program Memory FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY When modifying existing data in a program memory FLOWCHART row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: Rev.107-0/3000/025001A3 1. Load the starting address of the row to be modified. Start ModifyOperation 2. Read the existing data from the row into a RAM image. 3. Modify the RAM image to contain the new data to be written into program memory. ReadOperation (SeeNote1) 4. Load the starting address of the row to be rewritten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM Animageoftheentirerow image. readmustbestoredinRAM 7. Initiate a programming operation. ModifyImage Thewordstobemodifiedare changedintheRAMimage EraseOperation (SeeNote2) WriteOperation UseRAMimage (SeeNote3) End ModifyOperation Note 1: See Figure10-2. 2: See Figure10-4. 3: See Figure10-6.  2013-2015 Microchip Technology Inc. DS40001723D-page 101

PIC12(L)F1571/2 10.4 User ID, Device ID and When read access is initiated on an address outside the Configuration Word Access parameters listed in Table10-2, the PMDATH:PMDATL register pair is cleared, reading back ‘0’s. Instead of accessing program memory, the User IDs, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15>=1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table10-2. TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS=1) Address Function Read Access Write Access 8000h-8003h User IDs Yes Yes 8006h/8005h Device ID/Revision ID Yes No 8007h-8008h Configuration Words 1 and 2 Yes No EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL PMADRL ; Select correct Bank MOVLW PROG_ADDR_LO ; MOVWF PMADRL ; Store LSB of address CLRF PMADRH ; Clear MSB of address BSF PMCON1,CFGS ; Select Configuration Space BCF INTCON,GIE ; Disable interrupts BSF PMCON1,RD ; Initiate read NOP ; Executed (See Figure 10-2) NOP ; Ignored (See Figure 10-2) BSF INTCON,GIE ; Restore interrupts MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS40001723D-page 102  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Rev.10-000051A 7/30/2013 Start VerifyOperation Thisroutineassumesthatthelast rowofdatawrittenwasfroman imagesavedonRAM.Thisimage willbeusedtoverifythedata currentlystoredinFlashProgram Memory ReadOperation (SeeNote1) PMDAT= No RAMimage? Yes Fail VerifyOperation No Lastword? Yes End VerifyOperation Note 1: See Figure10-1.  2013-2015 Microchip Technology Inc. DS40001723D-page 103

PIC12(L)F1571/2 10.6 Register Definitions: Flash Program Memory Control REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PMDAT<7:0>: Read/Write Value for Least Significant bits of Program Memory bits REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — PMDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDAT<13:8>: Read/Write Value for Most Significant bits of Program Memory bits DS40001723D-page 104  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PMADR<7:0>: Specifies Least Significant bits for Program Memory Address bits REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 —(1) PMADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘1’(1) bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for Program Memory Address bits Note 1: Unimplemented, read as ‘1’.  2013-2015 Microchip Technology Inc. DS40001723D-page 105

PIC12(L)F1571/2 REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 —(1) CFGS LWLO(3) FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Hardware Clearable bit bit 7 Unimplemented: Read as ‘1’(1) bit 6 CFGS: Configuration Select bit 1 = Accesses Configuration, User ID and Device ID registers 0 = Accesses Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs a write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit(2) 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (writes ‘1’) of the WR bit) 0 = The program or erase operation completed normally bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive bit 0 RD: Read Control bit 1 = Initiates a program Flash read Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read Note 1: Unimplemented bit, read as ‘1’. 2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). 3: The LWLO bit is ignored during a program memory erase operation (FREE = 1). DS40001723D-page 106  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can only be set x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PMCON1 —(1) CFGS LWLO FREE WRERR WREN WR RD 106 PMCON2 Program Memory Control Register 2 107 PMADRL PMADRL<7:0> 105 PMADRH —(1) PMADRH<6:0> 105 PMDATL PMDATL<7:0> 104 PMDATH — — PMDATH<5:0> 104 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory. Note 1: Unimplemented, read as ‘1’. TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — — — CLKOUTEN BOREN<1:0> — CONFIG1 42 7:0 CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0> 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN CONFIG2 43 7:0 — — — — — — WRT<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.  2013-2015 Microchip Technology Inc. DS40001723D-page 107

PIC12(L)F1571/2 NOTES: DS40001723D-page 108  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 11.0 I/O PORTS Ports that support analog inputs have an associated ANSELx register. When an ANSELx bit is set, the Each port has three standard registers for its operation. digital input buffer associated with that bit is disabled. These registers are: Disabling the input buffer prevents analog signal levels • TRISx registers (Data Direction) on the pin between a logic high and low from causing excessive current in the logic input circuitry. A • PORTx registers (reads the levels on the pins of simplified model of a generic I/O port, without the the device) interfaces to other peripherals, is shown in Figure11-1. • LATx registers (Output Latch) • INLVLx (Input Level Control) FIGURE 11-1: GENERIC I/O PORT • ODCONx registers (Open-Drain Control) OPERATION • SLRCONx registers (Slew Rate Control) Some ports may have one or more of the following Rev.107-0/3000/025021A3 additional registers. These registers are: ReadLATx • ANSELx (Analog Select) • WPUx (Weak Pull-up) TRISx In general, when a peripheral is enabled on a port pin, D Q that pin cannot be used as a general purpose output. WriteLATx However, the pin can still be read. WritePORTx VDD CK TABLE 11-1: PORT AVAILABILITY PER DataRegister DEVICE Databus A I/Opin T Device R ReadPORTx O P Todigitalperipherals PIC12(L)F1571 ● ANSELx PIC12(L)F1572 ● Toanalogperipherals The Data Latch (LATx registers) is useful for VSS Read-Modify-Write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads the values held in the I/O port latches, while a read of the PORTx register reads the actual I/O pin value.  2013-2015 Microchip Technology Inc. DS40001723D-page 109

PIC12(L)F1571/2 11.1 Alternate Pin Function These bits have no effect on the values of any TRISx register. PORTx and TRISx overrides will be routed to The Alternate Pin Function Control (APFCON) register the correct pin. The unselected pin will be unaffected. is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register11-1. For this device family, the following functions can be moved between different pins. • RX/DT • TX/CK • CWGOUTA • CWGOUTB • PWM2 • PWM1 11.2 Register Definitions: Alternate Pin Function Control REGISTER 11-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RXDTSEL CWGASEL CWGBSEL — T1GSEL TXCKSEL P2SEL P1SEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 RXDTSEL: Pin Selection bit 1 = RX/DT function is on RA5 0 = RX/DT function is on RA1 bit 6 CWGASEL: Pin Selection bit 1 = CWGOUTA function is on RA5 0 = CWGOUTA function is on RA2 bit 5 CWGBSEL: Pin Selection bit 1 = CWGOUTB function is on RA4 0 = CWGOUTB function is on RA0 bit 4 Unimplemented: Read as ‘0’ bit 3 T1GSEL: Pin Selection bit 1 = T1G function is on RA3 0 = T1G function is on RA4 bit 2 TXCKSEL: Pin Selection bit 1 = TX/CK function is on RA4 0 = TX/CK function is on RA0 bit 1 P2SEL: Pin Selection bit 1 = PWM2 function is on RA4 0 = PWM2 function is on RA0 bit 0 P1SEL: Pin Selection bit 1 = PWM1 function is on RA5 0 = PWM1 function is on RA1 DS40001723D-page 110  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 11.3 PORTA Registers 11.3.5 INPUT THRESHOLD CONTROL The INLVLA register (Register11-9) controls the input 11.3.1 DATA REGISTER voltage threshold for each of the available PORTA input PORTA is a 6-bit wide, bidirectional port. The pins. A selection between the Schmitt Trigger CMOS or corresponding Data Direction register is TRISA the TTL compatible thresholds is available. The input (Register11-3). Setting a TRISA bit (= 1) will make the threshold is important in determining the value of a corresponding PORTA pin an input (i.e., disable the read of the PORTA register and also the level at which output driver). Clearing a TRISA bit (= 0) will make the an Interrupt-On-Change occurs, if that feature is corresponding PORTA pin an output (i.e., enables enabled. See Section26.3“DC Characteristics” for output driver and puts the contents of the output latch more information on threshold levels. on the selected pin). The exception is RA3, which is Note: Changing the input threshold selection input-only and its TRISA bit will always read as ‘1’. should be performed while all peripheral Example11-1 shows how to initialize an I/O port. modules are disabled. Changing the Reading the PORTA register (Register11-2) reads the threshold level during the time a module is status of the pins, whereas writing to it will write to the active may inadvertently generate a transi- PORT latch. All write operations are Read-Modify-Write tion associated with an input pin, regardless operations. Therefore, a write to a port implies that the of the actual voltage level on that pin. port pins are read, this value is modified and then written to the Port Data Latch (LATA). 11.3.6 ANALOG CONTROL 11.3.2 DIRECTION CONTROL The ANSELA register (Register11-5) is used to configure the Input mode of an I/O pin to analog. The TRISA register (Register11-3) controls the Setting the appropriate ANSELA bit high will cause all PORTA pin output drivers, even when they are being digital reads on the pin to be read as ‘0’ and allow used as analog inputs. The user should ensure the bits analog functions on the pin to operate correctly. in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog The state of the ANSELA bits has no effect on digital out- input always read ‘0’. put functions. A pin with TRIS clear and ANSELA set will still operate as a digital output, but the Input mode will be 11.3.3 OPEN-DRAIN CONTROL analog. This can cause unexpected behavior when The ODCONA register (Register11-7) controls the executing Read-Modify-Write instructions on the open-drain feature of the port. Open-drain operation is affected port. independently selected for each pin. When an Note: The ANSELA bits default to the Analog ODCONA bit is set, the corresponding port output mode after Reset. To use any pins as becomes an open-drain driver capable of sinking digital general purpose or peripheral current only. When an ODCONA bit is cleared, the inputs, the corresponding ANSELA bits corresponding port output pin is the standard push-pull must be initialized to ‘0’ by user software. drive capable of sourcing and sinking current. 11.3.4 SLEW RATE CONTROL EXAMPLE 11-1: INITIALIZING PORTA BANKSEL PORTA ; The SLRCONA register (Register11-8) controls the CLRF PORTA ;Init PORTA slew rate option for each port pin. Slew rate control is BANKSEL LATA ;Data Latch independently selectable for each port pin. When an CLRF LATA ; SLRCONA bit is set, the corresponding port pin drive is BANKSEL ANSELA ; slew rate limited. When an SLRCONA bit is cleared, CLRF ANSELA ;digital I/O the corresponding port pin drive slews at the maximum BANKSEL TRISA ; rate possible. MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA ;and set RA<2:0> as ;outputs  2013-2015 Microchip Technology Inc. DS40001723D-page 111

PIC12(L)F1571/2 11.3.7 PORTA FUNCTIONS AND OUTPUT TABLE 11-2: PORTA OUTPUT PRIORITY PRIORITIES Pin Name Function Priority(1) Each PORTA pin is multiplexed with other functions. The RA0 ICSPDAT pins, their combined functions and their output priorities CWG1B(3) are shown in Table11-2. DAC1OUT When multiple outputs are enabled, the actual pin TX(2,3) control goes to the peripheral with the highest priority. PWM2(3) RA0 Analog input functions, such as ADC and comparator RA1 PWM1(3) inputs, are not shown in the priority lists. These inputs RA1 are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may RA2 CWG1A control the pin when it is in Analog mode with the CWG1FLT C1OUT priority shown below in Table11-2. PWM3 RA2 RA3 None RA4 CLKOUT CWG1B TX(2) PWM2 RA4 RA5 CWG1A PWM1 RA5 Note 1: Priority listed from highest to lowest. 2: PIC12(L)F1572 only. 3: Default pin (see APFCON register). DS40001723D-page 112  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 11.4 Register Definitions: PORTA REGISTER 11-2: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from the PORTA register are the return of actual I/O pin values. REGISTER 11-3: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISA<5:4> —(1) TRISA<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 TRISA<5:4>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 Unimplemented: Read as ‘1’(1) bit 2-0 TRISA<2:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: Unimplemented, read as ‘1’.  2013-2015 Microchip Technology Inc. DS40001723D-page 113

PIC12(L)F1571/2 REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA<5:4>(1) — LATA<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented: Read as ‘0’ bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from the PORTA register are the return of actual I/O pin values. REGISTER 11-5: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — ANSA4 — ANSA<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-5 Unimplemented: Read as ‘0’ bit 4 ANSA4: Analog Select Between Analog or Digital Function on RA4 Pins (respectively) bit 1 = Analog input; pin is assigned as analog input, digital input buffer is disabled(1) 0 = Digital I/O; pin is assigned to port or digital special function bit 3 Unimplemented: Read as ‘0’ bit 2-0 ANSA<2:0>: Analog Select Between Analog or Digital Function on RA<2:0> pins (respectively) bits 1 = Analog input; pin is assigned as analog input, digital input buffer is disabled(1) 0 = Digital I/O; pin is assigned to port or digital special function Note 1: When setting a pin to an analog input, the corresponding TRISx bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001723D-page 114  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA<5:0>(1,2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(1,2,3) 1 = Pull-up is enabled 0 = Pull-up is disabled Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is configured as an output. 3: For the WPUA3 bit, when MCLRE = 1, the weak pull-up is internally enabled, but not reported here. REGISTER 11-7: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — ODA<5:4> — ODA<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ODA<5:4>: PORTA Open-Drain Enable bits For RA<5:4> Pins, Respectively: 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 3 Unimplemented: Read as ‘0’ bit 2-0 ODA<2:0>: PORTA Open-Drain Enable bits For RA<2:0> Pins, Respectively: 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current)  2013-2015 Microchip Technology Inc. DS40001723D-page 115

PIC12(L)F1571/2 REGISTER 11-8: SLRCONA: PORTA SLEW RATE CONTROL REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — SLRA<5:4> — SLRA<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits For RA<5:4> Pins, Respectively: 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 3 Unimplemented: Read as ‘0’ bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits For RA<2:0> Pins, Respectively: 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 11-9: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits For RA<5:0> Pins, Respectively: 1 = ST input is used for PORT reads and Interrupt-On-Change 0 = TTL input is used for PORT reads and Interrupt-On-Change DS40001723D-page 116  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA<2:0> 114 APFCON RXDTSEL CWGASEL CWGBSEL — T1GSEL TXCKSEL P2SEL P1SEL 110 INLVLA — — INLVLA<5:0> 116 LATA — — LATA<5:4> — LATA<2:0> 114 ODCONA — — ODA<5:4> — ODA<2:0> 115 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 157 PORTA — — RA<5:0> 113 SLRCONA — — SLRA<5:4> — SLRA<2:0> 116 TRISA — — TRISA<5:4> —(1) TRISA<2:0> 113 WPUA — — WPUA<5:0> 115 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Note 1: Unimplemented, read as ‘1’. TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH PORTA Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> — CONFIG1 42 7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.  2013-2015 Microchip Technology Inc. DS40001723D-page 117

PIC12(L)F1571/2 NOTES: DS40001723D-page 118  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 12.0 INTERRUPT-ON-CHANGE 12.3 Interrupt Flags The PORTA and PORTB pins can be configured to The IOCAFx and IOCBFx bits located in the IOCAF and operate as Interrupt-On-Change (IOC) pins. An interrupt IOCBF registers, respectively, are status flags that can be generated by detecting a signal that has either a correspond to the Interrupt-On-Change pins of the rising edge or a falling edge. Any individual port pin, or associated port. If an expected edge is detected on an combination of port pins, can be configured to generate appropriately enabled pin, then the status flag for that pin an interrupt. The Interrupt-On-Change module has the will be set, and an interrupt will be generated if the IOCIE following features: bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCAFx and IOCBFx bits. • Interrupt-On-Change enable (Master Switch) • Individual pin configuration 12.4 Clearing Interrupt Flags • Rising and falling edge detection • Individual pin interrupt flags The individual status flags, (IOCAFx and IOCBFx bits), can be cleared by resetting them to zero. If another edge Figure12-1 is a block diagram of the IOC module. is detected during this clearing operation, the associated status flag will be set at the end of the sequence, 12.1 Enabling the Module regardless of the value actually being written. To allow individual port pins to generate an interrupt, the In order to ensure that no detected edge is lost while IOCIE bit of the INTCON register must be set. If the clearing flags, only AND operations masking out known IOCIE bit is disabled, the edge detection on the pin will changed bits should be performed. The following still occur, but an interrupt will not be generated. sequence is an example of what should be performed. 12.2 Individual Pin Configuration EXAMPLE 12-1: CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a MOVLW 0xff rising edge, the associated bit of the IOCxP register is XORWF IOCAF, W set. To enable a pin to detect a falling edge, the ANDWF IOCAF, F associated bit of the IOCxN register is set. A pin can be configured to detect rising and falling 12.5 Operation in Sleep edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. The Interrupt-On-Change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep.  2013-2015 Microchip Technology Inc. DS40001723D-page 119

PIC12(L)F1571/2 FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000037A 6/2/2014 IOCANx D Q R Q4Q1 edge detect RAx to data bus IOCAPx D Q data bus = D S Q IOCAFx 0 or 1 write IOCAFx R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q4 Q4Q1 Q4Q1 Q4Q1 Q4Q1 DS40001723D-page 120  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 12.6 Register Definitions: Interrupt-On-Change Control REGISTER 12-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP<5:0>: Interrupt-On-Change PORTA Positive Edge Enable bits 1 = Interrupt-On-Change is enabled on the pin for a positive going edge; IOCAFx bit and IOCIF flag will be set upon detecting an edge 0 = Interrupt-On-Change is disabled for the associated pin REGISTER 12-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAN<5:0>: Interrupt-On-Change PORTA Negative Edge Enable bits 1 = Interrupt-On-Change is enabled on the pin for a negative going edge; IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-On-Change is disabled for the associated pin  2013-2015 Microchip Technology Inc. DS40001723D-page 121

PIC12(L)F1571/2 REGISTER 12-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 — — IOCAF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAF<5:0>: Interrupt-On-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected or the user cleared the detected change TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA<2:0> 114 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 IOCAF — — IOCAF<5:0> 122 IOCAN — — IOCAN<5:0> 121 IOCAP — — IOCAP<5:0> 121 TRISA — — TRISA<5:4> —(1) TRISA<2:0> 113 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-On-Change. Note 1: Unimplemented, read as ‘1’. DS40001723D-page 122  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 13.0 FIXED VOLTAGE REFERENCE The ADFVR<1:0> bits of the FVRCON register are (FVR) used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Refer- The Fixed Voltage Reference (FVR) is a stable voltage ence Section15.0“Analog-to-Digital Converter reference, independent of VDD, with a nominal output (ADC) Module” for additional information. level (VFVR) of 1.024V. The output of the FVR can be The CDAFVR<1:0> bits of the FVRCON register are configured to supply a reference voltage to the used to enable and configure the gain amplifier settings following: for the reference supplied to the comparator modules. • ADC input channel Reference Section17.0“Comparator Module” for • Comparator positive input additional information. • Comparator negative input To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by The FVR can be enabled by setting the FVREN bit of clearing the Buffer Gain Selection bits. the FVRCON register. 13.2 FVR Stabilization Period 13.1 Independent Gain Amplifier The FVR can be enabled by setting the FVREN bit of The output of the FVR supplied to the peripherals, the FVRCON register. (listed above), is routed through a programmable gain amplifier. Each amplifier can be programmed for a gain When the Fixed Voltage Reference module is enabled, it of 1x, 2x or 4x, to produce the three possible voltage requires time for the reference and amplifier circuits to levels. stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See the FVR Stabilization Period characterization graph, Figure27-21. FIGURE 13-1: VOLTAGE REFERENCE BLOCK DIAGRAM Rev. 10-000053A 8/6/2013 2 ADFVR<1:0> 1x FVR_buffer1 2x (To ADC Module) 4x 2 CDAFVR<1:0> 1x FVR_buffer2 2x (To Comparators) 4x FVREN + _ FVRRDY Note 1 Note 1: Any peripheral requiring the Fixed Voltage Reference (see Table13-1).  2013-2015 Microchip Technology Inc. DS40001723D-page 123

PIC12(L)F1571/2 TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral Conditions Description HFINTOSC FOSC<2:0> = 010 and INTOSC is active and device is not in Sleep. IRCF<3:0> = 000x BOREN<1:0> = 11 BOR is always enabled. BOR BOREN<1:0> = 10 and BORFS = 1 BOR is disabled in Sleep mode, BOR Fast Start is enabled. BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start is enabled. LDO All PIC12F1571/2 devices, when The device runs off of the Low-Power Regulator when in VREGPM = 1 and not in Sleep Sleep mode. DS40001723D-page 124  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 13.3 Register Definitions: FVR Control REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVREN(1) FVRRDY(2) TSEN(3) TSRNG(3) CDAFVR<1:0>(1) ADFVR<1:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit(1) 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(2) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature indicator is enabled 0 = Temperature indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD – 4VT (High Range) 0 = VOUT = VDD – 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits(1) 11 = Comparator FVR Buffer Gain is 4x, with output VCDAFVR = 4x VFVR(4) 10 = Comparator FVR Buffer Gain is 2x, with output VCDAFVR = 2x VFVR(4) 01 = Comparator FVR Buffer Gain is 1x, with output VCDAFVR = 1x VFVR 00 = Comparator FVR Buffer is off bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit(1) 11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(4) 10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(4) 01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR 00 = ADC FVR Buffer is off Note 1: To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by clearing the Buffer Gain Selection bits. 2: FVRRDY is always ‘1’ for the PIC12F1571/2 devices. 3: See Section14.0 “Temperature Indicator Module” for additional information. 4: Fixed Voltage Reference output cannot exceed VDD. TABLE 13-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR>1:0> ADFVR<1:0> 125  2013-2015 Microchip Technology Inc. DS40001723D-page 125

PIC12(L)F1571/2 NOTES: DS40001723D-page 126  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 14.0 TEMPERATURE INDICATOR FIGURE 14-1: TEMPERATURE CIRCUIT MODULE DIAGRAM This family of devices is equipped with a temperature Rev. 10-000069A circuit designed to measure the operating temperature VDD 7/31/2013 of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device TSEN temperature. The output of the temperature indicator is internally connected to the device ADC. The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, TSRNG depending on the level of calibration performed. A one- point calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal VOUT To ADC Temperature Indicator” (DS00001333) for more details Temp. Indicator regarding the calibration process. 14.1 Circuit Operation Figure14-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is 14.2 Minimum Operating VDD achieved by measuring the forward voltage drop across When the temperature circuit is operated in low range, multiple silicon junctions. the device may be operated at any operating voltage Equation14-1 describes the output characteristics of that is within specifications. the temperature indicator. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high EQUATION 14-1: VOUT RANGES enough to ensure that the temperature circuit is correctly biased. High Range: VOUT = VDD – 4 VT Table14-1 shows the recommended minimum VDD vs. Low Range: VOUT = VDD – 2 VT range setting. TABLE 14-1: RECOMMENDED VDD VS. The temperature sense circuit is integrated with the RANGE Fixed Voltage Reference (FVR) module. See Section13.0“Fixed Voltage Reference (FVR)” for Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 more information. 3.6V 1.8V The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no 14.3 Temperature Output current. The output of the circuit is measured using the The circuit operates in either high or low range. The high internal Analog-to-Digital Converter. A channel is range, selected by setting the TSRNG bit of the reserved for the temperature circuit output. Refer to FVRCON register, provides a wider output voltage. This Section15.0“Analog-to-Digital Converter (ADC) provides more resolution over the temperature range, Module” for detailed information. but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a 14.4 ADC Acquisition Time higher VDD is needed. The low range is selected by clearing the TSRNG bit of To ensure accurate temperature measurements, the the FVRCON register. The low range generates a lower user must wait at least 200 s after the ADC input voltage drop and thus, a lower bias voltage is needed multiplexer is connected to the temperature indicator to operate the circuit. The low range is provided for output before the conversion is performed. In addition, low-voltage operation. the user must wait 200 s between sequential conversions of the temperature indicator output.  2013-2015 Microchip Technology Inc. DS40001723D-page 127

PIC12(L)F1571/2 TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 118 Legend: Shaded cells are unused by the temperature indicator module. DS40001723D-page 128  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 15.0 ANALOG-TO-DIGITAL The ADC voltage reference is software selectable to be CONVERTER (ADC) MODULE either internally generated or externally supplied. The ADC can generate an interrupt upon completion of The Analog-to-Digital Converter (ADC) allows a conversion. This interrupt can be used to wake-up the conversion of an analog input signal to a 10-bit binary device from Sleep. representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure15-1 shows the block diagram of the ADC. FIGURE 15-1: ADC BLOCK DIAGRAM VDD ADPREF Rev.10-000033A 7/30/2013 Positive VDD Reference Select VREF+pin ADCS<2:0> AN0 VSS ANa VRNEG VRPOS External . Channel . FOSC/nDFivoisdcer FOSC Inputs ADC ADC_clk . sampled Clock ANz input Select FRC FRC TempIndicator Internal Channel DACx_output ADCCLOCKSOURCE Inputs FVR_buffer1 ADC SampleCircuit CHS<4:0> ADFM setbitADIF 10 complete 10-bitResult Writetobit GO/DONE GO/DONE Q1 16 start Q4 ADRESH ADRESL Q2 Enable TriggerSelect TRIGSEL<3:0> ADON . . . VSS TriggerSources AUTOCONVERSION TRIGGER  2013-2015 Microchip Technology Inc. DS40001723D-page 129

PIC12(L)F1571/2 15.1 ADC Configuration 15.1.4 CONVERSION CLOCK When configuring and using the ADC the following The source of the conversion clock is software-selectable functions must be considered: via the ADCSx bits of the ADCON1 register. There are seven possible clock options: • Port configuration • FOSC/2 • Channel selection • FOSC/4 • ADC voltage reference selection • FOSC/8 • ADC conversion clock source • FOSC/16 • Interrupt control • FOSC/32 • Result formatting • FOSC/64 15.1.1 PORT CONFIGURATION • FRC (internal Fast RC oscillator) The ADC can be used to convert both analog and The time to complete one bit conversion is defined as digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD pin should be configured for analog by setting the periods, as shown in Figure15-2. associated TRISx and ANSELx bits. Refer to For correct conversion, the appropriate TAD specification Section11.0“I/O Ports” for more information. must be met. Refer to the ADC conversion requirements Note: Analog voltages on any pin that is defined in Section26.0“Electrical Specifications” for more as a digital input may cause the input information. Table15-1 gives examples of appropriate buffer to conduct excess current. ADC clock selections. Note: Unless using the FRC, any changes in the 15.1.2 CHANNEL SELECTION system clock frequency will change the ADC clock frequency, which may There are 7 channel selections available: adversely affect the ADC result. • AN<3:0> pins • Temperature Indicator • DAC1_output • FVR_buffer1 The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay (TACQ) is required before starting the next conversion. Refer to Section15.2.6“ADC Conversion Procedure” for more information. 15.1.3 ADC VOLTAGE REFERENCE The ADC module uses a positive and a negative voltage reference. The positive reference is labeled ref+ and the negative reference is labeled ref-. The positive voltage reference (ref+) is selected by the ADPREFx bits in the ADCON1 register. The positive voltage reference source can be: • VREF+ pin • VDD The negative voltage reference (ref-) source is: • VSS DS40001723D-page 130  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz Source Fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 s Fosc/4 100 200 ns 250 ns 500 ns 1.0 s 4.0 s Fosc/8 001 400 ns 500 ns 1.0 s 2.0 s 8.0 s Fosc/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s Fosc/32 010 1.6 s 2.0 s 4.0 s 8.0 s 32.0 s Fosc/64 110 3.2 s 4.0 s 8.0 s 16.0 s 64.0 s FRC x11 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s Legend: Shaded cells are outside of recommended range. Note: The TAD period when using the FRC clock source can fall within a specified range (see TAD parameter). The TAD period when using the FOSC-based clock source can be configured for a more precise TAD period. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES Rev.10-000035A 7/30/2013 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 THCD ConversionStarts TACQ Holdingcapacitordisconnected Onthefollowingcycle: fromanaloginput(THCD). ADRESH:ADRESLisloaded, GObitiscleared, SetGObit ADIFbitisset, holdingcapacitorisreconnectedtoanaloginput. EnableADC (ADONbit) and Selectchannel(ACSbits)  2013-2015 Microchip Technology Inc. DS40001723D-page 131

PIC12(L)F1571/2 15.1.5 INTERRUPTS 15.1.6 RESULT FORMATTING The ADC module allows for the ability to generate an The 10-bit ADC conversion result can be supplied in interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit conversion. The ADC Interrupt Flag is the ADIF bit in of the ADCON1 register controls the output format. the PIR1 register. The ADC Interrupt Enable is the Figure15-3 shows the two output formats. ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruc- tion is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execu- tion, the ADIE bit of the PIE1 register and the PEIE bit of the INTCON register must both be set, and the GIE bit of the INTCON register must be cleared. If all three of these bits are set, the execution will switch to the Interrupt Service Routine. FIGURE 15-3: 10-BIT ADC CONVERSION RESULT FORMAT Rev.10-000054A 7/30/2013 ADRESH ADRESL (ADFM=0) MSB LSB bit7 bit0 bit7 bit0 10-bitADCResult Unimplemented:Read as ‘0’ (ADFM=1) MSB LSB bit7 bit0 bit7 bit0 Unimplemented:Read as ‘0’ 10-bitADCResult DS40001723D-page 132  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 15.2 ADC Operation 15.2.5 AUTO-CONVERSION TRIGGER The auto-conversion trigger allows periodic ADC 15.2.1 STARTING A CONVERSION measurements without software intervention. When a To enable the ADC module, the ADON bit of the rising edge of the selected source occurs, the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit is set by hardware. GO/DONE bit of the ADCON0 register to a ‘1’ will start The auto-conversion trigger source is selected with the the Analog-to-Digital conversion. TRIGSEL<3:0> bits of the ADCON2 register. Note: The GO/DONE bit should not be set in the Using the auto-conversion trigger does not assure same instruction that turns on the ADC. proper ADC timing. It is the user’s responsibility to Refer to Section15.2.6“ADC Conversion ensure that the ADC timing requirements are met. Procedure”. The PWM module can trigger the ADC in two ways, directly through the PWMx_OFx_match or through the 15.2.2 COMPLETION OF A CONVERSION interrupts generated by all four match signals. See When the conversion is complete, the ADC module will: Section22.0 “16-Bit Pulse-Width Modulation (PWM) Module”. If the interrupts are chosen, each enabled • Clear the GO/DONE bit interrupt in PWMxINTE will trigger a conversion. Refer • Set the ADIF Interrupt Flag bit to Figure15-4 for more information. • Update the ADRESH and ADRESL registers with See Table15-2 for auto-conversion sources. new conversion result 15.2.3 TERMINATING A CONVERSION FIGURE 15-4: 16-BIT PWM INTERRUPT BLOCK DIAGRAM If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The Rev. 10-000154A 10/24/2013 ADRESH and ADRESL registers will be updated with OFx_match the partially complete Analog-to-Digital conversion PWMxOFIE sample. Incomplete bits will match the last bit PHx_match converted. PWMxPHIE PWMx_interrupt Note: A device Reset forces all registers to their DCx_match PWMxDCIE Reset state. Thus, the ADC module is turned off and any pending conversion is PRx_match PWMxPRIE terminated. 15.2.4 ADC OPERATION DURING SLEEP TABLE 15-2: AUTO-CONVERSION The ADC module can operate during Sleep. This SOURCES requires the ADC clock source to be set to the FRC option. Performing the ADC conversion during Sleep Source Peripheral Signal Name can reduce system noise. If the ADC interrupt is Timer0 T0_overflow enabled, the device will wake-up from Sleep when the Timer1 T1_overflow conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion Timer2 T2_match completes, although the ADON bit remains set. Comparator C1 C1OUT_sync When the ADC clock source is something other than PWM1 PWM1_OF_match FRC, a SLEEP instruction causes the present conver- PWM1 PWM1_interrupt sion to be aborted and the ADC module is turned off, PWM2 PWM2_OF_match although the ADON bit remains set. PWM2 PWM2_interrupt PWM3 PWM3_OF_match PWM3 PWM3_interrupt  2013-2015 Microchip Technology Inc. DS40001723D-page 133

PIC12(L)F1571/2 15.2.6 ADC CONVERSION PROCEDURE EXAMPLE 15-1: ADC CONVERSION This is an example procedure for using the ADC to ;This code block configures the ADC perform an Analog-to-Digital conversion: ;for polling, Vdd and Vss references, FRC ;oscillator and AN0 input. 1. Configure port: ; • Disable pin output driver (refer to the ;Conversion start & polling for completion TRISx register) ; are included. ; • Configure pin as analog (refer to the BANKSEL ADCON1 ; ANSELx register) MOVLW B’11110000’ ;Right justify, FRC • Disable weak pull-ups either globally (refer to ;oscillator the OPTION_REG register) or individually MOVWF ADCON1 ;Vdd and Vss Vref+ (refer to the appropriate WPUx register) BANKSEL TRISA ; 2. Configure the ADC module: BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; • Select ADC conversion clock BSF ANSEL,0 ;Set RA0 to analog • Configure voltage reference BANKSEL WPUA • Select ADC input channel BCF WPUA,0 ;Disable weak ;pull-up on RA0 • Turn on ADC module BANKSEL ADCON0 ; 3. Configure ADC interrupt (optional): MOVLW B’00000001’ ;Select channel AN0 • Clear ADC interrupt flag MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay • Enable ADC interrupt BSF ADCON0,ADGO ;Start conversion • Enable peripheral interrupt BTFSC ADCON0,ADGO ;Is conversion done? • Enable global interrupt(1) GOTO $-1 ;No, test again 4. Wait the required acquisition time.(2) BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits 5. Start conversion by setting the GO/DONE bit. MOVWF RESULTHI ;store in GPR space 6. Wait for ADC conversion to complete by one of BANKSEL ADRESL ; the following: MOVF ADRESL,W ;Read lower 8 bits • Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC result. 8. Clear the ADC interrupt flag (required if interrupt is enabled). Note1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section15.4“ADC Acquisition Requirements”. DS40001723D-page 134  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 15.3 Register Definitions: ADC Control REGISTER 15-1: ADCON0: ADC CONTROL REGISTER 0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — CHS<4:0> GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = Reserved; no channel connected • • • 11100 = Reserved; no channel connected 11101 =Temperature indicator(1) 11110 = DAC (Digital-to-Analog Converter)(2) 11111 = FVR (Fixed Voltage Reference) Buffer 1 output(3) bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle is in progress Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section14.0“Temperature Indicator Module” for more information. 2: See Section16.0“5-Bit Digital-to-Analog Converter (DAC) Module” for more information. 3: See Section13.0“Fixed Voltage Reference (FVR)” for more information.  2013-2015 Microchip Technology Inc. DS40001723D-page 135

PIC12(L)F1571/2 REGISTER 15-2: ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ADFM ADCS<2:0> — — ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 ADFM: ADC Result Format Select bit 1 = Right justified; six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded 0 = Left justified; six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from an internal RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from an internal RC oscillator) bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits 00 = VRPOS is connected to VDD 01 = Reserved 10 = VRPOS is connected to external VREF+ pin(1) 11 = VRPOS is connected to internal Fixed Voltage Reference (FVR) Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Section26.0“Electrical Specifications” for details. DS40001723D-page 136  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 15-3: ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 TRIGSEL<3:0>(1) — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = PWM1 – PWM1_interrupt 0010 = PWM2 – PWM2_interrupt 0011 = Timer0 – T0_overflow(2) 0100 = Timer1 – T1_overflow(2) 0101 = Timer2 – T2_match 0110 = Comparator C1 – C1OUT_sync 0111 = PWM3 – PWM3_interrupt 1000 = PWM1 – PWM1_OF1_match 1001 = PWM2 – PWM2_OF2_match 1010 = PWM3 – PWM3_OF3_match 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved bit 3-0 Unimplemented: Read as ‘0’ Note 1: This is a rising edge sensitive input for all sources. 2: Signal also sets its corresponding interrupt flag.  2013-2015 Microchip Technology Inc. DS40001723D-page 137

PIC12(L)F1571/2 REGISTER 15-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result. REGISTER 15-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<1:0> — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result. bit 5-0 Reserved: Do not use DS40001723D-page 138  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-2 Reserved: Do not use bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result. REGISTER 15-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result.  2013-2015 Microchip Technology Inc. DS40001723D-page 139

PIC12(L)F1571/2 15.4 ADC Acquisition Requirements Source Impedance is decreased, the acquisition time may be decreased. After the analog input channel is For the ADC to meet its specified accuracy, the Charge selected (or changed), an ADC acquisition must be Holding Capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate charge to the input channel voltage level. The Analog the minimum acquisition time, Equation15-1 may be Input model is shown in Figure15-5. The Source used. This equation assumes that 1/2 LSb error is used Impedance (RS) and the internal Sampling Switch (1,024 steps for the ADC). The 1/2 LSb error is the Impedance (RSS) directly affect the time required to maximum error allowed for the ADC to meet its charge the capacitor, CHOLD. The Sampling Switch specified resolution. Impedance (RSS) varies over the device voltage (VDD); refer to Figure15-5. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 15-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD TACQ = Amplifier Settling Time +Hold Capacitor Charging Time+Temperature Coefficient = TAMP+TC+TCOFF = 2µs+TC+Temperature - 25°C0.05µs/°C The value for TC can be approximated with the following equations:  1  VAPPLIED1– ------n----+----1------------ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb 2 –1 –TC  ---------- RC VAPPLIED1–e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED   –Tc  -R----C----  1  VAPPLIED1–e  = VAPPLIED1– ------n---+-----1------------ ;combining [1] and [2]   2  –1 Note: Where n = number of bits of the ADC. Solving for TC: TC = –CHOLDRIC+RSS+RS ln(1/2047) = –12.5pF1k+7k+10k ln(0.0004885) = 1.715µs Therefore: TACQ = 2µs+1.715µs+50°C- 25°C0.05µs/°C = 4.96µs Note1: The Reference Voltage (VRPOS) has no effect on the equation, since it cancels itself out. 2: The Charge Holding Capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification. DS40001723D-page 140  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 15-5: ANALOG INPUT MODEL Rev. 10-000070B 8/5/2014 VDD Sampling RS InApnuatl opgin VT(cid:167) 0.6V RIC(cid:148) 1K sSwSitchRSS ILEAKAGE(1) CHOLD= 12.5 pF VA CPIN VT(cid:167) 0.6V 5pF Ref- 6V Legend: CHOLD = Sample/Hold Capacitance 5V CPIN = Input Capacitance VDD 4V RSS ILEAKAGE = Leakage Current at the pin due to varies injunctions 3V 2V RIC = Interconnect Resistance RSS = Resistance of Sampling switch SS = Sampling Switch 5 6 7 8 91011 VT = Threshold Voltage Sampling Switch (k(cid:159) ) Note 1: Refer to Section26.0“Electrical Specifications”. FIGURE 15-6: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh 3FDh 3FCh e od 3FBh C ut p ut O C D 03h A 02h 01h 00h Analog Input Voltage 0.5 LSB 1.5 LSB Zero-Scale Ref- Transition Full-Scale Ref+ Transition  2013-2015 Microchip Technology Inc. DS40001723D-page 141

PIC12(L)F1571/2 TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON0 — CHS<4:0> GO/DONE ADON 135 ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 136 ADCON2 TRIGSEL<3:0> — — — — 137 ADRESH ADC Result Register High 138, 139 ADRESL ADC Result Register Low 138, 139 ANSELA — — — ANSA4 — ANSA<2:0> 114 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE1 TMR1GIE ADIE RCIE(2) TXIE(2) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(2) TXIF(2) — — TMR2IF TMR1IF 78 TRISA — — TRISA5 TRISA4 —(1) TRISA<2:0> 113 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 125 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the ADC module. Note 1: Unimplemented, read as ‘1’. 2: PIC12(L)F1572 only. DS40001723D-page 142  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 16.0 5-BIT DIGITAL-TO-ANALOG The output of the DAC (DACx_output) can be selected CONVERTER (DAC) MODULE as a reference voltage to the following: • Comparator positive input The Digital-to-Analog Converter supplies a variable • ADC input channel voltage reference, ratiometric with the input source, • DACxOUT1 pin with 32 selectable output levels. The Digital-to-Analog Converter (DAC) can be enabled The positive input source (VSOURCE+) of the DAC can by setting the DACEN bit of the DACxCON0 register. be connected to the: • External VREF+ pin • VDD supply voltage • FVR buffered output The negative input source (VSOURCE-) of the DAC can be connected to the: • Vss FIGURE 16-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Rev. 10-000026B 9/6/2013 VDD 00 VREF+ 01 VSOURCE+ FVR_buffer2 10 DACR<4:0> 5 Reserved 11 R DACPSS R DACEN R R X U 32 M DACx_output Steps 1 To Peripherals o- 2-t 3 R DACxOUT1 (1) R DACOE1 R VSOURCE- VSS Note 1:The unbuffered DACx_output is provided on the DACxOUT pin(s).  2013-2015 Microchip Technology Inc. DS40001723D-page 143

PIC12(L)F1571/2 16.1 Output Voltage Selection Reading the DACxOUTn pin when it has been configured for DAC reference voltage output will The DAC has 32 voltage level ranges. The 32 levels always return a ‘0’. are set with the DACR<4:0> bits of the DACxCON1 register. Note: The unbuffered DAC output (DACxOUTn) is not intended to drive an external load. The DAC output voltage can be determined by using Equation16-1. 16.4 Operation During Sleep 16.2 Ratiometric Output Level When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of The DAC output value is derived using a resistor ladder the DACxCON0 register are not affected. To minimize with each end of the ladder tied to a positive and current consumption in Sleep mode, the voltage negative voltage reference input source. If the voltage reference should be disabled. of either input source fluctuates, a similar fluctuation will result in the DAC output value. 16.5 Effects of a Reset The value of the individual resistors within the ladder can be found in Table26-16. A device Reset affects the following: • DACx is disabled. 16.3 DAC Voltage Reference Output • DACX output voltage is removed from the The unbuffered DAC voltage can be output to the DACxOUTn pin(s). DACxOUTn pin(s) by setting the respective DACOEn • The DACR<4:0> range select bits are cleared. bit(s) of the DACxCON0 register. Selecting the DAC reference voltage for output on either DACxOUTn pin automatically overrides the digital output buffer, the weak pull-up and digital input threshold detector functions of that pin. EQUATION 16-1: DAC OUTPUT VOLTAGE IF DACEN = 1  DACR4:0 DACx_output = VSOURCE+–VSOURCE------------------------------ +VSOURCE-  5  2 Note: See the DACxCON0 register for the available VSOURCE+ and VSOURCE- selections. DS40001723D-page 144  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 16.6 Register Definitions: DAC Control REGISTER 16-1: DACxCON0: DACx VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 DACEN — DACOE — DACPSS<1:0> — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 DACEN: DAC Enable bit 1 = DACx is enabled 0 = DACx is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DACOE: DAC Voltage Output Enable bit 1 = DACx voltage level is output on the DACxOUT1 pin 0 = DACx voltage level is disconnected from the DACxOUT1 pin bit 4 Unimplemented: Read as ‘0’ bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits 11 = Reserved 10 = FVR_buffer2 01 = VREF+ pin 00 = VDD bit 1-0 Unimplemented: Read as ‘0’ REGISTER 16-2: DACxCON1: DACx VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page DACxCON0 DACEN — DACOE — DACPSS<1:0> — — 145 DACxCON1 — — — DACR<4:0> 145 Legend: — = Unimplemented location, read as ‘0’.  2013-2015 Microchip Technology Inc. DS40001723D-page 145

PIC12(L)F1571/2 NOTES: DS40001723D-page 146  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 17.0 COMPARATOR MODULE 17.1 Comparator Overview Comparators are used to interface analog circuits to a A single comparator is shown in Figure17-2 along with digital circuit by comparing two analog voltages and the relationship between the analog input levels and providing a digital indication of their relative magnitudes. the digital output. When the analog voltage at VIN+ is Comparators are very useful mixed signal building less than the analog voltage at VIN-, the output of the blocks because they provide analog functionality inde- comparator is a digital low level. When the analog volt- pendent of program execution. The analog comparator age at VIN+ is greater than the analog voltage at VIN-, module includes the following features: the output of the comparator is a digital high level. • Independent comparator control The comparators available for this device are listed in Table17-1. • Programmable input selection • Comparator output is available internally/externally • Programmable output polarity TABLE 17-1: AVAILABLE COMPARATORS • Interrupt-On-Change Device C1 • Wake-up from Sleep PIC12(L)F1571 ● • Programmable speed/power optimization PIC12(L)F1572 ● • PWM shutdown • Programmable and Fixed Voltage Reference FIGURE 17-1: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM Rev. 10-000027C 9/6/2013 CxNCH<2:0> 3 CxON(1) Interrupt CxINTP Rising Edge set bit CxIN0- 000 CxIF Interrupt CxINTN CxIN1- 001 Falling Reserved 010 CxON(1) Edge Reserved 011 CxVN - CxOUT Reserved 100 D Q Cx MCxOUT Reserved 101 CxVP + FVR_buffer2 110 Q1 111 CxSP CxHYS CxPOL CxOUT_async to peripherals CxOUT_sync to peripherals CxIN+ 00 CxSYNC CxOE TRIS bit DAC_out 01 0 FVR_buffer2 10 CxOUT D Q 1 11 (From Timer1 Module) T1CLK CxPCH<1:0> CxON(1) 2 Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.  2013-2015 Microchip Technology Inc. DS40001723D-page 147

PIC12(L)F1571/2 FIGURE 17-2: SINGLE COMPARATOR 17.2.2 COMPARATOR POSITIVE INPUT SELECTION VIN+ + Configuring the CxPCH<1:0> bits of the CMxCON1 Output register directs an internal voltage reference or an VIN- – analog pin to the non-inverting input of the comparator: • CxIN+ analog pin • DAC1_output • FVR_buffer2 VIN- • VSS VIN+ See Section13.0“Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section16.0“5-Bit Digital-to-Analog Converter Output (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all Note: The black areas of the output of the comparator inputs are disabled. comparator represents the uncertainty 17.2.3 COMPARATOR NEGATIVE INPUT due to input offsets and response time. SELECTION The CxNCH<2:0> bits of the CMxCON0 register direct 17.2 Comparator Control one of the input sources to the comparator inverting input. The comparator has two control registers: CMxCON0 Note: To use CxIN+ and CxIN- pins as analog and CMxCON1. input, the appropriate bits must be set in the ANSELx register and the correspond- The CMxCON0 register (see Register17-1) contains ing TRISx bits must also be set to disable control and status bits for the following: the output drivers. • Enable • Output selection 17.2.4 COMPARATOR OUTPUT SELECTION • Output polarity The output of the comparator can be monitored by • Speed/power selection reading either the CxOUT bit of the CMxCON0 register • Hysteresis enable or the MCxOUT bit of the CMOUT register. In order to • Output synchronization make the output available for an external connection, the following conditions must be true: The CMxCON1 register (see Register17-2) contains control bits for the following: • CxOE bit of the CMxCON0 register must be set • Corresponding TRISx bit must be cleared • Interrupt enable • CxON bit of the CMxCON0 register must be set • Interrupt edge polarity The synchronous comparator output signal • Positive input channel selection (CxOUT_sync) is available to the following peripheral(s): • Negative input channel selection • Analog-to-Digital Converter (ADC) 17.2.1 COMPARATOR ENABLE • Timer1 Setting the CxON bit of the CMxCON0 register enables The asynchronous comparator output signal the comparator for operation. Clearing the CxON bit (CxOUT_async) is available to the following peripheral(s): disables the comparator resulting in minimum current • Complementary Waveform Generator (CWG) consumption. Note1: The CxOE bit of the CMxCON0 register overrides the port data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. DS40001723D-page 148  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 17.2.5 COMPARATOR OUTPUT POLARITY 17.3 Analog Input Connection Considerations Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The A simplified circuit for an analog input is shown in polarity of the comparator output can be inverted by Figure17-3. Since the analog input pins share their setting the CxPOL bit of the CMxCON0 register. connection with a digital input, they have reverse Clearing the CxPOL bit results in a non-inverted output. biased ESD protection diodes to VDD and VSS. The Table17-2 shows the output state versus input analog input, therefore, must be between VSS and VDD. conditions, including polarity control. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is TABLE 17-2: COMPARATOR OUTPUT forward-biased and a latch-up may occur. STATE VS. INPUT CONDITIONS A maximum source impedance of 10 k is recommended Input Condition CxPOL CxOUT for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or CxVN > CxVP 0 0 a Zener diode, should have very little leakage current to CxVN < CxVP 0 1 minimize inaccuracies introduced. CxVN > CxVP 1 1 Note1: When reading a PORT register, all pins CxVN < CxVP 1 0 configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will 17.2.6 COMPARATOR SPEED/POWER convert as an analog input, according to SELECTION the input specification. The trade-off between speed or power can be opti- 2: Analog levels on any pin defined as a mized during program execution with the CxSP control digital input, may cause the input buffer to bit. The default state for this bit is ‘1’, which selects the consume more current than is specified. Normal Speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘0’. FIGURE 17-3: ANALOG INPUT MODEL Rev. 10-000071A 8/2/2013 VDD Analog VT (cid:167) 0.6V RS < 10K Input pin RIC To Comparator ILEAKAGE(1) VA CPIN VT (cid:167) 0.6V 5pF VSS Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage Note 1: See Section26.0“Electrical Specifications”.  2013-2015 Microchip Technology Inc. DS40001723D-page 149

PIC12(L)F1571/2 17.4 Comparator Hysteresis 17.6 Comparator Interrupt A selectable amount of separation voltage can be An interrupt can be generated upon a change in the out- added to the input pins of each comparator to provide a put value of the comparator for each comparator, a rising hysteresis function to the overall operation. Hysteresis edge detector and a falling edge detector are present. is enabled by setting the CxHYS bit of the CMxCON0 When either edge detector is triggered and its associ- register. ated enable bit is set (CxINTP and/or CxINTN bits of See Section26.0“Electrical Specifications” for the CMxCON1 register), the corresponding interrupt more information. flag bit (CxIF bit of the PIR2 register) will be set. To enable the interrupt, you must set the following bits: 17.5 Timer1 Gate Operation • CxON and CxPOL bits of the CMxCON0 register The output resulting from a comparator operation can • CxIE bit of the PIE2 register be used as a source for gate control of Timer1. See • CxINTP bit of the CMxCON1 register (for a rising Section19.5“Timer1 Gate” for more information. edge detection) This feature is useful for timing the duration or interval • CxINTN bit of the CMxCON1 register (for a falling of an analog event. edge detection) It is recommended that the comparator output be • PEIE and GIE bits of the INTCON register synchronized to Timer1. This ensures that Timer1 does The associated interrupt flag bit, CxIF bit of the PIR2 not increment while a change in the comparator is register, must be cleared in software. If another edge is occurring. detected while this flag is being cleared, the flag will still 17.5.1 COMPARATOR OUTPUT be set at the end of the sequence. SYNCHRONIZATION Note: Although a comparator is disabled, an The output from the Cx comparator can be interrupt can be generated by changing synchronized with Timer1 by setting the CxSYNC bit of the output polarity with the CxPOL bit of the CMxCON0 register. the CMxCON0 register, or by switching the comparator on or off with the CxON bit Once enabled, the comparator output is latched on the of the CMxCON0 register. falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after 17.7 Comparator Response Time the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the The comparator output is indeterminate for a period of Timer1 clock source and Timer1 increments on the time after the change of an input source or the selection rising edge of its clock source. See the Comparator of a new reference voltage. This period is referred to as Block Diagram (Figure17-2) and the Timer1 Block the response time. The response time of the comparator Diagram (Figure19-1) for more information. differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section26.0“Electrical Specifications” for more details. DS40001723D-page 150  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 17.8 Register Definitions: Comparator Control REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxON CxOUT CxOE CxPOL — CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin; requires that the associated TRISx bit be cleared to actually drive the pin, not affected by CxON 0 = CxOUT is internal only bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as ‘0’ bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator mode is in Normal Power, Higher Speed mode 0 = Comparator mode is in Low-Power, Low-Speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis is enabled 0 = Comparator hysteresis is disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source; output updated on the falling edge of Timer1 clock source 0 = Comparator output to Timer1 and I/O pin is asynchronous  2013-2015 Microchip Technology Inc. DS40001723D-page 151

PIC12(L)F1571/2 REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 CxINTP CxINTN CxPCH<1:0> — CxNCH<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bit 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bit 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits 11 = CxVP connects to VSS 10 = CxVP connects to FVR Voltage Reference 01 = CxVP connects to DAC Voltage Reference 00 = CxVP connects to CxIN+ pin bit 3 Unimplemented: Read as ‘0’ bit 2-0 CxNCH<1:0>: Comparator Negative Input Channel Select bits 111 = CxVN connects to GND 110 = CxVN connects to FVR Voltage Reference 101 = Reserved 100 = Reserved 011 = Reserved 010 = Reserved 001 = CxVN connects to CxIN1- pin 000 = CxVN connects to CxIN0- pin REGISTER 17-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 — — — — — — — MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-1 Unimplemented: Read as ‘0’ bit 0 MC1OUT: Mirror Copy of C1OUT bit DS40001723D-page 152  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA<2:0> 114 CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 151 CM1CON1 C1NTP C1INTN C1PCH<1:0> — C1NCH<2:0> 152 CMOUT — — — — — — — MC1OUT 152 DAC1CON0 DACEN — DACOE — DACPSS<1:0> — — 145 DAC1CON1 — — — DACR<4:0> 145 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 125 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE2 — — C1IE — — — — — 76 PIR2 — — C1IF — — — — — 79 PORTA — — RA5 RA4 RA3 RA<2:0> 113 LATA — — LATA5 LATA4 — LATA<2:0> 114 TRISA — — TRISA5 TRISA4 —(1) TRISA<2:0> 113 Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module. Note 1: Unimplemented, read as ‘1’.  2013-2015 Microchip Technology Inc. DS40001723D-page 153

PIC12(L)F1571/2 NOTES: DS40001723D-page 154  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 18.0 TIMER0 MODULE 18.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment The Timer0 module is an 8-bit timer/counter with the on every rising or falling edge of the T0CKI pin. following features: In 8-Bit Counter mode, the T0CKI pin is selected by • 8-Bit Timer/Counter register (TMR0) setting the TMR0CS bit in the OPTION_REG register • 3-bit prescaler (independent of Watchdog Timer) to‘1’. • Programmable internal or external clock source • Programmable external clock edge selection The rising or falling transition of the incrementing edge • Interrupt on overflow for either input source is determined by the TMR0SE bit • TMR0 can be used to gate Timer1 in the OPTION_REG register. Figure18-1 is a block diagram of the Timer0 module. 18.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 18.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle if used without a prescaler. The 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 18-1: TIMER0 BLOCK DIAGRAM TMR0CS Rev. 10-080/50/021071A3 Fosc/4 PSA T0CKI(1) 0 1 T0CKI T0_overflow TMR0 1 Prescaler 0 FOSC/2 Sync Circuit Q1 write R to TMR0 TMR0SE PS<2:0> set bit TMR0IF Note 1: The T0CKI prescale output frequency should not exceed FOSC/8.  2013-2015 Microchip Technology Inc. DS40001723D-page 155

PIC12(L)F1571/2 18.1.3 SOFTWARE PROGRAMMABLE 18.1.5 8-BIT COUNTER MODE PRESCALER SYNCHRONIZATION A software programmable prescaler is available for When in 8-Bit Counter mode, the incrementing edge on exclusive use with Timer0. The prescaler is enabled by the T0CKI pin must be synchronized to the instruction clearing the PSA bit of the OPTION_REG register. clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles Note: The Watchdog Timer (WDT) uses its own of the instruction clock. The high and low periods of the independent prescaler. external clocking source must meet the timing There are eight prescaler options for the Timer0 module, requirements as shown in Section26.0“Electrical ranging from 1:2 to 1:256. The prescale values are Specifications”. selectable via the PS<2:0> bits of the OPTION_REG 18.1.6 OPERATION DURING SLEEP register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by Timer0 cannot operate while the processor is in Sleep setting the PSA bit of the OPTION_REG register. mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 18.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. DS40001723D-page 156  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 18.2 Register Definitions: Option Register REGISTER 18-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate 000 1 : 2 001 1 : 4 010 1 : 8 011 1 : 16 100 1 : 32 101 1 : 64 110 1 : 128 111 1 : 256 TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ADCON2 TRIGSEL<3:0> — — — — 137 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 157 TMR0 Holding Register for the 8-bit Timer0 Count 155* TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 113 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. Note 1: Unimplemented, read as ‘1’.  2013-2015 Microchip Technology Inc. DS40001723D-page 157

PIC12(L)F1571/2 NOTES: DS40001723D-page 158  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 19.0 TIMER1 MODULE WITH GATE • Wake-up on overflow (external clock, CONTROL Asynchronous mode only) • ADC auto-conversion trigger(s) The Timer1 module is a 16-bit timer/counter with the • Selectable gate source polarity following features: • Gate Toggle mode • 16-bit Timer/Counter register pair (TMR1H:TMR1L) • Gate Single-Pulse mode • Programmable internal or external clock source • Gate value status • 2-bit prescaler • Gate event interrupt • Optionally synchronized comparator out Figure19-1 is a block diagram of the Timer1 module. • Multiple Timer1 gate (count enable) sources • Interrupt on overflow FIGURE 19-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> Rev. 10-000018D 8/5/2013 T1GSPM T1G 00 T0_overflow 01 1 C1OUT_sync 10 0 Single Pulse D Q T1GVAL 0 Reserved 11 1 Acq. Control Q1 D Q T1GPOL T1GGO/DONE CK Q TMR1ON Interrupt set bit R T1GTM det TMR1GIF TMR1GE set flag bit TMR1IF TMR1ON EN TMR1(2) T1_overflow TMR1H TMR1L Q D 0 Synchronized Clock Input 1 T1CLK T1SYNC TMR1CS<1:0> LFINTOSC 11 (1) T1CKI 10 Prescaler Synchronize(3) Fosc 01 1,2,4,8 Internal Clock det 00 2 Fosc/4 Fosc/2 Internal Clock T1CKPS<1:0> Internal Sleep Clock Input Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.  2013-2015 Microchip Technology Inc. DS40001723D-page 159

PIC12(L)F1571/2 19.1 Timer1 Operation 19.2 Clock Source Selection The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> bits of the T1CON register are used which is accessed through the TMR1H:TMR1L register to select the clock source for Timer1. Table19-2 pair. Writes to TMR1H or TMR1L directly update the displays the clock source selections. counter. 19.2.1 INTERNAL CLOCK SOURCE When used with an internal clock source, the module is a timer and increments on every instruction cycle. When the internal clock source is selected, the When used with an external clock source, the module TMR1H:TMR1L register pair will increment on multiples can be used as either a timer or counter and of FOSC, as determined by the Timer1 prescaler. increments on every selected edge of the external When the FOSC internal clock source is selected, the source. Timer1 register value will increment by four counts every Timer1 is enabled by configuring the TMR1ON and instruction clock cycle. Due to this condition, a 2 LSB TMR1GE bits in the T1CON and T1GCON registers, error in resolution will occur when reading the Timer1 respectively. Table19-1 displays the Timer1 enable value. To utilize the full resolution of Timer1, an selections. asynchronous input signal must be used to gate the Timer1 clock input. TABLE 19-1: TIMER1 ENABLE The following asynchronous sources may be used: SELECTIONS • Asynchronous event on the T1G pin to Timer1 gate Timer1 • C1 or C2 comparator input to Timer1 gate TMR1ON TMR1GE Operation 19.2.2 EXTERNAL CLOCK SOURCE 0 0 Off When the external clock source is selected, the Timer1 0 1 Off module may work as a timer or a counter. 1 0 Always On When enabled to count, Timer1 is incremented on the ris- 1 1 Count Enabled ing edge of the external clock input T1CKI. The external clock source can be synchronized to the microcontroller system clock or it can run asynchronously. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMR1H or TMR1L • Timer1 is disabled • Timer1 is disabled (TMR1ON = 0) when T1CKI is high, then Timer1 is enabled (TMR1ON = 1) when T1CKI is low TABLE 19-2: CLOCK SOURCE SELECTIONS TMR1CS<1:0> T1OSCEN(1) Clock Source 11 x LFINTOSC 10 x External Clocking on T1CKI Pin 01 x System Clock (FOSC) 00 x Instruction Clock (FOSC/4) Note 1: T1OSCEN is not available for these devices. DS40001723D-page 160  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 19.3 Timer1 Prescaler 19.5 Timer1 Gate Timer1 has four prescaler options, allowing 1, 2, 4 or 8 Timer1 can be configured to count freely or the count divisions of the clock input. The T1CKPSx bits of the can be enabled and disabled using Timer1 gate T1CON register control the prescale counter. The circuitry. This is also referred to as Timer1 Gate Enable. prescale counter is not directly readable or writable; Timer1 gate can also be driven by multiple selectable however, the prescaler counter is cleared upon a write to sources. TMR1H or TMR1L. 19.5.1 TIMER1 GATE ENABLE 19.4 Timer1 Operation in The Timer1 Gate Enable mode is enabled by setting Asynchronous Counter Mode the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using If control bit, T1SYNC, of the T1CON register is set, the T1GPOL bit of the T1GCON register. the external clock input is not synchronized. The timer increments asynchronously to the internal phase When Timer1 Gate Enable mode is enabled, Timer1 clocks. If the external clock source is selected then the will increment on the rising edge of the Timer1 clock timer will continue to run during Sleep and can source. When Timer1 Gate Enable mode is disabled, generate an interrupt on overflow, which will wake-up no incrementing will occur and Timer1 will hold the the processor. However, special precautions in current count. See Figure19-3 for timing details. software are needed to read/write the timer (see Section 19.4.1“Reading and Writing Timer1 in TABLE 19-3: TIMER1 GATE ENABLE Asynchronous Counter Mode”). SELECTIONS Note: When switching from synchronous to T1CLK T1GPOL T1G Timer1 Operation asynchronous operation, it is possible to skip an increment. When switching from  0 0 Counts asynchronous to synchronous operation,  0 1 Holds Count it is possible to produce an additional  1 0 Holds Count increment.  1 1 Counts 19.4.1 READING AND WRITING TIMER1 IN 19.5.2 TIMER1 GATE SOURCE ASYNCHRONOUS COUNTER SELECTION MODE Timer1 gate source selections are shown in Table19-4. Reading TMR1H or TMR1L while the timer is running Source selection is controlled by the T1GSS<1:0> bits from an external asynchronous clock will ensure a valid of the T1GCON register. The polarity for each available read (taken care of in hardware). However, the user source is also selectable. Polarity selection is controlled should keep in mind that reading the 16-bit timer in two by the T1GPOL bit of the T1GCON register. 8-bit values itself, poses certain problems, since the timer may overflow between the reads. TABLE 19-4: TIMER1 GATE SOURCES For writes, it is recommended that the user simply stop T1GSS<1:0> Timer1 Gate Source the timer and write the desired values. A write contention may occur by writing to the timer registers, 00 Timer1 Gate Pin (T1G) while the register is incrementing. This may produce an 01 Overflow of Timer0 (T0_overflow) unpredictable value in the TMR1H:TMR1L register pair. (TMR0 increments from FFh to 00h) 10 Comparator 1 Output (C1OUT_sync)(1) 11 Reserved Note 1: Optionally synchronized comparator output.  2013-2015 Microchip Technology Inc. DS40001723D-page 161

PIC12(L)F1571/2 19.5.2.1 T1G Pin Gate Operation If the Single-Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE The T1G pin is one source for Timer1 gate control. It bit should also be cleared. can be used to supply an external source to the Timer1 gate circuitry. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work 19.5.2.2 Timer0 Overflow Gate Operation together. This allows the cycle times on the Timer1 gate source to be measured. See Figure19-6 for timing When Timer0 increments from FFh to 00h, a low-to- details. high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 19.5.5 TIMER1 GATE VALUE STATUS 19.5.3 TIMER1 GATE TOGGLE MODE When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. When Timer1 Gate Toggle mode is enabled, it is The value is stored in the T1GVAL bit in the T1GCON possible to measure the full cycle length of a Timer1 gate register. The T1GVAL bit is valid even when the Timer1 signal, as opposed to the duration of a single level pulse. gate is not enabled (TMR1GE bit is cleared). The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the 19.5.6 TIMER1 GATE EVENT INTERRUPT signal. See Figure19-4 for timing details. When Timer1 gate event interrupt is enabled, it is pos- Timer1 Gate Toggle mode is enabled by setting the sible to generate an interrupt upon the completion of a T1GTM bit of the T1GCON register. When the T1GTM gate event. When the falling edge of T1GVAL occurs, bit is cleared, the flip-flop is cleared and held clear. This the TMR1GIF flag bit in the PIR1 register will be set. If is necessary in order to control which edge is measured. the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in The TMR1GIF flag bit operates even when the Timer1 indeterminate operation. gate is not enabled (TMR1GE bit is cleared). 19.5.4 TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/ DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/ DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See Figure19-5 for timing details. DS40001723D-page 162  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 19.6 Timer1 Interrupt The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON The Timer1 register pair (TMR1H:TMR1L) increments register is set, the device will call the Interrupt Service to FFFFh and rolls over to 0000h. When Timer1 rolls Routine. over, the Timer1 interrupt flag bit of the PIR1 register is Timer1 oscillator will continue to operate in Sleep set. To enable the interrupt on rollover, you must set regardless of the T1SYNC bit setting. these bits: • TMR1ON bit of the T1CON register 19.7.1 ALTERNATE PIN LOCATIONS • TMR1IE bit of the PIE1 register This module incorporates I/O pins that can be moved to • PEIE bit of the INTCON register other locations with the use of the Alternate Pin Func- • GIE bit of the INTCON register tion register, APFCON. To determine which pins can be The interrupt is cleared by clearing the TMR1IF bit in moved and what their default locations are upon a the Interrupt Service Routine. Reset, see Section 11.1“Alternate Pin Function” for more information. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. 19.7 Timer1 Operation During Sleep Timer1 can only operate during Sleep when set up in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • TMR1ON bit of the T1CON register must be set • TMR1IE bit of the PIE1 register must be set • PEIE bit of the INTCON register must be set • T1SYNC bit of the T1CON register must be set • TMR1CS bits of the T1CON register must be configured FIGURE 19-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 is Enabled T1CKI = 0 when TMR1 is Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2013-2015 Microchip Technology Inc. DS40001723D-page 163

PIC12(L)F1571/2 FIGURE 19-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 FIGURE 19-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 DS40001723D-page 164  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by Hardware on DONE Set by Software Falling Edge of T1GVAL Counting Enabled on Rising Edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 Cleared by TMR1GIF Cleared by Software Set by Hardware on Software Falling Edge of T1GVAL  2013-2015 Microchip Technology Inc. DS40001723D-page 165

PIC12(L)F1571/2 FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by Hardware on DONE Set by Software Falling Edge of T1GVAL Counting Enabled on Rising Edge of T1G t1g_in T1CKI T1GVAL Timer1 N N + 1 N + 2 N + 3 N + 4 Set by Hardware on Cleared by TMR1GIF Cleared by Software Falling Edge of T1GVAL Software DS40001723D-page 166  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 19.8 Register Definitions: Timer1 Control REGISTER 19-1: T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u U-0 R/W-0/u TMR1CS<1:0> T1CKPS<1:0> — T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Timer1 clock source is the LFINTOSC 10 = Timer1 clock source is the T1CKI pin (on the rising edge) 01 = Timer1 clock source is the system clock (FOSC) 00 = Timer1 clock source is the instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 Unimplemented: Read as ‘0’ bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Does not synchronize the asynchronous clock input 0 = Synchronizes the asynchronous clock input with the system clock (FOSC) bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop  2013-2015 Microchip Technology Inc. DS40001723D-page 167

PIC12(L)F1571/2 REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> DONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit HC = Hardware Clearable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Value Status bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable bit (TMR1GE). bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Reserved 10 = Comparator 1 optionally synchronized output (C1OUT_sync) 01 = Timer0 overflow output (T0_overflow) 00 = Timer1 gate pin (T1G) DS40001723D-page 168  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 19-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA<2:0> 114 APFCON RXDTSEL CWGASEL CWGBSEL — T1GSEL TXCKSEL P2SEL P1SEL 110 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 56 PIE1 TMR1GIE ADIE RCIE(2) TXIE(2) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(2) TXIF(2) — — TMR2IF TMR1IF 79 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count 163* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count 163* TRISA — — TRISA<5:4> —(1) TRISA<2:0> 113 T1CON TMR1CS<1:0> T1CKPS<1:0> — T1SYNC — TMR1ON 167 T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 168 DONE Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. Note 1: Unimplemented, read as ‘1’. 2: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 169

PIC12(L)F1571/2 NOTES: DS40001723D-page 170  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 20.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-Bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16 and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2 See Figure20-1 for a block diagram of Timer2. FIGURE 20-1: TIMER2 BLOCK DIAGRAM Rev.10-000019A 7/30/2013 T2_match Fosc/4 1:1,1P:r4e,s1c:a1l6e,r1:64 TMR2 R ToPeripherals 2 Postscaler setbit T2CKPS<1:0> Comparator 1:1to1:16 TMR2IF 4 PR2 T2OUTPS<3:0> FIGURE 20-2: TIMER2 TIMING DIAGRAM Rev.10-000020A 7/30/2013 FOSC/4 1:4 Prescale 0x03 PR2 0x00 0x01 0x02 0x03 0x00 0x01 0x02 TMR2 T2_match PulseWidth(1) Note1: ThePulseWidthofT2_matchisequaltothescaledinputofTMR2.  2013-2015 Microchip Technology Inc. DS40001723D-page 171

PIC12(L)F1571/2 20.1 Timer2 Operation 20.3 Timer2 Output The clock input to the Timer2 module is the system The output of TMR2 is T2_match. instruction clock (FOSC/4). The T2_match signal is synchronous with the system TMR2 increments from 00h on each clock edge. clock. Figure20-3 shows two examples of the timing of A 4-bit counter/prescaler on the clock input allows direct the T2_match signal relative to FOSC and prescale value, T2CKPS<1:0>. The upper diagram illustrates 1:1 input, divide-by-4 and divide-by-16 prescale options. prescale timing and the lower diagram, 1:X prescale These options are selected by the prescaler control bits, timing. T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on FIGURE 20-3: T2_MATCH TIMING each clock cycle. When the two values match, the comparator generates a match signal as the timer DIAGRAM output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/ Rev.107-0/3000/022011A3 postscaler (see Section20.2“Timer2 Interrupt”). Q1 Q2 Q3 Q4 Q1 The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any FOSC device Reset, whereas the PR2 register initializes to TCY1 FFh. Both the prescaler and postscaler counters are FOSC/4 cleared on the following events: • A write to the TMR2 register T2_match TMR2=PR2 TMR2=0 match • A write to the T2CON register PRESCALE=1:1 • Power-on Reset (POR) (T2CKPS<1:0>=00) • Brown-out Reset (BOR) • MCLR Reset TCY1 TCY2 ... TCYX • Watchdog Timer (WDT) Reset • Stack Overflow Reset FOSC/4 ... • Stack Underflow Reset T2_match TMR2=PR2 ... TMR2=0 • RESET Instruction match Note: TMR2 is not cleared when T2CON is PRESCALE=1:X written. (T2CKPS<1:0>=01,10,11) 20.2 Timer2 Interrupt 20.4 Timer2 Operation During Sleep Timer2 can also generate an optional device interrupt. The Timer2 output signal (T2_match) provides the input Timer2 cannot be operated while the processor is in for the 4-bit counter/postscaler. This counter generates Sleep mode. The contents of the TMR2 and PR2 the TMR2 match interrupt flag which is latched in registers will remain unchanged while the processor is TMR2IF of the PIR1 register. The interrupt is enabled by in Sleep mode. setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register. DS40001723D-page 172  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 20.5 Register Definitions: Timer2 Control REGISTER 20-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 =1:1 Postscaler 0001 =1:2 Postscaler 0010 =1:3 Postscaler 0011 =1:4 Postscaler 0100 =1:5 Postscaler 0101 =1:6 Postscaler 0110 =1:7 Postscaler 0111 =1:8 Postscaler 1000 =1:9 Postscaler 1001 =1:10 Postscaler 1010 =1:11 Postscaler 1011 =1:12 Postscaler 1100 =1:13 Postscaler 1101 =1:14 Postscaler 1110 =1:15 Postscaler 1111 =1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 11 = Prescaler is 64 TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 PR2 Timer2 Module Period Register 171* T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 173 TMR2 Holding Register for the 8-bit TMR2 Count 171* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. Note1: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 173

PIC12(L)F1571/2 NOTES: DS40001723D-page 174  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 21.0 ENHANCED UNIVERSAL The EUSART module includes the following capabilities: SYNCHRONOUS • Full-duplex asynchronous transmit and receive ASYNCHRONOUS RECEIVER • Two-character input buffer TRANSMITTER (EUSART) • One-character output buffer • Programmable 8-bit or 9-bit character length The Enhanced Universal Synchronous Asynchronous • Address detection in 9-bit mode Receiver Transmitter (EUSART) module is a serial I/O • Input buffer overrun error detection communications peripheral. It contains all the clock generators, shift registers and data buffers necessary • Received character framing error detection to perform an input or output serial data transfer, inde- • Half-duplex synchronous master pendent of device program execution. The EUSART, • Half-duplex synchronous slave also known as a Serial Communications Interface • Programmable clock polarity in synchronous (SCI), can be configured as a full-duplex asynchronous modes system or half-duplex synchronous system. • Sleep operation Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and per- The EUSART module implements the following sonal computers. Half-Duplex Synchronous mode is additional features, making it ideally suited for use in intended for communications with peripheral devices, Local Interconnect Network (LIN) bus systems: such as A/D or D/A integrated circuits, serial EEPROMs • Automatic detection and calibration of the baud rate or other microcontrollers. These devices typically do not • Wake-up on Break reception have internal clocks for baud rate generation and require • 13-bit Break character transmit the external clock signal provided by a master synchronous device. Block diagrams of the EUSART transmitter and receiver are shown in Figure21-1 and Figure21-2. FIGURE 21-1: EUSART TRANSMIT BLOCK DIAGRAM Rev. 10-000113B 7/14/2015 Data bus 8 TXIE Interrupt TXREG register TXIF 8 MSb LSb TX/CK Pin Buffer (8) 0 and Control Transmit Shift Register (TSR) TXEN TRMT Baud Rate Generator FOSC ÷ n TX9 n BRG16 TX9D + 1 Multiplier x4 x16 x64 SYNC 1 x 0 0 0 BRGH x 1 1 0 0 SPBRGH SPBRGL BRG16 x 1 0 1 0  2013-2015 Microchip Technology Inc. DS40001723D-page 175

PIC12(L)F1571/2 FIGURE 21-2: EUSART RECEIVE BLOCK DIAGRAM Rev.10-000114A 7/30/2013 CREN OERR RCIDL SPEN RX/DTpin MSb RSRRegister LSb PinBuffer Data Stop (8) 7 1 0 Start andControl Recovery BaudRateGenerator FOSC ÷n RX9 BRG16 n +1 Multiplier x4 x16 x64 SYNC 1 x 0 0 0 BRGH x 1 1 0 0 SPBRGH SPBRGL FIFO BRG16 x 1 0 1 0 FERR RX9D RCREGRegister 8 DataBus RCIF Interrupt RCIE The operation of the EUSART module is controlled These registers are detailed in Register21-1, through three registers: Register21-2 and Register21-3, respectively. • Transmit Status and Control (TXSTA) When the receiver or transmitter section is not enabled, • Receive Status and Control (RCSTA) then the corresponding RX or TX pin may be used for general purpose input and output. • Baud Rate Control (BAUDCON) DS40001723D-page 176  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 21.1 EUSART Asynchronous Mode 21.1.1.2 Transmitting Data The EUSART transmits and receives data using the A transmission is initiated by writing a character to the standard Non-Return-to-Zero (NRZ) format. NRZ is TXREG register. If this is the first character, or the previ- implemented with two levels: a VOH mark state which ous character has been completely flushed from the represents a ‘1’ data bit, and a VOL space state which TSR, the data in the TXREG is immediately transferred represents a ‘0’ data bit. NRZ refers to the fact that con- to the TSR register. If the TSR still contains all or part of secutively transmitted data bits of the same value stay a previous character, the new character data is held in at the output level of that bit without returning to a neutral the TXREG until the Stop bit of the previous character level between each bit transmission. An NRZ transmis- has been transmitted. The pending character in the sion port Idles in the mark state. Each character TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission consists of one Start bit, followed by eight transmission of the Start bit, data bits and Stop bit or nine data bits and is always terminated by one or sequence commences immediately following the more Stop bits. The Start bit is always a space and the transfer of the data to the TSR from the TXREG. Stop bits are always marks. The most common data for- mat is eight bits. Each transmitted bit persists for a 21.1.1.3 Transmit Data Polarity period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive The polarity of the transmit data can be controlled with standard baud rate frequencies from the system the SCKP bit of the BAUDCON register. The default oscillator. See Table21-5 for examples of baud rate state of this bit is ‘0’ which selects high true transmit Idle configurations. and data bits. Setting the SCKP bit to ‘1’ will invert the transmit data resulting in low true Idle and data bits. The The EUSART transmits and receives the LSb first. The SCKP bit controls transmit data polarity in Asynchro- EUSART’s transmitter and receiver are functionally nous mode only. In Synchronous mode, the SCKP bit independent, but share the same data format and baud has a different function. See Section21.5.1.2 “Clock rate. Parity is not supported by the hardware, but can be Polarity”. implemented in software and stored as the ninth data bit. 21.1.1.4 Transmit Interrupt Flag 21.1.1 EUSART ASYNCHRONOUS TRANSMITTER The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no The EUSART transmitter block diagram is shown in character is being held for transmission in the TXREG. Figure21-1. The heart of the transmitter is the serial In other words, the TXIF bit is only clear when the TSR Transmit Shift Register (TSR), which is not directly is busy with a character and a new character has been accessible by software. The TSR obtains its data from queued for transmission in the TXREG. The TXIF flag bit the transmit buffer, which is the TXREG register. is not cleared immediately upon writing TXREG. TXIF 21.1.1.1 Enabling the Transmitter becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following The EUSART transmitter is enabled for asynchronous the TXREG write will return invalid results. The TXIF bit operations by configuring the following three control bits: is read-only, it cannot be set or cleared by software. • TXEN = 1 The TXIF interrupt can be enabled by setting the TXIE • SYNC = 0 interrupt enable bit of the PIE1 register. However, the • SPEN = 1 TXIF flag bit will be set whenever the TXREG is empty, All other EUSART control bits are assumed to be in regardless of the state of the TXIE enable bit. their default state. To use interrupts when transmitting data, set the TXIE Setting the TXEN bit of the TXSTA register enables the bit only when there is more data to send. Clear the transmitter circuitry of the EUSART. Clearing the SYNC TXIE interrupt enable bit upon writing the last character bit of the TXSTA register configures the EUSART for of the transmission to the TXREG. asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSELx bit. Note: The TXIF transmitter interrupt flag is set when the TXEN enable bit is set.  2013-2015 Microchip Technology Inc. DS40001723D-page 177

PIC12(L)F1571/2 21.1.1.5 TSR Status 21.1.1.7 Asynchronous Transmission Setup The TRMT bit of the TXSTA register indicates the 1. Initialize the SPBRGH/SPBRGL register pair, status of the TSR register. This is a read-only bit. The and the BRGH and BRG16 bits to achieve the TRMT bit is set when the TSR register is empty and is desired baud rate (see Section21.4 “EUSART cleared when a character is transferred to the TSR Baud Rate Generator (BRG)”). register from the TXREG. The TRMT bit remains clear 2. Enable the asynchronous serial port by clearing until all bits have been shifted out of the TSR register. the SYNC bit and setting the SPEN bit. No interrupt logic is tied to this bit, so the user has to 3. If 9-bit transmission is desired, set the TX9 con- poll this bit to determine the TSR status. trol bit. A set ninth data bit will indicate that the Note: The TSR register is not mapped in data eight Least Significant data bits are an address memory, so it is not available to the user. when the receiver is set for address detection. 4. Set the SCKP bit if inverted transmit is desired. 21.1.1.6 Transmitting 9-Bit Characters 5. Enable the transmission by setting the TXEN The EUSART supports 9-bit character transmissions. control bit. This will cause the TXIF interrupt bit When the TX9 bit of the TXSTA register is set, the to be set. EUSART will shift nine bits out for each character trans- 6. If interrupts are desired, set the TXIE interrupt mitted. The TX9D bit of the TXSTA register is the ninth enable bit of the PIE1 register. An interrupt will and Most Significant data bit. When transmitting 9-bit occur immediately provided that the GIE and data, the TX9D data bit must be written before writing PEIE bits of the INTCON register are also set. the eight Least Significant bits into the TXREG. All nine 7. If 9-bit transmission is selected, the ninth bit bits of data will be transferred to the TSR register should be loaded into the TX9D data bit. immediately after the TXREG is written. 8. Load 8-bit data into the TXREG register. This A special 9-Bit Address mode is available for use with will start the transmission. multiple receivers. See Section21.1.2.7 “Address Detection” for more information on this mode. FIGURE 21-3: ASYNCHRONOUS TRANSMISSION Write to TXREG BRG Output Word 1 (Shift Clock) TX/CK Pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY TXIF bit (Transmit Buffer Reg. Empty Flag) Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 21-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG BRG Output Word 1 Word 2 (Shift Clock) TX/CK Pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 1 TCY Word 1 Word 2 TXIF bit R(eTgr.a Ensmmpitty B Fulaffge)r 1 TCY Word 1 Word 2 Transmit Shift Reg. Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. DS40001723D-page 178  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185* SPBRGL BRG<7:0> 187* SPBRGH BRG<15:8> 187* TXREG EUSART Transmit Data Register 177 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission. * Page provides register information. Note 1: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 179

PIC12(L)F1571/2 21.1.2 EUSART ASYNCHRONOUS 21.1.2.2 Receiving Data RECEIVER The receiver data recovery circuit initiates character The Asynchronous mode is typically used in RS-232 reception on the falling edge of the first bit. The first bit, systems. The receiver block diagram is shown in also known as the Start bit, is always a zero. The data Figure21-2. The data is received on the RX/DT pin and recovery circuit counts one-half bit time to the center of drives the data recovery block. The data recovery block the Start bit and verifies that the bit is still a zero. If it is is actually a high-speed shifter operating at 16 times not a zero then the data recovery circuit aborts charac- the baud rate, whereas the serial Receive Shift ter reception, without generating an error, and resumes Register (RSR) operates at the bit rate. When all eight looking for the falling edge of the Start bit. If the Start bit or nine bits of the character have been shifted in, they zero verification succeeds, then the data recovery are immediately transferred to a two character circuit counts a full bit time to the center of the next bit. First-In-First-Out (FIFO) memory. The FIFO buffering The bit is then sampled by a majority detect circuit and allows reception of two complete characters and the the resulting ‘0’ or ‘1’ is shifted into the RSR. This start of a third character before software must start ser- repeats until all data bits have been sampled and vicing the EUSART receiver. The FIFO and RSR regis- shifted into the RSR. One final bit time is measured and ters are not directly accessible by software. Access to the level sampled. This is the Stop bit, which is always the received data is via the RCREG register. a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this char- 21.1.2.1 Enabling the Receiver acter; otherwise, the framing error is cleared for this character. See Section21.1.2.4 “Receive Framing The EUSART receiver is enabled for asynchronous Error” for more information on framing errors. operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have • CREN = 1 been received, the character in the RSR is transferred • SYNC = 0 to the EUSART receive FIFO and the RCIF interrupt • SPEN = 1 flag bit of the PIR1 register is set. The top character in All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the their default state. RCREG register. Setting the CREN bit of the RCSTA register enables the Note: If the receive FIFO is overrun, no receiver circuitry of the EUSART. Clearing the SYNC bit additional characters will be received of the TXSTA register configures the EUSART for asyn- until the overrun condition is cleared. See chronous operation. Setting the SPEN bit of the RCSTA Section21.1.2.5 “Receive Overrun register enables the EUSART. The programmer must Error” for more information on overrun set the corresponding TRIS bit to configure the RX/DT errors. I/O pin as an input. 21.1.2.3 Receive Interrupts Note: If the RX/DT function is on an analog pin, the corresponding ANSELx bit must be The RCIF interrupt flag bit of the PIR1 register is set cleared for the receiver to function. whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE, Interrupt Enable bit of the PIE1 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS40001723D-page 180  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 21.1.2.4 Receive Framing Error 21.1.2.6 Receiving 9-Bit Characters Each character in the receive FIFO buffer has a The EUSART supports 9-bit character reception. When corresponding framing error status bit. A framing error the RX9 bit of the RCSTA register is set, the EUSART indicates that a Stop bit was not seen at the expected will shift nine bits into the RSR for each character time. The framing error status is accessed via the received. The RX9D bit of the RCSTA register is the FERR bit of the RCSTA register. The FERR bit rep- ninth and Most Significant data bit of the top unread resents the status of the top unread character in the character in the receive FIFO. When reading 9-bit data receive FIFO. Therefore, the FERR bit must be read from the receive FIFO buffer, the RX9D data bit must before reading the RCREG. be read before reading the eight Least Significant bits from the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error 21.1.2.7 Address Detection (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. A special Address Detection mode is available for use Reading the next character from the FIFO buffer will when multiple receivers share the same transmission advance the FIFO to the next character and the next line, such as in RS-485 systems. Address detection is corresponding framing error. enabled by setting the ADDEN bit of the RCSTA register. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Address detection requires 9-bit character reception. Clearing the CREN bit of the RCSTA register does not When address detection is enabled, only characters affect the FERR bit. A framing error by itself does not with the ninth data bit set will be transferred to the generate an interrupt. receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Note: If all receive characters in the receive Upon receiving an address character, user software FIFO have framing errors, repeated reads determines if the address matches its own. Upon of the RCREG will not clear the FERR bit. address match, user software must disable address detection by clearing the ADDEN bit before the next 21.1.2.5 Receive Overrun Error Stop bit occurs. When user software detects the end of The receive FIFO buffer can hold two characters. An the message, determined by the message protocol overrun error will be generated if a third character, in its used, software places the receiver back into the entirety, is received before the FIFO is accessed. When Address Detection mode by setting the ADDEN bit. this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read, but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register.  2013-2015 Microchip Technology Inc. DS40001723D-page 181

PIC12(L)F1571/2 21.1.2.8 Asynchronous Reception Setup 21.1.2.9 9-Bit Address Detection Mode Setup 1. Initialize the SPBRGH, SPBRGL register pair This mode would typically be used in RS-485 systems. and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address desired baud rate (see Section21.4 “EUSART Detect Enable: Baud Rate Generator (BRG)”). 1. Initialize the SPBRGH/SPBRGL register pair, 2. Clear the ANSELx bit for the RX pin (if applicable). and the BRGH and BRG16 bits to achieve the 3. Enable the serial port by setting the SPEN bit. desired baud rate (see Section21.4 “EUSART The SYNC bit must be clear for asynchronous Baud Rate Generator (BRG)”). operation. 2. Clear the ANSELx bit for the RX pin (if applicable). 4. If interrupts are desired, set the RCIE bit of the 3. Enable the serial port by setting the SPEN bit. PIE1 register, and the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous INTCON register. operation. 5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCIE bit of the 6. Enable reception by setting the CREN bit. PIE1 register, and the GIE and PEIE bits of the 7. The RCIF interrupt flag bit will be set when a INTCON register. character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit. receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN the RCIE interrupt enable bit was also set. bit. 8. Read the RCSTA register to get the error flags 7. Enable reception by setting the CREN bit. and, if 9-bit data reception is enabled, the ninth 8. The RCIF interrupt flag bit will be set when a data bit. character with the ninth bit set is transferred 9. Get the received eight Least Significant data bits from the RSR to the receive buffer. An interrupt from the receive buffer by reading the RCREG will be generated if the RCIE interrupt enable bit register. was also set. 10. If an overrun occurred, clear the OERR flag by 9. Read the RCSTA register to get the error flags. clearing the CREN receiver enable bit. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. FIGURE 21-5: ASYNCHRONOUS RECEPTION Start Start Start RX/DT Pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop bit bit bit Rcv Shift Reg. Rcv Buffer Reg. Word 1 Word 2 RCREG RCREG RCIDL Read Rcv Buffer Reg. (RCREG) RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS40001723D-page 182  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 21-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 RCREG EUSART Receive Data Register 180* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185* SPBRGL BRG<7:0> 187* SPBRGH BRG<15:8> 187* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception. * Page provides register information. Note 1: PIC12(L)F1572 only. 21.2 Clock Accuracy with The Auto-Baud Detect feature (see Section21.4.1 Asynchronous Operation “Auto-Baud Detect”) can be used to compensate for changes in the INTOSC frequency. The factory calibrates the Internal Oscillator Block There may not be fine enough resolution when (INTOSC) output. However, the INTOSC frequency adjusting the Baud Rate Generator to compensate for may drift as VDD or temperature changes, and this a gradual change in the peripheral clock frequency. directly affects the asynchronous baud rate.  2013-2015 Microchip Technology Inc. DS40001723D-page 183

PIC12(L)F1571/2 21.3 Register Definitions: EUSART Control REGISTER 21-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit is enabled 0 = Transmit is disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Sends Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS40001723D-page 184  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 21-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port is disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care. Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: Ninth Bit of Received Data bit This can be address/data bit or a parity bit and must be calculated by user firmware.  2013-2015 Microchip Technology Inc. DS40001723D-page 185

PIC12(L)F1571/2 REGISTER 21-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care. bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care. bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmits inverted data to the TX/CK pin 0 = Transmits non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-Bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge; no character will be received, RCIF bit will be set, WUE will automatically clear after RCIF is set 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: A.uto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care. DS40001723D-page 186  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 21.4 EUSART Baud Rate Generator EXAMPLE 21-1: CALCULATING BAUD (BRG) RATE ERROR The Baud Rate Generator (BRG) is an 8-bit or 16-bit For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: timer that is dedicated to the support of both the asyn- chronous and synchronous EUSART operation. By FOSC Desired Baud Rate = ------------------------------------------------------------------------ default, the BRG operates in 8-bit mode. Setting the 64[SPBRGH:SPBRGL]+1 BRG16 bit of the BAUDCON register selects 16-bit Solving for SPBRGH:SPBRGL: mode. FOSC The SPBRGH/SPBRGL register pair determines the --------------------------------------------- Desired Baud Rate period of the free-running baud rate timer. In Asynchro- X = ---------------------------------------------–1 64 nous mode, the multiplier of the baud rate period is 16000000 determined by both the BRGH bit of the TXSTA register ------------------------ 9600 and the BRG16 bit of the BAUDCON register. In = ------------------------–1 64 Synchronous mode, the BRGH bit is ignored. = 25.042 = 25 Table21-3 contains the formulas for determining the baud rate. Example21-1 provides a sample calculation 16000000 Calculated Baud Rate = --------------------------- for determining the baud rate and baud rate error. 6425+1 Typical baud rates and error values for various = 9615 Asynchronous modes have been computed for your convenience and are shown in Table21-3. It may be Calc. Baud Rate–Desired Baud Rate Error = -------------------------------------------------------------------------------------------- advantageous to use the high baud rate (BRGH = 1) or Desired Baud Rate the 16-bit BRG (BRG16 = 1) to reduce the baud rate 9615–9600 error. The 16-bit BRG mode is used to achieve slow = ---------------------------------- = 0.16% 9600 baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH/SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock.  2013-2015 Microchip Technology Inc. DS40001723D-page 187

PIC12(L)F1571/2 TABLE 21-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula SYNC BRG16 BRGH 0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 0 1 8-bit/Asynchronous FOSC/[16 (n+1)] 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous FOSC/[4 (n+1)] 1 1 x 16-bit/Synchronous Legend: x = Don’t care; n = value of SPBRGH/SPBRGL register pair. TABLE 21-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185 SPBRGL BRG<7:0> 187* SPBRGH BRG<15:8> 187* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. DS40001723D-page 188  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % Value Value Value Value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k — — — 57.60k 0.00 7 — — — 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % Value Value Value Value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % Value Value Value Value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5  2013-2015 Microchip Technology Inc. DS40001723D-page 189

PIC12(L)F1571/2 TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % Value Value Value Value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % Value Value Value Value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % Value Value Value Value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — DS40001723D-page 190  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % Value Value Value Value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz BAUD RATE SPBRG SPBRG SPBRG SPBRG Actual % Actual % Actual % Actual % Value Value Value Value Rate Error Rate Error Rate Error Rate Error (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —  2013-2015 Microchip Technology Inc. DS40001723D-page 191

PIC12(L)F1571/2 21.4.1 AUTO-BAUD DETECT and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the The EUSART module supports automatic detection average bit time when clocked at full speed. and calibration of the baud rate. Note1: If the WUE bit is set with the ABDEN bit, In the Auto-Baud Detect (ABD) mode, the clock to the Auto-Baud Detection will occur on the BRG is reversed. Rather than the BRG clocking the byte following the Break character incoming RX signal, the RX signal is timing the BRG. (see Section21.4.3 “Auto-Wake-up on The Baud Rate Generator is used to time the period of Break”). a received 55h (ASCII “U”), which is the Sync character for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the that it has five rising edges, including the Stop bit edge. incoming character baud rate is within the range of the selected BRG clock source. Setting the ABDEN bit of the BAUDCON register starts Some combinations of oscillator frequency the auto-baud calibration sequence (Figure21-6). and EUSART baud rates are not possible. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of 3: During the auto-baud process, the the receive line, after the Start bit, the SPBRG begins auto-baud counter starts counting at 1. counting up using the BRG counter clock as shown in Upon completion of the auto-baud Table21-6. The fifth rising edge will occur on the RX pin sequence, to achieve maximum accuracy, at the end of the eighth bit period. At that time, an subtract 1 from the SPBRGH:SPBRGL accumulated value totaling the proper BRG period is register pair. left in the SPBRGH/SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag TABLE 21-6: BRG COUNTER CLOCK RATES is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be BRG Base BRG ABD BRG16 BRGH discarded. When calibrating for modes that do not use Clock Clock the SPBRGH register, the user can verify that the 0 0 FOSC/64 FOSC/512 SPBRGL register did not overflow by checking for 00h in the SPBRGH register. 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 The BRG auto-baud clock is determined by the BRG16 and BRGH bits, as shown in Table21-6. During ABD, 1 1 FOSC/4 FOSC/32 both the SPBRGH and SPBRGL registers are used as Note: During the ABD sequence, the SPBRGL a 16-bit counter, independent of the BRG16 bit setting. and SPBRGH registers are both used as a While calibrating the baud rate period, the SPBRGH 16-bit counter, independent of the BRG16 setting. FIGURE 21-6: AUTOMATIC BAUD RATE CALIBRATION BRG Value XXXXh 0000h 001Ch Edge #1 Edge #2 Edge #3 Edge #4 Edge #5 RX Pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit BRG Clock Set by User Auto Cleared ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. DS40001723D-page 192  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 21.4.2 AUTO-BAUD OVERFLOW 21.4.3.1 Special Considerations During the course of Automatic Baud Detection, the Break Character ABDOVF bit of the BAUDCON register will be set if the To avoid character errors or character fragments during baud rate counter overflows before the fifth rising edge a wake-up event, the wake-up character must be all is detected on the RX pin. The ABDOVF bit indicates zeros. that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register When the wake-up is enabled, the function works pair. The overflow condition will set the RCIF flag. The independent of the low time on the data stream. If the counter continues to count until the fifth rising edge is WUE bit is set and a valid non-zero character is detected on the RX pin. The RCIDL bit will remain false received, the low time from the Start bit to the first rising (‘0’) until the fifth rising edge, at which time, the RDICL edge will be interpreted as the wake-up event. The bit will set. If the RCREG is read after the overflow remaining bits in the character will be received as a occurs, but before the fifth rising edge, the fifth rising fragmented character and subsequent characters can edge will set the RCIF again. result in framing or overrun errors. Terminating the auto-baud process early to clear an Therefore, the initial character in the transmission must overflow condition will prevent proper detection of the be all ‘0’s. This must be ten or more bit times; 13-bit Sync character fifth rising edge. If any falling edges of times are recommended for LIN bus or any number of the Sync character have not yet occurred when the bit times for standard RS-232 devices. ABDEN bit is cleared, then those will be falsely Oscillator Start-up Time detected as Start bits. The following steps are Oscillator start-up time must be considered, especially recommended to clear the overflow condition: in applications using oscillators with longer start-up 1. Read RCREG to clear RCIF. intervals (i.e., LP, XT or HS/PLL mode). The Sync 2. If RCIDL is zero, then wait for RCIF and repeat Break (or wake-up signal) character must be of Step 1. sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator 3. Clear the ABDOVF bit. to start and provide proper initialization of the EUSART. 21.4.3 AUTO-WAKE-UP ON BREAK WUE Bit During Sleep mode, all clocks to the EUSART are The wake-up event causes a receive interrupt by suspended. Because of this, the Baud Rate Generator setting the RCIF bit. The WUE bit is cleared in is inactive and a proper character reception cannot be hardware by a rising edge on RX/DT. The interrupt performed. The auto-wake-up feature allows the condition is then cleared in software by reading the controller to wake-up due to activity on the RX/DT line. RCREG register and discarding its contents. This feature is available only in Asynchronous mode. To ensure that no actual data is lost, check the RCIDL The auto-wake-up feature is enabled by setting the WUE bit to verify that a receive operation is not in process bit of the BAUDCON register. Once set, the normal before setting the WUE bit. If a receive operation is not receive sequence on RX/DT is disabled, and the occurring, the WUE bit may then be set just prior to EUSART remains in an Idle state, monitoring for a entering the Sleep mode. wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure21-7), and asynchronously if the device is in Sleep mode (Figure21-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.  2013-2015 Microchip Technology Inc. DS40001723D-page 193

PIC12(L)F1571/2 FIGURE 21-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto-Cleared WUE bit RX/DT Line RCIF Cleared due to User Read of RCREG Note1: The EUSART remains in Idle while the WUE bit is set. FIGURE 21-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1 Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 OSC1 Bit Set by User Auto Cleared WUE bit RX/DT Note 1 Line RCIF Cleared due to User Read of RCREG Sleep Command Executed Sleep Ends Note1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. 2: The EUSART remains in Idle while the WUE bit is set. DS40001723D-page 194  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 21.4.4 BREAK CHARACTER SEQUENCE 21.4.5 RECEIVING A BREAK CHARACTER The EUSART module has the capability of sending the The Enhanced USART module can receive a Break special Break character sequences that are required by character in two ways. the LIN bus standard. A Break character consists of a The first method to detect a Break character uses the Start bit, followed by twelve ‘0’ bits and a Stop bit. FERR bit of the RCSTA register and the received data To send a Break character, set the SENDB and TXEN as indicated by RCREG. The Baud Rate Generator is bits of the TXSTA register. The Break character trans- assumed to have been initialized to the expected baud mission is then initiated by a write to the TXREG. The rate. value of data written to TXREG will be ignored and all A Break character has been received when: ‘0’s will be transmitted. • RCIF bit is set The SENDB bit is automatically reset by hardware after • FERR bit is set the corresponding Stop bit is sent. This allows the user • RCREG = 00h to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync The second method uses the auto-wake-up feature character in the LIN specification). described in Section21.4.3 “Auto-Wake-up on The TRMT bit of the TXSTA register indicates when the Break”. By enabling this feature, the EUSART will transmit operation is active or idle, just as it does during sample the next two transitions on RX/DT, cause an normal transmission. See Figure21-9 for the timing of RCIF interrupt and receive the next data byte followed the Break character sequence. by another interrupt. Note that following a Break character, the user will 21.4.4.1 Break and Sync Transmit Sequence typically want to enable the Auto-Baud Detect feature. The following sequence will start a message frame For both methods, the user can set the ABDEN bit of header made up of a Break, followed by an auto-baud the BAUDCON register before placing the EUSART in Sync byte. This sequence is typical of a LIN bus master. Sleep mode. 1. Configure the EUSART for the desired mode. 2. Set the TXEN and SENDB bits to enable the Break sequence. 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 21-9: SEND BREAK CHARACTER SEQUENCE Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB SENDB Sampled Here Auto Cleared (send Break control bit)  2013-2015 Microchip Technology Inc. DS40001723D-page 195

PIC12(L)F1571/2 21.5 EUSART Synchronous Mode 21.5.1.2 Clock Polarity Synchronous serial communications are typically used A clock polarity option is provided for Microwire in systems with a single master and one or more compatibility. Clock polarity is selected with the SCKP slaves. The master device contains the necessary bit of the BAUDCON register. Setting the SCKP bit sets circuitry for baud rate generation and supplies the clock the clock Idle state as high. When the SCKP bit is set, for all devices in the system. Slave devices can take the data changes on the falling edge of each clock. advantage of the master clock by eliminating the Clearing the SCKP bit sets the Idle state as low. When internal clock generation circuitry. the SCKP bit is cleared, the data changes on the rising edge of each clock. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the 21.5.1.3 Synchronous Master Transmission external clock supplied by the master to shift the serial Data is transferred out of the device on the RX/DT pin. data into and out of their respective Receive and Trans- The RX/DT and TX/CK pin output drivers are automat- mit Shift registers. Since the data line is bidirectional, ically enabled when the EUSART is configured for synchronous operation is half-duplex only. Half-duplex synchronous master transmit operation. refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. A transmission is initiated by writing a character to the The EUSART can operate as either a master or slave TXREG register. If the TSR still contains all or part of a device. previous character the new character data is held in the TXREG until the last bit of the previous character has Start and Stop bits are not used in synchronous been transmitted. If this is the first character, or the transmissions. previous character has been completely flushed from 21.5.1 SYNCHRONOUS MASTER MODE the TSR, the data in the TXREG is immediately trans- ferred to the TSR. The transmission of the character The following bits are used to configure the EUSART commences immediately following the transfer of the for synchronous master operation: data to the TSR from the TXREG. • SYNC = 1 Each data bit changes on the leading edge of the • CSRC = 1 master clock and remains valid until the subsequent • SREN = 0 (for transmit); SREN = 1 (for receive) leading clock edge. • CREN = 0 (for transmit); CREN = 1 (for receive) Note: The TSR register is not mapped in data • SPEN = 1 memory, so it is not available to the user. Setting the SYNC bit of the TXSTA register configures 21.5.1.4 Synchronous Master Transmission the device for synchronous operation. Setting the CSRC Setup bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA 1. Initialize the SPBRGH, SPBRGL register pair register ensures that the device is in the Transmit mode, and the BRGH and BRG16 bits to achieve the otherwise the device will be configured to receive. Setting desired baud rate (see Section21.4 “EUSART the SPEN bit of the RCSTA register enables the Baud Rate Generator (BRG)”). EUSART. 2. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. 21.5.1.1 Master Clock 3. Disable Receive mode by clearing bits, SREN Synchronous data transfers use a separate clock line, and CREN. which is synchronous with the data. A device config- 4. Enable Transmit mode by setting the TXEN bit. ured as a master transmits the clock on the TX/CK line. 5. If 9-bit transmission is desired, set the TX9 bit. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous 6. If interrupts are desired, set the TXIE bit of the transmit or receive operation. Serial data bits change PIE1 register, and the GIE and PEIE bits of the on the leading edge to ensure they are valid at the trail- INTCON register. ing edge of each clock. One clock cycle is generated 7. If 9-bit transmission is selected, the ninth bit for each data bit. Only as many clock cycles are should be loaded in the TX9D bit. generated as there are data bits. 8. Start transmission by loading data to the TXREG register. DS40001723D-page 196  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 21-10: SYNCHRONOUS TRANSMISSION RX/PDiTn bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 1 Word 2 TX/CK Pin (SCKP = 0) TX/CK Pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ ‘1’ TXEN bit Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 21-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT Pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK Pin Write to TXREG Reg. TXIF bit TRMT bit TXEN bit TABLE 21-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185 SPBRGL BRG<7:0> 187* SPBRGH BRG<15:8> 187* TXREG EUSART Transmit Data Register 177* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission. * Page provides register information. Note1: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 197

PIC12(L)F1571/2 21.5.1.5 Synchronous Master Reception 21.5.1.7 Receive Overrun Error Data is received at the RX/DT pin. The RX/DT pin The receive FIFO buffer can hold two characters. An output driver is automatically disabled when the overrun error will be generated if a third character, in its EUSART is configured for synchronous master receive entirety, is received before RCREG is read to access operation. the FIFO. When this happens, the OERR bit of the RCSTA register is set. Previous data in the FIFO will In Synchronous mode, reception is enabled by setting not be overwritten. The two characters in the FIFO either the Single Receive Enable bit (SREN of the buffer can be read, however, no additional characters RCSTA register) or the Continuous Receive Enable bit will be received until the error is cleared. The OERR bit (CREN of the RCSTA register). can only be cleared by clearing the overrun condition. When SREN is set and CREN is clear, only as many If the overrun error occurred when the SREN bit is set clock cycles are generated as there are data bits in a and CREN is clear, then the error is cleared by reading single character. The SREN bit is automatically cleared RCREG. If the overrun occurred when the CREN bit is at the completion of one character. When CREN is set, set, then the error condition is cleared by either clearing clocks are continuously generated until CREN is the CREN bit of the RCSTA register or by clearing the cleared. If CREN is cleared in the middle of a character, SPEN bit which resets the EUSART. the CK clock stops immediately and the partial charac- ter is discarded. If SREN and CREN are both set, then 21.5.1.8 Receiving 9-Bit Characters SREN is cleared at the completion of the first character The EUSART supports 9-bit character reception. When and CREN takes precedence. the RX9 bit of the RCSTA register is set the EUSART To initiate reception, set either SREN or CREN. Data is will shift 9 bits into the RSR for each character sampled at the RX/DT pin on the trailing edge of the received. The RX9D bit of the RCSTA register is the TX/CK clock pin and is shifted into the Receive Shift ninth, and Most Significant, data bit of the top unread Register (RSR). When a complete character is character in the receive FIFO. When reading 9-bit data received into the RSR, the RCIF bit is set and the char- from the receive FIFO buffer, the RX9D data bit must acter is automatically transferred to the two-character be read before reading the eight Least Significant bits receive FIFO. The Least Significant eight bits of the top from the RCREG. character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread 21.5.1.9 Synchronous Master Reception Setup characters in the receive FIFO. 1. Initialize the SPBRGH/SPBRGL register pair for Note: If the RX/DT function is on an analog pin, the appropriate baud rate. Set or clear the the corresponding ANSELx bit must be BRGH and BRG16 bits, as required, to achieve cleared for the receiver to function. the desired baud rate. 2. Clear the ANSELx bit for the RX pin (if applicable). 21.5.1.6 Slave Clock 3. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured 4. Ensure bits, CREN and SREN, are clear. as a slave receives the clock on the TX/CK line. The 5. If interrupts are desired, set the RCIE bit of the TX/CK pin output driver is automatically disabled when PIE1 register, and the GIE and PEIE bits of the the device is configured for synchronous slave transmit INTCON register. or receive operation. Serial data bits change on the 6. If 9-bit reception is desired, set bit, RX9. leading edge to ensure they are valid at the trailing edge 7. Start reception by setting the SREN bit or for of each clock. One data bit is transferred for each clock continuous reception, set the CREN bit. cycle. Only as many clock cycles should be received as 8. Interrupt flag bit, RCIF, will be set when recep- there are data bits. tion of a character is complete. An interrupt will Note: If the device is configured as a slave and be generated if the enable bit, RCIE, was set. the TX/CK function is on an analog pin, the 9. Read the RCSTA register to get the ninth bit (if corresponding ANSELx bit must be enabled) and determine if any error occurred cleared. during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. DS40001723D-page 198  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 21-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Pin TX/CK Pin (SCKP = 0) TX/CK Pin (SCKP = 1) Write to SREN bit SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 21-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 RCREG EUSART Receive Data Register 180* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185 SPBRGL BRG<7:0> 187* SPBRGH BRG<15:8> 187* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception. * Page provides register information. Note1: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 199

PIC12(L)F1571/2 21.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the EUSART for synchronous slave operation: 1. The first character will immediately transfer to the TSR register and transmit. • SYNC = 1 2. The second word will remain in the TXREG • CSRC = 0 register. • SREN = 0 (for transmit); SREN = 1 (for receive) 3. The TXIF bit will not be set. • CREN = 0 (for transmit); CREN = 1 (for receive) 4. After the first character has been shifted out of • SPEN = 1 TSR, the TXREG register will transfer the Setting the SYNC bit of the TXSTA register configures the second character to the TSR and the TXIF bit device for synchronous operation. Clearing the CSRC bit will now be set. of the TXSTA register configures the device as a slave. 5. If the PEIE and TXIE bits are set, the interrupt Clearing the SREN and CREN bits of the RCSTA register will wake the device from Sleep and execute the ensures that the device is in Transmit mode; otherwise, next instruction. If the GIE bit is also set, the the device will be configured to receive. Setting the SPEN program will call the Interrupt Service Routine. bit of the RCSTA register enables the EUSART. 21.5.2.2 Synchronous Slave Transmission 21.5.2.1 EUSART Synchronous Slave Setup Transmit 1. Set the SYNC and SPEN bits, and clear the The operation of the Synchronous Master and CSRC bit. Slave modes is identical (see Section21.5.1.3 2. Clear the ANSELx bit for the CK pin (if applicable). “Synchronous Master Transmission”), except in the 3. Clear the CREN and SREN bits. case of Sleep mode. 4. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit transmission is desired, set the TX9 bit. 6. Enable transmission by setting the TXEN bit. 7. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 8. Start transmission by writing the Least Significant eight bits to the TXREG register. TABLE 21-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185 TXREG EUSART Transmit Data Register 177* TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission. * Page provides register information. Note1: PIC12(L)F1572 only. DS40001723D-page 200  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 21.5.2.3 EUSART Synchronous Slave 21.5.2.4 Synchronous Slave Reception Setup Reception 1. Set the SYNC and SPEN bits, and clear the The operation of the Synchronous Master and Slave CSRC bit. modes is identical (Section21.5.1.5 “Synchronous 2. Clear the ANSELx bit for both the CK and DT Master Reception”), with the following exceptions: pins (if applicable). • Sleep 3. If interrupts are desired, set the RCIE bit of the • CREN bit is always set, therefore, the receiver is PIE1 register, and the GIE and PEIE bits of the never Idle INTCON register. • SREN bit, which is a “don’t care” in Slave mode 4. If 9-bit reception is desired, set the RX9 bit. 5. Set the CREN bit to enable reception. A character may be received while in Sleep mode by 6. The RCIF bit will be set when reception is setting the CREN bit prior to entering Sleep. Once the complete. An interrupt will be generated if the word is received, the RSR register will transfer the data RCIE bit was set. to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep 7. If 9-bit mode is enabled, retrieve the Most and execute the next instruction. If the GIE bit is also Significant bit from the RX9D bit of the RCSTA set, the program will branch to the interrupt vector. register. 8. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 21-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 186 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74 PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78 RCREG EUSART Receive Data Register 180* RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception. * Page provides register information. Note1: PIC12(L)F1572 only.  2013-2015 Microchip Technology Inc. DS40001723D-page 201

PIC12(L)F1571/2 NOTES: DS40001723D-page 202  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 22.0 16-BIT PULSE-WIDTH Each PWM module has four Offset modes: MODULATION (PWM) MODULE • Independent Run • Slave Run with Synchronous Start The Pulse-Width Modulation (PWM) module generates • One-Shot Slave with Synchronous Start a pulse-width modulated signal determined by the phase, duty cycle, period and offset event counts that • Continuous Run Slave with Synchronous Start are contained in the following registers: and Timer Reset • PWMxPH register Using the Offset modes, each PWM module can offset • PWMxDC register its waveform relative to any other PWM module in the same device. For a more detailed description of the • PWMxPR register Offset modes, refer to Section22.3 “Offset Modes”. • PWMxOF register Every PWM module has a configurable reload Figure22-1 shows a simplified block diagram of the operation to ensure all event count buffers change at PWM operation. the end of a period, thereby avoiding signal glitches. Each PWM module has four modes of operation: Figure22-2 shows a simplified block diagram of the • Standard reload operation. For a more detailed description of • Set On Match the reload operation, refer to Section22.4 “Reload Operation”. • Toggle On Match • Center-Aligned For a more detailed description of each PWM mode, refer to Section22.2 “PWM Modes”. FIGURE 22-1: 16-BIT PWM BLOCK DIAGRAM MODE<1:0> Rev. 10-000152A 4/21/2014 EN PHx_match PWM Control DCx_match Unit D Q PWMxOUT Q4 CK OF3_match(1) 11 PWMxPOL OF2_match(1) 10 OF_match PWMx_output To Peripherals Offset OF1_match(1) 01 PRx_match Control PWMxOE Reserved 00 PWMx OFM<1:0> OFS E R U/D PWM_clock PWMxTMR TRIS Control PRx_match PHx_match OFx_match DCx_match Comparator Comparator Comparator Comparator set PRIF set PHIF set OFIF set DCIF LDx_trigger LDx_trigger LDx_trigger LDx_trigger 16-bt Latch 16-bt Latch 16-bt Latch 16-bt Latch PWMxPR PWMxPH PWMxOF PWMxDC Note 1: A PWM module cannot trigger from its own offset match event. The input corresponding to a PWM module’s own offset match is reserved.  2013-2015 Microchip Technology Inc. DS40001723D-page 203

PIC12(L)F1571/2 FIGURE 22-2: LOAD TRIGGER BLOCK DIAGRAM Rev. 10-000153A 4/21/2014 LD3_trigger(1) 11 LD2_trigger(1) 10 LD1_trigger(1) 01 Reserved 00 1 LDx_trigger 0 D Q PWMxLDA(2) PWMxLDS PRx_match PWMxLDT PWM_clock Note 1.The input corresponding to a PWM module’s own load trigger is reserved. 2. PWMxLDA is cleared by hardware upon LDx_trigger. 22.1 Fundamental Operation FIGURE 22-3: PWM CLOCK SOURCE BLOCK DIAGRAM The PWM module produces a 16-bit resolution pulse-width modulated output. Rev. 10-000156A 1/7/2015 Each PWM module has an independent timer driven by a selection of clock sources determined by the PWMxCS<1:0> PWMxCLKCON register (Register22-4). The timer value is compared to event count registers to generate the various events of a the PWM waveform, such as the FOSC 00 PWMxPS<2:0> period and duty cycle. For a block diagram describing HFINTOSC 01 the clock sources, refer to Figure22-3. Prescaler PWMx_clock LFINTOSC 10 Each PWM module can be enabled individually using Reserved 11 the EN bit of the PWMxCON register, or several PWM modules can be enabled simultaneously using the mirror bits of the PWMEN register. The current state of the PWM output can be read using the OUT bit of the PWMxCON register. In some modes, 22.1.1 PWMx PIN CONFIGURATION this bit can be set and cleared by software, giving All PWM outputs are multiplexed with the PORT data additional software control over the PWM waveform. latch, so the pins must also be configured as outputs by This bit is synchronized to FOSC/4 and therefore, does clearing the associated PORT TRISx bits. not change in real time with respect to the PWM_clock. The slew rate feature may be configured to optimize Note: If PWM_clock > FOSC/4, the OUT bit may the rate to be used in conjunction with the PWM not accurately represent the output state of outputs. High-speed output switching is attained by the PWM. clearing the associated PORT SLRCONx bits. The PWM outputs can be configured to be open-drain outputs by setting the associated PORT ODCONx bits. 22.1.2 PWMx Output Polarity The output polarity is inverted by setting the POL bit of the PWMxCON register. The polarity control affects the PWM output even when the module is not enabled. DS40001723D-page 204  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 22.2 PWM Modes The OUT bit can be used to set or clear the output of the PWM in this mode. Writes to this bit will take place PWM modes are selected with the MODE<1:0> bits of on the next rising edge of the PWM_clock after the bit the PWMxCON register (Register22-1). is written. In all PWM modes, an offset match event can also be A detailed timing diagram for Set On Match mode is used to synchronize the PWMxTMR in three Offset shown in Figure22-5. modes. See Section 22.3“Offset Modes” for more information. 22.2.3 TOGGLE ON MATCH MODE 22.2.1 STANDARD MODE The Toggle On Match mode (MODE<1:0> = 10) gener- ates a 50% duty cycle PWM with a period twice as long The Standard mode (MODE<1:0> = 00) selects a as that computed for the Standard PWM mode. Duty single-phase PWM output. The PWM output in this cycle count has no effect in this mode. The phase count mode is determined by when the period, duty cycle and determines how many PWMxTMR periods, after a phase counts match the PWMxTMR value. The start of period event, the output will toggle. the duty cycle occurs on the phase match and the end Writes to the OUT bit of the PWMxCON register will of the duty cycle occurs on the duty cycle match. The have no effect in this mode. period match resets the timer. The offset match can also be used to synchronize the PWMxTMR in the A detailed timing diagram for Toggle On Match mode is Offset modes. See Section 22.3“Offset Modes” for shown in Figure22-6. more information. 22.2.4 CENTER-ALIGNED MODE Equation22-1 is used to calculate the PWM period in Standard mode. The Center-Aligned mode (MODE = 11) generates a PWM waveform that is centered in the period. In this Equation22-2 is used to calculate the PWM duty cycle mode, the period is two times the PWMxPR count. The ratio in Standard mode. PWMxTMR counts up to the period value, then counts back down to 0. The duty cycle count determines both EQUATION 22-1: PWM PERIOD IN the start and end of the active PWM output. The start of STANDARD MODE the duty cycle occurs at the match event when PWMxTMR is incrementing and the duty cycle ends at PWMxPR+1Prescale the match event when PWMxTMR is decrementing. Period = -------------------------------------------------------------------- The incrementing match value is the period count PWMxCLK minus the duty cycle count. The decrementing match value is the incrementing match value plus 1. Equation22-3 is used to calculate the PWM period in EQUATION 22-2: PWM DUTY CYCLE IN Center-Aligned mode. STANDARD MODE EQUATION 22-3: PWM PERIOD IN CENTER-ALIGNED MODE PWMxDC –PWMxPH Duty Cycle = ----------------------------------------------------------------- PWMxPR+1 PWMxPR+1Prescale2 Period = --------------------------------------------------------------------------- PWMxCLK A detailed timing diagram for Standard mode is shown in Figure22-4. Equation22-4 is used to calculate the PWM duty cycle ratio in Center-Aligned mode. 22.2.2 SET ON MATCH MODE The Set On Match mode (MODE<1:0> = 01) generates EQUATION 22-4: PWM DUTY CYCLE IN an active output when the phase count matches the CENTER-ALIGNED MODE PWMxTMR value. The output stays active until the OUT bit of the PWMxCON register is cleared or the PWMxDC2 Duty Cycle = ------------------------------------------------- PWM module is disabled. The duty cycle count has no PWMxPR+12 effect in this mode. The period count only determines the maximum PWMxTMR value above which no phase matches can occur. Writes to the OUT bit will have no effect in this mode. A detailed timing diagram for Center-Aligned mode is shown in Figure22-7.  2013-2015 Microchip Technology Inc. DS40001723D-page 205

D FIGURE 22-4: STANDARD PWM MODE TIMING DIAGRAM P S 40 I 0 C 0 1 Rev. 10-000142A 7 9/5/2013 1 2 3D 2 -p Period ( ag L e Duty Cycle 2 ) 06 Phase F 1 PWMxCLK 5 PWMxPR 10 7 1 PWMxPH 4 / PWMxDC 9 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT FIGURE 22-5: SET ON MATCH PWM MODE TIMING DIAGRAM Rev. 10-000143A 9/5/2013 Period Phase  2 PWMxCLK 0 1 3 -2 PWMxPR 10 0 15 PWMxPH 4 M ic PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 ro c h ip PWMxOUT T e c h n o lo g y In c .

 FIGURE 22-6: TOGGLE ON MATCH PWM MODE TIMING DIAGRAM 2 0 1 3 -2 0 1 5 M Rev. 10-090/50/124041A3 ic ro c Period h ip T Phase e ch PWMxCLK n o log PWMxPR 10 y In PWMxPH 4 c . PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT FIGURE 22-7: CENTER-ALIGNED PWM MODE TIMING DIAGRAM ReRve. v1.0 41-00/204-200/20/122040/511240A451A4 PPeerioriodd DDuutyty C Cyycclele P PPWWMMxCxCLLKK I C PPWWMMxPxPRR 66 1 PPWWMMxDxDCC 44 2 PPWWMMxTxMTMRR 00 11 22 33 44 55 66 66 55 44 33 22 11 00 00 11 22 33 (L D S 4 ) 00 PPWWMMxxOOUUTT F 0 1 1 7 2 5 3 D -p 7 ag 1 e 20 /2 7

PIC12(L)F1571/2 22.3 Offset Modes 22.3.4 CONTINUOUS RUN SLAVE MODE WITH SYNC START AND TIMER The Offset modes provide the means to adjust the wave- RESET form of a slave PWM module relative to the waveform of a master PWM module in the same device. In Continuous Run Slave mode with Synchronous Start and Timer Reset (OFM<1:0> = 11), the slave 22.3.1 INDEPENDENT RUN MODE PWMxTMR is inhibited from counting after the slave PWM enable is set. The first master OFx_match event In Independent Run mode (OFM<1:0> = 00), the PWM starts the slave PWMxTMR. Subsequent master module is unaffected by the other PWM modules in the OFx_match events reset the slave PWMxTMR timer device. The PWMxTMR associated with the PWM value back to 1, after which, the slave PWMxTMR con- module in this mode starts counting as soon as the EN bit tinues to count. The next master OFx_match event associated with this PWM module is set and continues resets the slave PWMxTMR back to 1 to repeat the counting until the EN bit is cleared. Period events reset cycle. Slave period events that occur before the the PWMxTMR to zero, after which, the timer continues to master’s OFx_match event will reset the slave count. PWMxTMR to zero, after which, the timer will continue A detailed timing diagram of this mode used with to count. Slaves operating in this mode must have a Standard PWM mode is shown in Figure22-8. PWMxPH register pair value equal to or greater than 1; otherwise, the phase match event will not occur 22.3.2 SLAVE RUN MODE WITH SYNC START precluding the start of the PWM output duty cycle. In Slave Run mode with Sync Start (OFM<1:0> = 01), The offset timing will persist If both the master and the slave PWMxTMR waits for the master’s OFx_match slave PWMxPR values are the same, and the Slave event. When this event occurs, if the EN bit is set, the Offset mode is changed to Independent Run mode PWMxTMR begins counting and continues to count while the PWM module is operating. until software clears the EN bit. Slave period events reset the PWMxTMR to zero, after which, the timer A detailed timing diagram of this mode used in continues to count. Standard PWM mode is shown in Figure22-11. A detailed timing diagram of this mode used with Note: Unexpected results will occur if the slave Standard PWM mode is shown in Figure22-9. PWM_clock is a higher frequency than the master PWM_clock. 22.3.3 ONE-SHOT SLAVE MODE WITH SYNC START 22.3.5 OFFSET MATCH IN In One-Shot Slave mode with Synchronous Start CENTER-ALIGNED MODE (OFM<1:0> = 10), the slave PWMxTMR waits until the When a master is operating in Center-Aligned mode, master's OFx_match event. The timer then begins count- the offset match event depends on which direction the ing, starting from the value that is already in the timer, and PWMxTMR is counting. Clearing the OFO bit of the continues to count until the period match event. When the PWMxOFCON register will cause the OFx_match period event occurs, the timer resets to zero and stops event to occur when the timer is counting up. Setting counting. The timer then waits until the next master the OFO bit of the PWMxOFCON register will cause OFx_match event, after which, it begins counting again to the OFx_match event to occur when the timer is repeat the cycle. An OFx_match event that occurs before counting down. The OFO bit is ignored in the slave PWM has completed the previously triggered non-Center-Aligned modes. period will be ignored. A slave period that is greater than the master period, but less than twice the master period, The OFO bit is double-buffered and requires setting the will result in a slave output every other master period. LDA bit to take effect when the PWM module is operating. Note: During the time the slave timers are Detailed timing diagrams of Center-Aligned mode resetting to zero, if another offset match using offset match control in Independent Slave with event is received, it is possible that the slave Sync Start mode can be seen in Figure22-12 and PWM would not recognize this match event Figure22-13. and the slave timers would fail to begin counting again. This would result in missing duty cycles from the output of the slave PWM. To prevent this from happening, avoid using the same period for both the master and slave PWMs. A detailed timing diagram of this mode used with Standard PWM mode is shown in Figure22-10. DS40001723D-page 208  2013-2015 Microchip Technology Inc.

 FIGURE 22-8: INDEPENDENT RUN MODE TIMING DIAGRAM 2 0 1 3 -2 01 Rev. 10-070/80/124061B5 5 M icro Period c hip Duty Cycle T e Phase c h n Offset o lo g PWMxCLK y In c PWMxPR 10 . PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT OFx_match PHx_match DCx_match PRx_match P PWMyTMR 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 I C PWMyPR 4 1 PWMyPH 0 2 ( PWMyDC 1 L D S 40 PWMyOUT )F 0 0 17 Note: PWMx = Master, PWMy = Slave 1 2 5 3 D -p 7 ag 1 e 20 /2 9

D FIGURE 22-9: SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM P S 40 I 0 C 0 1 72 Rev. 10-070/80/124071B5 1 3D 2 -p ( ag Period L e 2 Duty Cycle ) 1 F 0 Phase 1 Offset 5 PWMxCLK 7 1 PWMxPR 10 / 2 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT OFx_match PWMyTMR 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 PWMyPR 4 PWMyPH 0 PWMyDC 1  PWMyOUT 2 0 1 Note: Master = PWMx, Slave = PWMy 3 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 FIGURE 22-10: ONE-SHOT SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM 2 0 1 3 -2 0 1 5 M Rev. 10-070/80/124081B5 ic roc Period h ip T Duty Cycle e c Phase h n olo Offset g y PWMxCLK In c . PWMxPR 10 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT OFx_match PWMyTMR 0 1 2 3 4 0 1 2 3 4 PWMyPR 4 PWMyPH 0 PWMyDC 1 P I PWMyOUT C 1 Note: Master = PWMx, Slave = PWMy 2 ( L D S 4 ) 0 F 0 0 1 1 7 2 5 3 D -p 7 ag 1 e 21 /2 1

D FIGURE 22-11: CONTINUOUS SLAVE RUN MODE WITH IMMEDIATE RESET AND SYNC START TIMING DIAGRAM P S 40 I 0 C 0 1 7 1 23D Rev. 10-070/80/124091B5 2 -p ( ag Period L e 2 Duty Cycle ) 1 F 2 Phase 1 Offset 5 7 PWMxCLK 1 PWMxPR 10 / 2 PWMxPH 3 PWMxDC 5 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 PWMxOUT OFx_match PWMyTMR 0 1 2 3 4 0 1 2 3 4 0 1 1 2 3 4 PWMyPR 4 PWMyPH 1 PWMyDC 2  PWMyOUT 2 0 1 3 -2 Note: Master= PWMx, Slave=PWMy 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 FIGURE 22-12: OFFSET MATCH ON INCREMENTING TIMER TIMING DIAGRAM 2 0 1 3 -2 0 15 Rev. 10-070/90/125001B5 M ic ro Period c h ip Duty Cycle T e Offset c h no PWMxCLK lo g y PWMxPR 6 In c. PWMxDC 2 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3 PWMxOUT OFx_match PHx_match DCx_match PRx_match PWMyTMR 0 0 1 2 3 4 4 3 2 1 0 0 0 1 P PWMyPR 4 I PWMyDC 1 C 1 PWMyOUT 2 Note: Master = PWMx, Slave = PWMy ( L D S 4 ) 0 F 0 0 1 1 7 2 5 3 D -p 7 ag 1 e 21 /2 3

D FIGURE 22-13: OFFSET MATCH ON DECREMENTING TIMER TIMING DIAGRAM P S 40 I 0 C 0 1 7 1 23D Rev. 10-070/90/125011B5 2 -p ( ag Period L e 2 Duty Cycle ) 1 F 4 Offset 1 PWMxCLK 5 7 PWMxPR 6 1 PWMxDC 2 / 2 PWMxOF 2 PWMxTMR 0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3 PWMxOUT OF5_match PH5_match DC5_match PR5_match PWMyTMR 0 0 1 2 3 4 4 3 PWMyPR 4  2 PWMyDC 1 0 1 3-2 PWMyOUT 0 1 5 Note: Master = PWMx, Slave = PWMy M ic ro c h ip T e c h n o lo g y In c .

PIC12(L)F1571/2 22.4 Reload Operation 22.4.2 TRIGGERED RELOAD Four of the PWM module control register pairs and one When the LDT bit is set, then the Triggered mode is control bit are double-buffered so that all can be selected and a trigger event is required for the LDA bit updated simultaneously. These include: to take effect. The trigger source is the buffer load event of one of the other PWM modules in the device. • PWMxPHH:PWMxPHL register pair The triggering source is selected by the LDS<1:0> bits • PWMxDCH:PWMxDCL register pair of the PWMxLDCON register. The buffers will be • PWMxPRH:PWMxPRL register pair loaded at the first period event following the trigger • PWMxOFH:PWMxOFL register pair event. Triggered reloading is used when a PWM module is operating as a slave to another PWM and it • OFO control bit is necessary to synchronize the buffer reloads in both When written to, these registers do not immediately modules. affect the operation of the PWM. By default, writes to these registers will not be loaded into the PWM Oper- Note1: The buffer load operation clears the ating Buffer registers until after the arming conditions LDA bit. are met. The arming control has two methods of 2: If the LDA bit is set at the same time as operation: PWMxTMR = PWMxPR, the LDA bit is • Immediate ignored until the next period event. Such is the case when triggered reload is • Triggered selected and the triggering event occurs The LDT bit of the PWMxLDCON register controls the simultaneously with the target’s period arming method. Both methods require the LDA bit to be event. set. All four buffer pairs will load simultaneously at the loading event. 22.5 Operation in Sleep Mode 22.4.1 IMMEDIATE RELOAD Each PWM module will continue to operate in Sleep When the LDT bit is clear, then the immediate mode is mode when either the HFINTOSC or LFINTOSC is selected and the buffers will be loaded at the first period selected as the clock source by PWMxCLKCON<1:0>. event after the LDA bit is set. Immediate reloading is used when a PWM module is operating stand-alone or 22.6 Interrupts when the PWM module is operating as a master to other slave PWM modules. Each PWM module has four independent interrupts based on the phase, duty cycle, period and offset match events. The interrupt flag is set on the rising edge of each of these signals. Refer to Figures 22-12 and 22-13 for detailed timing diagrams of the match signals.  2013-2015 Microchip Technology Inc. DS40001723D-page 215

PIC12(L)F1571/2 22.7 Register Definitions: PWM Control TABLE 22-1: BIT NAME PREFIXES Long bit name prefixes for the 16-bit PWM peripherals Peripheral Bit Name Prefix are shown in Table22-1. Refer to Section PWM1 PWM1 1.1“Register and Bit Naming Conventions” for more PWM2 PWM2 information PWM3 PWM3 REGISTER 22-1: PWMxCON: PWMx CONTROL REGISTER R/W-0/0 R/W-0/0 R/HS/HC-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 EN OE OUT POL MODE<1:0> — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 EN: PWMx Module Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 OE: PWMx Output Enable bit 1 = PWM output pin is enabled 0 = PWM output pin is disabled bit 5 OUT: Output State of the PWMx Module bit bit 4 POL: PWMx Output Polarity Control bit 1 = PWM output active state is low 0 = PWM output active state is high bit 3-2 MODE<1:0>: PWMx Mode Control bits 11 = Center-Aligned mode 10 = Toggle On Match mode 01 = Set On Match mode 00 = Standard PWM mode bit 1-0 Unimplemented: Read as ‘0’ DS40001723D-page 216  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 22-2: PWMxINTE: PWMx INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — OFIE PHIE DCIE PRIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 OFIE: Offset Interrupt Enable bit 1 = Interrupts CPU on offset match 0 = Does not interrupt CPU on offset match bit 2 PHIE: Phase Interrupt Enable bit 1 = Interrupts CPU on phase match 0 = Does not Interrupt CPU on phase match bit 1 DCIE: Duty Cycle Interrupt Enable bit 1 = Interrupts CPU on duty cycle match 0 = Does not interrupt CPU on duty cycle match bit 0 PRIE: Period Interrupt Enable bit 1 = Interrupts CPU on period match 0 = Does not interrupt CPU on period match  2013-2015 Microchip Technology Inc. DS40001723D-page 217

PIC12(L)F1571/2 REGISTER 22-3: PWMxINTF: PWMx INTERRUPT REQUEST REGISTER U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 — — — — OFIF PHIF DCIF PRIF bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 OFIF: Offset Interrupt Flag bit(1) 1 = Offset match event occurred 0 = Offset match event did not occur bit 2 PHIF: Phase Interrupt Flag bit(1) 1 = Phase match event occurred 0 = Phase match event did not occur bit 1 DCIF: Duty Cycle Interrupt Flag bit(1) 1 = Duty cycle match event occurred 0 = Duty cycle match event did not occur bit 0 PRIF: Period Interrupt Flag bit(1) 1 = Period match event occurred 0 = Period match event did not occur Note 1: Bit is forced clear by hardware while module is disabled (EN = 0). DS40001723D-page 218  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 22-4: PWMxCLKCON: PWMx CLOCK CONTROL REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — PS<2:0> — — CS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6-4 PS<2:0>: Clock Source Prescaler Select bits 111 = Divides clock source by 128 110 = Divides clock source by 64 101 = Divides clock source by 32 100 = Divides clock source by 16 011 = Divides clock source by 8 010 = Divides clock source by 4 001 = Divides clock source by 2 000 = No prescaler bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CS<1:0>: Clock Source Select bits 11 = Reserved 10 = LFINTOSC (continues to operate during Sleep) 01 = HFINTOSC (continues to operate during Sleep) 00 = FOSC  2013-2015 Microchip Technology Inc. DS40001723D-page 219

PIC12(L)F1571/2 REGISTER 22-5: PWMxLDCON: PWMx RELOAD TRIGGER SOURCE SELECT REGISTER R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 LDA(1) LDT — — — — LDS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 LDA: Load Buffer Armed bit(1) If LDT = 1: 1 = Loads the OFx, PHx, DCx and PRx buffers at the end of the period when the selected trigger occurs 0 = Does not load buffers or load has completed If LDT = 0: 1 = Loads the OFx, PHx, DCx and PRx buffers at the end of the current period 0 = Does not load buffers or load has completed bit 6 LDT: Load Buffer on Trigger bit 1 = Loads buffers on trigger enabled 0 = Loads buffers on trigger disabled Loads the OFx, PHx, DCx and PRx buffers at the end of every period after the selected trigger occurs. Reloads internal double buffers at the end of current period. The LDS<1:0> bits are ignored. bit 5-2 Unimplemented: Read as ‘0’ bit 1-0 LDS<1:0>: Load Trigger Source Select bits 11 = LD3_trigger(2) 10 = LD2_trigger(2) 01 = LD1_trigger(2) 00 = Reserved Note 1: This bit is cleared by the module after a reload operation. It can be cleared in software to clear an existing arming event. 2: The LD_trigger corresponding to the PWM used becomes reserved. DS40001723D-page 220  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 22-6: PWMxOFCON: PWMx OFFSET TRIGGER SOURCE SELECT REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 — OFM<1:0> OFO(1) — — OFS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 Unimplemented: Read as ‘0’ bit 6-5 OFM<1:0>: Offset Mode Select bits 11 = Continuous Slave Run mode with immediate Reset and synchronized start when the selected offset trigger occurs 10 = One-Shot Slave Run mode with synchronized start when the selected offset trigger occurs 01 = Independent Slave Run mode with synchronized start when the selected offset trigger occurs 00 = Independent Run mode bit 4 OFO: Offset Match Output Control bit(1) If MODE<1:0> = 11 (PWM Center-Aligned mode): 1 = OFx_match occurs on counter match when counter decrementing, (second match) 0 = OFx_match occurs on counter match when counter incrementing, (first match) If MODE<1:0> = 00, 01 or 10 (all other modes): Bit is ignored. bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 OFS<1:0>: Offset Trigger Source Select bits 11 = OF3_match(1) 10 = OF2_match(1) 01 = OF1_match(1) 00 = Reserved Note 1: The OFx_match corresponding to the PWM used becomes reserved.  2013-2015 Microchip Technology Inc. DS40001723D-page 221

PIC12(L)F1571/2 REGISTER 22-7: PWMxPHH: PWMx PHASE COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PH<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PH<15:8>: PWMx Phase High bits Upper eight bits of PWM phase count. REGISTER 22-8: PWMxPHL: PWMx PHASE COUNT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PH<7:0>: PWMx Phase Low bits Lower eight bits of PWM phase count. DS40001723D-page 222  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 22-9: PWMxDCH: PWMx DUTY CYCLE COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 DC<15:8>: PWMx Duty Cycle High bits Upper eight bits of PWM duty cycle count. REGISTER 22-10: PWMxDCL: PWMx DUTY CYCLE COUNT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 DC<7:0>: PWMx Duty Cycle Low bits Lower eight bits of PWM duty cycle count.  2013-2015 Microchip Technology Inc. DS40001723D-page 223

PIC12(L)F1571/2 REGISTER 22-11: PWMxPRH: PWMx PERIOD COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PR<15:8>: PWMx Period High bits Upper eight bits of PWM period count. REGISTER 22-12: PWMxPRL: PWMx PERIOD COUNT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 PR<7:0>: PWMx Period Low bits Lower eight bits of PWM period count. DS40001723D-page 224  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 22-13: PWMxOFH: PWMx OFFSET COUNT HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u OF<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 OF<15:8>: PWMx Offset High bits Upper eight bits of PWM offset count. REGISTER 22-14: PWMxOFL: PWMx OFFSET COUNT LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u OF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 OF<7:0>: PWMx Offset Low bits Lower eight bits of PWM offset count.  2013-2015 Microchip Technology Inc. DS40001723D-page 225

PIC12(L)F1571/2 REGISTER 22-15: PWMxTMRH: PWMx TIMER HIGH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u TMR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 TMR<15:8>: PWMx Timer High bits Upper eight bits of PWM timer counter. REGISTER 22-16: PWMxTMRL: PWMx TIMER LOW REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u TMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 TMR<7:0>: PWMx Timer Low bits Lower eight bits of PWM timer counter. DS40001723D-page 226  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 Note: There are no long and short bit name variants for the following three mirror registers REGISTER 22-17: PWMEN: PWMEN BIT ACCESS REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — PWM3EN_A PWM2EN_A PWM1EN_A bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 PWMxEN_A: PWM3/PWM2/PWM1 Enable bits Mirror copy of EN bit (PWMxCON<7>). REGISTER 22-18: PWMLD: LD BIT ACCESS REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 PWMxLDA_A: PWM3/PWM2/PWM1 LD bits Mirror copy of LD bit (PWMxLDCON<7>). REGISTER 22-19: PWMOUT: PWMOUT BIT ACCESS REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 PWMxOUT_A: PWM3/PWM2/PWM1 Output bits Mirror copy of OUT bit (PWMxCON<5>).  2013-2015 Microchip Technology Inc. DS40001723D-page 227

PIC12(L)F1571/2 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH PWM Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page OSCCON SPLLEN IRCF<3:0> — SCS<1:0> 55 PIE3 — PWM3IE PWM2IE PWM1IE — — — — 77 PIR3 — PWM3IF PWM2IF PWM1IF — — — — 80 PWMEN — — — — — PWM3EN_A PWM2EN_A PWM1EN_A 227 PWMLD — — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A 227 PWMOUT — — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A 227 PWM1PHL PH<7:0> 222 PWM1PHH PH<15:8> 222 PWM1DCL DC<7:0> 223 PWM1DCH DC<15:8> 223 PWM1PRH PR<7:0> 224 PWM1PRL PR<15:8> 224 PWM1OFH OF<7:0> 225 PWM1OFL OF<15:8> 225 PWM1TMRH TMR<7:0> 226 PWM1TMRL TMR<15:8> 226 PWM1CON EN OE OUT POL MODE<1:0> — — 216 PWM1INTE — — — — OFIE PHIE DCIE PRIE 217 PWM1INTF — — — — OFIF PHIF DCIF PRIF 218 PWM1CLKCON — PS<2:0> — — CS<1:0> 219 PWM1LDCON LDA LDT — — — — LDS<1:0> 220 PWM1OFCON — OFM<1:0> OFO — — OFS<1:0> 221 PWM2PHL PH<7:0> 222 PWM2PHH PH<15:8> 222 PWM2DCL DC<7:0> 223 PWM2DCH DC<15:8> 223 PWM2PRL PR<7:0> 224 PWM2PRH PR<15:8> 224 PWM2OFL OF<7:0> 225 PWM2OFH OF<15:8> 225 PWM2TMRL TMR<7:0> 226 PWM2TMRH TMR<15:8> 226 PWM2CON EN OE OUT POL MODE<1:0> — — 216 PWM2INTE — — — — OFIE PHIE DCIE PRIE 217 PWM2INTF — — — — OFIF PHIF DCIF PRIF 218 PWM2CLKCON — PS<2:0> — — CS<1:0> 219 PWM2LDCON LDA LDT — — — — LDS<1:0> 220 PWM2OFCON — OFM<1:0> OFO — — OFS<1:0> 221 PWM3PHL PH<7:0> 222 PWM3PHH PH<15:8> 222 PWM3DCL DC<7:0> 223 PWM3DCH DC<15:8> 223 PWM3PRL PR<7:0> 224 PWM3PRH PR<15:8> 224 PWM3OFL OF<7:0> 225 PWM3OFH OF<15:8> 225 PWM3TMRL TMR<7:0> 226 PWM3TMRH TMR<15:8> 226 PWM3CON EN OE OUT POL MODE<1:0> — — 216 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. DS40001723D-page 228  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH PWM (CONTINUED) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page PWM3INTE — — — — OFIE PHIE DCIE PRIE 217 PWM3INTF — — — — OFIF PHIF DCIF PRIF 218 PWM3CLKCON — PS<2:0> — — CS<1:0> 219 PWM3LDCON LDA LDT — — — — LDS<1:0> 220 PWM3OFCON — OFM<1:0> OFO — — OFS<1:0> 221 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. TABLE 22-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Register Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 on Page 13:8 — — — — CLKOUTEN BOREN<1:0> — CONFIG1 42 7:0 CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.  2013-2015 Microchip Technology Inc. DS40001723D-page 229

PIC12(L)F1571/2 NOTES: DS40001723D-page 230  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 23.0 COMPLEMENTARY WAVEFORM 23.3 Selectable Input Sources GENERATOR (CWG) MODULE The CWG generates the output waveforms from the input sources in Table23-1. The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources. TABLE 23-1: SELECTABLE INPUT SOURCES The CWG module has the following features: Source Peripheral Signal Name • Selectable dead-band clock source control • Selectable input sources Comparator C1 C1OUT_sync • Output enable control PWM1 PWM1_output • Output polarity control PWM2 PWM2_output • Dead-band control with independent 6-bit rising PWM3 PWM3_output and falling edge dead-band counters The input sources are selected using the GxIS<2:0> • Auto-shutdown control with: bits in the CWGxCON1 register (Register23-2). - Selectable shutdown sources - Auto-restart enable 23.4 Output Control - Auto-shutdown pin override control Immediately after the CWG module is enabled, the 23.1 Fundamental Operation complementary drive is configured with both CWGxA and CWGxB drives cleared. The CWG generates two output waveforms from the selected input source. 23.4.1 OUTPUT ENABLES The off-to-on transition of each output can be delayed Each CWG output pin has individual output enable from the on-to-off transition of the other output, thereby, control. Output enables are selected with the GxOEA creating a time delay immediately where neither output and GxOEB bits of the CWGxCON0 register. When an is driven. This is referred to as dead time and is covered output enable control is cleared, the module asserts no in Section23.5 “Dead-Band Control”. A typical control over the pin. When an output enable is set, the operating waveform with dead band, generated from a override value or active PWM waveform is applied to single input signal, is shown in Figure23-2. the pin per the port priority selection. The output pin enables are dependent on the module enable bit, It may be necessary to guard against the possibility of GxEN. When GxEN is cleared, CWG output enables circuit Faults or a feedback event arriving too late, or and CWG drive levels have no effect. not at all. In this case, the active drive must be termi- nated before the Fault condition causes damage. This 23.4.2 POLARITY CONTROL is referred to as auto-shutdown and is covered in Section23.9 “Auto-Shutdown Control”. The polarity of each CWG output can be selected independently. When the output polarity bit is set, the 23.2 Clock Source corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as The CWG module allows the following clock sources active-low. However, polarity does not affect the to be selected: override levels. Output polarity is selected with the • FOSC (system clock) GxPOLA and GxPOLB bits of the CWGxCON0 register. • HFINTOSC (16 MHz only) The clock sources are selected using the G1CS0 bit of the CWGxCON0 register (Register23-1).  2013-2015 Microchip Technology Inc. DS40001723D-page 231

D FIGURE 23-1: SIMPLIFIED CWG BLOCK DIAGRAM P S 40 I 0 C 0 1 7 1 2 3D Rev. 10-000123D 2 -p 7/10/2015 ( ag 2 L e GxASDLA 2 ) 3 F 2 00 1 GxCS 1 ‘0' 10 GxASDLA = 01 5 7 ‘1' 11 1 CWGxDBR FOSC cwg_clock / 6 2 HFINTOSC CWGxA 1 3 EN GxIS = 0 R TRISx C1OUT_async S Q GxPOLA GxOEA Reserved Input Source CWGxDBF PWM1_out PWM2_out R Q 6 PWM3_out Reserved Reserved GxOEB Reserved EN = TRISx 0 R 1 GxPOLB CWGxB 00  2 ‘0' 10 013-2 CWG1FGLxTA (SINDTS FpLinT) AutoS-Sohuurctdeown S GxsAhSuEtdown ‘1' 11 0 S Q D Q 15 M C1OGUxATS_DasSyCn1c GxASDLB 2 GxASDLB = 01 ic ro GxASE Data Bit R Q ch WRITE ip GxARSEN set dominate T ec x = CWG module number h n o lo g y In c .

PIC12(L)F1571/2 FIGURE 23-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN) cwg_clock PWM1 CWGxA Rising Edge Rising Edge Dead Band Rising Edge Dead Band Dead Band Falling Edge Dead Band Falling Edge Dead Band CWGxB 23.5 Dead-Band Control 23.7 Falling Edge Dead Band Dead-band control provides for non-overlapping output The falling edge dead band delays the turn-on of the signals to prevent shoot-through current in power CWGxB output from when the CWGxA output is turned switches. The CWG contains two 6-bit dead-band off. The falling edge dead-band time starts when the counters. One dead-band counter is used for the rising falling edge of the input source goes true. When this edge of the input source control. The other is used for happens, the CWGxA output is immediately turned off the falling edge of the input source control. and the falling edge dead-band delay time starts. When the falling edge dead-band delay time is reached, the Dead band is timed by counting CWG clock periods CWGxB output is turned on. from zero, up to the value in the rising or falling Dead- Band Counter registers. See the CWGxDBR and The CWGxDBF register sets the duration of the dead- CWGxDBF registers (Register23-4 and Register23-5, band interval on the falling edge of the input source respectively). signal. This duration is from 0 to 64 counts of deadband. 23.6 Rising Edge Dead Band Dead band is always counted off the edge on the input source signal. A count of 0 (zero), indicates that no The rising edge dead band delays the turn-on of the dead band is present. CWGxA output from when the CWGxB output is turned off. The rising edge dead-band time starts when the If the input source signal is not present for enough time rising edge of the input source signal goes true. When for the count to be completed, no output will be seen on this happens, the CWGxB output is immediately turned the respective output. off and the rising edge dead-band delay time starts. Refer to Figure23-3 and Figure23-4 for examples. When the rising edge dead-band delay time is reached, the CWGxA output is turned on. The CWGxDBR register sets the duration of the dead- band interval on the rising edge of the input source signal. This duration is from 0 to 64 counts of dead band. Dead band is always counted off the edge on the input source signal. A count of 0 (zero), indicates that no dead band is present. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output.  2013-2015 Microchip Technology Inc. DS40001723D-page 233

D FIGURE 23-3: DEAD-BAND OPERATION, CWGxDBR = 01h, CWGxDBF = 02h P S 40 I 0 C 0 1 7 1 2 3D 2 -p ( ag cwg_clock L e 2 ) 3 F 4 Input Source 1 5 CWGxA 7 1 CWGxB / 2 FIGURE 23-4: DEAD-BAND OPERATION, CWGxDBR = 03h, CWGxDBF = 04h, SOURCE SHORTER THAN DEAD BAND cwg_clock Input Source CWGxA CWGxB  2 0 Source Shorter than Dead Band 1 3 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

PIC12(L)F1571/2 23.8 Dead-Band Uncertainty 23.9 Auto-Shutdown Control When the rising and falling edges of the input source Auto-shutdown is a method to immediately override the triggers the dead-band counters, the input may be CWG output levels with specific overrides that allow for asynchronous. This will create some uncertainty in the safe shutdown of the circuit. The shutdown state can be dead-band time delay. The maximum uncertainty is either cleared automatically or held until cleared by equal to one CWG clock period. Refer to Equation23-1 software. for more detail. 23.9.1 SHUTDOWN EQUATION 23-1: DEAD-BAND The shutdown state can be entered by either of the UNCERTAINTY following two methods: • Software generated • External Input 1 TDEADBAND_UNCERTAINTY = ----------------------------- Fcwg_clock 23.9.1.1 Software Generated Shutdown Setting the GxASE bit of the CWGxCON2 register will force the CWG into the shutdown state. When auto-restart is disabled, the shutdown state will Example: persist as long as the GxASE bit is set. When auto-restart is enabled, the GxASE bit will clear automatically and resume operation on the next rising Fcwg_clock = 16 MHz edge event. See Figure23-6. 23.9.1.2 External Input Source External shutdown inputs provide the fastest way to Therefore: safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to 1 TDEADBAND_UNCERTAINTY = ----------------------------- the selected override levels without software delay. Any Fcwg_clock combination of two input sources can be selected to cause a shutdown condition. The sources are: 1 • Comparator C1 – C1OUT_async = ------------------- • CWG1FLT 16 MHz Shutdown inputs are selected in the CWGxCON2 = 62.5ns register (Register23-3). Note: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling auto-shutdown, as long as the shutdown input level persists.  2013-2015 Microchip Technology Inc. DS40001723D-page 235

PIC12(L)F1571/2 23.10 Operation During Sleep 23.11.1 PIN OVERRIDE LEVELS The CWG module operates independently from the The levels driven to the output pins, while the shutdown system clock, and will continue to run during Sleep input is true, are controlled by the GxASDLA provided that the clock and input sources selected and GxASDLB bits of the CWGxCON1 register remain active. (Register23-3). GxASDLA controls the CWG1A over- ride level and GxASDLB controls the CWG1B override The HFINTOSC remains active during Sleep, provided level. The control bit logic level corresponds to the out- that the CWG module is enabled, the input source is put logic drive level while in the shutdown state. The active and the HFINTOSC is selected as the clock polarity control does not apply to the override level. source, regardless of the system clock source selected. 23.11.2 AUTO-SHUTDOWN RESTART In other words, if the HFINTOSC is simultaneously After an auto-shutdown event has occurred, there are selected as the system clock and the CWG clock two ways to resume operation: source, when the CWG is enabled and the input source • Software controlled is active, the CPU will go idle during Sleep, but the CWG will continue to operate and the HFINTOSC will • Auto-restart remain active. The restart method is selected with the GxARSEN bit This will have a direct effect on the Sleep mode current. of the CWGxCON2 register. Waveforms of software controlled and automatic restarts are shown in 23.11 Configuring the CWG Figure23-5 and Figure23-6. The following steps illustrate how to properly configure 23.11.2.1 Software Controlled Restart the CWG to ensure a synchronous start: When the GxARSEN bit of the CWGxCON2 register 1. Ensure that the TRISx control bits correspond- is cleared, the CWG must be restarted after an ing to CWGxA and CWGxB are set so that both auto-shutdown event by software. are configured as inputs. Clearing the shutdown state requires all selected shut- 2. Clear the GxEN bit if not already cleared. down inputs to be low, otherwise, the GxASE bit will 3. Set desired dead-band times with the CWGxDBR remain set. The overrides will remain in effect until the and CWGxDBF registers. first rising edge event after the GxASE bit is cleared. 4. Set up the following controls in the CWGxCON2 The CWG will then resume operation. auto-shutdown register: 23.11.2.2 Auto-Restart • Select desired shutdown source. When the GxARSEN bit of the CWGxCON2 register is • Select both output overrides to the desired set, the CWG will restart from the auto-shutdown state levels (this is necessary even if not using automatically. auto-shutdown because start-up will be from a shutdown state). The GxASE bit will clear automatically when all shut- • Set the GxASE bit and clear the GxARSEN down sources go low. The overrides will remain in bit. effect until the first rising edge event after the GxASE bit is cleared. The CWG will then resume operation. 5. Select the desired input source using the CWGxCON1 register. 6. Configure the following controls in the CWGxCON0 register: • Select desired clock source. • Select the desired output polarities. • Set the output enables for the outputs to be used. 7. Set the GxEN bit. 8. Clear the TRISx control bits corresponding to CWGxA and CWGxB to be used to configure those pins as outputs. 9. If auto-restart is to be used, set the GxARSEN bit and the GxASE bit will be cleared automati- cally. Otherwise, clear the GxASE bit to start the CWG. DS40001723D-page 236  2013-2015 Microchip Technology Inc.

 FIGURE 23-5: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0, GxASDLA = 01, GxASDLB = 01) 2 0 1 3-2 Shutdown Event Ceases GxASE Cleared by Software 0 1 5 M CWG Input ic Source ro c h ip T Shutdown Source e c h n o lo GxASE g y In c. CWG1A Tri-State (No Pulse) CWG1B Tri-State (No Pulse) No Shutdown Shutdown Output Resumes FIGURE 23-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1, GxASDLA = 01, GxASDLB = 01) Shutdown Event Ceases GxASE Auto-Cleared by Hardware CWG Input Source P Shutdown Source I C 1 GxASE 2 ( L DS CWG1A Tri-State (No Pulse) 4 ) 0 F 0 0 17 CWG1B Tri-State (No Pulse) 1 2 5 3 D-p No Shutdown 7 ag Shutdown Output Resumes 1 e 23 /2 7

PIC12(L)F1571/2 23.12 Register Definitions: CWG Control REGISTER 23-1: CWGxCON0: CWGx CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 GxEN GxOEB GxOEA GxPOLB GxPOLA — — GxCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 GxEN: CWGx Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 GxOEB: CWGxB Output Enable bit 1 = CWGxB is available on appropriate I/O pin 0 = CWGxB is not available on appropriate I/O pin bit 5 GxOEA: CWGxA Output Enable bit 1 = CWGxA is available on appropriate I/O pin 0 = CWGxA is not available on appropriate I/O pin bit 4 GxPOLB: CWGxB Output Polarity bit 1 = Output is inverted polarity 0 = Output is normal polarity bit 3 GxPOLA: CWGxA Output Polarity bit 1 = Output is inverted polarity 0 = Output is normal polarity bit 2-1 Unimplemented: Read as ‘0’ bit 0 GxCS0: CWGx Clock Source Select bit 1 = HFINTOSC 0 = FOSC DS40001723D-page 238  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 23-2: CWGxCON1: CWGx CONTROL REGISTER 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 R/W-0/0 R/W-0/0 R/W-0/0 GxASDLB<1:0> GxASDLA<1:0> — GxIS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB bits When an Auto-Shutdown Event is Present (GxASE=1): 11 = CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit 10 = CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit 01 = CWGxB pin is tri-stated 00 = CWGxB pin is driven to its inactive state after the selected dead-band interval; GxPOLB will still control the polarity of the output bit 5-4 GxASDLA<1:0>: CWGx Shutdown State for CWGxA bits When an Auto-Shutdown Event is Present (GxASE=1): 11 = CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit 10 = CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit 01 = CWGxA pin is tri-stated 00 = CWGxA pin is driven to its inactive state after the selected dead-band interval; GxPOLA will still control the polarity of the output bit 3 Unimplemented: Read as ‘0’ bit 2-0 GxIS<2:0>: CWGx Input Source Select bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = PWM3 – PWM3_out 011 = PWM2 – PWM2_out 010 = PWM1 – PWM1_out 001 = Reserved 000 = Comparator C1 – C1OUT_async  2013-2015 Microchip Technology Inc. DS40001723D-page 239

PIC12(L)F1571/2 REGISTER 23-3: CWGxCON2: CWGx CONTROL REGISTER 2 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 U-0 GxASE GxARSEN — — — GxASDSC1 GxASDSFLT — bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets bit 7 GxASE: Auto-Shutdown Event Status bit 1 = An auto-shutdown event has occurred 0 = No auto-shutdown event has occurred bit 6 GxARSEN: Auto-Restart Enable bit 1 = Auto-restart is enabled 0 = Auto-restart is disabled bit 5-3 Unimplemented: Read as ‘0’ bit 2 GxASDSC1: CWGx Auto-Shutdown on Comparator C1 Enable bit 1 = Shutdown when Comparator C1 output (C1OUT_async) is high 0 = Comparator C1 output has no effect on shutdown bit 1 GxASDSFLT: CWGx Auto-Shutdown on FLT Enable bit 1 = Shutdown when CWG1FLT input is low 0 = CWG1FLT input has no effect on shutdown bit 0 Unimplemented: Read as ‘0’ DS40001723D-page 240  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 REGISTER 23-4: CWGxDBR: CWGx COMPLEMENTARY WAVEFORM GENERATOR RISING DEAD-BAND COUNT REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — CWGxDBR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising Counts bits 11 1111 = 63-64 counts of dead band 11 1110 = 62-63 counts of dead band • • • 00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band REGISTER 23-5: CWGxDBF: CWGx COMPLEMENTARY WAVEFORM GENERATOR FALLING DEAD-BAND COUNT REGISTER U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — CWGxDBF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling Counts bits 11 1111 = 63-64 counts of dead band 11 1110 = 62-63 counts of dead band • • • 00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band; dead-band generation is bypassed  2013-2015 Microchip Technology Inc. DS40001723D-page 241

PIC12(L)F1571/2 TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH CWG Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 114 CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA — — G1CS0 238 CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0> — — G1IS<1:0> 239 CWG1CON2 G1ASE G1ARSEN — — — G1ASDSC1 G1ASDSFLT — 240 CWG1DBF — — CWG1DBF<5:0> 241 CWG1DBR — — CWG1DBR<5:0> 241 TRISA — — TRISA<5:4> —(1) TRISA2 TRISA<1:0> 113 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the CWG. Note 1: Unimplemented, read as ‘1’. DS40001723D-page 242  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 24.0 IN-CIRCUIT SERIAL 24.3 Common Programming Interfaces PROGRAMMING™ (ICSP™) Connection to a target device is typically done through an ICSP™ header. A commonly found connector on ICSP™ programming allows customers to manufacture development tools is the RJ-11 in the 6P6C (6-pin, circuit boards with unprogrammed devices. Programming 6-connector) configuration. See Figure24-1. can be done after the assembly process, allowing the device to be programmed with the most recent firmware FIGURE 24-1: ICD RJ-11 STYLE or a custom firmware. Five pins are needed for ICSP™ programming: CONNECTOR INTERFACE • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS ICSPDAT In Program/Verify mode, the program memory, User IDs VDD 2 4 6 NC ICSPCLK and the Configuration Words are programmed through 1 3 5 Target serial communications. The ICSPDAT pin is a bidirec- tional I/O used for transferring the serial data and the VPP/MCLR VSS PC Board ICSPCLK pin is the clock input. For more information on Bottom Side ICSP™, refer to the “PIC12(L)F1501/PIC16(L)F150X Memory Programming Specification” (DS41573). Pin Description* 24.1 High-Voltage Programming Entry 1 = VPP/MCLR Mode 2 = VDD Target 3 = VSS (ground) The device is placed into High-Voltage Programming 4 = ICSPDAT Entry mode by holding the ICSPCLK and ICSPDAT pins 5 = ICSPCLK low, then raising the voltage on MCLR/VPP to VIHH. 6 = No Connect 24.2 Low-Voltage Programming Entry Another connector often found in use with the PICkit™ Mode programmers is a standard 6-pin header with 0.1inch The Low-Voltage Programming Entry mode allows the spacing. Refer to Figure24-2. PIC® MCUs (Flash) to be programmed using VDD only, without high voltage. When the LVP bit of the Configuration Words is set to ‘1’, the ICSP Low-Voltage Programming Entry mode is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. MCLR is brought to VIL. 2. A 32-bit key sequence is presented on ICSPDAT while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If Low-Voltage Programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section6.5 “MCLR” for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode.  2013-2015 Microchip Technology Inc. DS40001723D-page 243

PIC12(L)F1571/2 FIGURE 24-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Rev.10-000128A 7/30/2013 Pin1Indicator PinDescription* 1=VPP/MCLR 1 2=VDDTarget 2 3 4 3=VSS(ground) 5 6 4=ICSPDAT 5=ICSPCLK 6=Noconnect * The6-pinheader(0.100"spacing)accepts0.025"squarepins For additional interface recommendations, refer to your It is recommended that isolation devices be used to specific device programmer manual prior to PCB separate the programming pins from other circuitry. design. The type of isolation is highly dependent on the specific application and may include devices, such as resistors, diodes or even jumpers. See Figure24-3 for more information. FIGURE 24-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING Rev.10-000129A 7/30/2013 External Devicetobe Programming VDD Programmed Signals VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * ToNormalConnections * Isolationdevices(asrequired). DS40001723D-page 244  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 25.0 INSTRUCTION SET SUMMARY 25.1 Read-Modify-Write Operations Each instruction is a 14-bit word containing the opera- Any instruction that specifies a file register as part of tion code (opcode) and all required operands. The the instruction performs a Read-Modify-Write (R-M-W) opcodes are broken into three broad categories. operation. The register is read, the data is modified and the result is stored according to either the instruction or • Byte-Oriented the destination designator, ‘d’. A read operation is • Bit-Oriented performed on a register even if the instruction writes to • Literal and Control that register. The literal and control category contains the most varied instruction word format. TABLE 25-1: OPCODE FIELD DESCRIPTIONS Table25-3 lists the instructions recognized by the MPASM™ assembler. Field Description All instructions are executed within a single instruction f Register file address (0x00 to 0x7F). cycle, with the following exceptions, which may take W Working register (accumulator). two or three cycles: b Bit address within an 8-bit file register. • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two k Literal field, constant data or label. cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1). • Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0. BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for • One additional instruction cycle will be used when compatibility with all Microchip software tools. any instruction references an indirect file register d Destination select; d = 0: store result in W, and the file select register is pointing to program d = 1: store result in file register f. memory Default is d = 1. One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number (0-1). an oscillator frequency of 4 MHz, this gives a nominal mm Pre-Post Increment-Decrement mode instruction execution rate of 1 MHz. selection. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a TABLE 25-2: ABBREVIATION hexadecimal digit. DESCRIPTIONS Field Description PC Program Counter TO Time-out bit C Carry bit DC Digit Carry bit Z Zero bit PD Power-Down bit  2013-2015 Microchip Technology Inc. DS40001723D-page 245

PIC12(L)F1571/2 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 7 6 0 OPCODE k (literal) k = 7-bit immediate value MOVLB instruction only 13 5 4 0 OPCODE k (literal) k = 5-bit immediate value BRA instruction only 13 9 8 0 OPCODE k (literal) k = 9-bit immediate value FSR Offset instructions 13 7 6 5 0 OPCODE n k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 3 2 1 0 OPCODE n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS40001723D-page 246  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 25-3: ENHANCED MID-RANGE INSTRUCTION SET 14-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2 ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2 ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2 ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2 LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2 LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear W 1 00 0001 0000 00xx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 2 INCF f, d Increment f 1 00 1010 dfff ffff Z 2 IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 2 MOVWF f Move W to f 1 00 0000 1fff ffff 2 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2 SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2 SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2 SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2 XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2 BYTE-ORIENTED SKIP OPERATIONS DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 01 00bb bfff ffff 2 BSF f, b Bit Set f 1 01 01bb bfff ffff 2 BIT-ORIENTED SKIP OPERATIONS BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2 LITERAL OPERATIONS ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z MOVLB k Move literal to BSR 1 00 0000 001k kkkk MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk MOVLW k Move literal to W 1 11 0000 kkkk kkkk SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See the table in the MOVIW and MOVWI instruction descriptions.  2013-2015 Microchip Technology Inc. DS40001723D-page 247

PIC12(L)F1571/2 TABLE 25-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED) Mnemonic, 14-Bit Opcode Status Description Cycles Notes Operands MSb LSb Affected CONTROL OPERATIONS BRA k Relative Branch 2 11 001k kkkk kkkk BRW – Relative Branch with W 2 00 0000 0000 1011 CALL k Call Subroutine 2 10 0kkk kkkk kkkk CALLW – Call Subroutine with W 2 00 0000 0000 1010 GOTO k Go to address 2 10 1kkk kkkk kkkk RETFIE k Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 0100 kkkk kkkk RETURN – Return from Subroutine 2 00 0000 0000 1000 INHERENT OPERATIONS CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD NOP – No Operation 1 00 0000 0000 0000 OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010 RESET – Software device Reset 1 00 0000 0000 0001 SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD TRIS f Load TRIS register with W 1 00 0000 0110 0fff C COMPILER OPTIMIZED ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3 modifier, mm kkkk k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk 1nmm Z 2 MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 kkkk 2, 3 modifier, mm k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk 2 Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 3: See the table in the MOVIW and MOVWI instruction descriptions. DS40001723D-page 248  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 25.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k Operands: -32  k  31 Operands: 0  k  255 n  [ 0, 1] Operation: (W) .AND. (k)  (W) Operation: FSR(n) + k  FSR(n) Status Affected: Z Status Affected: None Description: The contents of W register are Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The the contents of the FSRnH:FSRnL result is placed in the W register. register pair. FSRn is limited to the range 0000h - FFFFh. Moving beyond these bounds will cause the FSR to wraparound. ADDLW Add literal and W ANDWF AND W with f Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d Operands: 0  k  255 Operands: 0  f  127 d 0,1 Operation: (W) + k  (W) Operation: (W) .AND. (f)  (destination) Status Affected: C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWF Add W and f ASRF Arithmetic Right Shift Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d} Operands: 0  f  127 Operands: 0  f  127 d 0,1 d [0,1] Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7> (f<7:1>)  dest<6:0>, Status Affected: C, DC, Z (f<0>)  C, Description: Add the contents of the W register Status Affected: C, Z with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted result is stored back in register ‘f’. one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC ADD W and CARRY bit to f register f C Syntax: [ label ] ADDWFC f {,d} Operands: 0  f  127 d [0,1] Operation: (W) + (f) + (C)  dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data mem- ory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.  2013-2015 Microchip Technology Inc. DS40001723D-page 249

PIC12(L)F1571/2 BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b Operands: 0  f  127 Operands: 0  f  127 0  b  7 0  b  7 Operation: 0  (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b [ label ] BRA $+k Operands: 0  f  127 Operands: -256label-PC+1255 0  b < 7 -256  k  255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k  PC Status Affected: None Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next Description: Add the signed 9-bit literal ‘k’ to the instruction is executed. PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next mented to fetch the next instruction, instruction is discarded and a NOP is the new address will be PC+1+k. executed instead, making this a This instruction is a 2-cycle instruc- 2-cycle instruction. tion. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W)  PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incre- mented to fetch the next instruction, the new address will be PC+1+(W). This instruction is a 2-cycle instruc- tion. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0  f  127 0  b  7 Operation: 1  (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. DS40001723D-page 250  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h  WDT k  PC<10:0>, 0  WDT prescaler, (PCLATH<6:3>)  PC<14:11> 1  TO Status Affected: None 1  PD Description: Call Subroutine. First, return address Status Affected: TO, PD (PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch- The 11-bit immediate address is dog Timer. It also resets the prescaler loaded into PC bits <10:0>. The upper of the WDT. bits of the PC are loaded from Status bits TO and PD are set. PCLATH. CALL is a 2-cycle instruc- tion. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d Operands: None Operands: 0  f  127 d  [0,1] Operation: (PC) +1  TOS, (W)  PC<7:0>, Operation: (f)  (destination) (PCLATH<6:0>) PC<14:8> Status Affected: Z Description: The contents of register ‘f’ are com- Status Affected: None plemented. If ‘d’ is ‘0’, the result is Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is return address (PC + 1) is pushed stored back in register ‘f’. onto the return stack. Then, the con- tents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f DECF Decrement f Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] Operation: 00h  (f) 1  Z Operation: (f) - 1  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the and the Z bit is set. result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h  (W) 1  Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set.  2013-2015 Microchip Technology Inc. DS40001723D-page 251

PIC12(L)F1571/2 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) - 1  (destination); Operation: (f) + 1  (destination), skip if result = 0 skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre- mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. is placed back in register ‘f’. If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is NOP is executed instead, making it a executed instead, making it a 2-cycle 2-cycle instruction. instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  2047 Operands: 0  k  255 Operation: k  PC<10:0> Operation: (W) .OR. k  (W) PCLATH<6:3>  PC<14:11> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The 11-bit immediate value is loaded into result is placed in the W register. PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d Operands: 0  f  127 Operands: 0  f  127 d  [0,1] d  [0,1] Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis- mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is is placed back in register ‘f’. placed back in register ‘f’. DS40001723D-page 252  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 LSLF Logical Left Shift MOVF Move f Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d Operands: 0  f  127 Operands: 0  f  127 d [0,1] d  [0,1] Operation: (f<7>)  C Operation: (f)  (dest) (f<6:0>)  dest<7:1> Status Affected: Z 0  dest<0> Description: The contents of register f is moved to Status Affected: C, Z a destination dependent upon the Description: The contents of register ‘f’ are shifted status of d. If d = 0, one bit to the left through the Carry flag. destination is W register. If d = 1, the A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, destination is file register f itself. d = 1 the result is placed in W. If ‘d’ is ‘1’, the is useful to test a file register since result is stored back in register ‘f’. status flag Z is affected. Words: 1 C register f 0 Cycles: 1 Example: MOVF FSR, 0 After Instruction LSRF Logical Right Shift W = value in FSR register Syntax: [ label ] LSRF f {,d} Z = 1 Operands: 0  f  127 d [0,1] Operation: 0  dest<7> (f<7:1>)  dest<6:0>, (f<0>)  C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 0 register f C  2013-2015 Microchip Technology Inc. DS40001723D-page 253

PIC12(L)F1571/2 MOVIW Move INDFn to W MOVLP Move literal to PCLATH Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k [ label ] MOVIW --FSRn Operands: 0  k  127 [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-- Operation: k  PCLATH [ label ] MOVIW k[FSRn] Status Affected: None Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the mm  [00,01, 10, 11] PCLATH register. -32  k  31 Operation: INDFn  W Effective address is determined by MOVLW Move literal to W • FSR + 1 (preincrement) Syntax: [ label ] MOVLW k • FSR - 1 (predecrement) • FSR + k (relative offset) Operands: 0  k  255 After the Move, the FSR value will be Operation: k  (W) either: • FSR + 1 (all increments) Status Affected: None • FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg- • Unchanged ister. The “don’t cares” will assemble as Status Affected: Z ‘0’s. Words: 1 Mode Syntax mm Cycles: 1 Preincrement ++FSRn 00 Example: MOVLW 0x5A Predecrement --FSRn 01 After Instruction W = 0x5A Postincrement FSRn++ 10 Postdecrement FSRn-- 11 MOVWF Move W to f Syntax: [ label ] MOVWF f Description: This instruction is used to move data between W and one of the indirect Operands: 0  f  127 registers (INDFn). Before/after this Operation: (W)  (f) move, the pointer (FSRn) is updated by Status Affected: None pre/post incrementing/decrementing it. Description: Move data from W register to register Note: The INDFn registers are not ‘f’. physical registers. Any instruction that Words: 1 accesses an INDFn register actually accesses the register at the address Cycles: 1 specified by the FSRn. Example: MOVWF OPTION_REG Before Instruction FSRn is limited to the range 0000h - OPTION_REG = 0xFF FFFFh. Incrementing/decrementing it W = 0x4F beyond these bounds will cause it to After Instruction wraparound. OPTION_REG = 0x4F W = 0x4F MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0  k  31 Operation: k  BSR Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR). DS40001723D-page 254  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 MOVWI Move W to INDFn NOP No Operation Syntax: [ label ] NOP Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn Operands: None [ label ] MOVWI FSRn++ Operation: No operation [ label ] MOVWI FSRn-- [ label ] MOVWI k[FSRn] Status Affected: None Operands: n  [0,1] Description: No operation. mm  [00,01, 10, 11] Words: 1 -32  k  31 Cycles: 1 Operation: W  INDFn Example: NOP Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be Load OPTION_REG Register either: OPTION with W • FSR + 1 (all increments) • FSR - 1 (all decrements) Syntax: [ label ] OPTION Unchanged Operands: None Status Affected: None Operation: (W)  OPTION_REG Status Affected: None Mode Syntax mm Description: Move data from W register to Preincrement ++FSRn 00 OPTION_REG register. Predecrement --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 RESET Software Reset Syntax: [ label ] RESET Description: This instruction is used to move data between W and one of the indirect Operands: None registers (INDFn). Before/after this Operation: Execute a device Reset. Resets the move, the pointer (FSRn) is updated by nRI flag of the PCON register. pre/post incrementing/decrementing it. Status Affected: None Note: The INDFn registers are not Description: This instruction provides a way to physical registers. Any instruction that execute a hardware Reset by soft- accesses an INDFn register actually ware. accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h - FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wraparound. The increment/decrement operation on FSRn WILL NOT affect any Status bits.  2013-2015 Microchip Technology Inc. DS40001723D-page 255

PIC12(L)F1571/2 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] RETFIE Syntax: [ label ] RETURN Operands: None Operands: None Operation: TOS  PC, Operation: TOS  PC 1  GIE Status Affected: None Status Affected: None Description: Return from subroutine. The stack is Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS) and Top-of-Stack (TOS) is loaded in is loaded into the Program Counter. the PC. Interrupts are enabled by This is a 2-cycle instruction. setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W RLF Rotate Left f through Carry Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d Operands: 0  k  255 Operands: 0  f  127 d  [0,1] Operation: k  (W); TOS  PC Operation: See description below Status Affected: None Status Affected: C Description: The W register is loaded with the 8-bit Description: The contents of register ‘f’ are rotated literal ‘k’. The Program Counter is one bit to the left through the Carry loaded from the top of the stack (the flag. If ‘d’ is ‘0’, the result is placed in return address). This is a 2-cycle the W register. If ‘d’ is ‘1’, the result is instruction. stored back in register ‘f’. Words: 1 C Register f Cycles: 2 Words: 1 Example: CALL TABLE;W contains table ;offset value Cycles: 1 • ;W now has table value Example: RLF REG1,0 TABLE • Before Instruction • REG1 = 1110 0110 ADDWF PC ;W = offset C = 0 RETLW k1 ;Begin table After Instruction RETLW k2 ; REG1 = 1110 0110 • W = 1100 1100 • C = 1 • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 DS40001723D-page 256  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 RRF Rotate Right f through Carry SUBLW Subtract W from literal Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: The W register is subtracted (2’s com- Description: The contents of register ‘f’ are rotated plement method) from the 8-bit literal one bit to the right through the Carry ‘k’. The result is placed in the W regis- flag. If ‘d’ is ‘0’, the result is placed in ter. the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. C = 0 W  k C Register f C = 1 W  k DC = 0 W<3:0>  k<3:0> DC = 1 W<3:0>  k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d Operands: None Operands: 0 f 127 d  [0,1] Operation: 00h  WDT, 0  WDT prescaler, Operation: (f) - (W) destination) 1  TO, Status Affected: C, DC, Z 0  PD Description: Subtract (2’s complement method) W Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is result is stored in the W cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored set. Watchdog Timer and its pres- back in register ‘f. caler are cleared. The processor is put into Sleep mode C = 0 W  f with the oscillator stopped. C = 1 W  f DC = 0 W<3:0>  f<3:0> DC = 1 W<3:0>  f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB f {,d} Operands: 0  f  127 d  [0,1] Operation: (f) – (W) – (B) dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s comple- ment method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2013-2015 Microchip Technology Inc. DS40001723D-page 257

PIC12(L)F1571/2 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k Operands: 0  f  127 Operands: 0 k 255 d  [0,1] Operation: (W) .XOR. k W) Operation: (f<3:0>)  (destination<7:4>), Status Affected: Z (f<7:4>)  (destination<3:0>) Description: The contents of the W register are Status Affected: None XOR’ed with the 8-bit Description: The upper and lower nibbles of regis- literal ‘k’. The result is placed in the ter ‘f’ are exchanged. If ‘d’ is ‘0’, the W register. result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. TRIS Load TRIS Register with W XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d Operands: 5  f  7 Operands: 0  f  127 d  [0,1] Operation: (W)  TRIS register ‘f’ Operation: (W) .XOR. (f) destination) Status Affected: None Status Affected: Z Description: Move data from W register to TRIS register. Description: Exclusive OR the contents of the W When ‘f’ = 5, TRISA is loaded. register with register ‘f’. If ‘d’ is ‘0’, the When ‘f’ = 6, TRISB is loaded. result is stored in the W register. If ‘d’ When ‘f’ = 7, TRISC is loaded. is ‘1’, the result is stored back in regis- ter ‘f’. DS40001723D-page 258  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 26.0 ELECTRICAL SPECIFICATIONS 26.1 Absolute Maximum Ratings(†) Ambient temperature under bias............................................................................................................ -40°C to +125°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on pins with respect to VSS: on VDD pin PIC12F1571/2 ................................................................................................................. -0.3V to +6.5V PIC12LF1571/2 ............................................................................................................... -0.3V to +4.0V on MCLR pin ................................................................................................................................. -0.3V to +9.0V on all other pins .................................................................................................................. -0.3V to (VDD + 0.3V) Maximum current: on VSS pin(1) -40°C  TA  +85°C .................................................................................................................... 250 mA +85°C  TA  +125°C ................................................................................................................... 85 mA on VDD pin(1) -40°C  TA  +85°C .................................................................................................................... 250 mA +85°C  TA  +125°C ................................................................................................................... 85 mA Sunk by any standard I/O pin ..................................................................................................................... 50 mA Sourced by any standard I/O pin ................................................................................................................ 50 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ......................................................................................................... 20 mA Total power dissipation(2).....................................................................................................................................800 mW Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table26-6: “Thermal Characteristics” to calculate device specifications. 2: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.  2013-2015 Microchip Technology Inc. DS40001723D-page 259

PIC12(L)F1571/2 26.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: VDDMIN VDD VDDMAX Operating Temperature: TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC12LF1571/2 VDDMIN (FOSC  16 MHz)............................................................................................................... +1.8V VDDMIN (FOSC  32 MHz)............................................................................................................... +2.5V VDDMAX.......................................................................................................................................... +3.6V PIC12F1571/2 VDDMIN (FOSC  16 MHz)............................................................................................................... +2.3V VDDMIN (FOSC  32 MHz)............................................................................................................... +2.5V VDDMAX.......................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN............................................................................................................................................ -40°C TA_MAX.......................................................................................................................................... +85°C Extended Temperature TA_MIN............................................................................................................................................ -40°C TA_MAX........................................................................................................................................ +125°C Note 1: See Parameter D001, DS Characteristics: Supply Voltage. DS40001723D-page 260  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 26-1: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC12F1571/2 ONLY Rev. 10-000130B 9/19/2013 5.5 V) ( D D V 2.5 2.3 0 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table26-7 for each Oscillator mode’s supported frequencies. FIGURE 26-2: VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC12LF1571/2 ONLY Rev. 10-000131B 9/19/2013 3.6 V) ( D D V 2.5 1.8 0 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table26-7 for each Oscillator mode’s supported frequencies.  2013-2015 Microchip Technology Inc. DS40001723D-page 261

PIC12(L)F1571/2 26.3 DC Characteristics TABLE 26-1: SUPPLY VOLTAGE PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated) PIC12F1571/2 Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. D001 VDD Supply Voltage VDDMIN VDDMAX 1.8 — 3.6 V FOSC  16MHz 2.5 — 3.6 V FOSC  32MHz (Note 3) D001 2.3 — 5.5 V FOSC  16MHz 2.5 — 5.5 V FOSC  32MHz (Note 3) D002* VDR RAM Data Retention Voltage(1) 1.5 — — V Device in Sleep mode D002* 1.7 — — V Device in Sleep mode D002A* VPOR Power-on Reset Release Voltage(2) — 1.6 — V D002A* — 1.6 — V D002B* VPORR* Power-on Reset Rearm Voltage(2) — 0.8 — V D002B* — 1.5 — V D003 VFVR Fixed Voltage Reference Voltage — 1.024 — V -40°C  TA  +85°C D003A VADFVR FVR Gain Voltage Accuracy for 1x VFVR, ADFVR = 01, VDD 2.5V -4 — +4 % ADC 2x VFVR, ADFVR = 10, VDD 2.5V 4x VFVR, ADFVR = 11, VDD 4.75V D003B VCDAFVR FVR Gain Voltage Accuracy for 1x VFVR, CDAFVR = 01, VDD 2.5V -4 — +4 % Comparator 2x VFVR, CDAFVR = 10, VDD 2.5V 4x VFVR, CDAFVR = 11, VDD 4.75V D004* SVDD VDD Rise Rate(2) 0.05 — — V/ms Ensures that the Power-on Reset signal is released properly * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: See Figure26-3, POR and POR Rearm with Slow Rising VDD. 3: PLL required for 32MHz operation. DS40001723D-page 262  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 26-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR Rearm VSS TVLOW(3) TPOR(2) Note 1: When NPOR is low, the device is held in Reset. 2: TPOR: 1s typical. 3: TVLOW: 2.7s typical.  2013-2015 Microchip Technology Inc. DS40001723D-page 263

PIC12(L)F1571/2 TABLE 26-2: SUPPLY CURRENT (IDD)(1,2) PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated) PIC12F1571/2 Conditions Param. Device Min. Typ† Max. Units No. Characteristics VDD Note D013 — 35 44 A 1.8 FOSC = 1MHz, External Clock (ECM), — 60 69 A 3.0 Medium Power mode D013 — 68 93 A 2.3 FOSC = 1MHz, — 91 120 A 3.0 External Clock (ECM), Medium Power mode — 131 160 A 5.0 D014 — 116 132 A 1.8 FOSC = 4MHz, External Clock (ECM), — 203 233 A 3.0 Medium Power mode D014 — 174 221 A 2.3 FOSC = 4MHz, — 234 286 A 3.0 External Clock (ECM), Medium Power mode — 299 374 A 5.0 D015 — 5.5 11 A 1.8 FOSC = 31kHz, — 7.3 12 A 3.0 LFINTOSC, -40°C  TA  +85°C D015 — 13 21 A 2.3 FOSC = 31kHz, — 15 24 A 3.0 LFINTOSC, -40°C  TA  +85°C — 17 25 A 5.0 D016 — 111 151 A 1.8 FOSC = 500 kHz, — 133 176 A 3.0 MFINTOSC D016 — 144 209 A 2.3 FOSC = 500 kHz, — 162 237 A 3.0 MFINTOSC — 216 288 A 5.0 D017* — 0.5 0.6 mA 1.8 FOSC = 8MHz, — 0.7 0.9 mA 3.0 HFINTOSC D017* — 0.6 0.8 mA 2.3 FOSC = 8MHz, — 0.8 0.9 mA 3.0 HFINTOSC — 0.9 1.0 mA 5.0 D018 — 0.7 0.8 mA 1.8 FOSC = 16MHz, — 1.1 1.2 mA 3.0 HFINTOSC D018 — 0.9 1.1 mA 2.3 FOSC = 16MHz, HFINTOSC — 1.1 1.3 mA 3.0 — 1.3 1.5 mA 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: PLL required for 32MHz operation. DS40001723D-page 264  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 26-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated) PIC12F1571/2 Conditions Param. Device Min. Typ† Max. Units No. Characteristics VDD Note D018A* — 2 2.4 mA 3.0 FOSC = 32 MHz, HFINTOSC (Note 3) D018A* — 2.1 2.5 mA 3.0 FOSC = 32 MHz, — 2.2 2.6 mA 5.0 HFINTOSC (Note 3) D019A — 1.7 1.9 mA 3.0 FOSC = 32 MHz, External Clock (ECH), High-Power mode (Note 3) D019A — 1.8 2 mA 3.0 FOSC = 32 MHz, — 1.9 2.3 mA 5.0 External Clock (ECH), High-Power mode (Note 3) D019B — 2.2 5.9 A 1.8 FOSC = 32 kHz, External Clock (ECL), — 4.3 8.3 A 3.0 Low-Power mode D019B — 12 20 A 2.3 FOSC = 32 kHz, — 15 25 A 3.0 External Clock (ECL), Low-Power mode — 17 26 A 5.0 D019C — 18 25 A 1.8 FOSC = 500 kHz, External Clock (ECL), — 30 38 A 3.0 Low-Power mode D019C — 29 40 A 2.3 FOSC = 500 kHz, — 37 51 A 3.0 External Clock (ECL), Low-Power mode — 42 53 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: PLL required for 32MHz operation.  2013-2015 Microchip Technology Inc. DS40001723D-page 265

PIC12(L)F1571/2 TABLE 26-3: POWER-DOWN CURRENTS (IPD)(1,2) Operating Conditions (unless otherwise stated) PIC12LF1571/2 Low-Power Sleep Mode PIC12F1571/2 Low-Power Sleep Mode, VREGPM = 1 Conditions Param. Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note D022 Base IPD — 0.020 0.6 2.6 A 1.8 WDT, BOR and FVR disabled, — 0.025 0.8 2.9 A 3.0 all peripherals inactive, VREGPM = 1 D022 Base IPD — 0.2 0.9 2.8 A 2.3 WDT, BOR and FVR disabled, — 0.3 3.0 3.8 A 3.0 all peripherals inactive, Low-Power Sleep mode, — 0.4 3.6 4.5 A 5.0 VREGPM = 1 D022A Base IPD — 9 14 15 A 2.3 WDT, BOR and FVR disabled, — 11 19 21 A 3.0 all peripherals inactive, Normal Power Sleep mode, — 12 21 22 A 5.0 VREGPM = 0 D023 — 0.3 0.8 2.9 A 1.8 WDT Current — 0.5 1.1 3.5 A 3.0 D023 — 0.5 1.7 4.1 A 2.3 WDT Current — 0.6 1.9 4.4 A 3.0 — 0.7 2.1 4.7 A 5.0 D023A — 13 18 20 A 1.8 FVR Current — 22 28 29 A 3.0 D023A — 16 24 25 A 2.3 FVR Current — 19 30 31 A 3.0 — 20 33 35 A 5.0 D024 — 6.5 9 11 A 3.0 BOR Current D024 — 7.0 10 11 A 3.0 BOR Current — 8.0 12 13 A 5.0 D24A — 0.2 2 4 A 3.0 LPBOR Current D24A — 0.4 2 4 A 3.0 LPBOR Current — 0.5 3 5 A 5.0 D026 — 0.03 0.7 2.7 A 1.8 ADC Current (Note 3), — 0.04 0.8 3 A 3.0 No conversion in progress D026 — 0.2 1.3 3.8 A 2.3 ADC Current (Note 3), — 0.3 1.4 3.9 A 3.0 No conversion in progress — 0.4 1.5 4 A 5.0 D026A* — 250 — — A 1.8 ADC Current (Note 3), — 250 — — A 3.0 Conversion in progress D026A* — 280 — — A 2.3 ADC Current (Note 3), Conversion in progress — 280 — — A 3.0 — 280 — — A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. 3: ADC clock source is FRC. DS40001723D-page 266  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 26-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) Operating Conditions (unless otherwise stated) PIC12LF1571/2 Low-Power Sleep Mode PIC12F1571/2 Low-Power Sleep Mode, VREGPM = 1 Conditions Param. Max. Max. Device Characteristics Min. Typ† Units No. +85°C +125°C VDD Note D027 — 4 7 9 A 1.8 Comparator, — 4.2 8 10 A 3.0 CxSP = 0 D027 — 13 20 21 A 2.3 Comparator, — 14 23 25 A 3.0 CxSP = 0 — 16 24 26 A 5.0 D028A — 20 35 36 A 1.8 Comparator, — 21 36 38 A 3.0 Normal Power, CxSP = 1 (Note 1) D028A — 28 47 48 A 2.3 Comparator, — 29 51 52 A 3.0 Normal Power, CxSP = 1, VREGPM = 1 (Note 1) — 31 52 53 A 5.0 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. 3: ADC clock source is FRC.  2013-2015 Microchip Technology Inc. DS40001723D-page 267

PIC12(L)F1571/2 TABLE 26-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. VIL Input Low Voltage I/O Ports: D030 with TTL Buffer — — 0.8 V 4.5V  VDD  5.5V D030A — — 0.15VDD V 1.8V  VDD  4.5V D031 with Schmitt Trigger Buffer — — 0.2VDD V 2.0V  VDD  5.5V with I2C Levels — — 0.3VDD V with SMbus Levels — — 0.8 V 2.7V  VDD  5.5V D032 MCLR — — 0.2VDD V VIH Input High Voltage I/O Ports: D040 with TTL Buffer 2.0 — — V 4.5V  VDD 5.5V D040A 0.25VDD + 0.8 — — V 1.8V  VDD  4.5V D041 with Schmitt Trigger Buffer 0.8VDD — — V 2.0V  VDD  5.5V with I2C Levels 0.7VDD — — V with SMbus Levels 2.1 — — V 2.7V  VDD  5.5V D042 MCLR 0.8VDD — — V IIL Input Leakage Current(1) D060 I/O Ports — ± 5 ± 125 nA VSS  VPIN  VDD, Pin at high-impedance, +85°C — ± 5 ± 1000 nA VSS  VPIN  VDD, Pin at high-impedance, +125°C D061 MCLR(2) — ± 50 ± 200 nA VSS  VPIN  VDD, Pin at high-impedance, +85°C IPUR Weak Pull-up Current D070* 25 100 200 A VDD = 3.3V, VPIN = VSS 25 140 300 A VDD = 5.0V, VPIN = VSS VOL Output Low Voltage D080 I/O Ports — — 0.6 V IOL = 8 mA, VDD = 5V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V VOH Output High Voltage D090 I/O Ports VDD – 0.7 — — V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V Capacitive Loading Specifications on Output Pins D101A* CIO All I/O Pins — — 50 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. DS40001723D-page 268  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 26-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP Pin 8.0 — 9.0 V (Note 2) D111 IDDP Supply Current during — — 10 mA Programming D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V D114 IPPPGM Current on MCLR/VPP during — 1.0 — mA Erase/Write D115 IDDPGM Current on VDD during — 5.0 — mA Erase/Write Program Flash Memory D121 EP Cell Endurance 10K — — E/W -40C  TA  +85C (Note 1) D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V D123 TIW Self-Timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D125 EHEFC High-Endurance Flash Cell 100K — — E/W 0C  TA  +60°C, lower byte last 128 addresses † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and block erase. 2: Required only if single-supply programming is disabled.  2013-2015 Microchip Technology Inc. DS40001723D-page 269

PIC12(L)F1571/2 TABLE 26-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to Ambient 56.7 C/W 8-pin DFN 3x3 mm package 89.3 C/W 8-pin PDIP package 149.5 C/W 8-pin SOIC package 39.4 C/W 8-pin UDFN 3x3 mm package TH02 JC Thermal Resistance Junction to Case 9.0 C/W 8-pin DFN 3x3 mm package 43.1 C/W 8-pin PDIP package 39.9 C/W 8-pin SOIC package 40.3 C/W 8-pin UDFN 3x3 mm package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD – VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ – TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature; TJ = Junction Temperature. DS40001723D-page 270  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 26.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc CLKIN ck CLKOUT rd RD cs CS rw RD or WR di SDIx sc SCKx do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance FIGURE 26-4: LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins  2013-2015 Microchip Technology Inc. DS40001723D-page 271

PIC12(L)F1571/2 FIGURE 26-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS02 OS04 OS04 OS03 CLKOUT (CLKOUT Mode) Note1: See Table26-10. TABLE 26-7: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz External Clock (ECL) DC — 4 MHz External Clock (ECM) DC — 20 MHz External Clock (ECH) OS02 TOSC External CLKIN Period(1) 50 —  ns External Clock (EC) OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. All devices are tested to operate at “min” values with an external clock applied to the CLKIN pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS40001723D-page 272  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 26-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. Freq. Sym. Characteristic Min. Typ† Max. Units Conditions No. Tolerance OS08 HFOSC Internal Calibrated HFINTOSC ±2% — 16.0 — MHz VDD = 3.0V, TA = 25°C Frequency(1) (Note 2) OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz OS10* TWARM HFINTOSC — — 5 15 s Wake-up from Sleep Start-up Time LFINTOSC — — 0.5 — ms Wake-up from Sleep Start-up Time * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 2: See Figure26-6: “HFINTOSC Frequency Accuracy Over Device VDD and Temperature. FIGURE 26-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE +125 ± 5% +85 ± 3% C) ° +60 ( e r u t a r e p +25 ± 2% m e T 0 ± 5% -40 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) TABLE 26-9: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) Param Sym. Characteristic Min. Typ† Max. Units Conditions No. F10 FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % * These parameters are characterized but not tested. † Data in “Typ” column is at 3V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested.  2013-2015 Microchip Technology Inc. DS40001723D-page 273

PIC12(L)F1571/2 FIGURE 26-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS11 OS12 OS20 CLKOUT OS21 OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS15 OS14 I/O pin Old Value New Value (Output) OS18, OS19 TABLE 26-10: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. OS11 TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V  VDD 5.0V OS12 TosH2ckH FOSC to CLKOUT(1) — — 72 ns 3.3V  VDD 5.0V OS13 TckL2ioV CLKOUT to Port Out Valid(1) — — 20 ns OS14 TioV2ckH Port Input Valid Before CLKOUT(1) TOSC + 200 ns — — ns OS15 TosH2ioV Fosc (Q1 cycle) to Port Out Valid — 50 70* ns 3.3V  VDD 5.0V OS16 TosH2ioI Fosc (Q2 cycle) to Port Input Invalid 50 — — ns 3.3V  VDD 5.0V (I/O in setup time) OS17 TioV2osH Port Input Valid to Fosc(Q2 cycle) 20 — — ns (I/O in setup time) OS18* TioR Port Output Rise Time — 40 72 ns VDD = 1.8V, — 15 32 3.3V  VDD 5.0V OS19* TioF Port Output Fall Time — 28 55 ns VDD = 1.8V, — 15 30 3.3V  VDD 5.0V OS20* Tinp INT Pin Input High or Low Time 25 — — ns OS21* Tioc Interrupt-On-Change New Input Level Time 25 — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25C unless otherwise stated. Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC. DS40001723D-page 274  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O Pins Note 1: Asserted low.  2013-2015 Microchip Technology Inc. DS40001723D-page 275

PIC12(L)F1571/2 TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2 — — s 31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V, Time-out Period 1:512 prescaler used 32 TOST Oscillator Start-up Timer Period(1) — 1024 — TOSC 33* TPWRT Power-up Timer Period 40 65 140 ms PWRTE=0 34* TIOZ I/O High-Impedance from MCLR Low — — 2.0 s or Watchdog Timer Reset 35 VBOR Brown-out Reset Voltage(2) 2.55 2.70 2.85 V BORV = 0 2.35 2.45 2.58 V BORV = 1 (PIC12F1571/2) 1.80 1.90 2.05 V BORV = 1 (PIC12LF1571/2) 36* VHYST Brown-out Reset Hysteresis 0 25 60 mV -40°C  TA  +85°C 37* TBORDC Brown-out Reset DC Response Time 1 16 35 s VDD  VBOR 38 VLPBOR Low-Power Brown-out Reset Voltage 1.8 2.1 2.5 V LPBOR = 1 * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. FIGURE 26-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset 33 (due to BOR) DS40001723D-page 276  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 26-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 47 49 TMR0 or TMR1 TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: — — ns N = Prescale value 20 or TCY + 40 N 45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns Time Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Synchronous Greater of: — — ns N = Prescale value Period 30 or TCY + 40 N Asynchronous 60 — — ns 49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync Increment mode * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2013-2015 Microchip Technology Inc. DS40001723D-page 277

PIC12(L)F1571/2 TABLE 26-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = +25°C Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — ±1 ±1.7 LSb VREF = 3.0V AD03 EDL Differential Error — ±1 ±1 LSb No missing codes, VREF = 3.0V AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V AD05 EGN Gain Error — ±1 ±2.0 LSb VREF = 3.0V AD06 VREF Reference Voltage 1.8 — VDD V VREF = (VRPOS – VRNEG) (Note 4) AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01 F capacitor is Analog Voltage Source present on input pin. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total absolute error includes integral, differential, offset and gain errors. 2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. 3: See Section27.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. 4: ADC VREF is selected by the ADPREF<0> bit. DS40001723D-page 278  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 26-11: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO 1 TCY AD133 AD131 Q4 AD130 ADC_clk ADC Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample FIGURE 26-12: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk ADC Data 9 8 7 6 3 2 1 0 ADRES OLD_DATA NEW_DATA ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts; this allows the SLEEP instruction to be executed.  2013-2015 Microchip Technology Inc. DS40001723D-page 279

PIC12(L)F1571/2 TABLE 26-14: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. Characteristic Min. Typ† Max. Units Conditions No. AD130* TAD ADC Clock Period (TADC) 1.0 — 6.0 s FOSC-based ADC Internal FRC Oscillator Period (TFRC) 1.0 2.0 6.0 s ADCS<2:0> = x11 (ADC FRC mode) AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to conversion (not including Acquisition Time)(1) complete AD132* TACQ Acquisition Time — 5.0 — s AD133* THCD Holding Capacitor Disconnect Time — 1/2 TAD — FOSC-based, — 1/2 TAD + 1TCY — ADCS<2:0> = x11 (ADC FRC mode) * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. DS40001723D-page 280  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 26-15: COMPARATOR SPECIFICATIONS(1) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = +25°C Param. Sym. Characteristics Min. Typ. Max. Units Comments No. CM01 VIOFF Input Offset Voltage — ±7.5 ±60 mV CxSP = 1, VICM = VDD/2 CM02 VICM Input Common-Mode Voltage 0 — VDD V CM03 CMRR Common-Mode Rejection Ration — 50 — dB CM04A TRESP(2) Response Time Rising Edge — 400 800 ns CxSP = 1 CM04B Response Time Falling Edge — 200 400 ns CxSP = 1 CM04C Response Time Rising Edge — 1200 — ns CxSP = 0 CM04D Response Time Falling Edge — 550 — ns CxSP = 0 CM05* TMC2OV Comparator Mode Change to — — 10 s Output Valid CM06 CHYSTER Comparator Hysteresis — 25 — mV CxHYS = 1, CxSP = 1 * These parameters are characterized but not tested. Note 1: See Section27.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. 2: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 26-16: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS(1) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = +25°C Param. Sym. Characteristics Min. Typ. Max. Units Comments No. DAC01* CLSB Step Size — VDD/32 — V DAC02* CACC Absolute Accuracy — —  1/2 LSb DAC03* CR Unit Resistor Value (R) — 5K —  DAC04* CST Settling Time(2) — — 10 s * These parameters are characterized but not tested. Note 1: See Section27.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. 2: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.  2013-2015 Microchip Technology Inc. DS40001723D-page 281

PIC12(L)F1571/2 FIGURE 26-13: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US120 US122 Note: Refer to Figure26-4 for load conditions. TABLE 26-17: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions No. US120 TCKH2DTV SYNC XMIT (Master and Slave) — 80 ns 3.0V  VDD  5.5V Clock High to Data-Out Valid — 100 ns 1.8V  VDD  5.5V US121 TCKRF Clock Out Rise Time and Fall Time — 45 ns 3.0V  VDD  5.5V (Master mode) — 50 ns 1.8V  VDD  5.5V US122 TDTRF Data-Out Rise Time and Fall Time — 45 ns 3.0V  VDD  5.5V — 50 ns 1.8V  VDD  5.5V FIGURE 26-14: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure26-4 for load conditions. TABLE 26-18: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Symbol Characteristic Min. Max. Units Conditions No. US125 TDTV2CKL SYNC RCV (Master and Slave) Data-Hold before CK  (DT hold time) 10 — ns US126 TCKL2DTL Data-Hold after CK  (DT hold time) 15 — ns DS40001723D-page 282  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 27.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at +25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean+3) or (mean–3) respectively, where  is a standard deviation over each temperature range.  2013-2015 Microchip Technology Inc. DS40001723D-page 283

PIC12(L)F1571/2 FIGURE 27-1: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC12LF1571/2 ONLY 6.0 5.5 Max. Max: 85°C + 3(cid:305) 5.0 Typical: 25°C 4.5 Typical 4.0 A) µ 3.5 ( D ID 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 27-2: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC12F1571/2 ONLY 25 Max: 85°C + 3(cid:305) 20 Typical: 25°C Max. Typical A) 15 µ ( D D I 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001723D-page 284  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-3: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC12LF1571/2 ONLY 40 Max: 85°C + 3(cid:305) 35 Typical: 25°C Max. Typical 30 A) µ ( D ID 25 20 15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 27-4: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC12F1571/2 ONLY 50 Max. Max: 85°C + 3(cid:305) 45 Typical: 25°C 40 Typical A) µ (D 35 D I 30 25 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 285

PIC12(L)F1571/2 FIGURE 27-5: IDD TYPICAL, EC OSCILLATOR, MEDIUM POWER MODE, PIC12LF1571/2 ONLY 300 250 Typical: 25°C 4 MHz 200 A) µ 150 ( D D I 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 27-6: IDD MAXIMUM, EC OSCILLATOR, MEDIUM POWER MODE, PIC12LF1571/2 ONLY 300 Max: 85°C + 3(cid:305) 4 MHz 250 200 A) (µ 150 D D I 100 1 MHz 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001723D-page 286  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-7: IDD TYPICAL, EC OSCILLATOR, MEDIUM POWER MODE, PIC12F1571/2 ONLY 350 4 MHz 300 Typical: 25°C 250 A) 200 µ ( D D I 150 1 MHz 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 27-8: IDD MAXIMUM, EC OSCILLATOR, MEDIUM POWER MODE, PIC12F1571/2 ONLY 400 350 Max: 85°C + 3(cid:305) 4 MHz 300 250 A) µ ( 200 D D I 1 MHz 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 287

PIC12(L)F1571/2 FIGURE 27-9: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1571/2 ONLY 2.5 Typical: 25°C 2.0 32 MHz 1.5 A) m ( 16 MHz D D I 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 27-10: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1571/2 ONLY 2.5 Max: 85°C + 3(cid:305) 32 MHz 2.0 1.5 A) 16 MHz m ( D D I 1.0 8 MHz 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001723D-page 288  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-11: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1571/2 ONLY 2.5 Typical: 25°C 2.0 32 MHz 1.5 A) 16 MHz m ( D D 1.0 I 8 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 27-12: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1571/2 ONLY 2.5 Max: 85°C + 3(cid:305) 32 MHz 2.0 1.5 16 MHz A) m ( D ID 1.0 8 MHz 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 289

PIC12(L)F1571/2 FIGURE 27-13: IDD, LFINTOSC, FOSC = 31 kHz, PIC12LF1571/2 ONLY 10 Max. 9 Max: 85°C + 3(cid:305) Typical: 25°C Typical 8 7 A) µ ( D 6 D I 5 4 3 2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 27-14: IDD, LFINTOSC, FOSC = 31 kHz, PIC12F1571/2 ONLY 25 Max: 85°C + 3(cid:305) Typical: 25°C Max. 20 Typical A) 15 µ ( D D I 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) DS40001723D-page 290  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-15: IDD, MFINTOSC, FOSC = 500 kHz, PIC12LF1571/2 ONLY 170 160 Max: 85°C + 3(cid:305) Max. Typical: 25°C 150 140 A) µ ( Typical D D 130 I 120 110 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 27-16: IDD, MFINTOSC, FOSC = 500 kHz, PIC12F1571/2 ONLY 260 Max. 240 Max: 85°C + 3(cid:305) Typical: 25°C Typical 220 200 A) (µ 180 D D I 160 140 120 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 291

PIC12(L)F1571/2 FIGURE 27-17: IDD TYPICAL, HFINTOSC, PIC12LF1571/2 ONLY 1.4 16 MHz 1.2 Typical: 25°C 1.0 8 MHz A) 0.8 m ( 4 MHz D D 0.6 I 2 MHz 0.4 1 MHz 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) FIGURE 27-18: IDD MAXIMUM, HFINTOSC, PIC12LF1571/2 ONLY 1.4 16 MHz 1.2 Max: 85°C + 3(cid:305) 1.0 8 MHz A) 0.8 4 MHz m ( D 2 MHz D 0.6 I 1 MHz 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V) DS40001723D-page 292  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-19: IDD TYPICAL, HFINTOSC, PIC12F1571/2 ONLY 1.4 16 MHz 1.2 Typical: 25°C 1.0 8 MHz 0.8 A) 4 MHz m ( 2 MHz D 0.6 D I 1 MHz 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V) FIGURE 27-20: IDD MAXIMUM, HFINTOSC, PIC12F1571/2 ONLY 1.6 1.4 Max: 85°C + 3(cid:305) 16 MHz 1.2 1.0 8 MHz A) m 0.8 4 MHz ( D 2 MHz D I 0.6 1 MHz 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 293

PIC12(L)F1571/2 FIGURE 27-21: IPD BASE, LOW-POWER SLEEP MODE, PIC12LF1571/2 ONLY 335500 300 Max: 85°C + 3(cid:305) Max. Typical: 25°C 250 A)A 220000 nn (( DD PP 115500 II 100 Typical 50 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 27-22: IPD BASE, LOW-POWER SLEEP MODE, PIC12F1571/2 ONLY 00..88 0.7 Max: 85°C + 3(cid:305) Typical: 25°C 0.6 Max 0.5 A)A µµ (( 00..44 DD PP II 0.3 Typical 0.2 00..11 00..00 22.00 22.55 33.00 33.55 44.00 44.55 55.00 55.55 66.00 VDD(V) DS40001723D-page 294  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-23: IPD, WATCHDOG TIMER (WDT), PIC12LF1571/2 ONLY 11..00 0.9 Max: 85°C + 3(cid:305) Typical: 25°C 0.8 Max. 0.7 0.6 A)A) TTyyppiiccaall µµ 00..55 (( DD IIPP 00.44 0.3 0.2 00..11 00..00 11.66 11.88 22.00 22.22 22.44 22.66 22.88 33.00 33.22 33.44 33.66 33.88 VDD(V) FIGURE 27-24: IPD, WATCHDOG TIMER (WDT), PIC12F1571/2 ONLY 11..66 1.4 Max: 85°C + 3(cid:305) Typical: 25°C 1.2 Max. 1.0 A)A µµ (( 00..88 DD TTyyppiiccaall PP II 0.6 0.4 0.2 00..00 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 295

PIC12(L)F1571/2 FIGURE 27-25: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12LF1571/2 ONLY 2288 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) 26 Typical: 25°C 24 Max. 22 A)A) 2200 uu (( DD 1188 PP II TTypiicall 16 14 1122 1100 11.66 11.88 22.00 22.22 22.44 22.66 22.88 33.00 33.22 33.44 33.66 33.88 VDD(V) FIGURE 27-26: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12F1571/2 ONLY 2244 22 Max. 20 Typical A)A 1188 uu (( DD PP 1166 II 14 Max: 85°C + 3(cid:305) 12 TTyyppiiccaall:: 2255°CC 1100 22.00 22.55 33.00 33.55 44.00 44.55 55.00 55.55 66.00 VDD(V) DS40001723D-page 296  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-27: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12LF1571/2 ONLY 99 8.5 Max: 85°C + 3(cid:305) Typical: 25°C 8 Max. 7.5 A) u 77 ((DD TTyyppiiccaall PP II 66..55 6 5.5 55 44..55 22.44 22.55 22.66 22.77 22.88 22.99 33.00 33.11 33.22 33.33 33.44 33.55 33.66 33.77 VDD(V) FIGURE 27-28: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12F1571/2 ONLY 1122 11 Max: 85°C + 3(cid:305) Typical: 25°C 10 Max. 9 A)A) 88 uu (( DD TTyyppiiccaall PP I 7 6 5 44 22.88 33.00 33.22 33.44 33.66 33.88 44.00 44.22 44.44 44.66 44.88 55.00 55.22 55.44 55.66 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 297

PIC12(L)F1571/2 FIGURE 27-29: IPD, LOW-POWER BROWN-OUT RESET (LPBOR = 0), PIC12LF1571/2 ONLY 11..88 11.66 Max: 85°C + 3(cid:305) Typical: 25°C 1.4 Max. 1.2 A)A 1 uu (( DD 00..88 PP II 0.6 0.4 Typical 0.2 00 22..44 22..55 22..66 22..77 22..88 22..99 33..00 33..11 33..22 33..33 33..44 33..55 33..66 33..77 VDD(V) FIGURE 27-30: IPD, LOW-POWER BROWN-OUT RESET (LPBOR = 0), PIC12F1571/2 ONLY 11..88 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) 1.6 Typical: 25°C Max. 1.4 1.2 A)A 11..00 µµ (( DD DD 00..88 II 0.6 Typical 0.4 00..22 00..00 22.88 33.00 33.22 33.44 33.66 33.88 44.00 44.22 44.44 44.66 44.88 55.00 55.22 55.44 55.66 VDD(V) DS40001723D-page 298  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-31: IPD, ADC NON-CONVERTING, PIC12LF1571/2 ONLY 550000 450 Max: 85°C + 3(cid:305) Typical: 25°C Max. 400 350 300 A)A) µµ225500 (( DD PP I220000 150 100 Typical 50 00 11..66 11..88 22..00 22..22 22..44 22..66 22..88 33..00 33..22 33..44 33..66 33..88 VDD(V) FIGURE 27-32: IPD, ADC NON-CONVERTING, PIC12F1571/2 ONLY 11..44 Max: 85°C + 3(cid:305) 1.2 Typical: 25°C Max. 1.0 00..88 A)A) µµ (( DDDD 00..66 I 0.4 Typical 0.2 00..00 11.55 22.00 22.55 33.00 33.55 44.00 44.55 55.00 55.55 66.00 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 299

PIC12(L)F1571/2 FIGURE 27-33: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12F1571/2 ONLY 2222 2200 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) Typical: 25°C Max. 18 16 Typical A) 14 µµ (( DD PP 1122 II 10 8 6 44 22.00 22.55 33.00 33.55 44.00 44.55 55.00 55.55 66.00 VDD(V) FIGURE 27-34: IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC12LF1571/2 ONLY 3322 MMaaxx:: --4400°°CC ++ 33(cid:305)(cid:305) 3300 Typical: 25°C 28 Max. 26 24 A)A (µ(µ 2222 DD TTyyppiiccaall PP II 2200 18 16 1144 1122 11.66 11.88 22.00 22.22 22.44 22.66 22.88 33.00 33.22 33.44 33.66 33.88 VDD(V) DS40001723D-page 300  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-35: IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC12F1571/2 ONLY 4455 MMaaxx:: -4400°°CC ++ 33(cid:305)(cid:305) 40 Typical: 25°C Max. 35 Typical 30 A)A µµ (( DD 2255 PP II 20 15 1100 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 301

PIC12(L)F1571/2 FIGURE 27-36: IPD, PWM, HFINTOSC MODE (16MHz), PIC12LF1571/2 ONLY 11110000 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) 1000 Typical: 25°C 900 Max. 800 A)A 770000 µµ (( TTyyppiiccaall PDPD 660000 II 500 400 300 220000 11.66 11.88 22.00 22.22 22.44 22.66 22.88 33.00 33.22 33.44 33.66 33.88 VDD(V) FIGURE 27-37: IPD, PWM, HFINTOSC MODE (16MHz), PIC12F1571/2 ONLY 11,,220000 MMaaxx:: 8855°°CC ++ 33(cid:305)(cid:305) 1,100 Typical: 25°C Max. 1,000 Typical 900 A)A µµ 880000 (( DD PP II 770000 600 500 440000 22..00 22..55 33..00 33..55 44..00 44..55 55..00 55..55 66..00 VDD(V) DS40001723D-page 302  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 FIGURE 27-38: FVR STABILIZATION PERIOD 60 Max: Typical + 3(cid:305) 50 Typical: statistical mean @ 25°C Max. 40 ) Typical s u e ( 30 m Ti 20 Note: The FVR Stabilization Period applies when: 1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices. 10 2) when exiting sleep mode with VREGPM = 1for PIC12/16Fxxxx devices In all other cases, the FVR is stable when released from RESET. 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD(V)  2013-2015 Microchip Technology Inc. DS40001723D-page 303

PIC12(L)F1571/2 NOTES: DS40001723D-page 304  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 28.0 DEVELOPMENT SUPPORT 28.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2013-2015 Microchip Technology Inc. DS40001723D-page 305

PIC12(L)F1571/2 28.2 MPLAB XC Compilers 28.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 28.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 28.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001723D-page 306  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 28.6 MPLAB X SIM Software Simulator 28.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 28.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 28.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 28.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2013-2015 Microchip Technology Inc. DS40001723D-page 307

PIC12(L)F1571/2 28.11 Demonstration/Development 28.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001723D-page 308  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX 12F1571 XXXXXNNN E/Pe3 017 YYWW 1310 8-Lead SOIC (3.90 mm) Example 12F1571 E/SN1310 NNN 017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2013-2015 Microchip Technology Inc. DS40001723D-page 309

PIC12(L)F1571/2 Package Marking Information (Continued) 8-Lead MSOP (3x3 mm) Example L1571I 310017 8-Lead DFN (3x3x0.9 mm) 8-Lead UDFN (3x3x0.5 mm) Example XXXX MFQ0 YYWW 1312 NNN 017 PIN 1 PIN 1 DS40001723D-page 310  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 TABLE 29-1: 8-LEAD 3x3x0.9 DFN (MF) TOP TABLE 29-2: 8-LEAD 3x3x0.5 UDFN (RF) MARKING TOP MARKING Part Number Marking Part Number Marking PIC12F1571-E/MF MFY0/YYWW/NNN PIC12F1571-E/MF MFY0/YYWW/NNN PIC12F1572-E/MF MGA0/YYWW/NNN PIC12F1572-E/MF MGA0/YYWW/NNN PIC12F1571-I/MF MFZ0 PIC12F1571-I/MF MFZ0 PIC12F1572-I/MF MGB0 PIC12F1572-I/MF MGB0 PIC12LF1571-E/MF MGC0 PIC12LF1571-E/MF MGC0 PIC12LF1572-E/MF MGE0 PIC12LF1572-E/MF MGE0 PIC12LF1571-I/MF MGD0 PIC12LF1571-I/MF MGD0 PIC12LF1572-I/MF MGF0 PIC12LF1572-I/MF MGF0  2013-2015 Microchip Technology Inc. DS40001723D-page 311

PIC12(L)F1571/2 29.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 DS40001723D-page 312  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2  2013-2015 Microchip Technology Inc. DS40001723D-page 313

PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001723D-page 314  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001723D-page 315

PIC12(L)F1571/2 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS40001723D-page 316  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001723D-page 317

PIC12(L)F1571/2 Note: For the mostcurrent package drawings,please seetheMicrochip Packaging Specification located at http://www.microchip.com/packaging DS40001723D-page 318  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001723D-page 319

PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001723D-page 320  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS40001723D-page 321

PIC12(L)F1571/2 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001723D-page 322  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.10 C 1 2 2X 0.10 C TOP VIEW 0.05 C A1 C A SEATING PLANE 8X (A3) 0.05 C SIDE VIEW 0.10 C A B D2 1 2 L 0.10 C A B E2 NOTE 1 K N e 8X b e 0.10 C A B 2 BOTTOM VIEW Microchip Technology Drawing C04-254A Sheet 1 of 2  2013-2015 Microchip Technology Inc. DS40001723D-page 323

PIC12(L)F1571/2 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Terminals N 8 Pitch e 0.65 BSC Overall Height A 0.45 0.50 0.55 Standoff A1 0.00 0.02 0.05 Terminal Thickness A3 0.065 REF Overall Width E 3.00 BSC Exposed Pad Width E2 1.40 1.50 1.60 Overall Length D 3.00 BSC Exposed Pad Length D2 2.20 2.30 2.40 Terminal Width b 0.25 0.30 0.35 Terminal Length L 0.35 0.45 0.55 Terminal-to-Exposed-Pad K 0.20 - - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-254A Sheet 2 of 2 DS40001723D-page 324  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C X2 E Y2 X1 G1 G2 SILK SCREEN Y1 RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MIN NOM MAX Contact Pitch E 0.65 BSC Optional Center Pad Width X2 1.60 Optional Center Pad Length Y2 2.40 Contact Pad Spacing C 2.90 Contact Pad Width (X8) X1 0.35 Contact Pad Length (X8) Y1 0.85 Contact Pad to Contact Pad (X6) G1 0.20 Contact Pad to Center Pad (X8) G2 0.30 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2254A  2013-2015 Microchip Technology Inc. DS40001723D-page 325

PIC12(L)F1571/2 NOTES: DS40001723D-page 326  2013-2015 Microchip Technology Inc.

PIC12(L)F1571/2 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (10/2013) Original release of this document. Revision B (2/2014) Updated PIC12(L)F1571/2 Family Types table Program Memory Flash heading (words to K words). Revision C (8/2014) Updated PWM chapter. Changed to Final data sheet. Updated IDD and IPD parameters in the Electrical Specification chapter. Added Characterization Graphs. Added Section 1.1: Register and Bit Naming Conventions. Updated Figures 5-3 and 15-5. Updated Tables 3-1, 3-7, and 3-10. Updated Section 15.2.5. Updated Equa- tion 15-1. Revision D (8/2015) Updated Clocking Structure, Memory, Low-Power Features, Family Types table and Pin Diagram Table on cover pages. Added Sections 3.2: High-Endurance Flash and 5.4:Clock Switching Before Sleep. Added Table 29-2 and 8-pin UDFN packaging. Updated Examples 3-2 and 15-1. Updated Figures 8-1, 21-1, 22-8 through 22-13 and 23-1. Updated Registers 7-5, 8-1, 22-6 and 23-3. Updated Sections 8.2.2, 15.2.6, 16.0, 21.0, 21.4.2, 22.3.3, 23.9.1.2, 23.11.1, 26.1 and 29.1. Updated Tables 1, 3-3, 3-4, 3-10, 5-1, 16-1, 17-3, 22-2, 23-2, 26-6, 26-8 and 29-1.  2013-2015 Microchip Technology Inc. DS40001723D-page 327

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PIC12(L)F1571/2 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2013-2015 Microchip Technology Inc. DS40001723D-page 329

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PIC12(L)F1571/2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC12LF1571T - I/SO Option Range Tape and Reel, Industrial temperature, SOIC package b) PIC12F1572 - I/P Device: PIC12LF1571, PIC12F1571 Industrial temperature, PIC12LF1572, PIC12F1572 PDIP package c) PIC12F1571-E/MF Extended Temperature, Tape and Reel Blank = Standard packaging (tube or tray) DFN package Option: T = Tape and Reel(1) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Note1: Tape and Reel identifier only appears in the catalog part number description. This identifier Package:(2) MF = Micro Lead Frame (DFN) 3x3x0.9 mm is used for ordering purposes and is not printed MS = MSOP on the device package. Check with your P = Plastic DIP Microchip Sales Office for package availability SN = SOIC with the Tape and Reel option. RF = Micro Lead Frame (UDFN) 3x3x0.5 mm 2: For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your Pattern: QTP, SQTP, Code or Special Requirements local sales office. (blank otherwise)  2013-2015 Microchip Technology Inc. DS40001723D-page 331

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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights unless otherwise stated. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-715-7 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2013-2015 Microchip Technology Inc. DS40001723D-page 333

Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office Asia Pacific Office China - Xiamen Austria - Wels 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 86-592-2388138 Tel: 43-7242-2244-39 Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 86-592-2388130 Fax: 43-7242-2244-393 Tel: 480-792-7200 Harbour City, Kowloon China - Zhuhai Denmark - Copenhagen Fax: 480-792-7277 Hong Kong Tel: 86-756-3210040 Tel: 45-4450-2828 Technical Support: Tel: 852-2943-5100 Fax: 86-756-3210049 Fax: 45-4485-2829 http://www.microchip.com/ Fax: 852-2401-3431 India - Bangalore France - Paris support Australia - Sydney Tel: 91-80-3090-4444 Tel: 33-1-69-53-63-20 Web Address: Tel: 61-2-9868-6733 Fax: 91-80-3090-4123 Fax: 33-1-69-30-90-79 www.microchip.com Fax: 61-2-9868-6755 India - New Delhi Germany - Dusseldorf Atlanta China - Beijing Tel: 91-11-4160-8631 Tel: 49-2129-3766400 Duluth, GA Tel: 86-10-8569-7000 Fax: 91-11-4160-8632 Tel: 678-957-9614 Germany - Karlsruhe Fax: 678-957-1455 Fax: 86-10-8528-2104 India - Pune Tel: 49-721-625370 China - Chengdu Tel: 91-20-3019-1500 Germany - Munich ATeul:s 5ti1n2, -T2X57-3370 Tel: 86-28-8665-5511 Japan - Osaka Tel: 49-89-627-144-0 Fax: 86-28-8665-7889 Tel: 81-6-6152-7160 Fax: 49-89-627-144-44 BWoessttobonrough, MA China - Chongqing Fax: 81-6-6152-9310 Italy - Milan Tel: 774-760-0087 Tel: 86-23-8980-9588 Japan - Tokyo Tel: 39-0331-742611 Fax: 86-23-8980-9500 Tel: 81-3-6880- 3770 Fax: 39-0331-466781 Fax: 774-760-0088 China - Dongguan Fax: 81-3-6880-3771 Italy - Venice CItahsiccaa,g IoL Tel: 86-769-8702-9880 Korea - Daegu Tel: 39-049-7625286 Tel: 630-285-0071 China - Hangzhou Tel: 82-53-744-4301 Netherlands - Drunen Fax: 630-285-0075 Tel: 86-571-8792-8115 Fax: 82-53-744-4302 Tel: 31-416-690399 Fax: 86-571-8792-8116 Korea - Seoul Fax: 31-416-690340 Cleveland Independence, OH China - Hong Kong SAR Tel: 82-2-554-7200 Poland - Warsaw Tel: 216-447-0464 Tel: 852-2943-5100 Fax: 82-2-558-5932 or Tel: 48-22-3325737 Fax: 852-2401-3431 82-2-558-5934 Fax: 216-447-0643 Spain - Madrid China - Nanjing Malaysia - Kuala Lumpur Tel: 34-91-708-08-90 Dallas Addison, TX Tel: 86-25-8473-2460 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91 Fax: 86-25-8473-2470 Fax: 60-3-6201-9859 Tel: 972-818-7423 Sweden - Stockholm Fax: 972-818-2924 China - Qingdao Malaysia - Penang Tel: 46-8-5090-4654 Tel: 86-532-8502-7355 Tel: 60-4-227-8870 Detroit UK - Wokingham Fax: 86-532-8502-7205 Fax: 60-4-227-4068 Novi, MI Tel: 44-118-921-5800 Tel: 248-848-4000 China - Shanghai Philippines - Manila Fax: 44-118-921-5820 Tel: 86-21-5407-5533 Tel: 63-2-634-9065 Houston, TX Fax: 86-21-5407-5066 Fax: 63-2-634-9069 Tel: 281-894-5983 China - Shenyang Singapore Indianapolis Tel: 86-24-2334-2829 Tel: 65-6334-8870 Noblesville, IN Fax: 86-24-2334-2393 Fax: 65-6334-8850 Tel: 317-773-8323 Fax: 317-773-5453 China - Shenzhen Taiwan - Hsin Chu Tel: 86-755-8864-2200 Tel: 886-3-5778-366 Los Angeles Fax: 86-755-8203-1760 Fax: 886-3-5770-955 Mission Viejo, CA Tel: 949-462-9523 China - Wuhan Taiwan - Kaohsiung Fax: 949-462-9608 Tel: 86-27-5980-5300 Tel: 886-7-213-7828 Fax: 86-27-5980-5118 New York, NY Taiwan - Taipei Tel: 631-435-6000 China - Xian Tel: 886-2-2508-8600 Tel: 86-29-8833-7252 Fax: 886-2-2508-0102 San Jose, CA Fax: 86-29-8833-7256 Tel: 408-735-9110 Thailand - Bangkok Tel: 66-2-694-1351 Canada - Toronto Fax: 66-2-694-1350 Tel: 905-673-0699 Fax: 905-673-6509 07/14/15 DS40001723D-page 334  2013-2015 Microchip Technology Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC12F1571-I/MF PIC12F1571-I/MS PIC12F1571-I/SN PIC12F1572-I/MF PIC12F1572-I/MS PIC12F1572-I/P PIC12F1572-I/SN PIC12F1571-I/P PIC12LF1571-E/P PIC12LF1572-I/SN PIC12LF1571-E/SN PIC12LF1571-I/MF PIC12LF1571-I/SN PIC12LF1571T-I/MF PIC12LF1572-E/MF PIC12LF1571-E/MF PIC12LF1572-I/MF PIC12LF1572- I/P PIC12LF1571-I/MS PIC12LF1572-E/P PIC12LF1571T-I/MS PIC12LF1572-I/MS PIC12LF1572T-I/SN PIC12LF1571-I/P PIC12LF1572-E/MS PIC12LF1572-E/SN PIC12LF1571-E/MS PIC12LF1572T-I/MF PIC12LF1571T-I/SN PIC12LF1572T-I/MS PIC12F1572-E/MS PIC12F1571-E/MS PIC12F1572T-I/MF PIC12F1571- E/MF PIC12F1571T-I/MF PIC12F1572-E/SN PIC12F1571-E/P PIC12F1572-E/MF PIC12F1572-E/P PIC12F1571T- I/SN PIC12F1571T-I/MS PIC12F1572T-I/SN PIC12F1572T-I/MS PIC12F1571-E/SN PIC12F1572-E/RF PIC12LF1571-I/RF PIC12F1571-E/RF PIC12F1572-I/RF PIC12LF1572-I/RF PIC12F1571-I/RF PIC12F1572T-I/RF PIC12LF1572T-I/RF PIC12LF1572-E/RF PIC12F1571T-I/RF PIC12LF1571-E/RF PIC12LF1571T-I/RF