PIC12C5XX 8-Pin, 8-Bit CMOS Microcontrollers Devices included in this Data Sheet: Peripheral Features: • PIC12C508 • PIC12C508A • PIC12CE518 • 8-bit real time clock/counter (TMR0) with 8-bit • PIC12C509 • PIC12C509A • PIC12CE519 programmable prescaler • PIC12CR509A • Power-On Reset (POR) • Device Reset Timer (DRT) Note: Throughout this data sheet PIC12C5XX refers to the PIC12C508, PIC12C509, • Watchdog Timer (WDT) with its own on-chip RC PIC12C508A, PIC12C509A, oscillator for reliable operation PIC12CR509A, PIC12CE518 and • Programmable code-protection PIC12CE519. PIC12CE5XX refers to • 1,000,000 erase/write cycle EEPROM data PIC12CE518 and PIC12CE519. memory High-Performance RISC CPU: • EEPROM data retention > 40 years • Only 33 single word instructions to learn • Power saving SLEEP mode • All instructions are single cycle (1 m s) except for • Wake-up from SLEEP on pin change program branches which are two-cycle • Internal weak pull-ups on I/O pins • Operating speed:DC - 4 MHz clock input • Internal pull-up on MCLR pin DC - 1 m s instruction cycle • Selectable oscillator options: Memory - INTRC: Internal 4 MHz RC oscillator Device EPROM ROM RAM EEPROM - EXTRC:External low-cost RC oscillator Program Program Data Data - XT: Standard crystal/resonator PIC12C508 512 x 12 25 - LP: Power saving, low frequency crystal PIC12C508A 512 x 12 25 CMOS Technology: PIC12C509 1024 x 12 41 • Low power, high speed CMOS EPROM/ROM PIC12C509A 1024 x 12 41 technology PIC12CE518 512 x 12 25 16 • Fully static design PIC12CE519 1024 x 12 41 16 • Wide operating voltage range PIC12CR509A 1024 x 12 41 • Wide temperature range: • 12-bit wide instructions - Commercial: 0°C to +70°C • 8-bit wide data path - Industrial: -40°C to +85°C • Seven special function hardware registers - Extended: -40°C to +125°C • Two-level deep hardware stack • Low power consumption • Direct, indirect and relative addressing modes for - < 2 mA @ 5V, 4 MHz data and instructions - 15 m A typical @ 3V, 32 KHz • Internal 4 MHz RC oscillator with programmable - < 1 m A typical standby current calibration • In-circuit serial programming (cid:211) 1999 Microchip Technology Inc. DS40139E-page 1

PIC12C5XX Pin Diagram - PIC12C508/509 PDIP, 208 mil SOIC, Windowed Ceramic Side Brazed VDD 1 PP 8 VSS GP5/OSC1/CLKIN 2 IC1IC1 7 GP0 22 GP4/OSC2 3 C5C5 6 GP1 GP3/MCLR/VPP 4 0908 5 GP2/T0CKI Pin Diagram - PIC12C508A/509A, PIC12CE518/519 PDIP, 150 & 208 mil SOIC, Windowed CERDIP VDD 1 PPPP8 VSS GP5/OSC1/CLKIN 2 IC1IC1IC1IC17 GP0 GP4/OSC2 3 2C2C2C2C6 GP1 GP3/MCLR/VPP 4 E519E518509A508A5 GP2/T0CKI Pin Diagram - PIC12CR509A PDIP, 150 & 208 mil SOIC VDD 1 P 8 VSS GP5/OSC1/CLKIN 2 IC1 7 GP0 2 GP4/OSC2 3 C 6 GP1 R GP3/MCLR/VPP 4 50 5 GP2/T0CKI 9 A Device Differences Oscillator Process Voltage Device Oscillator Calibration2 Technology Range (Bits) (Microns) PIC12C508A 3.0-5.5 See Note 1 6 0.7 PIC12LC508A 2.5-5.5 See Note 1 6 0.7 PIC12C508 2.5-5.5 See Note 1 4 0.9 PIC12C509A 3.0-5.5 See Note 1 6 0.7 PIC12LC509A 2.5-5.5 See Note 1 6 0.7 PIC12C509 2.5-5.5 See Note 1 4 0.9 PIC12CR509A 2.5-5.5 See Note 1 6 0.7 PIC12CE518 3.0-5.5 - 6 0.7 PIC12LCE518 2.5-5.5 - 6 0.7 PIC12CE519 3.0-5.5 - 6 0.7 PIC12LCE519 2.5-5.5 - 6 0.7 Note 1: If you change from the PIC12C50X to the PIC12C50XA or to the PIC12CR50XA, please verify oscillator characteristics in your application. Note 2: See Section 7.2.5 for OSCCAL implementation differences. DS40139E-page 2 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE OF CONTENTS 1.0 General Description...............................................................................................................................................4 2.0 PIC12C5XX Device Varieties................................................................................................................................7 3.0 Architectural Overview...........................................................................................................................................9 4.0 Memory Organization..........................................................................................................................................13 5.0 I/O Port................................................................................................................................................................21 6.0 Timer0 Module and TMR0 Register....................................................................................................................25 7.0 EEPROM Peripheral Operation...........................................................................................................................29 8.0 Special Features of the CPU...............................................................................................................................35 9.0 Instruction Set Summary.....................................................................................................................................47 10.0 Development Support..........................................................................................................................................59 11.0 Electrical Characteristics - PIC12C508/PIC12C509............................................................................................65 12.0 DC and AC Characteristics - PIC12C508/PIC12C509........................................................................................75 13.0 Electrical Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/ PIC12CE518/PIC12CE519/ PIC12LCE518/PIC12LCE519/PIC12LCR509A...................................................................................................79 14.0 DC and AC Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/ PIC12LCE518/PIC12LCE519/ PIC12LCR509A..................................................................................................93 15.0 Packaging Information.........................................................................................................................................99 Index...........................................................................................................................................................................105 PIC12C5XX Product Identification System ................................................................................................................109 Sales and Support:.....................................................................................................................................................109 To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of doc- ument DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and rec- ommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 3

PIC12C5XX 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC12C5XX from Microchip Technology is a fam- The PIC12C5XX series fits perfectly in applications ily of low-cost, high performance, 8-bit, fully static, ranging from personal care appliances and security EEPROM/EPROM/ROM-based CMOS microcontrol- systems to low-power remote transmitters/receivers. lers. It employs a RISC architecture with only 33 sin- The EPROM technology makes customizing applica- gle word/single cycle instructions. All instructions are tion programs (transmitter codes, appliance settings, single cycle (1 m s) except for program branches receiver frequencies, etc.) extremely fast and conve- which take two cycles. The PIC12C5XX delivers per- nient, while the EEPROM data memory technology formance an order of magnitude higher than its com- allows for the changing of calibration factors and secu- petitors in the same price category. The 12-bit wide rity codes. The small footprint packages, for through instructions are highly symmetrical resulting in 2:1 hole or surface mounting, make this microcontroller code compression over other 8-bit microcontrollers in series perfect for applications with space limitations. its class. The easy to use and easy to remember Low-cost, low-power, high performance, ease of use instruction set reduces development time signifi- and I/O flexibility make the PIC12C5XX series very ver- cantly. satile even in areas where no microcontroller use has The PIC12C5XX products are equipped with special been considered before (e.g., timer functions, replace- features that reduce system cost and power require- ment of “glue” logic and PLD’s in larger systems, copro- ments. The Power-On Reset (POR) and Device Reset cessor applications). Timer (DRT) eliminate the need for external reset cir- cuitry. There are four oscillator configurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator mode. Power saving SLEEP mode, Watchdog Timer and code protection features also improve system cost, power and reliability. The PIC12C5XX are available in the cost-effective One-Time-Programmable (OTP) versions which are suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in OTP microcontrollers while benefiting from the OTP’s flexibility. The PIC12C5XX products are supported by a full-fea- tured macro assembler, a software simulator, an in-cir- cuit emulator, a ‘C’ compiler, fuzzy logic support tools, a low-cost development programmer, and a full fea- tured programmer. All the tools are supported on IBM(cid:210) PC and compatible machines. DS40139E-page 4 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES PIC12C508(A) PIC12C509(A) PIC12CR509A PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674 Maximum 4 4 4 4 4 10 10 10 10 Frequency Clock of Operation (MHz) EPROM 512 x 12 1024 x 12 1024 x 12 512 x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14 Program (ROM) Memory Memory RAM Data 25 41 41 25 41 128 128 128 128 Memory (bytes) EEPROM — — — 16 16 — — 16 16 Data Memory (bytes) Timer TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 Peripherals Module(s) A/D Con- — — — — — 4 4 4 4 verter (8-bit) Channels Wake-up Yes Yes Yes Yes Yes Yes Yes Yes Yes from SLEEP on pin change Interrupt — — — 4 4 4 4 Sources Features I/O Pins 5 5 5 5 5 5 5 5 5 Input Pins 1 1 1 1 1 1 1 1 1 Internal Yes Yes Yes Yes Yes Yes Yes Yes Yes Pull-ups In-Circuit Yes Yes — Yes Yes Yes Yes Yes Yes Serial Programming Number of 33 33 33 33 33 35 35 35 35 Instructions Packages 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, 8-pin DIP, JW, SOIC JW, SOIC SOIC JW, SOIC JW, SOIC JW, SOIC JW, SOIC JW JW All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 5

PIC12C5XX NOTES: DS40139E-page 6 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 2.0 PIC12C5XX DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP) Devices A variety of packaging options are available. Depending on application and production Microchip offers a QTP Programming Service for requirements, the proper device option can be factory production orders. This service is made selected using the information in this section. When available for users who choose not to program a placing orders, please use the PIC12C5XX Product medium to high quantity of units and whose code Identification System at the back of this data sheet to patterns have stabilized. The devices are identical to specify the correct part number. the OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain 2.1 UV Erasable Devices code and prototype verification procedures do apply The UV erasable version, offered in ceramic side before production shipments are available. Please con- brazed package, is optimal for prototype development tact your local Microchip Technology sales office for and pilot programs. more details. The UV erasable version can be erased and 2.4 Serialized Quick-Turnaround reprogrammed to any of the configuration modes. Production (SQTPSM) Devices Note: Please note that erasing the device will Microchip offers a unique programming service where also erase the pre-programmed internal a few user-defined locations in each device are calibration value for the internal oscillator. programmed with different serial numbers. The serial The calibration value must be saved prior numbers may be random, pseudo-random or to erasing the part. sequential. Microchip’s PICSTART(cid:226) PLUS and PRO MATE(cid:226) pro- Serial programming allows each device to have a grammers all support programming of the PIC12C5XX. unique number which can serve as an entry-code, Third party programmers also are available; refer to the password or ID number. Microchip Third Party Guide for a list of sources. 2.5 Read Only Memory (ROM) Device 2.2 One-Time-Programmable (OTP) Devices Microchip offers masked ROM to give the customer a low cost option for high volume, mature products. The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications. The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 7

PIC12C5XX NOTES: DS40139E-page 8 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 3.0 ARCHITECTURAL OVERVIEW The PIC12C5XX device contains an 8-bit ALU and working register. The ALU is a general purpose The high performance of the PIC12C5XX family can arithmetic unit. It performs arithmetic and Boolean be attributed to a number of architectural features functions between data in the working register and any commonly found in RISC microprocessors. To begin register file. with, the PIC12C5XX uses a Harvard architecture in which program and data are accessed on separate The ALU is 8-bits wide and capable of addition, buses. This improves bandwidth over traditional von subtraction, shift and logical operations. Unless Neumann architecture where program and data are otherwise mentioned, arithmetic operations are two's fetched on the same bus. Separating program and complement in nature. In two-operand instructions, data memory further allows instructions to be sized typically one operand is the W (working) register. The differently than the 8-bit wide data word. Instruction other operand is either a file register or an immediate opcodes are 12-bits wide making it possible to have all constant. In single operand instructions, the operand is single word instructions. A 12-bit wide program either the W register or a file register. memory access bus fetches a 12-bit instruction in a The W register is an 8-bit working register used for single cycle. A two-stage pipeline overlaps fetch and ALU operations. It is not an addressable register. execution of instructions. Consequently, all instructions Depending on the instruction executed, the ALU may (33) execute in a single cycle (1m s @ 4MHz) except for affect the values of the Carry (C), Digit Carry (DC), program branches. and Zero (Z) bits in the STATUS register. The C and The table below lists program memory (EPROM), data DC bits operate as a borrow and digit borrow out bit, memory (RAM), ROM memory, and non-volatile respectively, in subtraction. See the SUBWF and ADDWF (EEPROM) for each device. instructions for examples. A simplified block diagram is shown in Figure3-1, with Memory the corresponding device pins described in Table3-1. Device EPROM ROM RAM EEPROM Program Program Data Data PIC12C508 512 x 12 25 PIC12C509 1024 x 12 41 PIC12C508A 512 x 12 25 PIC12C509A 1024 x 12 41 PIC12CR509A 1024 x 12 41 PIC12CE518 512 x 12 25 x 8 16 x 8 PIC12CE519 1024 x 12 41 x 8 16 x 8 The PIC12C5XX can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. The PIC12C5XX has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC12C5XX simple yet efficient. In addition, the learning curve is reduced significantly. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 9

PIC12C5XX FIGURE 3-1: PIC12C5XX BLOCK DIAGRAM 12 Data Bus 8 GPIO ROM/EPROM Program Counter 512 x 12 or GP0 1024 x 12 GP1 PMreomgroarmy SSTTAACCKK12 245RF1 xA ilx eM8 8 or GGGPPP432///MTO0SCCCLKR2I/VPP Registers GP5/OSC1/CLKIN Program 12 Bus RAM Addr 9 L A C D Instruction reg Addr MUX S S Direct Addr 5 Indirect 16 X 8 5-7 Addr EEPROM FSR reg Data Memory PIC12CE5XX STATUS reg Only 8 3 MUX Device Reset Timer Instruction DCecoondtreo l& Power-on ALU Reset 8 OOSSCC12/CLKIN GeTnimeriantgion WaTticmhedrog W reg Internal RC OSC Timer0 MCLR VDD, VSS DS40139E-page 10 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE 3-1: PIC12C5XX PINOUT DESCRIPTION DIP SOIC I/O/P Buffer Name Description Pin # Pin # Type Type GP0 7 7 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP1 6 6 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. GP2/T0CKI 5 5 I/O ST Bi-directional I/O port. Can be configured as T0CKI. GP3/MCLR/VPP 4 4 I TTL/ST Input port/master clear (reset) input/programming volt- age input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter programming mode. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull-up always on if configured as MCLR. ST when in MCLR mode. GP4/OSC2 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con- nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, GPIO in other modes). GP5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external clock source input (GPIO in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when GPIO, ST input in external RC oscillator mode. VDD 1 1 P — Positive supply for logic and I/O pins VSS 8 8 P — Ground reference for logic and I/O pins Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input, ST = Schmitt Trigger input (cid:211) 1999 Microchip Technology Inc. DS40139E-page 11

PIC12C5XX 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining The clock input (OSC1/CLKIN pin) is internally divided An Instruction Cycle consists of four Q cycles (Q1, Q2, by four to generate four non-overlapping quadrature Q3 and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle program counter is incremented every Q1, and the while decode and execute takes another instruction instruction is fetched from program memory and cycle. However, due to the pipelining, each instruction latched into instruction register in Q4. It is decoded effectively executes in one cycle. If an instruction and executed during the following Q1 through Q4. The causes the program counter to change (e.g., GOTO) clocks and instruction execution flow is shown in then two cycles are required to complete the Figure3-2 and Example3-1. instruction (Example3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Q3 phase clock Q4 PC PC PC+1 PC+2 Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF GPIO Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF GPIO, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS40139E-page 12 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP AND STACK PIC12C5XX memory is organized into program mem- ory and data memory. For devices with more than 512 PC<11:0> bytes of program memory, a paging scheme is used. CALL, RETLW 12 Program memory pages are accessed using one STA- TUS register bit. For the PIC12C509, PIC12C509A, Stack Level 1 PICCR509A and PIC12CE519 with a data memory Stack Level 2 register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR). Reset Vector (note 1) 0000h 4.1 Program Memory Organization On-chip Program The PIC12C5XX devices have a 12-bit Program Memory Counter (PC) capable of addressing a 2K x 12 y or program memory space. me OPInCly1 2Cth5e0 8f,i rPstI C1521C2 50x8 A1 2a nd(0 P0I0C01h2-0C1EF5F1h8) anfodr 1Kth ex ser MeSpac 512 Word 0012F00Fhh U 12 (0000h-03FFh) for the PIC12C509, PIC12C509A, On-chip Program PIC12CR509A, and PIC12CE519 are physically Memory implemented. Refer to Figure4-1. Accessing a location above these boundaries will cause a wrap- around within the first 512 x 12 space (PIC12C508, 1024 Word 03FFh PIC12C508A and PIC12CE518) or 1K x 12 space 0400h (PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519). The effective reset vector is at 000h, (see Figure4-1). Location 01FFh (PIC12C508, PIC12C508A and PIC12CE518) or location 03FFh (PIC12C509, PIC12C509A, PIC12CR509A and 7FFh PIC12CE519) contains the internal clock oscillator calibration value. This value should never be Note 1: Address 0000h becomes the overwritten. effective reset vector. Location 01FFh (PIC12C508, PIC12C508A, PIC12CE518) or location 03FFh (PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519) con- tains the MOVLW XX INTERNAL RC oscillator calibration value. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 13

PIC12C5XX 4.2 Data Memory Organization FIGURE 4-2: PIC12C508, PIC12C508A AND PIC12CE518 REGISTER FILE Data memory is composed of registers, or bytes of MAP RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two File Address functional groups: special function registers and general purpose registers. 00h INDF(1) The special function registers include the TMR0 01h TMR0 register, the Program Counter (PC), the Status 02h PCL Register, the I/O registers (ports), and the File Select 03h STATUS Register (FSR). In addition, special purpose registers are used to control the I/O port configuration and 04h FSR prescaler options. 05h OSCCAL The general purpose registers are used for data and 06h GPIO control information under command of the instructions. 07h For the PIC12C508, PIC12C508A and PIC12CE518, the register file is composed of 7 special function registers and 25 general purpose registers (Figure4- General 2). Purpose Registers For the PIC12C509, PIC12C509A, PIC12CR509A, and PIC12CE519 the register file is composed of 7 special function registers, 25 general purpose registers, and 16 general purpose registers that may 1Fh be addressed using a banking scheme (Figure4-3). 4.2.1 GENERAL PURPOSE REGISTER FILE Note 1: Not a physical register. See Section4.8 The general purpose register file is accessed either directly or indirectly through the file select register FSR (Section4.8). FIGURE 4-3: PIC12C509, PIC12C509A, PIC12CR509A AND PIC12CE519 REGISTER FILE MAP FSR<6:5> 00 01 File Address 00h INDF(1) 20h 01h TMR0 02h PCL 03h STATUS Addresses map back to 04h FSR addresses 05h OSCCAL in Bank 0. 06h GPIO 07h General Purpose Registers 0Fh 2Fh 10h 30h General General Purpose Purpose Registers Registers 1Fh 3Fh Bank 0 Bank 1 Note 1: Not a physical register. See Section4.8 DS40139E-page 14 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 4.2.2 SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets. The special function registers associated with the The Special Function Registers (SFRs) are registers “core” functions are described in this section. Those used by the CPU and peripheral functions to control related to the operation of the peripheral features are the operation of the device (Table4-1). described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY Value on Value on Power-On All Other Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Resets(2) N/A TRIS — — --11 1111 --11 1111 Contains control bits to configure Timer0, Timer0/WDT N/A OPTION prescaler, wake-up on change, and weak pull-ups 1111 1111 1111 1111 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111 03h STATUS GPWUF — PA0 TO PD Z DC C 0001 1xxx q00q quuu(3) FSR (PIC12C508/ PIC12C508A/ 04h PIC12C518) Indirect data memory address pointer 111x xxxx 111u uuuu FSR (PIC12C509/ PIC12C509A/ PIC12CR509A/ 04h PIC12CE519) Indirect data memory address pointer 110x xxxx 11uu uuuu OSCCAL (PIC12C508/ 05h PIC12C509) CAL3 CAL2 CAL1 CAL0 — — — — 0111 ---- uuuu ---- OSCCAL (PIC12C508A/ PIC12C509A/ PIC12CE518/ PIC12CE519/ 05h PIC12CR509A) CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- uuuu uu-- GPIO (PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ 06h PIC12CR509A) — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu GPIO (PIC12CE518/ 06h PIC12CE519) SCL SDA GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu Legend: Shaded boxes = unimplemented or unused, — = unimplemented, read as ’0’ (if applicable) x = unknown, u = unchanged, q = see the tables in Section8.7 for possible values. Note 1: The upper byte of the Program Counter is not directly accessible. See Section4.6 for an explanation of how to access these bits. 2: Other (non power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset. 3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 15

PIC12C5XX 4.3 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register This register contains the arithmetic status of the ALU, as 000u u1uu (where u = unchanged). the RESET status, and the page preselect bit for It is recommended, therefore, that only BCF, BSF and program memories larger than 512 words. MOVWF instructions be used to alter the STATUS The STATUS register can be the destination for any register because these instructions do not affect the Z, instruction, as with any other register. If the STATUS DC or C bits from the STATUS register. For other register is the destination for an instruction that affects instructions, which do affect STATUS bits, see the Z, DC or C bits, then the write to these three bits is Instruction Set Summary. disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. FIGURE 4-4: STATUS REGISTER (ADDRESS:03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x GPWUF — PA0 TO PD Z DC C R = Readable bit bit7 6 5 4 3 2 1 bit0 W = Writable bit - n = Value at POR reset bit 7: GPWUF: GPIO reset bit 1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset bit 6: Unimplemented bit 5: PA0: Program page preselect bits 1 = Page 1 (200h - 3FFh) - PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519 0 = Page 0 (000h - 1FFh) - PIC12C5XX Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur SUBWF 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF SUBWF RRF or RLF 1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively 0 = A carry did not occur 0 = A borrow occurred DS40139E-page 16 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 4.4 OPTION Register Note: If TRIS bit is set to ‘0’, the wake-up on The OPTION register is a 8-bit wide, write-only change and pull-up functions are disabled register which contains various control bits to for that pin; i.e., note that TRIS overrides configure the Timer0/WDT prescaler and Timer0. OPTION control of GPPU and GPWU. By executing the OPTION instruction, the contents of Note: If the T0CS bit is set to ‘1’, GP2 is forced to the W register will be transferred to the OPTION be an input even if TRIS GP2 = ‘0’. register. A RESET sets the OPTION<7:0> bits. FIGURE 4-5: OPTION REGISTER W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit bit7 6 5 4 3 2 1 bit0 U = Unimplemented bit - n = Value at POR reset Reference Table4-1 for other resets. bit 7: GPWU: Enable wake-up on pin change (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 6: GPPU: Enable weak pull-ups (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 5: T0CS: Timer0 clock source select bit 1 = Transition on T0CKI pin 0 = Transition on internal instruction cycle clock, Fosc/4 bit 4: T0SE: Timer0 source edge select bit 1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin bit 3: PSA: Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0: PS2:PS0: Prescaler rate select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 (cid:211) 1999 Microchip Technology Inc. DS40139E-page 17

PIC12C5XX 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains four to six bits for calibration. Increasing the cal value increases the frequency. See Section 7.2.5 for more information on the internal oscillator. FIGURE 4-6: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508 AND PIC12C509 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0 U-0 CAL3 CAL2 CAL1 CAL0 — — — — R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-4: CAL<3:0>: Calibration bit 3-0: Unimplemented: Read as ’0’ FIGURE 4-7: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508A/C509A/CR509A/12CE518/ 12CE519 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented: Read as ’0’ DS40139E-page 18 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program The Program Counter is set upon a RESET, which Counter (PC) will contain the address of the next means that the PC addresses the last location in the program instruction to be executed. The PC value is last page i.e., the oscillator calibration instruction. After increased by one every instruction cycle, unless an executing MOVLW XX, the PC will roll over to location instruction changes the PC. 00h, and begin executing user code. For a GOTO instruction, bits 8:0 of the PC are provided The STATUS register page preselect bits are cleared by the GOTO instruction word. The PC Latch (PCL) is upon a RESET, which means that page 0 is pre- mapped to PC<7:0>. Bit 5 of the STATUS register selected. provides page information to bit 9 of the PC (Figure4- Therefore, upon a RESET, a GOTO instruction will 8). automatically cause the program to jump to page0 For a CALL instruction, or any instruction where the until the value of the page bits is altered. PCL is the destination, bits 7:0 of the PC again are 4.7 Stack provided by the instruction word. However, PC<8> does not come from the instruction word, but is always PIC12C5XX devices have a 12-bit wide L.I.F.O. cleared (Figure4-8). hardware push/pop stack. Instructions where the PCL is the destination, or A CALL instruction will push the current value of stack Modify PCL instructions, include MOVWF PC, ADDWF 1 into stack 2 and then push the current program PC, and BSF PC,5. counter value, incremented by one, into stack level 1. If Note: Because PC<8> is cleared in the CALL more than two sequential CALL’s are executed, only instruction, or any Modify PCL instruction, the most recent two return addresses are stored. all subroutine calls or computed jumps are A RETLW instruction will pop the contents of stack level limited to the first 256 locations of any pro- 1 into the program counter and then copy stack level 2 gram memory page (512 words long). contents into level 1. If more than two sequential FIGURE 4-8: LOADING OF PC RETLW’s are executed, the stack will be filled with the address previously stored in level 2. Note that the BRANCH INSTRUCTIONS - Wregister will be loaded with the literal value specified PIC12C5XX in the instruction. This is particularly useful for the implementation of data look-up tables within the GOTO Instruction program memory. 11 10 9 8 7 0 PC PCL Upon any reset, the contents of the stack remain unchanged, however the program counter (PCL) will also be reset to 0. Instruction Word Note 1: There are no STATUS bits to indicate PA0 stack overflows or stack underflow condi- 7 0 tions. Note 2: There are no instructions mnemonics STATUS called PUSH or POP. These are actions that occur from the execution of the CALL CALL or Modify PCL Instruction and RETLW instructions. 11 10 9 8 7 0 PC PCL Instruction Word Reset to ‘0’ PA0 7 0 STATUS (cid:211) 1999 Microchip Technology Inc. DS40139E-page 19

PIC12C5XX 4.8 Indirect Data Addressing; INDF and EXAMPLE 4-2: HOW TO CLEAR RAM FSR Registers USING INDIRECT ADDRESSING The INDF register is not a physical register. movlw 0x10 ;initialize pointer Addressing INDF actually addresses the register movwf FSR ; to RAM whose address is contained in the FSR register (FSR NEXT clrf INDF ;clear INDF register is a pointer). This is indirect addressing. incf FSR,F ;inc pointer btfsc FSR,4 ;all done? EXAMPLE 4-1: INDIRECT ADDRESSING goto NEXT ;NO, clear next CONTINUE • Register file 07 contains the value 10h : ;YES, continue • Register file 08 contains the value 0Ah • Load the value 07 into the FSR register The FSR is a 5-bit wide register. It is used in • A read of the INDF register will return the value conjunction with the INDF register to indirectly address of10h the data memory area. • Increment the value of the FSR register by one The FSR<4:0> bits are used to select data memory (FSR = 08) addresses 00h to 1Fh. • A read of the INDR register now will return the PIC12C508/PIC12C508A/PIC12CE518: Does not value of 0Ah. use banking. FSR<7:5> are unimplemented and read Reading INDF itself indirectly (FSR = 0) will produce as'1's. 00h. Writing to the INDF register indirectly results in a PIC12C509/PIC12C509A/PIC12CR509A/ no-operation (although STATUS bits may be affected). PIC12CE519: Uses FSR<5>. Selects between bank 0 A simple program to clear RAM locations 10h-1Fh and bank 1. FSR<7:6> is unimplemented, read as '1’ . using indirect addressing is shown in Example4-2. FIGURE 4-9: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing (FSR) 6 5 4 (opcode) 0 6 5 4 (FSR) 0 bank select location select bank location select 00 01 00h Addresses map back to addresses in Bank 0. Data 0Fh Memory(1) 10h 1Fh 3Fh Bank 0 Bank 1(2) Note 1: For register map detail see Section4.2. Note 2: PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519. DS40139E-page 20 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 5.0 I/O PORT 5.3 I/O Interfacing As with any other register, the I/O register can be The equivalent circuit for an I/O port pin is shown in written and read under program control. However, read Figure5-1. All port pins, except GP3 which is input instructions (e.g., MOVF GPIO,W) always read the I/O only, may be used for both input and output operations. pins independent of the pin’s input/output modes. On For input operations these ports are non-latching. Any RESET, all I/O ports are defined as input (inputs are at input must be present until read by an input instruction hi-impedance) since the I/O control registers are all (e.g., MOVF GPIO,W). The outputs are latched and set. See Section 7.0 for SCL and SDA description for remain unchanged until the output latch is rewritten. To PIC12CE5XX. use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an 5.1 GPIO input, the corresponding TRIS bit must be set. Any I/O pin (except GP3) can be programmed individually as GPIO is an 8-bit I/O register. Only the low order 6 bits input or output. are used (GP5:GP0). Bits 7 and 6 are unimplemented and read as '0's. Please note that GP3 is an input only FIGURE 5-1: EQUIVALENT CIRCUIT pin. The configuration word can set several I/O’s to FOR A SINGLE I/O PIN alternate functions. When acting as alternate functions the pins will read as ‘0’ during port read. Pins GP0, Data Bus GP1, and GP3 can be configured with weak pull-ups D Q and also with wake-up on change. The wake-up on Data change and weak pull-up functions are not pin WR Latch VDD Port selectable. If pin 4 is configured as MCLR, weak pull- CK Q P up is always on and wake-up on change for this pin is not enabled. 5.2 TRIS Register W N I/O Reg pin(1,3) D Q The output driver control register is loaded with the TRIS contents of the W register by executing the TRIS f Latch VSS instruction. A '1' from a TRIS register bit puts the TRIS ‘f’ CK Q corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The Reset exceptions are GP3 which is input only and GP2 which (2) may be controlled by the option register, see Figure4- 5. Note: A read of the ports reads the pins, not the RD Port output data latches. That is, if an output driver on a pin is enabled and driven high, Note 1: I/O pins have protection diodes to VDD but the external system is holding it low, a and VSS. read of the port will indicate that the pin is Note 2: See Table 3-1 for buffer type. low. Note 3: See Section 7.0 for SCL and SDA The TRIS registers are “write-only” and are set (output description for PIC12CE5XX drivers disabled) upon RESET. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 21

PIC12C5XX TABLE 5-1: SUMMARY OF PORT REGISTERS Value on Power-On Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset All Other Resets N/A TRIS — — --11 1111 --11 1111 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03H STATUS GPWUF — PAO TO PD Z DC C 0001 1xxx q00q quuu(1) GPIO (PIC12C508/ PIC12C509/ PIC12C508A/ PIC12C509A/ 06h PIC12CR509A) — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu GPIO (PIC12CE518/ 06h PIC12CE519) SCL SDA GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in Section8.7 for possible values. Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0. 5.4 I/O Programming Considerations EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 5.4.1 BI-DIRECTIONAL I/O PORTS I/O PORT Some instructions operate internally as read followed ;Initial GPIO Settings ; GPIO<5:3> Inputs by write operations. The BCF and BSF instructions, for ; GPIO<2:0> Outputs example, read the entire port into the CPU, execute ; the bit operation and re-write the result. Caution must ; GPIO latch GPIO pins be used when these instructions are applied to a port ; ---------- ---------- where one or more pins are used as input/outputs. For BCF GPIO, 5 ;--01 -ppp --11 pppp example, a BSF operation on bit5 of GPIO will cause BCF GPIO, 4 ;--10 -ppp --11 pppp all eight bits of GPIO to be read into the CPU, bit5 to MOVLW 007h ; be set and the GPIO value to be written to the output TRIS GPIO ;--10 -ppp --11 pppp latches. If another bit of GPIO is used as a bi- ; directional I/O pin (say bit0) and it is defined as an ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused input at this time, the input signal present on the pin ;GP5 to be latched as the pin value (High). itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the 5.4.2 SUCCESSIVE OPERATIONS ON I/O previous content. As long as the pin stays in the input PORTS mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch The actual write to an I/O port happens at the end of may now be unknown. an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle Example5-1 shows the effect of two sequential read- (Figure5-2). Therefore, care must be exercised if a modify-write instructions (e.g., BCF, BSF, etc.) on an write followed by a read operation is carried out on the I/O port. same I/O port. The sequence of instructions should A pin actively outputting a high or a low should not be allow the pin voltage to stabilize (load dependent) driven from external devices at the same time in order before the next instruction, which causes that file to be to change the level on this pin (“wired-or”, “wired- read into the CPU, is executed. Otherwise, the and”). The resulting high output currents may damage previous state of that pin may be read into the CPU the chip. rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. DS40139E-page 22 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX FIGURE 5-2: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 This example shows a write to GPIO followed Instruction by a read from GPIO. fetched MOVWF GPIO MOVF GPIO,W NOP NOP Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle. GP5:GP0 TPD = propagation delay Port pin Port pin Therefore, at higher clock frequencies, a written here sampled here write followed by a read may be problematic. Instruction executed MOVWF GPIO MOVF GPIO,W NOP (Write to (Read GPIO) GPIO) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 23

PIC12C5XX NOTES: DS40139E-page 24 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 6.0 TIMER0 MODULE AND Counter mode is selected by setting the T0CS bit TMR0 REGISTER (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The The Timer0 module has the following features: T0SE bit (OPTION<4>) determines the source edge. • 8-bit timer/counter register, TMR0 Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed - Readable and writable in detail in Section6.1. • 8-bit software programmable prescaler The prescaler may be used by either the Timer0 • Internal or external clock select module or the Watchdog Timer, but not both. The - Edge select for external clock prescaler assignment is controlled in software by the Figure6-1 is a simplified block diagram of the Timer0 control bit PSA (OPTION<3>). Clearing the PSA bit module. will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is Timer mode is selected by clearing the T0CS bit assigned to the Timer0 module, prescale values of 1:2, (OPTION<5>). In timer mode, the Timer0 module will 1:4,..., 1:256 are selectable. Section6.2 details the increment every instruction cycle (without prescaler). If operation of the prescaler. TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure6-2 and A summary of registers associated with the Timer0 Figure6-3). The user can work around this by writing module is found in Table6-1. an adjusted value to the TMR0 register. FIGURE 6-1: TIMER0 BLOCK DIAGRAM Data bus GP2/T0CKI FOSC/4 0 Pin PSout 8 1 Sync with 1 Internal TMR0 reg Clocks Programmable 0 PSout T0SE Prescaler(2) (2 TCY delay) Sync 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) Note1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure6-5). (cid:211) 1999 Microchip Technology Inc. DS40139E-page 25

PIC12C5XX FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0+1 T0+2 NT0 NT0+1 NT0+2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0+1 NT0 NT0+1 T0 Instruction Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Power-On All Other Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Resets 01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRIS — — GP5 GP4 GP3 GP2 GP1 GP0 --11 1111 --11 1111 Legend:Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged, DS40139E-page 26 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 6.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type When an external clock input is used for Timer0, it prescaler so that the prescaler output is symmetrical. must meet certain requirements. The external clock For the external clock to meet the sampling requirement is due to internal phase clock (TOSC) requirement, the ripple counter must be taken into synchronization. Also, there is a delay in the actual account. Therefore, it is necessary for T0CKI to have a incrementing of Timer0 after synchronization. period of at least 4TOSC (and a small RC delay of 40ns) divided by the prescaler value. The only 6.1.1 EXTERNAL CLOCK SYNCHRONIZATION requirement on T0CKI high and low time is that they When no prescaler is used, the external clock input is do not violate the minimum pulse width requirement of the same as the prescaler output. The synchronization 10 ns. Refer to parameters 40, 41 and 42 in the of T0CKI with the internal phase clocks is electrical specification of the desired device. accomplished by sampling the prescaler output on the 6.1.2 TIMER0 INCREMENT DELAY Q2 and Q4 cycles of the internal phase clocks (Figure6-4). Therefore, it is necessary for T0CKI to be Since the prescaler output is synchronized with the high for at least 2TOSC (and a small RC delay of 20ns) internal clocks, there is a small delay from the time the and low for at least 2TOSC (and a small RC delay of external clock edge occurs to the time the Timer0 20ns). Refer to the electrical specification of the module is actually incremented. Figure6-4 shows the desired device. delay from the external clock edge to the timer incrementing. 6.1.3 OPTION REGISTER EFFECT ON GP2 TRIS If the option register is set to read TIMER0 from the pin, the port is forced to an input regardless of the TRIS reg- ister setting. FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output (2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = – 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 27

PIC12C5XX 6.2 Prescaler EXAMPLE 6-1: CHANGING PRESCALER (TIMER0fi WDT) An 8-bit counter is available as a prescaler for the 1.CLRWDT ;Clear WDT Timer0 module, or as a postscaler for the Watchdog 2.CLRF TMR0 ;Clear TMR0 & Prescaler Timer (WDT), respectively (Section8.6). For simplicity, 3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7) this counter is being referred to as “prescaler” 4.OPTION ; are required only if throughout this data sheet. Note that the prescaler ; desired may be used by either the Timer0 module or the WDT, 5.CLRWDT ;PS<2:0> are 000 or 001 but not both. Thus, a prescaler assignment for the 6.MOVLW '00xx1xxx’b ;Set Postscaler to Timer0 module means that there is no prescaler for 7.OPTION ; desired WDT rate the WDT, and vice-versa. To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example6-2. This The PSA and PS2:PS0 bits (OPTION<3:0>) sequence must be used even if the WDT is disabled. A determine prescaler assignment and prescale ratio. CLRWDT instruction should be executed before When assigned to the Timer0 module, all instructions switching the prescaler. writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. EXAMPLE 6-2: CHANGING PRESCALER When assigned to WDT, a CLRWDT instruction will (WDTfi TIMER0) clear the prescaler along with the WDT. The prescaler CLRWDT ;Clear WDT and is neither readable nor writable. On a RESET, the ;prescaler prescaler contains all '0's. MOVLW 'xxxx0xxx' ;Select TMR0, new ;prescale value and 6.2.1 SWITCHING PRESCALER ASSIGNMENT ;clock source OPTION The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = Fosc/4) Data Bus 0 8 GP2P/Tin0CKI 1 MUX 1 MU Sy2nc TMR0 reg 0 X Cycles T0SE T0CS PSA 0 8-bit Prescaler M U Watchdog 1 X 8 Timer 8 - to - 1MUX PS2:PS0 PSA 0 1 WDT Enable bit MUX PSA WDT Time-Out Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register. DS40139E-page 28 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 7.0 EEPROM PERIPHERAL Namely, to avoid code overhead in modifying the TRIS OPERATION register, both SDA and SCL are always outputs. To read data from the EEPROM peripheral requires out- This section applies to PIC12CE518 and putting a ‘1’ on SDA placing it in high-Z state, where PIC12CE519 only. only the internal 100K pull-up is active on the SDA line. The PIC12CE518 and PIC12CE519 each have 16 SDA: bytes of EEPROM data memory. The EEPROM mem- Built-in 100K (typical) pull-up to VDD ory has an endurance of 1,000,000 erase/write cycles Open-drain (pull-down only) and a data retention of greater than 40 years. The Always an output EEPROM data memory supports a bi-directional 2-wire Outputs a ‘1’ on reset bus and data transmission protocol. These two-wires SCL: are serial data (SDA) and serial clock (SCL), that are Full CMOS output mapped to bit6 and bit7, respectively, of the GPIO reg- Always an output ister (SFR 06h). Unlike the GP0-GP5 that are con- Outputs a ‘1’ on reset nected to the I/O pins, SDA and SCL are only The following example requires: connected to the internal EEPROM peripheral. For most applications, all that is required is calls to the fol- • Code Space: 77 words lowing functions: • RAM Space: 5 bytes (4 are overlayable) ; Byte_Write: Byte write routine • Stack Levels:1 (The call to the function itself. The ; Inputs:EEPROM Address EEADDR functions do not call any lower level functions.) ; EEPROM Data EEDATA • Timing: ; Outputs: Return 01 in W if OK, else - WRITE_BYTE takes 328 cycles return 00 in W ; - READ_CURRENT takes 212 cycles ; Read_Current: Read EEPROM at address - READ_RANDOM takes 416 cycles. currently held by EE device. • IO Pins: 0 (No external IO pins are used) ; Inputs:NONE ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else This code must reside in the lower half of a page. The return 00 in W code achieves it’s small size without additional calls ; through the use of a sequencing table. The table is a ; Read_Random: Read EEPROM byte at supplied address list of procedures that must be called in order. The ; Inputs:EEPROM Address EEADDR table uses an ADDWF PCL,F instruction, effectively a ; Outputs: EEPROM Data EEDATA computed goto, to sequence to the next procedure. ; Return 01 in W if OK, However the ADDWF PCL,F instruction yields an 8 bit else return 00 in W address, forcing the code to reside in the first 256 The code for these functions is available on our website addresses of a page. www.microchip.com. The code will be accessed by either including the source code FL51XINC.ASM or by linking FLASH5IX.ASM. It is very important to check the return codes when using these calls, and retry the operation if unsuccess- ful. Unsuccessful return codes occur when the EE data memory is busy with the previous write, which can take up to 4 mS. 7.0.1 SERIAL DATA SDA is a bi-directional pin used to transfer addresses and data into and data out of the device. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP condi- tions. The EEPROM interface is a 2-wire bus protocol con- sisting of data (SDA) and a clock (SCL). Although these lines are mapped into the GPIO register, they are not accessible as external pins; only to the internal EEPROM peripheral. SDA and SCL operation is also slightly different than GPO-GP5 as listed below. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 29

PIC12C5XX Figure 7-1: Block diagram of GPIO6 (SDA line) VDD reset To 24L00 SDA Pad D EN write ck Q databus GPIO Output Latch Q D ENck Schmitt Trigger Input Latch Read ltchpin GPIO Figure 7-2: Block diagram of GPIO7 (SCL line) VDD To 24LC00 SCL D Pad EN write ck Q databus GPIO Q D ENck Schmitt Trigger Read ltchpin GPIO DS40139E-page 30 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 7.0.2 SERIAL CLOCK 7.1.4 DATA VALID (D) This SCL input is used to synchronize the data transfer The state of the data line represents valid data when, from and to the device. after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. 7.1 BUS CHARACTERISTICS The data on the line must be changed during the LOW The following bus protocol is to be used with the period of the clock signal. There is one bit of data per EEPROM data memory. clock pulse. • Data transfer may be initiated only when the bus Each data transfer is initiated with a START condition is not busy. and terminated with a STOP condition. The number of the data bytes transferred between the START and During data transfer, the data line must remain stable STOP conditions is determined by the master device whenever the clock line is HIGH. Changes in the data and is theoretically unlimited. line while the clock line is HIGH will be interpreted as a START or STOP condition. 7.1.5 ACKNOWLEDGE Accordingly, the following bus conditions have been Each receiving device, when addressed, is obliged to defined (Figure7-3). generate an acknowledge after the reception of each 7.1.1 BUS NOT BUSY (A) byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Both data and clock lines remain HIGH. Note: Acknowledge bits are not generated if an 7.1.2 START DATA TRANSFER (B) internal programming cycle is in progress. The device that acknowledges has to pull down the A HIGH to LOW transition of the SDA line while the SDA line during the acknowledge clock pulse in such a clock (SCL) is HIGH determines a START condition. All way that the SDA line is stable LOW during the HIGH commands must be preceded by a START condition. period of the acknowledge related clock pulse. Of 7.1.3 STOP DATA TRANSFER (C) course, setup and hold times must be taken into account. A master must signal an end of data to the A LOW to HIGH transition of the SDA line while the slave by not generating an acknowledge bit on the last clock (SCL) is HIGH determines a STOP condition. All byte that has been clocked out of the slave. In this case, operations must be ended with a STOP condition. the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure7-4). (cid:211) 1999 Microchip Technology Inc. DS40139E-page 31

PIC12C5XX FIGURE 7-3: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (C) (D) (C) (A) SCL SDA START ADDRESS OR DATA STOP CONDITION ACKNOWLEDGE ALLOWED CONDITION VALID TO CHANGE FIGURE 7-4: ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 3 4 5 6 7 8 9 1 2 3 SDA Data from transmitter Data from transmitter Transmitter must release the SDA line at this point Receiver must release the SDA line at this point allowing the Receiver to pull the SDA line low to so the Transmitter can continue sending data. acknowledge the previous eight bits of data. 7.2 Device Addressing FIGURE 7-5: CONTROL BYTE FORMAT After generating a START condition, the bus master Read/Write Bit transmits a control byte consisting of a slave address and a Read/Write bit that indicates what type of opera- Device Select Don’t Care tion is to be performed. The slave address consists of Bits Bits a 4-bit device code (1010) followed by three don’t care bits. S 1 0 1 0 X X X R/W ACK The last bit of the control byte determines the operation to be performed. When set to a one a read operation is Slave Address selected, and when set to a zero a write operation is selected. (Figure7-5). The bus is monitored for its cor- Start Bit Acknowledge Bit responding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. DS40139E-page 32 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 7.3 WRITE OPERATIONS 7.4 ACKNOWLEDGE POLLING 7.3.1 BYTE WRITE Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is Following the start signal from the master, the device complete (this feature can be used to maximize bus code (4 bits), the don’t care bits (3 bits), and the R/W throughput). Once the stop condition for a write com- bit (which is a logic low) are placed onto the bus by the mand has been issued from the master, the device ini- master transmitter. This indicates to the addressed tiates the internally timed write cycle. ACK polling can slave receiver that a byte with a word address will follow be initiated immediately. This involves the master send- after it has generated an acknowledge bit during the ing a start condition followed by the control byte for a ninth clock cycle. Therefore, the next byte transmitted write command (R/W = 0). If the device is still busy with by the master is the word address and will be written the write cycle, then no ACK will be returned. If no ACK into the address pointer. Only the lower four address is returned, then the start bit and control byte must be bits are used by the device, and the upper four bits are re-sent. If the cycle is complete, then the device will don’t cares. The address byte is acknowledgeable and return the ACK and the master can then proceed with the master device will then transmit the data word to be the next read or write command. See Figure7-6 for written into the addressed memory location. The mem- flow diagram. ory acknowledges again and the master generates a stop condition. This initiates the internal write cycle, FIGURE 7-6: ACKNOWLEDGE POLLING and during this time will not generate acknowledge sig- FLOW nals (Figure7-7). After a byte write command, the inter- nal address counter will not be incremented and will Send point to the same address location that was just written. Write Command If a stop bit is transmitted to the device at any point in the write command sequence before the entire sequence is complete, then the command will abort Send Stop and no data will be written. If more than 8 data bits are Condition to transmitted before the stop bit is sent, then the device Initiate Write Cycle will clear the previously loaded byte and begin loading the data buffer again. If more than one data byte is transmitted to the device and a stop bit is sent before a full eight data bits have been transmitted, then the write Send Start command will abort and no data will be written. The EEPROM memory employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below minimum VDD. Send Control Byte with R/W = 0 Byte write operations must be preceded and immedi- ately followed by a bus not busy bus cycle where both SDA and SCL are held high. Did Device NO Acknowledge (ACK = 0)? YES Next Operation FIGURE 7-7: BYTE WRITE S S BUS ACTIVITY T CONTROL WORD T MASTER AR BYTE ADDRESS DATA O T P SDA LINE S 1 0 1 0 X X X 0 X X X X P A A A BUS ACTIVITY C C C K K K X = Don’t Care Bit (cid:211) 1999 Microchip Technology Inc. DS40139E-page 33

PIC12C5XX 7.5 READ OPERATIONS device as part of a write operation. After the word address is sent, the master generates a start condition Read operations are initiated in the same way as write following the acknowledge. This terminates the write operations with the exception that the R/W bit of the operation, but not before the internal address pointer is slave address is set to one. There are three basic types set. Then the master issues the control byte again but of read operations: current address read, random read, with the R/W bit set to a one. It will then issue an and sequential read. acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does gen- 7.5.1 CURRENT ADDRESS READ erate a stop condition and the device discontinues It contains an address counter that maintains the transmission (Figure7-9). After this command, the address of the last word accessed, internally incre- internal address counter will point to the address loca- mented by one. Therefore, if the previous read access tion following the one that was just read. was to address n, the next current address read opera- 7.5.3 SEQUENTIAL READ tion would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, Sequential reads are initiated in the same way as a ran- the device issues an acknowledge and transmits the dom read except that after the device transmits the first eight bit data word. The master will not acknowledge data byte, the master issues an acknowledge as the transfer but does generate a stop condition and the opposed to a stop condition in a random read. This device discontinues transmission (Figure7-8). directs the device to transmit the next sequentially addressed 8-bit word (Figure7-10). 7.5.2 RANDOM READ To provide sequential reads, it contains an internal Random read operations allow the master to access address pointer which is incremented by one at the any memory location in a random manner. To perform completion of each read operation. This address this type of read operation, first the word address must pointer allows the entire memory contents to be serially be set. This is done by sending the word address to the read during one operation. FIGURE 7-8: CURRENT ADDRESS READ S T S BUS ACTIVITY A CONTROL T MASTER R BYTE O T P SDA LINE S 10 10 XXX1 P A N BUS ACTIVITY C DATA O K A C X = Don’t Care Bit K FIGURE 7-9: RANDOM READ S S T T S BUS ACTIVITY A CONTROL WORD A CONTROL T MASTER R BYTE ADDRESS (n) R BYTE O T T P S 10 10 XXX0 X XXX S 10 10 XXX1 P SDA LINE A A A N C C C DATA (n) O K K K BUS ACTIVITY A C X = Don’t Care Bit K FIGURE 7-10: SEQUENTIAL READ S BUS ACTIVITY CONTROL T MASTER BYTE DATA n DATA n + 1 DATA n + 2 DATA n + X O P SDA LINE P A A A A N BUS ACTIVITY C C C C O K K K K A C K DS40139E-page 34 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 8.0 SPECIAL FEATURES OF THE The PIC12C5XX has a Watchdog Timer which can be CPU shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using What sets a microcontroller apart from other XT or LP selectable oscillator options, there is always processors are special circuits to deal with the needs an 18 ms (nominal) delay provided by the Device of real-time applications. The PIC12C5XX family of Reset Timer (DRT), intended to keep the chip in reset microcontrollers has a host of such features intended until the crystal oscillator is stable. If using INTRC or to maximize system reliability, minimize cost through EXTRC there is an 18 ms delay only on VDD power-up. elimination of external components, provide power With this timer on-chip, most applications need no saving operating modes and offer code protection. external reset circuitry. These features are: The SLEEP mode is designed to offer a very low • Oscillator selection current power-down mode. The user can wake-up • Reset from SLEEP through a change on input pins or - Power-On Reset (POR) through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit - Device Reset Timer (DRT) the application, including an internal 4 MHz oscillator. - Wake-up from SLEEP on pin change The EXTRC oscillator option saves system cost while • Watchdog Timer (WDT) the LP crystal option saves power. A set of • SLEEP configuration bits are used to select various options. • Code protection 8.1 Configuration Bits • ID locations • In-circuit Serial Programming The PIC12C5XX configuration word consists of 12 bits. Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit, and one bit is the MCLR enable bit. FIGURE 8-1: CONFIGURATION WORD FOR PIC12C5XX — — — — — — — MCLRE CP WDTE FOSC1FOSC0 Register: CONFIG bit11 10 9 8 7 6 5 4 3 2 1 bit0 Address(1): FFFh bit 11-5: Unimplemented bit 4: MCLRE: MCLR enable bit. 1 = MCLR pin enabled 0 = MCLR tied to VDD, (Internally) bit 3: CP: Code protection bit. 1 = Code protection off 0 = Code protection on bit 2: WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator selection bits 11 = EXTRC - external RC oscillator 10 = INTRC - internal RC oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the configuration word. This register is not user addressable during device operation. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 35

PIC12C5XX 8.2 Oscillator Configurations TABLE 8-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS 8.2.1 OSCILLATOR TYPES - PIC12C5XX The PIC12C5XX can be operated in four different Osc Resonator Cap. Range Cap. Range oscillator modes. The user can program two Type Freq C1 C2 configuration bits (FOSC1:FOSC0) to select one of XT 4.0 MHz 30 pF 30 pF these four modes: These values are for design guidance only. Since • LP: Low Power Crystal each resonator has its own characteristics, the user • XT: Crystal/Resonator should consult the resonator manufacturer for appropriate values of external components. • INTRC: Internal 4 MHz Oscillator • EXTRC:External Resistor/Capacitor TABLE 8-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - 8.2.2 CRYSTAL OSCILLATOR / CERAMIC PIC12C5XX RESONATORS Osc Resonator Cap.Range Cap. Range In XT or LP modes, a crystal or ceramic resonator is Type Freq C1 C2 connected to the GP5/OSC1/CLKIN and GP4/OSC2 LP 32 kHz(1) 15 pF 15 pF pins to establish oscillation (Figure8-2). The XT 200 kHz 47-68 pF 47-68 pF PIC12C5XX oscillator design requires the use of a 1 MHz 15 pF 15 pF parallel cut crystal. Use of a series cut crystal may give 4 MHz 15 pF 15 pF a frequency out of the crystal manufacturers specifications. When in XT or LP modes, the device Note1: For VDD > 4.5V, C1 = C2 » 30 pF is can have an external clock source drive the GP5/ recommended. OSC1/CLKIN pin (Figure8-3). These values are for design guidance only. Rs may be required to avoid overdriving crystals with low FIGURE 8-2: CRYSTAL OPERATION (OR drive level specification. Since each crystal has its CERAMIC RESONATOR) (XT own characteristics, the user should consult the crys- OR LP OSC tal manufacturer for appropriate values of external CONFIGURATION) components. C1(1) OSC1 PIC12C5XX SLEEP XTAL RF(3) To internal logic OSC2 RS(2) C2(1) Note1: See Capacitor Selection tables for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF approximate value = 10 MW . FIGURE 8-3: EXTERNAL CLOCK INPUT OPERATION (XT OR LP OSC CONFIGURATION) Clock from OSC1 ext. system PIC12C5XX Open OSC2 DS40139E-page 36 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 8.2.3 EXTERNAL CRYSTAL OSCILLATOR 8.2.4 EXTERNAL RC OSCILLATOR CIRCUIT For timing insensitive applications, the RC device Either a prepackaged oscillator or a simple oscillator option offers additional cost savings. The RC oscillator circuit with TTL gates can be used as an external frequency is a function of the supply voltage, the crystal oscillator circuit. Prepackaged oscillators resistor (Rext) and capacitor (Cext) values, and the provide a wide operating range and better stability. A operating temperature. In addition to this, the oscillator well-designed crystal oscillator will provide good frequency will vary from unit to unit due to normal performance with TTL gates. Two types of crystal process parameter variation. Furthermore, the oscillator circuits can be used: one with parallel difference in lead frame capacitance between package resonance, or one with series resonance. types will also affect the oscillation frequency, especially for low Cext values. The user also needs to Figure8-4 shows implementation of a parallel take into account variation due to tolerance of external resonant oscillator circuit. The circuit is designed to R and C components used. use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift Figure8-6 shows how the R/C combination is that a parallel oscillator requires. The 4.7 kW resistor connected to the PIC12C5XX. For Rext values below provides the negative feedback for stability. The 10kW 2.2kW , the oscillator operation may become unstable, potentiometers bias the 74AS04 in the linear region. or stop completely. For very high Rext values This circuit could be used for external oscillator (e.g.,1MW ) the oscillator becomes sensitive to noise, designs. humidity and leakage. Thus, we recommend keeping Rext between 3kW and 100kW . FIGURE 8-4: EXTERNAL PARALLEL RESONANT CRYSTAL Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values OSCILLATOR CIRCUIT above 20 pF for noise and stability reasons. With no or +5V small external capacitance, the oscillation frequency To Other can vary dramatically due to changes in external Devices 10k capacitances, such as PCB trace capacitance or 4.7k 74AS04 PIC12C5XX package lead frame capacitance. 74AS04 CLKIN The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R 10k (since leakage current variation will affect RC XTAL frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency 10k more). Also, see the Electrical Specifications sections for 20 pF 20 pF variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to Figure8-5 shows a series resonant oscillator circuit. operating temperature for given R, C, and VDD values. This circuit is also designed to use the fundamental FIGURE 8-6: EXTERNAL RC OSCILLATOR frequency of the crystal. The inverter performs a 180- MODE degree phase shift in a series resonant oscillator circuit. The 330W resistors provide the negative VDD feedback to bias the inverters in their linear region. FIGURE 8-5: EXTERNAL SERIES Rext Internal RESONANT CRYSTAL OSC1 clock OSCILLATOR CIRCUIT N To Other Cext 330 330 Devices PIC12C5XX PIC12C5XX VSS 74AS04 74AS04 74AS04 CLKIN 0.1 m F XTAL (cid:211) 1999 Microchip Technology Inc. DS40139E-page 37

PIC12C5XX 8.2.5 INTERNAL 4 MHz RC OSCILLATOR Some registers are not reset in any way; they are unknown on POR and unchanged in any other reset. The internal RC oscillator provides a fixed 4 MHz (nom- Most other registers are reset to “reset state” on power- inal) system clock at VDD = 5V and 25°C, see “Electri- on reset (POR), MCLR, WDT or wake-up on pin cal Specifications” section for information on variation change reset during normal operation. They are not over voltage and temperature. affected by a WDT reset during SLEEP or MCLR reset In addition, a calibration instruction is programmed into during SLEEP, since these resets are viewed as the top of memory which contains the calibration value resumption of normal operation. The exceptions to this for the internal RC oscillator. This location is never code are TO, PD, and GPWUF bits. They are set or cleared protected regardless of the code protect settings. This differently in different reset situations. These bits are value is programmed as a MOVLW XX instruction where used in software to determine the nature of reset. See XX is the calibration value, and is placed at the reset Table8-3 for a full description of reset states of all vector. This will load the W register with the calibration registers. value upon reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. . Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part. so it can be repro- grammed correctly later. For the PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, and PIC12CR509A, bits <7:2>, CAL5- CAL0 are used for calibration. Adjusting CAL5-0 from 000000 to 111111 yields a higher clock speed. Note that bits 1 and 0 of OSCCAL are unimplemented and should be written as 0 when modifying OSCCAL for compatibility with future devices. For the PIC12C508 and PIC12C509, the upper 4 bits of the register are used. Writing a larger value in this loca- tion yields a higher clock speed. 8.3 RESET The device differentiates between various kinds of reset: a) Power on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WDT time-out reset during normal operation e) WDT time-out reset during SLEEP f) Wake-up from SLEEP on pin change DS40139E-page 38 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE 8-3: RESET CONDITIONS FOR REGISTERS MCLR Reset Register Address Power-on Reset WDT time-out Wake-up on Pin Change W (PIC12C508/509) — qqqq xxxx (1) qqqq uuuu (1) W (PIC12C508A/509A/ — qqqq qqxx (1) qqqq qquu (1) PIC12CE518/519/ PIC12CE509A) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu (2,3) FSR (PIC12C508/ 04h 111x xxxx 111u uuuu PIC12C508A/ PIC12CE518) FSR (PIC12C509/ 04h 110x xxxx 11uu uuuu PIC12C509A/ PIC12CE519/ PIC12CR509A) OSCCAL 05h 0111 ---- uuuu ---- (PIC12C508/509) OSCCAL 05h 1000 00-- uuuu uu-- (PIC12C508A/509A/ PIC12CE518/512/ PIC12CR509A) GPIO 06h --xx xxxx --uu uuuu (PIC12C508/PIC12C509/ PIC12C508A/ PIC12C509A/ PIC12CR509A) GPIO 06h (PIC12CE518/ PIC12CE519) 11xx xxxx 11uu uuuu OPTION — 1111 1111 1111 1111 TRIS — --11 1111 --11 1111 Legend:u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. Note 2: See Table8-7 for reset value for specific conditions Note 3: If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0. TABLE 8-4: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h PCL Addr: 02h Power on reset 0001 1xxx 1111 1111 MCLR reset during normal operation 000u uuuu 1111 1111 MCLR reset during SLEEP 0001 0uuu 1111 1111 WDT reset during SLEEP 0000 0uuu 1111 1111 WDT reset normal operation 0000 uuuu 1111 1111 Wake-up from SLEEP on pin change 1001 0uuu 1111 1111 Legend:u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 39

PIC12C5XX 8.3.1 MCLR ENABLE The Power-On Reset circuit and the Device Reset Timer (Section8.5) circuit are closely related. On This configuration bit when unprogrammed (left in the power-up, the reset latch is set and the DRT is reset. ‘1’ state) enables the external MCLR function. When The DRT timer begins counting once it detects MCLR programmed, the MCLR function is tied to the internal to be high. After the time-out period, which is typically VDD, and the pin is assigned to be a GPIO. See 18 ms, it will reset the reset latch and thus end the on- Figure8-7. When pin GP3/MCLR/VPP is configured as chip reset signal. MCLR, the internal pull-up is always on. A power-up example where MCLR is held low is FIGURE 8-7: MCLR SELECT shown in Figure8-9. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of reset TDRT msec after MCLR goes high. MCLRE In Figure8-10, the on-chip Power-On Reset feature is WEAK being used (MCLR and VDD are tied together or the PULL-UP pin is programmed to be GP3.). The VDD is stable INTERNAL MCLR before the start-up timer times out and there is no GP3/MCLR/VPP problem in getting a proper reset. However, Figure8- 11 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR (and VDD) actually 8.4 Power-On Reset (POR) reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the The PIC12C5XX family incorporates on-chip Power- VDD (min) value and the chip is, therefore, not On Reset (POR) circuitry which provides an internal guaranteed to function correctly. For such situations, chip reset for most power-up situations. we recommend that external RC circuits be used to achieve longer POR delay times (Figure8-10). The on-chip POR circuit holds the chip in reset until VDD has reached a high enough level for proper opera- Note: When the device starts normal operation tion. To take advantage of the internal POR, program (exits the reset condition), device operating the GP3/MCLR/VPP pin as MCLR and tie through a parameters (voltage, frequency, tempera- resistor to VDD or program the pin as GP3. An internal ture, etc.) must be meet to ensure opera- weak pull-up resistor is implemented using a transistor. tion. If these conditions are not met, the Refer to Table11-1 for the pull-up resistor ranges. This device must be held in reset until the oper- will eliminate external RC components usually needed ating conditions are met. to create a Power-on Reset. A maximum rise time for For additional information refer to Application Notes VDD is specified. See Electrical Specifications for “Power-Up Considerations” - AN522 and “Power-up details. Trouble Shooting” - AN607. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating parameters are met. A simplified block diagram of the on-chip Power-On Reset circuit is shown in Figure8-8. DS40139E-page 40 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-Up Detect VDD POR (Power-On Reset) Pin Change Wake-up on pin change SLEEP GP3/MCLR/VPP WDT Time-out MCLRE RESET S Q 8-bit Asynch On-Chip Ripple Counter DRT OSC (Start-Up Timer) R Q CHIP RESET FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET (cid:211) 1999 Microchip Technology Inc. DS40139E-page 41

PIC12C5XX FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 ‡ VDD min. 8.5 Device Reset Timer (DRT) 8.6 Watchdog Timer (WDT) In the PIC12C5XX, DRT runs from RESET and varies The Watchdog Timer (WDT) is a free running on-chip based on oscillator selection (see Table8-5.) RC oscillator which does not require any external components. This RC oscillator is separate from the The DRT operates on an internal RC oscillator. The external RC oscillator of the GP5/OSC1/CLKIN pin processor is kept in RESET as long as the DRT is and the internal 4 MHz oscillator. That means that the active. The DRT delay allows VDD to rise above VDD WDT will run even if the main processor clock has min., and for the oscillator to stabilize. been stopped, for example, by execution of a SLEEP Oscillator circuits based on crystals or ceramic instruction. During normal operation or SLEEP, a WDT resonators require a certain time after power-up to reset or wake-up reset generates a device RESET. establish a stable oscillation. The on-chip DRT keeps The TO bit (STATUS<4>) will be cleared upon a the device in a RESET condition for approximately 18 Watchdog Timer reset. ms after MCLR has reached a logic high (VIHMCLR) level. Thus, programming GP3/MCLR/VPP as MCLR The WDT can be permanently disabled by and using an external RC network connected to the programming the configuration bit WDTE as a ’0’ MCLR input is not required in most cases, allowing for (Section8.1). Refer to the PIC12C5XX Programming savings in cost-sensitive and/or space restricted Specifications to determine how to access the applications, as well as allowing the use of the GP3/ configuration word. MCLR/VPP pin as a general purpose input. TABLE 8-5: DRT (DEVICE RESET TIMER The Device Reset time delay will vary from chip to chip PERIOD) due to VDD, temperature, and process variation. See AC parameters for details. Oscillator Subsequent POR Reset The DRT will also be triggered upon a Watchdog Configuration Resets Timer time-out. This is particularly important for IntRC & 18 ms (typical) 300 µs (typical) applications using the WDT to wake from SLEEP ExtRC mode automatically. XT & LP 18 ms (typical) 18 ms (typical) DS40139E-page 42 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 8.6.1 WDT PERIOD 8.6.2 WDT PROGRAMMING CONSIDERATIONS The WDT has a nominal time-out period of 18 ms, The CLRWDT instruction clears the WDT and the (with no prescaler). If a longer time-out period is postscaler, if assigned to the WDT, and prevents it desired, a prescaler with a division ratio of up to 1:128 from timing out and generating a device RESET. can be assigned to the WDT (under software control) The SLEEP instruction resets the WDT and the by writing to the OPTION register. Thus, a time-out postscaler, if assigned to the WDT. This gives the period of a nominal 2.3 seconds can be realized. maximum SLEEP time before a WDT wake-up reset. These periods vary with temperature, VDD and part-to- part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs. FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure8-5) 0 Watchdog 1 M PPoosststsccaalelerr U Timer X 8 - to - 1 MUX PS2:PS0 WDT Enable PSA Configuration Bit To Timer0 (Figure8-4) 0 1 MUX PSA Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register. WDT Time-out TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Power-On All Other Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Resets N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as ’0’, u = unchanged (cid:211) 1999 Microchip Technology Inc. DS40139E-page 43

PIC12C5XX 8.7 Time-Out Sequence, Power Down, FIGURE 8-14: BROWN-OUT PROTECTION and Wake-up from SLEEP Status Bits CIRCUIT 2 (TO/PD/GPWUF) VDD The TO, PD, and GPWUF bits in the STATUS register VDD can be tested to determine if a RESET condition has VDD been caused by a power-up condition, a MCLR or R1 Watchdog Timer (WDT) reset. Q1 MCLR TABLE 8-7: TO/PD/GPWUF STATUS R2 AFTER RESET 40k* PIC12C5XX GPWUF TO PD RESET caused by 0 0 0 WDT wake-up from SLEEP 0 0 u WDT time-out (not from This brown-out circuit is less expensive, although SLEEP) less accurate. Transistor Q1 turns off when VDD 0 1 0 MCLR wake-up from is below a certain level such that: SLEEP R1 0 1 1 Power-up VDD • = 0.7V R1 + R2 0 u u MCLR not during SLEEP 1 1 0 Wake-up from SLEEP on *Refer to Figure8-7 and Table11-1 for internal pin change weak pull-up on MCLR. Legend:u = unchanged Note1: The TO, PD, and GPWUF bits maintain FIGURE 8-15: BROWN-OUT PROTECTION their status (u) until a reset occurs. A low- CIRCUIT 3 pulse on the MCLR input does not change the TO, PD, and GPWUF status bits. VDD 8.8 Reset on Brown-Out MCP809 bypass VDD Vss capacitor A brown-out is a condition where device power (VDD) VDD dips below its minimum value, but not to zero, and then RST recovers. The device should be reset in the event of a MCLR brown-out. PIC12C5XX To reset PIC12C5XX devices when a brown-out occurs, external brown-out protection circuits may be This brown-out protection circuit employs built, as shown in Figure8-13 , Figure8-14 and Microchip Technology’s MCP809 microcontroller Figure8-15 supervisor. The MCP8XX and MCP1XX family of FIGURE 8-13: BROWN-OUT PROTECTION supervisors provide push-pull and open collector CIRCUIT 1 outputs with both high and low active reset pins. There are 7 different trip point selections to accomodate 5V and 3V systems. VDD VDD VDD 33k Q1 10k MCLR 40k* PIC12C5XX This circuit will activate reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). *Refer to Figure8-7 and Table11-1 for internal weak pull-up on MCLR. DS40139E-page 44 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 8.9 Power-Down Mode (SLEEP) 8.10 Program Verification/Code Protection A device may be powered down (SLEEP) and later If the code protection bit has not been programmed, powered up (Wake-up from SLEEP). the on-chip program memory can be read out for verification purposes. 8.9.1 SLEEP The first 64 locations can be read by the PIC12C5XX The Power-Down mode is entered by executing a regardless of the code protection bit setting. SLEEP instruction. The last memory location cannot be read if code pro- If enabled, the Watchdog Timer will be cleared but tection is enabled on the PIC12C508/509. keeps running, the TO bit (STATUS<4>) is set, the PD The last memory location can be read regardless of the bit (STATUS<3>) is cleared and the oscillator driver is code protection bit setting on the PIC12C508A/509A/ turned off. The I/O ports maintain the status they had CR509A/CE518/CE519. before the SLEEP instruction was executed (driving high, driving low, or hi-impedance). 8.11 ID Locations It should be noted that a RESET generated by a WDT Four memory locations are designated as ID locations time-out does not drive the MCLR pin low. where the user can store checksum or other code- For lowest current consumption while powered down, identification numbers. These locations are not the T0CKI input should be at VDD or VSS and the GP3/ accessible during normal execution but are readable MCLR/VPP pin must be at a logic high level (VIHMC) if and writable during program/verify. MCLR is enabled. Use only the lower 4 bits of the ID locations and 8.9.2 WAKE-UP FROM SLEEP always program the upper 8 bits as ’0’s. The device can wake-up from SLEEP through one of the following events: 1. An external reset input on GP3/MCLR/VPP pin, when configured as MCLR. 2. A Watchdog Timer time-out reset (if WDT was enabled). 3. A change on input pin GP0, GP1, or GP3/ MCLR/VPP when wake-up on change is enabled. These events cause a device reset. The TO, PD, and GPWUF bits can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The GPWUF bit indicates a change in state while in SLEEP at pins GP0, GP1, or GP3 (since the last time there was a file or bit operation on GP port). Caution: Right before entering SLEEP, read the input pins. When in SLEEP, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering SLEEP, a wake up will occur immediately even if no pins change while in SLEEP mode. The WDT is cleared when the device wakes from sleep, regardless of the wake-up source. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 45

PIC12C5XX 8.12 In-Circuit Serial Programming FIGURE 8-16: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING The PIC12C5XX microcontrollers with EPROM pro- CONNECTION gram memory can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, To Normal ground, and the programming voltage. This allows cus- Connections External tomers to manufacture boards with unprogrammed Connector PIC12C5XX devices, and then program the microcontroller just Signals before shipping the product. This also allows the most +5V VDD recent firmware or a custom firmware to be pro- 0V VSS grammed. VPP MCLR/VPP The device is placed into a program/verify mode by holding the GP1 and GP0 pins low while raising the CLK GP1 MCLR (VPP) pin from VIL to VIHH (see programming specification). GP1 becomes the programming clock Data I/O GP0 and GP0 becomes the programming data. Both GP1 and GP0 are Schmitt Trigger inputs in this mode. VDD After reset, a 6-bit command is then supplied to the device. Depending on the command, 14-bits of pro- To Normal gram data are then supplied to or from the device, Connections depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC12C5XX Programming Specifications. A typical in-circuit serial programming connection is shown in Figure8-16. DS40139E-page 46 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 9.0 INSTRUCTION SET SUMMARY All instructions are executed within a single instruction cycle, unless a conditional test is true or the program Each PIC12C5XX instruction is a 12-bit word divided counter is changed as a result of an instruction. In this into an OPCODE, which specifies the instruction type, case, the execution takes two instruction cycles. One and one or more operands which further specify the instruction cycle consists of four oscillator periods. operation of the instruction. The PIC12C5XX Thus, for an oscillator frequency of 4 MHz, the normal instruction set summary in Table9-2 groups the instruction execution time is 1 m s. If a conditional test is instructions into byte-oriented, bit-oriented, and literal true or the program counter is changed as a result of and control operations. Table9-1 shows the opcode an instruction, the instruction execution time is 2 m s. field descriptions. Figure9-1 shows the three general formats that the For byte-oriented instructions, ’f’ represents a file instructions can have. All examples in the figure use the register designator and ’d’ represents a destination following format to represent a hexadecimal number: designator. The file register designator is used to specify which one of the 32 file registers is to be used 0xhhh by the instruction. where ’h’ signifies a hexadecimal digit. The destination designator specifies where the result FIGURE 9-1: GENERAL FORMAT FOR of the operation is to be placed. If ’d’ is ’0’, the result is INSTRUCTIONS placed in the W register. If ’d’ is ’1’, the result is placed in the file register specified in the instruction. Byte-oriented file register operations For bit-oriented instructions, ’b’ represents a bit field 11 6 5 4 0 designator which selects the number of the bit affected OPCODE d f (FILE #) by the operation, while ’f’ represents the number of the d = 0 for destination W file in which the bit is located. d = 1 for destination f f = 5-bit file register address For literal and control operations, ’k’ represents an 8or 9-bit constant or literal value. Bit-oriented file register operations 11 8 7 5 4 0 TABLE 9-1: OPCODE FIELD OPCODE b (BIT #) f (FILE #) DESCRIPTIONS b = 3-bit bit address Field Description f = 5-bit file register address f Register file address (0x00 to 0x7F) Literal and control operations (except GOTO) W Working register (accumulator) 11 8 7 0 b Bit address within an 8-bit file register OPCODE k (literal) k Literal field, constant data or label k = 8-bit immediate value Don’t care location (= 0 or 1) x The assembler will generate code with x = 0. It is Literal and control operations - GOTO instruction the recommended form of use for compatibility with all Microchip software tools. 11 9 8 0 OPCODE k (literal) Destination select; d = 0 (store result in W) d k = 9-bit immediate value d = 1 (store result in file register ’f’) Default is d = 1 label Label name TOS Top of Stack PC Program Counter WDT Watchdog Timer Counter TO Time-Out bit PD Power-Down bit Destination, either the W register or the specified dest register file location [ ] Options ( ) Contents fi Assigned to < > Register bit field ˛ In the set of italics User defined term (font is courier) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 47

PIC12C5XX TABLE 9-2: INSTRUCTION SET SUMMARY 12-Bit Opcode Mnemonic, Status Operands Description Cycles MSb LSb Affected Notes ADDWF f,d Add W and f 1 0001 11df ffff C,DC,Z 1,2,4 ANDWF f,d AND W with f 1 0001 01df ffff Z 2,4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW – Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2,4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2,4 INCF f, d Increment f 1 0010 10df ffff Z 2,4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2,4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2,4 MOVF f, d Move f 1 0010 00df ffff Z 2,4 MOVWF f Move W to f 1 0000 001f ffff None 1,4 NOP – No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2,4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2,4 SUBWF f, d Subtract W from f 1 0000 10df ffff C,DC,Z 1,2,4 SWAPF f, d Swap f 1 0011 10df ffff None 2,4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2,4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2,4 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1 (2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call subroutine 2 1001 kkkk kkkk None 1 CLRWDT k Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION – Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk None SLEEP – Go into standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z Note1: The 9th bit of the program counter will be forced to a ’0’ by any instruction that writes to the PC except for GOTO. (Section4.6) 2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ’0’. 3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of GPIO. A ’1’ forces the pin to a hi-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS40139E-page 48 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX ADDWF Add W and f ANDWF AND W with f Syntax: [ label ] ADDWF f,d Syntax: [ label ] ANDWF f,d Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 d ˛[0,1] d ˛[0,1] Operation: (W) + (f) fi (dest) Operation: (W) .AND. (f) fi (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: 0001 11df ffff Encoding: 0001 01df ffff Description: Add the contents of the W register and Description: The contents of the W register are register ’f’. If ’d’ is 0 the result is stored AND’ed with register 'f'. If 'd' is 0 the in the W register. If ’d’ is ’1’ the result is result is stored in the W register. If 'd' is stored back in register ’f’. '1' the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: ADDWF FSR, 0 Example: ANDWF FSR, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 FSR = 0xC2 FSR = 0xC2 After Instruction After Instruction W = 0xD9 W = 0x17 FSR = 0xC2 FSR = 0x02 ANDLW And literal with W BCF Bit Clear f Syntax: [ label ] ANDLW k Syntax: [ label ] BCF f,b Operands: 0 £ k £ 255 Operands: 0 £ f £ 31 Operation: (W).AND. (k) fi (W) 0 £ b £ 7 Operation: 0 fi (f<b>) Status Affected: Z Status Affected: None Encoding: 1110 kkkk kkkk Encoding: 0100 bbbf ffff Description: The contents of the W register are AND’ed with the eight-bit literal 'k'. The Description: Bit 'b' in register 'f' is cleared. result is placed in the W register. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example: BCF FLAG_REG, 7 Example: ANDLW 0x5F Before Instruction Before Instruction FLAG_REG = 0xC7 W = 0xA3 After Instruction After Instruction FLAG_REG = 0x47 W = 0x03 (cid:211) 1999 Microchip Technology Inc. DS40139E-page 49

PIC12C5XX BSF Bit Set f BTFSS Bit Test f, Skip if Set Syntax: [ label ] BSF f,b Syntax: [ label ] BTFSS f,b Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 0 £ b £ 7 0 £ b < 7 Operation: 1 fi (f<b>) Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 0101 bbbf ffff Encoding: 0111 bbbf ffff Description: Bit ’b’ in register ’f’ is set. Description: If bit ’b’ in register ’f’ is ’1’ then the next instruction is skipped. Words: 1 If bit ’b’ is ’1’, then the next instruction Cycles: 1 fetched during the current instruction Example: BSF FLAG_REG, 7 execution, is discarded and an NOP is executed instead, making this a 2 cycle Before Instruction instruction. FLAG_REG = 0x0A Words: 1 After Instruction Cycles: 1(2) FLAG_REG = 0x8A Example: HERE BTFSS FLAG,1 FALSE GOTO PROCESS_CODE TRUE • BTFSC Bit Test f, Skip if Clear • Syntax: [ label ] BTFSC f,b • Operands: 0 £ f £ 31 Before Instruction 0 £ b £ 7 PC = address (HERE) Operation: skip if (f<b>) = 0 After Instruction If FLAG<1> = 0, Status Affected: None PC = address (FALSE); Encoding: 0110 bbbf ffff if FLAG<1> = 1, PC = address (TRUE) Description: If bit ’b’ in register ’f’ is 0 then the next instruction is skipped. If bit ’b’ is 0 then the next instruction fetched during the current instruction execution is discarded, and an NOP is executed instead, making this a 2 cycle instruction. Words: 1 Cycles: 1(2) Example: HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address (HERE) After Instruction if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address(FALSE) DS40139E-page 50 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX CALL Subroutine Call CLRW Clear W Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 £ k £ 255 Operands: None Operation: (PC) + 1fi Top of Stack; Operation: 00h fi (W); k fi PC<7:0>; 1 fi Z (STATUS<6:5>) fi PC<10:9>; Status Affected: Z 0 fi PC<8> Encoding: 0000 0100 0000 Status Affected: None Description: The W register is cleared. Zero bit (Z) Encoding: 1001 kkkk kkkk is set. Description: Subroutine call. First, return address Words: 1 (PC+1) is pushed onto the stack. The eight bit immediate address is loaded Cycles: 1 into PC bits <7:0>. The upper bits Example: CLRW PC<10:9> are loaded from STA- TUS<6:5>, PC<8> is cleared. CALL is Before Instruction a two cycle instruction. W = 0x5A Words: 1 After Instruction W = 0x00 Cycles: 2 Z = 1 Example: HERE CALL THERE Before Instruction PC = address (HERE) CLRWDT Clear Watchdog Timer After Instruction Syntax: [ label ] CLRWDT PC = address (THERE) Operands: None TOS= address (HERE + 1) Operation: 00h fi WDT; 0 fi WDT prescaler (if assigned); 1 fi TO; CLRF Clear f 1 fi PD Syntax: [ label ] CLRF f Status Affected: TO, PD Operands: 0 £ f £ 31 Encoding: 0000 0000 0100 Operation: 00h fi (f); 1 fi Z Description: The CLRWDT instruction resets the WDT. It also resets the prescaler, if the Status Affected: Z prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are Encoding: 0000 011f ffff set. Description: The contents of register ’f’ are cleared Words: 1 and the Z bit is set. Cycles: 1 Words: 1 Example: CLRWDT Cycles: 1 Before Instruction Example: CLRF FLAG_REG WDT counter = ? Before Instruction After Instruction FLAG_REG = 0x5A WDT counter = 0x00 After Instruction WDT prescale= 0 FLAG_REG = 0x00 TO = 1 Z = 1 PD = 1 (cid:211) 1999 Microchip Technology Inc. DS40139E-page 51

PIC12C5XX COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 d ˛ [0,1] d ˛ [0,1] Operation: (f) fi (dest) Operation: (f) – 1 fi d; skip if result = 0 Status Affected: Z Status Affected: None Encoding: 0010 01df ffff Encoding: 0010 11df ffff Description: The contents of register ’f’ are comple- Description: The contents of register ’f’ are decre- mented. If ’d’ is 0 the result is stored in mented. If ’d’ is 0 the result is placed in the W register. If ’d’ is 1 the result is the W register. If ’d’ is 1 the result is stored back in register ’f’. placed back in register ’f’. Words: 1 If the result is 0, the next instruction, which is already fetched, is discarded Cycles: 1 and an NOP is executed instead mak- Example: COMF REG1,0 ing it a two cycle instruction. Before Instruction Words: 1 REG1 = 0x13 Cycles: 1(2) After Instruction Example: HERE DECFSZ CNT, 1 REG1 = 0x13 GOTO LOOP W = 0xEC CONTINUE • • • DECF Decrement f Before Instruction Syntax: [ label ] DECF f,d PC = address (HERE) Operands: 0 £ f £ 31 After Instruction d ˛ [0,1] CNT = CNT - 1; if CNT = 0, Operation: (f) – 1 fi (dest) PC = address (CONTINUE); if CNT „ 0, Status Affected: Z PC = address (HERE+1) Encoding: 0000 11df ffff Description: Decrement register ’f’. If ’d’ is 0 the result is stored in the W register. If ’d’ is GOTO Unconditional Branch 1 the result is stored back in register ’f’. Syntax: [ label ] GOTO k Words: 1 Operands: 0 £ k £ 511 Cycles: 1 Operation: k fi PC<8:0>; Example: DECF CNT, 1 STATUS<6:5> fi PC<10:9> Before Instruction Status Affected: None CNT = 0x01 Encoding: 101k kkkk kkkk Z = 0 After Instruction Description: GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC CNT = 0x00 bits <8:0>. The upper bits of PC are Z = 1 loaded from STATUS<6:5>. GOTO is a two cycle instruction. Words: 1 Cycles: 2 Example: GOTO THERE After Instruction PC = address (THERE) DS40139E-page 52 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX INCF Increment f IORLW Inclusive OR literal with W Syntax: [ label ] INCF f,d Syntax: [ label ] IORLW k Operands: 0 £ f £ 31 Operands: 0 £ k £ 255 d ˛ [0,1] Operation: (W) .OR. (k) fi (W) Operation: (f) + 1 fi (dest) Status Affected: Z Status Affected: Z Encoding: 1101 kkkk kkkk Encoding: 0010 10df ffff Description: The contents of the W register are Description: The contents of register ’f’ are incre- OR’ed with the eight bit literal 'k'. The mented. If ’d’ is 0 the result is placed in result is placed in the W register. the W register. If ’d’ is 1 the result is Words: 1 placed back in register ’f’. Cycles: 1 Words: 1 Example: IORLW 0x35 Cycles: 1 Before Instruction Example: INCF CNT, 1 W = 0x9A Before Instruction After Instruction CNT = 0xFF W = 0xBF Z = 0 Z = 0 After Instruction CNT = 0x00 Z = 1 IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d INCFSZ Increment f, Skip if 0 Operands: 0 £ f £ 31 d ˛ [0,1] Syntax: [ label ] INCFSZ f,d Operands: 0 £ f £ 31 Operation: (W).OR. (f) fi (dest) d ˛ [0,1] Status Affected: Z Operation: (f) + 1 fi (dest), skip if result = 0 Encoding: 0001 00df ffff Status Affected: None Description: Inclusive OR the W register with regis- ter 'f'. If 'd' is 0 the result is placed in Encoding: 0011 11df ffff the W register. If 'd' is 1 the result is Description: The contents of register ’f’ are incre- placed back in register 'f'. mented. If ’d’ is 0 the result is placed in Words: 1 the W register. If ’d’ is 1 the result is placed back in register ’f’. Cycles: 1 If the result is 0, then the next instruc- Example: IORWF RESULT, 0 tion, which is already fetched, is dis- Before Instruction carded and an NOP is executed instead making it a two cycle instruc- RESULT = 0x13 tion. W = 0x91 Words: 1 After Instruction RESULT = 0x13 Cycles: 1(2) W = 0x93 Example: HERE INCFSZ CNT, 1 Z = 0 GOTO LOOP CONTINUE • • • Before Instruction PC = address (HERE) After Instruction CNT = CNT + 1; if CNT = 0, PC = address (CONTINUE); if CNT „ 0, PC = address (HERE +1) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 53

PIC12C5XX MOVF Move f MOVWF Move W to f Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f Operands: 0 £ f £ 31 Operands: 0 £ f £ 31 d ˛ [0,1] Operation: (W) fi (f) Operation: (f) fi (dest) Status Affected: None Status Affected: Z Encoding: 0000 001f ffff Encoding: 0010 00df ffff Description: Move data from the W register to regis- Description: The contents of register ’f’ is moved to ter 'f'. destination ’d’. If ’d’ is 0, destination is Words: 1 the W register. If ’d’ is 1, the destination is file register ’f’. ’d’ is 1 is useful to test Cycles: 1 a file register since status flag Z is Example: MOVWF TEMP_REG affected. Before Instruction Words: 1 TEMP_REG = 0xFF Cycles: 1 W = 0x4F Example: MOVF FSR, 0 After Instruction TEMP_REG = 0x4F After Instruction W = 0x4F W = value in FSR register NOP No Operation MOVLW Move Literal to W Syntax: [ label ] NOP Syntax: [ label ] MOVLW k Operands: None Operands: 0 £ k £ 255 Operation: No operation Operation: k fi (W) Status Affected: None Status Affected: None Encoding: 0000 0000 0000 Encoding: 1100 kkkk kkkk Description: No operation. Description: The eight bit literal ’k’ is loaded into the Words: 1 W register. The don’t cares will assem- Cycles: 1 ble as 0s. Example: NOP Words: 1 Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A DS40139E-page 54 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX OPTION Load OPTION Register RLF Rotate Left f through Carry Syntax: [ label ] OPTION Syntax: [ label ] RLF f,d Operands: None Operands: 0 £ f £ 31 Operation: (W) fi OPTION d ˛ [0,1] Status Affected: None Operation: See description below Encoding: 0000 0000 0010 Status Affected: C Description: The content of the W register is loaded Encoding: 0011 01df ffff into the OPTION register. Description: The contents of register ’f’ are rotated Words: 1 one bit to the left through the Carry Cycles: 1 Flag. If ’d’ is 0 the result is placed in the W register. If ’d’ is 1 the result is stored Example OPTION back in register ’f’. Before Instruction W = 0x07 C register ’f’ After Instruction Words: 1 OPTION = 0x07 Cycles: 1 Example: RLF REG1,0 RETLW Return with Literal in W Before Instruction Syntax: [ label ] RETLW k REG1 = 1110 0110 Operands: 0 £ k £ 255 C = 0 Operation: k fi (W); After Instruction TOS fi PC REG1 = 1110 0110 W = 1100 1100 Status Affected: None C = 1 Encoding: 1000 kkkk kkkk Description: The W register is loaded with the eight RRF Rotate Right f through Carry bit literal ’k’. The program counter is loaded from the top of the stack (the Syntax: [ label ] RRF f,d return address). This is a two cycle Operands: 0 £ f £ 31 instruction. d ˛ [0,1] Words: 1 Operation: See description below Cycles: 2 Status Affected: C Example: CALL TABLE ;W contains Encoding: 0011 00df ffff ;table offset ;value. Description: The contents of register ’f’ are rotated • ;W now has table one bit to the right through the Carry • ;value. Flag. If ’d’ is 0 the result is placed in the • W register. If ’d’ is 1 the result is placed TABLE ADDWF PC ;W = offset back in register ’f’. RETLW k1 ;Begin table RETLW k2 ; C register ’f’ • • Words: 1 • Cycles: 1 RETLW kn ; End of table Example: RRF REG1,0 Before Instruction W = 0x07 Before Instruction After Instruction REG1 = 1110 0110 C = 0 W = value of k8 After Instruction REG1 = 1110 0110 W = 0111 0011 C = 0 (cid:211) 1999 Microchip Technology Inc. DS40139E-page 55

PIC12C5XX SLEEP Enter SLEEP Mode SUBWF Subtract W from f Syntax: [label] SLEEP Syntax: [label] SUBWF f,d Operands: None Operands: 0 £ f £ 31 Operation: 00h fi WDT; d ˛ [0,1] 0 fi WDT prescaler; Operation: (f) – (W) fi( dest) 1 fi TO; Status Affected: C, DC, Z 0 fi PD Encoding: 0000 10df ffff Status Affected: TO, PD, GPWUF Description: Subtract (2’s complement method) the Encoding: 0000 0000 0011 W register from register 'f'. If 'd' is 0 the Description: Time-out status bit (TO) is set. The result is stored in the W register. If 'd' is power down status bit (PD) is cleared. 1 the result is stored back in register 'f'. GPWUF is unaffected. Words: 1 The WDT and its prescaler are Cycles: 1 cleared. Example 1: SUBWF REG1, 1 The processor is put into SLEEP mode with the oscillator stopped. See sec- Before Instruction tion on SLEEP for more details. REG1 = 3 Words: 1 W = 2 C = ? Cycles: 1 After Instruction Example: SLEEP REG1 = 1 W = 2 C = 1 ; result is positive Example 2: Before Instruction REG1 = 2 W = 2 C = ? After Instruction REG1 = 0 W = 2 C = 1 ; result is zero Example 3: Before Instruction REG1 = 1 W = 2 C = ? After Instruction REG1 = FF W = 2 C = 0 ; result is negative DS40139E-page 56 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [label] XORLW k Operands: 0 £ f £ 31 Operands: 0 £ k £ 255 d ˛ [0,1] Operation: (W) .XOR. k fi ( W) Operation: (f<3:0>) fi (dest<7:4>); (f<7:4>) fi (dest<3:0>) Status Affected: Z Encoding: 1111 kkkk kkkk Status Affected: None Description: The contents of the W register are Encoding: 0011 10df ffff XOR’ed with the eight bit literal 'k'. The Description: The upper and lower nibbles of register result is placed in the W register. ’f’ are exchanged. If ’d’ is 0 the result is Words: 1 placed in W register. If ’d’ is 1 the result is placed in register ’f’. Cycles: 1 Words: 1 Example: XORLW 0xAF Cycles: 1 Before Instruction W = 0xB5 Example SWAPF REG1, 0 After Instruction Before Instruction W = 0x1A REG1 = 0xA5 After Instruction REG1 = 0xA5 XORWF Exclusive OR W with f W = 0X5A Syntax: [ label ] XORWF f,d Operands: 0 £ f £ 31 TRIS Load TRIS Register d ˛ [0,1] Syntax: [ label ] TRIS f Operation: (W) .XOR. (f) fi( dest) Operands: f = 6 Status Affected: Z Operation: (W) fi TRIS register f Encoding: 0001 10df ffff Status Affected: None Description: Exclusive OR the contents of the W Encoding: 0000 0000 0fff register with register 'f'. If 'd' is 0 the Description: TRIS register ’f’ (f = 6) is loaded with the result is stored in the W register. If 'd' is contents of the W register 1 the result is stored back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example TRIS GPIO Example XORWF REG,1 Before Instruction Before Instruction W = 0XA5 REG = 0xAF After Instruction W = 0xB5 TRIS = 0XA5 After Instruction Note: f = 6 for PIC12C5XX only. REG = 0x1A W = 0xB5 (cid:211) 1999 Microchip Technology Inc. DS40139E-page 57

PIC12C5XX NOTES: DS40139E-page 58 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 10.0 DEVELOPMENT SUPPORT 10.3 ICEPIC: Low-Cost PICmicro(cid:226) In-Circuit Emulator 10.1 Development Tools ICEPIC is a low-cost in-circuit emulator solution for the The PICmicro(cid:226) microcontrollers are supported with a Microchip PIC12CXXX, PIC16C5X and PIC16CXXX full range of hardware and software development tools: families of 8-bit OTP microcontrollers. • MPLAB™-ICE Real-Time In-Circuit Emulator ICEPIC is designed to operate on PC-compatible • ICEPIC(cid:228) Low-Cost PIC16C5X and PIC16CXXX machines ranging from 386 through Pentium(cid:228) based In-Circuit Emulator machines under Windows 3.x, Windows 95, or Win- • PRO MATE(cid:226) II Universal Programmer dows NT environment. ICEPIC features real time, non- (cid:226) intrusive emulation. • PICSTART Plus Entry-Level Prototype Programmer 10.4 PRO MATE II: Universal Programmer • SIMICE • PICDEM-1 Low-Cost Demonstration Board The PRO MATE II Universal Programmer is a full-fea- tured programmer capable of operating in stand-alone • PICDEM-2 Low-Cost Demonstration Board mode as well as PC-hosted mode. PRO MATE II is CE • PICDEM-3 Low-Cost Demonstration Board compliant. • MPASM Assembler The PRO MATE II has programmable VDD and VPP • MPLAB(cid:228) SIM Software Simulator supplies which allows it to verify programmed memory • MPLAB-C17 (C Compiler) at VDD min and VDD max for maximum reliability. It has • Fuzzy Logic Development System an LCD display for displaying error messages, keys to (fuzzyTECH(cid:226) - MP) enter commands and a modular detachable socket • KEELOQ® Evaluation Kits and Programmer assembly to support various package types. In stand- alone mode the PRO MATE II can read, verify or pro- 10.2 MPLAB-ICE: High Performance gram PIC12CXXX, PIC14C000, PIC16C5X, Universal In-Circuit Emulator with PIC16CXXX and PIC17CXX devices. It can also set MPLAB IDE configuration and code-protect bits in this mode. The MPLAB-ICE Universal In-Circuit Emulator is 10.5 PICSTART Plus Entry Level intended to provide the product development engineer Development System with a complete microcontroller design tool set for PICmicro(cid:226) microcontrollers (MCUs). MPLAB-ICE is The PICSTART programmer is an easy-to-use, low- supplied with the MPLAB Integrated Development cost prototype programmer. It connects to the PC via Environment (IDE), which allows editing, “make” and one of the COM (RS-232) ports. MPLAB Integrated download, and source debugging from a single envi- Development Environment software makes using the ronment. programmer simple and efficient. PICSTART Plus is not recommended for production programming. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- PICSTART Plus supports all PIC12CXXX, PIC14C000, cessors. The universal architecture of the MPLAB-ICE PIC16C5X, PIC16CXXX and PIC17CXX devices with allows expansion to support all new Microchip micro- up to 40 pins. Larger pin count devices such as the controllers. PIC16C923, PIC16C924 and PIC17C756 may be sup- ported with an adapter socket. PICSTART Plus is CE The MPLAB-ICE Emulator System has been designed compliant. as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. The PC compatible 386 (and higher) (cid:226) machine platform and Microsoft Windows 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. MPLAB-ICE is available in two versions. MPLAB-ICE1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor mod- ules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across (cid:226) the entire operating speed range of the PICmicro MCU. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 59

PIC12C5XX 10.6 SIMICE Entry-Level Hardware 10.8 PICDEM-2 Low-Cost PIC16CXX Simulator Demonstration Board SIMICE is an entry-level hardware development sys- The PICDEM-2 is a simple demonstration board that tem designed to operate in a PC-based environment supports the PIC16C62, PIC16C64, PIC16C65, with Microchip’s simulator MPLAB™-SIM. Both SIM- PIC16C73 and PIC16C74 microcontrollers. All the ICE and MPLAB-SIM run under Microchip Technol- necessary hardware and software is included to ogy’s MPLAB Integrated Development Environment run the basic demonstration programs. The user (IDE) software. Specifically, SIMICE provides hardware can program the sample microcontrollers provided simulation for Microchip’s PIC12C5XX, PIC12CE5XX, with the PICDEM-2 board, on a PRO MATE II pro- and PIC16C5X families of PICmicro(cid:226) 8-bit microcon- grammer or PICSTART-Plus, and easily test firmware. trollers. SIMICE works in conjunction with MPLAB-SIM The MPLAB-ICE emulator may also be used with the to provide non-real-time I/O port emulation. SIMICE PICDEM-2 board to test firmware. Additional prototype enables a developer to run simulator code for driving area has been provided to the user for adding addi- the target system. In addition, the target system can tional hardware and connecting it to the microcontroller provide input to the simulator code. This capability socket(s). Some of the features include a RS-232 inter- allows for simple and interactive debugging without face, push-button switches, a potentiometer for simu- having to manually generate MPLAB-SIM stimulus lated analog input, a Serial EEPROM to demonstrate files. SIMICE is a valuable debugging tool for entry- usage of the I2C bus and separate headers for connec- level system development. tion to an LCD module and a keypad. 10.7 PICDEM-1 Low-Cost PICmicro(cid:226) 10.9 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board Demonstration Board The PICDEM-1 is a simple board which demonstrates The PICDEM-3 is a simple demonstration board that the capabilities of several of Microchip’s microcontrol- supports the PIC16C923 and PIC16C924 in the PLCC lers. The microcontrollers supported are: PIC16C5X package. It will also support future 44-pin PLCC (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, microcontrollers with a LCD Module. All the neces- PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and sary hardware and software is included to run the PIC17C44. All necessary hardware and software is basic demonstration programs. The user can pro- included to run basic demo programs. The users can gram the sample microcontrollers provided with program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II program- the PICDEM-1 board, on a PROMATE II or mer or PICSTART Plus with an adapter socket, and PICSTART-Plus programmer, and easily test firm- easily test firmware. The MPLAB-ICE emulator may ware. The user can also connect the PICDEM-1 also be used with the PICDEM-3 board to test firm- board to the MPLAB-ICE emulator and download the ware. Additional prototype area has been provided to firmware to the emulator for testing. Additional proto- the user for adding hardware and connecting it to the type area is available for the user to build some addi- microcontroller socket(s). Some of the features include tional hardware and connect it to the microcontroller an RS-232 interface, push-button switches, a potenti- socket(s). Some of the features include an RS-232 ometer for simulated analog input, a thermistor and interface, a potentiometer for simulated analog input, separate headers for connection to an external LCD push-button switches and eight LEDs connected to module and a keypad. Also provided on the PICDEM-3 PORTB. board is an LCD panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an addi- tional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the LCD signals. DS40139E-page 60 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 10.10 MPLAB Integrated Development 10.12 Software Simulator (MPLAB-SIM) Environment Software The MPLAB-SIM Software Simulator allows code The MPLAB IDE Software brings an ease of software development in a PC host environment. It allows the development previously unseen in the 8-bit microcon- user to simulate the PICmicro(cid:226) series microcontrollers troller market. MPLAB is a windows based application on an instruction level. On any given instruction, the which contains: user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ • A full featured editor output radix can be set by the user and the execution • Three operating modes can be performed in; single step, execute until break, or - editor in a trace mode. - emulator - simulator MPLAB-SIM fully supports symbolic debugging using • A project manager MPLAB-C17 and MPASM. The Software Simulator • Customizable tool bar and key mapping offers the low cost flexibility to develop and debug code • A status bar with project information outside of the laboratory environment making it an • Extensive on-line help excellent multi-project software development tool. MPLAB allows you to: 10.13 MPLAB-C17 Compiler • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download The MPLAB-C17 Code Development System is a to PICmicro(cid:226) tools (automatically updates all complete ANSI ‘C’ compiler and integrated develop- project information) ment environment for Microchip’s PIC17CXXX family of • Debug using: microcontrollers. The compiler provides powerful inte- - source files gration capabilities and ease of use not found with - absolute listing file other compilers. The ability to use MPLAB with Microchip’s simulator For easier source level debugging, the compiler pro- allows a consistent platform and the ability to easily vides symbol information that is compatible with the switch from the low cost simulator to the full featured MPLAB IDE memory display. emulator with minimal retraining due to development 10.14 Fuzzy Logic Development System tools. (fuzzyTECH-MP) 10.11 Assembler (MPASM) fuzzyTECH-MP fuzzy logic development tool is avail- The MPASM Universal Macro Assembler is a PC- able in two versions - a low cost introductory version, hosted symbolic assembler. It supports all microcon- MPExplorer, for designers to gain a comprehensive troller series including the PIC12C5XX, PIC14000, working knowledge of fuzzy logic system design; and a PIC16C5X, PIC16CXXX, and PIC17CXX families. full-featured version, fuzzyTECH-MP, Edition for imple- menting more complex systems. MPASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. Both versions include Microchip’s fuzzyLAB(cid:228) demon- It generates various object code formats to support stration board for hands-on experience with fuzzy logic Microchip's development tools as well as third party systems implementation. programmers. 10.15 SEEVAL(cid:226) Evaluation and MPASM allows full symbolic debugging from MPLAB- Programming System ICE, Microchip’s Universal Emulator System. MPASM has the following features to assist in develop- The SEEVAL SEEPROM Designer’s Kit supports all ing software for specific use applications. Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or • Provides translation of Assembler source code to program special features of any Microchip SEEPROM object code for all Microchip microcontrollers. product including Smart Serials(cid:212) and secure serials. • Macro assembly capability. The Total Endurance(cid:212) Disk is included to aid in trade- • Produces all the files (Object, Listing, Symbol, and off analysis and reliability calculations. The total kit can special) required for symbolic debug with significantly reduce time-to-market and result in an Microchip’s emulator systems. optimized system. • Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support (cid:226) programming of the PICmicro . Directives are helpful in making the development of your assemble source code shorter and more maintainable. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 61

PIC12C5XX 10.16 KEELOQ(cid:226) Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS40139E-page 62 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP 001 000 S2S3S3 Æ Æ Æ Æ CCC HHH XXX CXCXCX Æ Æ Æ 453 229 X X 7 C Æ Æ Æ Æ Æ 7 1 C PI X 4 7C Æ Æ Æ Æ Æ Æ Æ 1 C PI X X 9 C Æ Æ Æ Æ Æ Æ Æ 6 1 C PI X 8 C 6 Æ Æ Æ Æ Æ Æ Æ 1 C PI X X 7 C Æ Æ Æ Æ Æ Æ Æ 6 1 C PI X 6 6C Æ Æ Æ Æ Æ Æ Æ 1 C PI X X X C Æ Æ Æ Æ Æ Æ Æ 6 1 C PI X 5 6C Æ Æ Æ Æ Æ Æ Æ Æ 1 C PI 0 0 40 Æ Æ Æ Æ Æ Æ 1 C PI X X 5 C Æ Æ Æ Æ Æ Æ 2 1 C PI MPLAB™-ICE (cid:228)ICEPIC Low-CostIn-Circuit Emulator(cid:228)MPLABIntegratedDevelopmentEnvironment(cid:228)MPLAB C17*Compiler(cid:226)fuzzyTECH-MPExplorer/EditionFuzzy LogicDev. Tool(cid:228)Total EnduranceSoftware Model(cid:226)PICSTARTPlus Low-CostUniversal Dev. Kit(cid:226)PRO MATE IIUniversalProgrammer(cid:226)KEELOQProgrammer(cid:226)SEEVALDesigners Kit SIMICE PICDEM-14A PICDEM-1 PICDEM-2 PICDEM-3®KLEEOQEvaluation Kit KL EEOQTransponder Kit stcudorP rotalumE slooT erawtfoS sremmargorP sdraoB omeD (cid:211) 1999 Microchip Technology Inc. DS40139E-page 63

PIC12C5XX NOTES: DS40139E-page 64 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 11.0 ELECTRICAL CHARACTERISTICS - PIC12C508/PIC12C509 Absolute Maximum Ratings† Ambient Temperature under bias...........................................................................................................–40°C to +125°C Storage Temperature.............................................................................................................................–65°C to +150°C Voltage on VDD with respect to VSS.................................................................................................................0 to +7.5 V Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V Voltage on all other pins with respect to VSS...............................................................................–0.6 V to (VDD + 0.6 V) Total Power Dissipation(1)....................................................................................................................................700 mW Max. Current out of VSS pin..................................................................................................................................200 mA Max. Current into VDD pin.....................................................................................................................................150 mA Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................– 20 mA Output Clamp Current, IOK (VO < 0 or VO > VDD).............................................................................................................– 20 mA Max. Output Current sunk by any I/O pin................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................25 mA Max. Output Current sourced by I/O port (GPIO).................................................................................................100 mA Max. Output Current sunk by I/O port (GPIO )......................................................................................................100 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD-VOH) x IOH} + (cid:229) (VOL x IOL) †NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 65

PIC12C5XX 11.1 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) Power Supply Pins –40(cid:176)C £ TA £ +85(cid:176)C (industrial) –40(cid:176)C £ TA £ +125(cid:176)C (extended) Parm Characteristic Sym Min Typ(1) Max Units Conditions No. D001 Supply Voltage VDD 2.5 5.5 V FOSC = DC to 4 MHz (Commercial/ Industrial) 3.0 5.5 V FOSC = DC to 4 MHz (Extended) D002 RAM Data Retention VDR 1.5* V Device in SLEEP mode Voltage(2) D003 VDD Start Voltage to VPOR VSS V See section on Power-on Reset for details ensure Power-on Reset D004 VDD Rise Rate to ensure SVDD 0.05 V/ms See section on Power-on Reset for details Power-on Reset * Supply Current(3) D010 IDD — .78 2.4 mA XT and EXTRC options (4) FOSC = 4 MHz, VDD = 5.5V D010C — 1.1 2.4 mA INTRC Option FOSC = 4 MHz, VDD = 5.5V D010A — 10 27 m A LP OPTION, Commercial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled — 14 35 m A LP OPTION, Industrial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled — 14 35 µA LP OPTION, Extended Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled Power-Down Current (5) D020 IPD — 0.25 4 m A VDD = 3.0V, Commercial WDT disabled D021 — 0.25 5 m A VDD = 3.0V, Industrial WDT disabled D021B — 2 18 m A VDD = 3.0V, Extended WDT disabled D022 D IWDT — 3.75 8 m A VDD = 3.0V, Commercial — 3.75 9 m A VDD = 3.0V, Industrial — 3.75 14 m A VDD = 3.0V, Extended * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is based on characterization results at 25(cid:176)C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. DS40139E-page 66 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 11.2 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) DC CHARACTERISTICS –40°C £ TA £ +125°C (extended) Operating voltage VDD range as described in DC spec Section11.1 and Section11.2. Param Characteristic Sym Min Typ† Max Units Conditions No. Input Low Voltage I/O ports VIL - D030 with TTL buffer VSS - 0.8V V 4.5 < VDD £ 5.5V - 0.15VDD V otherwise D031 with Schmitt Trigger buffer VSS - 0.15VDD V D032 MCLR, GP2/T0CKI (in EXTRC mode) VSS - 0.15VDD V D033 OSC1 (EXTRC) (1) VSS - 0.15VDD D033 OSC1 (in XT and LP) VSS - 0.3VDD V Note1 Input High Voltage I/O ports VIH - D040 with TTL buffer VSS 2.0V - VDD V 4.5 £ VDD £ 5.5V D040A 0.25VDD + - VDD V otherwise 0.8V D041 with Schmitt Trigger buffer 0.85VDD - VDD V For entire VDD range D042 MCLR/GP2/T0CKI 0.85VDD - VDD V D042A OSC1 (XT and LP) 0.7VDD - VDD V Note1 D043 OSC1 (in EXTRC mode) 0.85VDD - VDD V D070 GPIO weak pull-up current IPUR 50 250 400 m A VDD = 5V, VPIN = VSS Input Leakage Current (2, 3) For VDD £ 5.5V D060 I/O ports IIL -1 0.5 +1 m A Vss £ VPIN £ VDD, Pin at hi-impedance D061 MCLR, GP2/T0CKI 20 130 250 m A VPIN = VSS + 0.25V(2) 0.5 +5 m A VPIN = VDD D063 OSC1 -3 0.5 +3 m A Vss £ VPIN £ VDD, XT and LP options Output Low Voltage D080 I/O ports/CLKOUT VOL - - 0.6 V IOL = 8.7 mA, VDD = 4.5V Output High Voltage D090 I/O ports/CLKOUT (3) VOH VDD - 0.7 - - V IOH = -5.4 mA, VDD = 4.5V Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT and LP modes when external clock is used to drive OSC1. D101 All I/O pins CIO - - 50 pF † Data in “Typ” column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C5XX be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 67

PIC12C5XX TABLE 11-1: PULL-UP RESISTOR RANGES - PIC12C508/C509 VDD (Volts) Temperature ((cid:176)C) Min Typ Max Units GP0/GP1 2.5 –40 38K 42K 63K W 25 42K 48K 63K W 85 42K 49K 63K W 125 50K 55K 63K W 5.5 –40 15K 17K 20K W 25 18K 20K 23K W 85 19K 22K 25K W 125 22K 24K 28K W GP3 2.5 –40 285K 346K 417K W 25 343K 414K 532K W 85 368K 457K 532K W 125 431K 504K 593K W 5.5 –40 247K 292K 360K W 25 288K 341K 437K W 85 306K 371K 448K W 125 351K 407K 500K W * These parameters are characterized but not tested. DS40139E-page 68 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 11.3 Timing Parameter Symbology and Load Conditions - PIC12C508/C509 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 11-1: LOAD CONDITIONS - PIC12C508/C509 Pin CL = 50 pF for all pins except OSC2 CL 15 pF for OSC2 in XT or LP modes when external clock is used to drive OSC1 VSS (cid:211) 1999 Microchip Technology Inc. DS40139E-page 69

PIC12C5XX 11.4 Timing Diagrams and Specifications FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC12C508/C509 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial), –40(cid:176)C £ TA £ +85(cid:176)C (industrial), –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section11.1 Parameter Sym Characteristic Min Typ(1) Max Units Conditions No. FOSC External CLKIN Frequency(2) DC — 4 MHz XT osc mode DC — 200 kHz LP osc mode Oscillator Frequency(2) 0.1 — 4 MHz XT osc mode DC — 200 kHz LP osc mode 1 TOSC External CLKIN Period(2) 250 — — ns EXTRC osc mode 250 — — ns XT osc mode 5 — — ms LP osc mode Oscillator Period(2) 250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode 5 — — ms LP osc mode 2 Tcy Instruction Cycle Time(3) — 4/FOSC — — 3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator 2* — — ms LP oscillator 4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS40139E-page 70 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE 11-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial), –40(cid:176)C £ TA £ +85(cid:176)C (industrial), –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section10.1 Parameter Sym Characteristic Min* Typ(1) Max* Units Conditions No. Internal Calibrated RC Frequency 3.58 4.00 4.32 MHz VDD = 5.0V Internal Calibrated RC Frequency 3.50 — 4.26 MHz VDD = 2.5V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 11-3: I/O TIMING - PIC12C508/C509 Q4 Q1 Q2 Q3 OSC1 I/O Pin (input) 17 19 18 I/O Pin (output) Old Value New Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 71

PIC12C5XX TABLE 11-4: TIMING REQUIREMENTS - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) –40(cid:176)C £ TA £ +85(cid:176)C (industrial) –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section11.1 Parameter No. Sym Characteristic Min Typ(1) Max Units 17 TosH2ioV OSC1› (Q1 cycle) to Port out valid(3) — — 100* ns 18 TosH2ioI OSC1› (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1› TBD — — ns (I/O in setup time) 20 TioR Port output rise time(2, 3) — 10 25** ns 21 TioF Port output fall time(2, 3) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure11-1 for loading conditions. FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508/C509 VDD MCLR 30 Internal POR 32 32 32 DRT Timeout (Note 2) Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT and LP modes. DS40139E-page 72 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) –40(cid:176)C £ TA £ +85(cid:176)C (industrial) –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section11.1 Parameter No. Sym Characteristic Min Typ(1) Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5 V 31 Twdt Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5 V (Commercial) (No Prescaler) 32 TDRT Device Reset Timer Period(2) 9* 18* 30* ms VDD = 5 V (Commercial) 34 TioZ I/O Hi-impedance from MCLR Low — — 2000* ns * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 2: See Table 11-6. TABLE 11-6: DRT (DEVICE RESET TIMER PERIOD - PIC12C508/C509) Oscillator Configuration POR Reset Subsequent Resets IntRC & ExtRC 18 ms (typical) 300 µs (typical) XT & LP 18 ms (typical) 18 ms (typical) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 73

PIC12C5XX FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC12C508/C509 T0CKI 40 41 42 TABLE 11-7: TIMER0 CLOCK REQUIREMENTS - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) –40(cid:176)C £ TA £ +85(cid:176)C (industrial) –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section11.1. Parameter Sym Characteristic Min Typ(1) Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width- No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40139E-page 74 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 12.0 DC AND AC CHARACTERISTICS - PIC12C508/PIC12C509 The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3s ) and (mean – 3s ) respectively, where s is standard deviation. FIGURE 12-1: CALIBRATED INTERNAL RC FIGURE 12-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. FREQUENCY RANGE VS. TEMPERATURE (VDD = 2.5V) TEMPERATURE (VDD = 5.0V) 4.50 4.50 4.40 4.40 4.30 4.30 4.20 z) 4.20 H z) M H Frequency ( 44..1000 Max. equency (M 44..1000 Max. Fr 3.90 3.90 3.80 3.80 3.70 Min. 3.70 3.60 Min. 3.60 3.50 -40 25 85 125 3.50 -40 25 85 125 Temperature (Deg.C) Temperature (Deg.C) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 75

PIC12C5XX TABLE 12-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C Oscillator Frequency VDD = 2.5V VDD = 5.5V External RC 4 MHz 250 µA* 780 µA* Internal RC 4 MHz 420 µA 1.1 mA XT 4 MHz 251 µA 780 µA LP 32 KHz 15 µA 37 µA *Does not include current through external R&C. FIGURE 12-3: WDT TIMER TIME-OUT FIGURE 12-4: SHORT DRT PERIOD VS. VDD PERIOD VS. VDD 1000 50 900 45 800 40 700 35 s) µ mS) od ( 600 od ( 30 Max +125(cid:176)C peri DT peri 25 Max +85(cid:176)C WDT 500 MMaaxx ++18255(cid:176)(cid:176)CC W 400 20 Typ +25(cid:176)C 300 Typ +25(cid:176)C 15 200 10 MIn –40(cid:176)C 100 MIn –40(cid:176)C 5 2 3 4 5 6 7 2 3 4 5 6 7 VDD (Volts) VDD (Volts) DS40139E-page 76 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX FIGURE 12-5: IOH vs. VOH, VDD = 2.5 V FIGURE 12-7: IOL vs. VOL, VDD = 2.5 V 25 0 -1 20 -2 Max –40(cid:176)C A) -3 15 m I (OH -4 (mA)L Typ +25(cid:176)C O I 10 Min +125(cid:176)C -5 Min +85(cid:176)C Min +85(cid:176)C -6 Typ +25(cid:176)C 5 Min +125(cid:176)C Max –40(cid:176)C -7 500m 1.0 1.5 2.0 2.5 0 VOH (Volts) 0 250.0m 500.0m 1.0 VOL (Volts) FIGURE 12-6: IOH vs. VOH, VDD = 5.5 V FIGURE 12-8: IOL vs. VOL, VDD = 5.5 V 0 50 -5 Max –40(cid:176)C 40 -10 mA) 30 Typ +25(cid:176)C I (OH -15 mA) -20 MiMinn ++18(cid:176)25(cid:176)5CCC I (OL 20 Min +85(cid:176)C -25 TypM a+x 2(cid:176)–54(cid:176)0C 10 Min +125(cid:176)C -30 3.5 4.0 4.5 5.0 5.5 VOH (Volts) 0 250.0m 500.0m 750.0m 1.0 VOL (Volts) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 77

PIC12C5XX NOTES: DS40139E-page 78 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 13.0 ELECTRICAL CHARACTERISTICS - PIC12C508A/PIC12C509A/ PIC12LC508A/PIC12LC509A/PIC12CR509A/PIC12CE518/PIC12CE519/ PIC12LCE518/PIC12LCE519/PIC12LCR509A Absolute Maximum Ratings† Ambient Temperature under bias...........................................................................................................–40°C to +125°C Storage Temperature.............................................................................................................................–65°C to +150°C Voltage on VDD with respect to VSS.................................................................................................................0 to +7.0 V Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V Voltage on all other pins with respect to VSS...............................................................................–0.3 V to (VDD + 0.3 V) Total Power Dissipation(1)....................................................................................................................................700 mW Max. Current out of VSS pin..................................................................................................................................200 mA Max. Current into VDD pin.....................................................................................................................................150 mA Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................– 20 mA Output Clamp Current, IOK (VO < 0 or VO > VDD).............................................................................................................– 20 mA Max. Output Current sunk by any I/O pin................................................................................................................25 mA Max. Output Current sourced by any I/O pin...........................................................................................................25 mA Max. Output Current sourced by I/O port (GPIO).................................................................................................100 mA Max. Output Current sunk by I/O port (GPIO )......................................................................................................100 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - (cid:229) IOH} + (cid:229) {(VDD-VOH) x IOH} + (cid:229) (VOL x IOL) †NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 79

PIC12C5XX 13.1 DC CHARACTERISTICS: PIC12C508A/509A (Commercial, Industrial, Extended) PIC12CE518/519 (Commercial, Industrial, Extended) PIC12CR509A (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) Power Supply Pins –40(cid:176)C £ TA £ +85(cid:176)C (industrial) –40(cid:176)C £ TA £ +125(cid:176)C (extended) Parm Characteristic Sym Min Typ(1) Max Units Conditions No. D001 Supply Voltage VDD 3.0 5.5 V FOSC = DC to 4 MHz (Commercial/ Industrial, Extended) D002 RAM Data Retention VDR 1.5* V Device in SLEEP mode Voltage(2) D003 VDD Start Voltage to ensure VPOR VSS V See section on Power-on Reset for details Power-on Reset D004 VDD Rise Rate to ensure SVDD 0.05* V/ms See section on Power-on Reset for details Power-on Reset D010 Supply Current(3) IDD — 0.8 1.4 mA XT and EXTRC options (Note 4) FOSC = 4 MHz, VDD = 5.5V D010C — 0.8 1.4 mA INTRC Option FOSC = 4 MHz, VDD = 5.5V D010A — 19 27 m A LP OPTION, Commercial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled — 19 35 m A LP OPTION, Industrial Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled — 30 55 µA LP OPTION, Extended Temperature FOSC = 32 kHz, VDD = 3.0V, WDT disabled D020 Power-Down Current (5) IPD — 0.25 4 m A VDD = 3.0V, Commercial WDT disabled D021 — 0.25 5 m A VDD = 3.0V, Industrial WDT disabled D021B — 2 12 m A VDD = 3.0V, Extended WDT disabled D022 Power-Down Current D IWDT — 2.2 5 m A VDD = 3.0V, Commercial — 2.2 6 m A VDD = 3.0V, Industrial — 4 11 m A VDD = 3.0V, Extended Supply Current (3) D IEE — 0.1 0.2 mA FOSC = 4 MHz, Vdd = 5.5V, During read/write to SCL = 400kHz EEPROM peripheral * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is based on characterization results at 25(cid:176)C. This data is for design guid- ance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea- sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. DS40139E-page 80 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 13.2 DC CHARACTERISTICS: PIC12LC508A/509A (Commercial, Industrial) PIC12LCE518/519 (Commercial, Industrial) PIC12LCR509A (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) DC Characteristics Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) Power Supply Pins –40(cid:176)C £ TA £ +85(cid:176)C (industrial) Parm Characteristic Sym Min Typ(1) Max Units Conditions No. D001 Supply Voltage VDD 2.5 5.5 V FOSC = DC to 4 MHz (Commercial/ Industrial) D002 RAM Data Retention VDR 1.5* V Device in SLEEP mode Voltage(2) D003 VDD Start Voltage to ensure VPOR VSS V See section on Power-on Reset for details Power-on Reset D004 VDD Rise Rate to ensure SVDD 0.05* V/ms See section on Power-on Reset for details Power-on Reset D010 Supply Current(3) IDD — 0.4 0.8 mA XT and EXTRC options (Note 4) FOSC = 4 MHz, VDD = 2.5V D010C — 0.4 0.8 mA INTRC Option FOSC = 4 MHz, VDD = 2.5V D010A — 15 23 m A LP OPTION, Commercial Temperature FOSC = 32 kHz, VDD = 2.5V, WDT disabled — 15 31 m A LP OPTION, Industrial Temperature FOSC = 32 kHz, VDD = 2.5V, WDT disabled D020 Power-Down Current (5) IPD D021 — 0.2 3 m A VDD = 2.5V, Commercial D021B — 0.2 4 m A VDD = 2.5V, Industrial D IWDT — 2.0 4 mA VDD = 2.5V, Commercial 2.0 5 mA VDD = 2.5V, Industrial * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is based on characterization results at 25(cid:176)C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode. 4: Does not include current through Rext. The current through the resistor can be estimated by the formula: IR = VDD/2Rext (mA) with Rext in kOhm. 5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 81

PIC12C5XX 13.3 DC CHARACTERISTICS: PIC12C508A/509A (Commercial, Industrial, Extended) PIC12C518/519 (Commercial, Industrial, Extended) PIC12CR509A (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C £ TA £ +70°C (commercial) –40°C £ TA £ +85°C (industrial) DC CHARACTERISTICS –40°C £ TA £ +125°C (extended) Operating voltage VDD range as described in DC spec Section13.1 and Section13.2. Param Characteristic Sym Min Typ† Max Units Conditions No. Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.8V V For 4.5V £ VDD £ 5.5V VSS - 0.15VDD V otherwise D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, GP2/T0CKI (in EXTRC mode) VSS - 0.2VDD V D033 OSC1 (in EXTRC mode) VSS - 0.2VDD Note 1 D033 OSC1 (in XT and LP) VSS - 0.3VDD V Note 1 Input High Voltage I/O ports VIH - D040 with TTL buffer 0.25VDD + - VDD V 4.5V £ VDD £ 5.5V 0.8V D040A 2.0V - VDD V otherwise D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR, GP2/T0CKI 0.8VDD - VDD V D042A OSC1 (XT and LP) 0.7VDD - VDD V Note 1 D043 OSC1 (in EXTRC mode) 0.9VDD - VDD V D070 GPIO weak pull-up current (Note 4) IPUR 30 250 400 m A VDD = 5V, VPIN = VSS MCLR pull-up current - - - 30 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - +1 m A Vss £ VPIN £ VDD, Pin at hi- impedance D061 T0CKI - - +5 m A Vss £ VPIN £ VDD D063 OSC1 - - +5 m A Vss £ VPIN £ VDD, XT and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, –40(cid:176)C to +85(cid:176)C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, –40(cid:176)C to +125(cid:176)C Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, –40(cid:176)C to +85(cid:176)C D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V, –40(cid:176)C to +125(cid:176)C Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC2 - - 15 pF In XT and LP modes when exter- nal clock is used to drive OSC1. D101 All I/O pins CIO - - 50 pF † Data in “Typ” column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C5XX be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: This spec. applies when GP3/MCLR is configured as MCLR. The leakage current of the MCLR circuit is higher than the standard I/O logic. DS40139E-page 82 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 13.4 DC CHARACTERISTICS: PIC12LC508A/509A (Commercial, Industrial) PIC12LC518/519 (Commercial, Industrial) PIC12LCR509A (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C £ TA £ +70°C (commercial) DC CHARACTERISTICS –40°C £ TA £ +85°C (industrial) Operating voltage VDD range as described in DC spec Section13.1 and Section13.2. Param Characteristic Sym Min Typ† Max Units Conditions No. Input Low Voltage I/O ports VIL D030 with TTL buffer VSS - 0.8V V For 4.5V £ VDD £ 5.5V VSS - 0.15VDD V otherwise D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, GP2/T0CKI (in EXTRC mode) VSS - 0.2VDD V D033 OSC1 (in EXTRC mode) VSS - 0.2VDD V Note 1 D033 OSC1 (in XT and LP) VSS - 0.3VDD V Note 1 Input High Voltage I/O ports VIH - D040 with TTL buffer 0.25VDD + - VDD V 4.5V £ VDD £ 5.5V 0.8V D040A 2.0V - VDD V otherwise D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR, GP2/T0CKI 0.8VDD - VDD V D042A OSC1 (XT and LP) 0.7VDD - VDD V Note 1 D043 OSC1 (in EXTRC mode) 0.9VDD - VDD V D070 GPIO weak pull-up current (Note 4) IPUR 30 250 400 m A VDD = 5V, VPIN = VSS MCLR pull-up current - - - 30 m A VDD = 5V, VPIN = VSS Input Leakage Current (Notes 2, 3) D060 I/O ports IIL - - +1 m A Vss £ VPIN £ VDD, Pin at hi-imped- ance D061 T0CKI - - +5 m A Vss £ VPIN £ VDD D063 OSC1 - - +5 m A Vss £ VPIN £ VDD, XT and LP osc configuration Output Low Voltage D080 I/O ports VOL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, –40(cid:176)C to +85(cid:176)C D080A - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, –40(cid:176)C to +125(cid:176)C Output High Voltage D090 I/O ports (Note 3) VOH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V, –40(cid:176)C to +85(cid:176)C D090A VDD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V, –40(cid:176)C to +125(cid:176)C Capacitive Loading Specs on Output Pins D100 OSC2 pin COSC - - 15 pF In XT and LP modes when exter- 2 nal clock is used to drive OSC1. D101 All I/O pins CIO - - 50 pF † Data in “Typ” column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C5XX be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 4: This spec. applies when GP3/MCLR is configured as MCLR. The leakage current of the MCLR circuit is higher than the standard I/O logic. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 83

PIC12C5XX TABLE 13-1: PULL-UP RESISTOR RANGES* - PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 VDD (Volts) Temperature ((cid:176)C) Min Typ Max Units GP0/GP1 2.5 –40 38K 42K 63K W 25 42K 48K 63K W 85 42K 49K 63K W 125 50K 55K 63K W 5.5 –40 15K 17K 20K W 25 18K 20K 23K W 85 19K 22K 25K W 125 22K 24K 28K W GP3 2.5 –40 285K 346K 417K W 25 343K 414K 532K W 85 368K 457K 532K W 125 431K 504K 593K W 5.5 –40 247K 292K 360K W 25 288K 341K 437K W 85 306K 371K 448K W 125 351K 407K 500K W * These parameters are characterized but not tested. DS40139E-page 84 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 13.5 Timing Parameter Symbology and Load Conditions - PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance FIGURE 13-1: LOAD CONDITIONS - PIC12C508A/C509A, PIC12CE518/519, PIC12LC508A/509A, PIC12LCE518/519, PIC12LCR509A Pin CL = 50 pF for all pins except OSC2 CL 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1 VSS (cid:211) 1999 Microchip Technology Inc. DS40139E-page 85

PIC12C5XX 13.6 Timing Diagrams and Specifications FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 TABLE 13-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial), –40(cid:176)C £ TA £ +85(cid:176)C (industrial), –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section13.1 Parameter Sym Characteristic Min Typ(1) Max Units Conditions No. FOSC External CLKIN Frequency(2) DC — 4 MHz XT osc mode DC — 200 kHz LP osc mode Oscillator Frequency(2) DC — 4 MHz EXTRC osc mode 0.1 — 4 MHz XT osc mode DC — 200 kHz LP osc mode 1 TOSC External CLKIN Period(2) 250 — — ns XT osc mode 5 — — ms LP osc mode Oscillator Period(2) 250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode 5 — — ms LP osc mode 2 Tcy Instruction Cycle Time(3) — 4/FOSC — — 3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator 2* — — ms LP oscillator 4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator — — 50* ns LP oscillator * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 3: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS40139E-page 86 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE 13-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial), –40(cid:176)C £ TA £ +85(cid:176)C (industrial), –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section10.1 Parameter Sym Characteristic Min* Typ(1) Max* Units Conditions No. Internal Calibrated RC Frequency 3.65 4.00 4.28 MHz VDD = 5.0V Internal Calibrated RC Frequency 3.55 — 4.31 MHz VDD = 2.5V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 87

PIC12C5XX FIGURE 13-3: I/O TIMING - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 Q4 Q1 Q2 Q3 OSC1 I/O Pin (input) 17 19 18 I/O Pin (output) Old Value New Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 13-4: TIMING REQUIREMENTS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) –40(cid:176)C £ TA £ +85(cid:176)C (industrial) –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section13.1 Parameter No. Sym Characteristic Min Typ(1) Max Units 17 TosH2ioV OSC1› (Q1 cycle) to Port out valid(3) — — 100* ns 18 TosH2ioI OSC1› (Q2 cycle) to Port input invalid TBD — — ns (I/O in hold time) 19 TioV2osH Port input valid to OSC1› TBD — — ns (I/O in setup time) 20 TioR Port output rise time(2, 3) — 10 25** ns 21 TioF Port output fall time(2, 3) — 10 25** ns * These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time. Note1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure13-1 for loading conditions. DS40139E-page 88 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 VDD MCLR 30 Internal POR 32 32 32 DRT Timeout (Note 2) Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT and LP modes. TABLE 13-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) –40(cid:176)C £ TA £ +85(cid:176)C (industrial) –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section13.1 Parameter No. Sym Characteristic Min Typ(1) Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5 V 31 Twdt Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5 V (Commercial) (No Prescaler) 32 TDRT Device Reset Timer Period(2) 9* 18* 30* ms VDD = 5 V (Commercial) 34 TioZ I/O Hi-impedance from MCLR Low — — 2000* ns * These parameters are characterized but not tested. Note1: Data in the Typical (“Typ”) column is at 5V, 25(cid:176)C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 2: See Table 13-6. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 89

PIC12C5XX TABLE 13-6: DRT (DEVICE RESET TIMER PERIOD) - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 Oscillator Configuration POR Reset Subsequent Resets IntRC & ExtRC 18 ms (typical)(1) 300 µs (typical)(1) XT & LP 18 ms (typical)(1) 18 ms (typical)(1) Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 T0CKI 40 41 42 TABLE 13-7: TIMER0 CLOCK REQUIREMENTS - PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A, PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C (commercial) –40(cid:176)C £ TA £ +85(cid:176)C (industrial) –40(cid:176)C £ TA £ +125(cid:176)C (extended) Operating Voltage VDD range is described in Section13.1. Parameter Sym Characteristic Min Typ(1) Max Units Conditions No. 40 Tt0H T0CKI High Pulse Width- No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns - With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater. N N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40139E-page 90 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX TABLE 13-8: EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE5XX ONLY. AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0(cid:176)C £ TA £ +70(cid:176)C, Vcc = 3.0V to 5.5V (commercial) –40(cid:176)C £ TA £ +85(cid:176)C, Vcc = 3.0V to 5.5V (industrial) –40(cid:176)C £ TA £ +125(cid:176)C, Vcc = 4.5V to 5.5V (extended) Operating Voltage VDD range is described in Section13.1 Parameter Symbol Min Max Units Conditions Clock frequency FCLK — 100 kHz 4.5V £ Vcc £ 5.5V (E Temp range) — 100 3.0V £ Vcc £ 4.5V — 400 4.5V £ Vcc £ 5.5V Clock high time THIGH 4000 — ns 4.5V £ Vcc £ 5.5V (E Temp range) 4000 — 3.0V £ Vcc £ 4.5V 600 — 4.5V £ Vcc £ 5.5V Clock low time TLOW 4700 — ns 4.5V £ Vcc £ 5.5V (E Temp range) 4700 — 3.0V £ Vcc £ 4.5V 1300 — 4.5V £ Vcc £ 5.5V SDA and SCL rise time TR — 1000 ns 4.5V £ Vcc £ 5.5V (E Temp range) (Note1) — 1000 3.0V £ Vcc £ 4.5V — 300 4.5V £ Vcc £ 5.5V SDA and SCL fall time TF — 300 ns (Note1) START condition hold time THD:STA 4000 — ns 4.5V £ Vcc £ 5.5V (E Temp range) 4000 — 3.0V £ Vcc £ 4.5V 600 — 4.5V £ Vcc £ 5.5V START condition setup time TSU:STA 4700 — ns 4.5V £ Vcc £ 5.5V (E Temp range) 4700 — 3.0V £ Vcc £ 4.5V 600 — 4.5V £ Vcc £ 5.5V Data input hold time THD:DAT 0 — ns (Note2) Data input setup time TSU:DAT 250 — ns 4.5V £ Vcc £ 5.5V (E Temp range) 250 — 3.0V £ Vcc £ 4.5V 100 — 4.5V £ Vcc £ 5.5V STOP condition setup time TSU:STO 4000 — ns 4.5V £ Vcc £ 5.5V (E Temp range) 4000 — 3.0V £ Vcc £ 4.5V 600 — 4.5V £ Vcc £ 5.5V Output valid from clock TAA — 3500 ns 4.5V £ Vcc £ 5.5V (E Temp range) (Note2) — 3500 3.0V £ Vcc £ 4.5V — 900 4.5V £ Vcc £ 5.5V Bus free time: Time the bus must TBUF 4700 — ns 4.5V £ Vcc £ 5.5V (E Temp range) be free before a new transmis- 4700 — 3.0V £ Vcc £ 4.5V sion can start 1300 — 4.5V £ Vcc £ 5.5V Output fall time from VIH TOF 20+0.1 250 ns (Note1), CB £ 100 pF minimum to VIL maximum CB Input filter spike suppression TSP — 50 ns (Notes1, 3) (SDA and SCL pins) Write cycle time TWC — 4 ms Endurance 1M — cycles 25(cid:176)C, VCC = 5.0V, Block Mode (Note4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli- cation, please consult the Total Endurance Model which can be obtained on Microchip’s website. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 91

PIC12C5XX NOTES: DS40139E-page 92 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 14.0 DC AND AC CHARACTERISTICS - PIC12C508A/PIC12C509A/ PIC12LC508A/PIC12LC509A, PIC12CE518/PIC12CE519/PIC12CR509A/ PIC12LCE518/PIC12LCE519/ PIC12LCR509A The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3s ) and (mean – 3s ) respectively, where s is standard deviation. FIGURE 14-1: CALIBRATED INTERNAL RC FIGURE 14-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V) TEMPERATURE (VDD = 2.5V) (INTERNAL RC IS (INTERNAL RC IS CALIBRATED TO 25°C, 5.0V) CALIBRATED TO 25°C, 5.0V) 4.50 4.50 4.40 4.40 4.30 4.30 Max. 4.20 4.20 Max. MHz) 4.10 MHz)4.10 Frequency ( 43..0900 Frequency (43..0900 3.80 3.80 3.70 Min. 3.70 3.60 3.60 Min. 3.50 3.50 -40 0 25 85 125 -40 0 25 85 125 Temperature (Deg.C) Temperature (Deg.C) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 93

PIC12C5XX TABLE 14-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C Oscillator Frequency VDD =3.0V VDD = 5.5V External RC 4 MHz 240 µA* 800 µA* Internal RC 4 MHz 320 µA 800 µA XT 4 MHz 300 µA 800 µA LP 32 KHz 19 µA 50 µA *Does not include current through external R&C. FIGURE 14-3: TYPICAL IDD VS. VDD FIGURE 14-4: TYPICAL IDD VS. FREQUENCY (WDT DIS, 25°C, FREQUENCY (WDT DIS, 25°C, VDD = 5.5V) = 4MHZ) 600 600 550 550 500 500 450 450 400 400 350 350 A) A) (µD 300 (µD 300 D D I I 250 250 200 200 150 150 100 100 0 0 2.5 3.0 4.5 5.0 5.5 0 .5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VDD (Volts) Frequency (MHz) DS40139E-page 94 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX FIGURE 14-5: WDT TIMER TIME-OUT FIGURE 14-7: IOH vs. VOH, VDD = 2.5 V PERIOD vs. VDD 55 -0 50 -1 45 -2 -3 40 µS) A) -4 Min +125(cid:176)C eriod ( 35 Max +125(cid:176)C (mOH -5 Min +85(cid:176)C p I T 30 -6 WD Max +85(cid:176)C Typ +25(cid:176)C 25 -7 -8 20 Typ +25(cid:176)C -9 Max -40(cid:176)C 15 -10 MIn –40(cid:176)C .5 .75 1.0 1.25 1.5 1.75 2.0 2.252.5 10 VOH (Volts) 0 2.5 3.5 4.5 5.5 6.5 VDD (Volts) FIGURE 14-6: SHORT DRT PERIOD VS. VDD FIGURE 14-8: IOH vs. VOH, VDD = 3.5 V 950 0 850 -5 750 A) Min +125(cid:176)C m -10 650 (H O s) I Min +85(cid:176)C µ eriod ( 550 Max +125(cid:176)C -15 Typ +25(cid:176)C p T 450 D Max +85(cid:176)C W -20 Max -40(cid:176)C 350 Typ +25(cid:176)C 250 -25 1.5 2.0 2.5 3.0 3.5 MIn –40(cid:176)C VOH (Volts) 150 0 0 2.5 3.5 4.5 5.5 6.5 VDD (Volts) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 95

PIC12C5XX FIGURE 14-9: IOL vs. VOL, VDD = 2.5 V FIGURE 14-11:IOH vs. VOH, VDD = 5.5 V 35 0 -5 30 Max -40(cid:176)C -10 (mA)L 2250 Typ +25(cid:176)C (mA)H --1250 MTMiyinnp +++182(cid:176)(cid:176)525(cid:176)5CCC O O I I 15 -25 Min +85(cid:176)C C 10 -30 Max –4(cid:176)0 Min +125(cid:176)C 5 -35 0 -40 3.5 4.0 4.5 5.0 5.5 0 0.25 0.5 0.75 1.0 VOL (Volts) VOH (Volts) FIGURE 14-12:IOL vs. VOL, VDD = 5.5 V FIGURE 14-10:IOL vs. VOL, VDD = 3.5 V 45 55 Max -40(cid:176)C Max -40(cid:176)C 40 50 45 35 40 30 35 Typ +25(cid:176)C Typ +25(cid:176)C A) 25 A) 30 m m (L (L O O I I 25 20 20 Min +85(cid:176)C 15 Min +85(cid:176)C 15 Min +125(cid:176)C Min +125(cid:176)C 10 10 0 0 0 0.25 0.5 0.75 1.0 0 0.25 0.5 0.75 1.0 VOL (Volts) VOL (Volts) DS40139E-page 96 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX FIGURE 14-13:TYPICAL IPD VS. VDD, FIGURE 14-14:VTH (INPUT THRESHOLD WATCHDOG DISABLED (25°C) VOLTAGE) OF GPIO PINS VS. VDD 260 1.8 250 1.6 Max (-40 to 125) s) 240 Volt 1.4 (H A) VT n Typ (25) d ( 230 1.2 p I Min (-40 to 125) 220 1.0 210 0.8 200 0.6 2.5 3.0 3.5 4.5 5.0 5.5 VDD (Volts) 0 2.5 3.5 4.5 5.5 VDD (Volts) (cid:211) 1999 Microchip Technology Inc. DS40139E-page 97

PIC12C5XX FIGURE 14-15:VIL, VIH OF NMCLR, AND T0CKI VS. VDD 3.5 Vih Max (-40 to 125) VIH Typ (25) 3.0 VIH Min (-40 to 125) s) olt V 2.5 (H VI V, IL 2.0 VIL Max (-40 to 125) 1.5 VIL Typ (25) VIL Min (-40 to 125) 1.0 0.5 2.5 3.5 4.5 5.5 VDD (Volts) DS40139E-page 98 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX 15.0 PACKAGING INFORMATION 15.1 Package Marking Information 8-Lead PDIP (300 mil) Example XXXXXXXX 12C508A XXXXXCDE 04I/PSAZ AABB 9825 8-Lead SOIC (150 mil) Example XXXXXXX C508A AABB 9825 8-Lead SOIC (208 mil) Example XXXXXXX 12C508A XXXXXXX 04I/SM AABBCDE 9824SAZ 8-Lead Windowed Ceramic Side Brazed (300 mil) Example XXX JW XXXXXX 12C508A Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured O = Outside Vendor C = 5” Line S = 6” Line H = 8” Line D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 99

PIC12C5XX Package Type: K04-018 8-Lead Plastic Dual In-line (P) – 300 mil E D 2 1 n a E1 A A1 R L c A2 b B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 8 8 Pitch p 0.100 2.54 Lower Lead Width B 0.014 0.018 0.022 0.36 0.46 0.56 Upper Lead Width B1† 0.055 0.060 0.065 1.40 1.52 1.65 Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.006 0.012 0.015 0.20 0.29 0.38 Top to Seating Plane A 0.140 0.150 0.160 3.56 3.81 4.06 Top of Lead to Seating Plane A1 0.060 0.080 0.100 1.52 2.03 2.54 Base to Seating Plane A2 0.005 0.020 0.035 0.13 0.51 0.89 Tip to Seating Plane L 0.120 0.130 0.140 3.05 3.30 3.56 Package Length D‡ 0.355 0.370 0.385 9.02 9.40 9.78 Molded Package Width E‡ 0.245 0.250 0.260 6.22 6.35 6.60 Radius to Radius Width E1 0.267 0.280 0.292 6.78 7.10 7.42 Overall Row Spacing eB 0.310 0.342 0.380 7.87 8.67 9.65 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom b 5 10 15 5 10 15 * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” DS40139E-page 100 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX Package Type: K04-057 8-Lead Plastic Small Outline (SN) –Narrow, 150 mil E1 E p D 2 B n 1 X a 45° L c R2 A A1 R1 f b L1 A2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0.050 1.27 Number of Pins n 8 8 Overall Pack. Height A 0.054 0.061 0.069 1.37 1.56 1.75 Shoulder Height A1 0.027 0.035 0.044 0.69 0.90 1.11 Standoff A2 0.004 0.007 0.010 0.10 0.18 0.25 Molded Package Length D‡ 0.189 0.193 0.196 4.80 4.89 4.98 Molded Package Width E‡ 0.150 0.154 0.157 3.81 3.90 3.99 Outside Dimension E1 0.229 0.237 0.244 5.82 6.01 6.20 Chamfer Distance X 0.010 0.015 0.020 0.25 0.38 0.51 Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25 Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25 Foot Length L 0.011 0.016 0.021 0.28 0.41 0.53 Foot Angle f 0 4 8 0 4 8 Radius Centerline L1 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.008 0.009 0.010 0.19 0.22 0.25 Lower Lead Width B† 0.014 0.017 0.020 0.36 0.43 0.51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom b 0 12 15 0 12 15 * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” (cid:211) 1999 Microchip Technology Inc. DS40139E-page 101

PIC12C5XX Package Type: K04-056 8-Lead Plastic Small Outline (SM) –Medium, 208 mil E1 E p D 2 n 1 B a L R2 c A A1 R1 f A2 b L1 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0.050 1.27 Number of Pins n 8 8 Overall Pack. Height A 0.070 0.074 0.079 1.78 1.89 2.00 Shoulder Height A1 0.037 0.042 0.048 0.94 1.08 1.21 Standoff A2 0.002 0.005 0.009 0.05 0.14 0.22 Molded Package Length D‡ 0.200 0.205 0.210 5.08 5.21 5.33 Molded Package Width E‡ 0.203 0.208 0.213 5.16 5.28 5.41 Outside Dimension E1 0.300 0.313 0.325 7.62 7.94 8.26 Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25 Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25 Foot Length L 0.011 0.016 0.021 0.28 0.41 0.53 Foot Angle f 0 4 8 0 4 8 Radius Centerline L1 0.010 0.015 0.020 0.25 0.38 0.51 Lead Thickness c 0.008 0.009 0.010 0.19 0.22 0.25 Lower Lead Width B† 0.014 0.017 0.020 0.36 0.43 0.51 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom b 0 12 15 0 12 15 * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” DS40139E-page 102 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX Package Type: K04-084 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil E W T D 2 n 1 U A A1 L A2 c B1 p eB B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 8 8 Pitch p 0.098 0.100 0.102 2.49 2.54 2.59 Lower Lead Width B 0.016 0.018 0.020 0.41 0.46 0.51 Upper Lead Width B1 0.050 0.055 0.060 1.27 1.40 1.52 Lead Thickness c 0.008 0.010 0.012 0.20 0.25 0.30 Top to Seating Plane A 0.145 0.165 0.185 3.68 4.19 4.70 Top of Body to Seating Plane A1 0.103 0.123 0.143 2.62 3.12 3.63 Base to Seating Plane A2 0.025 0.035 0.045 0.64 0.89 1.14 Tip to Seating Plane L 0.130 0.140 0.150 3.30 3.56 3.81 Package Length D 0.510 0.520 0.530 12.95 13.21 13.46 Package Width E 0.280 0.290 0.300 7.11 7.37 7.62 Overall Row Spacing eB 0.310 0.338 0.365 7.87 8.57 9.27 Window Diameter W 0.161 0.166 0.171 4.09 4.22 4.34 Lid Length T 0.440 0.450 0.460 11.18 11.43 11.68 Lid Width U 0.260 0.270 0.280 6.60 6.86 7.11 * Controlling Parameter. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 103

PIC12C5XX NOTES: DS40139E-page 104 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX INDEX O A OPTION Register................................................................17 OSC selection.....................................................................35 ALU.......................................................................................9 OSCCAL Register...............................................................18 Applications...........................................................................4 Oscillator Configurations.....................................................36 Architectural Overview..........................................................9 Oscillator Types Assembler HS...............................................................................36 MPASM Assembler.....................................................61 LP...............................................................................36 B RC..............................................................................36 Block Diagram XT...............................................................................36 On-Chip Reset Circuit.................................................41 P Timer0.........................................................................25 Package Marking Information.............................................99 TMR0/WDT Prescaler.................................................28 Packaging Information........................................................99 Watchdog Timer..........................................................43 PICDEM-1 Low-Cost PICmicro Demo Board.....................60 Brown-Out Protection Circuit..............................................44 PICDEM-2 Low-Cost PIC16CXX Demo Board...................60 C PICDEM-3 Low-Cost PIC16CXXX Demo Board................60 CAL0 bit..............................................................................18 PICSTART(cid:210) Plus Entry Level Development System.........59 CAL1 bit..............................................................................18 POR CAL2 bit..............................................................................18 Device Reset Timer (DRT)...................................35, 42 CAL3 bit..............................................................................18 PD...............................................................................44 CALFST bit.........................................................................18 Power-On Reset (POR)..............................................35 CALSLW bit........................................................................18 TO...............................................................................44 Carry.....................................................................................9 PORTA...............................................................................21 Clocking Scheme................................................................12 Power-Down Mode.............................................................45 Code Protection............................................................35, 45 Prescaler............................................................................28 Configuration Bits................................................................35 PRO MATE(cid:210) II Universal Programmer..............................59 Configuration Word.............................................................35 Program Counter................................................................19 D Q DC and AC Characteristics...........................................75, 93 Q cycles..............................................................................12 Development Support.........................................................59 R Development Tools.............................................................59 RC Oscillator.......................................................................37 Device Varieties....................................................................7 Read Modify Write..............................................................22 Digit Carry.............................................................................9 Register File Map................................................................14 E Registers EEPROM Peripheral Operation..........................................29 Special Function.........................................................15 Errata....................................................................................3 Reset..................................................................................35 F Reset on Brown-Out...........................................................44 Family of Devices..................................................................5 S Features................................................................................1 SEEVAL(cid:210) Evaluation and Programming System..............61 FSR.....................................................................................20 SLEEP..........................................................................35, 45 Fuzzy Logic Dev. System (fuzzyTECH(cid:210) -MP)....................61 Software Simulator (MPLAB-SIM)......................................61 I Special Features of the CPU..............................................35 Special Function Registers.................................................15 I/O Interfacing.....................................................................21 Stack...................................................................................19 I/O Ports..............................................................................21 STATUS...............................................................................9 I/O Programming Considerations........................................22 STATUS Register...............................................................16 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator............59 ID Locations..................................................................35, 45 T INDF....................................................................................20 Timer0 Indirect Data Addressing.....................................................20 Switching Prescaler Assignment................................28 Instruction Cycle.................................................................12 Timer0........................................................................25 Instruction Flow/Pipelining..................................................12 Timer0 (TMR0) Module..............................................25 Instruction Set Summary.....................................................48 TMR0 with External Clock..........................................27 K Timing Diagrams and Specifications............................70, 86 KeeLoq(cid:210) Evaluation and Programming Tools....................62 Timing Parameter Symbology and Load Conditions....69, 85 TRIS Registers...................................................................21 L W Loading of PC.....................................................................19 Wake-up from SLEEP.........................................................45 M Watchdog Timer (WDT)................................................35, 42 Memory Organization..........................................................13 Period.........................................................................43 Data Memory..............................................................14 Programming Considerations.....................................43 Program Memory........................................................13 WWW, On-Line Support.......................................................3 MPLAB Integrated Development Environment Software....61 Z Zero bit.................................................................................9 (cid:211) 1999 Microchip Technology Inc. DS40139E-page 105

PIC12C5XX DS40139E-page 106 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX ON-LINE SUPPORT Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides Microchip provides on-line support on the Microchip system users a listing of the latest versions of all of World Wide Web (WWW) site. Microchip’s development systems software products. The web site is used by Microchip as a means to make Plus, this line provides information on how customers files and information easily available to customers. To can receive any currently available upgrade kits.The view the site, the user must have access to the Internet Hot Line Numbers are: and a web browser, such as Netscape or Microsoft 1-800-755-2345 for U.S. and most of Canada, and Explorer. Files are also available for FTP download from our FTP site. 1-602-786-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 981103 The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User’s Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: Trademarks: The Microchip name, logo, PIC, PICmicro, • Latest Microchip Press Releases PICSTART, PICMASTER and PRO MATE are registered • Technical Support Section with Frequently Asked trademarks of Microchip Technology Incorporated in the Questions U.S.A. and other countries. FlexROM, MPLAB and fuzzy- LAB are trademarks and SQTP is a service mark of Micro- • Design Tips chip in the U.S.A. • Device Errata All other trademarks mentioned herein are the property of • Job Postings their respective companies. • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Sys- tems, technical information and more • Listing of seminars and events (cid:211) 1999 Microchip Technology Inc. DS40139E-page 107

PIC12C5XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC12C5XX Literature Number: DS40139E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS40139E-page 108 (cid:211) 1999 Microchip Technology Inc.

PIC12C5XX PIC12C5XX Product Identification System PART NO. -XX X /XX XXX Examples Pattern: Special Requirements a) PIC12C508A-04/P Commercial Temp., Package: SN = 150 mil SOIC PDIP Package, 4MHz, SM = 208 mil SOIC normal VDD limits P = 300 mil PDIP JW = 300 mil Windowed Ceramic Side Brazed b) PIC12C508A-04I/SM Industrial Temp., SOIC Temperature - = 0(cid:176)C to +70(cid:176)C Range: IE == --4400(cid:176)(cid:176)CC ttoo ++8152(cid:176)5C(cid:176)C pVaDcDk laimgeit,s 4MHz, normal Frequency 04 = 4 MHz c) PIC12C509-04I/P Range: Industrial Temp., PDIP package, 4MHz, normal VDD limits Device PIC12C508 PIC12C509 PIC12C508T (Tape & reel for SOIC only) PIC12C509T (Tape & reel for SOIC only) PIC12C508A PIC12C509A PIC12C508AT (Tape & reel for SOIC only) PIC12C509AT (Tape & reel for SOIC only) PIC12LC508A PIC12LC509A PIC12LC508AT (Tape & reel for SOIC only) PIC12LC509AT (Tape & reel for SOIC only) PIC12CR509A PIC12CR509AT (Tape & reel for SOIC only) PIC12LCR509A PIC12LCR509AT (Tape & reel for SOIC only) PIC12CE518 PIC12CE518T (Tape & reel for SOIC only) PIC12CE519 PIC12CE519T (Tape & reel for SOIC only) PIC12LCE518 PIC12LCE518T (Tape & reel for SOIC only) PIC12LCE519 PIC12LCE519T (Tape & reel for SOIC only) Please contact your local sales office for exact ordering procedures. Sales and Support: Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. (cid:211) 1999 Microchip Technology Inc. DS40139E-page 109

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PIC12C5XX NOTES: (cid:211) 1999 Microchip Technology Inc. DS40139E-page 111

Note the following details of the code protection feature on PICmicro® MCUs. (cid:127) The PICmicro family meets the specifications contained in the Microchip Data Sheet. (cid:127) Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. (cid:127) There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl- edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. (cid:127) Microchip is willing to work with the customer who is concerned about the integrity of their code. (cid:127) Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable”. (cid:127) Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device Trademarks applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab, ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech- to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries. patents or other intellectual property rights arising from such dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, use or otherwise. Use of Microchip’s products as critical com- In-Circuit Serial Programming, ICSP, ICEPIC, microPort, ponents in life support systems is not authorized except with Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, express written approval by Microchip. No licenses are con- MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode veyed, implicitly or otherwise, under any intellectual property and Total Endurance are trademarks of Microchip Technology rights. Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2002 Microchip Technology Inc.

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