PIC10F220/222 Data Sheet High-Performance Microcontrollers with 8-Bit A/D  2005-2013 Microchip Technology Inc. DS40001270F

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, ensure that your application meets with your specifications. PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology WARRANTIES OF ANY KIND WHETHER EXPRESS OR Incorporated in the U.S.A. and other countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries. the buyer’s risk, and the buyer agrees to defend, indemnify and Analog-for-the-Digital Age, Application Maestro, BodyCom, hold harmless Microchip from any and all damages, claims, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, suits, or expenses resulting from such use. No licenses are dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, conveyed, implicitly or otherwise, under any Microchip ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial intellectual property rights. Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2005-2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620775912 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide CERTIFIED BY DNV headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS40001270F-page 2  2005-2013 Microchip Technology Inc.

PIC10F220/222 6-Pin, 8-Bit Flash Microcontrollers Device Included In This Data Sheet: Low-Power Features/CMOS Technology: • PIC10F220 • Operating Current: • PIC10F222 - < 175A @ 2V, 4MHz • Standby Current: High-Performance RISC CPU: - 100nA @ 2V, typical • Low-Power, High-Speed Flash Technology: • Only 33 Single-Word Instructions to Learn - 100,000 Flash endurance • All Single-Cycle Instructions Except for Program Branches which are Two-Cycle - > 40-year retention • 12-bit Wide Instructions • Fully Static Design • 2-Level Deep Hardware Stack • Wide Operating Voltage Range: 2.0V to 5.5V • Direct, Indirect and Relative Addressing modes • Wide Temperature Range: for Data and Instructions - Industrial: -40C to +85C • 8-bit Wide Data Path - Extended: -40C to +125C • 8 Special Function Hardware Registers • Operating Speed: Peripheral Features: - 500ns instruction cycle with 8MHz internal • 4 I/O Pins: clock - 3 I/O pins with individual direction control - 1s instruction cycle with 4MHz internal - 1 input only pin clock - High current sink/source for direct LED drive Special Microcontroller Features: - Wake-on-change - Weak pull-ups • 4or 8MHz Precision Internal Oscillator: • 8-bit Real-Time Clock/Counter (TMR0) with 8-bit - Factory calibrated to ±1% Programmable Prescaler • In-Circuit Serial Programming™ (ICSP™) • Analog-to-Digital (A/D) Converter: • In-Circuit Debugging (ICD) Support - 8-bit resolution • Power-On Reset (POR) - 2 external input channels • Short Device Reset Timer, DRT (1.125ms typical) - 1 internal input channel dedicated • Watchdog Timer (WDT) with Dedicated On-Chip RC Oscillator for Reliable Operation • Programmable Code Protection • Multiplexed MCLR Input Pin • Internal Weak Pull-Ups on I/O Pins • Power-Saving Sleep mode • Wake-up from Sleep on Pin Change Program Memory Data Memory Timers Device I/O 8-Bit A/D (ch) 8-bit Flash (words) SRAM (bytes) PIC10F220 256 16 4 1 2 PIC10F222 512 23 4 1 2  2005-2013 Microchip Technology Inc. DS40001270F-page 1

PIC10F220/222 6-Lead SOT-23 Pin Diagram GP0/AN0/ICSPDAT 1 2 6 GP3/MCLR/VPP 2 2 VSS 2 20/ 5 VDD 2 F 0 GP1/AN1/ICSPCLK 3 C1 4 GP2/T0CKI/FOSC4 PI 8-Lead DIP Pin Diagram N/C 1 2 8 GP3/MCLR/VPP 2 VDD 2 0/2 7 VSS 2 2 GP2/T0CKI/FOSC4 3 F 6 N/C 0 1 GP1/AN1/ICSPCLK 4 C 5 GP0/AN0/ICSPDAT PI 8-Lead DFN Pin Diagram N/C 1 2 8 GP3/MCLR/VPP 2 2 VDD 2 0/ 7 VSS 2 2 GP2/T0CKI/FOSC4 3 F 6 N/C 0 1 C GP1/AN1/ICSPCLK 4 PI 5 GP0/AN0/ICSPDAT DS40001270F-page 2  2005-2013 Microchip Technology Inc.

PIC10F220/222 Table of Contents 1.0 General Description......................................................................................................................................................................5 2.0 Device Varieties ..........................................................................................................................................................................7 3.0 Architectural Overview.................................................................................................................................................................9 4.0 Memory Organization.................................................................................................................................................................13 5.0 I/O Port.......................................................................................................................................................................................21 6.0 TMR0 Module and TMR0 Register.............................................................................................................................................25 7.0 Analog-to-Digital (A/D) converter...............................................................................................................................................29 8.0 Special Features Of The CPU....................................................................................................................................................33 9.0 Instruction Set Summary............................................................................................................................................................43 10.0 Electrical Characteristics............................................................................................................................................................51 11.0 Development Support.................................................................................................................................................................61 12.0 DC and AC Characteristics Graphs and Charts.........................................................................................................................69 13.0 Packaging Information................................................................................................................................................................73 Index....................................................................................................................................................................................................81 The Microchip Web Site.......................................................................................................................................................................83 Customer Change Notification Service................................................................................................................................................83 Customer Support................................................................................................................................................................................83 Product Identification System..............................................................................................................................................................85 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include _literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.  2005-2013 Microchip Technology Inc. DS40001270F-page 3

PIC10F220/222 NOTES: DS40001270F-page 4  2005-2013 Microchip Technology Inc.

PIC10F220/222 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC10F220/222 devices from Microchip The PIC10F220/222 devices fit in applications ranging Technology are low-cost, high-performance, 8-bit, fully- from personal care appliances and security systems to static Flash-based CMOS microcontrollers. They low-power remote transmitters/receivers. The Flash employ a RISC architecture with only 33 single-word/ technology makes customizing application programs single-cycle instructions. All instructions are single- (transmitter codes, appliance settings, receiver fre- cycle (1s) except for program branches, which take quencies, etc.) extremely fast and convenient. The two cycles. The PIC10F220/222 devices deliver perfor- small footprint packages, for through hole or surface mance in an order of magnitude higher than their com- mounting, make these microcontrollers well suited for petitors in the same price category. The 12-bit wide applications with space limitations. Low-cost, low- instructions are highly symmetrical, resulting in a power, high-performance, ease-of-use and I/O flexibil- typical 2:1 code compression over other 8-bit ity make the PIC10F220/222 devices very versatile, microcontrollers in its class. The easy-to-use and easy even in areas where no microcontroller use has been to remember instruction set reduces development time considered before (e.g., timer functions, logic and significantly. PLDs in larger systems and coprocessor applications). The PIC10F220/222 products are equipped with spe- cial features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminates the need for the external Reset circuitry. INTOSC Internal Oscillator mode is pro- vided, thereby, preserving the limited number of I/O available. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC10F220/222 devices are available in cost- effective Flash, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers while benefiting from the Flash programmable flexibility. The PIC10F220/222 products are supported by a full- featured macro assembler, a software simulator, an in- circuit debugger, a ‘C’ compiler, a low-cost development programmer and a full featured program- mer. All the tools are supported on IBM® PC and compatible machines. TABLE 1-1: PIC10F220/222 DEVICES(1), (2) PIC10F220 PIC10F222 Clock Maximum Frequency of Operation (MHz) 8 8 Memory Flash Program Memory 256 512 Data Memory (bytes) 16 23 Peripherals Timer Module(s) TMR0 TMR0 Wake-up from Sleep on pin change Yes Yes Analog inputs 2 2 Features I/O Pins 3 3 Input Only Pins 1 1 Internal Pull-ups Yes Yes In-Circuit Serial Programming™ Yes Yes Number of instructions 33 33 Packages 6-pin SOT-23, 6-pin SOT-23, 8-pin DIP, DFN 8-pin DIP, DFN Note 1: The PIC10F220/222 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. 2: The PIC10F220/222 devices use serial programming with data pin GP0 and clock pin GP1.  2005-2013 Microchip Technology Inc. DS40001270F-page 5

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PIC10F220/222 2.0 DEVICE VARIETIES A variety of packaging options are available. Depend- ing on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC10F220/222 Product Identification System at the back of this data sheet to specify the correct part number. 2.1 Quick Turn Programming (QTP) Devices Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. 2.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number, which can serve as an entry-code, password or ID number.  2005-2013 Microchip Technology Inc. DS40001270F-page 7

PIC10F220/222 NOTES: DS40001270F-page 8  2005-2013 Microchip Technology Inc.

PIC10F220/222 3.0 ARCHITECTURAL OVERVIEW The PIC10F220/222 devices contain an 8-bit ALU and working register. The ALU is a general purpose arith- The high performance of the PIC10F220/222 devices metic unit. It performs arithmetic and Boolean functions can be attributed to a number of architectural features between data in the working register and any register commonly found in RISC microprocessors. To begin file. with, the PIC10F220/222 devices use a Harvard archi- The ALU is 8-bits wide and capable of addition, sub- tecture in which program and data are accessed on traction, shift and logical operations. Unless otherwise separate buses. This improves bandwidth over tradi- mentioned, arithmetic operations are two’s comple- tional von Neumann architectures where program and ment in nature. In two-operand instructions, one oper- data are fetched on the same bus. Separating program and is typically the W (working) register. The other and data memory further allows instructions to be sized operand is either a file register or an immediate differently than the 8-bit wide data word. Instruction constant. In single operand instructions, the operand is opcodes are 12 bits wide, making it possible to have all either the W register or a file register. single-word instructions. A 12-bit wide program mem- ory access bus fetches a 12-bit instruction in a single The W register is an 8-bit working register used for ALU cycle. A two-stage pipeline overlaps fetch and execu- operations. It is not an addressable register. tion of instructions. Consequently, all instructions (33) Depending on the instruction executed, the ALU may execute in a single cycle (1s @ 4MHz or 500ns @ affect the values of the Carry (C), Digit Carry (DC) and 8MHz) except for program branches. Zero (Z) bits in the STATUS register. The C and DC bits The table below lists program memory (Flash) and data operate as a borrow and digit borrow out bit, respec- memory (RAM) for the PIC10F220/222 devices. tively, in subtraction. See the SUBWF and ADDWF instructions for examples. Memory A simplified block diagram is shown in Figure3-1 with Device Program Data the corresponding device pins described in Table3-1. PIC10F220 256 x 12 16 x 8 PIC10F222 512 x 12 23 x 8 The PIC10F220/222 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC10F220/222 devices have a highly orthogonal (symmetrical) instruc- tion set that makes it possible to carry out any opera- tion, on any register, using any addressing mode. This symmetrical nature and lack of “special optimal situa- tions” make programming with the PIC10F220/222 devices simple, yet efficient. In addition, the learning curve is reduced significantly.  2005-2013 Microchip Technology Inc. DS40001270F-page 9

PIC10F220/222 FIGURE 3-1: BLOCK DIAGRAM 9-10 Data Bus 8 GPIO Flash Program Counter 512 x 12 or GP0/AN0/ICSPDAT 256 x 12 GP1/AN1/ICSPCLK RAM GP2/T0CKI/FOSC4 PMreomgroarmy STACK1 23b yotre 1s6 GP3/MCLR/VPP STACK2 File Registers Program 12 Bus RAM Addr 9 Addr MUX Instruction Reg Direct Addr 5 Indirect 5-7 Addr FSR Reg STATUS Reg 8 3 MUX Device Reset Timer Instruction Power-on Decode & Reset ALU Control AN0 Watchdog 8 Timer ADC Timing Generation Internal RC W Reg AN1 Clock Timer0 Absolute MCLR Voltage VDD, VSS Reference TABLE 3-1: PINOUT DESCRIPTION Input Output Name Function Description Type Type GP0/AN0/ICSPDAT GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. AN0 AN — Analog Input ICSPDAT ST CMOS In-Circuit programming data GP1/AN1/ICSPCLK GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. AN1 AN — Analog Input ICSPCLK ST — In-Circuit programming clock GP2/T0CKI/FOSC4 GP2 TTL CMOS Bidirectional I/O pin T0CKI ST — Clock input to TMR0 FOSC4 — CMOS Oscillator/4 output GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is an active-low Reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter Programming mode. VPP HV — Programming voltage input VDD VDD P — Positive supply for logic and I/O pins VSS VSS P — Ground reference for logic and I/O pins Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input, ST = Schmitt Trigger input, AN = Analog Input DS40001270F-page 10  2005-2013 Microchip Technology Inc.

PIC10F220/222 3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining Cycle An instruction cycle consists of four Q cycles (Q1, Q2, The clock is internally divided by four to generate four Q3 and Q4). The instruction fetch and execute are non-overlapping quadrature clocks, namely Q1, Q2, pipelined such that fetch takes one instruction cycle, Q3 and Q4. Internally, the PC is incremented every Q1, while decode and execute takes another instruction and the instruction is fetched from program memory cycle. However, due to the pipelining, each instruction and latched into the Instruction Register (IR) in Q4. It is effectively executes in one cycle. If an instruction decoded and executed during Q1 through Q4. The causes the PC to change (e.g., GOTO) then two cycles clocks and instruction execution flow is shown in are required to complete the instruction (Example3-1). Figure3-2 and Example3-1. A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register in cycle Q1. This instruc- tion is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC + 1 PC + 2 Fetch INST (PC) Execute INST (PC - 1) Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF GPIO Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF GPIO, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.  2005-2013 Microchip Technology Inc. DS40001270F-page 11

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PIC10F220/222 4.0 MEMORY ORGANIZATION 4.2 Program Memory Organization for the PIC10F222 The PIC10F220/222 memories are organized into pro- gram memory and data memory. Data memory banks The PIC10F222 devices have a 10-bit Program are accessed using the File Select Register (FSR). Counter (PC) capable of addressing a 1024 x 12 program memory space. 4.1 Program Memory Organization for Only the first 512 x 12 (0000h-01FFh) for the Mem- the PIC10F220 High are physically implemented (see Figure4-2). Accessing a location above these boundaries will The PIC10F220 devices have a 9-bit Program Counter cause a wrap-around within the first 512 x 12 space (PC) capable of addressing a 512 x 12 program (PIC10F222). The effective Reset vector is at 0000h, memory space. (see Figure4-2). Location 01FFh (PIC10F222) con- Only the first 256 x 12 (0000h-00FFh) for the tains the internal clock oscillator calibration value. PIC10F220 are physically implemented (see This value should never be overwritten. Figure4-1). Accessing a location above these boundaries will cause a wrap-around within the first FIGURE 4-2: PROGRAM MEMORY MAP 256 x 12 space (PIC10F220). The effective Reset AND STACK FOR THE vector is at 0000h, (see Figure4-1). Location 00FFh PIC10F222 (PIC10F220) contains the internal clock oscillator calibration value. This value should never be PC<8:0> <9:0> overwritten. CALL, RETLW 10 FIGURE 4-1: PROGRAM MEMORY MAP Stack Level 1 AND STACK FOR THE Stack Level 2 PIC10F220 PC<7:0> <8:0> Reset Vector(1) 0000h CALL, RETLW 9 On-chip Program Stack Level 1 Memory Stack Level 2 y or me ec Reset Vector(1) 0000h er MSpa s U On-chip Program Memory y or emce 512 Words 01FFh Ma p 0200h er S s U 02FFh 256 Word 00FFh 0100h Note 1: Address 0000h becomes the effective Reset vector. Location 01FFh contains the MOVLW XX internal oscillator calibration value. 01FFh Note 1: Address 0000h becomes the effective Reset vector. Location 00FFh contains the MOVLW XX internal oscillator calibration value.  2005-2013 Microchip Technology Inc. DS40001270F-page 13

PIC10F220/222 4.3 Data Memory Organization FIGURE 4-4: PIC10F222 REGISTER FILE MAP Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified File Address by its register file. The register file is divided into two 00h INDF(1) functional groups: Special Function Registers (SFR) 01h TMR0 and General Purpose Registers (GPR). 02h PCL The Special Function Registers include the TMR0 reg- ister, the Program Counter (PCL), the STATUS register, 03h STATUS the I/O register (GPIO) and the File Select Register 04h FSR (FSR). In addition, Special Function Registers are used 05h OSCCAL to control the I/O port configuration and prescaler options. 06h GPIO The General Purpose Registers are used for data and 07h ADCON0 control information under command of the instructions. 08h ADRES For the PIC10F220, the register file is composed of 9 09h Special Function Registers and 16 General Purpose Registers (Figure4-3, Figure4-4). General Purpose For the PIC10F222, the register file is composed of 9 Registers Special Function Registers and 23 General Purpose Registers (Figure4-4). 1Fh 4.3.1 GENERAL PURPOSE REGISTER FILE Note 1: Not a physical register. See Section4.9 “Indirect Data Addressing; INDF and The General Purpose Register file is accessed, either FSR Registers”. directly or indirectly, through the File Select Register (FSR). See Section4.9 “Indirect Data Addressing; INDF and FSR Registers”. 4.3.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers FIGURE 4-3: PIC10F220 REGISTER used by the CPU and peripheral functions to control the FILE MAP operation of the device (Table4-1). File Address The Special Function Registers can be classified into 00h INDF(1) two sets. The Special Function Registers associated with the “core” functions are described in this section. 01h TMR0 Those related to the operation of the peripheral 02h PCL features are described in the section for each peripheral feature. 03h STATUS 04h FSR 05h OSCCAL 06h GPIO 07h ADCON0 08h ADRES 09h Unimplemented(2) 0Fh 10h General Purpose Registers 1Fh Note 1: Not a physical register. See Section4.9 “Indirect Data Addressing; INDF and FSR Registers”. 2: Unimplemented, read as 00h. DS40001270F-page 14  2005-2013 Microchip Technology Inc.

PIC10F220/222 TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On Page # Reset(2) 00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20 01h TMR0 8-Bit Real-Time Clock/Counter xxxx xxxx 25 02h PCL(1) Low Order 8 Bits of PC 1111 1111 19 03h STATUS GPWUF — — TO PD Z DC C 0--1 1xxx(3) 15 04h FSR Indirect Data Memory Address Pointer 111x xxxx 20 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 1111 1110 18 06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx 21 07h ADCON0 ANS1 ANS0 — — CHS1 CHS0 GO/DONE ADON 11-- 1100 30 08h ADRES Result of Analog-to-Digital Conversion xxxx xxxx 31 N/A TRISGPIO — — — — I/O Control Register ---- 1111 23 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 17 Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: The upper byte of the Program Counter is not directly accessible. See Section4.7 “Program Counter” for an explanation of how to access these bits. 2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin change Reset. 3: See Table8-1 for other Reset specific values. 4.4 STATUS Register This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS regis- ter. These instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect Status bits, see Instruction Set Summary.  2005-2013 Microchip Technology Inc. DS40001270F-page 15

PIC10F220/222 REGISTER 4-1: STATUS REGISTER (ADDRESS: 03h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x GPWUF — — TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWUF: GPIO Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 Reserved: Do not use. Use of this bit may affect upward compatibility with future products. bit 5 Reserved: Do not use. Use of this bit may affect upward compatibility with future products. bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry to the 4th low-order bit of the result occurred 0 = A carry to the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred bit 0 C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred DS40001270F-page 16  2005-2013 Microchip Technology Inc.

PIC10F220/222 4.5 OPTION Register The OPTION register is a 8-bit wide, write-only register, Note: If TRIS bit is set to ‘0’, the wake-up on which contains various control bits to configure the change and pull-up functions are disabled Timer0/WDT prescaler and Timer0. for that pin (i.e., note that TRIS overrides Option control of GPPU and GPWU). The OPTION register is not memory mapped and is therefore only addressable by executing the OPTION instruction, the contents of the W register will be trans- Note: If the T0CS bit is set to ‘1’, it will override ferred to the OPTION register. A Reset sets the the TRIS function on the T0CKI pin. OPTION<7:0> bits. REGISTER 4-2: OPTION REGISTER W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWU: Enable Wake-up On Pin Change bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 6 GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4 bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 RateWDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128  2005-2013 Microchip Technology Inc. DS40001270F-page 17

PIC10F220/222 4.6 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4/8MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. After you move in the calibration constant, do not change the value. See Section8.2.2 “Internal 4/8MHz Oscillator”. REGISTER 4-3: OSCCAL – OSCILLATOR CALIBRATION REGISTER (ADDRESS: 05h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 CAL<6:0>: Oscillator Calibration bits 0111111 =Maximum frequency • • • 0000001 0000000 =Center frequency 1111111 • • • 1000000 =Minimum frequency bit 0 FOSC4: INTOSC/4 Output Enable bit(1) 1 = INTOSC/4 output onto GP2 0 = GP2/T0CKI applied to GP2 Note 1: Overrides GP2/T0CKI control registers when enabled. DS40001270F-page 18  2005-2013 Microchip Technology Inc.

PIC10F220/222 4.7 Program Counter 4.7.1 EFFECTS OF RESET As a program instruction is executed, the Program The PC is set upon a Reset, which means that the PC Counter (PC) will contain the address of the next addresses the last location in program memory (i.e., program instruction to be executed. The PC value is the oscillator calibration instruction). After executing increased by one every instruction cycle, unless an MOVLW XX, the PC will roll over to location 0000h and instruction changes the PC. begin executing user code. For a GOTO instruction, bits 8:0 of the PC are provided 4.8 Stack by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0>. The PIC10F220 device has a 2-deep, 8-bit wide For a CALL instruction or any instruction where the PCL hardware PUSH/POP stack. is the destination, bits 7:0 of the PC again are provided The PIC10F222 device has a 2-deep, 9-bit wide by the instruction word. However, PC<8> does not hardware PUSH/POP stack. come from the instruction word, but is always cleared A CALL instruction will PUSH the current value of stack (Figure4-5). 1 into stack 2 and then PUSH the current PC value, Instructions where the PCL is the destination or Modify incremented by one, into stack level 1. If more than two PCL instructions, include MOVWF PC, ADDWF PC and sequential CALL’s are executed, only the most recent BSF PC, 5. two return addresses are stored. Note: Because PC<8> is cleared in the CALL A RETLW instruction will POP the contents of stack level instruction or any Modify PCL instruction, 1 into the PC and then copy stack level 2 contents into all subroutine calls or computed jumps are level 1. If more than two sequential RETLW’s are exe- limited to the first 256 locations of any cuted, the stack will be filled with the address program memory page (512 words long). previously stored in level 2. Note1: The Wregister will be loaded with the lit- FIGURE 4-5: LOADING OF PC eral value specified in the instruction. This BRANCH INSTRUCTIONS is particularly useful for the implementa- tion of data look-up tables within the GOTO Instruction program memory. 8 7 0 2: There are no Status bits to indicate stack PC PCL overflows or stack underflow conditions. 3: There are no instructions mnemonics Instruction Word called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions. CALL or Modify PCL Instruction 8 7 0 PC PCL Instruction Word Reset to ‘0’  2005-2013 Microchip Technology Inc. DS40001270F-page 19

PIC10F220/222 4.9 Indirect Data Addressing; INDF EXAMPLE 4-1: HOW TO CLEAR RAM and FSR Registers USING INDIRECT ADDRESSING The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is MOVLW 0x10 ;initialize pointer contained in the FSR register (FSR is a pointer). This is MOVWF FSR ;to RAM NEXT CLRF INDF ;clear INDF indirect addressing. ;register 4.9.1 INDIRECT ADDRESSING INCF FSR,F ;inc pointer BTFSC FSR,4 ;all done? • Register file 09 contains the value 10h GOTO NEXT ;NO, clear next • Register file 0A contains the value 0Ah CONTINUE : ;YES, continue • Load the value 09 into the FSR register : • A read of the INDF register will return the value of10h The FSR is a 5-bit wide register. It is used in conjunc- • Increment the value of the FSR register by one tion with the INDF register to indirectly address the data (FSR = 0A) memory area. • A read of the INDR register now will return the value of 0Ah. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a Note: Do not use banking. FSR <7:5> are no-operation (although Status bits may be affected). unimplemented and read as ‘1’s. A simple program to clear RAM locations 10h-1Fh using Indirect addressing is shown in Example4-1. FIGURE 4-6: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing 4 (opcode) 0 4 (FSR) 0 Location Select Location Select 00h Data 0Fh Memory(1) 10h 1Fh Bank 0 Note 1: For register map detail, see Section4.3 “Data Memory Organization”. DS40001270F-page 20  2005-2013 Microchip Technology Inc.

PIC10F220/222 5.0 I/O PORT The TRIS registers are “write-only” and are set (output drivers disabled) upon Reset. As with any other register, the I/O register(s) can be written and read under program control. However, read 5.3 I/O Interfacing instructions (e.g., MOVF GPIO, W) always read the I/O pins independent of the pin’s Input/Output modes. On The equivalent circuit for an I/O port pin is shown in Reset, all I/O ports are defined as input (inputs are at Figure5-1. All port pins, except GP3, which is input high-impedance) since the I/O control registers are all only, may be used for both input and output operations. set. For input operations, these ports are non-latching. Any input must be present until read by an input instruction 5.1 GPIO (e.g., MOVF GPIO, W). The outputs are latched and remain unchanged until the output latch is rewritten. To GPIO is an 8-bit I/O register. Only the low-order 4 bits use a port pin as output, the corresponding direction are used (GP<3:0>). Bits 7 through 4 are unimple- control bit in TRIS must be cleared (= 0). For use as an mented and read as ‘0’s. Please note that GP3 is an input, the corresponding TRIS bit must be set. Any I/O input only pin. Pins GP0, GP1 and GP3 can be config- pin (except GP3) can be programmed individually as ured with weak pull-ups and also for wake-up on input or output. change. The wake-up on change and weak pull-up functions are not individually pin selectable. If GP3/ FIGURE 5-1: EQUIVALENT CIRCUIT MCLR is configured as MCLR, a weak pull-up can be FOR A SINGLE I/O PIN enabled via the Configuration Word. Configuring GP3 Data as MCLR disables the wake-up on change function for Bus this pin. D Q Data WR Latch VDD VDD 5.2 TRIS Registers Port CK Q P (1) The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f W N I/O instruction. A ‘1’ from a TRIS register bit puts the corre- Reg pin sponding output driver in a High-Impedance mode. A D Q ‘0’ puts the contents of the output data latch on the TLaRtIcSh VSS VSS selected pins, enabling the output buffer. The excep- TRIS ‘f’ CK Q tions are GP3, which is input only, and the GP2/T0CKI/ FOSC4 pin, which may be controlled by various registers. See Table5-1. Reset (2) Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, RD Port but the external system is holding it low, a Note 1: I/O pins have protection diodes to VDD and read of the port will indicate that the pin is VSS. low. 2: See Table3-1 for buffer type. TABLE 5-1: ORDER OF PRECEDENCE FOR PIN FUNCTIONS Priority GP0 GP1 GP2 GP3 1 AN0 AN1 FOSC4 MCLR 2 TRIS GPIO TRIS GPIO T0CKI — 3 — — TRIS GPIO — TABLE 5-2: REQUIREMENTS TO MAKE PINS AVAILABLE IN DIGITAL MODE Bit GP0 GP1 GP2 GP3 FOSC4 — — 0 — T0CS — — 0 — ANS1 — 0 — — ANS0 0 — — — MCLRE — — — 0 Legend: — = Condition of bit will have no effect on the setting of the pin to Digital mode.  2005-2013 Microchip Technology Inc. DS40001270F-page 21

PIC10F220/222 FIGURE 5-2: BLOCK DIAGRAM OF GP0 FIGURE 5-3: BLOCK DIAGRAM OF GP2 AND GP1 Data I/O Pin(1) Bus GPPU D Q Data WR Latch Port CK Q FOSC4 Data W OSCCAL<0> Bus D Q Reg D Q Data TRIS WR Latch I/O Pin(1) Latch Port CK Q TRIS ‘f’ CK Q W Reset Reg D Q T0CS TRIS Latch TRIS ‘f’ CK Q RD Port Reset T0CKI Analog Enable Note 1: I/O pins have protection diodes to VDD and VSS. RD Port FIGURE 5-4: BLOCK DIAGRAM OF GP3 Q D GPPU CK MCLRE Mis-Match Reset ADC I/O Pin(1) Note 1: I/O pins have protection diodes to VDD and VSS. Data Bus RD Port Q D CK Mis-match Note 1: GP3/MCLR pin has a protection diode to VSS only. DS40001270F-page 22  2005-2013 Microchip Technology Inc.

PIC10F220/222 TABLE 5-3: SUMMARY OF PORT REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Resets Reset N/A TRISGPIO — — — — I/O Control Registers ---- 1111 ---- 1111 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS GPWUF — — TO PD Z DC C 0001 1xxx q00q quuu(1) 06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx ---- uuuu Legend: Shaded cells not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = depends on condition. Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. 5.4 I/O Programming Considerations EXAMPLE 5-1: I/O PORT READ-MODIFY- WRITE INSTRUCTIONS 5.4.1 BIDIRECTIONAL I/O PORTS ;Initial GPIO Settings Some instructions operate internally as read followed ;GPIO<3:2> Inputs by write operations. The BCF and BSF instructions, for ;GPIO<1:0> Outputs example, read the entire port into the CPU, execute the ; ; GPIO latch GPIO pins bit operation and re-write the result. Caution must be ; ---------- ---------- used when these instructions are applied to a port BCF GPIO, 1 ;---- pp01 ---- pp11 where one or more pins are used as input/outputs. For BCF GPIO, 0 ;---- pp10 ---- pp11 example, a BSF operation on bit 2 of GPIO will cause MOVLW 007h; all eight bits of GPIO to be read into the CPU, bit 2 to TRIS GPIO ;---- pp10 ---- pp11 be set and the GPIO value to be written to the output ; latches. If another bit of GPIO is used as a bidirectional Note: The user may have expected the pin values to I/O pin (say bit 0) and it is defined as an input at this be ---- pp00. The second BCF caused GP1 time, the input signal present on the pin itself would be to be latched as the pin value (High). read into the CPU and rewritten to the data latch of this 5.4.2 SUCCESSIVE OPERATIONS ON I/O particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. PORTS However, if bit 0 is switched into Output mode later on, The actual write to an I/O port happens at the end of an the content of the data latch may now be unknown. instruction cycle, whereas for reading, the data must be Example5-1 shows the effect of two sequential valid at the beginning of the instruction cycle (Figure5-5). Read-Modify-Write instructions (e.g., BCF, BSF, etc.) Therefore, care must be exercised if a write followed by on an I/O port. a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to A pin actively outputting a high or a low should not be stabilize (load dependent) before the next instruction driven from external devices at the same time in order causes that file to be read into the CPU. Otherwise, the to change the level on this pin (“wired-or”, “wired-and”). previous state of that pin may be read into the CPU rather The resulting high output currents may damage the than the new state. When in doubt, it is better to separate chip. these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-5: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 This example shows a write to GPIO followed Instruction by a read from GPIO. Fetched MOVWF GPIO MOVF GPIO, W NOP NOP Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle GP<2:0> TPD = propagation delay Port pin Port pin Therefore, at higher clock frequencies, a written here sampled here write followed by a read may be problematic. Instruction Executed MOVWF GPIO MOVF GPIO,W NOP (Write to GPIO) (Read GPIO)  2005-2013 Microchip Technology Inc. DS40001270F-page 23

PIC10F220/222 NOTES: DS40001270F-page 24  2005-2013 Microchip Technology Inc.

PIC10F220/222 6.0 TMR0 MODULE AND TMR0 Counter mode is selected by setting the T0CS bit REGISTER (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The The Timer0 module has the following features: T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restric- • 8-bit timer/counter register, TMR0 tions on the external clock input are discussed in detail • Readable and writable in Section6.1 “Using Timer0 With An External • 8-bit software programmable prescaler Clock”. • Internal or external clock select: The prescaler may be used by either the Timer0 - Edge select for external clock module or the Watchdog Timer, but not both. The Figure6-1 is a simplified block diagram of the Timer0 prescaler assignment is controlled in software by the module. control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not Timer mode is selected by clearing the T0CS bit readable or writable. When the prescaler is assigned to (OPTION<5>). In Timer mode, the Timer0 module will the Timer0 module, prescale values of 1:2, 1:4, 1:256 increment every instruction cycle (without prescaler). If are selectable. Section6.2 “Prescaler” details the TMR0 register is written, the increment is inhibited for operation of the prescaler. the following two cycles (Figure6-2 and Figure6-3). The user can work around this by writing an adjusted A summary of registers associated with the Timer0 value to the TMR0 register. module is found in Table6-1. FIGURE 6-1: TIMER0 BLOCK DIAGRAM Data Bus GP2/T0CKI FOSC/4 0 Pin PSOUT 8 1 Sync with 1 Internal TMR0 Reg Clocks PrPorgersacmalmera(2b)le 0 PSOUT T0SE (2 TCY delay) Sync 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure6-5). FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 (Program Counter) PC-1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2  2005-2013 Microchip Technology Inc. DS40001270F-page 25

PIC10F220/222 FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 (Program Counter) PC-1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 NT0 NT0 + 1 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets 01h TMR0 Timer0 – 8-Bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRISGPIO(1) — — — — I/O Control Register ---- 1111 ---- 1111 Legend: Shaded cells not used by Timer0, – = unimplemented, x = unknown, u = unchanged. Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1 6.1 Using Timer0 With An External 6.1.1 EXTERNAL CLOCK Clock SYNCHRONIZATION When no prescaler is used, the external clock input is When an external clock input is used for Timer0, it must the same as the prescaler output. The synchronization meet certain requirements. The external clock require- of T0CKI with the internal phase clocks is accom- ment is due to internal phase clock (TOSC) synchroniza- plished by sampling the prescaler output on the Q2 and tion. Also, there is a delay in the actual incrementing of Q4 cycles of the internal phase clocks (Figure6-4). Timer0 after synchronization. Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 2Tt0H) and low for at least 2TOSC (and a small RC delay of 2Tt0H). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling require- ment, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 4Tt0H) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of Tt0H. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. DS40001270F-page 26  2005-2013 Microchip Technology Inc.

PIC10F220/222 6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 mod- ule is actually incremented. Figure6-4 shows the delay from the external clock edge to the timer incrementing. FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output(2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4TOSC max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 6.2 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Section8.6 “Watch- dog Timer (WDT)”). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice-versa. The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a Reset, the prescaler contains all ‘0’s.  2005-2013 Microchip Technology Inc. DS40001270F-page 27

PIC10F220/222 6.2.1 SWITCHING PRESCALER To change prescaler from the WDT to the Timer0 ASSIGNMENT module, use the sequence shown in Example6-2. This sequence must be used even if the WDT is disabled. A The prescaler assignment is fully under software CLRWDT instruction should be executed before control (i.e., it can be changed “on-the-fly” during pro- switching the prescaler. gram execution). To avoid an unintended device Reset, the following instruction sequence (Example6-1) must EXAMPLE 6-2: CHANGING PRESCALER be executed when changing the prescaler assignment (WDTTIMER0) from Timer0 to the WDT. CLRWDT ;Clear WDT and EXAMPLE 6-1: CHANGING PRESCALER ;prescaler (TIMER0 WDT) MOVLW ‘xxxx0xxx’ ;Select TMR0, new ;prescale value and CLRWDT ;Clear WDT ;clock source CLRF TMR0 ;Clear TMR0 & Prescaler OPTION MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7) OPTION ;are required only if ;desired CLRWDT ;PS<2:0> are 000 or 001 MOVLW ‘00xx1xxx’b;Set Postscaler to OPTION ;desired WDT rate FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY (= FOSC/4) Data Bus GP2/T0CKI(2) 0 M 8 Pin U 1 M 1 X U Sy2nc TMR0 Reg 0 X Cycles T0SE(1) T0CS(1) PSA(1) 0 8-bit Prescaler M U X 1 8 Watchdog Timer 8-to-1 MUX PS<2:0>(1) PSA(1) 0 1 WDT Enable bit MUX PSA(1) WDT Time-Out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2: T0CKI is shared with pin GP2 on the PIC10F220/222. DS40001270F-page 28  2005-2013 Microchip Technology Inc.

PIC10F220/222 7.0 ANALOG-TO-DIGITAL (A/D) CONVERTER Note: The A/D Converter module consumes power when the ADON bit is set even The A/D converter allows conversion of an analog when no channels are selected as analog signal into an 8-bit digital signal. inputs. For low-power applications, it is recommended that the ADON bit be 7.1 Clock Divisors cleared when the A/D Converter is not in use. The A/D Converter has a single clock source setting, INTOSC/4. The A/D Converter requires 13 TAD periods 7.5 The GO/DONE bit to complete a conversion. The divisor values do not affect the number of TAD periods required to perform a The GO/DONE bit is used to determine the status of a conversion. The divisor values determine the length of conversion, to start a conversion and to manually halt a the TAD period. conversion in process. Setting the GO/DONE bit starts Note: Due to the fixed clock divisor, a conversion a conversion. When the conversion is complete, the A/ will complete in 13 CPU instruction cycles. D Converter module clears the GO/DONE bit. A con- version can be terminated by manually clearing the 7.2 Voltage Reference GO/DONE bit while a conversion is in process. Manual termination of a conversion may result in a partially Due to the nature of the design, there is no external converted result in ADRES. voltage reference allowed for the A/D Converter. The GO/DONE bit is cleared when the device enters TheA/D Converter reference voltage will always be Sleep, stopping the current conversion. The A/D Con- VDD. verter does not have a dedicated oscillator, it runs off of the system clock. 7.3 Analog Mode Selection The GO/DONE bit cannot be set when ADON is clear. The ANS<1:0> bits are used to configure pins for ana- log input. Upon any Reset ANS<1:0> defaults to 11. 7.6 Sleep This configures pins AN0 and AN1 as analog inputs. Pins configured as analog inputs are not available for This A/D Converter does not have a dedicated A/D digital output. Users should not change the ANS bits Converter clock and therefore no conversion in Sleep while a conversion is in process. ANS bits are active is possible. If a conversion is underway and a Sleep regardless of the condition of ADON. command is executed, the GO/DONE and ADON bit will be cleared. This will stop any conversion in process and power-down the A/D Converter module to con- 7.4 A/D Converter Channel Selection serve power. Due to the nature of the conversion pro- The CHS bits are used to select the analog channel to cess, the ADRES may contain a partial conversion. At be sampled by the A/D Converter. The CHS bits least 1 bit must have been converted prior to Sleep to should not be changed during a conversion. To have partial conversion data in ADRES. The CHS bits acquire an analog signal, the CHS selection must are reset to their default condition and CHS<1:0> = 11. match one of the pin(s) selected by the ANS bits. The For accurate conversions, TAD must meet the following: Internal Absolute Voltage Reference can be selected regardless of the condition of the ANS bits. All channel • 500ns < TAD < 50s selection information will be lost when the device • TAD = 1/(FOSC/divisor) enters Sleep. TABLE 7-1: EFFECTS OF SLEEP AND WAKE ON ADCON0 ANS1 ANS0 CHS1 CHS0 GO/DONE ADON Prior to Sleep x x x x 0 0 Prior to Sleep x x x x 1 1 Entering Sleep Unchanged Unchanged 1 1 0 0 Wake 1 1 1 1 0 0  2005-2013 Microchip Technology Inc. DS40001270F-page 29

PIC10F220/222 7.7 Analog Conversion Result 7.8 Internal Absolute Voltage Register Reference The ADRES register contains the results of the last The function of the Internal Absolute Voltage Refer- conversion. These results are present during the sam- ence is to provide a constant voltage for conversion pling period of the next analog conversion process. across the devices VDD supply range. The A/D Con- After the sampling period is over, ADRES is cleared (= verter is ratiometric with the conversion reference 0). A ‘leading one’ is then right shifted into the ADRES voltage being VDD. Converting a constant voltage of to serve as an internal conversion complete bit. As 0.6V (typical) will result in a result based on the voltage each bit weight, starting with the MSb, is converted, the applied to VDD of the device. The result of conversion leading one is shifted right and the converted bit is of this reference across the VDD range can be stuffed into ADRES. After a total of 9 right shifts of the approximated by: Conversion Result = 0.6V/(VDD/256) ‘leading one’ have taken place, the conversion is com- Note: The actual value of the Absolute Voltage plete; the ‘leading one’ has been shifted out and the Reference varies with temperature and GO/DONE bit is cleared. part-to-part variation. The conversion is If the GO/DONE bit is cleared in software during a con- also susceptible to analog noise on the version, the conversion stops. The data in ADRES is VDD pin and noise generated by the sink- the partial conversion result. This data is valid for the bit ing or sourcing of current on the I/O pins. weights that have been converted. The position of the ‘leading one’ determines the number of bits that have been converted. The bits that were not converted before the GO/DONE was cleared are unrecoverable. REGISTER 7-1: ADCON0: A/D CONVERTER 0 REGISTER R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-0 ANS1 ANS0 — — CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ANS1: ADC Analog Input Pin Select bit 1 = GP1/AN1 configured for analog input 0 = GP1/AN1 configured as digital I/O bit 6 ANS0: ADC Analog Input Pin Select bit(1), (2) 1 = GP0/AN0 configured as an analog input 0 = GP0/AN0 configured as digital I/O bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CHS<1:0>: ADC Channel Select bits(3) 00 = Channel 00 (GP0/AN0) 01 = Channel 01 (GP1/AN1) 1X = 0.6V absolute Voltage reference bit 1 GO/DONE: ADC Conversion Status bit(4) 1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC is done converting. 0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process terminates the current conversion. bit 0 ADON: ADC Enable bit 1 = ADC module is operating 0 = ADC module is shut-off and consumes no power Note 1: When the ANS bits are set, the channel(s) selected are automatically forced into analog mode regardless of the pin function previously defined. 2: The ANS<1:0> bits are active regardless of the condition of ADON 3: CHS<1:0> bits default to 11 after any Reset. 4: If the ADON bit is clear, the GO/DONE bit cannot be set. DS40001270F-page 30  2005-2013 Microchip Technology Inc.

PIC10F220/222 REGISTER 7-2: ADRES: ANALOG CONVERSION RESULT REGISTER R-X R-X R-X R-X R-X R-X R-X R-X ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>  2005-2013 Microchip Technology Inc. DS40001270F-page 31

PIC10F220/222 7.9 A/D Acquisition Requirements After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion For the ADC to meet its specified accuracy, the charge can be started. To calculate the minimum acquisition holding capacitor (CHOLD) must be allowed to fully time, Equation7-1 may be used. This equation charge to the input channel voltage level. The Analog assumes that 1/2 LSb error is used (256 steps for the Input model is shown in Figure7-1. The source ADC). The 1/2 LSb error is the maximum error allowed impedance (RS) and the internal sampling switch (RSS) for the ADC to meet its specified resolution. impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure7-1. The maximum recommended impedance for analog sources is 10k. As the source impedance is decreased, the acquisition time may be decreased. EQUATION 7-1: ACQUISITION TIME EXAMPLE Assumptions: Temperature = 50°C and external impedance of 10k 5.0V VDD Tacq = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [(Temperature - 25°C)(0.05s/°C)] Solving for Tc: Tc = CHOLD (RIC + RSS + RS) In(1/512) = -25pF (lk + 7k + 10k ) In(0.00196) = 2.81s Therefore: Tacq = 2s + 2.81s + [(50°C-25°C)(0.05s/°C)] = 6.06s Note1: The charge holding capacitor (CHOLD) is not discharged after each conversion. 2: The maximum recommended impedance for analog sources is 10k. This is required to meet the pin leakage specification. FIGURE 7-1: ANALOG INPUT MODULE VDD Sampling Switch VT = 0.6V Rs ANx RIC  1k SS Rss VA C5 PpIFN VT = 0.6V I± L5E0A0K AnGAE CHOLD = 25 pF VSS/VREF- 6V Legend: CPIN = Input Capacitance 5V RSS VDD4V VT = Threshold Voltage 3V ILEAKAGE = Leakage current at the pin due 2V to various junctions RIC = Interconnect Resistance 5 6 7 891011 SS = Sampling Switch Sampling Switch CHOLD = Sample/Hold Capacitance (k) DS40001270F-page 32  2005-2013 Microchip Technology Inc.

PIC10F220/222 8.0 SPECIAL FEATURES OF THE The PIC10F220/222 devices have a Watchdog Timer, CPU which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reli- What sets a microcontroller apart from other proces- ability. When using DRT, there is an 1.125ms (typical) sors are special circuits that deal with the needs of real- delay only on VDD power-up. With this timer on-chip, time applications. The PIC10F220/222 microcontrol- most applications need no external Reset circuitry. lers have a host of such features intended to maximize The Sleep mode is designed to offer a very low current system reliability, minimize cost through elimination of Power-Down mode. The user can wake-up from Sleep external components, provide power-saving operating through a change on input pins or through a Watchdog modes and offer code protection. These features are: Timer time-out. • Reset: - Power-on Reset (POR) 8.1 Configuration Bits - Device Reset Timer (DRT) The PIC10F220/222 Configuration Words consist of 12 - Watchdog Timer (WDT) bits. Configuration bits can be programmed to select - Wake-up from Sleep on pin change various device configurations. One bit is the Watchdog • Sleep Timer enable bit, one bit is the MCLR enable bit and one bit is for code protection (see Register8-1). • Code Protection • ID Locations • In-Circuit Serial Programming™ • Clock Out REGISTER 8-1: CONFIG: CONFIGURATION WORD(1) — — — — — — — MCLRE CP WDTE MCPU IOSCFS bit 11 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 11-5 Unimplemented: Read as ‘0’ bit 4 MCLRE: GP3/MCLR Pin Function Select bit 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 3 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1 MCPU: Master Clear Pull-up Enable bit(2) 1 = Pull-up disabled 0 = Pull-up enabled bit 0 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8MHz 0 = 4MHz Note 1: Refer to the “PIC10F220/222 Memory Programming Specification” (DS41266), to determine how to access the Configuration Word. The Configuration Word is not user addressable during device operation. 2: MCLRE must be a ‘1’ to enable this selection.  2005-2013 Microchip Technology Inc. DS40001270F-page 33

PIC10F220/222 8.2 Oscillator Configurations 8.3 Reset 8.2.1 OSCILLATOR TYPES The device differentiates between various kinds of Reset: The PIC10F220/222 devices are offered with internal • Power-on Reset (POR) oscillator mode only. • MCLR Reset during normal operation • INTOSC: Internal 4/8MHz Oscillator • MCLR Reset during Sleep 8.2.2 INTERNAL 4/8MHz OSCILLATOR • WDT Time-out Reset during normal operation The internal oscillator provides a 4/8MHz (nominal) • WDT Time-out Reset during Sleep system clock (see Section10.0 “Electrical Charac- • Wake-up from Sleep on pin change teristics” for information on variation over voltage and Some registers are not reset in any way, they are temperature). unknown on POR and unchanged in any other Reset. In addition, a calibration instruction is programmed into Most other registers are reset to “Reset state” on the last address of memory, which contains the calibra- Power-on Reset (POR), MCLR, WDT or Wake-up on tion value for the internal oscillator. This location is pin change Reset during normal operation. They are always uncode protected, regardless of the code-pro- not affected by a WDT Reset during Sleep or MCLR tect settings. This value is programmed as a MOVLW XX Reset during Sleep, since these Resets are viewed as instruction where XX is the calibration value and is resumption of normal operation. The exceptions to this placed at the Reset vector. This will load the W register are TO, PD and GPWUF bits. They are set or cleared with the calibration value upon Reset and the PC will differently in different Reset situations. These bits are then roll over to the users program at address 0x000. used in software to determine the nature of Reset. See The user then has the option of writing the value to the Table8-1 for a full description of Reset states of all OSCCAL Register (05h) or ignoring it. registers. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. Note: Erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. TABLE 8-1: RESET CONDITIONS FOR REGISTERS – PIC10F220/222 Register Address Power-on Reset MCLR Reset, WDT Time-out, Wake-up On Pin Change, W — qqqq qqqu(1) qqqq qqqu(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0--1 1xxx q00q quuu FSR 04h 111x xxxx 111u uuuu OSCCAL 05h 1111 1110 uuuu uuuu GPIO 06h ---- xxxx ---- uuuu ADCON0 07h 11-- 1100 11-- 1100 ADRES 08h xxxx xxxx uuuu uuuu OPTION — 1111 1111 1111 1111 TRIS — ---- 1111 ---- 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. DS40001270F-page 34  2005-2013 Microchip Technology Inc.

PIC10F220/222 TABLE 8-2: RESET CONDITION FOR SPECIAL REGISTERS STATUS Addr: 03h PCL Addr: 02h Power-on Reset 0--1 1xxx 1111 1111 MCLR Reset during normal operation 0--u uuuu 1111 1111 MCLR Reset during Sleep 0--1 0uuu 1111 1111 WDT Reset during Sleep 0--0 0uuu 1111 1111 WDT Reset normal operation 0--0 uuuu 1111 1111 Wake-up from Sleep on pin change 1--1 0uuu 1111 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’. 8.3.1 MCLR ENABLE The Power-on Reset circuit and the Device Reset Timer (see Section8.5 “Device Reset Timer (DRT)”) This Configuration bit, when unprogrammed (left in the circuit are closely related. On power-up, the Reset latch ‘1’ state), enables the external MCLR function. When is set and the DRT is reset. The DRT timer begins programmed, the MCLR function is tied to the internal counting once it detects MCLR to be high. After the VDD and the pin is assigned to be a I/O. See Figure8-1. time-out period, which is typically 1.125ms, it will reset the Reset latch and thus end the on-chip Reset signal. FIGURE 8-1: MCLR SELECT A power-up example where MCLR is held low is shown in Figure8-3. VDD is allowed to rise and stabilize before GPWU Weak Pull-up bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. GP3/MCLR/VPP In Figure8-4, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together or the pin MCLRE Internal MCLR is programmed to be GP3). The VDD is stable before the Start-up timer times out and there is no problem in getting a proper Reset. However, Figure8-5 depicts a problem situation where VDD rises too slowly. The time 8.4 Power-on Reset (POR) between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value, is The PIC10F220/222 devices incorporate an on-chip too long. In this situation, when the start-up timer times Power-on Reset (POR) circuitry, which provides an out, VDD has not reached the VDD (min) value and the internal chip Reset for most power-up situations. chip may not function correctly. For such situations, we recommend that external RC circuits be used to The on-chip POR circuit holds the chip in Reset until achieve longer POR delay times (Figure8-4). VDD has reached a high enough level for proper oper- ation. To take advantage of the internal POR, program Note: When the devices start normal operation the GP3/MCLR/VPP pin as MCLR and tie through a (exit the Reset condition), device operat- resistor to VDD, or program the pin as GP3. An internal ing parameters (voltage, frequency, tem- weak pull-up resistor is implemented using a transistor perature, etc.) must be met to ensure (refer to Table10-1 for the pull-up resistor ranges). This proper operation. If these conditions are will eliminate external RC components usually needed not met, the device must be held in Reset to create a Power-on Reset. until the operating conditions are met. When the devices start normal operation (exit the For additional information on design considerations Reset condition), device operating parameters (volt- related to the use of PIC10F220/222 devices with their age, frequency, temperature,...) must be met to ensure short device Reset timer, refer to Application Notes operation. If these conditions are not met, the devices AN522, “Power-Up Considerations” (DS00522) and must be held in Reset until the operating parameters AN607, “Power-up Trouble Shooting” (DS00607). are met. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure8-2.  2005-2013 Microchip Technology Inc. DS40001270F-page 35

PIC10F220/222 FIGURE 8-2: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) GP3/MCLR/VPP MCLR Reset S Q MCLRE R Q WDT Reset WDT Time-out Start-up Timer CHIP Reset 1.125ms Pin Change Sleep Wake-up on pin Change Reset FIGURE 8-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 8-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR Internal POR TDRT DRT Time-out Internal Reset DS40001270F-page 36  2005-2013 Microchip Technology Inc.

PIC10F220/222 FIGURE 8-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1  VDD min.  2005-2013 Microchip Technology Inc. DS40001270F-page 37

PIC10F220/222 8.5 Device Reset Timer (DRT) 8.6.1 WDT PERIOD On the PIC10F220/222 devices, the DRT runs any time The WDT has a nominal time-out period of 18ms, (with the device is powered up. no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be The DRT operates on an internal oscillator. The pro- assigned to the WDT (under software control) by writ- cessor is kept in Reset as long as the DRT is active. ing to the OPTION register. Thus, a time-out period of The DRT delay allows VDD to rise above VDD min. and a nominal 2.3 seconds can be realized. These periods for the oscillator to stabilize. vary with temperature, VDD and part-to-part process The on-chip DRT keeps the devices in a Reset condi- variations (see DC specs). tion for approximately 1.125ms after MCLR has Under worst-case conditions (VDD = Min., Temperature reached a logic high (VIH MCLR) level. Programming = Max., max. WDT prescaler), it may take several GP3/MCLR/VPP as MCLR and using an external RC seconds before a WDT time-out occurs. network connected to the MCLR input is not required in most cases. This allows savings in cost-sensitive and/ 8.6.2 WDT PROGRAMMING or space restricted applications, as well as allowing the CONSIDERATIONS use of the GP3/MCLR/VPP pin as a general purpose input. The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from The Device Reset Time delays will vary from chip-to- timing out and generating a device Reset. chip due to VDD, temperature and process variation. See AC parameters for details. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the Reset sources are POR, MCLR, WDT time-out and maximum Sleep time before a WDT wake-up Reset. wake-up on pin change. See Section8.9.2 “Wake-up from Sleep”, Notes 1, 2 and 3. TABLE 8-3: DRT (DEVICE RESET TIMER PERIOD) POR Reset Subsequent Resets 1.125ms (typical) 10s (typical) 8.6 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the internal 4/8MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruc- tion. During normal operation or Sleep, a WDT Reset or wake-up Reset, generates a device Reset. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by program- ming the configuration WDTE as a ‘0’ (see Section8.1 “Configuration Bits”). Refer to the PIC10F220/222 Programming Specification to determine how to access the Configuration Word. DS40001270F-page 38  2005-2013 Microchip Technology Inc.

PIC10F220/222 FIGURE 8-6: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure6-5) 0 M Watchdog 1 U PPoossttssccaalleerr Timer X 3 8-to-1 MUX PS<2:0> PSA WDT Enable Configuration To Timer0 (Figure6-4) Bit 0 1 MUX PSA WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. TABLE 8-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u = unchanged. 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO/PD/GPWUF/CWUF) The TO, PD and GPWUF bits in the STATUS register can be tested to determine if a Reset condition has been caused by a Power-up condition, a MCLR, Watchdog Timer (WDT) Reset or wake-up on pin change. TABLE 8-5: TO/PD/GPWUF STATUS AFTER RESET GPWUF TO PD Reset Caused By 0 0 0 WDT wake-up from Sleep 0 0 u WDT time-out (not from Sleep) 0 1 0 MCLR wake-up from Sleep 0 1 1 Power-up 0 u u MCLR not during Sleep 1 1 0 Wake-up from Sleep on pin change Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: The TO, PD and GPWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR input does not change the TO, PD or GPWUF Status bits.  2005-2013 Microchip Technology Inc. DS40001270F-page 39

PIC10F220/222 8.8 Reset on Brown-out FIGURE 8-9: BROWN-OUT PROTECTION CIRCUIT 3 A Brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then VDD recovers. The device should be reset in the event of a Brown-out. MCP809 Bypass VDD VSS Capacitor To reset PIC10F220/222 devices when a Brown-out VDD occurs, external Brown-out protection circuits may be RST (2) built, as shown in Figure8-7 and Figure8-8. MCLR PIC10F22X FIGURE 8-7: BROWN-OUT PROTECTION CIRCUIT 1 Note 1: This Brown-out Protection circuit employs VDD Microchip Technology’s MCP809 micro- controller supervisor. There are 7 different VDD trip point selections to accommodate 5V to 33k 3V systems. 2: Pin must be configured as MCLR. PIC10F22X 10k Q1 MCLR(2) 40k(1) 8.9 Power-down Mode (Sleep) A device may be powered down (Sleep) and later powered up (wake-up from Sleep). Note 1: This circuit will activate Reset when VDD goes 8.9.1 SLEEP below Vz + 0.7V (where Vz = Zener voltage). 2: Pin must be configured as MCLR. The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but FIGURE 8-8: BROWN-OUT keeps running, the TO bit (STATUS<4>) is set, the PD PROTECTION CIRCUIT 2 bit (STATUS<3>) is cleared and the oscillator driver is VDD turned off. The I/O ports maintain the status they had VDD before the SLEEP instruction was executed (driving high, driving low or high-impedance). R1 PIC10F22X Note: A Reset generated by a WDT time-out Q1MCLR(2) does not drive the MCLR pin low. R2 40k(1) For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the GP3/ MCLR/VPP pin must be at a logic high level if MCLR is enabled. Note 1: This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 VDD • = 0.7V R1 + R2 2: Pin must be configured as MCLR. DS40001270F-page 40  2005-2013 Microchip Technology Inc.

PIC10F220/222 8.9.2 WAKE-UP FROM SLEEP 8.12 In-Circuit Serial Programming™ The device can wake-up from Sleep through one of the The PIC10F220/222 microcontrollers can be serially following events: programmed while in the end application circuit. This is 1. An external Reset input on GP3/MCLR/VPP pin, simply done with two lines for clock and data, and three when configured as MCLR. other lines for power, ground and the programming 2. A Watchdog Timer Time-out Reset (if WDT was voltage. This allows customers to manufacture boards enabled). with unprogrammed devices and then program the microcontroller just before shipping the product. This 3. A change on input pin GP0, GP1 or GP3 when also allows the most recent firmware, or a custom wake-up on change is enabled. firmware, to be programmed. These events cause a device Reset. The TO, PD The devices are placed into a Program/Verify mode by GPWUF bits can be used to determine the cause of a holding the GP1 and GP0 pins low while raising the device Reset. The TO bit is cleared if a WDT time-out MCLR (VPP) pin from VIL to VIHH (see programming occurred (and caused wake-up). The PD bit, which is specification). GP1 becomes the programming clock set on power-up, is cleared when SLEEP is invoked. and GP0 becomes the programming data. Both GP1 The GPWUF bit indicates a change in state while in and GP0 are Schmitt Trigger inputs in this mode. Sleep at pins GP0, GP1 or GP3 (since the last file or bit operation on GP port). After Reset, a 6-bit command is then supplied to the device. Depending on the command, 16 bits of program Caution: Right before entering Sleep, read the data are then supplied to or from the device, depending input pins. When in Sleep, wake up if the command was a Load or a Read. For complete occurs when the values at the pins details of serial programming, please refer to the change from the state they were in at the PIC10F220/222 Programming Specifications. last reading. If a wake-up on change occurs and the pins are not read before A typical In-Circuit Serial Programming connection is re-entering Sleep, a wake-up will occur shown in Figure8-10. immediately even if no pins change while in Sleep mode. FIGURE 8-10: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING™ Note: The WDT is cleared when the device CONNECTION wakes from Sleep, regardless of the wake- up source. To Normal Connections External 8.10 Program Verification/Code Connector PIC10F22X Signals Protection +5V VDD If the Code Protection bit has not been programmed, 0V VSS the on-chip program memory can be read out for VPP MCLR/VPP verification purposes. The first 64 locations and the last location (Reset CLK GP1 Vector) can be read, regardless of the code protection bit setting. Data I/O GP0 8.11 ID Locations VDD Four memory locations are designated as ID locations To Normal where the user can store checksum or other code Connections identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as ‘1’s.  2005-2013 Microchip Technology Inc. DS40001270F-page 41

PIC10F220/222 NOTES: DS40001270F-page 42  2005-2013 Microchip Technology Inc.

PIC10F220/222 9.0 INSTRUCTION SET SUMMARY All instructions are executed within a single instruction cycle, unless a conditional test is true or the program The PIC16 instruction set is highly orthogonal and is counter is changed as a result of an instruction. In this comprised of three basic categories. case, the execution takes two instruction cycles. One • Byte-oriented operations instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4MHz, the normal • Bit-oriented operations instruction execution time is 1s. If a conditional test is • Literal and control operations true or the program counter is changed as a result of an Each PIC16 instruction is a 12-bit word divided into an instruction, the instruction execution time is 2s. opcode, which specifies the instruction type, and one Figure9-1 shows the three general formats that the or more operands which further specify the operation instructions can have. All examples in the figure use of the instruction. The formats for each of the catego- the following format to represent a hexadecimal ries is presented in Figure9-1, while the various number: opcode fields are summarized in Table9-1. ‘0xhhh’ For byte-oriented instructions, ‘f’ represents a file reg- ister designator and ‘d’ represents a destination desig- where ‘h’ signifies a hexadecimal digit. nator. The file register designator specifies which file register is to be used by the instruction. FIGURE 9-1: GENERAL FORMAT FOR INSTRUCTIONS The destination designator specifies where the result of the operation is to be placed. If ‘d’ is ‘0’, the result is Byte-oriented file register operations placed in the W register. If ‘d’ is ‘1’, the result is placed 11 6 5 4 0 in the file register specified in the instruction. OPCODE d f (FILE #) For bit-oriented instructions, ‘b’ represents a bit field d = 0 for destination W designator which selects the number of the bit affected d = 1 for destination f by the operation, while ‘f’ represents the number of the f = 5-bit file register address file in which the bit is located. Bit-oriented file register operations For literal and control operations, ‘k’ represents an 11 8 7 5 4 0 8or 9-bit constant or literal value. OPCODE b (BIT #) f (FILE #) TABLE 9-1: OPCODE FIELD b = 3-bit address DESCRIPTIONS f = 5-bit file register address Field Description Literal and control operations (except GOTO) f Register file address (0x00 to 0x7F) 11 8 7 0 W Working register (accumulator) OPCODE k (literal) b Bit address within an 8-bit file register k = 8-bit immediate value k Literal field, constant data or label x Don’t care location (= 0 or 1) Literal and control operations – GOTO instruction The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all 11 9 8 0 Microchip software tools. OPCODE k (literal) d Destination select; d = 0 (store result in W) k = 9-bit immediate value d = 1 (store result in file register ‘f’) Default is d = 1 label Label name TOS Top-of-Stack PC Program Counter WDT Watchdog Timer counter TO Time-out bit PD Power-down bit dest Destination, either the W register or the specified register file location [ ] Options ( ) Contents  Assigned to < > Register bit field  In the set of italics User defined term (font is courier)  2005-2013 Microchip Technology Inc. DS40001270F-page 43

PIC10F220/222 TABLE 9-2: INSTRUCTION SET SUMMARY Mnemonic, 12-Bit Opcode Status Description Cycles Notes Operands Affected MSb LSb ADDWF f, d Add W and f 1 0001 11df ffff C,DC,Z 1,2,4 ANDWF f, d AND W with f 1 0001 01df ffff Z 2,4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW – Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2,4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2,4 INCF f, d Increment f 1 0010 10df ffff Z 2,4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2,4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2,4 MOVF f, d Move f 1 0010 00df ffff Z 2,4 MOVWF f Move W to f 1 0000 001f ffff None 1,4 NOP – No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2,4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2,4 SUBWF f, d Subtract W from f 1 0000 10df ffff C,DC,Z 1,2,4 SWAPF f, d Swap f 1 0011 10df ffff None 2,4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2,4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2,4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2,4 BTFSC f, b Bit Test f, Skip if Clear 1(2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1(2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call subroutine 2 1001 kkkk kkkk None 1 CLRWDT k Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z MOVLW k Move Literal to W 1 1100 kkkk kkkk None OPTION – Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk None SLEEP – Go into standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for GOTO. See Section4.7 “Program Counter”. 2: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tri-state latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS40001270F-page 44  2005-2013 Microchip Technology Inc.

PIC10F220/222 9.1 Instruction Description ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BCF f,b Operands: 0  f  31 Operands: 0  f  31 d  0  b  7 Operation: (W) + (f)  (destination) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is cleared. and register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BSF Bit Set f Syntax: [ label ] ANDLW k Syntax: [ label ] BSF f,b Operands: 0  k  255 Operands: 0  f  31 0  b  7 Operation: (W).AND. (k)  (W) Operation: 1  (f<b>) Status Affected: Z Status Affected: None Description: The contents of the W register are AND’ed with the eight-bit literal ‘k’. Description: Bit ‘b’ in register ‘f’ is set. The result is placed in the W register. ANDWF AND W with f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b Operands: 0  f  31 Operands: 0  f  31 d [0,1] 0  b  7 Operation: (W) AND (f)  (destination) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of the W register are Description: If bit ‘b’ in register ‘f’ is ‘0’, then the AND’ed with register ‘f’. If ‘d’ is ‘0’, next instruction is skipped. the result is stored in the W register. If bit ‘b’ is ‘0’, then the next instruc- If ‘d’ is ‘1’, the result is stored back tion fetched during the current in register ‘f’. instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction.  2005-2013 Microchip Technology Inc. DS40001270F-page 45

PIC10F220/222 BTFSS Bit Test f, Skip if Set CLRW Clear W Syntax: [ label ] CLRW Syntax: [ label ] BTFSS f,b Operands: None Operands: 0  f  31 0  b < 7 Operation: 00h  (W); 1  Z Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The W register is cleared. Zero bit Description: If bit ‘b’ in register ‘f’ is ‘1’, then the (Z) is set. next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruc- tion fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. CALL Subroutine Call CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT k Operands: 0  k  255 Operands: None Operation: (PC) + 1 Top of Stack; Operation: 00h  WDT; k  PC<7:0>; 0  WDT prescaler (if assigned); (Status<6:5>)  PC<10:9>; 1  TO; 0  PC<8> 1  PD Status Affected: None Status Affected: TO, PD Description: Subroutine call. First, return Description: The CLRWDT instruction resets the address (PC + 1) is pushed onto WDT. It also resets the prescaler, if the stack. The eight-bit immediate the prescaler is assigned to the address is loaded into PC bits WDT and not Timer0. Status bits <7:0>. The upper bits PC<10:9> TO and PD are set. are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a two- cycle instruction. CLRF Clear f COMF Complement f Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] Operation: 00h  (f); 1  Z Operation: (f)  (dest) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are cleared and the Z bit is set. complemented. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001270F-page 46  2005-2013 Microchip Technology Inc.

PIC10F220/222 DECF Decrement f INCF Increment f Syntax: [ label ] DECF f,d Syntax: [ label ] INCF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: (f) – 1  (dest) Operation: (f) + 1  (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, Description: The contents of register ‘f’ are the result is stored in the W incremented. If ‘d’ is ‘0’, the result register. If ‘d’ is ‘1’, the result is is placed in the W register. If ‘d’ is stored back in register ‘f’. ‘1’, the result is placed back in register ‘f’. DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: (f) – 1  d; skip if result = 0 Operation: (f) + 1  (dest), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are dec- Description: The contents of register ‘f’ are remented. If ‘d’ is ‘0’, the result is incremented. If ‘d’ is ‘0’, the result placed in the W register. If ‘d’ is ‘1’, is placed in the W register. If ‘d’ is the result is placed back in register ‘1’, the result is placed back in ‘f’. register ‘f’. If the result is ‘0’, the next instruc- If the result is ‘0’, then the next tion, which is already fetched, is instruction, which is already discarded and a NOP is executed fetched, is discarded and a NOP is instead making it a two-cycle executed instead making it a two- instruction. cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  511 Operands: 0  k  255 Operation: k  PC<8:0>; Operation: (W) .OR. (k)  (W) STATUS<6:5>  PC<10:9> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’. The 9-bit immediate value is The result is placed in the W loaded into PC bits <8:0>. The register. upper bits of PC are loaded from STATUS<6:5>. GOTO is a two- cycle instruction.  2005-2013 Microchip Technology Inc. DS40001270F-page 47

PIC10F220/222 IORWF Inclusive OR W with f MOVWF Move W to f Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f Operands: 0  f  31 Operands: 0  f  31 d  [0,1] Operation: (W)  (f) Operation: (W).OR. (f)  (dest) Status Affected: None Status Affected: Z Description: Move data from the W register to Description: Inclusive OR the W register with register ‘f’. register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0  f  31 Operands: None d  [0,1] Operation: No operation Operation: (f)  (dest) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register ‘f’ are moved to destination ‘d’. If ‘d’ is ‘0’, destination is the W register. If ‘d’ is ‘1’, the destination is file register ‘f’. ‘d’ = 1 is useful as a test of a file register, since status flag Z is affected. MOVLW Move Literal to W OPTION Load OPTION Register Syntax: [ label ] MOVLW k Syntax: [ label ] OPTION Operands: 0  k  255 Operands: None Operation: k  (W) Operation: (W)  OPTION Status Affected: None Status Affected: None Description: The content of the W register is Description: The eight-bit literal ‘k’ is loaded loaded into the OPTION register. into the W register. The “don’t cares” will assembled as ‘0’s. DS40001270F-page 48  2005-2013 Microchip Technology Inc.

PIC10F220/222 RETLW Return with Literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] RETLW k Syntax: [label] SLEEP Operands: 0  k  255 Operands: None Operation: k  (W); Operation: 00h  WDT; TOS  PC 0  WDT prescaler; Status Affected: None 1  TO; 0  PD Description: The W register is loaded with the eight-bit literal ‘k’. The program Status Affected: TO, PD, RBWUF counter is loaded from the top of Description: Time-out Status bit (TO) is set. The the stack (the return address). This Power-down Status bit (PD) is is a two-cycle instruction. cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See section on Sleep for more details. RLF Rotate Left f through Carry SUBWF Subtract W from f Syntax: [ label ] RLF f,d Syntax: [label] SUBWF f,d Operands: 0  f  31 Operands: 0 f 31 d  [0,1] d  [0,1] Operation: See description below Operation: (f) – (W) dest) Status Affected: C Status Affected: C, DC, Z Description: The contents of register ‘f’ are Description: Subtract (2’s complement method) rotated one bit to the left through the W register from register ‘f’. If ‘d’ the Carry Flag. If ‘d’ is ‘0’, the is ‘0’, the result is stored in the W result is placed in the W register. If register. If ‘d’ is ‘1’, the result is ‘d’ is ‘1’, the result is stored back in stored back in register ‘f’. register ‘f’. C register ‘f’ RRF Rotate Right f through Carry SWAPF Swap Nibbles in f Syntax: [ label ] RRF f,d Syntax: [label] SWAPF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: See description below Operation: (f<3:0>)  (dest<7:4>); (f<7:4>)  (dest<3:0>) Status Affected: C Status Affected: None Description: The contents of register ‘f’ are rotated one bit to the right through Description: The upper and lower nibbles of the Carry Flag. If ‘d’ is ‘0’, the register ‘f’ are exchanged. If ‘d’ is result is placed in the W register. If ‘0’, the result is placed in W ‘d’ is ‘1’, the result is placed back register. If ‘d’ is ‘1’, the result is in register ‘f’. placed in register ‘f’. C register ‘f’  2005-2013 Microchip Technology Inc. DS40001270F-page 49

PIC10F220/222 TRIS Load TRIS Register Syntax: [ label ] TRIS f Operands: f = 6 Operation: (W)  TRIS register f Status Affected: None Description: TRIS register ‘f’ (f = 6 or 7) is loaded with the contents of the W register XORLW Exclusive OR literal with W Syntax: [label] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. XORWF Exclusive OR W with f Syntax: [ label ] XORWF f,d Operands: 0  f  31 d  [0,1] Operation: (W) .XOR. (f) dest) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001270F-page 50  2005-2013 Microchip Technology Inc.

PIC10F220/222 10.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature...............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS..................................................................................................................0 to +6.5V Voltage on MCLR with respect to VSS.............................................................................................................0 to +13.5V Voltage on all other pins with respect to VSS..................................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1).....................................................................................................................................800mW Max. current out of VSS pin.....................................................................................................................................80mA Max. current into VDD pin........................................................................................................................................80mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Max. output current sunk by any I/O pin.................................................................................................................25mA Max. output current sourced by any I/O pin............................................................................................................25mA Max. output current sourced by I/O port .................................................................................................................75mA Max. output current sunk by I/O port ......................................................................................................................75mA Note1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} ..+ (VOL x IOL) †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2005-2013 Microchip Technology Inc. DS40001270F-page 51

PIC10F220/222 FIGURE 10-1: VOLTAGE-FREQUENCY GRAPH, -40C  TA  +125C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 25 Frequency (MHz) DS40001270F-page 52  2005-2013 Microchip Technology Inc.

PIC10F220/222 10.1 DC Characteristics: PIC10F220/222 (Industrial) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature -40×C  TA  +85C (industrial) Param Sym Characteristic Min Typ(1) Max Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure10-1 D002 VDR RAM Data Retention Voltage(2) 1.5* — — V Device in Sleep mode D003 VPOR VDD Start Voltage — Vss — V to ensure Power-on Reset D004 SVDD VDD Rise Rate 0.05* — — V/ms to ensure Power-on Reset IDD Supply Current(3) D010 — 175 275 A VDD = 2.0V, Fosc = 4 MHz — 0.625 1.1 mA VDD = 5.0V, Fosc = 4 MHz — 250 400 A VDD = 2.0V, Fosc = 8 MHz — 0.800 1.5 mA VDD = 5.0V, Fosc = 8 MHz IPD Power-down Current(4) D020 — 0.1 1.2 A VDD = 2.0V — 1 2.4 A VDD = 5.0V IWDT WDT Current(4) D022 — 1.0 3 A VDD = 2.0V — 7 16 A VDD = 5.0V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. 4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS. The peripheral current is the sum of the base IPD and the additional current consumed when the peripheral is enabled.  2005-2013 Microchip Technology Inc. DS40001270F-page 53

PIC10F220/222 10.2 DC Characteristics: PIC10F220/222 (Extended) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature -40×C £ TA £ +125×C (extended) Param Sym Characteristic Min Typ(1) Max Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure10-1 D002 VDR RAM Data Retention Voltage(2) 1.5* — V Device in Sleep mode D003 VPOR VDD Start Voltage — Vss — V to ensure Power-on Reset IDD Supply Current(3) D010 — 175 275 A VDD = 2.0V, Fosc = 4 MHz — 0.625 1.1 mA VDD = 5.0V, Fosc = 4 MHz — 250 400 A VDD = 2.0V, Fosc = 8 MHz — 0.800 1.5 mA VDD = 5.0V, Fosc = 8 MHz IPD Power-down Current(4) D020 — 0.1 9 A VDD = 2.0V — 1 15 A VDD = 5.0V IWDT WDT Current(4) D022 — 1.0 18 A VDD = 2.0V — 7 22 A VDD = 5.0V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. 4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS. The peripheral current is the sum of the base IPD and the additional current consumed when the peripheral is enabled. DS40001270F-page 54  2005-2013 Microchip Technology Inc.

PIC10F220/222 10.3 DC Characteristics: PIC10F220/222 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C  TA  +85°C (industrial) DC CHARACTERISTICS -40°C  TA  +125°C (extended) Operating voltage VDD range as described in DC specification Param Sym Characteristic Min Typ† Max Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer Vss — 0.8 V For all 4.5  VDD 5.5V D030A Vss — 0.15 VDD V Otherwise D031 with Schmitt Trigger Vss — 0.2 VDD V buffer D032 MCLR, T0CKI Vss — 0.2 VDD V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5  VDD 5.5V D040A 0.25 VDD + 0.8 — VDD V Otherwise D041 with Schmitt Trigger 0.8VDD — VDD V For entire VDD range buffer D042 MCLR, T0CKI 0.8VDD — VDD V D070 IPUR GPIO weak pull-up current 50 250 400 A VDD = 5V, VPIN = VSS IIL Input Leakage Current(1) D060 I/O ports — ±0.1 ± 1 A Vss VPIN VDD, Pin at high-imped- ance D061 GP3/MCLR(2) — ±0.7 ± 5 A Vss VPIN VDD Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C Output High Voltage D090 I/O ports(2) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D090A VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C Capacitive Loading Specs on Output Pins D101 All I/O pins — — 50* pF † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. * These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as coming out of the pin. 2: This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic.  2005-2013 Microchip Technology Inc. DS40001270F-page 55

PIC10F220/222 TABLE 10-1: PULL-UP RESISTOR RANGES VDD (Volts) Temperature (C) Min Typ Max Units GP0/GP1 2.0 -40 73K 105K 186K  25 73K 113K 187K  85 82K 123K 190K  125 86K 132k 190K  5.5 -40 15K 21K 33K  25 15K 22K 34K  85 19K 26k 35K  125 23K 29K 35K  GP3 2.0 -40 63K 81K 96K  25 77K 93K 116K  85 82K 96k 116K  125 86K 100K 119K  5.5 -40 16K 20k 22K  25 16K 21K 23K  85 24K 25k 28K  125 26K 27K 29K  DS40001270F-page 56  2005-2013 Microchip Technology Inc.

PIC10F220/222 10.4 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc Oscillator cy Cycle time os OSC1 drt Device Reset Timer t0 T0CKI io I/O port wdt Watchdog Timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (high-impedance) V Valid L Low Z High-impedance FIGURE 10-2: LOAD CONDITIONS Legend: pin CL CL = 50 pF for all pins VSS TABLE 10-2: CALIBRATED INTERNAL RC FREQUENCIES – PIC10F220/222 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial), AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section10.1 “DC Characteristics: PIC10F220/222 (Industrial)”. Param Freq. Sym Characteristic Min Typ† Max Units Conditions No. Tolerance F10 FOSC Internal Calibrated 1% 3.96 4.00 4.04 MHz VDD=3.5V @ 25C INTOSC 2% 3.92 4.00 4.08 MHz 2.5V VDD  5.5V Frequency(1, 2, 3) 0C  TA  +85C (industrial) 5% 3.80 4.00 4.20 MHz 2.0V VDD  5.5V -40C  TA  +85C (industrial) -40C  TA  +125C (extended) † Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 2: Under stable VDD conditions. 3: Frequency values in this table are doubled when the 8MHz INTOSC option is selected.  2005-2013 Microchip Technology Inc. DS40001270F-page 57

PIC10F220/222 FIGURE 10-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING VDD MCLR 30 Internal POR 32 32 32 DRT Timeout(2) Internal Reset Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: I/O pins must be taken out of High-impedance mode by enabling the output drivers in software. 2: Runs on POR Reset only. TABLE 10-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC10F220/222 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section10.1 “DC Characteristics: PIC10F220/222 (Industrial)” Param Sym Characteristic Min Typ(1) Max Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2* — — s VDD = 5V, -40°C to +85°C 5* — — s VDD = 5.0V 31 TWDT Watchdog Timer Time-out Period 10 18 29 ms VDD = 5.0V (Industrial) (no prescaler) 10 18 31 ms VDD = 5.0V (Extended) 32 TDRT* Device Reset Timer Period 0.600 1.125 1.85 ms VDD = 5.0V (Industrial) (standard) 0.600 1.125 1.95 ms VDD = 5.0V (Extended) 34 TIOZ I/O High-impedance from MCLR — — 2* s low * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001270F-page 58  2005-2013 Microchip Technology Inc.

PIC10F220/222 FIGURE 10-4: TIMER0 CLOCK TIMINGS T0CKI 40 41 42 TABLE 10-4: TIMER0 CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40C  TA  +85C (industrial) -40C  TA  +125C (extended) Param Sym Characteristic Min Typ(1) Max Units Conditions No. 40 Tt0H T0CKI High Pulse No Prescaler 0.5 TCY + 20* — — ns Width With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse No Prescaler 0.5 TCY + 20* — — ns Width With Prescaler 10* — — ns 42 Tt0P T0CKI Period 20 or TCY + 40* N — — ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2005-2013 Microchip Technology Inc. DS40001270F-page 59

PIC10F220/222 TABLE 10-5: A/D CONVERTER CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8 bits bit A03 EIL Integral Error — — ±1.5 LSb A04 EDL Differential Error — — -1 < EDL + 1.5 LSb A05 EFS Full-scale Range 2.0* — 5.5* V A06 EOFF Offset Error — — ±1.5 LSb A07 EGN Gain Error — — ±1.5 LSb A10 — Monotonicity — guaranteed(1) — — VSS  VAIN  VDD A25 VAIN Analog Input Voltage VSS — VDD V A30 ZAIN Recommended — — 10 k Impedence of Analog Voltage Source A31* IAD A/D Conversion Current(2) — 120 150 A 2.0V — 200 250 A 5.0V * These parameters are characterized but not tested. † Data in the “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only are not tested. Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: This is the additional current consumed by the A/D module when it is enabled; this current adds to base IDD. TABLE 10-6: A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C  TA  +125°C Param Sym Characteristic Min Typ† Max Units Conditions No. AD131 TCNV Conversion Time — 13 — TCY Set GO/DONE bit to new data in A/D (not including Result register Acquisition Time) AD132* TACQ Acquisition Time(1) — 3.5 — s VDD = 5V 5 s VDD = 2.5V * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The Section7.9 “A/D Acquisition Requirements” for information on how to compute minimum acquisition times based on operating conditions. DS40001270F-page 60  2005-2013 Microchip Technology Inc.

PIC10F220/222 11.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean+3) or (mean- 3) respectively, where s is a standard deviation, over each temperature range. FIGURE 11-1: IDD vs. VDD OVER FOSC (4 MHZ) XT Mode 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst Case Temp) + 3 Maximum (-40°C to 125°C) 1,000 4 MHz 800 A) Typical  (D ID 600 4 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2013 Microchip Technology Inc. DS40001270F-page 61

PIC10F220/222 FIGURE 11-2: IDD vs. VDD OVER FOSC (8 MHZ) Typical (Sleep Mode all Peripherals Disabled) 1,800 Typical: Statistical Mean @25°C Maximum 1,600 Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) 1,400 8 MHz 1,200 A) 1,000 (D Typical D 800 I 8 MHz 600 400 200 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-3: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 1.10 Typical: Statistical Mean @25°C 1.00 0.90 0.80 A) 0.70  (D P 0.60 I 0.50 0.40 0.30 0.20 0.10 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001270F-page 62  2005-2013 Microchip Technology Inc.

PIC10F220/222 FIGURE 11-4: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 Typical: Statistical Mean @25°C 16.0 Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) 14.0 Max. 125°C 12.0 A) 10.0  (D P 8.0 I 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-5: TYPICAL WDT IPD vs. VDD 9 8 Typical: Statistical Mean @25°C 7 6 A) 5  (D P 4 I 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2013 Microchip Technology Inc. DS40001270F-page 63

PIC10F220/222 FIGURE 11-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) 20.0 Max. 125°C 15.0 A)  (D P I 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-7: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C 45 Max. 125°C Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) 40 Max. 85°C 35 30 ms) Typical. 25°C e ( 25 m Ti 20 Min. -40°C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001270F-page 64  2005-2013 Microchip Technology Inc.

PIC10F220/222 FIGURE 11-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) Max. 125°C 0.6 0.5 Max. 85°C V) (L 0.4 O V 0.3 Typical 25°C 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 11-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 MaximTuympi:c aMl:e Satna (tiWstoicraslt MCeaasne T@e2m5p×)C + 3 Maximum: Mea s( -+4 03×C to 125×C) (-40°C to 125°C) Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA)  2005-2013 Microchip Technology Inc. DS40001270F-page 65

PIC10F220/222 FIGURE 11-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 11-11: VOH vs. IOH OVER TE(MPERAT, URE (VDD = 5).0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) DS40001270F-page 66  2005-2013 Microchip Technology Inc.

PIC10F220/222 FIGURE 11-12: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 11-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst Case Temp) + 3 (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2005-2013 Microchip Technology Inc. DS40001270F-page 67

PIC10F220/222 NOTES: DS40001270F-page 68  2005-2013 Microchip Technology Inc.

PIC10F220/222 12.0 DEVELOPMENT SUPPORT 12.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2005-2013 Microchip Technology Inc. DS40001270F-page 69

PIC10F220/222 12.2 MPLAB XC Compilers 12.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other relo- related modules together catable object files and archives to create an execut- • Flexible creation of libraries with easy module able file. MPLAB XC Compiler uses the assembler to listing, replacement, deletion and extraction produce its object file. Notable features of the assem- bler include: 12.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 12.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001270F-page 70  2005-2013 Microchip Technology Inc.

PIC10F220/222 12.6 MPLAB X SIM Software Simulator 12.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 12.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 12.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar- programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati- with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 12.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2005-2013 Microchip Technology Inc. DS40001270F-page 71

PIC10F220/222 12.11 Demonstration/Development 12.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001270F-page 72  2005-2013 Microchip Technology Inc.

PIC10F220/222 13.0 PACKAGING INFORMATION 13.1 Package Marking Information 6-Lead SOT-23* Example XXNN 20JR 8-Lead PDIP Example XXXXXXXX PIC10F220 XXXXXNNN I/P e3 07Q YYWW 0520 8-Lead DFN* Example XXX BJ0 YWW 625 NN 3Q Legend: XX...X Product-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2005-2013 Microchip Technology Inc. DS40001270F-page 73

PIC10F220/222 TABLE 13-1: 8-LEAD 2x3 DFN (MC) TOP TABLE 13-2: 6-LEAD SOT-23 (OT) MARKING PACKAGE TOP MARKING Part Number Marking Part Number Marking PIC10F220-I/MC BJ0 PIC10F220-I/OT 20NN PIC10F220-E/MC BK0 PIC10F220-E/OT A0NN PIC10F222-I/MC BL0 PIC10F222-I/OT 22NN PIC10F222-E/MC BM0 PIC10F222-E/OT A2NN Note: NN represents the alphanumeric traceability code. DS40001270F-page 74  2005-2013 Microchip Technology Inc.

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DS40001270F-page 75

PIC10F220/222 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001270F-page 76  2005-2013 Microchip Technology Inc.

PIC10F220/222 (cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:18)(cid:6)(cid:10)(cid:8)!(cid:19)(cid:3)(cid:4)(cid:13)(cid:19)(cid:5)(cid:8)(cid:23)(cid:9)(cid:24)(cid:8)"(cid:8)(cid:27)##(cid:8)(cid:16)(cid:13)(cid:10)(cid:8)$(cid:22)(cid:7)%(cid:8)(cid:25)(cid:9) !(cid:9)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L A1 c e eB b1 b 3(cid:15)(cid:7)# (cid:19)5*:"(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 < 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:20)(cid:30)(cid:4)(cid:4)(cid:2))(cid:22)* (cid:13)(cid:10)(cid:12)(cid:2)#(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)#(cid:7)(cid:15)(cid:17)(cid:2)1(cid:16)(cid:28)(cid:15)(cid:14) (cid:25) ; ; (cid:20)(cid:3)(cid:30)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:20)(cid:30)(cid:30)( (cid:20)(cid:30)(cid:29)(cid:4) (cid:20)(cid:30)(cid:24)( )(cid:28) (cid:14)(cid:2)#(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)#(cid:7)(cid:15)(cid:17)(cid:2)1(cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:30) (cid:20)(cid:4)(cid:30)( ; ; (cid:22)(cid:11)(cid:10)$(cid:16)!(cid:14)(cid:9)(cid:2)#(cid:10)(cid:2)(cid:22)(cid:11)(cid:10)$(cid:16)!(cid:14)(cid:9)(cid:2)=(cid:7)!#(cid:11) " (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)(cid:29)(cid:30)(cid:4) (cid:20)(cid:29)(cid:3)( (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3)((cid:4) (cid:20)(cid:3)<(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:20)(cid:29)(cid:23)< (cid:20)(cid:29)9( (cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2)#(cid:10)(cid:2)(cid:22)(cid:14)(cid:28)#(cid:7)(cid:15)(cid:17)(cid:2)1(cid:16)(cid:28)(cid:15)(cid:14) 4 (cid:20)(cid:30)(cid:30)( (cid:20)(cid:30)(cid:29)(cid:4) (cid:20)(cid:30)((cid:4) 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:20)(cid:4)(cid:4)< (cid:20)(cid:4)(cid:30)(cid:4) (cid:20)(cid:4)(cid:30)( 3(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8(cid:30) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)9(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 4(cid:10)-(cid:14)(cid:9)(cid:2)4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:20)(cid:4)(cid:30)(cid:23) (cid:20)(cid:4)(cid:30)< (cid:20)(cid:4)(cid:3)(cid:3) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)-(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)? (cid:14)) ; ; (cid:20)(cid:23)(cid:29)(cid:4) (cid:29)(cid:22)(cid:12)(cid:5)(cid:11)(cid:30) (cid:30)(cid:20) 1(cid:7)(cid:15)(cid:2)(cid:30)(cid:2),(cid:7) $(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)!(cid:14)&(cid:2)%(cid:14)(cid:28)#$(cid:9)(cid:14)(cid:2)(cid:31)(cid:28)(cid:18)(cid:2),(cid:28)(cid:9)(cid:18)0(cid:2)8$#(cid:2)(cid:31)$ #(cid:2)8(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)-(cid:7)#(cid:11)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)#(cid:8)(cid:11)(cid:14)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) ?(cid:2)(cid:22)(cid:7)(cid:17)(cid:15)(cid:7)%(cid:7)(cid:8)(cid:28)(cid:15)#(cid:2)*(cid:11)(cid:28)(cid:9)(cid:28)(cid:8)#(cid:14)(cid:9)(cid:7) #(cid:7)(cid:8)(cid:20) (cid:29)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:20)(cid:4)(cid:30)(cid:4)@(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+(cid:2))(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)(cid:30)<)  2005-2013 Microchip Technology Inc. DS40001270F-page 77

PIC10F220/222 (cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:18)(cid:6)(cid:10)(cid:8)&(cid:10)(cid:6)(cid:12)’(cid:8)(cid:29)(cid:22)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)((cid:6))(cid:5)(cid:8)(cid:23)*+(cid:24)(cid:8)"(cid:8)(cid:26),(cid:27),#-.(cid:8)(cid:16)(cid:16)(cid:8)$(cid:22)(cid:7)%(cid:8)(cid:25) &(cid:29)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 < 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)((cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)( *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:29) (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26)". 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:3)(cid:20)(cid:4)(cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:29)(cid:20)(cid:4)(cid:4)(cid:2))(cid:22)* "&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)!(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21)(cid:3) (cid:30)(cid:20)(cid:29)(cid:4) ; (cid:30)(cid:20)(( "&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)!(cid:2)=(cid:7)!#(cid:11) "(cid:3) (cid:30)(cid:20)((cid:4) ; (cid:30)(cid:20)(cid:5)( *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:3)( (cid:4)(cid:20)(cid:29)(cid:4) *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)((cid:4) *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:27)#(cid:10)(cid:27)"&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)! A (cid:4)(cid:20)(cid:3)(cid:4) ; ; (cid:29)(cid:22)(cid:12)(cid:5)(cid:11)(cid:30) (cid:30)(cid:20) 1(cid:7)(cid:15)(cid:2)(cid:30)(cid:2),(cid:7) $(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)!(cid:14)&(cid:2)%(cid:14)(cid:28)#$(cid:9)(cid:14)(cid:2)(cid:31)(cid:28)(cid:18)(cid:2),(cid:28)(cid:9)(cid:18)0(cid:2)8$#(cid:2)(cid:31)$ #(cid:2)8(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)-(cid:7)#(cid:11)(cid:7)(cid:15)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:11)(cid:28)#(cid:8)(cid:11)(cid:14)!(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) 1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:31)(cid:28)(cid:18)(cid:2)(cid:11)(cid:28),(cid:14)(cid:2)(cid:10)(cid:15)(cid:14)(cid:2)(cid:10)(cid:9)(cid:2)(cid:31)(cid:10)(cid:9)(cid:14)(cid:2)(cid:14)&(cid:12)(cid:10) (cid:14)!(cid:2)#(cid:7)(cid:14)(cid:2)8(cid:28)(cid:9) (cid:2)(cid:28)#(cid:2)(cid:14)(cid:15)! (cid:20) (cid:29)(cid:20) 1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:7) (cid:2) (cid:28)-(cid:2) (cid:7)(cid:15)(cid:17)$(cid:16)(cid:28)#(cid:14)!(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)".+ (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)0(cid:2)$ $(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)0(cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)(cid:31)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)$(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)(cid:29)* DS40001270F-page 78  2005-2013 Microchip Technology Inc.

PIC10F220/222 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2013 Microchip Technology Inc. DS40001270F-page 79

PIC10F220/222 APPENDIX A: REVISION HISTORY Revision A Original release of document. Revision B (03/2006) Table 3-1, GP1; Section 4.7, Program Counter; Table 5- 2; Figure 8-5; Section 9.1, ANDWF, SLEEP, SUBWF, SWAPF, XORLW. Revision C (08/2006) Added 8-Lead DFN pinout diagram, updated Table 1-1 with DFN package, updated Table 10-3 in Section 10.0, added 8-Lead DFN package marking information to section 13.0, updated the Product Identification System section to include DFN package identification. Added note to package drawings. Revision D (02/2007) Replaced Dev. Tool Section; Replaced Package Drawings. Revision E (06/2007) Updated and added Characterization Data; Revised Operating Current; Revised Section 8.4 and Note; Revised Section 10.0, Total Power Dissipation, 10.1, 10.2, 10.3 DC Characteristics; Revised Tables 10-2, 10-3, 10-5, 10-6; Section 11.0; Revised Product ID System. Revision F (10/2013) Revised Packaging Legend. DS40001270F-page 80  2005-2013 Microchip Technology Inc.

PIC10F220/222 INDEX A M A/D Memory Organization.........................................................13 Specifications..............................................................60 Data Memory..............................................................14 ADC Program Memory (PIC10F220)..................................13 Internal Sampling Switch (RSS) IMPEDANCE................32 Program Memory (PIC10F222)..................................13 Source Impedance......................................................32 Microchip Internet Web Site................................................75 ALU.......................................................................................9 MPLAB ASM30 Assembler, Linker, Librarian.....................62 Assembler MPLAB ICD 2 In-Circuit Debugger.....................................63 MPASM Assembler.....................................................62 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator......................................................63 B MPLAB Integrated Development Environment Software....61 Block Diagram MPLAB PM3 Device Programmer......................................63 On-Chip Reset Circuit.................................................36 MPLAB REAL ICE In-Circuit Emulator System..................63 Timer0.........................................................................25 MPLINK Object Linker/MPLIB Object Librarian..................62 TMR0/WDT Prescaler.................................................28 O Watchdog Timer..........................................................39 Block Diagrams OPTION Register................................................................17 Analog Input Model.....................................................32 OSCCAL Register...............................................................18 Brown-Out Protection Circuit..............................................40 Oscillator Configurations.....................................................34 Oscillator Types C HS...............................................................................34 C Compilers LP...............................................................................34 MPLAB C18................................................................62 P MPLAB C30................................................................62 Carry.....................................................................................9 PIC10F220/222 Device Varieties..........................................7 Clocking Scheme................................................................11 PICSTART Plus Development Programmer.......................64 Code Protection............................................................33, 41 POR Configuration Bits................................................................33 Device Reset Timer (DRT)...................................33, 38 Customer Change Notification Service...............................75 PD...............................................................................39 Customer Notification Service.............................................75 Power-on Reset (POR)...............................................33 Customer Support...............................................................75 TO...............................................................................39 Power-down Mode..............................................................40 D Prescaler............................................................................27 DC and AC Characteristics.................................................65 Program Counter................................................................19 Development Support.........................................................61 Q Digit Carry.............................................................................9 Q cycles..............................................................................11 E R Errata....................................................................................3 Reader Response...............................................................76 F Read-Modify-Write..............................................................23 Family of Devices Register File Map PIC10F22X...................................................................5 PIC10F220.................................................................14 FSR.....................................................................................20 PIC10F222.................................................................14 Registers G Special Function.........................................................14 GPIO...................................................................................21 Reset..................................................................................33 I Reset on Brown-Out...........................................................40 I/O Interfacing.....................................................................21 S I/O Ports..............................................................................21 Sleep............................................................................33, 40 I/O Programming Considerations........................................23 Software Simulator (MPLAB SIM)......................................62 ID Locations..................................................................33, 41 Special Features of the CPU..............................................33 INDF....................................................................................20 Special Function Registers.................................................14 Indirect Data Addressing.....................................................20 Stack...................................................................................19 Instruction Cycle.................................................................11 STATUS Register.....................................................9, 15, 29 Instruction Flow/Pipelining..................................................11 T Instruction Set Summary.....................................................44 Internal Sampling Switch (RSS) IMPEDANCE........................32 Timer0 Internet Address..................................................................75 Timer0........................................................................25 Timer0 (TMR0) Module..............................................25 L TMR0 with External Clock..........................................26 Loading of PC.....................................................................19 Timing Parameter Symbology and Load Conditions..........57 TRIS Registers...................................................................21  2005-2013 Microchip Technology Inc. DS40001270F-page 81

PIC10F220/222 W Wake-up from Sleep...........................................................41 Watchdog Timer (WDT)................................................33, 38 Period..........................................................................38 Programming Considerations.....................................38 WWW Address....................................................................75 WWW, On-Line Support........................................................3 Z Zero bit..................................................................................9 DS40001270F-page 82  2005-2013 Microchip Technology Inc.

PIC10F220/222 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2005-2013 Microchip Technology Inc. DS40001270F-page 83

PIC10F220/222 NOTES: DS40001270F-page 84  2005-2013 Microchip Technology Inc.

PIC10F220/222 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Examples: Device Temperature Package Pattern a) PIC10F220-I/P = Industrial temp., PDIP Range package (Pb-free) b) PIC10F222T-E/OT = Extended temp., SOT-23 package (Pb-free), Tape and Reel c) PIC10F222-E/MC = Extended temp., DFN Device: PIC10F220 package (Pb-free) PIC10F222 PIC10F220T (Tape & Reel) PIC10F222T (Tape & Reel) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Package: P = 300 mil PDIP (Pb-free) OT = SOT-23, 6-LD (Pb-free) MC = DFN, 8-LD 2x3 (Pb-free) Pattern: Special Requirements  2005-2013 Microchip Technology Inc. DS40001270F-page 85

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC10F220T-I/OT PIC10F222-E/OT PIC10F220-E/OT PIC10F220-I/OT PIC10F222-I/OT PIC10F220-E/P PIC10F220-I/MC PIC10F220-I/P PIC10F220T-E/OT PIC10F220T-I/MC PIC10F222-E/P PIC10F222-I/MC PIC10F222-I/P PIC10F222T-E/OT PIC10F222T-I/MC PIC10F222T-I/OT PIC10F220-E/MC PIC10F222-E/MC