PIC10F200/202/204/206 6-Pin, 8-Bit Flash Microcontrollers Devices Included In This Data Sheet: Low-Power Features/CMOS Technology: • PIC10F200 • PIC10F204 • Operating Current: • PIC10F202 • PIC10F206 - < 175A @ 2V, 4MHz, typical • Standby Current: High-Performance RISC CPU: - 100nA @ 2V, typical • Low-Power, High-Speed Flash Technology: • Only 33 Single-Word Instructions to Learn - 100,000 Flash endurance • All Single-Cycle Instructions except for Program - > 40 year retention Branches, which are Two-Cycle • Fully Static Design • 12-Bit Wide Instructions • Wide Operating Voltage Range: 2.0V to 5.5V • 2-Level Deep Hardware Stack • Wide Temperature Range: • Direct, Indirect and Relative Addressing modes for Data and Instructions - Industrial: -40C to +85C - Extended: -40C to +125C • 8-Bit Wide Data Path • Eight Special Function Hardware Registers Peripheral Features (PIC10F200/202): • Operating Speed: • Four I/O Pins: - 4MHz internal clock - Three I/O pins with individual direction control - 1s instruction cycle - One input-only pin Special Microcontroller Features: - High current sink/source for direct LED drive - Wake-on-change • 4MHz Precision Internal Oscillator: - Weak pull-ups - Factory calibrated to ±1% • 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit • In-Circuit Serial Programming™ (ICSP™) Programmable Prescaler • In-Circuit Debugging (ICD) Support Peripheral Features (PIC10F204/206): • Power-on Reset (POR) • Device Reset Timer (DRT) • Four I/O Pins: • Watchdog Timer (WDT) with Dedicated On-Chip - Three I/O pins with individual direction control RC Oscillator for Reliable Operation - One input-only pin • Programmable Code Protection - High current sink/source for direct LED drive - Wake-on-change • Multiplexed MCLR Input Pin - Weak pull-ups • Internal Weak Pull-ups on I/O Pins • 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit • Power-Saving Sleep mode Programmable Prescaler • Wake-up from Sleep on Pin Change • One Comparator: - Internal absolute voltage reference - Both comparator inputs visible externally - Comparator output visible externally TABLE 1: PIC10F20X MEMORY AND FEATURES Program Memory Data Memory Timers Device I/O Comparator 8-bit Flash (words) SRAM (bytes) PIC10F200 256 16 4 1 0 PIC10F202 512 24 4 1 0 PIC10F204 256 16 4 1 1 PIC10F206 512 24 4 1 1  2004-2014 Microchip Technology Inc. DS40001239F-page 1

PIC10F200/202/204/206 Pin Diagrams FIGURE 1: 6-PIN SOT-23 GP0/ICSPDAT 1 2 6 GP3/MCLR/VPP 0 2 VSS 2 00/ 5 VDD 2 F GP1/ICSPCLK 3 10 4 GP2/T0CKI/FOSC4 C PI GP0/ICSPDAT/CIN+ 1 6 6 GP3/MCLR/VPP 0 2 VSS 2 04/ 5 VDD 2 F GP1/ICSPCLK/CIN- 3 10 4 GP2/T0CKI/COUT/FOSC4 C PI FIGURE 2: 8-PIN PDIP N/C 1 2 8 GP3/MCLR/VPP 0 VDD 2 0/2 7 VSS 0 GP2/T0CKI/FOSC4 3 F2 6 N/C 0 GP1/ICSPCLK 4 C1 5 GP0/ICSPDAT PI N/C 1 6 8 GP3/MCLR/VPP 0 VDD 2 4/2 7 VSS 0 GP2/T0CKI/COUT/FOSC4 3 F2 6 N/C 0 GP1/ICSPCLK/CIN- 4 C1 5 GP0/ICSPDAT/CIN+ PI FIGURE 3: 8-PIN DFN N/C 1 02 8 GP3/MCLR/VPP 2 VDD 2 00/ 7 VSS 2 GP2/T0CKI/FOSC4 3 F 6 N/C 0 1 GP1/ICSPCLK 4 C 5 GP0/ICSPDAT PI N/C 1 06 8 GP3/MCLR/VPP 2 VDD 2 04/ 7 VSS 2 GP2/T0CKI/COUT/FOSC4 3 0F 6 N/C 1 GP1/ICSPCLK/CIN- 4 PIC 5 GP0/ICSPDAT/CIN+ DS40001239F-page 2  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 Table of Contents 1.0 General Description......................................................................................................................................................................4 2.0 PIC10F200/202/204/206 Device Varieties ..................................................................................................................................5 3.0 Architectural Overview.................................................................................................................................................................6 4.0 Memory Organization.................................................................................................................................................................11 5.0 I/O Port.......................................................................................................................................................................................20 6.0 Timer0 Module and TMR0 Register (PIC10F200/202)...............................................................................................................23 7.0 Timer0 Module and TMR0 Register (PIC10F204/206)...............................................................................................................27 8.0 Comparator Module....................................................................................................................................................................31 9.0 Special Features of the CPU......................................................................................................................................................35 10.0 Instruction Set Summary............................................................................................................................................................45 11.0 Development Support.................................................................................................................................................................53 12.0 Electrical Characteristics............................................................................................................................................................57 13.0 DC and AC Characteristics Graphs and Tables.........................................................................................................................67 14.0 Packaging Information................................................................................................................................................................75 The Microchip Web Site.......................................................................................................................................................................85 Customer Change Notification Service................................................................................................................................................85 Customer Support................................................................................................................................................................................85 Product Identification System..............................................................................................................................................................86 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2004-2014 Microchip Technology Inc. DS40001239F-page 3

PIC10F200/202/204/206 1.0 GENERAL DESCRIPTION 1.1 Applications The PIC10F200/202/204/206 devices from Microchip The PIC10F200/202/204/206 devices fit in applications Technology are low-cost, high-performance, 8-bit, ranging from personal care appliances and security fully-static, Flash-based CMOS microcontrollers. They systems to low-power remote transmitters/receivers. employ a RISC architecture with only 33 single-word/ The Flash technology makes customizing application single-cycle instructions. All instructions are single programs (transmitter codes, appliance settings, cycle (1s) except for program branches, which take receiver frequencies, etc.) extremely fast and two cycles. The PIC10F200/202/204/206 devices convenient. The small footprint packages, for through deliver performance in an order of magnitude higher hole or surface mounting, make these microcontrollers than their competitors in the same price category. The well suited for applications with space limitations. Low 12-bit wide instructions are highly symmetrical, cost, low power, high performance, ease-of-use and I/O resulting in a typical 2:1 code compression over other flexibility make the PIC10F200/202/204/206 devices 8-bit microcontrollers in its class. The easy-to-use and very versatile even in areas where no microcontroller easy to remember instruction set reduces development use has been considered before (e.g., timer functions, time significantly. logic and PLDs in larger systems and coprocessor applications). The PIC10F200/202/204/206 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. INTRC Internal Oscillator mode is provided, thereby preserving the limited number of I/O available. Power-Saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC10F200/202/204/206 devices are available in cost-effective Flash, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility. The PIC10F200/202/204/206 products are supported by a full-featured macro assembler, a software simulator, an in-circuit debugger, a ‘C’ compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM® PC and compatible machines. TABLE 1-1: PIC10F200/202/204/206 DEVICES PIC10F200 PIC10F202 PIC10F204 PIC10F206 Clock Maximum Frequency of Operation (MHz) 4 4 4 4 Memory Flash Program Memory 256 512 256 512 Data Memory (bytes) 16 24 16 24 Peripherals Timer Module(s) TMR0 TMR0 TMR0 TMR0 Wake-up from Sleep on Pin Change Yes Yes Yes Yes Comparators 0 0 1 1 Features I/O Pins 3 3 3 3 Input-Only Pins 1 1 1 1 Internal Pull-ups Yes Yes Yes Yes In-Circuit Serial Programming™ Yes Yes Yes Yes Number of Instructions 33 33 33 33 Packages 6-pin SOT-23 6-pin SOT-23 6-pin SOT-23 6-pin SOT-23 8-pin PDIP, DFN 8-pin PDIP, DFN 8-pin PDIP, DFN 8-pin PDIP, DFN The PIC10F200/202/204/206 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC10F200/202/204/206 devices use serial programming with data pin GP0 and clock pin GP1. DS40001239F-page 4  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 2.0 PIC10F200/202/204/206 DEVICE 2.2 Serialized Quick Turn VARIETIES ProgrammingSM (SQTPSM) Devices A variety of packaging options are available. Microchip offers a unique programming service, where Depending on application and production a few user-defined locations in each device are requirements, the proper device option can be selected programmed with different serial numbers. The serial using the information in this section. When placing numbers may be random, pseudo-random or orders, please use the PIC10F200/202/204/206 sequential. Product Identification System at the back of this data Serial programming allows each device to have a sheet to specify the correct part number. unique number, which can serve as an entry code, password or ID number. 2.1 Quick Turn Programming (QTP) Devices Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.  2004-2014 Microchip Technology Inc. DS40001239F-page 5

PIC10F200/202/204/206 3.0 ARCHITECTURAL OVERVIEW The PIC10F200/202/204/206 devices contain an 8-bit ALU and working register. The ALU is a general The high performance of the PIC10F200/202/204/206 purpose arithmetic unit. It performs arithmetic and devices can be attributed to a number of architectural Boolean functions between data in the working register features commonly found in RISC microprocessors. To and any register file. begin with, the PIC10F200/202/204/206 devices use a The ALU is 8 bits wide and capable of addition, Harvard architecture in which program and data are subtraction, shift and logical operations. Unless accessed on separate buses. This improves otherwise mentioned, arithmetic operations are two’s bandwidth over traditional von Neumann architectures complement in nature. In two-operand instructions, one where program and data are fetched on the same bus. operand is typically the W (working) register. The other Separating program and data memory further allows operand is either a file register or an immediate instructions to be sized differently than the 8-bit wide constant. In single operand instructions, the operand is data word. Instruction opcodes are 12 bits wide, either the W register or a file register. making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a The W register is an 8-bit working register used for ALU 12-bit instruction in a single cycle. A two-stage pipeline operations. It is not an addressable register. overlaps fetch and execution of instructions. Depending on the instruction executed, the ALU may Consequently, all instructions (33) execute in a single affect the values of the Carry (C), Digit Carry (DC) and cycle (1s @ 4MHz) except for program branches. Zero (Z) bits in the STATUS register. The C and DC bits The table below lists program memory (Flash) and data operate as a borrow and digit borrow out bit, memory (RAM) for the PIC10F200/202/204/206 respectively, in subtraction. See the SUBWF and ADDWF devices. instructions for examples. A simplified block diagram is shown in Figure3-1 and TABLE 3-1: PIC10F2XX MEMORY Figure3-2, with the corresponding device pins described in Table3-2. Memory Device Program Data PIC10F200 256 x 12 16 x 8 PIC10F202 512 x 12 24 x 8 PIC10F204 256 x 12 16 x 8 PIC10F206 512 x 12 24 x 8 The PIC10F200/202/204/206 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC10F200/202/ 204/206 devices have a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. This symmetrical nature and lack of “special optimal situations” make programming with the PIC10F200/202/204/206 devices simple, yet efficient. In addition, the learning curve is reduced significantly. DS40001239F-page 6  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 FIGURE 3-1: PIC10F200/202 BLOCK DIAGRAM 9-10 Data Bus 8 GPIO Program Counter Flash 512 x12 or GP0/ICSPDAT GP1/ICSPCLK 256 x12 RAM GP2/T0CKI/FOSC4 PMreomgroarmy Stack 1 24b yotre 1s6 GP3/MCLR/VPP Stack 2 File Registers Program 12 Bus RAM Addr 9 Addr MUX Instruction Reg Direct Addr 5 Indirect 5-7 Addr FSR Reg STATUS Reg 8 3 MUX Device Reset Timer Instruction Power-on Decode & Reset ALU Control Watchdog 8 Timer Timing Generation Internal RC W Reg Clock Timer0 MCLR VDD, VSS  2004-2014 Microchip Technology Inc. DS40001239F-page 7

PIC10F200/202/204/206 FIGURE 3-2: PIC10F204/206 BLOCK DIAGRAM 9-10 Data Bus 8 GPIO Program Counter Flash 512 x12 or GP0/ICSPDAT/CIN+ GP1/ICSPCLK/CIN- 256 x12 RAM GP2/T0CKI/COUT/FOSC4 PMreomgroarmy Stack 1 24b yotre 1s6 GP3/MCLR/VPP Stack 2 File Registers Program 12 Bus RAM Addr 9 Addr MUX Instruction Reg Direct Addr 5 Indirect 5-7 Addr FSR Reg STATUS Reg 8 3 MUX Device Reset Timer Instruction Power-on Decode & Reset ALU Control Watchdog 8 Timer Timing Generation Internal RC W Reg Clock CIN+ Timer0 Comparator CIN- MCLR VDD, VSS COUT DS40001239F-page 8  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 TABLE 3-2: PIC10F200/202/204/206 PINOUT DESCRIPTION Input Output Name Function Description Type Type GP0/ICSPDAT/CIN+ GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPDAT ST CMOS In-Circuit Serial Programming™ data pin. CIN+ AN — Comparator input (PIC10F204/206 only). GP1/ICSPCLK/CIN- GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ICSPCLK ST CMOS In-Circuit Serial Programming clock pin. CIN- AN — Comparator input (PIC10F204/206 only). GP2/T0CKI/COUT/ GP2 TTL CMOS Bidirectional I/O pin. FOSC4 T0CKI ST — Clock input to TMR0. COUT — CMOS Comparator output (PIC10F204/206 only). FOSC4 — CMOS Oscillator/4 output. GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is an active-low Reset to the device. Voltage on GP3/MCLR/VPP must not exceed VDD during normal device operation or the device will enter Programming mode. Weak pull-up always on if configured as MCLR. VPP HV — Programming voltage input. VDD VDD P — Positive supply for logic and I/O pins. VSS VSS P — Ground reference for logic and I/O pins. Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input, ST = Schmitt Trigger input, AN = Analog input  2004-2014 Microchip Technology Inc. DS40001239F-page 9

PIC10F200/202/204/206 3.1 Clocking Scheme/Instruction 3.2 Instruction Flow/Pipelining Cycle An instruction cycle consists of four Q cycles (Q1, Q2, The clock is internally divided by four to generate four Q3 and Q4). The instruction fetch and execute are non-overlapping quadrature clocks, namely Q1, Q2, pipelined such that fetch takes one instruction cycle, Q3 and Q4. Internally, the PC is incremented every Q1 while decode and execute take another instruction and the instruction is fetched from program memory cycle. However, due to the pipelining, each instruction and latched into the instruction register in Q4. It is effectively executes in one cycle. If an instruction decoded and executed during the following Q1 through causes the PC to change (e.g., GOTO), then two cycles Q4. The clocks and instruction execution flow is shown are required to complete the instruction (Example3-1). in Figure3-3 and Example3-1. A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC + 1 PC + 2 Fetch INST (PC) Execute INST (PC – 1) Fetch INST (PC + 1) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 03H Fetch 1 Execute 1 2. MOVWF GPIO Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF GPIO, BIT1 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. DS40001239F-page 10  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 4.0 MEMORY ORGANIZATION FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE The PIC10F200/202/204/206 memories are organized PIC10F200/204 into program memory and data memory. Data memory banks are accessed using the File Select Register PC<7:0> (FSR). CALL, RETLW 9 4.1 Program Memory Organization for Stack Level 1 Stack Level 2 the PIC10F200/204 The PIC10F200/204 devices have a 9-bit Program Counter (PC) capable of addressing a 512x12 Reset Vector(1) 0000h program memory space. Only the first 256x12 (0000h-00FFh) for the On-chip Program PIC10F200/204 are physically implemented (see Memory Figure4-1). Accessing a location above these y boundaries will cause a wraparound within the first more 256x12 space (PIC10F200/204). The effective Meac p Reset vector is at 0000h (see Figure4-1). Location er S s 00FFh (PIC10F200/204) contains the internal clock U oscillator calibration value. This value should never be overwritten. 256 Word 00FFh 0100h 01FFh Note 1: Address 0000h becomes the effective Reset vector. Location 00FFh contains the MOVLW XX internal oscillator calibration value.  2004-2014 Microchip Technology Inc. DS40001239F-page 11

PIC10F200/202/204/206 4.2 Program Memory Organization for 4.3 Data Memory Organization the PIC10F202/206 Data memory is composed of registers or bytes of The PIC10F202/206 devices have a 10-bit Program RAM. Therefore, data memory for a device is specified Counter (PC) capable of addressing a 1024x12 by its register file. The register file is divided into two program memory space. functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). Only the first 512x12 (0000h-01FFh) for the PIC10F202/206 are physically implemented (see The Special Function Registers include the TMR0 Figure4-2). Accessing a location above these register, the Program Counter (PCL), the STATUS boundaries will cause a wraparound within the first register, the I/O register (GPIO) and the File Select 512x12 space (PIC10F202/206). The effective Register (FSR). In addition, Special Function Registers Reset vector is at 0000h (see Figure4-2). Location are used to control the I/O port configuration and 01FFh (PIC10F202/206) contains the internal clock prescaler options. oscillator calibration value. This value should never The General Purpose registers are used for data and be overwritten. control information under command of the instructions. For the PIC10F200/204, the register file is composed of FIGURE 4-2: PROGRAM MEMORY MAP seven Special Function registers and 16 General AND STACK FOR THE Purpose registers (see Figure4-3 and Figure4-4). PIC10F202/206 For the PIC10F202/206, the register file is composed of PC<8:0> eight Special Function registers and 24 General CALL, RETLW 10 Purpose registers (see Figure4-4). Stack Level 1 4.3.1 GENERAL PURPOSE REGISTER Stack Level 2 FILE The General Purpose Register file is accessed, either directly or indirectly, through the File Select Register Reset Vector(1) 0000h (FSR). See Section4.9 “Indirect Data Addressing: INDF and FSR Registers”. On-chip Program Memory y or me ec Ma p er S s U 512 Words 01FFh 0200h 02FFh Note 1: Address 0000h becomes the effective Reset vector. Location 01FFh contains the MOVLW XX internal oscillator calibration value. DS40001239F-page 12  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 FIGURE 4-3: PIC10F200/204 REGISTER FIGURE 4-4: PIC10F202/206 REGISTER FILE MAP FILE MAP File Address File Address 00h INDF(1) 00h INDF(1) 01h TMR0 01h TMR0 02h PCL 02h PCL 03h STATUS 03h STATUS 04h FSR 04h FSR 05h OSCCAL 05h OSCCAL 06h GPIO 06h GPIO 07h CMCON0(2) 07h CMCON0(2) 08h 08h Unimplemented(3) 0Fh General Purpose Registers 10h General Purpose Registers 1Fh 1Fh Note 1: Not a physical register. See Section4.9 Note 1: Not a physical register. See Section4.9 “Indirect Data Addressing: INDF and “Indirect Data Addressing: INDF and FSR Registers”. FSR Registers”. 2: PIC10F204 only. Unimplemented on the 2: PIC10F206 only. Unimplemented on the PIC10F200 and reads as 00h. PIC10F202 and reads as 00h. 3: Unimplemented, read as 00h.  2004-2014 Microchip Technology Inc. DS40001239F-page 13

PIC10F200/202/204/206 4.3.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY (PIC10F200/202/204/206) Value on Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On on Page Reset(2) 00h INDF Uses Contents of FSR to Address Data Memory (not a physical register) xxxx xxxx 19 01h TMR0 8-bit Real-Time Clock/Counter xxxx xxxx 23, 27 02h(1) PCL Low-order 8 bits of PC 1111 1111 18 03h STATUS GPWUF CWUF(5) — TO PD Z DC C 00-1 1xxx(3) 15 04h FSR Indirect Data Memory Address Pointer 111x xxxx 19 05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 1111 1110 17 06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx 20 07h(4) CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 28 N/A TRISGPIO — — — — I/O Control Register ---- 1111 31 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 16 Legend: – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = value depends on condition. Note 1: The upper byte of the Program Counter is not directly accessible. See Section4.7 “Program Counter” for an explanation of how to access these bits. 2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin change Reset. 3: See Table9-1 for other Reset specific values. 4: PIC10F204/206 only. 5: PIC10F204/206 only. On all other devices, this bit is reserved and should not be used. DS40001239F-page 14  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 4.4 STATUS Register For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register This register contains the arithmetic status of the ALU, as 000u u1uu (where u = unchanged). the Reset status and the page preselect bit. Therefore, it is recommended that only BCF, BSF and The STATUS register can be the destination for any MOVWF instructions be used to alter the STATUS instruction, as with any other register. If the STATUS register. These instructions do not affect the Z, DC or C register is the destination for an instruction that affects bits from the STATUS register. For other instructions the Z, DC or C bits, then the write to these three bits is which do affect Status bits, see Section10.0 disabled. These bits are set or cleared according to the “Instruction Set Summary”. device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 4-1: STATUS REGISTER R/W-0 R/W-0 U-1 R-1 R-1 R/W-x R/W-x R/W-x GPWUF CWUF(1) — TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWUF: GPIO Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset bit 6 CWUF: Comparator Wake-up on Change Flag bit(1) 1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset conditions. bit 5 Reserved: Do not use. Use of this bit may affect upward compatibility with future products. bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred bit 0 C: Carry/Borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred Note 1: This bit is used on the PIC10F204/206. For code compatibility do not use this bit on the PIC10F200/202.  2004-2014 Microchip Technology Inc. DS40001239F-page 15

PIC10F200/202/204/206 4.5 OPTION Register The OPTION register is a 8-bit wide, write-only register, Note: If TRIS bit is set to ‘0’, the wake-up on which contains various control bits to configure the change and pull-up functions are disabled Timer0/WDT prescaler and Timer0. for that pin (i.e., note that TRIS overrides By executing the OPTION instruction, the contents of Option control of GPPU and GPWU). the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits. Note: If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin. REGISTER 4-2: OPTION REGISTER W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1 GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPWU: Enable Wake-up on Pin Change bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 6 GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin (overrides TRIS on the T0CKI pin) 0 = Transition on internal instruction cycle clock, FOSC/4 bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on the T0CKI pin 0 = Increment on low-to-high transition on the T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 bit 2-0 PS<2:0>: Prescaler Rate Select bits Bit Value Timer0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 . DS40001239F-page 16  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 4.6 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. After you move in the calibration constant, do not change the value. See Section9.2.2 “Internal 4MHz Oscillator”. REGISTER 4-3: OSCCAL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 FOSC4 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 CAL<6:0>: Oscillator Calibration bits 0111111 = Maximum frequency • • • 0000001 0000000 = Center frequency 1111111 • • • 1000000 = Minimum frequency bit 0 FOSC4: INTOSC/4 Output Enable bit(1) 1 = INTOSC/4 output onto GP2 0 = GP2/T0CKI/COUT applied to GP2 Note 1: Overrides GP2/T0CKI/COUT control registers when enabled.  2004-2014 Microchip Technology Inc. DS40001239F-page 17

PIC10F200/202/204/206 4.7 Program Counter 4.7.1 EFFECTS OF RESET As a program instruction is executed, the Program The PC is set upon a Reset, which means that the PC Counter (PC) will contain the address of the next addresses the last location in program memory (i.e., program instruction to be executed. The PC value is the oscillator calibration instruction). After executing increased by one every instruction cycle, unless an MOVLW XX, the PC will roll over to location 0000h and instruction changes the PC. begin executing user code. For a GOTO instruction, bits 8-0 of the PC are provided 4.8 Stack by the GOTO instruction word. The Program Counter Low (PCL) is mapped to PC<7:0>. The PIC10F200/204 devices have a 2-deep, 8-bit wide For a CALL instruction, or any instruction where the hardware PUSH/POP stack. PCL is the destination, bits 7:0 of the PC again are The PIC10F202/206 devices have a 2-deep, 9-bit wide provided by the instruction word. However, PC<8> hardware PUSH/POP stack. does not come from the instruction word, but is always A CALL instruction will PUSH the current value of Stack 1 cleared (Figure4-5). into Stack 2 and then PUSH the current PC value, Instructions where the PCL is the destination, or modify incremented by one, into Stack Level 1. If more than two PCL instructions, include MOVWF PC, ADDWF PC and sequential CALLs are executed, only the most recent two BSF PC,5. return addresses are stored. Note: Because PC<8> is cleared in the CALL A RETLW instruction will POP the contents of Stack instruction or any modify PCL instruction, Level 1 into the PC and then copy Stack Level 2 all subroutine calls or computed jumps are contents into level 1. If more than two sequential limited to the first 256 locations of any RETLWs are executed, the stack will be filled with the program memory page (512 words long). address previously stored in Stack Level 2. Note1: The W register will be loaded with the FIGURE 4-5: LOADING OF PC literal value specified in the instruction. BRANCH INSTRUCTIONS This is particularly useful for the implementation of the data look-up tables GOTO Instruction within the program memory. 8 7 0 2: There are no Status bits to indicate stack PC PCL overflows or stack underflow conditions. 3: There are no instruction mnemonics Instruction Word called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions. CALL or Modify PCL Instruction 8 7 0 PC PCL Instruction Word Reset to ‘0’ DS40001239F-page 18  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 4.9 Indirect Data Addressing: INDF EXAMPLE 4-1: HOW TO CLEAR RAM and FSR Registers USING INDIRECT ADDRESSING The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is MOVLW 0x10 ;initialize pointer contained in the FSR register (FSR is a pointer). This is MOVWF FSR ;to RAM NEXT CLRF INDF ;clear INDF indirect addressing. ;register INCF FSR,F ;inc pointer 4.10 Indirect Addressing BTFSC FSR,4 ;all done? GOTO NEXT ;NO, clear next • Register file 09 contains the value 10h CONTINUE • Register file 0A contains the value 0Ah : ;YES, continue • Load the value 09 into the FSR register : • A read of the INDF register will return the value of10h The FSR is a 5-bit wide register. It is used in • Increment the value of the FSR register by one conjunction with the INDF register to indirectly address (FSR = 0A) the data memory area. • A read of the INDR register now will return the The FSR<4:0> bits are used to select data memory value of 0Ah. addresses 00h to 1Fh. Reading INDF itself indirectly (FSR = 0) will produce Note: PIC10F200/202/204/206 – Do not use 00h. Writing to the INDF register indirectly results in a banking. FSR <7:5> are unimplemented no operation (although Status bits may be affected). and read as ‘1’s. A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example4-1. FIGURE 4-6: DIRECT/INDIRECT ADDRESSING (PIC10F200/202/204/206) Direct Addressing Indirect Addressing 4 (opcode) 0 4 (FSR) 0 Location Select Location Select 00h Data 0Fh Memory(1) 10h 1Fh Bank 0 Note 1: For register map detail, see Section4.3 “Data Memory Organization”.  2004-2014 Microchip Technology Inc. DS40001239F-page 19

PIC10F200/202/204/206 5.0 I/O PORT 5.3 I/O Interfacing As with any other register, the I/O register(s) can be The equivalent circuit for an I/O port pin is shown in written and read under program control. However, read Figure5-1. All port pins, except GP3 which is input- instructions (e.g., MOVF GPIO, W) always read the I/O only, may be used for both input and output operations. pins independent of the pin’s Input/Output modes. On For input operations, these ports are non-latching. Any Reset, all I/O ports are defined as input (inputs are at input must be present until read by an input instruction high-impedance) since the I/O control registers are all (e.g., MOVF GPIO, W). The outputs are latched and set. remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction 5.1 GPIO control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O GPIO is an 8-bit I/O register. Only the low-order 4 bits pin (except GP3) can be programmed individually as are used (GP<3:0>). Bits 7 through 4 are input or output. unimplemented and read as ‘0’s. Please note that GP3 is an input-only pin. Pins GP0, GP1 and GP3 can be FIGURE 5-1: PIC10F200/202/204/206 configured with weak pull-ups and also for wake-up on EQUIVALENT CIRCUIT change. The wake-up on change and weak pull-up FOR A SINGLE I/O PIN functions are not pin selectable. If GP3/MCLR is configured as MCLR, weak pull-up is always on and Data Bus wake-up on change for this pin is not enabled. D Q Data 5.2 TRIS Registers WR Latch VDD VDD Port CK Q The Output Driver Control register is loaded with the P contents of the W register by executing the TRIS f instruction. A ‘1’ from a TRIS register bit puts the corresponding output driver in a High-Impedance W N I/O Reg pin mode. A ‘0’ puts the contents of the output data latch D Q on the selected pins, enabling the output buffer. The TRIS VSS VSS exceptions are GP3, which is input-only and the GP2/ Latch TRIS ‘f’ T0CKI/COUT/FOSC4 pin, which may be controlled by CK Q various registers. See Table5-1. Note: A read of the ports reads the pins, not the Reset output data latches. That is, if an output (1) driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. RD Port The TRIS registers are “write-only” and are set (output Note 1: See Table3-2 for buffer type. drivers disabled) upon Reset. TABLE 5-1: ORDER OF PRECEDENCE FOR PIN FUNCTIONS Priority GP0 GP1 GP2 GP3 1 CIN+ CIN- FOSC4 I/MCLR 2 TRIS GPIO TRIS GPIO COUT — 3 — — T0CKI — 4 — — TRIS GPIO — DS40001239F-page 20  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 TABLE 5-2: SUMMARY OF PORT REGISTERS Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Resets Reset N/A TRISGPIO — — — — I/O Control Register ---- 1111 ---- 1111 N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS GPWUF CWUF — TO PD Z DC C 00-1 1xxx qq-q quuu(1), (2) 06h GPIO — — — — GP3 GP2 GP1 GP0 ---- xxxx ---- uuuu Legend: Shaded cells are not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x = unknown, u = unchanged, q = depends on condition. Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0. 2: If Reset was due to wake-up on comparator change, then bit 6 = 1. All other Resets will cause bit 6 = 0. 5.4 I/O Programming Considerations EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN 5.4.1 BIDIRECTIONAL I/O PORTS I/O PORT Some instructions operate internally as read followed ;Initial GPIO Settings by write operations. The BCF and BSF instructions, for ;GPIO<3:2> Inputs example, read the entire port into the CPU, execute the ;GPIO<1:0> Outputs ; bit operation and rewrite the result. Caution must be ; GPIO latch GPIO pins used when these instructions are applied to a port ; ---------- ---------- where one or more pins are used as input/outputs. For BCF GPIO, 1 ;---- pp01 ---- pp11 example, a BSF operation on bit 2 of GPIO will cause BCF GPIO, 0 ;---- pp10 ---- pp11 all eight bits of GPIO to be read into the CPU, bit 2 to MOVLW 007h; be set and the GPIO value to be written to the output TRIS GPIO ;---- pp10 ---- pp11 latches. If another bit of GPIO is used as a bidirectional ; I/O pin (say bit 0), and it is defined as an input at this Note 1: The user may have expected the pin values to time, the input signal present on the pin itself would be be ---- pp00. The 2nd BCF caused GP1 to read into the CPU and rewritten to the data latch of this be latched as the pin value (High). particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit 0 is switched into Output mode later on, 5.4.2 SUCCESSIVE OPERATIONS ON the content of the data latch may now be unknown. I/O PORTS Example5-1 shows the effect of two sequential The actual write to an I/O port happens at the end of an Read-Modify-Write instructions (e.g., BCF, BSF, etc.) instruction cycle, whereas for reading, the data must be on an I/O port. valid at the beginning of the instruction cycle (Figure5-2). A pin actively outputting a high or a low should not be Therefore, care must be exercised if a write followed by driven from external devices at the same time in order a read operation is carried out on the same I/O port. The to change the level on this pin (“wired OR”, “wired sequence of instructions should allow the pin voltage to AND”). The resulting high output currents may damage stabilize (load dependent) before the next instruction the chip. causes that file to be read into the CPU. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.  2004-2014 Microchip Technology Inc. DS40001239F-page 21

PIC10F200/202/204/206 FIGURE 5-2: SUCCESSIVE I/O OPERATION (PIC10F200/202/204/206) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 This example shows a write to GPIO followed by a Instruction read from GPIO. Fetched MOVWF GPIO MOVF GPIO, W NOP NOP Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle GP<2:0> TPD = propagation delay Therefore, at higher clock frequencies, a Port pin Port pin write followed by a read may be problematic. written here sampled here Instruction Executed MOVWF GPIO MOVF GPIO,W NOP (Write to GPIO) (Read GPIO) DS40001239F-page 22  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 6.0 TIMER0 MODULE AND TMR0 Counter mode is selected by setting the T0CS bit REGISTER (PIC10F200/202) (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The The Timer0 module has the following features: T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. • 8-bit timer/counter register, TMR0 Restrictions on the external clock input are discussed • Readable and writable in detail in Section6.1 “Using Timer0 with an • 8-bit software programmable prescaler External Clock (PIC10F200/202)”. • Internal or external clock select: The prescaler may be used by either the Timer0 - Edge select for external clock module or the Watchdog Timer, but not both. The Figure6-1 is a simplified block diagram of the Timer0 prescaler assignment is controlled in software by the module. control bit, PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not Timer mode is selected by clearing the T0CS bit readable or writable. When the prescaler is assigned to (OPTION<5>). In Timer mode, the Timer0 module will the Timer0 module, prescale values of 1:2, 1:4, 1:256 increment every instruction cycle (without prescaler). If are selectable. Section6.2 “Prescaler” details the TMR0 register is written, the increment is inhibited for operation of the prescaler. the following two cycles (Figure6-2 and Figure6-3). The user can work around this by writing an adjusted A summary of registers associated with the Timer0 value to the TMR0 register. module is found in Table6-1. FIGURE 6-1: TIMER0 BLOCK DIAGRAM Data Bus GP2/T0CKI FOSC/4 0 Pin PSOUT 8 1 Sync with 1 Internal TMR0 Reg Clocks PrPorgersacmalmera(2b)le 0 PSOUT T0SE(1) (2 TCY delay) Sync 3 PS2, PS1, PS0(1) PSA(1) T0CS(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure6-5). FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 (Program Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2  2004-2014 Microchip Technology Inc. DS40001239F-page 23

PIC10F200/202/204/206 FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 (Program Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 NT0 NT0 + 1 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets 01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRISGPIO(1) — — — — I/O Control Register ---- 1111 ---- 1111 Legend: Shaded cells not used by Timer0. – = unimplemented, x = unknown, u = unchanged. Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1. 6.1 Using Timer0 with an External 6.1.1 EXTERNAL CLOCK Clock (PIC10F200/202) SYNCHRONIZATION When no prescaler is used, the external clock input is When an external clock input is used for Timer0, it must the same as the prescaler output. The synchronization meet certain requirements. The external clock of T0CKI with the internal phase clocks is requirement is due to internal phase clock (TOSC) accomplished by sampling the prescaler output on the synchronization. Also, there is a delay in the actual Q2 and Q4 cycles of the internal phase clocks incrementing of Timer0 after synchronization. (Figure6-4). Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 2 Tt0H) and low for at least 2 TOSC (and a small RC delay of 2 Tt0H). Refer to the electrical specification of the desired device. When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4 TOSC (and a small RC delay of 4 Tt0H) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of Tt0H. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. DS40001239F-page 24  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure6-4 shows the delay from the external clock edge to the timer incrementing. FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output(2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 6.2 Prescaler 6.2.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog The prescaler assignment is fully under software Timer (WDT), respectively (see Section9.6 control (i.e., it can be changed “on-the-fly” during “Watchdog Timer (WDT)”). For simplicity, this counter program execution). To avoid an unintended device is being referred to as “prescaler” throughout this data Reset, the following instruction sequence (Example6-1) sheet. must be executed when changing the prescaler assignment from Timer0 to the WDT. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. EXAMPLE 6-1: CHANGING PRESCALER Thus, a prescaler assignment for the (TIMER0 WDT) Timer0 module means that there is no prescaler for the WDT and vice versa. CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 & Prescaler The PSA and PS<2:0> bits (OPTION<3:0>) determine MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7) prescaler assignment and prescale ratio. OPTION ;are required only if ;desired When assigned to the Timer0 module, all instructions CLRWDT ;PS<2:0> are 000 or 001 writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, MOVLW ‘00xx1xxx’b;Set Postscaler to BSF 1,x, etc.) will clear the prescaler. When assigned OPTION ;desired WDT rate to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a Reset, the prescaler contains all ‘0’s.  2004-2014 Microchip Technology Inc. DS40001239F-page 25

PIC10F200/202/204/206 To change the prescaler from the WDT to the Timer0 EXAMPLE 6-2: CHANGING PRESCALER module, use the sequence shown in Example6-2. This (WDTTIMER0) sequence must be used even if the WDT is disabled. A CLRWDT ;Clear WDT and CLRWDT instruction should be executed before ;prescaler switching the prescaler. MOVLW ‘xxxx0xxx’ ;Select TMR0, new ;prescale value and ;clock source OPTION FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY (= FOSC/4) Data Bus GP2/T0CKI(2) 0 M 1 8 Pin U M 1 X Sync U 2 TMR0 Reg 0 X Cycles T0SE(1) T0CS(1) PSA(1) 0 8-bit Prescaler M U 1 X Watchdog 8 Timer 8-to-1 MUX PS<2:0>(1) PSA(1) 0 1 WDT Enable bit MUX PSA(1) WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2: T0CKI is shared with pin GP2 on the PIC10F200/202/204/206. DS40001239F-page 26  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 7.0 TIMER0 MODULE AND TMR0 The second Counter mode uses the output of the REGISTER (PIC10F204/206) comparator to increment Timer0. It can be entered in two different ways. The first way is selected by setting The Timer0 module has the following features: the T0CS bit (OPTION<5>) and clearing the CMPT0CS bit (CMCON<4>); (COUTEN [CMCON<6>]) does not • 8-bit timer/counter register, TMR0 affect this mode of operation. This enables an internal • Readable and writable connection between the comparator and the Timer0. • 8-bit software programmable prescaler The second way is selected by setting the T0CS bit • Internal or external clock select: (OPTION<5>), setting the CMPT0CS bit - Edge select for external clock (CMCON0<4>) and clearing the COUTEN bit - External clock from either the T0CKI pin or (CMCON0<6>). This allows the output of the from the output of the comparator comparator onto the T0CKI pin, while keeping the T0CKI input active. Therefore, any comparator change Figure7-1 is a simplified block diagram of the Timer0 on the COUT pin is fed back into the T0CKI input. The module. T0SE bit (OPTION<4>) determines the source edge. Timer mode is selected by clearing the T0CS bit Clearing the T0SE bit selects the rising edge. (OPTION<5>). In Timer mode, the Timer0 module will Restrictions on the external clock input as discussed in increment every instruction cycle (without prescaler). If Section7.1 “Using Timer0 with an External Clock TMR0 register is written, the increment is inhibited for (PIC10F204/206)” the following two cycles (Figure7-2 and Figure7-3). The prescaler may be used by either the Timer0 The user can work around this by writing an adjusted module or the Watchdog Timer, but not both. The value to the TMR0 register. prescaler assignment is controlled in software by the There are two types of Counter mode. The first Counter control bit, PSA (OPTION<3>). Clearing the PSA bit mode uses the T0CKI pin to increment Timer0. It is will assign the prescaler to Timer0. The prescaler is not selected by setting the T0CS bit (OPTION<5>), setting readable or writable. When the prescaler is assigned to the CMPT0CS bit (CMCON0<4>) and setting the the Timer0 module, prescale values of 1:2, 1:4,..., COUTEN bit (CMCON0<6>). In this mode, Timer0 will 1:256 are selectable. Section7.2 “Prescaler” details increment either on every rising or falling edge of pin the operation of the prescaler. T0CKI. The T0SE bit (OPTION<4>) determines the A summary of registers associated with the Timer0 source edge. Clearing the T0SE bit selects the rising module is found in Table7-1. edge. Restrictions on the external clock input are discussed in detail in Section7.1 “Using Timer0 with an External Clock (PIC10F204/206)”. FIGURE 7-1: TIMER0 BLOCK DIAGRAM (PIC10F204/206) T0CKI Pin Data Bus FOSC/4 0 PSOUT 8 Internal 1 1 Sync with Comparator 0 1 Internal TMR0 Reg Output PrPorgersacmalmera(2b)le 0 Clocks PSOUT T0SE(1) (2 TCY delay) Sync 3 CMPT0CS(3) PS2, PS1, PS0(1) PSA(1) T0CS(1) Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2: The prescaler is shared with the Watchdog Timer (Figure7-5). 3: Bit CMPT0CS is located in the CMCON0 register, CMCON0<4>.  2004-2014 Microchip Technology Inc. DS40001239F-page 27

PIC10F200/202/204/206 FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3 Q4 (Program Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC+5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC Q1Q2 Q3 Q4Q1Q2Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 (Program Counter) PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6 Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Fetch Timer0 T0 T0 + 1 NT0 NT0 + 1 Instruction Executed Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2 TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0 Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets 01h TMR0 Timer0 – 8-bit Real-Time Clock/Counter xxxx xxxx uuuu uuuu 07h CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 uuuu uuuu N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRISGPIO(1) — — — — I/O Control Register ---- 1111 ---- 1111 Legend: Shaded cells not used by Timer0. – = unimplemented, x = unknown, u = unchanged. Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1. 7.1 Using Timer0 with an External small RC delay of 2 Tt0H) and low for at least 2 TOSC Clock (PIC10F204/206) (and a small RC delay of 2 Tt0H). Refer to the electrical specification of the desired device. When an external clock input is used for Timer0, it must When a prescaler is used, the external clock input is meet certain requirements. The external clock divided by the asynchronous ripple counter type requirement is due to internal phase clock (TOSC) prescaler, so that the prescaler output is symmetrical. synchronization. Also, there is a delay in the actual For the external clock to meet the sampling incrementing of Timer0 after synchronization. requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI or the 7.1.1 EXTERNAL CLOCK comparator output to have a period of at least 4 TOSC SYNCHRONIZATION (and a small RC delay of 4 Tt0H) divided by the When no prescaler is used, the external clock input is prescaler value. The only requirement on T0CKI or the the same as the prescaler output. The synchronization comparator output high and low time is that they do not of an external clock with the internal phase clocks is violate the minimum pulse width requirement of Tt0H. accomplished by sampling the prescaler output on the Refer to parameters 40, 41 and 42 in the electrical Q2 and Q4 cycles of the internal phase clocks specification of the desired device. (Figure7-4). Therefore, it is necessary for T0CKI or the comparator output to be high for at least 2 TOSC (and a DS40001239F-page 28  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 7.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure7-4 shows the delay from the external clock edge to the timer incrementing. FIGURE 7-4: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Small pulse Prescaler Output(2) misses sampling (1) External Clock/Prescaler (3) Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max. 2: External clock if no prescaler selected; prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 7.2 Prescaler 7.2.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog The prescaler assignment is fully under software Timer (WDT), respectively (see Figure9-6). For control (i.e., it can be changed “on-the-fly” during simplicity, this counter is being referred to as program execution). To avoid an unintended device “prescaler” throughout this data sheet. Reset, the following instruction sequence (Example7-1) must be executed when changing the prescaler Note: The prescaler may be used by either the assignment from Timer0 to the WDT. Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the EXAMPLE 7-1: CHANGING PRESCALER Timer0 module means that there is no (TIMER0 WDT) prescaler for the WDT and vice versa. CLRWDT ;Clear WDT The PSA and PS<2:0> bits (OPTION<3:0>) determine CLRF TMR0 ;Clear TMR0 & Prescaler prescaler assignment and prescale ratio. MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7) OPTION ;are required only if When assigned to the Timer0 module, all instructions ;desired writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, CLRWDT ;PS<2:0> are 000 or 001 BSF 1,x, etc.) will clear the prescaler. When assigned MOVLW ‘00xx1xxx’b;Set Postscaler to to WDT, a CLRWDT instruction will clear the prescaler OPTION ;desired WDT rate along with the WDT. The prescaler is neither readable nor writable. On a Reset, the prescaler contains all ‘0’s. To change the prescaler from the WDT to the Timer0 module, use the sequence shown in Example7.2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.  2004-2014 Microchip Technology Inc. DS40001239F-page 29

PIC10F200/202/204/206 EXAMPLE 7-2: CHANGING PRESCALER (WDTTIMER0) CLRWDT ;Clear WDT and ;prescaler MOVLW ‘xxxx0xxx’ ;Select TMR0, new ;prescale value and ;clock source OPTION FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER GP2/T0CKI(2) Pin TCY (= FOSC/4) Data Bus 0 8 M 1 1 U Comparator 1 X M Sync Output U 2 TMR0 Reg 0 0 X Cycles T0SE(1) T0CS(1) PSA(1) CMPT0CS(3) 0 8-bit Prescaler M U 1 X Watchdog 8 Timer 8-to-1 MUX PS<2:0>(1) PSA(1) 0 1 WDT Enable bit MUX PSA(1) WDT Time-out Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. 2: T0CKI is shared with pin GP2. 3: Bit CMPT0CS is located in the CMCON0 register. DS40001239F-page 30  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 8.0 COMPARATOR MODULE The comparator module contains one Analog comparator. The inputs to the comparator are multiplexed with GP0 and GP1 pins. The output of the comparator can be placed on GP2. The CMCON0 register, shown in Register8-1, controls the comparator operation. A block diagram of the comparator is shown in Figure8-1. REGISTER 8-1: CMCON0 REGISTER R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CMPOUT: Comparator Output bit 1 = VIN+ > VIN- 0 = VIN+ < VIN- bit 6 COUTEN: Comparator Output Enable bit(1, 2) 1 = Output of comparator is NOT placed on the COUT pin 0 = Output of comparator is placed in the COUT pin bit 5 POL: Comparator Output Polarity bit(2) 1 = Output of comparator not inverted 0 = Output of comparator inverted bit 4 CMPT0CS: Comparator TMR0 Clock Source bit(2) 1 = TMR0 clock source selected by T0CS control bit 0 = Comparator output used as TMR0 clock source bit 3 CMPON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off bit 2 CNREF: Comparator Negative Reference Select bit(2) 1 = CIN- pin(3) 0 = Internal voltage reference bit 1 CPREF: Comparator Positive Reference Select bit(2) 1 = CIN+ pin(3) 0 = CIN- pin(3) bit 0 CWU: Comparator Wake-up on Change Enable bit(2) 1 = Wake-up on comparator change is disabled 0 = Wake-up on comparator change is enabled. Note 1: Overrides T0CS bit for TRIS control of GP2. 2: When the comparator is turned on, these control bits assert themselves. When the comparator is off, these bits have no effect on the device operation and the other control registers have precedence. 3: PIC10F204/206 only.  2004-2014 Microchip Technology Inc. DS40001239F-page 31

PIC10F200/202/204/206 8.1 Comparator Configuration The on-board comparator inputs, (GP0/CIN+, GP1/ Note: The comparator can have an inverted CIN-), as well as the comparator output (GP2/COUT), output (see Figure8-1). are steerable. The CMCON0, OPTION and TRIS registers are used to steer these pins (see Figure8-1). If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table12-1. FIGURE 8-1: BLOCK DIAGRAM OF THE COMPARATOR CPREF T0CKI/GP2/COUT C+ COUTEN + C- COUT (Register) Band Gap Buffer - (0.6V) CNREF POL CMPON T0CKI T0CKI Pin T0CKSEL CWU Q D S Read CWUF CMCON TABLE 8-1: TMR0 CLOCK SOURCE FUNCTION MUXING T0CS CMPT0CS COUTEN Source 0 x x Internal Instruction Cycle 1 0 0 CMPOUT 1 0 1 CMPOUT 1 1 0 CMPOUT 1 1 1 T0CKI DS40001239F-page 32  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 8.2 Comparator Operation 8.5 Comparator Output A single comparator is shown in Figure8-2 along with The comparator output is read through CMCON0 the relationship between the analog input levels and register. This bit is read-only. The comparator output the digital output. When the analog input at VIN+ is less may also be used internally, see Figure8-1. than the analog input VIN-, the output of the comparator Note: Analog levels on any pin that is defined as is a digital low level. When the analog input at VIN+ is a digital input may cause the input buffer greater than the analog input VIN-, the output of the to consume more current than is comparator is a digital high level. The shaded areas of specified. the output of the comparator in Figure8-2 represent the uncertainty due to input offsets and response time. See Table12-1 for Common Mode Voltage. 8.6 Comparator Wake-up Flag The comparator wake-up flag is set whenever all of the FIGURE 8-2: SINGLE COMPARATOR following conditions are met: • CWU = 0 (CMCON0<0>) Vin+ + Result • CMCON0 has been read to latch the last known Vin- – state of the CMPOUT bit (MOVF CMCON0, W) • Device is in Sleep • The output of the comparator has changed state The wake-up flag may be cleared in software or by another device Reset. VIN- 8.7 Comparator Operation During VIN+ Sleep When the comparator is active and the device is placed in Sleep mode, the comparator remains active. While the comparator is powered-up, higher Sleep currents Result than shown in the power-down current specification will occur. To minimize power consumption while in Sleep 8.3 Comparator Reference mode, turn off the comparator before entering Sleep. An internal reference signal may be used depending on 8.8 Effects of a Reset the Comparator Operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+ A Power-on Reset (POR) forces the CMCON0 register and the digital output of the comparator is adjusted to its Reset state. This forces the comparator module to accordingly (Figure8-2). Please see Table12-1 for be in the comparator Reset mode. This ensures that all internal reference specifications. potential inputs are analog inputs. Device current is minimized when analog inputs are present at Reset 8.4 Comparator Response Time time. The comparator will be powered-down during the Reset interval. Response time is the minimum time, after selecting a new reference voltage or input source, before the 8.9 Analog Input Connection comparator output is to have a valid level. If the Considerations comparator inputs are changed, a delay must be used to allow the comparator to settle to its new state. Please A simplified circuit for an analog input is shown in see Table12-1 for comparator response time Figure8-3. Since the analog pins are connected to a specifications. digital output, they have reverse biased diodes to VDD and VSS. The analog input therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.  2004-2014 Microchip Technology Inc. DS40001239F-page 33

PIC10F200/202/204/206 FIGURE 8-3: ANALOG INPUT MODE VDD RS < 10k VT = 0.6V RIC AIN VA C5PpIFN VT = 0.6V I±L5E0A0KAnGAE VSS Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the Pin RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage TABLE 8-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other POR Resets 03h STATUS GPWUF CWUF — TO PD Z DC C 00-1 1xxx qq0q quuu 07h CMCON0 CMPOUT COUTEN POL CMPT0CS CMPON CNREF CPREF CWU 1111 1111 uuuu uuuu N/A TRISGPIO — — — — I/O Control Register ---- 1111 ---- 1111 Legend: x = Unknown, u = Unchanged, – = Unimplemented, read as ‘0’, q = Depends on condition. DS40001239F-page 34  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 9.0 SPECIAL FEATURES OF THE The PIC10F200/202/204/206 devices have a CPU Watchdog Timer, which can be shut off only through Configuration bit WDTE. It runs off of its own RC What sets a microcontroller apart from other oscillator for added reliability. When using INTRC, processors are special circuits that deal with the needs there is an 18ms delay only on VDD power-up. With of real-time applications. The PIC10F200/202/204/206 this timer on-chip, most applications need no external microcontrollers have a host of such features intended Reset circuitry. to maximize system reliability, minimize cost through The Sleep mode is designed to offer a very low-current elimination of external components, provide power- Power-Down mode. The user can wake-up from Sleep saving operating modes and offer code protection. through a change on input pins, wake-up from These features are: comparator change, or through a Watchdog Timer • Reset: time-out. - Power-on Reset (POR) 9.1 Configuration Bits - Device Reset Timer (DRT) - Watchdog Timer (WDT) The PIC10F200/202/204/206 Configuration Words - Wake-up from Sleep on pin change consist of 12 bits. Configuration bits can be - Wake-up from Sleep on comparator change programmed to select various device configurations. One bit is the Watchdog Timer enable bit, one bit is the • Sleep MCLR enable bit and one bit is for code protection (see • Code Protection Register9-1). • ID Locations • In-Circuit Serial Programming™ • Clock Out REGISTER 9-1: CONFIGURATION WORD FOR PIC10F200/202/204/206(1,2) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — — — — — MCLRE CP WDTE — — bit 11 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 11-5 Unimplemented: Read as ‘0’ bit 4 MCLRE: GP3/MCLR Pin Function Select bit 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD bit 3 CP: Code Protection bit 1 = Code protection off 0 = Code protection on bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 Reserved: Read as ‘0’ Note 1: Refer to the “PIC10F200/202/204/206 Memory Programming Specifications” (DS41228) to determine how to access the Configuration Word. The Configuration Word is not user addressable during device operation. 2: INTRC is the only oscillator mode offered on the PIC10F200/202/204/206.  2004-2014 Microchip Technology Inc. DS40001239F-page 35

PIC10F200/202/204/206 9.2 Oscillator Configurations 9.3 Reset 9.2.1 OSCILLATOR TYPES The device differentiates between various kinds of Reset: The PIC10F200/202/204/206 devices are offered with • Power-on Reset (POR) Internal Oscillator mode only. • MCLR Reset during normal operation • INTOSC: Internal 4MHz Oscillator • MCLR Reset during Sleep 9.2.2 INTERNAL 4MHz OSCILLATOR • WDT time-out Reset during normal operation The internal oscillator provides a 4MHz (nominal) system • WDT time-out Reset during Sleep clock (see Section12.0 “Electrical Characteristics” for • Wake-up from Sleep on pin change information on variation over voltage and temperature). • Wake-up from Sleep on comparator change In addition, a calibration instruction is programmed into Some registers are not reset in any way, they are the last address of memory, which contains the unknown on POR and unchanged in any other Reset. calibration value for the internal oscillator. This location Most other registers are reset to “Reset state” on is always uncode protected, regardless of the code- Power-on Reset (POR), MCLR, WDT or Wake-up on protect settings. This value is programmed as a MOVLW pin change Reset during normal operation. They are xx instruction where xx is the calibration value and is not affected by a WDT Reset during Sleep or MCLR placed at the Reset vector. This will load the W register Reset during Sleep, since these Resets are viewed as with the calibration value upon Reset and the PC will resumption of normal operation. The exceptions to this then roll over to the users program at address 0x000. are TO, PD, GPWUF and CWUF bits. They are set or The user then has the option of writing the value to the cleared differently in different Reset situations. These OSCCAL Register (05h) or ignoring it. bits are used in software to determine the nature of Reset. See Table9-1 for a full description of Reset OSCCAL, when written to with the calibration value, will states of all registers. “trim” the internal oscillator to remove process variation from the oscillator frequency. Note: Erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. TABLE 9-1: RESET CONDITIONS FOR REGISTERS – PIC10F200/202/204/206 MCLR Reset, WDT Time-out, Register Address Power-on Reset Wake-up On Pin Change, Wake on Comparator Change W — qqqq qqqu(1) qqqq qqqu(1) INDF 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PCL 02h 1111 1111 1111 1111 STATUS 03h 00-1 1xxx q00q quuu(2) STATUS(3) 03h 00-1 1xxx qq0q quuu(2) FSR 04h 111x xxxx 111u uuuu OSCCAL 05h 1111 1110 uuuu uuuu GPIO 06h ---- xxxx ---- uuuu CMCON(3) 07h 1111 1111 uuuu uuuu OPTION — 1111 1111 1111 1111 TRISGPIO — ---- 1111 ---- 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table9-2 for Reset value for specific conditions. 3: PIC10F204/206 only. DS40001239F-page 36  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 TABLE 9-2: RESET CONDITION FOR SPECIAL REGISTERS — STATUS Address: 03h PCL Address: 02h Power-on Reset 00-1 1xxx 1111 1111 MCLR Reset during normal operation 000u uuuu 1111 1111 MCLR Reset during Sleep 0001 0uuu 1111 1111 WDT Reset during Sleep 0000 0uuu 1111 1111 WDT Reset normal operation 0000 uuuu 1111 1111 Wake-up from Sleep on pin change 1001 0uuu 1111 1111 Wake-up from Sleep on comparator change 0101 0uuu 1111 1111 Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’. 9.3.1 MCLR ENABLE The Power-on Reset circuit and the Device Reset Timer (see Section9.5 “Device Reset Timer (DRT)”) This Configuration bit, when unprogrammed (left in the circuit are closely related. On power-up, the Reset latch ‘1’ state), enables the external MCLR function. When is set and the DRT is reset. The DRT timer begins programmed, the MCLR function is tied to the internal counting once it detects MCLR to be high. After the VDD and the pin is assigned to be a I/O. See Figure9-1. time-out period, which is typically 18ms, it will reset the Reset latch and thus end the on-chip Reset signal. FIGURE 9-1: MCLR SELECT A power-up example where MCLR is held low is shown in Figure9-3. VDD is allowed to rise and stabilize before GPWU bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. GP3/MCLR/VPP In Figure9-4, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together or the pin MCLRE Internal MCLR is programmed to be GP3). The VDD is stable before the Start-up Timer times out and there is no problem in getting a proper Reset. However, Figure9-5 depicts a problem situation where VDD rises too slowly. The time 9.4 Power-on Reset (POR) between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value, is The PIC10F200/202/204/206 devices incorporate an too long. In this situation, when the Start-up Timer times on-chip Power-on Reset (POR) circuitry, which out, VDD has not reached the VDD (min) value and the provides an internal chip Reset for most power-up chip may not function correctly. For such situations, we situations. recommend that external RC circuits be used to achieve longer POR delay times (Figure9-4). The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper Note: When the devices start normal operation operation. To take advantage of the internal POR, (exit the Reset condition), device program the GP3/MCLR/VPP pin as MCLR and tie operating parameters (voltage, frequency, through a resistor to VDD, or program the pin as GP3. temperature, etc.) must be met to ensure An internal weak pull-up resistor is implemented using operation. If these conditions are not met, a transistor (refer to Table12-2 for the pull-up resistor the device must be held in Reset until the ranges). This will eliminate external RC components operating conditions are met. usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See For additional information, refer to Application Notes Section12.0 “Electrical Characteristics” for details. AN522 “Power-up Considerations”, (DS00522) and AN607 “Power-up Trouble Shooting”, (DS00000607). When the devices start normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the devices must be held in Reset until the operating parameters are met. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure9-2.  2004-2014 Microchip Technology Inc. DS40001239F-page 37

PIC10F200/202/204/206 FIGURE 9-2: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT VDD Power-up Detect POR (Power-on Reset) GP3/MCLR/VPP MCLR Reset S Q MCLRE R Q WDT Reset WDT Time-out Start-up Timer CHIP Reset Pin Change (10 s or 18 ms) Sleep Wake-up on pin change Reset FIGURE 9-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR Internal POR TDRT DRT Time-out Internal Reset FIGURE 9-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR Internal POR TDRT DRT Time-out Internal Reset DS40001239F-page 38  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 FIGURE 9-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR Internal POR TDRT DRT Time-out Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1  VDD min.  2004-2014 Microchip Technology Inc. DS40001239F-page 39

PIC10F200/202/204/206 9.5 Device Reset Timer (DRT) 9.6.1 WDT PERIOD On the PIC10F200/202/204/206 devices, the DRT runs The WDT has a nominal time-out period of 18ms, (with any time the device is powered-up. no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be The DRT operates on an internal oscillator. The assigned to the WDT (under software control) by processor is kept in Reset as long as the DRT is active. writing to the OPTION register. Thus, a time-out period The DRT delay allows VDD to rise above VDD min. and of a nominal 2.3 seconds can be realized. These for the oscillator to stabilize. periods vary with temperature, VDD and part-to-part The on-chip DRT keeps the devices in a Reset process variations (see DC specs). condition for approximately 18ms after MCLR has Under worst-case conditions (VDD = Min., Temperature reached a logic high (VIH MCLR) level. Programming = Max., max. WDT prescaler), it may take several GP3/MCLR/VPP as MCLR and using an external RC seconds before a WDT time-out occurs. network connected to the MCLR input is not required in most cases. This allows savings in cost-sensitive and/ 9.6.2 WDT PROGRAMMING or space restricted applications, as well as allowing the CONSIDERATIONS use of the GP3/MCLR/VPP pin as a general purpose input. The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from The Device Reset Time delays will vary from chip-to- timing out and generating a device Reset. chip due to VDD, temperature and process variation. See AC parameters for details. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the Reset sources are POR, MCLR, WDT time-out and maximum Sleep time before a WDT wake-up Reset. wake-up on pin change. See Section9.9.2 “Wake-up from Sleep”, Notes 1, 2 and 3. TABLE 9-3: DRT PERIOD Subsequent Oscillator POR Reset Resets INTOSC 18ms (typical) 10s (typical) 9.6 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the internal 4MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or wake-up Reset, generates a device Reset. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by programming the configuration WDTE as a ‘0’ (see Section9.1 “Configuration Bits”). Refer to the PIC10F200/202/204/206 Programming Specifications to determine how to access the Configuration Word. DS40001239F-page 40  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 FIGURE 9-6: WATCHDOG TIMER BLOCK DIAGRAM From Timer0 Clock Source (Figure6-5) 0 M Watchdog 1 U PPoossttssccaalleerr Time X 8-to-1 MUX PS<2:0> PSA WDT Enable Configuration To Timer0 (Figure6-4) Bit 0 1 MUX PSA WDT Time-out TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On All Other Reset Resets N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u = unchanged.  2004-2014 Microchip Technology Inc. DS40001239F-page 41

PIC10F200/202/204/206 9.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF, CWUF) The TO, PD, GPWUF and CWUF bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR, Watchdog Timer (WDT) Reset, wake-up on comparator change or wake-up on pin change. TABLE 9-5: TO, PD, GPWUF, CWUF STATUS AFTER RESET CWUF GPWUF TO PD Reset Caused By 0 0 0 0 WDT wake-up from Sleep 0 0 0 u WDT time-out (not from Sleep) 0 0 1 0 MCLR wake-up from Sleep 0 0 1 1 Power-up 0 0 u u MCLR not during Sleep 0 1 1 0 Wake-up from Sleep on pin change 1 0 1 0 Wake-up from Sleep on comparator change Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: The TO, PD, GPWUF and CWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR input does not change the TO, PD, GPWUF or CWUF Status bits. 9.8 Reset on Brown-out FIGURE 9-8: BROWN-OUT PROTECTION CIRCUIT 2 A Brown-out Reset is a condition where device power (VDD) dips below its minimum value, but not to zero, VDD and then recovers. The device should be reset in the VDD event of a brown-out. R1 To reset PIC10F200/202/204/206 devices when a PIC10F20X Brown-out Reset occurs, external brown-out protection Q1MCLR(2) circuits may be built, as shown in Figure9-7 and Figure9-8. R2 40k(1) FIGURE 9-7: BROWN-OUT PROTECTION CIRCUIT 1 VDD Note 1: This brown-out circuit is less expensive, VDD although less accurate. Transistor Q1 turns off when VDD is below a certain level such 33k that: R1 10k Q1 MCLR(2) PIC10F20X VDD • R1 + R2 = 0.7V 40k(1) 2: Pin must be confirmed as MCLR. Note 1: This circuit will activate Reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). 2: Pin must be confirmed as MCLR. DS40001239F-page 42  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 FIGURE 9-9: BROWN-OUT 9.9.2 WAKE-UP FROM SLEEP PROTECTION CIRCUIT 3 The device can wake-up from Sleep through one of VDD the following events: MCP809 Bypass VDD 1. Awnh eenx tceornnfaigl Rureesde at sin MpuCt LoRn. GP3/MCLR/VPP pin, VSS Capacitor VDD 2. A Watchdog Timer time-out Reset (if WDT was enabled). RST MCLR 3. A change on input pin GP0, GP1 or GP3 when PIC10F20X wake-up on change is enabled. 4. A comparator output change has occurred when wake-up on comparator change is enabled. Note: This brown-out protection circuit employs Microchip Technology’s MCP809 These events cause a device Reset. The TO, PD microcontroller supervisor. There are GPWUF and CWUF bits can be used to determine the seven different trip point selections to cause of device Reset. The TO bit is cleared if a WDT accommodate 5V to 3V systems. time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The GPWUF bit indicates a change in state 9.9 Power-down Mode (Sleep) while in Sleep at pins GP0, GP1 or GP3 (since the last A device may be powered-down (Sleep) and later file or bit operation on GP port). The CWUF bit powered-up (wake-up from Sleep). indicates a change in the state while in Sleep of the comparator output. 9.9.1 SLEEP Caution: Right before entering Sleep, read the The Power-down mode is entered by executing a input pins. When in Sleep, wake-up SLEEP instruction. occurs when the values at the pins change from the state they were in at the If enabled, the Watchdog Timer will be cleared but last reading. If a wake-up on change keeps running, the TO bit (STATUS<4>) is set, the PD occurs and the pins are not read before bit (STATUS<3>) is cleared and the oscillator driver is re-entering Sleep, a wake-up will occur turned off. The I/O ports maintain the status they had immediately even if no pins change before the SLEEP instruction was executed (driving while in Sleep mode. high, driving low or high-impedance). Note: A Reset generated by a WDT time-out does not drive the MCLR pin low. Note: The WDT is cleared when the device For lowest current consumption while powered-down, wakes from Sleep, regardless of the the T0CKI input should be at VDD or VSS and the GP3/ wake-up source. MCLR/VPP pin must be at a logic high level if MCLR is enabled.  2004-2014 Microchip Technology Inc. DS40001239F-page 43

PIC10F200/202/204/206 9.10 Program Verification/Code FIGURE 9-10: TYPICAL IN-CIRCUIT Protection SERIAL PROGRAMMING™ If the code protection bit has not been programmed, the CONNECTION on-chip program memory can be read out for verification purposes. To Normal The first 64 locations and the last location (Reset External Connections vector) can be read, regardless of the code protection Connector PIC10F20X Signals bit setting. +5V VDD 9.11 ID Locations 0V VSS Four memory locations are designated as ID locations VPP MCLR/VPP where the user can store checksum or other code CLK GP1 identification numbers. These locations are not accessible during normal execution, but are readable Data I/O GP0 and writable during Program/Verify. Use only the lower four bits of the ID locations and VDD always program the upper eight bits as ‘0’s. To Normal 9.12 In-Circuit Serial Programming™ Connections The PIC10F200/202/204/206 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware, to be programmed. The devices are placed into a Program/Verify mode by holding the GP1 and GP0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). GP1 becomes the programming clock and GP0 becomes the programming data. Both GP1 and GP0 are Schmitt Trigger inputs in this mode. After Reset, a 6-bit command is then supplied to the device. Depending on the command, 16 bits of program data are then supplied to or from the device, depending if the command was a Load or a Read. For complete details of serial programming, please refer to the PIC10F200/202/204/206 Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure9-10. DS40001239F-page 44  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 10.0 INSTRUCTION SET SUMMARY All instructions are executed within a single instruction cycle, unless a conditional test is true or the program The PIC16 instruction set is highly orthogonal and is counter is changed as a result of an instruction. In this comprised of three basic categories. case, the execution takes two instruction cycles. One • Byte-oriented operations instruction cycle consists of four oscillator periods. • Bit-oriented operations Thus, for an oscillator frequency of 4MHz, the normal • Literal and control operations instruction execution time is 1s. If a conditional test is true or the program counter is changed as a result of an Each PIC16 instruction is a 12-bit word divided into an instruction, the instruction execution time is 2s. opcode, which specifies the instruction type and one or more operands which further specify the operation of Figure10-1 shows the three general formats that the the instruction. The formats for each of the categories instructions can have. All examples in the figure use is presented in Figure10-1, while the various opcode the following format to represent a hexadecimal fields are summarized in Table10-1. number: For byte-oriented instructions, ‘f’ represents a file 0xhhh register designator and ‘d’ represents a destination where ‘h’ signifies a hexadecimal digit. designator. The file register designator specifies which file register is to be used by the instruction. FIGURE 10-1: GENERAL FORMAT FOR The destination designator specifies where the result of INSTRUCTIONS the operation is to be placed. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed Byte-oriented file register operations in the file register specified in the instruction. 11 6 5 4 0 For bit-oriented instructions, ‘b’ represents a bit field OPCODE d f (FILE #) designator which selects the number of the bit affected d = 0 for destination W by the operation, while ‘f’ represents the number of the d = 1 for destination f file in which the bit is located. f = 5-bit file register address For literal and control operations, ‘k’ represents an Bit-oriented file register operations 8or 9-bit constant or literal value. 11 8 7 5 4 0 TABLE 10-1: OPCODE FIELD OPCODE b (BIT #) f (FILE #) DESCRIPTIONS b = 3-bit address Field Description f = 5-bit file register address f Register file address (0x00 to 0x7F) Literal and control operations (except GOTO) W Working register (accumulator) 11 8 7 0 b Bit address within an 8-bit file register OPCODE k (literal) k Literal field, constant data or label k = 8-bit immediate value x Don’t care location (= 0 or 1) The assembler will generate code with x = 0. It is Literal and control operations – GOTO instruction the recommended form of use for compatibility with all Microchip software tools. 11 9 8 0 d Destination select; OPCODE k (literal) d = 0 (store result in W) k = 9-bit immediate value d = 1 (store result in file register ‘f’) Default is d = 1 label Label name TOS Top-of-Stack PC Program Counter WDT Watchdog Timer counter TO Time-out bit PD Power-down bit dest Destination, either the W register or the specified register file location [ ] Options ( ) Contents  Assigned to < > Register bit field  In the set of italics User defined term (font is courier)  2004-2014 Microchip Technology Inc. DS40001239F-page 45

PIC10F200/202/204/206 TABLE 10-2: INSTRUCTION SET SUMMARY 12-Bit Opcode Mnemonic, Status Description Cycles Notes Operands Affected MSb LSb ADDWF f, d Add W and f 1 0001 11df ffff C, DC, Z 1, 2, 4 ANDWF f, d AND W with f 1 0001 01df ffff Z 2, 4 CLRF f Clear f 1 0000 011f ffff Z 4 CLRW — Clear W 1 0000 0100 0000 Z COMF f, d Complement f 1 0010 01df ffff Z DECF f, d Decrement f 1 0000 11df ffff Z 2, 4 DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2, 4 INCF f, d Increment f 1 0010 10df ffff Z 2, 4 INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2, 4 IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2, 4 MOVF f, d Move f 1 0010 00df ffff Z 2, 4 MOVWF f Move W to f 1 0000 001f ffff None 1, 4 NOP — No Operation 1 0000 0000 0000 None RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2, 4 RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2, 4 SUBWF f, d Subtract W from f 1 0000 10df ffff C, DC, Z 1, 2, 4 SWAPF f, d Swap f 1 0011 10df ffff None 2, 4 XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f 1 0100 bbbf ffff None 2, 4 BSF f, b Bit Set f 1 0101 bbbf ffff None 2, 4 BTFSC f, b Bit Test f, Skip if Clear 1(2) 0110 bbbf ffff None BTFSS f, b Bit Test f, Skip if Set 1(2) 0111 bbbf ffff None LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL k Call Subroutine 2 1001 kkkk kkkk None 1 CLRWDT Clear Watchdog Timer 1 0000 0000 0100 TO, PD GOTO k Unconditional branch 2 101k kkkk kkkk None IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk Z MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION — Load OPTION register 1 0000 0000 0010 None RETLW k Return, place Literal in W 2 1000 kkkk kkkk None SLEEP — Go into Standby mode 1 0000 0000 0011 TO, PD TRIS f Load TRIS register 1 0000 0000 0fff None 3 XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Z Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for GOTO. See Section4.7 “Program Counter”. 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0). DS40001239F-page 46  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 ADDWF Add W and f BCF Bit Clear f Syntax: [ label ] ADDWF f,d Syntax: [ label ] BCF f,b Operands: 0  f  31 Operands: 0  f  31 d 01 0  b  7 Operation: (W) + (f)  (dest) Operation: 0  (f<b>) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is cleared. and register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W BSF Bit Set f Syntax: [ label ] ANDLW k Syntax: [ label ] BSF f,b Operands: 0  k  255 Operands: 0  f  31 0  b  7 Operation: (W).AND. (k)  (W) Operation: 1  (f<b>) Status Affected: Z Status Affected: None Description: The contents of the W register are AND’ed with the 8-bit literal ‘k’. The Description: Bit ‘b’ in register ‘f’ is set. result is placed in the W register. ANDWF AND W with f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDWF f,d Syntax: [ label ] BTFSC f,b Operands: 0  f  31 d [0,1] Operands: 0  f  31 0  b  7 Operation: (W) .AND. (f)  (dest) Operation: skip if (f<b>) = 0 Status Affected: Z Status Affected: None Description: The contents of the W register are AND’ed with register ‘f’. If ‘d’ is ‘0’, Description: If bit ‘b’ in register ‘f’ is ‘0’, then the the result is stored in the W register. next instruction is skipped. If ‘d’ is ‘1’, the result is stored back If bit ‘b’ is ‘0’, then the next in register ‘f’. instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a 2-cycle instruction.  2004-2014 Microchip Technology Inc. DS40001239F-page 47

PIC10F200/202/204/206 BTFSS Bit Test f, Skip if Set CLRW Clear W Syntax: [ label ] CLRW Syntax: [ label ] BTFSS f,b Operands: None Operands: 0  f  31 0  b < 7 Operation: 00h  (W); 1  Z Operation: skip if (f<b>) = 1 Status Affected: Z Status Affected: None Description: The W register is cleared. Zero bit Description: If bit ‘b’ in register ‘f’ is ‘1’, then the (Z) is set. next instruction is skipped. If bit ‘b’ is ‘1’, then the next instruc- tion fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a 2-cycle instruction. CALL Subroutine Call CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0  k  255 Operands: None Operation: (PC) + 1 Top-of-Stack; Operation: 00h  WDT; k  PC<7:0>; 0  WDT prescaler (if assigned); (STATUS<6:5>)  PC<10:9>; 1  TO; 0  PC<8> 1  PD Status Affected: None Status Affected: TO, PD Description: Subroutine call. First, return Description: The CLRWDT instruction resets the address (PC + 1) is PUSHed onto WDT. It also resets the prescaler, if the stack. The 8-bit immediate the prescaler is assigned to the address is loaded into PC WDT and not Timer0. Status bits bits <7:0>. The upper bits TO and PD are set. PC<10:9> are loaded from STATUS<6:5>, PC<8> is cleared. CALL is a 2-cycle instruction. CLRF Clear f COMF Complement f Syntax: [ label ] CLRF f Syntax: [ label ] COMF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] Operation: 00h  (f); 1  Z Operation: (f)  (dest) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are cleared and the Z bit is set. complemented. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001239F-page 48  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 DECF Decrement f INCF Increment f Syntax: [ label ] DECF f,d Syntax: [ label ] INCF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: (f) – 1  (dest) Operation: (f) + 1  (dest) Status Affected: Z Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, Description: The contents of register ‘f’ are the result is stored in the W incremented. If ‘d’ is ‘0’, the result register. If ‘d’ is ‘1’, the result is is placed in the W register. If ‘d’ is stored back in register ‘f’. ‘1’, the result is placed back in register ‘f’. DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: (f) – 1  d; skip if result = 0 Operation: (f) + 1  (dest), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is ‘1’, the result is placed back in ‘1’, the result is placed back in register ‘f’. register ‘f’. If the result is ‘0’, the next instruc- If the result is ‘0’, then the next tion, which is already fetched, is instruction, which is already discarded and a NOP is executed fetched, is discarded and a NOP is instead making it a 2-cycle instruc- executed instead making it a tion. 2-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k Operands: 0  k  511 Operands: 0  k  255 Operation: k  PC<8:0>; Operation: (W) .OR. (k)  (W) STATUS<6:5>  PC<10:9> Status Affected: Z Status Affected: None Description: The contents of the W register are Description: GOTO is an unconditional branch. OR’ed with the 8-bit literal ‘k’. The The 9-bit immediate value is result is placed in the W register. loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS<6:5>. GOTO is a 2-cycle instruction.  2004-2014 Microchip Technology Inc. DS40001239F-page 49

PIC10F200/202/204/206 IORWF Inclusive OR W with f MOVWF Move W to f Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVWF f Operands: 0  f  31 Operands: 0  f  31 d  [0,1] Operation: (W)  (f) Operation: (W).OR. (f)  (dest) Status Affected: None Status Affected: Z Description: Move data from the W register to Description: Inclusive OR the W register with register ‘f’. register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. MOVF Move f NOP No Operation Syntax: [ label ] MOVF f,d Syntax: [ label ] NOP Operands: 0  f  31 Operands: None d  [0,1] Operation: No operation Operation: (f)  (dest) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register ‘f’ are moved to destination ‘d’. If ‘d’ is ‘0’, destination is the W register. If ‘d’ is ‘1’, the destination is file register ‘f’. ‘d’ = 1 is useful as a test of a file register, since status flag Z is affected. MOVLW Move literal to W OPTION Load OPTION Register Syntax: [ label ] MOVLW k Syntax: [ label ] OPTION Operands: 0  k  255 Operands: None Operation: k  (W) Operation: (W)  Option Status Affected: None Status Affected: None Description: The content of the W register is Description: The 8-bit literal ‘k’ is loaded into loaded into the OPTION register. the W register. The “don’t cares” will assembled as ‘0’s. DS40001239F-page 50  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 RETLW Return with literal in W SLEEP Enter SLEEP Mode Syntax: [ label ] RETLW k Syntax: [ label ] SLEEP Operands: 0  k  255 Operands: None Operation: k  (W); Operation: 00h  WDT; TOS  PC 0  WDT prescaler; Status Affected: None 1  TO; 0  PD Description: The W register is loaded with the 8-bit literal ‘k’. The program Status Affected: TO, PD, RBWUF counter is loaded from the top of Description: Time-out Status bit (TO) is set. The the stack (the return address). This Power-down Status bit (PD) is is a 2-cycle instruction. cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See Section9.9 “Power-down Mode (Sleep)” for more details. RLF Rotate Left f through Carry SUBWF Subtract W from f Syntax: [ label ] RLF f,d Syntax: [ label ] SUBWF f,d Operands: 0  f  31 Operands: 0 f 31 d  [0,1] d  [0,1] Operation: See description below Operation: (f) – (W) dest) Status Affected: C Status Affected: C, DC, Z Description: The contents of register ‘f’ are Description: Subtract (2’s complement method) rotated one bit to the left through the W register from register ‘f’. If ‘d’ the Carry flag. If ‘d’ is ‘0’, the result is ‘0’, the result is stored in the W is placed in the W register. If ‘d’ is register. If ‘d’ is ‘1’, the result is ‘1’, the result is stored back in stored back in register ‘f’. register ‘f’. C register ‘f’ RRF Rotate Right f through Carry SWAPF Swap Nibbles in f Syntax: [ label ] RRF f,d Syntax: [ label ] SWAPF f,d Operands: 0  f  31 Operands: 0  f  31 d  [0,1] d  [0,1] Operation: See description below Operation: (f<3:0>)  (dest<7:4>); (f<7:4>)  (dest<3:0>) Status Affected: C Status Affected: None Description: The contents of register ‘f’ are rotated one bit to the right through Description: The upper and lower nibbles of the Carry flag. If ‘d’ is ‘0’, the result register ‘f’ are exchanged. If ‘d’ is is placed in the W register. If ‘d’ is ‘0’, the result is placed in W ‘1’, the result is placed back in register. If ‘d’ is ‘1’, the result is register ‘f’. placed in register ‘f’. C register ‘f’  2004-2014 Microchip Technology Inc. DS40001239F-page 51

PIC10F200/202/204/206 TRIS Load TRIS Register XORWF Exclusive OR W with f Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d Operands: f = 6 Operands: 0  f  31 Operation: (W)  TRIS register f d  [0,1] Status Affected: None Operation: (W) .XOR. (f) dest) Description: TRIS register ‘f’ (f = 6 or 7) is Status Affected: Z loaded with the contents of the W Description: Exclusive OR the contents of the register W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is XORLW Exclusive OR literal with W stored back in register ‘f’. Syntax: [ label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the 8-bit literal ‘k’. The result is placed in the W register. DS40001239F-page 52  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 11.0 DEVELOPMENT SUPPORT 11.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2004-2014 Microchip Technology Inc. DS40001239F-page 53

PIC10F200/202/204/206 11.2 MPLAB XC Compilers 11.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other related modules together relocatable object files and archives to create an • Flexible creation of libraries with easy module executable file. MPLAB XC Compiler uses the listing, replacement, deletion and extraction assembler to produce its object file. Notable features of the assembler include: 11.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 11.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001239F-page 54  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 11.6 MPLAB X SIM Software Simulator 11.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by The MPLAB ICD 3 In-Circuit Debugger System is simulating the PIC MCUs and dsPIC DSCs on an Microchip’s most cost-effective, high-speed hardware instruction level. On any given instruction, the data debugger/programmer for Microchip Flash DSC and areas can be examined or modified and stimuli can be MCU devices. It debugs and programs PIC Flash applied from a comprehensive stimulus controller. microcontrollers and dsPIC DSCs with the powerful, Registers can be logged to files for further run-time yet easy-to-use graphical user interface of the MPLAB analysis. The trace buffer and logic analyzer display IDE. extend the power of the simulator to record and track The MPLAB ICD 3 In-Circuit Debugger probe is program execution, actions on I/O, most peripherals connected to the design engineer’s PC using a high- and internal registers. speed USB 2.0 interface and is connected to the target The MPLAB X SIM Software Simulator fully supports with a connector compatible with the MPLAB ICD 2 or symbolic debugging using the MPLAB XCCompilers, MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 and the MPASM and MPLAB Assemblers. The supports all MPLAB ICD 2 headers. software simulator offers the flexibility to develop and debug code outside of the hardware laboratory 11.9 PICkit 3 In-Circuit Debugger/ environment, making it an excellent, economical Programmer software development tool. The MPLAB PICkit 3 allows debugging and 11.7 MPLAB REAL ICE In-Circuit programming of PIC and dsPIC Flash microcontrollers Emulator System at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The The MPLAB REAL ICE In-Circuit Emulator System is MPLAB PICkit 3 is connected to the design engineer’s Microchip’s next generation high-speed emulator for PC using a full-speed USB interface and can be Microchip Flash DSC and MCU devices. It debugs and connected to the target via a Microchip debug (RJ-11) programs all 8, 16 and 32-bit MCU, and DSC devices connector (compatible with MPLAB ICD 3 and MPLAB with the easy-to-use, powerful graphical user interface of REAL ICE). The connector uses two device I/O pins the MPLAB X IDE. and the Reset line to implement in-circuit debugging The emulator is connected to the design engineer’s and In-Circuit Serial Programming™ (ICSP™). PC using a high-speed USB 2.0 interface and is connected to the target with either a connector 11.10 MPLAB PM3 Device Programmer compatible with in-circuit debugger systems (RJ-11) The MPLAB PM3 Device Programmer is a universal, or with the new high-speed, noise tolerant, Low- CE compliant device programmer with programmable Voltage Differential Signal (LVDS) interconnection (CAT5). voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display The emulator is field upgradable through future firmware (128 x 64) for menus and error messages, and a downloads in MPLAB X IDE. MPLAB REAL ICE offers modular, detachable socket assembly to support significant advantages over competitive emulators various package types. The ICSP cable assembly is including full-speed emulation, run-time variable included as a standard item. In Stand-Alone mode, the watches, trace analysis, complex breakpoints, logic MPLAB PM3 Device Programmer can read, verify and probes, a ruggedized probe interface and long (up to program PIC devices without a PC connection. It can three meters) interconnection cables. also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2004-2014 Microchip Technology Inc. DS40001239F-page 55

PIC10F200/202/204/206 11.11 Demonstration/Development 11.12 Third-Party Development Tools Boards, Evaluation Kits, and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide and Trace Systems application firmware and source code for examination • Protocol Analyzers from companies, such as and modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001239F-page 56  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 12.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40°C to +125°C Storage temperature............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS...............................................................................................................0 to +6.5V Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V Voltage on all other pins with respect to VSS...............................................................................-0.3V to (VDD + 0.3V) Total power dissipation(1)..................................................................................................................................800mW Max. current out of VSS pin..................................................................................................................................80mA Max. current into VDD pin.....................................................................................................................................80mA Input clamp current, IIK (VI < 0 or VI > VDD)20mA Output clamp current, IOK (VO < 0 or VO > VDD)20mA Max. output current sunk by any I/O pin..............................................................................................................25mA Max. output current sourced by any I/O pin.........................................................................................................25mA Max. output current sourced by I/O port ..............................................................................................................75mA Max. output current sunk by I/O port ...................................................................................................................75mA Note1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2004-2014 Microchip Technology Inc. DS40001239F-page 57

PIC10F200/202/204/206 FIGURE 12-1: PIC10F200/202/204/206 VOLTAGE-FREQUENCY GRAPH, -40C  TA  +125C 6.0 5.5 5.0 4.5 VDD (Volts) 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) DS40001239F-page 58  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 12.1 DC Characteristics: PIC10F200/202/204/206 (Industrial) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature -40°C  TA  +85°C (industrial) Param. Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure12-1 D002 VDR RAM Data Retention Voltage(2) 1.5* — — V Device in Sleep mode D003 VPOR VDD Start Voltage — Vss — V to ensure Power-on Reset D004 SVDD VDD Rise Rate 0.05* — — V/ms to ensure Power-on Reset IDD Supply Current(3) D010 — 175 275 A VDD = 2.0V — 0.63 1.1 mA VDD = 5.0V IPD Power-down Current(4) D020 — 0.1 1.2 A VDD = 2.0V — 0.35 2.4 A VDD = 5.0V IWDT WDT Current(5) D022 — 1.0 3 A VDD = 2.0V — 7 16 A VDD = 5.0V ICMP Comparator Current(5) D023 — 12 23 A VDD = 2.0V — 44 80 A VDD = 5.0V IVREF Internal Reference Current(5,6) D024 — 85 115 A VDD = 2.0V 175 195 A VDD = 5.0V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ.”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. 4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS. 5: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. 6: Measured with the comparator enabled.  2004-2014 Microchip Technology Inc. DS40001239F-page 59

PIC10F200/202/204/206 12.2 DC Characteristics: PIC10F200/202/204/206 (Extended) Standard Operating Conditions (unless otherwise specified) DC CHARACTERISTICS Operating Temperature -40°C  TA  +125°C (extended) Param. Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. D001 VDD Supply Voltage 2.0 5.5 V See Figure12-1 D002 VDR RAM Data Retention 1.5* — V Device in Sleep mode Voltage(2) D003 VPOR VDD Start Voltage — Vss — V to ensure Power-on Reset D004 SVDD VDD Rise Rate 0.05* — — V/ms to ensure Power-on Reset IDD Supply Current(3) D010 — 175 275 A VDD = 2.0V — 0.63 1.1 mA VDD = 5.0V IPD Power-down Current(4) D020 — 0.1 9 A VDD = 2.0V — 0.35 15 A VDD = 5.0V IWDT WDT Current(5) D022 — 1.0 18 A VDD = 2.0V — 7 22 A VDD = 5.0V ICMP Comparator Current(5) D023 — 12 27 A VDD = 2.0V — 42 85 A VDD = 5.0V VREF Internal Reference Current(5,6) D024 — 85 120 A VDD = 2.0V 175 200 A VDD = 5.0V * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ.”) column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. 4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS. 5: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. 6: Measured with the Comparator enabled. DS40001239F-page 60  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 12.3 DC Characteristics: PIC10F200/202/204/206 (Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating temperature -40°C  TA  +85°C (industrial) DC CHARACTERISTICS -40°C  TA  +125°C (extended) Operating voltage VDD range as described in DC specification Param. Sym. Characteristic Min. Typ.† Max. Units Conditions No. VIL Input Low Voltage I/O ports: D030 with TTL buffer Vss — 0.8 V For all 4.5V  VDD 5.5V D030A Vss — 0.15 V VDD D031 with Schmitt Trigger Vss — 0.2 VDD V buffer D032 MCLR, T0CKI Vss — 0.2 VDD V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V  VDD 5.5V D040A 0.25 VDD + 0.8 — VDD V Otherwise D041 with Schmitt Trigger 0.8VDD — VDD V For entire VDD range buffer D042 MCLR, T0CKI 0.8VDD — VDD V D070 IPUR GPIO weak pull-up 50 250 400 A VDD = 5V, VPIN = VSS current(3) IIL Input Leakage Current(1, 2) D060 I/O ports — ±0.1 ± 1 A Vss VPIN VDD, Pin at high-impedance D061 GP3/MCLR(3) — ±0.7 ± 5 A Vss VPIN VDD Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40C to +125C Output High Voltage D090 I/O ports(2) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D090A VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V, -40C to +125C Capacitive Loading Specs on Output Pins D101 All I/O pins — — 50* pF † Data in “Typ.” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. * These parameters are for design guidance only and are not tested. Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as coming out of the pin. 3: This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic.  2004-2014 Microchip Technology Inc. DS40001239F-page 61

PIC10F200/202/204/206 TABLE 12-1: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. Sym. Characteristics Min. Typ.† Max. Units Comments No. D300 VOS Input Offset Voltage —  5.0  10 mV (VDD - 1.5)/2 D301 VCM Input Common Mode Voltage 0 — VDD–1.5* V D302 CMRR Common Mode Rejection Ratio 55* — — dB D303* TRT Response Time Falling — 150 600 ns (Note 1) Rising — 200 1000 ns D304* TMC2COV Comparator Mode Change to — — 10* s Output Valid D305 VIVRF Internal Reference Voltage 0.55 0.6 0.65 V 2.0V  VDD  5.5V -40°C  TA  ±125°C (extended) * These parameters are characterized but not tested. † Data in ‘Typ.’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD-1.5)/2-100mV to (VDD-1.5)/2+20mV. TABLE 12-2: PULL-UP RESISTOR RANGES VDD (Volts) Temperature (C) Min. Typ. Max. Units GP0/GP1 2.0 -40 73K 105K 186K  25 73K 113K 187K  85 82K 123K 190K  125 86K 132k 190K  5.5 -40 15K 21K 33K  25 15K 22K 34K  85 19K 26k 35K  125 23K 29K 35K  GP3 2.0 -40 63K 81K 96K  25 77K 93K 116K  85 82K 96k 116K  125 86K 100K 119K  5.5 -40 16K 20k 22K  25 16K 21K 23K  85 24K 25k 28K  125 26K 27K 29K  DS40001239F-page 62  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 12.4 Timing Parameter Symbology and Load Conditions – PIC10F200/202/204/206 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp 2 to mc MCLR ck CLKOUT osc Oscillator cy Cycle time t0 T0CKI drt Device Reset Timer wdt Watchdog Timer io I/O port wdt Watchdog Timer Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (high-impedance) V Valid L Low Z High-impedance FIGURE 12-2: LOAD CONDITIONS – PIC10F200/202/204/206 pin CL Legend: CL = 50 pF for all pins VSS  2004-2014 Microchip Technology Inc. DS40001239F-page 63

PIC10F200/202/204/206 TABLE 12-3: CALIBRATED INTERNAL RC FREQUENCIES – PIC10F200/202/204/206 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial), -40C  TA  +125C (extended) AC CHARACTERISTICS Operating Voltage VDD range is described in Section12.1 “DC Characteristics: PIC10F200/202/204/206 (Industrial)” Param. Freq. Sym. Characteristic Min. Typ.† Max. Units Conditions No. Tolerance F10 FOSC Internal Calibrated 1% 3.96 4.00 4.04 MHz VDD=3.5V @ 25C INTOSC Frequency(1,2) 2% 3.92 4.00 4.08 MHz 2.5V VDD  5.5V 0C  TA  +85C (industrial) 5% 3.80 4.00 4.20 MHz 2.0V VDD  5.5V -40C  TA  +85C (industrial) -40C  TA  +125C (extended) * These parameters are characterized but not tested. † Data in the Typical (“Typ.”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1F and 0.01F values in parallel are recommended. 2: Under stable VDD conditions. FIGURE 12-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING – PIC10F200/202/204/206 VDD MCLR 30 Internal POR 32 32 32 DRT Timeout(2) Internal Reset Watchdog Timer Reset 31 34 34 I/O pin(1) Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. 2: Runs on POR only. DS40001239F-page 64  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 TABLE 12-4: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC10F200/202/204/206 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section12.1 “DC Characteristics: PIC10F200/202/204/206 (Industrial)” Param. Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. 30 TMCL MCLR Pulse Width (low) 2* — — s VDD = 5V, -40°C to +85°C 5* — — s VDD = 5.0V 31 TWDT Watchdog Timer Time-out 10 16 29 ms VDD = 5.0V (industrial) Period (no prescaler) 10 16 31 ms VDD = 5.0V (extended) 32 TDRT Device Reset Timer Period 10 16 29 ms VDD = 5.0V (industrial) (standard) 10 16 31 ms VDD = 5.0V (extended) 34 TIOZ I/O High-impedance from MCLR — — 2* s low * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ.”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 12-4: TIMER0 CLOCK TIMINGS – PIC10F200/202/204/206 T0CKI 40 41 42 TABLE 12-5: TIMER0 CLOCK REQUIREMENTS – PIC10F200/202/204/206 Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C  TA  +85C (industrial) AC CHARACTERISTICS -40C  TA  +125C (extended) Operating Voltage VDD range is described in Section12.1 “DC Characteristics: PIC10F200/202/204/206 (Industrial)”. Param. Sym. Characteristic Min. Typ.(1) Max. Units Conditions No. 40 Tt0H T0CKI High Pulse No Prescaler 0.5 TCY + 20* — — ns Width With Prescaler 10* — — ns 41 Tt0L T0CKI Low Pulse No Prescaler 0.5 TCY + 20* — — ns Width With Prescaler 10* — — ns 42 Tt0P T0CKI Period T +40 — — ns Whichever is greater. 20 or ----C----Y------------------ N = Prescale Value N (1, 2, 4,..., 256) * These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ.”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2004-2014 Microchip Technology Inc. DS40001239F-page 65

PIC10F200/202/204/206 TABLE 12-6: THERMAL CONSIDERATIONS Standard Operating Conditions (unless otherwise specified) Param. Sym. Characteristic Typ. Units Conditions No. TH01 JA Thermal Resistance Junction to 60 C/W 6-pin SOT-23 package Ambient 80 C/W 8-pin PDIP package 90 C/W 8-pin DFN package TH02 JC Thermal Resistance Junction to 31.4 C/W 6-pin SOT-23 package Case 24 C/W 8-pin PDIP package 24 C/W 8-pin DFN package TH03 TJMAX Maximum Junction Temperature 150 C TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature; TJ = Junction Temperature. DS40001239F-page 66  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean+3) or (mean-3) respectively, where  is a standard deviation, over each temperature range. FIGURE 13-1: IDD vs. VDD OVER FOSC XT Mode 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-Case Temp) + 3 Maximum (-40°C to 125°C) 1,000 4 MHz 800 A) Typical  (D ID 600 4 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2004-2014 Microchip Technology Inc. DS40001239F-page 67

PIC10F200/202/204/206 FIGURE 13-2: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.35 0.30 A) 0.25  (D P 0.20 I 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-3: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 Typical: Statistical Mean @25°C 16.0 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 14.0 Max. 125°C 12.0 A) 10.0  (D P 8.0 I 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001239F-page 68  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 FIGURE 13-4: COMPARATOR IPD vs. VDD (COMPARATOR ENABLED) 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 Maximum (-40°C to 125°C) 60 Typical A)  (PD 40 I 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-5: TYPICAL WDT IPD vs. VDD 9 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 7 (-40°C to 125°C) 6 A) 5  (PD 4 I 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2004-2014 Microchip Technology Inc. DS40001239F-page 69

PIC10F200/202/204/206 FIGURE 13-6: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 20.0 Max. 125°C 15.0 A)  (D P I 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-7: WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER) 50 Typical: Statistical Mean @25°C 45 Max. 125°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 40 Max. 85°C 35 30 ms) Typical. 25°C e ( 25 m Ti 20 Min. -40°C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001239F-page 70  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 FIGURE 13-8: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 0.6 0.5 Max. 85°C V) (L 0.4 O V 0.3 Typical 25°C 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 13-9: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C 0.40 MaximTuympi:c aMl:e Santa (tiWstoicraslt -MCeaasne @Te2m5p×)C + 3 Maximum: Mea s( -+4 03×C to 125×C) (-40°C to 125°C) Max. 125°C 0.35 Max. 85°C 0.30 0.25 V) (L Typ. 25°C O V 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA)  2004-2014 Microchip Technology Inc. DS40001239F-page 71

PIC10F200/202/204/206 FIGURE 13-10: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C 2.0 V) (H O V 1.5 Typical: Statistical Mean @25°C 1.0 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 13-11: VOH vs. IOH OVER TE(MPERAT, URE (VDD = 5).0V) 5.5 5.0 Max. -40°C Typ. 25°C 4.5 V) Min. 125°C (H O V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) DS40001239F-page 72  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 FIGURE 13-12: TTL INPUT THRESHOLD VIN vs. VDD (TTL Input, -40×C TO 125×C) 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C 1.3 Typ. 25°C V) (N 1.1 VI Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 13-13: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) VIH Min. -40°C 3.0 2.5 V) (N VI 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)  2004-2014 Microchip Technology Inc. DS40001239F-page 73

PIC10F200/202/204/206 FIGURE 13-14: INTOSC (INTERNAL OSCILLATOR) POWER-UP TIMES vs. VDD Maximum (Sleep Mode all Peripherals Disabled) 45 40 s) 35 m me ( 30 Max. 125°C Ti p u 25 r- e w Max. 85°C Po 20 15 Typical 25°C Max. -40°C 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001239F-page 74  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 6-Lead SOT-23 Example XXNN 0217 8-Lead PDIP (300 mil) Example XXXXXXXX PIC10F200 XXXXXNNN I/P e 3 017 YYWW 1433 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2004-2014 Microchip Technology Inc. DS40001239F-page 75

PIC10F200/202/204/206 Package Marking Information (Continued) 8-Lead DFN (2x3x0.9 mm) Example BE0 433 17 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. * Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS40001239F-page 76  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 TABLE 14-1: 8-LEAD 2x3 DFN (MC) TABLE 14-2: 6-LEAD SOT-23 (OT) PACKAGE TOP MARKING PACKAGE TOP MARKING Part Number Marking Part Number Marking PIC10F200-I/MC BA0 PIC10F200-I/OT 00NN PIC10F200-E/MC BB0 PIC10F200-E/OT 00NN PIC10F202-I/MC BC0 PIC10F202-I/OT 02NN PIC10F202-E/MC BD0 PIC10F202-E/OT 02NN PIC10F204-I/MC BE0 PIC10F204-I/OT 04NN PIC10F204-E/MC BF0 PIC10F204-E/OT 04NN PIC10F206-I/MC BG0 PIC10F206-I/OT 06NN PIC10F206-E/MC BH0 PIC10F206-E/OT 06NN Note: NN represents the alphanumeric traceability code.  2004-2014 Microchip Technology Inc. DS40001239F-page 77

PIC10F200/202/204/206 14.2 Package Details The following sections give the technical details of the packages. (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:21)(cid:6)(cid:19)(cid:11)(cid:13)(cid:11)(cid:12)(cid:22)(cid:21)(cid:8)(cid:23)(cid:17)(cid:20)(cid:24)(cid:8)(cid:25)(cid:15)(cid:17)(cid:20)(cid:3)(cid:26)(cid:27)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) b N 4 E E1 PIN1IDBY LASERMARK 1 2 3 e e1 D A A2 c φ L A1 L1 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 9 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)(cid:24)((cid:2))(cid:22)* 6$# (cid:7)!(cid:14)(cid:2)4(cid:14)(cid:28)!(cid:2)1(cid:7)#(cid:8)(cid:11) (cid:14)(cid:30) (cid:30)(cid:20)(cid:24)(cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20)(cid:24)(cid:4) ; (cid:30)(cid:20)(cid:23)( (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:3) (cid:4)(cid:20)<(cid:24) ; (cid:30)(cid:20)(cid:29)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%% (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) ; (cid:4)(cid:20)(cid:30)( 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:3)(cid:20)(cid:3)(cid:4) ; (cid:29)(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)!(cid:14)!(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)!#(cid:11) "(cid:30) (cid:30)(cid:20)(cid:29)(cid:4) ; (cid:30)(cid:20)<(cid:4) 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:3)(cid:20)(cid:5)(cid:4) ; (cid:29)(cid:20)(cid:30)(cid:4) .(cid:10)(cid:10)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:30)(cid:4) ; (cid:4)(cid:20)9(cid:4) .(cid:10)(cid:10)#(cid:12)(cid:9)(cid:7)(cid:15)# 4(cid:30) (cid:4)(cid:20)(cid:29)( ; (cid:4)(cid:20)<(cid:4) .(cid:10)(cid:10)#(cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)> ; (cid:29)(cid:4)> 4(cid:14)(cid:28)!(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:8) (cid:4)(cid:20)(cid:4)< ; (cid:4)(cid:20)(cid:3)9 4(cid:14)(cid:28)!(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:3)(cid:4) ; (cid:4)(cid:20)((cid:30) (cid:29)(cid:22)(cid:12)(cid:5)(cid:11)(cid:30) (cid:30)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15) (cid:2)(cid:21)(cid:2)(cid:28)(cid:15)!(cid:2)"(cid:30)(cid:2)!(cid:10)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:7)(cid:15)(cid:8)(cid:16)$!(cid:14)(cid:2)(cid:31)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:20)(cid:2)(cid:6)(cid:10)(cid:16)!(cid:2)%(cid:16)(cid:28) (cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10)#(cid:9)$ (cid:7)(cid:10)(cid:15) (cid:2) (cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10)#(cid:2)(cid:14)&(cid:8)(cid:14)(cid:14)!(cid:2)(cid:4)(cid:20)(cid:30)(cid:3)(cid:5)(cid:2)(cid:31)(cid:31)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2) (cid:7)!(cid:14)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:4)(cid:3)<) DS40001239F-page 78  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2004-2014 Microchip Technology Inc. DS40001239F-page 79

PIC10F200/202/204/206 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 DS40001239F-page 80  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e e 2 2 e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A - - .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 - - Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB - - .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2  2004-2014 Microchip Technology Inc. DS40001239F-page 81

PIC10F200/202/204/206 (cid:31)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8) (cid:18)(cid:6)(cid:10)(cid:8)!(cid:10)(cid:6)(cid:12)"(cid:8)(cid:29)(cid:22)(cid:8)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:6)(cid:14)#(cid:6)$(cid:5)(cid:8)(cid:23)%&(cid:24)(cid:8)’(cid:8)(cid:26)((cid:27)()*+(cid:8)(cid:16)(cid:16)(cid:8),(cid:22)(cid:7)-(cid:8)(cid:25) !(cid:29)(cid:28) (cid:29)(cid:22)(cid:12)(cid:5)(cid:30) .(cid:10)(cid:9)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:31)(cid:10) #(cid:2)(cid:8)$(cid:9)(cid:9)(cid:14)(cid:15)#(cid:2)(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)!(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17) 0(cid:2)(cid:12)(cid:16)(cid:14)(cid:28) (cid:14)(cid:2) (cid:14)(cid:14)(cid:2)#(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7)%(cid:7)(cid:8)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)#(cid:14)!(cid:2)(cid:28)#(cid:2) (cid:11)##(cid:12)+22---(cid:20)(cid:31)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)(cid:31)2(cid:12)(cid:28)(cid:8)/(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D e b N N L K E E2 EXPOSEDPAD NOTE1 NOTE1 1 2 2 1 D2 TOPVIEW BOTTOMVIEW A NOTE2 A3 A1 3(cid:15)(cid:7)# (cid:6)(cid:19)44(cid:19)(cid:6)"(cid:13)"(cid:26)(cid:22) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:2)4(cid:7)(cid:31)(cid:7)# (cid:6)(cid:19)5 56(cid:6) (cid:6)(cid:25)7 5$(cid:31)8(cid:14)(cid:9)(cid:2)(cid:10)%(cid:2)1(cid:7)(cid:15) 5 < 1(cid:7)#(cid:8)(cid:11) (cid:14) (cid:4)(cid:20)((cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2):(cid:14)(cid:7)(cid:17)(cid:11)# (cid:25) (cid:4)(cid:20)<(cid:4) (cid:4)(cid:20)(cid:24)(cid:4) (cid:30)(cid:20)(cid:4)(cid:4) (cid:22)#(cid:28)(cid:15)!(cid:10)%%(cid:2) (cid:25)(cid:30) (cid:4)(cid:20)(cid:4)(cid:4) (cid:4)(cid:20)(cid:4)(cid:3) (cid:4)(cid:20)(cid:4)( *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)/(cid:15)(cid:14) (cid:25)(cid:29) (cid:4)(cid:20)(cid:3)(cid:4)(cid:2)(cid:26)". 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21) (cid:3)(cid:20)(cid:4)(cid:4)(cid:2))(cid:22)* 6,(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)!#(cid:11) " (cid:29)(cid:20)(cid:4)(cid:4)(cid:2))(cid:22)* "&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)!(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) (cid:21)(cid:3) (cid:30)(cid:20)(cid:29)(cid:4) ; (cid:30)(cid:20)(( "&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)!(cid:2)=(cid:7)!#(cid:11) "(cid:3) (cid:30)(cid:20)((cid:4) ; (cid:30)(cid:20)(cid:5)( *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)=(cid:7)!#(cid:11) 8 (cid:4)(cid:20)(cid:3)(cid:4) (cid:4)(cid:20)(cid:3)( (cid:4)(cid:20)(cid:29)(cid:4) *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:2)4(cid:14)(cid:15)(cid:17)#(cid:11) 4 (cid:4)(cid:20)(cid:29)(cid:4) (cid:4)(cid:20)(cid:23)(cid:4) (cid:4)(cid:20)((cid:4) *(cid:10)(cid:15)#(cid:28)(cid:8)#(cid:27)#(cid:10)(cid:27)"&(cid:12)(cid:10) (cid:14)!(cid:2)1(cid:28)! ? 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(cid:20) (cid:29)(cid:20) 1(cid:28)(cid:8)/(cid:28)(cid:17)(cid:14)(cid:2)(cid:7) (cid:2) (cid:28)-(cid:2) (cid:7)(cid:15)(cid:17)$(cid:16)(cid:28)#(cid:14)!(cid:20) (cid:23)(cid:20) (cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)!(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)"(cid:2)’(cid:30)(cid:23)(cid:20)((cid:6)(cid:20) )(cid:22)*+ )(cid:28) (cid:7)(cid:8)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14)#(cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14)&(cid:28)(cid:8)#(cid:2),(cid:28)(cid:16)$(cid:14)(cid:2) (cid:11)(cid:10)-(cid:15)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14) (cid:20) (cid:26)".+ (cid:26)(cid:14)%(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)(cid:31)(cid:14)(cid:15) (cid:7)(cid:10)(cid:15)0(cid:2)$ $(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)-(cid:7)#(cid:11)(cid:10)$#(cid:2)#(cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)0(cid:2)%(cid:10)(cid:9)(cid:2)(cid:7)(cid:15)%(cid:10)(cid:9)(cid:31)(cid:28)#(cid:7)(cid:10)(cid:15)(cid:2)(cid:12)$(cid:9)(cid:12)(cid:10) (cid:14) (cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)-(cid:7)(cid:15)(cid:17)*(cid:4)(cid:23)(cid:27)(cid:30)(cid:3)(cid:29)* DS40001239F-page 82  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2004-2014 Microchip Technology Inc. DS40001239F-page 83

PIC10F200/202/204/206 APPENDIX A: REVISION HISTORY Revision C (August 2006) Added 8-Pin DFN Pin Diagram; Revised Table 1-1; Reformatted all Registers; Revised Section 4.8 and added note; Section 5.3 (changed Figure reference to Figure 5-1); Tables 6-1 and 7-1 (removed shading from TRISGPIO (I/O Control Register); Sections 8.1-8.4 (changed Table reference to Table 12-2); Section 14.1 Revised and replaced Package Marking Information and drawings, Added Tables 14-1 & 14-2, Added DFN Package drawing. Revision D (April 2007) Revised section 12.1, 12.2, 12.3, Table 1-1, 12-1, 12-3, 12-4. Added Section 13.0. Replaced Package Drawings (Rev. AP); Removed instances of PICmicro® and replaced it with PIC®. Revision E (October 2013) Revised Figure 8-1 (deleted OSCCAL); Revised Packaging Legend. Revision F (September 2014) Added Table 12-6 (Thermal Considerations); Updated Register 4-1, Register 9-1 and Chapter 14 (Packaging Information); Other minor corrections. DS40001239F-page 84  2004-2014 Microchip Technology Inc.

PIC10F200/202/204/206 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2004-2014 Microchip Technology Inc. DS40001239F-page 85

PIC10F200/202/204/206 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) - X /XX XXX Examples: Device Tape and Reel Temperature Package Pattern a) PIC10F202T - E/OT Option Range Tape and Reel Extended temperature SOT-23 package (Pb-free) b) PIC10F200 - I/P Device: PIC10F200 Industrial temperature, PIC10F202 PDIP package (Pb-free) PIC10F204 c) PIC10F204 - I/MC PIC10F206 Industrial temperature PIC10F200T (Tape & Reel) DFN package (Pb-free) PIC10F202T (Tape & Reel) PIC10F204T (Tape & Reel) PIC10F206T (Tape & Reel) Tape and Reel Blank = Standard packaging (tube or tray) Option: T = Tape and Reel(1) Temperature I = -40C to +85C (Industrial) Range: E = -40C to +125C (Extended) Note1: Tape and Reel identifier only appears in the catalog part number description. This Package: P = 300 mil PDIP (Pb-free) identifier is used for ordering purposes and is OT = SOT-23, 6-LD (Pb-free) not printed on the device package. Check MC = DFN, 8-LD 2x3 (Pb-free) with your Microchip Sales Office for package availability with the Tape and Reel option. Pattern: QTP, SQTP, Code or Special Requirements (blank otherwise) DS40001239F-page 86  2004-2014 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2004-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-597-0 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2004-2014 Microchip Technology Inc. DS40001239F-page 87

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC10F206-E/P PIC10F202-I/P PIC10F204T-I/OT PIC10F200T-I/OT PIC10F206T-I/OT PIC10F202T-I/OT PIC10F202-E/P PIC10F204-I/P PIC10F204-E/P PIC10F206-I/P PIC10F200T-E/OT PIC10F202T-E/OT PIC10F206T- E/OT PIC10F204T-E/OT PIC10F200-I/P PIC10F200-E/P PIC10F200-I/MC PIC10F200T-I/MC PIC10F202-I/MC PIC10F202T-I/MC PIC10F204-I/MC PIC10F204T-I/MC PIC10F206-I/MC PIC10F206T-I/MC PIC10F206-E/MC PIC10F202-E/MC PIC10F204-E/MC PIC10F200-E/MC