 PI2007 Cool-ORing® Series Universal High Side Active ORing Controller IC Description Features ® The PI2007 Cool-ORing solution is a universal  Fast dynamic response to power source failure, high-speed Active ORing controller IC designed for with 80ns reverse current turn off delay time. use with N-channel MOSFETs in redundant power  4A gate discharge current system architectures. The PI2007 Cool-ORing  Forward Over Current Fault indication controller enables an extremely low power loss  Accurate MOSFET drain-to-source voltage solution with fast dynamic response to fault sensing conditions, critical for high availability systems. The  Internal charge pump PI2007 controls single or parallel MOSFETs to  FET check at initial power-up address Active ORing applications protecting  100V for 100ms, operation in high side against power source failures. The PI2007 has an application internal charge pump enabling an ideal solution in  VC under voltage fault detection 12V or 36-75V bus high-side Active ORing applications. Applications The gate drive output turns the MOSFET on in  N+1 Redundant Power Systems normal steady state operation, while achieving high-  Servers & High End Computing speed turn-off during input power source fault  Telecom Systems conditions, that causes reverse current flow. The  High-side Active ORing controller auto-resets once the fault clears. The  High current Active ORing MOSFET drain-to-source voltage is monitored to detect reverse current flow. The PI2007 has an internal charge pump to drive the gate of a high side Package Information N-Channel MOSFET above the VC input. There is The PI2007 is offered in the following packages: an internal shunt regulator at the VC input for high  10 Lead 3mm x 3mm DFN package voltage applications. Typical Applications: Figure 1: PI2007 High Side Active ORing for 12V Figure 2: PI2007 referenced to Vin in high voltage Bus applications high side Active ORing applications Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 1 of 19

 Pin Description Pin Name Pin Description Number Gate Turn Off Switch Return: This pin is the high current return path for the gate driver PGND 1 during turn off. Connect this pin to the low side of the VC coupling capacitor and SGND. Gate Drive Output: This pin drives the gate of the external N-channel MOSFET. Under normal operating conditions and when V > 6mV, the GATE pin pulls high to SP-SN GATE 2 approximately 2*VC with respect to the SGND pin. The controller turns the gate off during a reverse current fault that is below the reverse voltage threshold (-6mV) and when VC is in Under Voltage (7.15V). Controller Input Supply: This pin is the supply pin for the control circuitry and gate driver. Connect a 1μF capacitor between the VC pin and the SGND pin. Voltage on this VC 3 pin is regulated to 11.7V with respect to SGND by an internal shunt regulator. For high voltage supply applications connect a shunt resistor between the SGND and PGND pins and the supply return, as shown in Figure 2. VC Return: This pin is the return (ground) for the control circuitry. Connect this pin to SGND 4 the low side of VC decoupling capacitor. Controller Input Supply With Limiting Resistor: This pin is connected internally to VC VR 5 through a 420Ω resistor needed for Bus voltages greater than 10V and less than 14V. Leave this pin open if unused. Positive Sense Input: Connect SP pin to the Source pin of the external N-channel SP 6 MOSFETs. The polarity of the voltage difference between SP and SN provides an indication of current flow direction through the MOSFET. NC 7, 10 Not Connected: Leave pins floating. Negative Sense Input: Connect SN to the Drain pin of the external N-channel MOSFET. SN 8 The polarity of the voltage difference between SP and SN provides an indication of current flow direction through the MOSFET. Fault Status Output: This open collector pin pulls low to indicate one of the several potential fault conditions may exist. The FT pin will pull low after a reverse or forward fault has been detected with a defined delay time (8μs). In addition, the FT pin will pull FT 9 low when the controller input voltage is below the VC under-voltage threshold V < VC-SGND 7V. When V > 7.15V and 6mV < V < 275mV this pin clears (High). In high VC-SGND SP-SN voltage applications this output must be translated with reference to the system return with external circuitry, see Figure 19. Leave this pin open if unused. Package Pin-Outs 10 Lead DFN (3mm x 3mm) Top view Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 2 of 19

 Absolute Maximum Ratings Note: All voltage nodes are referenced to SGND VR -0.3V to 17.3V / 40mA SP, FT -0.3V to 17.3V / 10mA GATE -0.3V to 24V / 5A peak PGND -0.3V to 3V / 5A peak SGND, VC 40mA SN (Continuous, TA ≤ 85°C) -0.3V to 80V / 10mA SN (100ms Pulse, TA ≤ 85°C) 100V / 10mA Storage Temperature -65oC to 150oC Operating Junction Temperature -40oC to 140°C Soldering Temperature for 20 seconds 260oC ESD Rating 2kV HBM Electrical Specifications Unless otherwise specified: -40C < T < 125C, VC =10.5V, VR open, C = 1uF, C 1nF, J Vc GATE_PGND = SGND=PGND=0V Parameter Symbol Min Typ Max Units Conditions VC Supply Operating Supply Range (3) V 8.5 10.5 V No VC limiting Resistor VC-SGND Quiescent Current I 1.5 2.0 mA VC = 10.5V VC VC Clamp Voltage V 11 11.7 12.5 V I =3mA VC-CLM VC VC Clamp Shunt Resistance R 10  Delta I =10mA VC VC VC Under-Voltage Rising Threshold V 6.1 7.15 8.0 V VCUVR VC Under-Voltage Falling Threshold V 6 7.00 7.9 V VCUVF VC Under-Voltage Hysteresis V 100 150 200 mV VCUV-HS VR Supply (VR pin connected to Vin, VC pin to bypass capacitor Figure 1) Recommended for 12V Bus applications Operating Supply Range V 10 14 V Biased from VR pin VR-SGND Quiescent Current I 3.0 5.5 10 mA VR = 14V VR Bias Resistor R 300 420 550 Ω Bias DIFFERENTIAL AMPLIFIER AND COMPARATORS Common Mode Input Voltage V -3 3 V SP to VC, SN to VC CM Differential Operating Input Voltage(1) V -80 400 mV SP-SN SP-SN SP Input Bias Current I 35 55 75 μA SP=SN=VC SP SN Input Bias Current I 35 55 75 μA SP=SN=VC SN SN Leakage Current ISN_Lg 7 9 mA VSN = 80V,SP=VC=0V Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 3 of 19

 Electrical Specifications (Continued) Unless otherwise specified: -40C < T < 125C, VC =10.5V, VR open, C = 1uF, C 1nF, J Vc GATE_PGND = SGND=PGND=0V Parameter Symbol Min Typ Max Units Conditions DIFFERENTIAL AMPLIFIER AND COMPARATORS (Continued) Gate Enable Threshold V +1 +6 +11 mV V = 10.5V @ 25°C RVS-EN SN Reverse Comparator Threshold V -11 -6 -2 mV V = 10.5V @ 25°C RVS-TH SN Reverse Comparator Hysteresis V 10 12 14 mV V = 10.5V @ 25°C RVS-HY SN Reverse Fault to Gate Turn-off V = +50mV to -50mV t 80 150 ns SP-SN Response Time RVS step to 90% of V max G Forward Comparator Threshold V 250 275 300 mV V = 10.5V @ 25°C FWD-TH SN Forward Comparator Hysteresis V 15 25 35 mV V = 10.5V @ 25°C FWD-HY SN GATE DRIVER Gate Source Current I -20 -15 μA V =V –1V, I =3mA G-SC G G-Hi VC Pull Down Peak Current to PGND(1) I 1.5 4.0 A G-PGND Pull-down Gate Resistance to R 0.3  V = 1.5V @ 25C PGND(1) G-PGND G-PGND AC Gate Pull-down Voltage to V 0.2 V PGND(1) G-PGND DC Gate Pull-down Voltage V 0.8 1.2 V I =100mA, in reverse fault G-SGND G 7.0 8.0 11 V I =-20μA, I =3mA G VC Gate Drive Voltage to VC V G-Hi 8.0 9.0 11 V I =-2μA, I =3mA G VC Gate Fall Time t 10 25 ns 90% to 10% of V max. G-F G I =10μA, SP= SN=open 0.7 1 V G VC = 4.5V Gate Voltage V G-UVLO I =10μA, SP=0V; VC=0V 0.7 1 V G 5.5V ≤ SN ≤ 80V GATE DRIVER (VR pin connected to Vin, VC pin to bypass capacitor Figure 1) 4.5 7.0 9.5 V I =-20μA, 10V VR 14V G Gate Drive Voltage to VR V G-Hi 5.0 8.0 9.5 V I =-2μA, 10V VR 14V G Fault Status: FT Fault Output Low Voltage V 0.2 0.5 V I =1.5mA, VC > 4.5V FT FT Fault Output High Source Current I -1 μA V =14V, V > +6mV FT FT SP-SN V = ± 50mV step to Fault Delay time T 4 8 16 μs SP-SN FT-DLY 90% of V max GST Note 1: These parameters are not production tested but are guaranteed by design, characterization, and correlation with statistical process control. Note 2: Current sourced by a pin is reported with a negative sign. Note 3: Refer to the VC Bias section in the Application Information for details on the VC requirement to meet the MOSFET V requirement. GS Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 4 of 19

 Functional Description: There is a bias current path from SN to SP during the reverse fault condition. The bias current is The PI2007 Cool-ORing controller IC is designed to proportional to the voltage between SN and SP. drive single or parallel N-channel MOSFETs in high The maximum SN pin bias current is 9mA when side Active ORing applications. The PI2007 used V =80V and V =0V and assumes that the SN SP with an external MOSFET can function as an ideal MOSFET is in the off condition. Refer to Figure 15 ORing diode in the high side of a redundant power in the Application Information section for more system, significantly reducing power dissipation and details. eliminating the need for heatsinking. Forward Voltage Comparator: FWD An N-channel MOSFET in the conduction path offers extremely low on-resistance resulting in a dramatic The FWD comparator detects when a forward reduction of power dissipation versus the voltage condition exists and SP is above 275mV performance of a diode used in conventional ORing (typical) positive with respect to SN. When SP-SN is applications due to its high forward voltage drop. more than 275mV, the FWD comparator will assert This can allow for the elimination of complex heat the Gate Status low to report a fault condition. sinking and other thermal management VC and Internal Voltage Regulator: requirements. The PI2007 has a separate input VC that provides Due to the inherent characteristics of the MOSFET, power to the control circuitry, charge pump and gate current will flow in the forward and reverse directions driver. An internal regulator clamps the VC voltage while the gate remains above the gate threshold (V ) to 11.7V. VC-SGND voltage. Ideal ORing applications should not allow The internal regulator circuit has a comparator to reverse current flow, so the controller has to be monitor the VC voltage and pulls the GATE pin low capable of very fast and accurate detection of when the VC is lower than the VC Under-Voltage reverse current caused by input power source Threshold. failures, and very fast turn off of the gate of the MOSFET. Once the gate voltage falls below the gate In 12V Bus applications (10V to 14V) the VR input threshold, the MOSFET is off and the body diode will pin can be connected to the input voltage eliminating be reverse biased preventing reverse current flow the need for an external limiter. An internal 420Ω and subsequent excessive voltage droop on the resistor is connected between the VR pin and the redundant bus. internal regulator VC pin. Differential Amplifier: Charge Pump: The PI2007 integrates a high-speed low offset The PI2007 has an integrated charge pump that voltage differential amplifier to sense the difference approximately doubles the VC voltage with between the Sense Positive (SP) pin voltage and reference to the SGND pin, to drive the N-Channel Sense Negative (SN) pin voltage with high accuracy. MOSFET gate to a voltage higher than the input The amplifier output is connected to the Reverse voltage at 15µA minimum source current. and Forward comparators. Gate Driver: Reverse Current Comparator: RVS The gate driver (GATE) output is configured to drive The reverse current comparator provides the critical an external N-channel MOSFET. In the high state, function in the controller, detecting negative voltage the gate driver applies a 20µA typical current source caused by reverse current. When the SN pin is 6mV to the MOSFET gate from the integrated charge higher than the SP pin, the reverse comparator will pump. The Charge Pump voltage is limited to force the gate discharge circuit to turn off the 2*(V –V -1V). VC SGND MOSFETs in typically 80ns. When a reverse current fault is initiated, the gate The reverse comparator will hold the gate low until driver pulls the GATE pin low to the PGND pin and the SP pin is 6mV higher than the SN pin. The discharges the MOSFET gate with 4A typical peak reverse comparator hysteresis is shown in Figure 3. capability. Fault Indication: FT The FT pin is an open collector NPN that will be pulled low when the Gate pin is low. The FT pin is also pulled low when V is below UVLO or VC-SGND during the following fault conditions as indicated in Figure 3: Reverse comparator hysteresis: V - V SP SN the table below: Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 5 of 19

 Condition Indication of possible faults 1 Reverse: V - V ≤ -6mV Input supply shorted SP SN 2 Forward: V - V ≥ +275mV Open FET, Gate short or open, High current SP SN 3 Forward V - V ≤ +6mV Shorted FET on power-up SP SN Figure 4: PI2007 Controller Internal Block Diagram Figure 5: PI2007 State Diagram for gate drive. Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 6 of 19

 Figure 6: Timing diagram for two PI2007 controllers in a high side Active ORing application Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 7 of 19

 Typical Characteristics: Figure 7: Controller bias current vs. temperature Figure 10: VC UVLO threshold vs. temperature Figure 8: Reverse Fault to Gate Turn-off Response Figure 11: Reverse comparator threshold vs. Time vs. temperature. temperature. Figure 9: Gate drive voltage to VC vs. temperature. Figure 12: Gate source current vs. temperature Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 8 of 19

 Figure 13: PI2007 performance in response to a fault (input short), configured for a +48V application as shown in Figure 17. Application Information: The PI2007 is designed to replace ORing diodes in at the C termination to keep SGND noise free when VC high current redundant power architectures. the Gate is turned off in response to a fault. Replacing a traditional diode with a PI2007 controller In 12V system applications, where the input voltage IC and a low on-state resistance N-channel MOSFET (Vin) is between 10V and 14V, connect the VR pin to will result in significant power dissipation reduction as Vin and connect SGND and PGND to the Vin return. well as board space reduction, efficiency improvement A 420Ω internal resistor is connected between the VR and additional protection features. This section pin and the VC pin. describes in detail the procedure to follow when designing with the PI2007 Active ORing controller and In high voltage applications, above 14V, a bias N-Channel MOSFETs. Two different Active ORing resistor (R ) and low current low forward voltage PG design examples are presented. drop Schottky diode are required. Connect one terminal of R to the SGND and PGND and the other VC Bias: PG terminal to ground (Vin return). The Schottky diode The PI2007 has a separate input (VC) that provides anode will be connected to the SGND pin and its power to the control circuitry, the charge pump and cathode connected at the VC pin. See typical the gate driver. An internal regulator clamps the VC application drawings on page 1. voltage (V ) to 11.7V. A bypass ceramic VC-SGND capacitor (C = 1μF) has to be connected between Recommended Schottky: VC VC and SGND to hold V steady. Also, the Gate VC-SGND PMEG3005AEA: from NXP or equivalent turn off return (PGND) should be connected to SGND R selection for input voltage greater than 14V: PG Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 9 of 19

 Select the resistor (R ) value at the minimum input PG voltage to avoid a voltage drop that may reduce V VC- lower than VC under voltage lockout. SGND Select the value of R using the following equations: PG V V R  VCmin VCCLMMax PG I 0.1mA VC_Max R maximum power dissipation: PG (V V )2 PdR  VCmax VCCLMMin PG R PG Figure 14: Constant current bias circuit Where: Pulling the Q2 base (EN) to the system return (RTN) V : VC pin minimum applied voltage with will turn off the transistor and the controller returns VCmin (SGND pin and PGND pin) will float and eventually respect to Vin return the MOSFET will be turned off. An open collector V : VC pin maximum applied voltage with VCmax device can be used to enable and disable the PI2007. respect to Vin return The constant current circuit should guarantee current V : Controller maximum clamp voltage, 12.5V VCCLMMax greater than the PI2007 maximum Quiescent current V : Controller minimum clamp voltage, 11.0V (I ), 2.0mA. VCCLMMin VC I : Controller maximum bias current, use VC_Max RLIMIT can be calculated from the following equation: 2.0mA plus 0.1mA for margin V V (on) R  Z_MIN BE Example: 40V <V <50V LIMIT I VC VC_MAX V V 40V 12.5V Where: RPG  VICmin VC0.C1LmMMAax  2.1mA 13.1k VZ_MIN: Minimum Zener diode voltage VC_Max V (on): Q2 Base-Emitter On maximum voltage, for BE (V V )2 50V 11V2 default use V (on)=0.7V PdR  VCmax VCCLMMin  116mW BE PG RPG 13.1k I : PI2007 Quiescent Current, maximum VC_MAX I =2.0mA Alternative Bias Circuit with Device Enable: VC Constant current circuit Zener Diode Selection: In a wide operating input voltage range the size of R PG Select a Zener diode with a low reverse current may be become large to support power dissipation. A requirement to minimize R . Zener diodes with higher simple constant current circuit can be used instead of Z break down voltage will have lower reverse current R to reduce power dissipation and can be used as a PG and reduce Q2 collector current variation. Zener device enable. diodes with a breakdown voltage of 6V and higher will As shown in Figure 14, the constant current circuit require low bias current and accurate voltage consists of an NPN transistor (Q2), Zener diode D , breakdown. Z current limit resistor (R ) and Zener bias resistor LIMIT (R ). R and R can be very low power resistors R maximum value can be calculated with the Z LIMIT Z Z and Q2 is a signal transistor where its Collector- following equation: Emitter Voltage (V ) is equal or greater than the CEO input operating voltage and supports 2.5mA at the Note that the surface mount resistors have limited operating input voltage. operating voltage capability. Be sure to pick a resistor package that can meet the maximum operating voltage (Vin). Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 10 of 19

 V V R  in_MIN Z_MAX Z I I Z B_MAX Where: V : Min input voltage in_MIN V : Zener diode maximum breakdown voltage Z_MAX I : Zener diode required reverse current Z I : Q2 required maximum base current which B_MAX calculated from the following equation: I I  C_MAX B_MAX h FE_MIN I : Q2 maximum expected collector current. Figure 15: SN leakage current vs. SN voltage during C_MAX input fault condition (input short) h : Q2 minimum gain. FE_MIN Fault Indication: N-Channel MOSFET Selection: FT is an open collector output and its return is Several factors affect MOSFET selection including referenced to SGND. When SGND is referenced to cost, on-state resistance (R ), DC current rating, DS(on) system ground, FT should be pulled up to the logic short pulse current rating, avalanche rating, power voltage via a resistor (10KΩ). When the SGND pin is dissipation, thermal conductivity, drain-to-source floating on a bias resistor (R ) or in a constant breakdown voltage (BVdss), gate-to-source voltage PG current circuit, a level shift circuit can be added to rating (Vgs), and gate threshold voltage (Vgs ). (TH) make the FT pin output referenced to the system The first step is to select a suitable MOSFET based on ground. See Figure 19. Leave FT unconnected if the BVdss requirement for the application. The BVdss not used. voltage rating should be higher than the applied Vin voltage plus expected transient voltages. Stray Note that in case of an input fault condition, where parasitic inductance in the circuit can also contribute the input voltage (Vin) and the VC pin are at to significant transient voltage conditions, particularly ground and the SN pin is at a high voltage, a during MOSFET turn-off after a reverse current fault parasitic path between SN and VC will draw bias has been detected. current (leakage current) from the output as a function of the voltage between SN and grounded In Active ORing applications when one of the input VC (V ) based on the following equation: power sources is shorted, a large reverse current is SN-GND sourced from the circuit output through the MOSFET. V 12V I  SNGND Depending on the output impedance of the system, SN_Lg R the reverse current may get very high in some PAR conditions before the MOSFET is turned off. Make Where: sure that the MOSFET pulse current capability can withstand the peak current. Such high current I : SN leakage current during input short SN_Lg conditions will store energy even in a small parasitic element. Note that PI2007 has a very fast response V : Voltage difference between SN pin (or load SNGND time to a fault condition achieving 80ns typical and voltage) and ground. 150ns maximum. This fast response time will minimize the reverse peak current to keep stored R : Resistor in the parasitic path, 10KΩ typical PAR energy and MOSFET avalanche energy very low to and 8kΩ minimum avoid damage (breakdown) to the MOSFET. Peak current during input short is calculated as follows, assuming that the output has very low impedance and it is not a limiting factor: V *t I  S RVS PEAK L PARASITIC Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 11 of 19

 Where: Trise Rth Pd Rth Is2R , I : Peak current in the MOSFET right before it MOSFET JA MOSFET JA DS(on) PEAK is turned off. Where: VS : Input voltage or load voltage at MOSFET Rth : Junction-to-Ambient thermal resistance JA source before input short condition did occur. R and PI2007 sensing: DS(on) tRVS : Reverse fault to MOSFET turn-off time. This The PI2007 senses the MOSFET source-to-drain will include PI2007 delay and the MOSFET voltage drop via the SP and SN pins to determine the turn off time. status of the current through the MOSFET. When the MOSFET is fully enhanced, its source-to-drain voltage L : Circuit parasitic inductance PARASITIC is equal to the MOSFET on-state resistance multiplied And the MOSFET avalanche energy during an input by the source current, VSD = RDS(on)*Is. The reverse current threshold is set for -6mV and when the short is calculated as follows: differential voltage between the SP & SN pins is more 1 1.3*V negative than -6mV, i.e. SP-SN-6mV, the PI2007 E  * (BR)DSS *L *I 2 AS 2 *1.3V V PARASITIC PEAK detects a reverse current fault condition and pulls the (BR)DSS S MOSFET gate pin low, thus turning off the MOSFET and preventing further reverse current. The reverse Where: current fault protection disconnects the power source E : Avalanche energy fault condition from the redundant bus, and allows the AS system to keep running. V : MOSFET breakdown voltage (BR)DSS MOSFET R and maximum steady state power DS(on) dissipation are closely related. Generally the lower the MOSFET R , the higher the current capability and DS(on) the lower the resultant power dissipation. This leads to reduced thermal management overhead, but will ultimately be higher cost compared to higher R DS(on) parts. It is important to understand the primary design goal objectives for the application in order to effectively trade off the performance of one MOSFET versus another. Power dissipation in active ORing circuits is derived from the total source current and the on-state resistance of the selected MOSFET. MOSFET power dissipation: Pd Is2 R MOSFET DS(on) Where : Is : Source Current R : MOSFET on-state resistance DS(on) Note: In the calculation use R at maximum MOSFET DS(on) temperature because R is temperature DS(on) dependent. Refer to the normalized R curves in DS(on) the MOSFET manufacturers datasheet. Some MOSFET R values may increase by 50% at DS(on) 125°C compared to values at 25°C. The Junction Temperature rise is a function of power dissipation and thermal resistance. Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 12 of 19

 Typical application Example 1: 40C  T 75C (15A)24.48m115C Jmax  W  Requirement: Redundant Bus Voltage = 12V (±10%, 10.8V to Recalculate based on increased Junction 13.2V) temperature, 115°C. Load Current = 15A (assume through each redundant At 115°C R will increase by 32%. DS(on) path) R 3.5m1.324.62m Maximum Ambient Temperature = 75°C DS(on) 40C  Solution: T 75C (15A)24.62m116.5C A single PI2007 with a suitable external MOSFET for Jmax  W  each redundant 12V power source should be used, configured as shown in the circuit schematic in Figure VC Bias: Vin maximum input is 13.2V, this is higher 16. than the 11V VC Clamp Voltage (V ) minimum. VC-SGND Use the high side PI2007 internal resistor between VR Select a suitable N-Channel MOSFET: Most pin and VC pin will fit for this application. industry standard MOSFETs have a Vgs rating of +/- 12V or higher. Select an N-Channel MOSFET with a Since the MOSFET requires only 4.5V for full low R which is capable of supporting the full load DS(on) enhancement then the PI2007 internal resistor current with some margin, so a MOSFET capable of between VR pin and VC pin will fit for this application. at least 18A in steady state is reasonable. An Connect VR to Vin at the source of the MOSFET and exemplary MOSFET having these characteristic is the connect a 1μF ceramic capacitor between VC pin and FDS6162N7 from Fairchild. SGND pin. From FDS6162N7 datasheet: Fault Indication:  N-Channel MOSFET  VDS= 20V Connect FT pin to the logic input and to the logic  I = 23A continuous drain current power supply via a 10KΩ resistor. D  I (Pulse) = 60A Pulsed drain current D  VGS(MAX)= 12V  R = 40°C/W when mounted on a 1in2 PCB θJA pad of 2 oz copper  R =2.9mΩ typical and 3.5mΩ maximum at DS(on) I =23A, V ≥4.5V, T =25°C D GS J Reverse current threshold is: Vth.reverse 6mV Is.reverse  2.07A Rds(on) 2.9m Power dissipation: R is 3.5mΩ maximum at 25°C & 4.5Vgs and will DS(on) increase as the temperature increases. Add 25°C to maximum ambient temperature to compensate for the temperature rise due to power dissipation. At 100°C (75°C + 25°C) R will increase by 28%. DS(on) R 3.5m1.284.48m maximum at 100°C DS(on) TriseRth Is2R Figure 16: PI2007 in 12V bus high side Active ORing JA DS(on) configuration Maximum Junction temperature T T Trise Jmax A Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 13 of 19

 R 18m1.5027m maximum at 95°C Typical application Example 2: DS(on) Requirement: Maximum Junction temperature after 10s +48V High Side Redundant 50C  Bus Voltage = +48V (+36V to +60V, 100V for 100ms T 60C (5.0A)227m93.75C transient) Jmax  W  Load Current = 5A load (assume through each For continuous operation refer the MOSFET redundant path) datasheet for R under continuous operation and Maximum Ambient Temperature = 60°C θJA plug it in place of 50°C/W. Solution: A single PI2007 with a suitable MOSFET for each VC Bias: Since the bus voltage is higher than 14V, redundant +48V power source should be used and connect VC pin to the high side of the input voltage configured as shown in Figure 17 or Figure 18. Figure and connect a bias resistor (R ) or a constant current 17 is configured with the VC biased from the return PG circuit between PI2007 SGND pin and ground (Vin line through a bias resistor. Figure 18 is configured return), as shown in Figure 17 and Figure 18. Place a with the VC biased from the return line through the low forward voltage drop Schottky diode and a 1μF constant current circuit. ceramic capacitor between SGND pin and VC pin. Select a suitable N-Channel MOSFET: Select the Also connect PGND pin to SGND at the coupling N-Channel MOSFET with voltage rating higher than capacitor terminal. the input voltage, Vin, plus any expected transient Recommended Schottky: PMEG3005AEA from NXP voltages, with a low R that is capable of DS(on) or equivalent supporting the full load current with margin. For instance, a 100V rated MOSFET with 10A current R selection: capability is suitable. An exemplary MOSFET having PG V V 36V 12.5V these characteristic is IRF7853PbF from International R  VCmin VCCLMMax  11.19k Rectifier. PG I 0.1mA 2.0mA0.1mA VC_Max Select R =11kΩ 1% PG From the IRF7853PbF datasheet: N-Channel MOSFET RPG maximum power dissipation: V = 100V (V V )2 60V 11V2 DS PdR  VCmax VCCLMMin  218mW ID = 8.3A maximum continuous drain current at PG R 11k 25°C PG Use ¼ W Resistor in 1206 package I = 66A pulsed drain current D-PULSE VGS(MAX) = 20V R = 50°C/W on 1in2 copper, t ≤ 10seconds θJA R for continuous operation not provided θJA R =14.4mΩ typical at V =10V, T =25°C DS(on) GS J R =18mΩ maximum at V =10V, T =25°C DS(on) GS J Reverse current threshold is: Vth.reverse 6mV Is.reverse  333mA R 18m DS(on) Power dissipation: Rds(on) is 18mΩ maximum at 25°C & 10Vgs and will increase as the temperature increases. Add 20°C to maximum ambient temperature to compensate for the temperature rise due to power dissipation. At 80°C (60°C + 20°C) Rds(on) will increase by 40%. R 18m1.4025.2m maximum at 80°C DS(on) Maximum Junction temperature 50C  T 60C (5.0A)225.2m91.5C Jmax  W  Figure 17: PI2007 in high side +48V application, VC Recalculate maximum R at 95°C. DS(on) is biased through a bias resistor At 95°C Rds(on) will increase by 50%: Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 14 of 19

 Pd 2.29mA[60V 11V (9.8V 0.7V)]91.37mW Q2 VC bias through Constant current circuit Select an NPN transistor with V equal or higher The transistor Power De-rating vs. temperature curve CEO than the input voltage (Vin) plus any expected in the manufacturer datasheet shows that the device transient voltage and capable of handling the can operate up to 110°C. expected maximum power dissipation. Any NPN transistor with V ≥ 100V in a small footprint is CEO suitable. An exemplary NPN is FJV1845 from Fairchild: From the FJV1845 datasheet: NPN Silicon Transistor V = 120V Collector-Emitter maximum voltage CEO I = 50mA maximum collector current C h = 150 minimum at I =3mA FE C V = 0.55V to 0.65V Base-Emitter saturation BE(sat) voltage at 25°C Select Zener Diode: Select the Zener diode with low bias current, a Zener diode with V =10 in small foot Z print is suitable for this application. An exemplary Zener diode MM3Z10VST1 from ON Semiconductor From the MM3Z10VST1 datasheet: 10V, 200mW Zener Diode V = 9.80V to 10.2V Zener voltage range Z I = 10μA will hold the Zener breakdown voltage R at 9.8V Figure 18: PI2007 in high side +48V application, VC is biased through constant current circuit. V V (on) 9.8V 0.7V R  Z_MIN BE  4.33k LIMIT I 2.1mA Fault Indication: VC_MAX Or 4.32kΩ 1% PI2007 SGND pin in this application is floating and FT is referenced to SGND. The FT output can be I 3.5mA I  C_MAX  23.33A referenced to system return (RTN) by adding a level B_MAX h 150 shift circuit as shown in Figure 19. FE_MIN Q1: 2SA1579T106R, 120V PNP transistor from R Calculation: Rohm. Z Use 100μA as minimum for the Zener diode reverse Q2: DTC114EET1G, 50V NPN with bias resistors from leakage current and Q2 base current combined. ON semiconductor. V V 36V 10.2V D1: 30V general purpose diode. R  in_MIN Z_MAX  258k Z I I 100A Z B_MAX Select R = 249kΩ 1% Z Maximum Q2 collector current: V V 10.2V 0.50V I  Z_MAX BE_MIN  2.29mA C_MAX R 4.32k*0.98 LIMIT_MIN Maximum Q2 power dissipation Pd I [Vin V (V V )] Q2 C_MAX MAX VCCLM Z_MIN EB_MAX Figure 19: FT level shift circuitry Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 15 of 19

 High and Low Side Active ORing for the Same Source: PI2007 and Picor PI2003 controllers can be configured to meet ATCA application that requires low and high side ORing as shown in Figure 20. See PICOR Application Notes for more details of the design procedure for this application. Figure 20: PI2007 and PI2003 configured for a combined high and low side ORing application Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 16 of 19

 Layout Recommendation: Use the following general guidelines when designing printed circuit boards. An example of the typical land pattern for a DFN PI2007 and SO-8/PowerPak MOSFET is shown in Figure 21 and Figure 22:  It is best to connect the gate of the MOSFET to the GATE pin of the controller with a short trace. A gate resistor (R ) is added to slow down the gate G turn off if needed.  The VC bypass capacitor should be located as close as possible to the VC and SGND pins. Place the PI2007 and VC bypass capacitor on the same layer of the board. The VC pin and C VC PCB trace should not contain any vias.  In an application where SGND is floating, a low forward voltage drop Schottky diode has to be added in parallel with C to protect the controller VC during an input voltage short fault. Figure 21: PI2007 controller and MOSFET layout  PGND pin of the controller carries high peak recommendation in a floating application. current during gate pull down, Connect PGND pin with a wide trace to the C terminal at SGND. VC Make sure that SGND trace and PGND trace connect only at C terminal. VC  Connections from the SP and SN pins to the MOSFET source and drain pins respectively should be as short as possible  Connect all MOSFET source pins together with a wide trace to reduce trace parasitics and to accommodate the high current input. Similarly, connect all MOSFET Drain pins together with a wide trace to accommodate the high current output. Figure 22: PI2007 controller and MOSFET layout recommendation in a non-floating application Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 17 of 19

 Package Drawing: 10 Lead DFN Thermal Resistance Ratings Parameter Symbol Typical Unit Maximum Junction-to-Ambient (4) θ 53 C/W JA Note 4: In accordance with JEDEC JESD 51 Ordering Information Part Number Package Transport Media PI2007-00-QEIG 3mm x 3mm 10 Lead DFN T&R Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 18 of 19

 Warranty Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR LIMITED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages. Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. Vicor Corporation Picor Corporation 25 Frontage Road 51 Industrial Drive Andover, MA 01810 North Smithfield, RI 02896 USA USA Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com Tel: 800-735-6200 Fax: 978-475-6715 Picor Corporation • picorpower.com PI2007 Rev 1.3 Page 19 of 19