PGA112 PGA113 PPGGAA111166 PGA117 PGA116,, PGA117 PGA112 PGA113 , www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 Zerø-Drift PROGRAMMABLE GAIN AMPLIFIER with MUX FEATURES APPLICATIONS 1 • Rail-to-RailInput/Output • Remotee-MeterReading 23 • Offset:25m V(typ),100m V(max) • AutomaticGainControl • ZerøDrift:0.35m V/°C(typ),1.2m V/°C(max) • PortableDataAcquisition • LowNoise:12nV/√Hz • PC-BasedSignalAcquisitionSystems • InputOffsetCurrent:±5nAmax(+25°C) • TestandMeasurement • ProgrammableLogicControllers • GainError:0.1%max(G≤32), • Battery-PoweredInstruments 0.3%max(G>32) • HandheldTestEquipment • BinaryGains:1,2,4,8,16,32,64,128 (PGA112,PGA116) DESCRIPTION • ScopeGains:1,2,5,10,20,50,100,200 (PGA113,PGA117) The PGA112 and PGA113 (binary/scope gains) offer two analog inputs, a three-pin SPI interface, and • GainSwitchingTime:200ns software shutdown in an MSOP-10 package. The • TwoChannelMUX:PGA112,PGA113 PGA116 and PGA117 (binary/scope gains) offer 10 10ChannelMUX:PGA116,PGA117 analog inputs, a four-pin SPI interface with • FourInternalCalibrationChannels daisy-chain capability, and hardware and software shutdowninaTSSOP-20package. • AmplifierOptimizedforDrivingCDACADCs • OutputSwing:50mVtoSupplyRails All versions provide internal calibration channels for system-level calibration. The channels are tied to • AV andDV forMixedVoltageSystems DD DD GND, 0.9V , 0.1V , and V , respectively. V , CAL CAL REF CAL • I =1.1mA(typ) an external voltage connected to Channel 0, is used Q • Software/HardwareShutdown:I ≤4m A(typ) as the system calibration reference. Binary gains are: Q 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, • TemperatureRange:–40°Cto+125°C 5,10,20,50,100,and200. • SPI™Interface(10MHz)withDaisy-Chain Capability +3V +5V CBYPASS CBYPASS CBYPASS 0.1mF 0.1mF 0.1mF AVDD DVDD 1 10 MSP430 PGA112 Microcontroller PGA113 VCAL/CCHH10 32 MUX OSutatpguet 5 VOUT ADC CAL1 10kW G = 1 RF 0.9VCAL CAL2 0.1VCAL CAL3 80kW CAL4 VREF RI 7 SCLK SPI 8 DIO CAL2/3 Interface 9 CS 10kW 6 4 GND VREF 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SPIisatrademarkofMotorola. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. PACKAGEANDMODELCOMPARISON SHUTDOWN #OFMUX GAINS SPI DEVICE INPUTS (EightEach) DAISY-CHAIN HARDWARE SOFTWARE PACKAGE PGA112 Two Binary No No (cid:252) MSOP-10 PGA113 Two Scope No No (cid:252) MSOP-10 PGA116 10 Binary (cid:252) (cid:252) (cid:252) TSSOP-20 PGA117 10 Scope (cid:252) (cid:252) (cid:252) TSSOP-20 ORDERINGINFORMATION(1) DESCRIPTION PACKAGE PACKAGE PRODUCT (Gains/Channels) PACKAGE-LEAD DESIGNATOR MARKING PGA112 Binary(2)/2Channels MSOP-10 DGS P112 PGA113 Scope(3)/2Channels MSOP-10 DGS P113 PGA116 Binary(2)/10Channels TSSOP-20 PW PGA116 PGA117 Scope(3)/10Channels TSSOP-20 PW PGA117 (1) ForthemostcurrentpackageandorderinginformationseethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. (2) Binarygains:1,2,4,8,16,32,64,and128. (3) Scopegains:1,2,5,10,20,50,100,and200. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. PGA112,PGA113,PGA116,PGA117 UNIT SupplyVoltage +7 V SignalInputTerminals,Voltage(2) GND–0.5to(AV )+0.5 V DD SignalInputTerminals,Current(2) ±10 mA OutputShort-Circuit Continuous OperatingTemperature –40to+125 °C StorageTemperature –65to+150 °C JunctionTemperature +150 °C HumanBodyModel(HBM) 3000 V ESDRatings: ChargedDeviceModel(CDM) 1000 V MachineModel(MM) 300 V (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotimplied. (2) Inputterminalsarediode-clampedtothepower-supplyrails.Inputsignalsthatcanswingmorethan0.5Vbeyondthesupplyrailsshould becurrentlimitedto10mAorless. 2 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 ELECTRICAL CHARACTERISTICS: V = AV = DV = +5V S DD DD Boldfacelimitsapplyoverthespecifiedtemperaturerange,T =–40°Cto+125°C. A AtT =+25°C,R =10kΩ//C =100pFconnectedtoDV /2,andV =GND,unlessotherwisenoted. A L L DD REF PGA112,PGA113,PGA116,PGA117 PARAMETER CONDITIONS MIN TYP MAX UNIT OFFSETVOLTAGE InputOffsetVoltage VOS AVDD=DVDD=+5V,VREF=VIN=AVDD/2,VCM=2.5V ±25 ±100 m V AVDD=DVDD=+5V,VREF=VIN=AVDD/2,VCM=4.5V ±75 ±325 m V vsTemperature,–40°Cto+125°C dVOS/dT AVDD=DVDD=+5V,VCM=2.5V 0.35 1.2 m V/°C vsTemperature,–40°Cto+85°C AVDD=DVDD=+5V,VCM=2.5V 0.15 0.9 m V/°C vsTemperature,–40°Cto+125°C AVDD=DVDD=+5V,VCM=4.5V 0.6 1.8 m V/°C vsTemperature,–40°Cto+85°C AVDD=DVDD=+5V,VCM=4.5V 0.3 1.3 m V/°C vsPowerSupply PSRR AVDD=DVDD=+2.2Vto+5.5V,VCM=0.5V, 5 20 m V/V VREF=VIN=AVDD/2 OverTemperature,–40°Cto+125°C AVDD=DVDD=+2.2Vto+5.5V,VCM=0.5V, 5 40 m V/V VREF=VIN=AVDD/2 INPUTON-CHANNELCURRENT InputOn-ChannelCurrent(Ch0,Ch1) IIN VREF=VIN=AVDD/2 ±1.5 ±5 nA OverTemperature,–40°Cto+125°C VREF=VIN=AVDD/2 SeeTypicalCharacteristics nA INPUTVOLTAGERANGE InputVoltageRange(1) IVR GND–0.1 AVDD+0.1 V OvervoltageInputRange NoOutputPhaseReversal(2) GND–0.3 AVDD+0.3 V INPUTIMPEDANCE(ChannelOn)(3) ChannelInputCapacitance CCH 2 pF ChannelSwitchResistance RSW 150 Ω AmplifierInputCapacitance CAMP 3 pF AmplifierInputResistance RAMP InputResistancetoGND 10 GΩ VCAL/CH0 RIN CAL1orCAL2Selected 100 kΩ GAINSELECTIONS NominalGains Binarygains:1,2,4,8,16,32,64,128 1 128 Scopegains:1,2,5,10,20,50,100,200 1 200 DCGainError G=1 VOUT=GND+85mVtoDVDD–85mV 0.006 0.1 % 1<G≤32 VOUT=GND+85mVtoDVDD–85mV 0.1 % G≥50 VOUT=GND+85mVtoDVDD–85mV 0.3 % DCGainDrift G=1 VOUT=GND+85mVtoDVDD–85mV 0.5 ppm/°C 1<G≤32 VOUT=GND+85mVtoDVDD–85mV 2 ppm/°C G≥50 VOUT=GND+85mVtoDVDD–85mV 6 ppm/°C CAL2DCGainError(4) OpAmp+Input=0.9VCAL, 0.02 % VREF=VCAL=AVDD/2,G=1 CAL2DCGainDrift(4) OpAmp+Input=0.9VCAL, 2 ppm/°C VREF=VCAL=AVDD/2,G=1 CAL3DCGainError(4) OpAmp+Input=0.1VCAL, 0.02 % VREF=VCAL=AVDD/2,G=1 CAL3DCGainDrift(4) OpAmp+Input=0.1VCAL, 2 ppm/°C VREF=VCAL=AVDD/2,G=1 INPUTIMPEDANCE(ChannelOff)(3) InputImpedance CCH SeeFigure1 2 pF INPUTOFF-CHANNELCURRENT InputOff-ChannelCurrent(Ch0,Ch1)(5) ILKG VREFV=ONG-CNHADN,NEVLO=FFA-CVHADNDN/2EL–=0A.1VVDD/2, ±0.05 ±1 nA OverTemperature,–40°Cto+125°C VREF=GND,VOFF-CHANNEL=AVDD/2, SeeTypicalCharacteristics VON-CHANNEL=AVDD/2–0.1V Channel-to-ChannelCrosstalk 130 dB (1) Gainerrorisafunctionoftheinputvoltage.Gainerroroutsideoftherange(GND+85mV≤V ≤DV –85mV)increasesto0.5% OUT DD (typical). (2) Inputvoltagesbeyondthisrangemustbecurrentlimitedto<|10mA|throughtheinputprotectiondiodesoneachchanneltoprevent permanentdestructionofthedevice. (3) SeeFigure1. (4) TotalV errormustbecomputedusinginputoffsetvoltageerrormultipliedbygain.IncludesopampG=1error. OUT (5) Maximumspecificationlimitationlimitedbyfinaltesttimeandcapability. Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS: V = AV = DV = +5V (continued) S DD DD Boldfacelimitsapplyoverthespecifiedtemperaturerange,T =–40°Cto+125°C. A AtT =+25°C,R =10kΩ//C =100pFconnectedtoDV /2,andV =GND,unlessotherwisenoted. A L L DD REF PGA112,PGA113,PGA116,PGA117 PARAMETER CONDITIONS MIN TYP MAX UNIT OUTPUT VoltageOutputSwingfromRail IOUT=±0.25mA,AVDD≥DVDD(6) GND+0.05 DVDD–0.05 V IOUT=±5mA,AVDD≥DVDD(6) GND+0.25 DVDD–0.25 V DCOutputNonlinearity VOUT=GND+85mVtoDVDD–85mV(7) 0.0015 %FSR Short-CircuitCurrent ISC –30/+60 mA CapacitiveLoadDrive CLOAD SeeTypicalCharacteristics NOISE InputVoltageNoiseDensity en f>10kHz,CL=100pF,VS=5V 12 nV/√Hz f>10kHz,CL=100pF,VS=2.2V 22 nV/√Hz InputVoltageNoise en f=0.1Hzto10Hz,CL=100pF,VS=5V 0.362 m VPP f=0.1Hzto10Hz,CL=100pF,VS=2.2V 0.736 m VPP InputCurrentDensity In f=10kHz,CL=100pF 400 fA/√Hz SLEWRATE SlewRate SR SeeTable1 V/m s SETTLINGTIME SettlingTime tS SeeTable1 m s FREQUENCYRESPONSE FrequencyResponse SeeTable1 MHz THD+NOISE G=1,f=1kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.003 % G=10,f=1kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.005 % G=50,f=1kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.03 % G=128,f=1kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.08 % G=200,f=1kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.1 % G=1,f=20kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.02 % G=10,f=20kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.01 % G=50,f=20kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.03 % G=128,f=20kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.08 % G=200,f=20kHz,VOUT=4VPPat2.5VDC,CL=100pF 0.11 % POWERSUPPLY OperatingVoltageRange(6) AVDD 2.2 5.5 V DVDD 2.2 5.5 V QuiescentCurrentAnalog IQA IO=0,G=1,VOUT=VREF 0.33 0.45 mA OverTemperature,–40°Cto+125°C 0.45 mA QuiescentCurrentDigital(8)(9)(10) IQD IO=C0,SG==Lo1g,iVcO0U,TD=IOVRoErF,DSINCL=KLaotg1ic00MHz, 0.75 1.2 mA OverTemperature,–40°Cto+125°C(8)(9)(10) IO=0,G=1,VOUT=VREF,SCLKat10MHz, 1.2 mA CS=Logic0,DIOorDIN=Logic0 ShutdownCurrentAnalog+Digital(8)(9) ISDA+ISDD IO=0,VOUT=VREF,G=1,SCLKIdle 4 m A IO=0,VOUT=0,G=1,SCLKat10MHz, 245 m A CS=Logic0,DIOorDIN=Logic0 POWER-ONRESET(POR) DigitalinterfacedisabledandCommandRegistersettoPOR PORTripVoltage 1.6 V valuesforDVDD <PORTripVoltage (6) WhenAV islessthanDV ,theoutputisclampedtoAV +300mV. DD DD DD (7) Measurementlimitedbynoiseintestequipmentandtesttime. (8) DoesnotincludecurrentintooroutoftheV pin.InternalR andR arealwaysconnectedbetweenV andV . REF F I OUT REF (9) Digitallogiclevels:DIOorDIN=logic0.10m Ainternalpull-downcurrentsource. (10) Includescurrentfromopampoutputstructure. 4 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 ELECTRICAL CHARACTERISTICS: V = AV = DV = +5V (continued) S DD DD Boldfacelimitsapplyoverthespecifiedtemperaturerange,T =–40°Cto+125°C. A AtT =+25°C,R =10kΩ//C =100pFconnectedtoDV /2,andV =GND,unlessotherwisenoted. A L L DD REF PGA112,PGA113,PGA116,PGA117 PARAMETER CONDITIONS MIN TYP MAX UNIT TEMPERATURERANGE SpecifiedRange –40 +125 °C OperatingRange –40 +125 °C ThermalResistance q JA MSOP-10 164 °C/W DIGITALINPUTS(SCLK,CS,DIO,DIN) LogicLow 0 0.3DVDD V InputLeakageCurrent(SCLKandCSonly) –1 +1 m A WeakPull-DownCurrent(DIO,DINonly) 10 m A LogicHigh 0.7DVDD DVDD V Hysteresis 700 mV DIGITALOUTPUT(DIO,DOUT) LogicHigh IOH=–3mA(sourcing) DVDD–0.4 DVDD V LogicLow IOL=+3mA(sinking) GND GND+0.4 V CHANNELANDGAINTIMING ChannelSelectTime 0.2 m s GainSelectTime 0.2 m s SHUTDOWNMODETIMING EnableTime 4.0 m s DisableTime VOUTgoeshigh-impedance,RFandRIremainconnected 2.0 m s betweenVOUTandVREF POWER-ON-RESET(POR)TIMING PORPower-UpTime DVDD≥2V 40 m s PORPower-DownTime DVDD≤1.5V 5 m s Table1.FrequencyResponseversusGain(C =100pF,R =10kΩ) L L 0.1% 0.01% 0.1% 0.01% TYPICAL SLEW SLEW SETTLING SETTLING TYPICAL SLEW SLEW SETTLING SETTLING –3dB RATE- RATE- TIME: TIME: SCOPE –3dB RATE- RATE- TIME: TIME: BINARY FREQUENCY FALL RISE 4VPP 4VPP GAIN FREQUENCY FALL RISE 4VPP 4VPP GAIN(V/V) (MHz) (V/m s) (V/m s) (m s) (m s) (V/V) (MHz) (V/m s) (V/m s) (m s) (m s) 1 10 8 3 2 2.55 1 10 8 3 2 2.55 2 3.8 9 6.4 2 2.6 2 3.8 9 6.4 2 2.6 4 2 12.8 10.6 2 2.6 5 1.8 12.8 10.6 2 2.6 8 1.8 12.8 10.6 2 2.6 10 1.8 12.8 10.6 2.2 2.6 16 1.6 12.8 12.8 2.3 2.6 20 1.3 12.8 9.1 2.3 2.8 32 1.8 12.8 13.3 2.3 3 50 0.9 9.1 7.1 2.4 3.8 64 0.6 4 3.5 3 6 100 0.38 4 3.5 4.4 7 128 0.35 2.5 2.5 4.8 8 200 0.23 2.3 2 6.9 10 Mux Switch R SW CHx (Input) CCH CAMP RAMP VOUT Break-Before-Make R F R I V REF Figure1.EquivalentInputCircuit Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com SPI TIMING: V = AV = DV = +2.2V to +5V S DD DD Boldfacelimitsapplyoverthespecifiedtemperaturerange,T =–40°Cto+125°C. A AtT =+25°C,R =10kΩ//C =100pFconnectedtoDV /2,andV =GND,unlessotherwisenoted. A L L DD REF PGA112,PGA113, PGA116,PGA117 PARAMETER TESTCONDITIONS MIN TYP MAX UNIT InputCapacitance(SCLK,CS,andDIOpins) 1 pF InputRise/FallTime(1) t 2 m s (CS,SCLK,andDIOpins) RFI OutputRise/FallTime(DIOpin)(1) t C =60pF 10 ns RFO LOAD CSHighTime(CSpin)(1) t 40 ns CSH SCLKEdgetoCSFallSetupTime(1) t 10 ns CSO CSFalltoFirstSCLKEdgeSetupTime t 10 ns CSSC SCLKFrequency(2) f 10 MHz SCLK SCLKHighTime(3) t 40 ns HI SCLKLowTime(3) t 40 ns LO SCLKLastEdgetoCSRiseSetupTime(1) t 10 ns SCCS CSRisetoSCLKEdgeSetupTime(1) t 10 ns CS1 DINSetupTime t 10 ns SU DINHoldTime t 10 ns HD SCLKtoDOUTValidPropagationDelay(1) t 25 ns DO CSRisetoDOUTForcedtoHi-Z(1) t 20 ns SOZ (1) Ensuredbydesign;notproductiontested. (2) Whenusingdevicesindaisy-chainmode,themaximumclockfrequencyforSCLKislimitedbySCLKrise/falltime,DINsetuptime,and DOUTpropagationdelay.SeeFigure63.Basedonthislimitation,themaximumSCLKfrequencyfordaisy-chainmodeis9.09MHz. (3) t andt mustnotbelessthan1/SCLK(max). HI LO 6 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 SPI TIMING DIAGRAMS t CSH CS t t t t CSSC SCCS CS1 CS0 t t LO HI SCLK 1/f SCLK t t SU HD DIN t t DO SOZ Hi-Z Hi-Z DOUT Figure2.SPIMode0,0 t CSH CS tCSSC tSCCS tCS1 tCS0 t t HI LO SCLK 1/f SCLK t t SU HD DIN t t DO SOZ Hi-Z Hi-Z DOUT Figure3.SPIMode1,1 Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com PIN CONFIGURATIONS MSOP-10 DGSPACKAGE (TOPVIEW) AV 1 10 DV DD DD CH1 2 9 CS PGA112 V /CH0 3 8 DIO CAL PGA113 V 4 7 SCLK REF V 5 6 GND OUT PGA112,PGA113TERMINALFUNCTIONS MSOP PACKAGE PIN# NAME DESCRIPTION 1 AV Analogsupplyvoltage(+2.2Vto+5.5V) DD 2 CH1 InputMUXchannel1 InputMUXchannel0andV input.Forsystemcalibrationpurposes,connectthispintoa CAL low-impedanceexternalreferencevoltagetouseinternalcalibrationchannels.Thefourinternal 3 V /CH0 calibrationchannelsareconnectedtoGND,0.9V ,0.1V ,andV ,respectively.V isloaded CAL CAL CAL REF CAL with100kΩ(typical)wheninternalcalibrationchannelsCAL2orCAL3areselected.Otherwise, V /CH0appearsashighimpedance. CAL Referenceinputpin.ConnectexternalreferenceforV offsetshiftortomidsupplyformidsupply OUT 4 V referencedsystems.V mustbeconnectedtoalow-impedancereferencecapableofsourcingand REF REF sinkingatleast2mAorV mustbeconnectedtoGND. REF 5 V Analogvoltageoutput.WhenAV <DV ,V isclampedtoAV +300mV. OUT DD DD OUT DD 6 GND Groundpin 7 SCLK ClockinputforSPIserialinterface 8 DIO Datainput/outputforSPIserialinterface.DIOcontainsaweak,10m Ainternalpull-downcurrentsource. 9 CS ChipselectlineforSPIserialinterface Digitalandopampoutputstagesupplyvoltage(+2.2Vto+5.5V).Usefulinmulti-supplysystemsto preventovervoltage/lockupconditiononananalog-to-digital(ADC)input(forexample,amicrocontroller 10 DV withanADCrunningon+3VandthePGApoweredfrom+5V).DigitalI/OlevelstoberelativetoDV . DD DD DV shouldbebypassedwitha0.1m Fceramiccapacitor,andDV mustsupplythecurrentforthe DD DD digitalportionofthePGAaswellastheloadcurrentfortheopampoutputstage. 8 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 TSSOP-20 PWPACKAGE (TOPVIEW) AV 1 20 CH6 DD CH5 2 19 DV DD CH4 3 18 CS CH3 4 17 DOUT PGA116 CH2 5 16 DIN PGA117 CH1 6 15 SCLK V /CH0 7 14 GND CAL V 8 13 ENABLE REF V 9 12 CH9 OUT CH7 10 11 CH8 PGA116,PGA117TERMINALFUNCTIONS TSSOP PACKAGE PIN# NAME DESCRIPTION 1 AV Analogsupplyvoltage(+2.2Vto+5.5V) DD 2 CH5 InputMUXchannel5 3 CH4 InputMUXchannel4 4 CH3 InputMUXchannel3 5 CH2 InputMUXchannel2 6 CH1 InputMUXchannel1 InputMUXchannel0andV input.Forsystemcalibrationpurposes,connectthispintoa CAL low-impedanceexternalreferencevoltagetouseinternalcalibrationchannels.Thefourinternal 7 V /CH0 calibrationchannelsareconnectedtoGND,0.9V ,0.1V ,andV ,respectively.V isloaded CAL CAL CAL REF CAL with100kΩ(typical)wheninternalcalibrationchannelsCAL2orCAL3areselected.Otherwise, V /CH0appearsashighimpedance. CAL Referenceinputpin.ConnectexternalreferenceforV offsetshiftortomidsupplyformidsupply OUT 8 V referencedsystems.V mustbeconnectedtoalow-impedancereferencecapableofsourcingand REF REF sinkingatleast2mAortoGND. 9 V Analogvoltageoutput.WhenAV <DV ,V isclampedtoAV +300mV. OUT DD DD OUT DD 10 CH7 InputMUXchannel7 11 CH8 InputMUXchannel8 12 CH9 InputMUXchannel9 13 ENABLE Hardwareenablepin.LogiclowputsthepartintoShutdownmode(I <1m A). Q 14 GND Groundpin 15 SCLK ClockinputforSPIserialinterface DatainputforSPIserialinterface.DINcontainsaweak,10m Ainternalpull-downcurrentsourceto 16 DIN allowforeaseofdaisy-chainconfigurations. DataoutputforSPIserialinterface.DOUTgoestohigh-ZstatewhenCSgoeshighforstandardSPI 17 DOUT interface. 18 CS ChipselectlineforSPIserialinterface Digitalandopampoutputstagesupplyvoltage(+2.2Vto+5.5V).Usefulinmulti-supplysystemsto preventovervoltage/lockupconditiononanADCinput(forexample,amicrocontrollerwithanADC 19 DV runningon+3VandthePGApoweredfrom+5V).DigitalI/OlevelstoberelativetoDV .DV should DD DD DD bebypassedwitha0.1m Fceramiccapacitor,andDV mustsupplythecurrentforthedigitalportionof DD thePGAaswellastheloadcurrentfortheopampoutputstage. 20 CH6 InputMUXchannel6 Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com TYPICAL APPLICATION CIRCUITS +3V +5V C C C BYPASS BYPASS BYPASS 0.1mF 0.1mF 0.1mF AV DV DD DD 1 10 MSP430 PGA112 Microcontroller PGA113 3 V /CH0 MUX CALCH1 2 Output 5 VOUT ADC Stage CAL1 10kW R G = 1 F 0.9V CAL CAL2 0.1V CAL CAL3 80kW CAL4 VREF RI 7 SCLK SPI 8 DIO CAL2/3 Interface 9 CS 10kW 6 4 GND V REF Figure4.PGA112,PGA113(MSOP-10) +5V C BYPASS 0.1mF AV DD 1 7 V /CH0 +3V CAL 6 19 DV CH1 DD CH2 45 PPGGAA111167 C0.B1YmPFASS CBYPASS CH3 0.1mF 3 CH4 2 CH5 20 MSP430 CH6 Microcontroller 10 CH7 MUX 11 CH8 CH9 12 Output 9 VOUT ADC Stage CAL1 10kW R G = 1 F 0.9V CAL CAL2 0.1V CAL CAL3 80kW CAL4 VREF RI 15 SCLK 16 DIN SPI 18 CS CAL2/3 Interface 10kW 17 DOUT 14 8 13 GND V ENABLE REF Figure5.PGA116,PGA117(TSSOP-20) 10 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 TYPICAL CHARACTERISTICS AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L OFFSETVOLTAGE OFFSETVOLTAGE VCM= 2.5V VCM= 4.5V n n o o ati ati ul ul p p o o P P -100-90-80-70-60-50-40-30-20-100102030405060708090100 325.0292.5260.0227.5195.0162.5130.0-97.5-65.0-32.5032.565.097.5130.0162.5195.0227.5260.0292.5325.0 Offset Voltage (mV) ------- Offset Voltage (mV) Figure6. Figure7. OFFSETVOLTAGEDRIFT OFFSETVOLTAGEDRIFT (–40°Cto+85°C) (–40°CTO+85°C) VCM= 2.5V VCM= 4.5V n n o o ati ati ul ul p p o o P P -0.90-0.81-0.72-0.63-0.54-0.45-0.36-0.27-0.18-0.0900.090.180.270.360.450.540.630.720.810.90 -1.30-1.17-1.04-0.91-0.78-0.65-0.52-0.39-0.26-0.1300.130.260.390.520.650.780.911.041.171.30 Offset Voltage Drift (mV/°C) Offset Voltage Drift (mV/°C) Figure8. Figure9. OFFSETVOLTAGEDRIFT OFFSETVOLTAGEDRIFT (–40°Cto+125°C) (–40°CTO+125°C) V = 2.5V V = 4.5V CM CM n n o o ati ati ul ul p p o o P P 086420864202468024680 024680246808642086420 2098764321 1234678902 8642097531 1357902468 1.1.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.1.1. 1.1.1.1.1.0.0.0.0.0. 0.0.0.0.0.1.1.1.1.1. ---------- ---------- Offset Voltage Drift (mV/°C) Offset Voltage Drift (mV/°C) Figure10. Figure11. Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L INPUTOFFSETVOLTAGEvsINPUTVOLTAGE PGA112/PGA116NONLINEARITY 100 0.0010 80 SR) 0.0008 AVDD= DVDD= +5V F G = 1 G = 2 mge (V) 6400 Error (% 00..00000064 Input Offset Volta ---224600000 utput Nonlinearity ---0000....00000000000022460 G = 16 O G = 128 -80 C -0.0008 D -100 -0.0010 0 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Input Voltage (V) V (V) OUT Figure12. Figure13. GAINERROR(G=1) GAINERROR(1<G≤32) n n o o ati ati ul ul p p o o P P 098765432101234567890 098765432101234567890 1000000000 0000000001 1000000000 0000000001 0.0.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.0.0. ---------- ---------- Gain Error (%) Gain Error (%) Figure14. Figure15. GAINERRORDRIFT GAINERROR(G≥50) (–40°Cto+125°C) G = 1 n n o o ati ati ul ul p p o o P P 000000000000000000000 050505050505050505050 0741852963 3692581470 01122334455667788990 0.30.20.20.20.10.10.10.00.00.0 0.00.00.00.10.10.10.20.20.20.3 0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.1. ---------- Gain Error Drift (ppm/°C) Gain Error (%) Figure16. Figure17. 12 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L GAINERRORDRIFT GAINERRORDRIFT (–40°Cto+125°C) (–40°Cto+125°C) 1<G£32 G³50 n n o o ati ati ul ul p p o o P P 050505050505050505050 050505050505050505050 0.20.50.71.01.21.51.72.02.22.52.73.03.23.53.74.04.24.54.75.0 0.1.1.2.2.3.3.4.4.5.5.6.6.7.7.8.8.9.9.10. Gain Error Drift (ppm/°C) Gain Error Drift (ppm/°C) Figure18. Figure19. CAL2GAINERROR CAL3GAINERROR n n o o ati ati ul ul p p o o P P 098765432101234567890 098765432101234567890 1000000000 0000000001 1000000000 0000000001 0.0.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.0.0. 0.0.0.0.0.0.0.0.0.0. ---------- ---------- Gain Error (%) Gain Error (%) Figure20. Figure21. CAL2GAINERRORDRIFT CAL3GAINERRORDRIFT (–40°Cto+125°C) (–40°Cto+125°C) n n o o ati ati ul ul p p o o P P 086420864202468024680 0864208642024680246800 2.1.1.1.1.1.0.0.0.0. 0.0.0.0.1.1.1.1.1.2. 2.1.1.1.1.1.0.0.0.0. 0.0.0.0.1.1.1.1.1.2.2. ---------- ---------- > Gain Error Drift (ppm/°C) Gain Error Drift (ppm/°C) Figure22. Figure23. Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L 0.1HzTO10HzNOISE 0.1HzTO10HzNOISE V = 2.2V V = 5V S S v v di di V/ V/ n n 0 0 5 0 2 1 2.5s/div 2.5s/div Figure24. Figure25. PGA112,PGA116THD+NOISEvsFREQUENCY SPECTRALNOISEDENSITY (V =2V ) OUT PP 100 1k 1 G = 128 G = 64 G = 32 G = 16 z) C 0.1 ÖVoltage Noise (nV/H 5200 CurreVnot lNtaogisee N, oViSse=, 5VVS= 2.2V 520000 urrent Noise Hz(fA/)Ö THD+N (%) 0.00.0011 Voltage Noise, V = 5V S G = 8 G = 1 G = 2 G = 4 10 100 0.0001 1 10 100 1k 10k 100k 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure26. Figure27. PGA112,PGA116THD+NOISEvsFREQUENCY PGA113,PGA117THD+NOISEvsFREQUENCY (V =4V ) (V =2V ) OUT PP OUT PP 1 1 G = 200 G = 100 G = 50 G = 20 G = 128 G = 64 G = 32 G = 16 0.1 0.1 %) %) +N ( 0.01 +N ( 0.01 D D H H T T G = 8 0.001 0.001 G = 4 G = 2 G = 1 G = 1 G = 2 G = 5 G = 10 0.0001 0.0001 10 100 1k 10k 100k 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure28. Figure29. 14 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L PGA113,PGA117THD+NOISEvsFREQUENCY QUIESCENTCURRENT (V =4V ) vsTEMPERATURE OUT PP 1 0.8 G = 200 G = 100 G = 50 0.7 G = 20 0.1 0.6 Digital %) 0.5 D+N ( 0.01 (mA)Q 0.4 H I T 0.3 G = 1 Analog 0.001 0.2 V = 5.5V G = 2 0.1 S G = 5 G = 10 VS= 2.2V fSCLK= 10MHz 0.0001 0 10 100 1k 10k 100k -50 -25 0 25 50 75 100 125 Frequency (Hz) Temperature (°C) Figure30. Figure31. TOTALQUIESCENTCURRENT SHUTDOWNQUIESCENTCURRENT vsSUPPLYVOLTAGE vsTEMPERATURE 1.2 4.0 SCLK = 5MHz SCLK = 10MHz 3.5 1.0 3.0 Digital mA) 0.8 SCLK = 500kHz SCLK = 2MHz m(A)Q 2.5 (QD 0.6 wn I 2.0 + I do IQA 0.4 Shut 1.5 1.0 Analog 0.2 0.5 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 -25 0 25 50 75 100 125 Supply Voltage (V) Temperature (°C) Figure32. Figure33. OUTPUTVOLTAGE OUTPUTVOLTAGE vsOUTPUTCURRENT vsOUTPUTCURRENT 2.2 5.5 V = 2.2V V = 5.5V 2.0 S 5.0 S G = 1 G = 1 1.8 4.5 V) 1.6 V) 4.0 Output Voltage ( 11100.....42086 +125°C +25°C -40°C Output Voltage ( 33221.....50505 +125°C +25°C-40°C 0.4 1.0 0.2 0.5 0 0 0 2 4 6 8 10 12 14 16 18 20 22 24 0 10 20 30 40 50 60 70 80 90 100 Output Current (mA) Output Current (mA) Figure34. Figure35. Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L PGA112,PGA116OUTPUTVOLTAGESWINGvs PGA112,PGA116OUTPUTVOLTAGESWINGvs FREQUENCY FREQUENCY 2.5 2.5 AVDD= DVDD= 2.2V G = 4 AVDD=DVDD=2.2V 2.0 2.0 G = 8 V) V) ge ( 1.5 ge ( 1.5 a G = 2 a G = 16 Volt Volt G = 64 ut 1.0 ut 1.0 p p ut ut O O G = 32 0.5 0.5 G = 1 G = 128 0 0 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure36. Figure37. PGA112,PGA116OUTPUTVOLTAGESWINGvs PGA112,PGA116OUTPUTVOLTAGESWINGvs FREQUENCY FREQUENCY 6 6 G = 8 G = 16 5 5 G = 4 e (V) 4 e (V) 4 G = 32 g g a a olt 3 olt 3 ut V G = 1 ut V G = 64 p p ut 2 ut 2 O O G = 2 1 1 AVDD= DVDD= 5.5V AVDD= DVDD= 5.5V G = 128 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure38. Figure39. PGA113,PGA117OUTPUTVOLTAGESWINGvs PGA113,PGA117OUTPUTVOLTAGESWINGvs FREQUENCY FREQUENCY 2.5 2.5 2.0 2.0 G = 20 V) G = 10 V) Voltage ( 1.5 G = 2 Voltage ( 1.5 G = 100 G = 50 Output 1.0 G = 1 Output 1.0 G = 200 0.5 G = 5 0.5 AV = DV = 2.2V AV = DV = 2.2V DD DD DD DD 0 0 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure40. Figure41. 16 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L PGA113,PGA117OUTPUTVOLTAGESWINGvs PGA113,PGA117OUTPUTVOLTAGESWINGvs FREQUENCY FREQUENCY 6 6 5 5 G = 10 G = 50 e (V) 4 G = 5 e (V) 4 G = 20 g g a a olt 3 olt 3 V V ut ut G = 100 p p ut 2 ut 2 O O G = 1 1 1 G = 200 AV = DV = 5.5V G = 2 AV = DV = 5.5V DD DD DD DD 0 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure42. Figure43. SMALL-SIGNALOVERSHOOT vsLOADCAPACITANCE GAINvsSETTLINGTIME 50 12 C = 100pF//R = 10kW L L 40 10 VOUT= 4VPP G = 1 0.01% ot (%) 30 mme (s) 8 sho G>2 g Ti 6 Over 20 ettlin 4 0.1% S 10 2 0 0 0 100 200 300 400 500 600 700 800 0 50 100 150 200 Load Capacitance (pF) Gain Figure44. Figure45. INPUTON-CHANNELCURRENT INPUTOFF-CHANNELLEAKAGECURRENT vsTEMPERATURE vsTEMPERATURE 25 Measurement made with channel pin nA) 25 Measurement made with channel pin 0.15 Input On-Channel Current (nA) 21105050 connected to midsupply CCCHHH019 to annel 0 Input Off-Channel Current ( 21105050 connected to midsCupHp0ly CCHH19 to 000--00..10..000551 Input Off-Channel Current (nA)Channel 1 to Channel 9 -5 Ch -5 -0.15 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure46. Figure47. Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L POWER-SUPPLYREJECTIONRATIO vsFREQUENCY CROSSTALKvsFREQUENCY 110 140 100 G = 1 130 90 120 80 R (dB) 7600 G³2 G = 5G0 = 200 alk (dB) 111000 R 50 st PS 40 Cros 90 30 G = 2 80 20 70 10 G = 10 0 60 0.1 1 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure48. Figure49. SMALL-SIGNALPULSERESPONSE SMALL-SIGNALPULSERESPONSE G = 20 G = 10 100mV G = 1 100mV G = 50 Output Output G = 100, 200 0V 0V V /G V /G IN IN Input Input 0V 0V 2.5ms/div 2.5ms/div Figure50. Figure51. LARGE-SIGNALPULSERESPONSE LARGE-SIGNALPULSERESPONSE G = 10 G = 2 G = 50 G = 1 v Output v Output G = 100, 200 di di V/ V/ 2 2 Input Input 2.5ms/div 2.5ms/div Figure52. Figure53. 18 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 TYPICAL CHARACTERISTICS (continued) AtT =+25°C,AV =DV =5V,R =10kΩconnectedtoDV /2,V =GND,andC =100pF,unlessotherwisenoted. A DD DD L DD REF L POWER-UP/POWER-DOWNTIMING OUTPUTOVERDRIVEPERFORMANCE V IN 5V Output (1V/div) V v OUT 0V V/di 1 Supply (5V/div) V = 5V S R = 10kW 0V 0V L C = 100pF L 25ms/div 1ms/div Figure54. Figure55. OUTPUTVOLTAGEvsSHUTDOWNMODE PGA116,PGA117HARDWARESHUTDOWNMODE Active Active In Output In Shutdown Shutdown Output Output V/div V/div 2 2 Enable CS CS 10ms/div 10ms/div Figure56. Figure57. Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com SERIAL INTERFACE INFORMATION SPI Mode 0, 0 (CPOL = 0, CPHA = 0) CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK DIN DOUT SPI Mode 1, 1 (CPOL = 1, CPHA = 1) CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK DIN DOUT Figure58.SPIMode0,0andMode1,1 Table2.SPIModeSettingDescription MODE CPOL CPHA CPOLDESCRIPTION CPHADESCRIPTION 0,0 0 0(1) Clockidleslow Dataarereadontherisingedgeofclock.Datachangeonthefallingedgeofclock. 1,1 1 1(2) Clockidleshigh Dataarereadontherisingedgeofclock.Datachangeonthefallingedgeofclock. (1) CPHA=0meanssampleonfirstclockedge(risingorfalling)afteravalidCS. (2) CPHA=1meanssampleonsecondclockedge(risingorfalling)afteravalidCS. SERIAL DIGITAL INTERFACE: SPI MODES The PGA uses a standard serial peripheral interface (SPI). Both SPI Mode 0,0 and Mode 1,1 are DOUT supported, as shown in Figure 58 and described in Table2. If there are not even-numbered increments of 16 clocks (that is, 16, 32, 64, and so forth) between CS DIN going low (falling edge) and CS going high (rising edge), the device takes no action. This condition 10mA PGA116 provides reliable serial communication. Furthermore, PGA117 this condition also provides a way to quickly reset the SPI interface to a known starting condition for data synchronization. Transmitted data are latched Figure59.DigitalI/OStructure—PGA116/PGA117 internallyontherisingedgeofCS. On the PGA116/PGA117, CS, DIN, and SCLK are Schmitt-triggeredCMOS logic inputs. DIN has a weak internal pull-down to support daisy-chain communications on the PGA116/PGA117. DOUT is a CMOS logic output. When CS is high, the state of DOUT is high-impedance. When CS is low, DOUT is drivenasillustratedinFigure59. 20 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 On the PGA112/PGA113, there are digital output and used (see Table 4) to ensure that data are written or digital input gates both internally connected to the read in the proper sequence. There is a special DIO pin. DIN is an input-only gate and DOUT is a daisy-chain NOP command (No OPeration) which, digital output that can give a 3-state output. The DIO when presented to the desired device in the pin has a weak 10m A pull-down current source to daisy-chain, causes no changes in that respective prevent the pin from floating in systems with a device. Detailed timing diagrams for daisy-chain high-impedance SPI DOUT line. When CS is high, operationareshowninFigure65throughFigure67. the state of the internal DOUT gate is high-impedance. When CS is low, the state of DIO depends on the previous valid SPI communication; CS SCLK either DIO becomes an output to clock out data or it DOUT remains an input to receive data. This structure is MSP430 DIN PGA116/PGA117 PGA116/PGA117 showninFigure60. CS U1 CS U2 SCLK SCLK DIN1 DOUT1 DIN2 DOUT2 DOUT DIO Figure61.Daisy-ChainRead/WriteConfiguration The PGA112/PGA113 can be used as the last device in a daisy-chain as shown in Figure 62 if write-only communication is acceptable, because the DIN PGA112/PGA113 have no separate DOUT pin to 10mA connect back to the microcontroller DIN pin in order PGA112 toreadbackdatainthisconfiguration. PGA113 CS Figure60.DigitalI/OStructure—PGA112/PGA113 SCLK DOUT DIN PGA116/PGA117 PGA112/PGA113 MSP430 CS U1 CS U2 SERIAL DIGITAL INTERFACE: SPI SCLK SCLK DIN1 DOUT1 DIO DAISY-CHAIN COMMUNICATIONS To reduce the number of I/O port pins used on a microcontroller, the PGA116/PGA117 support SPI Figure62.Daisy-ChainWrite-OnlyConfiguration daisy-chain communications with full read/write capability. A two-device daisy-chain configuration is shown in Figure 61, although any number of devices can be daisy-chained. The SPI daisy-chain communication uses a common SCLK and CS line for all devices in the daisy chain, rather than each device requiring a separate CS line. The daisy-chain mode of communication routes data serially through each device in the chain by using its respective DIN and DOUT pins as shown. Special commands are Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com The maximum SCLK frequency that can be used in daisy-chain operation is directly related to SCLK t t rise/fall times, DIN setup time, and DOUT 10RnFIs 10RnFIs propagation delay. Any number of two or more devices have the same limitations because it is the timing considerations between adjacent devices that limittheclockspeed. SCLK Figure 63 analyzes the maximum SCLK frequency for daisy-chain mode based on the circuit of Figure 61. A clock rise and fall time of 10ns is assumed to allow for extra bus capacitance that could occur as a result ofmultipledevicesinthedaisy-chain. t DO 25ns DOUT1 t SU 10ns DIN2 t = 55ns t = 55ns MIN MIN SCLK = 9.09MHz MAX Figure63.Daisy-ChainMaximumSCLK Frequency 22 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 SPI SERIAL INTERFACE Hi-Z Hi-Z 2829303132 G0CH3CH2CH1CH0DD4D2D10D3 2233389012 G0CCH2CH1CH0H3D0D4D3D2D1 27 G1D5 27 G1D5 26 G2D6 26 G2D6 25 G3D7 25 G3D7 24 0D8 24 0D8 23 0D9 23 0D9 202122 000D12D10D11 221220 000D12D11D10 19 0D13 19 0D13 1718 00D15D14 1718 00D15D14 16 D0 16 D0 16 0 D0 16 0D0 15 D1 15 D1 15 0 D1 15 0D1 14 D2 14 D2 14 0 D2 14 0D2 13 D3 13 D3 13 0D3 13 0D3 12 D4 12 D4 12 0 D4 12 0D4 11 D5 11 D5 11 0 D5 11 0D5 Mode = 0, 0 910 D7D6 Mode = 1, 1 910 D7D6 Mode = 0, 0 910 00D7D6 Mode = 1, 1 910 00D7D6 Write, 8 D8 Write, 8 D8 Read, 8 0D8 Read, 8 0D8 SPI 7 D9 SPI 7 D9 SPI 7 1D9 SPI 7 1 D9 6 D10 Hi-Z 6 D10 Hi-Z 6 0D10 Hi-Z 6 0 D10 Hi-Z 5 D11 5 D11 5 1D11 5 1D11 4 D12 4 D12 4 0D12 4 0 D12 3 D13 3 D13 3 1D13 3 1 D13 2 D14 2 D14 2 1D14 2 1D14 1 D15 1 D15 1 0D15 1 0D15 CS CLK DIN OUT CS CLK DIN OUT CS CLK DIN OUT CS CLK DIN OUT S D S D S D S D DIOPin DIOPin DIOPin DIOPin Figure64.SPISerialInterfaceTimingDiagrams Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com 32 D0 D0 32 D0 D0 31 D1 D1 31 D1 D1 30 D2 D2 30 D2 D2 29 D3 D3 29 D3 D3 28 D4 D4 28 D4 D4 27 D5 D5 27 D5 D5 242526 D7D6D8 CommandU1 D6D7D8 CommandU2 242526 D6D8D7 CommandU1 D6D8D7 CommandU2 7 23 D9 D9 23 D9 D9 1 2 PGA116/PGA1 CSU2SCLKDOUTDIN2 0 212220 D12D10D11 D12D10D11 212220 D12D10D11 D10D12D11 PGA117 U1 DOUT1 SPIWrite,Mode=0, 171819 D13D15D14 D13D15D14 PI Write, Mode = 1,1 171819 D15D13D14 D15D13D14 PGA116/ CSSCLKDIN1 Daisy-Chain 1516 D1D0 Daisy-Chain S 1516 D1D0 14 D2 14 D2 13 D3 13 D3 SKTN CSCLDOUDI0 12 D4 12 D4 3 P4 11 D5 11 D5 S M 10 D6 10 D6 56789 D9D7D10D8D11 CommandU2 Hi-ZPulledLowbyDINWeakPull-Down 56789 D9D7DD108D11 CommandU2 PulledLowbyDINWeakPull-Down 4 D12 DOUT 4 D12 UTHi-Z O 3 D13 3 D13 D 2 D14 2 D14 1 D15 1 D15 CS SCLK DOUTDIN1 DOUT1DIN2 CS SCLK DOUTDIN1 DOUT1DIN2 Figure65.SPIDaisy-ChainWriteTimingDiagrams 24 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 32 0 0 Hi-Z 31 0 0 32 H0 30 0 0 C 31 H1 29 0 0 C 30 H2 28 0 0 C 24252627 0000 CommandU1 0000 CommandU2 2526272829 G3CH3G2G1G0 Data Byte U1 17 2 23 1 1 24 0 PGA116/PGA1 CSU2SCLKDOUTDIN2 0 212220 011 011 212223 000 e=0, 19 1 1 20 0 d PGA116/PGA117 CSU1SCLKDOUT1DIN1 Daisy-ChainSPIRead,Mo 15161718 0100 01 1718191516 CH0CH1 CH1000CH0 14 0 14 CH2 CH2 CSCLKOUTDIN 1213 00 1213 CH3G0 Data Byte U1 CH3G0 Data Byte U2 SD 30 11 G1 G1 MSP4 1011 00 10 G2 G2 wn 9 G3 G3 789 100 CommandU2 wbyDINWeakPull-Do 678 000 000 6 0 PulledLo 5 0 0 5 1 Hi-Z 4 0 0 4 1 OUT D 3 0 0 3 1 2 0 0 2 1 1 0 0 1 0 CS SCLK DOUTDIN1 DOUT1DIN2 CS SCLK DOUT1DIN2 DOUT2DIN Figure66.SPIDaisy-ChainReadTimingDiagram(Mode0,0) Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com 32 0 0 Hi-Z 31 0 0 32 H0 30 0 0 C 31 H1 29 0 0 C 30 H2 28 0 0 C 24252627 0000 CommandU1 0000 CommandU2 2526272829 G3CH3G2G1G0 Data Byte U1 17 2 23 1 1 24 0 PGA116/PGA1 CSU2SCLKDOUTDIN2 1 212220 011 110 212223 000 e=1, 19 1 1 20 0 d PGA116/PGA117 CSU1SCLKDOUT1DIN1 Daisy-ChainSPIRead,Mo 15161718 0100 10 1718193132 CH0CH1 000CH0CH1 14 0 30 CH2 CH2 CSCLKOUTDIN 1213 00 2829 CH3G0 Data Byte U1 CH3G0 Data Byte U2 SD 30 27 G1 G1 MSP4 1011 00 wn 2526 G3G2 G3G2 789 100 CommandU2 wbyDINWeakPull-Do 222324 000 000 6 0 PulledLo 21 0 0 5 1 Hi-Z 20 0 0 4 1 DOUT 19 0 0 3 1 18 0 0 2 1 17 0 0 1 0 CS SCLK DOUTDIN1 DOUT1DIN2 CS SCLK DOUT1DIN2 DOUT2DIN Figure67.SPIDaisy-ChainReadTimingDiagram(Mode1,1) 26 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 SPI COMMANDS Table3.SPICommands(PGA112/PGA113)(1)(2) THREE-WIRE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SPICOMMAND 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 READ 0 0 1 0 1 0 1 0 G3 G2 G1 G0 CH3 CH2 CH1 CH0 WRITE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOPWRITE SDN_DIS 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 WRITE 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 SDN_ENWRITE (1) SDN=Shutdownmode.EnterShutdownmodebyissuinganSDN_ENcommand.Shutdownmodeiscleared(returnedtothelastvalid writeconfiguration)byaSDN_DIScommandorbyanyvalidWritecommand. (2) POR(Power-on-Reset)valueofinternalGain/ChannelSelectRegisterisall0s;thisvaluesetsGain=1,andChannel=V /CH0. CAL Table4.SPIDaisy-ChainCommands(1)(2) DAISY-CHAIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 NOP 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 SDN_DIS 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 SDN_EN 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 READ 0 0 1 1 1 0 1 0 G3 G2 G1 G0 CH3 CH2 CH1 CH0 WRITE (1) SDN=ShutdownMode.ShutdownModeisenteredbyanSDN_ENcommand.ShutdownModeiscleared(returnedtothelastvalid writeconfiguration)byaSDN_DIScommandorbyanyvalidWritecommand. (2) POR(Power-on-Reset)valueofinternalGain/ChannelRegisterisall0s;thisvaluesetsGain=1,V /CH0selected. CAL Table5.GainSelectionBits(PGA112/PGA113) G3 G2 G1 G0 BINARYGAIN SCOPEGAIN 0 0 0 0 1 1 0 0 0 1 2 2 0 0 1 0 4 5 0 0 1 1 8 10 0 1 0 0 16 20 0 1 0 1 32 50 0 1 1 0 64 100 0 1 1 1 128 200 Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com Table6.MuxChannelSelectionBits CH3 CH2 CH1 CH0 PGA112,PGA113 PGA116,PGA117 0 0 0 0 VCAL/CH0 VCAL/CH0 0 0 0 1 CH1 CH1 0 0 1 0 X(1) CH2 0 0 1 1 X CH3 0 1 0 0 X CH4 0 1 0 1 X CH5 0 1 1 0 X CH6 0 1 1 1 X CH7 1 0 0 0 X CH8 1 0 0 1 X CH9 1 0 1 0 X X(1) 1 0 1 1 FactoryReserved FactoryReserved 1 1 0 0 CAL1(2) CAL1(2) 1 1 0 1 CAL2(3) CAL2(3) 1 1 1 0 CAL3(4) CAL3(4) 1 1 1 1 CAL4(5) CAL4(5) (1) X=channelisnotused. (2) CAL1:connectstoGND. (3) CAL2:connectsto0.9V . CAL (4) CAL3:connectsto0.1V . CAL (5) CAL4:connectstoV . REF 28 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 APPLICATION INFORMATION PMOS transistors. The result of this transition FUNCTIONAL DESCRIPTION appears as a small input offset voltage transition that is reflected to the output by the selected PGA gain. The PGA112/PGA113 and PGA116/PGA117 are This transition may be either increasing or single-ended input, single-supply, programmable gain decreasing, and differs from part to part as described amplifiers (PGAs) with an input multiplexer. in Figure 69 and Figure 70. These figures illustrate Multiplexer channel selection and gain selection are possible differences in input offset voltage between done through a standard SPI interface. The two different devices when used with AV = +5V. PGA112/PGA113 have a two-channel input MUX and DD Because the exact transition region varies from the PGA116/PGA117 have a 10-channel input MUX. device to device, the Electrical Characteristics table The PGA112 and PGA116 provide binary gain specifies an input offset voltage above and below this selections (1, 2, 4, 8, 16, 32, 64, 128) and the inputtransitionregion. PGA113 and PGA117 provide scope gain selections (1, 2, 5, 10, 20, 50, 100, 200). All models use a AV split-supply architecture with an analog supply, AV , DD DD and a digital supply, DV . This split-supply Reference DD Current architecture allows for ease of interface to analog-to-digital converters (ADCs) and microcontrollers in mixed-supply voltage systems, such as where the analog supply is +5V and the digital supply is +3V. Four internal calibration VIN+ VIN- channels are provided for system-level calibration. The channels are tied to GND, 0.9V , 0.1V , and CAL CAL V , respectively. V , an external voltage REF CAL connected to V /CH0, acts as the system CAL calibration reference. If V is the system ADC CAL reference, then gain and offset calibration on the ADC are easily accomplished through the PGA using only one MUX input. If calibration is not used, then GND V /CH0 can be used as a standard MUX input. All CAL four versions provide a V pin that can be tied to REF Figure68.PGARail-to-RailInputStage ground or, for ease of scaling, to midsupply in single-supply systems where midsupply is used as a virtual ground. The PGA112/PGA113 offer a 80 software-controlled shutdown feature for low standby power. The PGA116/PGA117 offer both hardware- 70 and software-controlled shutdown for low standby V) 60 m power. The PGA112/PGA113 have a three-wire SPI e ( digital interface; the PGA116/PGA117 have a ag 50 four-wire SPI digital interface. The PGA116/117 also Volt 40 havedaisy-chaincapability. set Off 30 ut OP AMP: INPUT STAGE p 20 n I The PGA op amp is a rail-to-rail input and output 10 AV = 5V (RRIO) single-supply op amp. The input topology DD 0 uses two separate input stages in parallel to achieve 0 1 2 3 4 5 6 rail-to-rail input. As Figure 68 shows, there is a Input Voltage (V) PMOS transistor on each input for operation down to ground; there is also an NMOS transistor on each Figure69.V versusInputVoltage—Case1 OS input in parallel for operation to the positive supply rail. When the common-mode input voltage (that is, the single-ended input, because this PGA is configured internally for noninverting gain) crosses a level that is typically about 1.5V below the positive supply, there is a transition between the NMOS and Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com 50 CH0 PGA112 40 AVDD= 5V CH1 MUX PGA113 V) 30 V RI VOUT m IN0 V ge ( 20 IN1 VREF RF a et oltV 10 VS/2 +- G = 1 s Off 0 ut p -10 n I Figure72.PGA112/PGA113Configurationfor -20 PositiveandNegativeExcursionsAround -30 MidsupplyVirtualGround 0 1 2 3 4 5 6 V = G´V -AV /2´(G-1) Input Voltage (V) OUT0 IN0 DD (2) When:G=1 Figure70.V versusInputVoltage—Case2 OS Then:V =G×V OUT0 IN0 OP AMP: GENERAL GAIN EQUATIONS V = G´(V + AV /2)-AV /2´(G-1) OUT1 IN1 DD DD Figure 71 shows the basic configuration for using the V = G´V +AV /2, where:-AV /2 < G´V < +AV /2 OUT1 IN1 DD DD IN1 DD PGA as a gain block. V /V is the selected OUT IN (3) noninverting gain, depending on the model selected, foreitherbinaryorscopegains. Where: G=1,2,4,8,16,32,64,and128(binarygains) G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope CH1 gains) RI VOUT Table 7 details the internal typical values for the op V amp internal feedback resistor (R ) and op amp IN F VREF RF internal input resistor (RI) for both binary and scope gains. G = 1 Table7.TypicalR andR versusGain F I Binary Scope Gain Gain Figure71.PGAUsedasaGainBlock (V/V) R (Ω) R (Ω) (V/V) R (Ω) R (Ω) F I F I V = G´V 1 0 3.25k 1 0 3.25k OUT IN (1) 2 3.25k 3.25k 2 3.25k 3.25k Where: 4 9.75k 3.25k 5 13k 3.25k G=1,2,4,8,16,32,64,and128(binarygains) 8 22.75k 3.25k 10 29.25k 3.25k G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope 16 48.75k 3.25k 20 61.75k 3.25k gains) 32 100.75k 3.25k 50 159.25k 3.25k Figure 72 shows the PGA configuration and gain 64 204.75k 3.25k 100 321.75k 3.25k equations for V = AV /2. V is V when REF DD OUT0 OUT 128 412.75k 3.25k 200 646.75k 3.25k CH0 is selected and V is V when CH1 is OUT1 OUT selected. Notice the V pin has no effect for G = 1 REF because the internal feedback resistor, R , is shorted F out. This configuration allows for positive and negative voltage excursions around a midsupply virtualground. 30 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 OP AMP: FREQUENCY RESPONSE VERSUS ANALOG MUX GAIN The analog input MUX provides two input channels Table 8 documents how small-signal bandwidth and for the PGA112/PGA113 and 10 input channels for slew rate change correspond to changes in PGA the PGA116/PGA117. The MUX switches are gain. designed to be break-before-make and thereby eliminate any concerns about shorting the two input Full power bandwidth (that is, the highest frequency signalsourcestogether. that a sine wave can pass through the PGA for a givengain)isrelatedtoslewratebyEquation4: Four internal MUX CAL channels are included in the SR (V/ms) = 2pf´V (1´10-6) analog MUX for ease of system calibration. These OP (4) CAL channels allow ADC gain and offset errors to be Where: calibrated out. This calibration does not remove the SR=SlewrateinV/m s offset and gain errors of the PGA for gains greater than 1, but most systems should see a significant f=FrequencyinHz increase in the ADC accuracy. In addition, these CAL VOP=Outputpeakvoltageinvolts channels can be used by the ADC to read the minimum and maximum possible voltages from the Example: PGA. With these minimum and maximum levels For G = 8, then SR = 10.6V/m s (slew rate rise is known, the system architecture can be designed to indicate an out-of-range condition on the measured minimumslewrate). analog input signals if these levels are ever For a 5V system, choose 0.1V < V < 4.9V or OUT measured. V =4.8VorV =2.4V. OUTPP OUTP SR(V/m s)=2p f×VOP(1×10–6). To use the CAL channels, VCAL/CH0 must be 10.6=2p f(2.4)(1×10–6)→f=702.9kHz permanently connected to the system ADC reference. There is a typical 100kΩ load from V /CH0 to This example shows that a G = 8 configuration CAL ground. Table 9 illustrates how to use the CAL can produce a 4.8V sine wave with frequency PP channelswithV = ground. Table 10 describes how up to 702.9kHz. This computation only shows the REF to use the CAL channels with V = AV /2. The theoretical upper limit of frequency for this REF DD V pin must be connected to a source that is example, but does not indicate the distortion of REF low-impedance for both dc and ac in order to the sine wave. The acceptable distortion depends maintain gain and nonlinearity accuracy. Worst-case on the specific application. As a general current demand on the V pin occurs when G = 1 guideline, maintain two to three times the REF because there is a 3.25kΩ resistor between V and calculated slew rate to minimize distortion on the OUT V . For a 5V system with AV /2 = 2.5V, the V sine wave. For this example, the application REF DD REF pinbuffer must source and sink 2.5V/3.25kΩ = 0.7mA should only use G = 8, 4.8V , up to a frequency PP minimum for a V that can swing from ground to range of 234kHz to 351kHz, depending upon the OUT +5V. acceptable distortion. For a given gain and slew rate requirement, check for adequate small-signal bandwidth (typical –3dB frequency) in order to assure that the frequency of the signal can be passedwithoutattenuation. Table8.FrequencyResponseversusGain(C =100pF,R =10kΩ) L L 0.1% 0.01% 0.1% 0.01% TYPICAL SLEW SLEW SETTLING SETTLING TYPICAL SLEW SLEW SETTLING SETTLING –3dB RATE- RATE- TIME: TIME: SCOPE –3dB RATE- RATE- TIME: TIME: BINARY FREQUENCY FALL RISE 4VPP 4VPP GAIN FREQUENCY FALL RISE 4VPP 4VPP GAIN(V/V) (MHz) (V/m s) (V/m s) (m s) (m s) (V/V) (MHz) (V/m s) (V/m s) (m s) (m s) 1 10 8 3 2 2.55 1 10 8 3 2 2.55 2 3.8 9 6.4 2 2.6 2 3.8 9 6.4 2 2.6 4 2 12.8 10.6 2 2.6 5 1.8 12.8 10.6 2 2.6 8 1.8 12.8 10.6 2 2.6 10 1.8 12.8 10.6 2.2 2.6 16 1.6 12.8 12.8 2.3 2.6 20 1.3 12.8 9.1 2.3 2.8 32 1.8 12.8 13.3 2.3 3 50 0.9 9.1 7.1 2.4 3.8 64 0.6 4 3.5 3 6 100 0.38 4 3.5 4.4 7 128 0.35 2.5 2.5 4.8 8 200 0.23 2.3 2 6.9 10 Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com +3V +3V C BYPASS CBYPASS CBYPASS 0.1mF 0.1mF 0.1mF AV DV DD DD 2.5V ADC Ref PGA112 REF3225 PGA113 V /CH0 CAL MUX Output VOUT CH1 ADC Stage CAL1 10kW R G = 1 F 0.9V MSP430 CAL CAL2 0.1V Microcontroller CAL CAL3 80kW CAL4 VREF RI SCLK SPI DIO CAL2/3 Interface CS 10kW GND V REF Figure73.UsingCALChannelswithV =Ground REF Table9.UsingtheMUXCALChannelswithV =GND REF (AV =3V,DV =3V,ADCRef=2.5V,andV =GND) DD DD REF MUX GAIN OPAMP OPAMP FUNCTION SELECT SELECT MUXINPUT (+In) (V ) DESCRIPTION OUT Minimumsignallevelthatthe MUX,opamp,andADCcan MinimumSignal CAL1 1 GND GND 50mV read.OpampV islimited OUT bynegativesaturation. 90%ADCRefforsystem 0.9× GainCalibration CAL2 1 2.25V 2.25V full-scaleorgaincalibration (V /CH0) CAL oftheADC. Maximumsignallevelthat theMUX,opamp,andADC canread.OpampV is 0.9× OUT MaximumSignal CAL2 2 2.25V 2.95V limitedbypositivesaturation. (V /CH0) CAL SystemislimitedbyADC maxinputof2.5V(ADCRef =2.5V). 0.1× 10%ADCRefforsystem OffsetCalibration CAL3 1 0.25V 0.25V (V /CH0) offsetcalibrationoftheADC. CAL Minimumsignallevelthatthe MUX,opamp,andADCcan MinimumSignal CAL4 1 V GND 50mV REF read.OpampV islimited OUT bynegativesaturation. 32 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 +3V +3V C C C BYPASS BYPASS BYPASS 0.1mF 0.1mF 0.1mF AV DV DD DD PGA112 ADC Ref PGA113 V /CH0 CAL MUX Output V CH1 OUT ADC Stage CAL1 10kW R G = 1 F 0.9VCAL CAL2 MSP430 0.1VCAL CAL3 Microcontroller 80kW CAL4 VREF RI SCLK SPI DIO CAL2/3 Interface CS 10kW GND V REF R F 10kW C F 2.7nF +3V +3V CBYPASS 0.1mF RX (1.5V) 100kW OPA364 C RY 0.1mF 0.L12mF 100kW Figure74.UsingCALChannelswithV =AV /2 REF DD Table10.UsingtheMUXCALChannelswithV =AV /2 REF DD (AV =3V,DV =3V,ADCRef=3V,andV =1.5V) DD DD REF MUX GAIN OPAMP OPAMP FUNCTION SELECT SELECT MUXINPUT (+In) (V ) DESCRIPTION OUT MinimumsignallevelthattheMUX, MinimumSignal CAL1 1 GND GND 50mV opamp,andADCcanread.Opamp V islimitedbynegativesaturation. OUT 0.9× 90%ADCRefforsystemfull-scaleor GainCalibration CAL2 1 2.7V 2.7V (V /CH0) gaincalibrationoftheADC. CAL MaximumsignallevelthattheMUX, 0.9× MaximumSignal CAL2 4or5 2.25V 2.95V opamp,andADCcanread.Opamp (V /CH0) CAL V islimitedbypositivesaturation. OUT 0.1× 10%ADCRefforsystemoffset OffsetCalibration CAL3 1 0.3V 0.3V (V /CH0) calibrationoftheADC. CAL V Check CAL4 1 V 1.5V 1.5V MidsupplyvoltageusedasV . REF REF REF Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com SYSTEM CALIBRATION USING THE PGA In practice, the zero input (0V) or full-scale input Analog-to-digital converters (ADCs) contain two major (VREF_ADC – 1LSB) of ADCs cannot always be errors that can be easily removed by calibration at a measured because of internal offset error and gain system level. These errors are gain error and offset error.However,ifmeasurementsaremadeveryclose error, as shown in Figure 75. Figure 75 shows a to the full-scale input and the zero input, both zero typical transfer function for a 12-bit ADC. The analog and full-scale can be calibrated very accurately with input is on the x-axis with a range from 0V to the assumption of linearity from the calibration points (V – 1LSB), where V is the ADC to the desired end points of the ADC ideal transfer REF_ADC REF_ADC reference voltage. The y-axis is the hexadecimal function. For the zero calibration, choose equivalent of the digital codes that result from ADC 10%VREF_ADC; this value should be above the internal conversions. The dotted red line represents an ideal offset error and sufficiently out of the noise floor transfer function with 0000h representing 0V analog range of the ADC. For the gain calibration, choose input and 0FFFh representing an analog input of 90%VREF_ADC; this value should be less than the (V – 1LSB). The solid blue line illustrates the internal gain error and sufficiently below the tolerance REF_ADC offset error. Although the solid blue line includes both of VREF. These key points can be summarized in this offset error and gain error, at an analog input of 0V way: the offset error voltage, VZ_ACTUAL, can be measured. Forzerocalibration: Thedashedblacklinerepresentsthetransferfunction • The ADC cannot read the ideal zero because of with gain error. The dashed black line is equivalent to offseterror the solid blue line without the offset error, and can be • Must be far enough above ground to be above measured and computed using V and Z_ACTUAL noisefloorandADCoffseterror V . The difference between the dashed black Z_IDEAL line and the dotted red line is the gain error. Gain and • Therefore, choose 10%V for zero REF_ADC offset error can be computed by taking zero input and calibration full-scale input readings. Using these error Forgaincalibration: calculations, compute a calibrated ADC reading to • The ADC cannot read the ideal full-scale because removetheADCgainandoffseterror. ofgainerror • Must be far enough below full-scale to be below VFS_ACTUAL theV toleranceandADCgainerror REF 0FFFh Gain Error • Therefore, choose 90%VREF_ADC for gain calibration VFS_IDEAL Transfer Function with Offset Error + Gain Error Transfer Function with Gain Error Only Digital Output Ideal Transfer Function VZ_ACTUAL 0000h Offset Error VZ_IDEAL 0V Analog Input VREF_ADC-1LSB Figure75.ADCOffsetandGainError 34 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 The 12-bit ADC example in Figure 76 illustrates the V 90 = 0.9(V ) REF REF_ADC (5) technique for calibrating an ADC using a V 10 = 0.1(V ) 10%V and 90%V reading where REF REF_ADC (6) REF_ADC REF_ADC VREF_ADC is the ADC reference voltage. Note that the VMEAS90 = ADCMEASUREMENTat VREF90 (7) 10%VREF reading also contains a gain error because VMEAS10 = ADCMEASUREMENTat VREF10 (8) it is not a V = 0 calibration point. First, use the IN 90%V and 10%V points to compute the 2. Compute the ADC measured gain. The slope of REF REF measuredgainerror.Themeasuredgain error is then the curve connecting the measured 10%VREF and used to remove the gain error from the 10%VREF measured 90%VREF point is computed and reading, giving a measured 10%V number. The compared to the slope between the ideal REF measured 10%VREF number is used to compute the 10%VREF and ideal 90%VREF. This result is the measuredoffseterror. measuredgain. V 90-V 10 G = MEAS MEAS MEAS V 90-V 10 VREF= +5V REF REF (9) Offset Error = +4LSB 0FFFh (4.99878V) Gain Error = +6LSB (4.5114751443V) 3. Compute the ADC measured offset. The measured offset is computed by taking the difference between the measured 10%V and REF Digital Output (V)AD_MEAS with OTffrsaents Eferrr oFru +n cGtiaoinn ErIrdoeral Transfer Function 4. CthVOoeAmMD(Ei_pdAMuSeEtAa=eSl Vt=1hM0 eAE%AncSVya1 lR0VibEI-FrNa)A(t×VeDRd(CEmFAM1eDE0aACSs´UuRrGreEeMaMdEEdNAigTSna)gisn.). ((1101)) V -O AD_MEAS MEAS V = ADC_CAL G MEAS (12) (0.5056191443V) Any ADC reading can therefore be calibrated by 0000h (0V) removing the gain error and offset error. The 0V 0(0.5.1V´VREF_ADC) VIN (0.9´VREF_4A.D5CV) 4(V.9R9E8F_7A8DVC-1LSB) measured offset is subtracted from the ADC reading and then divided by the measured gain to give a Figure76.12-BitExampleofADCCalibrationfor corrected reading. If this calibration is performed on a GainandOffsetError timed basis, relative to the specific application, gain and offset error over temperature are also removed The gain error and offset error in ADC readings can fromtheADCreadingbycalibration. be calibrated by using 10%V and REF_ADC Forexample;given: 90%V calibration points. Because the REF_ADC • 12-BitADC calibration is ratiometric to V , the exact value of V does not need tRoEFb_eADCknown in the end • ADCGainError=+6LSB REF_ADC application. • ADCOffsetError=+4LSB • ADCReference(V )=+5V Follow these steps to compute a calibrated ADC REF_ADC reading: • Temperature=+25°C 1. Take the ADC reading at VIN = 90% × VREF and Table11showstheresultingsystemaccuracy. V = 10% × V . The ADC readings for IN REF 10%V and90%V aretaken. REF REF Table11.BitsofSystemAccuracy(1)(to0.5LSB) ADCACCURACYWITHOUT ADCACCURACYWITHPGA112 V CALIBRATION CALIBRATION IN 10%V 8.80Bits 12.80Bits REF_ADC 90%V 7.77Bits 11.06Bits REF_ADC (1) DifferenceinmaximuminputoffsetvoltageforV =10%V andV =90%V isthereasonfordifferentaccuracies. IN REF_ADC IN REF_ADC Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com APPLICATIONS: GENERAL-PURPOSE INPUT Table 12 summarizes the scaling resistor values for SCALING R , R , and R for different ADC Ref voltages. A X B V is the reference voltage used for the ADC Figure 77 is an example application that REF_ADC connected to the PGA112/PGA113 output. It is demonstrates the flexibility of the PGA for assumed the ADC input range is 0V to V . The general-purpose input scaling. V is a ±100mV input REF_ADC IN0 Bipolar Input to Single-Supply Scaling section gives that is ac-coupled into CH0. The PGA112/PGA113 is the algorithm to compute resistor values for powered from a +5V supply voltage, V , and S references not listed in Table 12. As a general configured with the V pin connected to V /2 REF S guideline, R should be chosen such that the input (+2.5V). V is the ±100mV input, level-shifted and B CH0 on-channel current multiplied by R is less than or centered on V /2 (+2.5V). A gain of 20 is applied to B S equal to the input offset voltage. This value ensures CH0, and because of the PGA113 configuration, the that the scaling network contributes no more error output voltage at V is ±2V centered on V /2 OUT S than the input offset voltage. Individual applications (+2.5V). mayrequireotherdesigntrade-offs. CH1 is set to G = 1; through a resistive divider and scalar network, we can read ±5V or 0V. This setting provides bipolar to single-ended input scaling. VIN0 VCH0 +2.6V +100mV +2.5V 0 -100mV CA +2.4V V OUT0 V PGA112 V IN0 S +4.5V 200mV PGA113 (+5V) PP CH0 AV +2.5V DD RA CH1 MUX DVDD +0.5V RI G = 20 VOUT VREF VOUT1 VREF_ADC RF +4.9625V V /2 + S (+2.5V) - +37.5mV R X G = 1 R A VIN1 RB Figure77.General-PurposeInputScaling 36 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 Table12.BipolartoSingle-EndedInputScaling(1)(2) V (V) V (V) CH1INPUT R (kΩ) R (Ω) R (kΩ) REF_ADC IN1 A X B 2.5 –5 0.047613 9.2 4.81k 10 0 1.247613 5 2.447613 2.5 –10 0.050317 3.16 2.4k 10 0 1.250317 10 2.450317 3 –5 0.058003 13.5 5.76k 10 0 1.498003 5 2.938003 3 –10 0.059303 4.02 2.87k 10 0 1.499303 10 2.939303 4.096 –5 0.082224 37 7.87k 10 0 2.048304 5 4.014384 4.096 –10 0.086018 6.49 3.92k 10 0 2.052098 10 4.018178 5 –5 0.093506 24 965 10 0 2.493506 5 4.893506 5 –10 0.095227 9.2 4.81k 10 0 2.495227 10 4.895227 (1) Scalingisbasedon0.02(V )to0.98(V ),usingstandard0.1%resistorvalues. REF_ADC REF_ADC (2) AssumessymmetricalV andsymmetricalscalingforCH1inputminimumandmaximum. IN Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com BipolarInputtoSingle-SupplyScaling 2´R ´g B R = Note that this process assumes a symmetrical V A 1-g IN1 and that symmetrical scaling is used for CH1 input minimum and maximum values. The following steps 2´10kW´0.315789474 9.23077kW= give the algorithm to compute resistor values for 1-0.315789474 referencesnotlistedinTable12. d. R can now be computed from the starting value X Step1:Choosethefollowing: ofR andthecomputedvalueforR . B A R ´R a. VREF_ADC=2.5V(ADCreferencevoltage) R = B A b. |V |=5 X R + R IN1 B A (magnitudeofVIN,assumingscalingisfor±VIN1) 10kW´9.23077kW 4.81kW= c. Choose RB as a standard resistor value. The 10kW+ 9.23077kW input on-channel current multiplied by R should B be less than the input offset voltage, such that R B isnotamajorsourceofinaccuracy. + V REF_ADC RreBsis=tors1)0kΩ (select as a starting value for (2.5V) R R4.X81kW B d. For the most negative V , choose the 10kW CH1 Input IN1 (2.447817V, percentage (in decimal format) of VREF_ADC 0.0474093V) desiredattheADCinput. VIN1 RA (+5V,-5V) 9.2kW k =0.02 VO– (CH1input=k ×V whenV =–V ) VO– REF_ADC IN1 IN1 e. ForthemostpositiveV ,choosethepercentage Figure78.BipolartoSingle-EndedInput IN1 (in decimal format) of V desired at the Algorithm REF_ADC ADC input. Since this scaling is based on symmetry, k must be the same percentage APPLICATIONS: HIGH GAIN/WIDE VO+ away from V at the upper limit as at the BANDWIDTH CONSIDERATIONS REF_ADC lowerlimitwherek iscomputed. VO– As a result of the combination of wide bandwidth and k =1–k high gain capability of the PGA112/PGA113 and VO+ VO– PGA116/PGA117, there are several printed circuit k =1–0.02=0.98 VO+ board (PCB) design and system recommendations to (CH1input=k ×V whenV =+V ) considerforoptimumapplicationperformance. VO+ REF_ADC IN1 IN1 1. Power-supply bypass. Bypass each Step2:Computethefollowing: power-supply pin separately. Use a ceramic a. To simplify analysis, create one constant called capacitor connected directly from the k . VO power-supply pin to the ground pin of the IC on k = k -k VO VO+ VO- the same PCB plane. Vias can then be used to 0.96 = 0.98-0.02 connect to ground and voltage planes. This configuration keeps parasitic inductive paths out b. A constant, g, is created to simplify resistor value of the local bypass for the PGA. Good analog computations. design practice dictates the use of a large value k ´V VO REF_ADC tantalum bypass capacitor on the PCB for each g = 2´|V |-k ´V respectivevoltage. IN1 VO REF_ADC 0.96´2.5 0.315789474 = 2´5-0.96´2.5 c. R is now selected from the starting value of R A B andthegconstant. 38 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 www.ti.com............................................................................................................................................ SBOS424B–MARCH2008–REVISEDSEPTEMBER2008 2. Signal trace routing. Keep V and other low Bypass capacitors greater than 100pF are OUT impedance traces away from MUX channel inputs recommended. Lower impedances and a bypass that are high impedance. Poor signal routing can capacitor placed directly at the input MUX cause positive feedback, unwanted oscillations, channels keep crosstalk between channels to a or excessive overshoot and ringing on minimum as a result of parasitic capacitive step-changing signals. If the input signals are coupling from adjacent PCB traces and pin-to-pin particularly noisy, separate MUX input channels capacitance. with guard traces on either side of the signal traces. Connect the guard traces to ground near APPLICATIONS: DRIVING/INTERFACING TO the PGA and at the signal entry point into the ADCS PCB. On multilayer PCBs, ensure that there are CDAC SAR ADCs contain an input sampling no parallel traces near MUX input traces on capacitor, C , to sample the input signal during a adjacent layers; capacitive coupling from other SH sample period as shown in Figure 79. After the layers can be a problem. Use ground planes to sample period, C is removed from the input signal. isolate MUX input signal traces from signal traces SH Subsequentcomparisonsofthechargestored on C onotherlayers. SH are performed during the ADC conversion process. Additionally, group and route the digital signals To achieve optimal op amp stability, input signal into the PGA as far away as possible from the settling, and the demands for charge from the input analog MUX input signals. Most digital signals signal conditioning circuitry, most ADC applications are fast rise/fall time signals with low-impedance are optimized by the use of a resistor (R ) and FILT drive capability that can easily couple into the capacitor (C ) filter placed between the op amp FILT high-impedance inputs of the input MUX output and ADC input. For the PGA112/PGA113, or channels. This coupling can create unwanted the PGA116/PGA117, setting C = 1nF and R = FILT FILT noisethatgainsuptoV . 100Ω yields optimum system performance for OUT 3. Input MUX channels and source impedance. sampling converters operating at speeds up to Input MUX channels are high-impedance; when 500kHz, depending upon the application settling time combined with high gain, the channels can pick andaccuracyrequirements. up unwanted noise. Keep the input signal sources low-impedance (< 10kΩ). Also, consider bypassing input MUX channels with a ceramic bypass capacitor directly at the MUX input pin. +3V +5V C C C BYPASS BYPASS BYPASS 0.1mF 0.1mF 0.1mF AV DV DD DD 1 10 PGA112 PGA113 VCAL/CCHH01 32 MUX (MSOP-10) OSutatpguet 5 VOUT 1R0F0ILWT CSH CAL1 CFILT 40pF 10kW G = 1 RF (1nF) CDAC SAR 0.9VCAL CAL2 ADC 0.1V CAL CAL3 80kW CAL4 VREF RI 7 SCLK SPI 8 DIO CAL2/3 Interface 9 CS 10kW 6 4 12-Bit Settling®500kHz GND VREF 16-Bit Settling®300kHz Figure79.Driving/InterfacingtoADCs Copyright©2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PGA112,, PGA113 PGA116, PGA117 SBOS424B–MARCH2008–REVISEDSEPTEMBER2008............................................................................................................................................ www.ti.com POWER SUPPLIES At initial power-on, the state of the PGA is G = 1 and Channel0active.CAUTION:For most applications, Figure 80 shows a typical mixed-supply voltage set AV ≥ DV to prevent V from driving system where the analog supply, AV , is +5V and DD DD OUT DD current into AV and raising the voltage level of the digital supply voltage, DV , is +3V. The analog DD DD AV . output stage of the PGA and the SPI interface digital DD circuitry are both powered from DV . When DD SHUTDOWN AND POWER-ON-RESET (POR) considering the power required for DV , use the DD Electrical Characteristics table and add any load The PGA112/PGA113 have a software shutdown current anticipated on V ; this load current must be mode, and the PGA116/PGA117 offer both a OUT provided by DV . This split-supply architecture hardware and software shutdown mode. When the DD ensures compatible logic levels with the PGA is shut down, it goes into a low-power standby microcontroller. It also ensures that the PGA output mode. The Electrical Characteristics table details the cannot run the input for the onboard ADC into an current draw in shutdown mode with and without the overvoltage condition; this condition could cause SPI interface being clocked. In shutdown mode, R F device latch-up and system lock-up, and require andR remainconnectedbetweenV andV . I OUT REF power-supply sequencing. Each supply pin should be individually bypassed with a 0.1m F ceramic capacitor When DVDD is less than 1.6V, the digital interface is disabled and the channel and gain selections are directly at the device to ground. If there is only one held to the respective POR states of Gain = 1 and power supply in the system, AV and DV can both DD DD Channel = V /CH0. When DV is above 1.8V, the be connected to the same supply; however, it is CAL DD digital interface is enabled and the POR gain and recommended to use individual bypass capacitors channel states remain unchanged until a valid SPI directly at each respective supply pin to a single point communicationisreceived. ground. V is diode-clamped to AV (as shown in OUT DD Figure 80); therefore, set DV less than or equal to DD AV + 0.3V. DV and AV must be within the DD DD DD operatingvoltagerangeof+2.2Vto+5.5V. +3V +5V AV DV DD DD PGA112 1 10 MSP430 PGA113 Microcontroller (MSOP-10) 3 V /CH0 MUX CAL 2 Output 5 V CH1 Stage OUT ADC CAL1 10kW G = 1 RF 0.9V CAL CAL2 0.1V CAL CAL3 80kW CAL4 VREF RI 7 SCLK SPI 8 DIO Interface CAL2/3 9 CS 10kW 6 4 GND V REF Figure80.SplitPower-SupplyArchitecture:AV ≠DV DD DD 40 SubmitDocumentationFeedback Copyright©2008,TexasInstrumentsIncorporated ProductFolderLink(s):PGA112PGA113 PGA116 PGA117

PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) PGA112AIDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 P112 & no Sb/Br) CU NIPDAUAG PGA112AIDGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 P112 & no Sb/Br) PGA112AIDGST ACTIVE VSSOP DGS 10 250 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 P112 & no Sb/Br) CU NIPDAUAG PGA112AIDGSTG4 ACTIVE VSSOP DGS 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 P112 & no Sb/Br) PGA113AIDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 P113 & no Sb/Br) PGA113AIDGSRG4 ACTIVE VSSOP DGS 10 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 P113 & no Sb/Br) PGA113AIDGST ACTIVE VSSOP DGS 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 P113 & no Sb/Br) PGA113AIDGSTG4 ACTIVE VSSOP DGS 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 P113 & no Sb/Br) PGA116AIPW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PGA116 & no Sb/Br) PGA116AIPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PGA116 & no Sb/Br) PGA116AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PGA116 & no Sb/Br) PGA117AIPW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PGA117 & no Sb/Br) PGA117AIPWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PGA117 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2015 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2014 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) PGA112AIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 PGA112AIDGST VSSOP DGS 10 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PGA112AIDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 PGA113AIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 PGA113AIDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 PGA116AIPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PGA117AIPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2014 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) PGA112AIDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 PGA112AIDGST VSSOP DGS 10 250 366.0 364.0 50.0 PGA112AIDGST VSSOP DGS 10 250 195.0 200.0 45.0 PGA113AIDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 PGA113AIDGST VSSOP DGS 10 250 195.0 200.0 45.0 PGA116AIPWR TSSOP PW 20 2000 367.0 367.0 38.0 PGA117AIPWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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