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PE4250MLI-Z产品简介:
ICGOO电子元器件商城为您提供PE4250MLI-Z由Peregrine设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 PE4250MLI-Z价格参考。PeregrinePE4250MLI-Z封装/规格:RF 开关, RF Switch IC General Purpose SPDT 3GHz 50Ohm 8-MSOP。您可以下载PE4250MLI-Z参考资料、Datasheet数据手册功能说明书,资料中有PE4250MLI-Z 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | |
描述 | IC RF SWITCH SPDT 50 OHM 8-MSOP |
产品分类 | |
IIP3 | 59dBm |
品牌 | Peregrine Semiconductor |
数据手册 | |
产品图片 | |
P1dB | 30.5dBm (标准) IP1dB |
产品型号 | PE4250MLI-Z |
RF类型 | 通用 |
rohs | 无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | UltraCMOS®,HaRP™ |
供应商器件封装 | 8-MSOP |
其它名称 | 1046-1017-1 |
包装 | 剪切带 (CT) |
封装/外壳 | 8-VSSOP,8-MSOP(0.118",3.00mm 宽) |
工作温度 | -40°C ~ 85°C |
拓扑 | 反射 |
插损@频率 | 0.75dB @ 3GHz |
标准包装 | 1 |
特性 | 直流隔离,单双线路控制 |
电压-电源 | 3 V ~ 3.6 V,4.5 V ~ 5.5 V |
电路 | SPDT |
阻抗 | 50 欧姆 |
隔离@频率 | 40dB @ 3GHz (标准) |
频率 -上 | 3GHz |
频率 -下 | 10MHz |
Product Specification PE4250 SPDT UltraCMOS™ RF Switch Product Description 10 – 3000 MHz, Reflective The PE4250 is a HaRP™-enhanced Reflective SPDT (single Features pole double throw) RF Switch for use in general switching • HaRP-Technology Enhanced applications and mobile infrastructure. This device offers a • flexible supply voltage of 3.3/5V, single-pin or complementary Low Insertion Loss: 0.65 dB @ 1000 MHz pin control inputs, and 4000 V ESD tolerance. It presents a • High Isolation: 51 dB @ 1000 MHz simple alternative solution to pin diode and mechanical relay • switches. P1dB typical: +30.5 dBm • IIP3 typical: +59 dBm Peregrine’s HaRP™ technology enhancements deliver high linearity and exceptional performance. It is an innovative • Fast switching time: 150 ns feature of the UltraCMOS™ process, providing performance • Flexible supply voltage: 3.3 V ±10% or 5.0 superior to GaAs with the economy and integration of V ±10% supply (see table 3) conventional CMOS. • Excellent ESD protection: 4000 V HBM • No blocking capacitors required • Single pin or complementary control inputs Figure 1. Functional Diagram RFC Figure 2. Package Type D ES 8-lead MSOP RF1 RF2 ESD ESD CMOS Control Driver V1 V2 Table 1. Target Electrical Specifications Temp = 25°C, V = 3.3 or 5.0 V DD Parameter Conditions Min Typical Max Units Operation Frequency1 10 3000 MHz 10 MHz 0.6 0.65 dB 1000 MHz 0.65 0.70 dB Insertion Loss (RF1/RF2) 2000 MHz 0.75 0.80 dB 3000 MHz 0.75 0.90 dB 1000 MHz 50 51 dB Isolation (RFC to RF1/RF2) 2000 MHz 46 48 dB 3000 MHz 35 40 dB 1000 MHz 25 dB Return Loss 2000 MHz 23 dB 3000 MHz 20 dB Input 1 dB Compression2 50 - 3000 MHz 30.5 dBm Input IP3 50 - 3000 MHz, +18 dBm per tone, 5 MHz spacing 59 dBm Switching Time 50% CTRL to 10/90% RF 150 300 ns Notes: 1. Device linearity will begin to degrade below 10 MHz. 2. Note Absolute Maximum rating of P = 27 dBm. IN Document No. 70-0254-02 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4250 Product Specification Figure 3. Pin Configuration (Top View) Table 4. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units V2 1 8 RF2 V Power supply voltage 3 5.5 V DD V1 2 7 GND VI Voltage on any control input -0.3 5.5 V 4 25 TST Storage temperature range -65 150 °C 0 RFC 3 6 GND P RF Input power (50Ω) 27 dBm IN ESD voltage (HBM)5 4000 N/C or 4 5 RF1 VESD ESD voltage (Machine Model) 250 V GND Note: 5. Human Body Model (HBM, MIL_STD 883 Method 3015.7) Table 2. Pin Descriptions Exceeding absolute maximum ratings may cause permanent damage. Operation should be Pin No. Pin Name Description restricted to the limits in the Operating Ranges table. Operation between operating range This pin supports two interface options: Single-pin control mode. A nominal 3-volt maximum and absolute maximum for extended or 5-volt supply connection is required. periods may reduce reliability. 1 V2 Complementary-pin control mode. A complementary CMOS control signal to V1 is supplied to this pin. 2 V1 Switch control input, CMOS logic level. Latch-Up Avoidance 3 RFC RF Common port.3 Unlike conventional CMOS devices, UltraCMOS™ 4 N/C or GND No Connect or Ground devices are immune to latch-up. 5 RF13 RF1 port.3 Ground Connection. Traces should be Electrostatic Discharge (ESD) Precautions 6 GND physically short and connected to ground plane for best performance. When handling this UltraCMOS™ device, observe Ground Connection. Traces should be the same precautions that you would use with 7 GND physically short and connected to ground plane for best performance. other ESD-sensitive devices. Although this device 8 RF23 RF2 port.3 contains circuitry to protect it from damage due to Note 3. All RF pins must be DC blocked with an external ESD, precautions should be taken to avoid series capacitor or held at 0 VDC. exceeding the specified rating. Table 3. Operating Ranges Switching Frequency Parameter Min Typ Max Units The PE4250 has a maximum 25 kHz switching rate. 3.0 3.3 3.6 V V Power Supply Voltage4 DD 4.5 5.0 5.5 V Moisture Sensitivity Level I Power Supply Current The Moisture Sensitivity Level rating for the PE4250 DD VDD = VCNTL= 3.3V 55 60 µA in the 8-lead MSOP package is MSL1. V = V = 5.0V 75 80 µA DD CNTL Control Voltage High 0.8 x V V DD Control Voltage Low 0.2 x V V DD P RF Input Power (50Ω) 27 dBm IN T Operating temperature OP -40 25 85 °C range T Storage temperature range -65 25 150 °C ST Note 4. Customer must choose either 3.3 V or 5.0 V power supply range ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0254-02 │ UltraCMOS™ RFIC Solutions Page 2 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4250 Product Specification Table 5. Single-pin Control Logic Truth Table Control Logic Input Control Voltages Signal Path The PE4250 is a versatile RF CMOS switch that supports two operating control modes; single-pin Pin 1 (V2) = V DD RFC to RF1 Pin 2 (V1) = High control mode and complementary-pin control mode. Pin 1 (V2) = V DD RFC to RF2 Pin 2 (V1) = Low Single-pin control mode enables the switch to Table 6. Complementary-pin Control Logic operate with a single control pin (pin 2) supporting Truth Table a +3.3 or 5.0-volt CMOS logic input, and requires a dedicated +3.3 or 5.0-volt power supply Control Voltages Signal Path connection (pin 1). This mode of operation Pin 1 (V2 ) = Low Pin 2 (V1) = High RFC to RF1 reduces the number of control lines required and simplifies the switch control interface typically Pin 1 (V2) = High RFC to RF2 Pin 2 (V1) = Low derived from a CMOS µProcessor I/O port. Complementary-pin control mode allows the switch to operate using complementary control pins V1 and V2 (pins 2 & 1), that can be directly driven by +3.3 or 5.0-volt CMOS logic or a suitable µProcessor I/O port. This enables the PE4250 to operate in positive control voltage mode within the PE4250 operating limits. Document No. 70-0254-02 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4250 Product Specification Evaluation Kit Figure 4. Evaluation Board Layouts Peregrine specification 101/0337 The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE4250 SPDT switch. The RF common port is connected through a 50 Ω transmission line to the bottom SMA connector, J3. Port 1 and Port 2 are connected through 50 Ω transmission lines to two SMA connectors on either side of the board, J4 and J2. A through transmission line connects SMA connectors J5 and J6. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.0322”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.033”, trace gaps of 0.010”, dielectric thickness of 0.028”, copper thickness of 0.0021” and ε of 4.3. r J1 provides a means for controlling the DC inputs to the device. The second-to-bottom lower right pin (J1-3) is connected to the device V1 input. The second-to-top upper right pin (J1-7) is connected to the device V2input. Footprints for decoupling capacitors are provided on both V1 and V2 traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation Figure 5. Evaluation Board Schematic board has not been shown to degrade RF Peregrine specification 102/0408 performance. NOTES: J1 1. USE 101-0337-02 PCB. HEADER 2 X 5 PIN 246 246 135 135 2. CTCOAOU NDTTAIAOMINNA:SG PEA BRYT ESL AENCTDR AOSSSTEAMTBICL IDEISS SCUHSACREGPET I(BESLED) 108 810 79 79 3. A33LLM TILR AWNIDSTMHIS, I1O0NM LILIN GEASP ASR, 2E8:MIL CORE DIELECTRIC 4.3 Er AND 2.1MIL Cu C1 R1 C2 R2 R3 THICKNESS. 100pF DNI 100pF 0 OHM 0 OHM J2 SMASM MU1SOP 1 JS3MASM 21 VV12 GNDRSF22 78 2 1 34 RNF/CC GNDRSF11 65 JS4MASM 2 or GND 1 2 J5 J6 SMASM SMASM 1 1 2 2 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0254-02 │ UltraCMOS™ RFIC Solutions Page 4 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4250 Product Specification Figure 6. Insertion Loss: RFC-RF @ 25 °C Figure 7. Insertion Loss: RFC-RF @ 3.3 V Figure 8. Isolation: RFC-RF @ 25 °C Figure 9. Isolation: RFC-RF @ 3.3 V Document No. 70-0254-02 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4250 Product Specification Figure 10. Return Loss at active port @ 25 °C Figure 11. Return Loss at active port @ 3.3 V ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0254-02 │ UltraCMOS™ RFIC Solutions Page 6 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4250 Product Specification Figure 12. Package Drawing 8-lead MSOP: 19-0118-01 Figure 13. Top Marking Specification 4250 AAAA: Product Number, last 4 digits, Exp. LLLL: Last four digits of the Assembly lot number LLLL YWW: Date Code, last digit of the year and work week YWW Document No. 70-0254-02 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4250 Product Specification Figure 14. Tape and Reel Specifications 8-lead MSOP Table 7. Dimensions Tape Feed Direction Dimension MSOP-8 Ao 5.30 ± 0.1 Pin 1 Bo 3.40 ± 0.1 Ko 1.40 ± 0.1 Top of F 5.50 ± 0.05 Device P 8 ± 0.1 1 W 12 ± 0.3 Device Orientation in Tape Table 7. Ordering Information Order Code Part Marking Description Package Shipping Method EK4250-01 PE4250-EK PE4250-08MSOP-EK Evaluation Kit 1 / Box PE4250MLI 4250 PE4250G-08MSOP-cut tape or loose Green 8-lead MSOP Cut tape or loose PE4250MLI-Z 4250 PE4250G-08MSOP-2000C Green 8-lead MSOP 2000 units / T&R ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0254-02 │ UltraCMOS™ RFIC Solutions Page 8 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4250 Product Specification Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9380 Carroll Park Drive Shanghai, 200040, P.R. China San Diego, CA 92121 Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Tel: 858-731-9400 Fax: 858-731-9499 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Europe Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Peregrine Semiconductor Europe Tel: +82-31-728-3939 Bâtiment Maine Fax: +82-31-728-3940 13-15 rue des Quatre Vents Peregrine Semiconductor K.K., Japan F-92380 Garches, France Teikoku Hotel Tower 10B-6 Tel: +33-1-4741-9173 1-1-1 Uchisaiwai-cho, Chiyoda-ku Fax : +33-1-4741-9173 Tokyo 100-0011 Japan Tel: +81-3-3502-5211 High-Reliability and Defense Products Fax: +81-3-3502-5213 Americas San Diego, CA, USA Phone: 858-731-9475 Fax: 848-731-9499 Europe/Asia-Pacific Aix-En-Provence Cedex 3, France Phone: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this The product is in a formative or design stage. The data information. Use shall be entirely at the user’s own risk. sheet contains design target specifications for product development. Specifications and features may change in No patent rights or licenses to any circuits described in this any manner without notice. data sheet are implied or granted to any third party. Preliminary Specification Peregrine’s products are not designed or intended for use in The data sheet contains preliminary data. Additional data devices or systems intended for surgical implant, or in other may be added at a later date. Peregrine reserves the right applications intended to support or sustain life, or in any to change specifications at any time without notice in order application in which the failure of the Peregrine product could to supply the best possible product. create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including Product Specification consequential or incidental damages, arising out of the use of its products in such applications. The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify The Peregrine name, logo, and UTSi are registered trademarks customers of the intended changes by issuing a CNF and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks (Customer Notification Form). of Peregrine Semiconductor Corp. Document No. 70-0254-02 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 9 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com