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PE42422MLAA-Z产品简介:
ICGOO电子元器件商城为您提供PE42422MLAA-Z由Peregrine设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 PE42422MLAA-Z价格参考¥4.91-¥4.91。PeregrinePE42422MLAA-Z封装/规格:RF 开关, RF Switch IC General Purpose SPDT 6GHz 50Ohm 12-QFN (2x2)。您可以下载PE42422MLAA-Z参考资料、Datasheet数据手册功能说明书,资料中有PE42422MLAA-Z 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | |
描述 | IC RF SWITCH SPDT 50 OHM 12QFN |
产品分类 | |
IIP3 | 70dBm (标准) |
品牌 | Peregrine Semiconductor |
数据手册 | |
产品图片 | |
P1dB | - |
产品型号 | PE42422MLAA-Z |
RF类型 | 通用 |
rohs | 无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | UltraCMOS®,HaRP™ |
供应商器件封装 | 12-QFN(2x2) |
其它名称 | 1046-1062-2 |
包装 | 带卷 (TR) |
封装/外壳 | 12-UFQFN 裸露焊盘 |
工作温度 | -40°C ~ 85°C |
拓扑 | 反射 |
插损@频率 | 0.9dB @ 6GHz |
标准包装 | 3,000 |
特性 | - |
特色产品 | http://www.digikey.cn/product-highlights/cn/zh/peregrine-pe42422-rf-switch/2968 |
电压-电源 | 2.3 V ~ 5.5 V |
电路 | SPDT |
阻抗 | 50 欧姆 |
隔离@频率 | 17dB @ 6GHz (标准) |
频率 -上 | 6GHz |
频率 -下 | 100MHz |
Product Specification PE42422 UltraCMOS® SPDT RF Switch 5–6000 MHz Product Description Features The PE42422 is a HaRP™ technology-enhanced SPDT Symmetric SPDT reflective switch RF switch designed to cover a broad range of Low insertion loss applications from 5–6000 MHz. This reflective switch 0.23 dB typical @ 100 MHz integrates on-board CMOS control logic with a low 0.25 dB typical @ 1000 MHz voltage CMOS-compatible control interface and requires 0.40 dB typical @ 3000 MHz no external components. 0.65 dB typical @ 5000 MHz 0.90 dB typical @ 6000 MHz Peregrine’s HaRP technology enhancements deliver high Wide supply range of 2.3–5.5V linearity and exceptional harmonics performance. It is an innovative feature of the UltraCMOS® process, providing Excellent linearity performance superior to GaAs with the economy and IIP2 of 105 dBm @ 17 MHz integration of conventional CMOS. IIP3 of 81 dBm @ 17 MHz High ESD tolerance 4 kV HBM on RF pins to GND 1 kV on all other pins Logic Select (LS) pin provides maximum flexibility of control logic 12-lead 2 × 2 mm QFN package Figure 1. Functional Diagram Figure 2. Package Type 12-lead 2 x 2 x 0.55 mm QFN RFC D S E RF1 RF2 ESD ESD CMOS Control Driver and ESD 71-0068 V1 LS D ocument No. DOC-33314-4 | www.psemi.com ©2012-2016 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 16
PE42422 Product Specification Table 1. Electrical Specifications @ +25 °C1, V = 2.3–5.5V (Z = Z = 50Ω), unless otherwise specified DD S L Parameter Path Condition Min Typ Max Unit Operational frequency 5 6000 MHz 5–100 MHz 0.23 dB 100–1000 MHz 0.25 0.35 dB 1000–2000 MHz 0.30 0.40 dB Insertion loss2 RFX–RFC 2000–3000 MHz 0.40 0.50 dB 3000–4000 MHz 0.50 0.70 dB 4000–5000 MHz 0.65 0.902 dB 5000–6000 MHz 0.90 1.252 dB 5–100 MHz 68 dB 100–1000 MHz 42 44 dB 1000–2000 MHz 33 35 dB Isolation RFX–RFC 2000–3000 MHz 27 29 dB 3000–4000 MHz 22 24 dB 4000–5000 MHz 18 20 dB 5000–6000 MHz 15 17 dB 5–100 MHz 61 dB 100–1000 MHz 40 41 dB 1000–2000 MHz 32 33 dB Isolation RFX–RFX 2000–3000 MHz 26 28 dB 3000–4000 MHz 22 24 dB 4000–5000 MHz 18 20 dB 5000–6000 MHz 15 16 dB 5–100 MHz 33 dB 100-1000 MHz 28 dB 1000–2000 MHz 21 dB Return loss2 RFX–RFC 2000–3000 MHz 20 dB 3000–4000 MHz 18 dB 4000–5000 MHz 162 dB 5000–6000 MHz 132 dB +18 dBm input power, 17–204 MHz –92 dBc 2nd harmonic RFX–RFC +32 dBm output power, 850 / 900 MHz –99 dBc +32 dBm output power, 1800 / 1900 MHz –101 dBc +18 dBm input power, 17–204 MHz –125 dBc 3rd harmonic RFX–RFC +32 dBm output power, 850 / 900 MHz –93 dBc +32 dBm output power, 1800 / 1900 MHz –87 dBc Bands I, II, V, VIII +17 dBm CW @ TX freq at RFC, IMD3 RF–RFC –115 dBm –15 dBm CW @ 2Tx-Rx at RFC, 50Ω © 2012-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-33314-4 | UltraCMOS® RFIC Solutions Page 2 of 16
PE42422 Product Specification Table 1. Electrical Specifications @ +25 °C1, V = 2.3–5.5V (Z = Z = 50Ω), unless otherwise specified DD S L Parameter Path Condition Min Typ Max Unit 5 MHz 96 dBm IIP2 RFX 17 MHz 105 dBm 100–6000 MHz 115 dBm 5 MHz 75 dBm IIP3 RFX 17 MHz 81 dBm 100–6000 MHz 75 dBm 5–100 MHz 33 dBm Input 0.1dB compression point3 RFX or RFC 100–6000 MHz 34 dBm Switching time 50% CTRL to (10%–90%) or (90%–10%) RF 2 4 μs Notes: 1. Typical performance over temperature and VDD shown in Figure 5 through Figure 21. 2. High frequency performance can be improved by external matching (see Figure 22 through Figure 27 and Figure 30). 3. The input P0.1dB compression point is a linearity figure of merit. Refer to Table 4 for the operating RF input power. D ocument No. DOC-33314-4 | www.psemi.com ©2012-2016 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 16
PE42422 Product Specification Figure 3. Pin Configuration (Top View) Table 4. Operating Ranges Pin 1 dot Parameter Min Typ Max Unit marking VDD LS V1 12 11 10 VDD Supply voltage 2.3 3.3 5.5 V I Power supply current 120 200 µA DD GND 1 9 DGND RFX–RFC input power Fig. 4 dBm Exposed Control voltage high 1.2 1.5 3.3 V RF2 2 Ground 8 RF1 Control voltage low 0 0 0.5 V Pad Operating temperature range –40 +25 +85 °C GND 3 7 GND Table 5. Absolute Maximum Ratings 4 5 6 Parameter/Condition Min Max Unit GND/NC RFC GND RF input power, 50Ω1 5–100 MHz 33 dBm Table 2. Pin Descriptions 100–6000 MHz 34 dBm Pin No. Pin Name Description ESD voltage HBM2 1 GND Ground RF pins to GND 4000 V All other pins 1000 V 2 RF21 RF port 2 ESD voltage MM, all pins3 200 V 3 GND Ground T Storage temperature –65 +150 °C 4 GND/NC2 Ground or no connect ST 5 RFC1 RF common Notes: 1. VDD within operating range specified in Table 4. 2. Human Body Model (MIL_STD 883 Method 3015.7). 3. Machine Model (JEDEC JESD22-A115-A). 6 GND Ground 7 GND Ground Exceeding absolute maximum ratings may cause 8 RF11 RF port 1 permanent damage. Operation should be restricted to the limits in the Operating Ranges table. 9 DGND Digital Ground 10 V1 Switch control input, CMOS logic level Electrostatic Discharge (ESD) Precautions 11 LS Logic Select, CMOS logic level When handling this UltraCMOS device, observe 12 V Supply DD the same precautions that you would use with Pad GND Exposed pad: ground for proper operation other ESD-sensitive devices. Although this device Notes: 1. RF pins 2, 5 and 8 must be at 0 VDC. The RF pins do not required DC contains circuitry to protect it from damage due to blocking capacitors for proper operation if the 0 VDC requirement is met. 2. Pin 4 can be grounded or left unconnected externally. ESD, precautions should be taken to avoid exceeding the specified rating. Table 3. Truth Table Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS Path V1 LS devices are immune to latch-up. RFC–RF2 1 1 Moisture Sensitivity Level RFC–RF1 0 1 The Moisture Sensitivity Level rating for the RFC–RF1 1 0 PE42422 in the 12-lead 2 × 2 × 0.55 mm QFN RFC–RF2 0 0 package is MSL1. © 2012-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-33314-4 | UltraCMOS® RFIC Solutions Page 4 of 16
PE42422 Product Specification Figure 4. Power De-rating Curve for 5–6000 MHz D ocument No. DOC-33314-4 | www.psemi.com ©2012-2016 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 16
PE42422 Product Specification Typical Performance Data @ +25 °C and V = 3.3V, unless otherwise specified DD Figure 5. Insertion Loss RFX* Figure 6. Insertion Loss vs Temp (RF1–RFC)* Figure 8. Insertion Loss vs V (RF1–RFC)* DD Figure 7. Insertion Loss vs Temp (RF2–RFC)* Figure 9. Insertion Loss vs V (RF2–RFC)* DD Note: * High frequency performance can be improved by external matching (see Figure 22 through Figure 27 and Figure 30). © 2012-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-33314-4 | UltraCMOS® RFIC Solutions Page 6 of 16
PE42422 Product Specification Typical Performance Data @ +25 °C and V = 3.3V, unless otherwise specified (cont.) DD Figure 10. RFX–RFX Isolation vs Temp Figure 12. RFX–RFX Isolation vs V DD Figure 11. RFC–RFX Isolation vs Temp Figure 13. RFC–RFX Isolation vs V DD D ocument No. DOC-33314-4 | www.psemi.com ©2012-2016 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 16
PE42422 Product Specification Typical Performance Data @ +25 °C and V = 3.3V, unless otherwise specified (cont.) DD Figure 14. RFC Port Return Loss vs Temp Figure 16. RFC Port Return Loss vs V DD (RF1 Active)* (RF1 Active)* Figure 15. RFC Port Return Loss vs Temp Figure 17. RFC Port Return Loss vs V DD (RF2 Active)* (RF2 Active)* Note: * High frequency performance can be improved by external matching (see Figure 22 through Figure 27 and Figure 30). © 2012-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-33314-4 | UltraCMOS® RFIC Solutions Page 8 of 16
PE42422 Product Specification Typical Performance Data @ +25 °C and V = 3.3V, unless otherwise specified (cont.) DD Figure 18. Active Port Return Loss vs Temp Figure 20. Active Port Return Loss vs V DD (RF1 Active)* (RF1 Active)* Figure 19. Active Port Return Loss vs Temp Figure 21. Active Port Return Loss vs V DD (RF2 Active)* (RF2 Active)* Note: * High frequency performance can be improved by external matching (see Figure 22 through Figure 27 and Figure 30). D ocument No. DOC-33314-4 | www.psemi.com ©2012-2016 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 16
PE42422 Product Specification Performance Comparison @ +25 °C and V = 3.3V, with or without matching DD Figure 22. Insertion Loss RF1* Figure 25. Insertion Loss RF2* Figure 23. Active Port Return Loss (RF1 Active)* Figure 26. Active Port Return Loss (RF2 Active)* Figure 24. RFC Port Return Loss (RF1 Active)* Figure 27. RFC Port Return Loss (RF2 Active)* Note: * High frequency performance can be improved by external matching (see Figure 22 through Figure 27 and Figure 30). © 2012-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-33314-4 | UltraCMOS® RFIC Solutions Page 10 of 16
PE42422 Product Specification Evaluation Board Figure 28. Evaluation Board Layout The SPDT switch evaluation board was designed to ease customer evaluation of Peregrine’s PE42422. The RF common port is connected through a 50Ω transmission line via the top SMA connector, J2. RF1 and RF2 ports are connected through 50Ω transmission lines via SMA connectors J1 and J3, respectively. A through 50Ω transmission is available via SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. J8 provides DC and digital inputs to the device. The board is constructed of a four metal layer material with a total thickness of 62 mils. The top and bottom RF layers are Rogers RO4350 material with a 10 mil RF core. The middle layers provide ground for the transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 22 mils, trace gaps of 7 mils, and metal thickness of 2.1 mils. PRT-29005 D ocument No. DOC-33314-4 | www.psemi.com ©2012-2016 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 16
PE42422 Product Specification Figure 29. Evaluation Board Schematic DOC-33327 © 2012-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-33314-4 | UltraCMOS® RFIC Solutions Page 12 of 16
PE42422 Product Specification Figure 30. Evaluation Board Schematic with Matching DOC-33327 D ocument No. DOC-33314-4 | www.psemi.com ©2012-2016 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 16
PE42422 Product Specification Figure 31. Package Drawing 12-lead 2 × 2 × 0.55 mm QFN 0.25 (X12) 0.10 C A 2.00 (X2) 0.475 B 0.50 (X12) 1.10±0.05 0.50 7 9 6 10 2.00 1.10±0.05 1.10 2.40 4 0.20±0.05 12 0.10 C (X12) 3 1 0.275±0.05 (X2) 1.00 (X12) 1.10 2.40 PIN#1Identifier TOPVIEW BOTTOMVIEW RECOMMENDEDLANDPATTERN DOC-01882 0.10 C 0.10 C A B 0.05 C 0.60MAX 0.05 C ALLFEATURES SEATINGPLANE 0.152REF. 0.05MAX SIDEVIEW C © 2012-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-33314-4 | UltraCMOS® RFIC Solutions Page 14 of 16
PE42422 Product Specification Figure 32. Top Marking Specifications Marking Spec Package Definition PPZZ Symbol Marking PP DE Part number marking for PE42422 YWW ZZ 00-99 Last two digits of lot code Last digit of year, starting from 2009 Y 0-9 (0 for 2010, 1 for 2011, etc) WW 01-53 Work week 17-0112 Marking Spec Package Definition PPZZ Symbol Marking PP DE Part number marking for PE42422 YYWW ZZ 00-99 Last two digits of lot code Last two digits of assembly year YY 00-99 (Ex: 15 for 2015) WW 01-53 Work week DOC-66046 D ocument No. DOC-33314-4 | www.psemi.com ©2012-2016 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 16
PE42422 Product Specification Figure 33. Tape and Reel Specifications 12-lead 2 × 2 × 0.55 mm QFN Tape Feed Direction Pin 1 Nominal Tolerance Top of Ao 2.20 ±0.1 Device Bo 2.20 ±0.1 Ko 0.75 ±0.1 Device Orientation in Tape Table 6. Ordering Information Order Code Description Package Shipping Method PE42422MLAA-Z PE42422 SPDT RF switch Green 12-lead 2 × 2mm QFN 3000 units T/R EK42422-01 PE42422 Evaluation board Evaluation kit 1/Box Sales Contact and Information For sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. specifications for product development. Specifications and features may change in any manner without notice. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later or in other applications intended to support or sustain life, or in any application in which the failure of the date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to liability for damages, including consequential or incidental damages, arising out of the use of its products in change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer such applications. Notification Form). The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use are trademarks of Peregrine Semiconductor Corp. Peregrin e products are protected under one or more of of this information. Use shall be entirely at the user’s own risk. the following U.S. Patents: http://patents.psemi.com. © 2012-2016 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-33314-4 | UltraCMOS® RFIC Solutions Page 16 of 16