Product Sample & Technical Tools & Support & Folder Buy Documents Software Community PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 PCM510xA 2.1 V , 112/106/100 dB Audio Stereo DAC RMS with PLL and 32-bit, 384 kHz PCM Interface 1 Features Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-V ground • UltraLowOut-of-BandNoise RMS 1 centered outputs, allowing designers to eliminate DC • IntegratedHigh-PerformanceAudioPLLwithBCK blocking capacitors on the output, as well as external ReferencetoGenerateSCKInternally muting circuits traditionally associated with single- • DirectLineLevel2.1-V Output supplylinedrivers. RMS • NoDCBlockingCapacitorsRequired The integrated line driver surpasses all other charge- pump based line drivers by supporting loads down to • LineLevelOutputDownto1KΩ 1kΩ perpin. • IntelligentMutingSystem;SoftUporDownRamp andAnalogMuteFor120-dBMuteSNR The integrated PLL on the device removes the requirement for a system clock (commonly known as • Accepts16-,24-,and32-BitAudioData master clock), allowing a 3-wire I2S connection and • PCMDataFormats:I2S,Left-Justified reducingsystemEMI. • AutomaticPower-SaveModeWhenLRCKAnd Intelligent clock error and PowerSense undervoltage BCKAreDeactivated protection utilizes a two-level mute system for pop- • 1.8Vor3.3VFailsafeLVCMOSDigitalInputs freeperformance. • SimpleConfigurationUsingHardwarePins Comparedwithmanyconventionalswitchedcapacitor • Single-SupplyOperation:14 DAC architectures, the PCM510xA family offers up to – 3.3VAnalog,1.8Vor3.3VDigital 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured • QualifiedinAccordancewithAEC-Q100 from the traditional 100-kHz OBN measurements to 3 MHz). 2 Applications • A/VReceivers,DVD,BDPlayers Table1.DeviceInformation(1) • AutomotiveInfotainmentandTelematics PARTNUMBER PACKAGE BODYSIZE(NOM) • HDTVReceivers PCM5102A • AftermarketAutomotiveAmplifiers PCM5101A TSSOP(20) 5.50mm×4.40mm PCM5100A 3 Description (1) For all available packages, see the orderable addendum at The PCM510xA devices are a family of monolithic theendofthedatasheet. CMOS-integrated circuits that include a stereo digital- to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment- DAC architecture to achieve excellent dynamic performanceandimprovedtolerancetoclockjitter. 4 Simplified System Diagram I2S 2ch Single Ended PCM1863/5 BCK L PCM510xA L LRCK P IN AUX Charge Pump OUT LINE 2ch Single Ended INMIC ASneanlsoogr BTModule WiLAN chip MSP430 -Light Intensity -Ultrasonic -Battery Level 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 9.4 DeviceFunctionalModes........................................25 2 Applications........................................................... 1 10 ApplicationsandImplementation...................... 26 3 Description............................................................. 1 10.1 ApplicationInformation..........................................26 4 SimplifiedSystemDiagram.................................. 1 11 PowerSupplyRecommendations..................... 28 5 RevisionHistory..................................................... 2 11.1 PowerSupplyDistributionandRequirements......28 11.2 RecommendedPowerdownSequence.................28 6 DeviceComparison............................................... 4 11.3 ExternalPowerSenseUndervoltageProtection 7 PinConfigurationandFunctions......................... 5 Mode........................................................................ 30 8 Specifications......................................................... 6 11.4 Power-OnResetFunction.....................................32 8.1 AbsoluteMaximumRatings......................................6 11.5 PCM510xAPowerModes.....................................33 8.2 ESDRatings ............................................................6 12 Layout................................................................... 34 8.3 RecommendedOperatingConditions.......................6 12.1 LayoutGuidelines.................................................34 8.4 ThermalInformation..................................................6 13 DeviceandDocumentationSupport................. 35 8.5 ElectricalCharacteristics...........................................7 13.1 RelatedLinks........................................................35 8.6 TimingRequirements..............................................11 13.2 CommunityResources..........................................35 8.7 TimingRequirements,XSMT..................................11 13.3 Trademarks...........................................................35 8.8 TypicalCharacteristics............................................12 13.4 ElectrostaticDischargeCaution............................35 9 DetailedDescription............................................ 14 14 Mechanical,Packaging,andOrderable 9.1 Overview.................................................................14 Information........................................................... 35 9.2 FunctionalBlockDiagram.......................................14 14.1 MechanicalData...................................................35 9.3 FeatureDescription.................................................14 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(January2015)toRevisionC Page • Changedthedevicenumberfrom"PCM510x"to"PCM510xA"intheSimplifiedSystemDiagram ..................................... 1 • Changedtypicalperformancetabletoreflectpartdifferencesaccurately ............................................................................ 4 • Changed"Storagetemperatures,T "to"Operatingjunctiontemperaturerangeat–40°Cto130°C"................................. 6 stg • Changed"Storagetemperature(Q1devices)–40°Cto125°C"to"Storagetemperatures,T –65°Cto150°C"................6 stg • ChangedthestereolineoutputloadresistanceMINvalueintheRecommendedOperatingConditionsfrom"2kΩ" to"1kΩ".................................................................................................................................................................................. 6 • ChangedtheoperatingjunctiontemperaturerangeintheRecommendedOperatingConditionsfrom"MIN=–25°C MAX=85°C"to"MIN=–40°CMAX=130°C"....................................................................................................................... 6 • Added"Q1Automotivegradedevices..."and"Consumergrade(non-Q1)devices..."totheconditionstatementin theElectricalCharacteristics.................................................................................................................................................. 7 • Added"Q1Automotivegradedevices..."and"Consumergrade(non-Q1)devices..."totheconditionstatementin theTypicalCharacteristicsgraphssection........................................................................................................................... 12 • Changed"MCK"to"SCK"atthePLLClockintheFunctionalBlockDiagram..................................................................... 14 • Addedlabel"MuteCircuit"andgroundsymbolstopinsDEMPandFMTinFigure33 ...................................................... 26 ChangesfromRevisionA(September2012)toRevisionB Page • AddedESDRatingtable,DetailedDescriptionsection,ApplicationandImplementationsection,PowerSupply Recommendationssection,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderable Information.............................................................................................................................................................................. 1 • Addeditemstoshow1.8VDVDDcapability......................................................................................................................... 1 • ChangedtheFeatureslist...................................................................................................................................................... 1 • Changed"Operatingtemperaturerange"to"Operatingjunctiontemperaturerange".......................................................... 6 • DeletedredundantPLLspecificationintheRecommendedOperatingConditions .............................................................. 6 • Deleted"Intelligentclockerror..."and"...forpop-freeperformance."................................................................................... 14 2 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 • Clarifiedclockgenerationexplanation.................................................................................................................................. 24 • ClarifiedexternalSCKdiscussion........................................................................................................................................ 25 • Deleted"ThePCM510xAdisablestheinternalPLLwhenanexternalSCKissupplied."................................................... 25 ChangesfromOriginal(May2012)toRevisionA Page • Changedlayoutoffirsttwopages.......................................................................................................................................... 1 • Changed"VOUT=–1dB"to"THD+Nat–1dBFS"inintheDymamicPerformancesectionoftheElectrical Characteristics........................................................................................................................................................................ 8 • Changedreferencetocorrectfootnote................................................................................................................................. 10 • Changedt andt valuesto9ns................................................................................................................................. 11 SCKH SCKL • Removed48kHzsampleratewithPLL-generatedclock...................................................................................................... 25 Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 6 Device Comparison DifferencesBetweenPCM510xADevices PARTNUMBER DYNAMICRANGE SNR THD PCM5102A 112dB 112dB –93dB PCM5101A 106dB 106dB –92dB PCM5100A 100dB 100dB –90dB TypicalPerformance(3.3VPowerSupply) PARAMETER PCM5102/PCM5101/PCM5100 SNR 112/106/100dB Dynamicrange 112/106/100dB THD+Nat–1dBFS –93/–92/–90dB Full-scalesingle-endedoutput 2.1V (GNDcenter) RMS Normal8×oversamplingdigitalfilterlatency 20t S Lowlatency8×oversamplingdigitalfilterlatency 3.5t S Samplingfrequency 8kHzto384kHz Systemclockmultiples(f ):64,128,192,256,384, Upto50MHz SCK 512,768,1024,1152,1536,2048,3072 4 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 7 Pin Configuration and Functions PW20-PinPackage (TopView) PinFunctions PIN TYPE DESCRIPTION NAME NO. AGND 9 — Analogground AVDD 8 P Analogpowersupply,3.3V BCK 13 I Audiodatabitclockinput(1) CAPM 4 O Chargepumpflyingcapacitorterminalfornegativerail CAPP 2 O Chargepumpflyingcapacitorterminalforpositiverail CPGND 3 — Chargepumpground CPVDD 1 P Chargepumppowersupply,3.3V DEMP 10 I De-emphasiscontrolfor44.1-kHzsamplingrate(1):Off(Low)/On(High) DGND 19 — Digitalground DIN 14 I Audiodatainput(1) DVDD 20 P Digitalpowersupply,1.8Vor3.3V FLT 11 I Filterselect:Normallatency(Low)/Lowlatency(High) FMT 16 I Audioformatselection:I2S(Low)/Left-justified(High) LDOO 18 P Internallogicsupplyrailterminalfordecoupling,orexternal1.8Vsupplyterminal LRCK 15 I Audiodatawordclockinput(1) OUTL 6 O AnalogoutputfromDACleftchannel OUTR 7 O AnalogoutputfromDACrightchannel SCK 12 I Systemclockinput(1) VNEG 5 O Negativechargepumprailterminalfordecoupling,–3.3V XSMT 17 I Softmutecontrol(1):Softmute(Low)/softun-mute(High) (1) FailsafeLVCMOSSchmitttriggerinput Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT AVDD,CPVDD,DVDD –0.3 3.9 Supplyvoltage LDOwithDVDDat1.8V –0.3 2.25 DVDDat1.8V –0.3 2.25 V Digitalinputvoltage DVDDat3.3V –0.3 3.9 Analoginputvoltage –0.3 3.9 Operatingjunctiontemperaturerange –40 130 °C Storagetemperature,T –65 150 °C stg 8.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±750 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 8.3 Recommended Operating Conditions MIN NOM MAX UNIT Referencedto VCOMmode 3 3.3 3.46 AVDD Analogpowersupplyvoltagerange AGND(1) VREFmode 3.2 3.3 3.46 V Referencedto 1.8VDVDD 1.65 1.8 1.95 DVDD Digitalpowersupplyvoltagerange DGND(1) 3.3VDVDD 3.1 3.3 3.46 V CPVDD Chargepumpsupplyvoltagerange ReferencedtoCPGND(1) 3.1 3.3 3.46 V MCLK Masterclockfrequency 50 MHz LOL,LOR Stereolineoutputloadresistance 1 10 kΩ C Digitaloutputloadcapacitance 10 pF LOUT T Operatingjunctiontemperaturerange –40 130 °C J (1) Allgroundsonboardaretiedtogether;theymustnotdifferinvoltagebymorethan0.2Vmax,foranycombinationofgroundsignals. 8.4 Thermal Information PW THERMALMETRIC(1) UNIT 20PINS R Junction-to-ambientthermalresistance 91.2 θJA R Junction-to-case(top)thermalresistance 25.3 θJC(top) R Junction-to-boardthermalresistance 42 θJB °C/W ψ Junction-to-topcharacterizationparameter 1 JT ψ Junction-to-boardcharacterizationparameter 41.5 JB R Junction-to-case(bottom)thermalresistance — θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 6 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 8.5 Electrical Characteristics Q1AutomotivegradedevicesarespecifiedforT =–40°Cto125°C.Consumergrade(non-Q1)devicesarespecifiedatT = A A 25°C.AlldevicesinthefamilyarecharacterizedwithAVDD=CPVDD=DVD=3.3V,f =48kHz,systemclock=512f and S S 24-bitdataunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Resolution 16 24 32 Bits DataFormat(PCMMode) Audiodatabitlength 16 24 32 Bits fS(1) Samplingfrequency 8 384 kHz Clockmultiples:64,128,192,256,384, fSCK Systemclockfrequency 512,768,1024,1152,1536,2048,or 50 MHz 3072 DigitalInput/Outputfornon-Q1ConsumerGradeDevices Logicfamily:3.3VLVCMOScompatible VIH 0.7×DVDD Inputlogiclevel V VIL 0.3×DVDD IIH VIN=VDD 10 Inputlogiccurrent µA IIL VIN=0V –10 VOH IOH=–4mA 0.8×DVDD Outputlogiclevel V VOL IOL=4mA 0.22×DVDD Logicfamily1.8VLVCMOScompatible VIH 0.7×DVDD Inputlogiclevel V VIL 0.3×DVDD IIH VIN=VDD 10 Inputlogiccurrent µA IIL VIN=0V –10 VOH IOH=–2mA 0.8×DVDD Outputlogiclevel V VOL IOL=2mA 0.22×DVDD DigitalInput/OutputforQ1AutomotiveGradeDevices Logicfamily:3.3VLVCMOScompatible VIH 0.7×DVDD Inputlogiclevel V VIL 0.3×DVDD IIH VIN=VDD 10 Inputlogiccurrent µA IIL VIN=0V –10 VOH IOH=–4mA 0.8×DVDD Outputlogiclevel V VOL IOL=4mA 0.22×DVDD Logicfamily1.8VLVCMOScompatible VIH 0.7×DVDD Inputlogiclevel V VIL 0.3×DVDD IIH VIN=VDD 10 Inputlogiccurrent µA IIL VIN=0V –10 VOH IOH=–2mA 0.8×DVDD Outputlogiclevel V VOL IOL=2mA 0.3×DVDD (1) Onesampletimeisdefinedasthereciprocalofthesamplingfrequency.1t =1/f S S Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com Electrical Characteristics (continued) Q1AutomotivegradedevicesarespecifiedforT =–40°Cto125°C.Consumergrade(non-Q1)devicesarespecifiedatT = A A 25°C.AlldevicesinthefamilyarecharacterizedwithAVDD=CPVDD=DVD=3.3V,f =48kHz,systemclock=512f and S S 24-bitdataunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DynamicPerformance(PCMMode)(2)(3) PCM5102A –93 –83 dB fS=48kHz PCM5101A –92 –82 PCM5100A –90 –80 THD+Nat–1dBFS(3) PCM5102A –93 fS=96kHzand192kHz PCM5101A –92 PCM5100A –90 PCM5102A 106 112 EIAJ,A-weighted,fS=48 PCM5101A 100 106 kHz PCM5100A 95 100 Dynamicrange(3) PCM5102A 112 EIAJ,A-weighted,fS=96 PCM5101A 106 kHzand192kHz PCM5100A 100 PCM5102A 112 EIAJ,A-weighted,fS=48 PCM5101A 106 kHz PCM5100A 100 Signal-to-noiseratio(3) PCM5102A 112 EIAJ,A-weighted,fS=96 PCM5101A 106 kHzand192kHz PCM5100A 100 EIAJ,A-weighted,fS=48kHz 113 123 Signaltonoiseratiowithanalog mute(3)(4) EIAJ,A-weighted,fS=96kHzand192 123 kHz PCM5102A 100 109 fS=48kHz PCM5101A 95 103 PCM5100A 90 97 PCM5102A 109 Channelseparation fS=96kHz PCM5101A 103 PCM5100A 97 PCM5102A 109 fS=192kHz PCM5101A 103 PCM5100A 97 (2) Filtercondition:THD+N:20-HzHPF,20-kHzAES17LPF;Dynamicrange:20-HzHPF,20-kHzAES17LPF;A-weightedsignal-to-noise ratio:20-HzHPF,20-kHzAES17LPF;A-weightedchannelseparation:20-HzHPF,20-kHzAES17LPF.Analogperformance specificationsaremeasuredusingtheSystemTwoCascade™audiomeasurementsystembyAudioPrecision™intheRMSmode. (3) Outputloadis10kΩ,with470-Ωoutputresistoranda2.2-nFshuntcapacitor(seerecommendedoutputfilter). (4) AssertXSMTorbothL-chandR-chPCMdataareBipolarZero. 8 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 Electrical Characteristics (continued) Q1AutomotivegradedevicesarespecifiedforT =–40°Cto125°C.Consumergrade(non-Q1)devicesarespecifiedatT = A A 25°C.AlldevicesinthefamilyarecharacterizedwithAVDD=CPVDD=DVD=3.3V,f =48kHz,systemclock=512f and S S 24-bitdataunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT AnalogOutput Outputvoltage 2.1 VRMS Gainerror –6 ±2 6 %ofFSR GainerroronQ1AutomotiveGrade –7 ±2 7 %ofFSR Devices Gainmismatch,channel-to-channel –6 ±2 6 %ofFSR Gainmismatch,channel-to-channelon –6 ±2 6 %ofFSR Q1Devices PCM5100/1bipolarzeroerror Atbipolarzero –5 ±1 5 mV PCM5102Bipolarzeroerror Atbipolarzero –2 ±1 2 mV Loadimpedance 1 kΩ FilterCharacteristics–1:Normal Passband 0.45fS Stopband 0.55fS Stopbandattenuation –60 dB Pass-bandripple ±0.02 Delaytime 20tS s FilterCharacteristics–2:LowLatency Passband 0.47fS Stopband 0.55fS Stopbandattenuation –52 dB Pass-bandripple ±0.0001 Delaytime 3.5tS s PowerSupplyRequirements DVDD Digitalsupplyvoltage TargetDVDD=1.8V 1.65 1.8 1.95 VDC DVDD Digitalsupplyvoltage TargetDVDD=3.3V 3 3.3 3.6 AVDD Analogsupplyvoltage 3 3.3 3.6 VDC CPVDD Charge-pumpsupplyvoltage 3 3.3 3.6 fS=48kHz 7 IDD DVDDsupplycurrentat1.8V(5) fS=96kHz 8 mA fS=192kHz 9 fS=48kHz 7 IDD DVDDsupplycurrentat1.8V(6) fS=96kHz 8 mA fS=192kHz 9 IDD DVDDsupplycurrentat1.8V(7) Standby 0.3 mA fS=48kHz 7 12 IDD DVDDsupplycurrentat3.3V(5) fS=96kHz 8 mA fS=192kHz 9 fS=48kHz 8 13 IDD DVDDsupplycurrentat3.3V(6) fS=96kHz 9 mA fS=192kHz 10 IDD DVDDsupplycurrentat3.3V(7) Standby 0.5 0.8 mA fS=48kHz 11 16 IDD AVDD/CPVDDsupplycurrent(5) fS=96kHz 11 mA fS=192kHz 11 (5) InputisBipolarZerodata. (6) Inputis1kHz–1dBFSdata. (7) PowerDownMode Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com Electrical Characteristics (continued) Q1AutomotivegradedevicesarespecifiedforT =–40°Cto125°C.Consumergrade(non-Q1)devicesarespecifiedatT = A A 25°C.AlldevicesinthefamilyarecharacterizedwithAVDD=CPVDD=DVD=3.3V,f =48kHz,systemclock=512f and S S 24-bitdataunlessotherwisenoted. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT fS=48kHz 22 32 IDD AVDD/CPVDDsupplycurrent(6) fS=96kHz 22 mA fS=192kHz 22 IDD AVDD/CPVDDsupplycurrent(7) fS=n/a 0.2 0.4 mA fS=48kHz 49 185 Powerdissipation,DVDD=1.8V(5) fS=96kHz 51 mW fS=192kHz 53 fS=48kHz 85 187 Powerdissipation,DVDD=1.8V(6) fS=96kHz 87 mW fS=192kHz 89 Powerdissipation,DVDD=1.8V(7) fS=n/a(PowerDownMode) 1 mW fS=48kHz 60 92.4 Powerdissipation,DVDD=3.3V(5) fS=96kHz 63 mW fS=192kHz 66 fS=48kHz 99 148.5 Powerdissipation,DVDD=3.3V(6) fS=96kHz 102 mW fS=192kHz 106 Powerdissipation,DVDD=3.3V(7) fS=n/a(PowerDownMode) 2 4 mW 10 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 8.6 Timing Requirements Figure1showsthetimingrequirementsforthesystemclockinput.Foroptimalperformance,useaclocksourcewithlow phasejitterandnoise. MIN TYP MAX UNIT t Systemclockpulsecycletime 20 1000 ns SCY DVDD=1.8V 8 t Systemclockpulsewidth,High ns SCKH DVDD=3.3V 9 DVDD=1.8V 8 t Systemclockpulsewidth,Low ns SCKL DVDD=3.3V 9 t SCKH "H" 0.7*DVDD System Clock (SCK) 0.3*DVDD "L" t t SCKL SCY Figure1. TimingRequirementsforSCKInput 8.7 Timing Requirements, XSMT MIN TYP MAX UNIT t Risetime 20 ns r t Falltime 20 ns f 0.9 * DVDD XSMT 0.1 * DVDD tr tf <20ns <20ns Figure2. XSMTTimingforSoftMuteandSoftUn-Mute Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 8.8 Typical Characteristics Q1AutomotivegradedevicesarespecifiedforT =–40°Cto125°C.Consumergrade(non-Q1)devicesarespecifiedatT = A A 25°C,AV =CPV =DV =3.3V,f =48kHz,systemclock=512f and24-bitdataunlessotherwisenoted. DD DD DD S S 10 10 -10 -10 -30 -30 D+N (dB)-50 D+N (dB)-50 H H T-70 T-70 -90 -90 -110 -110 -100 -80 -60 -40 -20 0 -100 -80 -60 -40 -20 0 Input Level (dBFS) Input Level (dBFS) Figure3.PCM5101THD+NversusInputLevel Figure4.PCM5102THD+NversusInputLevel -20 -20 -40 -40 -60 -60 B) B) e (d -80 e (d -80 d d u u plit-100 plit-100 m m A A -120 -120 -140 -140 -160 -160 0 5 10 15 20 0 5 10 15 20 Frequency (kHz) Frequency (kHz) Figure5.PCM5101FFTPlotusinga1-kHztone(–60dBFS) Figure6.PCM5102FFTPlotusinga1-kHztone(–60dBFS) fromDCto20kHz fromDCto20kHz -20 -20 -40 -40 -60 -60 mplitude (dB)--11-208000 mplitude (dB)--11-208000 A A -140 -140 -160 -160 -180 -180 0 5 10 15 20 0 5 10 15 20 Frequency (kHz) Frequency (kHz) Figure7.PCM5101FFTPlotAtBipolarZeroData(BPZ) Figure8.PCM5102FFTPlotatBPZ 12 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 Typical Characteristics (continued) Q1AutomotivegradedevicesarespecifiedforT =–40°Cto125°C.Consumergrade(non-Q1)devicesarespecifiedatT = A A 25°C,AV =CPV =DV =3.3V,f =48kHz,systemclock=512f and24-bitdataunlessotherwisenoted. DD DD DD S S -20 -40 -60 mplitude (dB) mplitude (dB)--11-208000 A A -140 -160 -180 0 5 10 15 20 Frequency (kHz) Frequency (kHz) Figure9.PCM5101FFTPlotatBPZWithAnalogMute Figure10.PCM5102FFTPlotatBPZWithAnalogMute (AMUTE) (AMUTE) 0 0 -20 -20 -40 -40 dB) -60 dB) -60 e ( e ( ud -80 ud -80 plit plit m-100 m-100 A A -120 -120 -140 -140 -160 -160 0 50 100 150 200 250 300 0 50 100 150 200 250 300 Frequency (kHz) Frequency (kHz) Figure11.PCM5101FFTPlotusinga1-kHztone(–60dBFS) Figure12.PCM5102FFTPlotusinga1-kHztone(–60dBFS) fromDCto300kHz fromDCto300kHz Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 9 Detailed Description 9.1 Overview The integrated PLL on the device provided adds the flexibility to remove the system clock (commonly known as masterclock),allowinga3-wireI2SconnectionandreducingsystemEMI. Powersense undervoltage protection utilizes a two-level mute system. Upon clock error or system power failure, thedevicedigitallyattenuatesthedata(orlastknowngooddata)andthenmutestheanalogcircuit. Compared with existing DAC technology, the PCM510xA devices offer up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs. (from traditional 100-kHz OBN measurements to 3 MHz). The PCM510xA devices accept industry-standard audio data formats with 16- to 32-bit data. Sample rates up to 384kHzaresupported. 9.2 Functional Block Diagram DIN (i2s) Audio Interface 8x Interpolation Filter û(cid:8)(cid:3)32bit Modulator CSDCSDeeuAuAggrrCCrrmmeenneettnntt I/VI/V Analog Analog MuteMute LINE OUT Zero Data Advanced Mute Control Detector Clock Halt PCM510xA Detection LRCK CPVDD (3.3V) Power AVDD (3.3V) BCK PLL Clock Supply DVDD (1.8V or 3.3V) SCK UVP/Reset POR Ch. Pump GND VCC NAA EPP GMP 9.3 Feature Description 9.3.1 Terminology Sampling frequency is symbolized by f . Full scale is symbolized by FS. Sample time as a unit is symbolized by S t . S 9.3.2 AudioDataInterface 9.3.2.1 AudioSerialInterface The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM510xA on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK polarityforleft/rightisgivenbytheformatselected. 14 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 Feature Description (continued) Table2.PCM510xAAudioDataFormats,BitDepthsandClockRates MAXLRCK CONTROLMODE FORMAT DATABITS SCKRATE[xf ] BCKRATE[xf ] FREQUENCY[f ] S S S 128–3072 Upto192kHz 64,48,32 HardwareControl I2S/LJ 32,24,20,16 (≤50MHz) 384kHz 64,128 64,48,32 The PCM510xA requires the synchronization of LRCK and system clock, but does not need a specific phase relationbetweenLRCKandsystemclock. If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level untilresynchronizationbetweenLRCKandsystemclockiscompleted. If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation (using an onchip oscillator) is initialized within one sample period and analog outputs are forced to the bipolar zero level untilresynchronizationbetweenLRCKandBCKiscompleted. 9.3.2.2 PCMAudioDataFormats The PCM510xA supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected using the FMT (pin 16), Low for I2S, and High for Left-justified. All formats require binary twos-complement,MSB-firstaudiodata;upto32-bitaudiodataisaccepted. 1t S R-channel LRCK L-channel BCK Audio data word = 16-bit, BCK = 32, 48, 64f S 1 2 15 16 1 2 15 16 DATA MSB LSB MSB LSB Audio data word = 24-bit, BCK = 48, 64f S - , 1 2 2 24 1 2 23 24 DATA MSB LSB MSB LSB Audio data word = 32-bit, BCK = 64f S 1 2 31 32 1 2 31 32 DATA MSB LSB MSB LSB Figure13. LeftJustifiedAudioDataFormat Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 1t S LRCK L-channel R-channel BCK Audio data word = 16-bit, BCK = 32, 48, 64f S 1 2 15 16 1 2 15 16 DATA MSB LSB MSB LSB Audio data word = 24-bit, BCK = 48, 64f S 1 2 23 24 1 2 23 24 DATA MSB LSB MSB LSB Audio data word = 32-bit, BCK = 64f S 1 2 31 32 1 2 31 32 DATA MSB LSB MSB LSB I2SDataFormat;L-channel=LOW,R-channel=HIGH Figure14. I2SAudioDataFormat 9.3.2.3 ZeroDataDetect The PCM510xA has a zero-data detect function. When the device detects continuous zero data, it enters a full analog mute condition. The PCM510xA counts zero data over 1024 LRCKs (21ms @ 48kHz) before setting analogmute. In Hardware mode, the device uses default values. By default, Both L-ch and R-ch have to be zero data for zero datadetectiontobeginthemutingprocessetc. 9.3.3 XSMTPin(SoftMute/SoftUn-Mute) An external digital host controls the PCM510xA soft mute function by driving the XSMT pin with a specific minimum rise time (t) and fall time (t) for soft mute and soft un-mute. The PCM510xA requires t and t times of r f r f less than 20ns. In the majority of applications, this is no problem, however, traces with high capacitance may haveissues. When the XSMT pin is shifted from high to low (3.3 V to 0 V), a soft digital attenuation ramp begins. –1-dB attenuationisthenappliedeverysampletimefrom0dBFSto –∞.Thesoftattenuationramptakes104samples. When the XSMT pin is shifted from low to high (0 V to 3.3 V), a soft digital “un-mute” is started. 1-dB gain steps areappliedeverysampletimefrom–∞to0dBFS.Theun-mutetakes104samples. InsystemswhereXSMTisnotrequired,itcanbedirectlyconnectedtoAVDD. 16 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 9.3.4 AudioProcessing 9.3.4.1 InterpolationFilter ThePCM510xAprovidestwotypesofinterpolationfilter.UserscanselectwhichfiltertousebyusingtheFLTpin (pin11). Table3.DigitalInterpolationFilterOptions FLTPin Description 0 FIRnormalx8/x4/x2/x1interpolationfilters 1 IIRlow-latencyx8/x4/x2/x1interpolationfilters Thenormalx8/x4/x2/x1(bypass)interpolationfilterisprogrammedforsampleratesfrom8kHzto384kHz. Table4.Normalx8InterpolationFilter Parameter Condition Value(Typ) Value(Max) Units Filtergainpassband 0…….0.45f ±0.02 dB S Filtergainstopband 0.55f …..7.455f –60 dB S S Filtergroupdelay 22t s S 0 1.0 0.8 −20 0.6 −40 mplitude (dB) −60 mplitude (FFS) 00..24 A A −80 0.0 −100 −0.2 −120 −0.4 0 1 2 3 4 0 50 100 150 200 250 300 350 400 Frequency (xfS) Samples G012 G023 Figure15.Normalx8InterpolationFilterFrequency Figure16.Normalx8InterpolationFilterImpulse Response Response Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 0.05 0.04 0.03 0.02 B) 0.01 d e ( ud 0.00 plit m A −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.1 0.2 0.3 0.4 0.5 Frequency (xfS) G034 Figure17.Normalx8InterpolationFilterPassbandRipple 18 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 Thenormalx4/x2/x1(bypass)interpolationfilterisprogrammedforsampleratesfrom8kHzto384kHz. Table5.Normalx4InterpolationFilter Parameter Condition Value(Typ) Value(Max) Units Filtergainpassband 0…….0.45f ±0.02 dB S Filtergainstopband 0.55f …..7.455f –60 dB S S Filtergroupdelay 22t s S 0 1.0 0.8 −20 0.6 −40 mplitude (dB) −60 mplitude (FFS) 00..24 A A −80 0.0 −100 −0.2 −120 −0.4 0 1 2 3 4 0 20 40 60 80 100 120 140 160 Frequency (xfS) Samples G009 G020 Figure18.Normalx4InterpolationFilterFrequency Figure19.Normalx4InterpolationFilterImpulse Response Response 0.05 0.04 0.03 0.02 B) 0.01 d e ( ud 0.00 plit m A −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.5 1.0 Frequency (xfS) G031 Figure20.Normalx4InterpolationFilterPassbandRipple Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com Table6.Normalx2InterpolationFilter Parameter Condition Value(Typ) Value(Max) Units Filtergainpassband 0…….0.45f ±0.02 dB S Filtergainstopband 0.55f …..7.455f –60 dB S S Filtergroupdelay 22t s S 0 1.0 0.8 −20 0.6 −40 mplitude (dB) −60 mplitude (FFS) 00..24 A A −80 0.0 −100 −0.2 −120 −0.4 0 1 2 3 4 0 10 20 30 40 50 60 70 80 90 100 Frequency (xfS) Samples G006 G017 Figure21.Normalx2InterpolationFilterFrequency Figure22.Normalx2InterpolationFilterImpulse Response Response 0.05 0.04 0.03 0.02 B) 0.01 d e ( ud 0.00 plit m A −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.5 1.0 1.5 2.0 Frequency (xfS) G028 Figure23.Normalx2InterpolationFilterPassbandRipple 20 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 The low-latency x8 / x4 / x2 / x1 (bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz. Table7.LowLatencyx8InterpolationFilter Parameter Condition Value(Typ) Units Filtergainpassband 0…….0.45f ±0.0001 dB S Filtergainstopband 0.55f …..7.455f –52 dB S S Filtergroupdelay 3.5t s S 0 1.0 0.8 −20 0.6 −40 mplitude (dB) −60 mplitude (FFS) 00..24 A A 0.0 −80 −0.2 −100 −0.4 −120 −0.6 0 1 2 3 4 0 50 100 150 200 250 300 350 400 Frequency (xfS) Samples G011 G022 Figure24.LowLatencyx8InterpolationFilterFrequency Figure25.LowLatencyx8InterpolationFilterImpulse Response Response 0.00010 0.00008 0.00006 0.00004 B) 0.00002 d e ( ud 0.00000 plit m A−0.00002 −0.00004 −0.00006 −0.00008 −0.00010 0.0 0.1 0.2 0.3 0.4 0.5 Frequency (xfS) G033 Figure26.LowLatencyx8InterpolationFilterPassbandRipple Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com Table8.LowLatencyx4InterpolationFilter Parameter Condition Value(Typ) Units Filtergainpassband 0…….0.45f ±0.0001 dB S Filtergainstopband 0.55f …..3.455f –52 dB S S Filtergroupdelay 3.5t s S 0 1.0 0.8 −20 0.6 −40 mplitude (dB) −60 mplitude (FFS) 00..24 A A 0.0 −80 −0.2 −100 −0.4 −120 −0.6 0 1 2 3 4 0 20 40 60 80 100 120 140 160 180 Frequency (xfS) Samples G008 G019 Figure27.LowLatencyx4InterpolationFilterFrequency Figure28.LowLatencyx4InterpolationFilterImpulse Response Response 0.0001 0.00008 0.00006 0.00004 B) 0.00002 d e ( ud 0 plit m A−0.00002 −0.00004 −0.00006 −0.00008 −0.0001 0.0 0.5 1.0 Frequency (xfS) G030 Figure29.LowLatencyx4InterpolationFilterPassbandRipple 22 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 Table9.LowLatencyx2InterpolationFilter Parameter Condition Value(Typ) Units Filtergainpassband 0…….0.45f ±0.0001 dB S Filtergainstopband 0.55f …..1.455f –52 dB S S Filtergroupdelay 3.5t s S space 0 1.0 0.8 −20 0.6 −40 mplitude (dB) −60 mplitude (FFS) 00..24 A A −80 0.0 −100 −0.2 −120 −0.4 0 1 2 3 4 0 10 20 30 40 50 60 70 80 90 100 Frequency (xfS) Samples G005 G016 Figure30.LowLatencyx2InterpolationFilterFrequency Figure31.LowLatencyx2InterpolationFilterImpulse Response Response 0.0001 0.00008 0.00006 0.00004 B) 0.00002 d e ( ud 0 plit m A−0.00002 −0.00004 −0.00006 −0.00008 −0.0001 0.0 0.5 1.0 Frequency (xfS) G030 Figure32.LowLatencyx2InterpolationFilterPassbandRipple Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 9.3.5 ResetandSystemClockFunctions 9.3.5.1 ClockingOverview The PCM510xA devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the serial audio interfaceinoneformoranother. The data flows at the sample rate (f ). Once the data is brought into the serial audio interface, it gets processed, S interpolated and modulated all the way to 128 × f before arriving at the current segments for the final digital to S analogconversion. The serial audio interface typically has 4 connections SCK (system master clock), BCK (bit clock), LRCK (left right word clock) and DIN (data). The device has an internal PLL that is used to take either SCK or BCK and createthehigherrateclocksrequiredbytheinterpolatingprocessorandtheDACclock.Thisallowsthedeviceto operatewithorwithoutanexternalSCK. 9.3.5.2 ClockSlaveModeWithMaster/SystemClock(SCK)Input(4WireI2S) The PCM510xA requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input and supports up to 50 MHz. The PCM510xA system- clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz - 44.1 kHz - 48 kHz), (88.2kHz - 96kHz), (176.4 kHz - 192 kHz), and 384 kHz with ±4% tolerance are supported. Values in the parentheses are grouped when detected, e.g. 88.2kHZ and 96kHzaredetectedas"doublerate,"32kHz,44.1kHzand48kHzwillbedetectedas"singlerate". The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 10 shows examples of system clock frequencies for common audiosamplingrates. SCK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in software mode, available only in the PCM512x, PCM514x, and PCM5242 devices, by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz [LRCK]and2.8224MHz[BCK]). Table10.SystemMasterClockInputsforAudioRelatedClocks Sampling SystemClockFrequency(fSCK)(MHz) Frequency 64fS 128fS 192fS 256fS 384fS 512fS 768fS 1024fS 1152fS 1536fS 2048fS 3072fS 8kHz –(1) 1.024(2) 1.536(2) 2.048 3.072 4.096 6.144 8.192 9.216 12.288 16.384 24.576 16kHz –(1) 2.048(2) 3.072(2) 4.096 6.144 8.192 12.288 16.384 18.432 24.576 36.864 49.152 32kHz –(1) 4.096(2) 6.144(2) 8.192 12.288 16.384 24.576 32.768 36.864 49.152 –(1) –(1) 44.1kHz –(1) 5.6488(2) 8.4672(2) 11.2896 16.9344 22.5792 33.8688 45.1584 –(1) –(1) –(1) –(1) 48kHz –(1) 6.144(2) 9.216(2) 12.288 18.432 24.576 36.864 49.152 –(1) –(1) –(1) –(1) 88.2kHz –(1) 11.2896(2) 16.9344 22.5792 33.8688 45.1584 –(1) –(1) –(1) –(1) –(1) –(1) 96kHz –(1) 12.288(2) 18.432 24.576 36.864 49.152 –(1) –(1) –(1) –(1) –(1) –(1) 176.4kHz –(1) 22.579 33.8688 45.1584 –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) 192kHz –(1) 24.576 36.864 49.152 –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) 384kHz 24.576 49.152 –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) (1) Thissystemclockrateisnotsupportedforthegivensamplingfrequency. (2) ThissystemclockrateissupportedbyPLLmode. 24 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 9.3.5.3 ClockSlaveModewithBCKPLLtoGenerateInternalClocks(3-WirePCM) The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagneticinterference. TheinternalPLLisdisabledassoonasanexternalSCKissupplied. The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock. Table 11 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internalSCK. Table11.BCKRates(MHz)byLRCKSampleRatefor PCM510xAPLLOperation BCK(f ) S Samplef(kHz) 32 64 8 – – 16 – 1.024 32 1.024 2.048 44.1 1.4112 2.8224 48 1.536 3.072 96 3.072 6.144 192 6.144 12.288 384 12.288 24.576 9.4 Device Functional Modes 9.4.1 ExternalSCKandPLLActivation As discussed in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM), the internal PLL of aPCM510xAdevicesuppliesaSCKifanexternalSCKisnotpresentatpowerup. 9.4.1.1 InterpolationFilterModes Interpolation-filteroptionsarecontrolledbytheFLTpin.SeeTable3. 9.4.1.2 44.1kHzDe-emphasis De-emphasiscontrolfor44.1-kHzf iscontrolledbytheDEMPpin.SeePinConfigurationandFunctions. S 9.4.1.3 AudioFormat AudioformatisselectedbytheFMTpin.SeePinConfigurationandFunctions. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 10 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information 10.1.1 TypicalApplications FLT DEMP udio Source SBDCCINKK PCM510x AOAGVUDNTRDD 0.1mF + 10mF3.3VAAGND 470W 2.2nFRight Channel Line Output A CM LRCK OUTL P AGND FMT VNEG Mute Circuit XSMT CAPM 2.2mF 2.2mF Left Channel Line Output LDOO CPGND 470W 2.2nF 10mF+ 0.1mF DGND CAPP 0.1mF+ 10mF3.3VAAGND AGND DVDD CPVDD 3.3V 10mF+ 0.1mF Figure33. SimplifiedSchematic,Hardware-ControlledSubsystem 10.1.1.1 ExampleDesignRequirements • Devicecontrolmethod:hardwarecontrol – Normalfilterlatency – I2Sdigitalaudiointerface – Powerrailmonitoringfromthesystem12-Vrailtomuteearlyonsystempowerloss • Single-ended2.1-V analogoutputs RMS • 3-wireI2Sinterface(BCKPLL) • Single3.3-Vsupply 10.1.1.2 DetailedDesignProcedure • Devicecontrolmethod:SeePinConfigurationandFunctionsandAudioProcessing. – Normalfilterlatency:FLTpintiedlow – Audioformatselection:FMTpintiedlow • Clock and PLL setup (See Reset and System Clock Functions). Ensure incoming BCK meets minimum requirements. • XSMTpinsetupfor12-Vmonitoring(SeeExternalPowerSenseUndervoltageProtectionMode). • Single-supply3.3-Voperation(SeeSettingDigitalPowerSuppliesandI/OVoltageRails) 26 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 Application Information (continued) 10.1.1.3 ApplicationCurve -20 -40 -60 B) d e ( -80 d u plit -100 m A -120 -140 -160 0 5 10 15 20 Frequency (kHz) Figure34. PCM5101AFFTPlot,DCto20kHzwitha1kHz, –60dBFSInput Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 11 Power Supply Recommendations 11.1 Power Supply Distribution and Requirements ThePCM510xAdevicesarepoweredthroughthefollowingpins: AVDD 3.3V CPVDD 3.3V DVDD (1.8V or 3.3v) LDOO 1.8V DAC Charge Pump Digital IO ((cid:24)^DWi[g(cid:144)i,t aLlo Cgoicr eetc) Reference Oscillator Analog Circuits PLL 1.8V LDO Clock Halt Detect Digital Circuits Line Driver Power Circuits PCM186x Figure35. PowerDistributionTreewithinPCM510xA Table12.PowerSupplyPinDescriptions NAME USAGE/DESCRIPTION AVDD Analogvoltagesupply;mustbe3.3V.ThispowersallanalogcircuitrythattheDACrunson. DVDD Digitalvoltagesupply.ThisisusedastheI/OvoltagecontrolandtheinputtotheonchipLDO. CPVDD ChargePumpVoltageSupply-mustbe3.3V OutputfromtheonchipLDO.Shouldbeusedwitha0.1-µFdecouplingcap.Canbedriven(usedaspower LDOO input)witha1.8-VsupplytobypasstheonchipLDOforlowerpowerconsumption. AGND Analogground DGND Digitalground 11.2 Recommended Powerdown Sequence Under certain conditions, the PCM510xA devices can exhibit some pop on power down. Pops are caused by a devicenothavingenoughtimetodetectpowerlossandstartthemutingprocess. The PCM510xA devices have two auto-mute functions to mute the device upon power loss (intentional or unintentional). XSMT=0 When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog mute.Thisprocesstakes150sampletimes(t )+0.2ms. s Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192 kHz will mute muchfasterthana48-kHzsystem. ClockErrorDetect When clock error is detected on the incoming data clock, the PCM510xA devices switch to an internal oscillator, and continue to the drive the output, while attenuating the data from the last known value. Once this process is complete,thePCM510xAoutputsarehardmutedtoground. 11.2.1 PlannedShutdown These auto-muting processes can be manipulated by system designs to mute before power loss in the following ways: 1. AssertXSMTlow150t +0.2msbeforepowerisremoved. S 28 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 Recommended Powerdown Sequence (continued) 3.3V VDD 0V 150tS+ 0.2ms High XSMT Low High I2S Clocks SCK,BCK,LRCK Low Time Figure36. AssertXSMT 2. StopI2Sclocks(SCK,BCK,LRCK)3msbeforepowerdownasshowninFigure37. 3.3V VDD 0V High XSMT Low 3 ms High I2S Clocks SCK,BCK,LRCK Low Time Figure37. StopI2CClocks 11.2.2 UnplannedShutdown Many systems use a low-noise regulator to provide an AVDD 3.3-V supply for the DAC. The XSMT Pin can take advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output before the entire SMPS discharges. Figure 38 shows how to configure such a system to use the XSMT pin. The XSMTpincanalsobeusedinparallelwithaGPIOpinfromthesystemmicrocontroller/DSPorpowersupply. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com Recommended Powerdown Sequence (continued) MCU GPIO “mute”signal GND XSMT 110V/ 220V Linear PCM5xxx SMPS 6V 3.3V Regulator Audio DAC 10 F GND GND Figure38. UsingtheXSMTPin 11.3 External Power Sense Undervoltage Protection Mode NOTE External Power Sense Undervoltage Protection Mode is supported only when DVDD = 3.3 V. The XSMT pin can also be used to monitor a system voltage, such as the 24-VDC LCD TV backlight, or 12-VDC systemsupplyusingavoltagedividercreatedwithtworesistors.(SeeFigure39) • If the XSMT pin makes a transition from “1” to “0” over 6 ms or more, the device switches into external under- voltageprotectionmode.Thismodeusestwotriggerlevels: – WhentheXSMTpinlevelreaches2V,softmuteprocessbegins. – When the XSMT pin level reaches 1.2 V, analog mute engages, regardless of digital audio level, and analogshutdownbegins.(DACandrelatedcircuitrypowersdown). If XSMT is moved from "1" to "0" in 20 ns or less, then the device will interpret it as a digital controlled request to mute.Itwillperformasoftmute,thenmovetostandby. AtimingdiagramtoshowthisisshowninFigure40. NOTE The XSMT input pin voltage range is from –0.3 V to DVDD+0.3 V. The ratio of external resistors must produce a voltage within this input range. Any increase in power supply (such as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD+0.3V. For example, if the PCM510xA is monitoring a 12-V input, and dividing the voltage by 4, then the voltage at XSMTduringidealpowersupplyconditionsis3.3V.Avoltagespikehigherthan14.4Vcausesavoltagegreater than3.6V(DVDD+0.3)ontheXSMTpin,potentiallydamagingthedevice. Providingthedividerissetappropriately,anyDCvoltagecanbemonitored. 30 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 External Power Sense Undervoltage Protection Mode (continued) System 12V VDD supply 7.25kW XSMT 2.75kW Figure39. XSMTinExternalUVPMode Digital Attenuation Followed by Analog Mute 0.9 * DVDD 2.0 V XSMT Analog Mute 1.2 V 0.1 * DVDD t f Figure40. XSMTTimingforUndervoltageProtection The trigger voltage values for the soft mute and hard mute are shown in Table 13. The range of values will vary from device to device, but typical thresholds are shown. XSMT should be set up to nominally be 3.3 V along with DVDD,butderivedfromahighersystempowersupplyrail. Table13.DistributionofVoltageThresholds MIN TYP MAX SoftMuteThreshold 2.0V 2.2V 0.9×DVDD Voltage HardMuteThreshold 0.1×DVDD 0.9V 1.2V Voltage Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 11.4 Power-On Reset Function Power-OnReset,DVDD3.3-VSupply The PCM510xA includes a power-on reset function shown in Figure 41. With V > 2.8 V, the power-on reset DD function is enabled. After the initialization period, the PCM510xA is set to its default reset state. Analog output will begin ramping after valid data has been passing through the device for the given group delay given by the digitalinterpolationfilterselected. 3.3V 2.8V AVDD, DVDD, CPVDD Internal Reset Reset Removal Internal Reset 4 ms I2S Clocks SCK, BCK, LRCK Figure41. Power-OnResetTiming,DVDD=3.3V Power-OnReset,DVDD1.8-VSupply The PCM510xA includes a power-on reset function shown in Figure 42 operating at DVDD = 1.8 V. With AVDD greater than approximately 2.8 V, CPVDD greater than approximately 2.8 V, and DVDD greater than approximately 1.5 V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set toitsdefaultresetstate. 3.3V 2.8V AVDD, CPVDD 1.8V 1.5V DVDD, LDOO Internal Reset Reset Removal Internal Reset 4 ms I2S Clocks SCK, BCK, LRCK Figure42. Power-OnResetTiming,DVDD=1.8V 32 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 11.5 PCM510xA Power Modes 11.5.1 SettingDigitalPowerSuppliesandI/OVoltageRails TheinternaldigitalcoreofthePCM510xAdevicesrunfroma1.8-Vsupply.Thiscanbegeneratedbytheinternal LDO,orbyanexternal1.8-Vsupply. DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V requiredbythedigitalcore. For systems that require 3.3 V I/O support, but lower power consumption, DVDD should be connected to 3.3 V andLDOOcanbeconnectedtoanexternal1.8-Vsource.DoingsowilldisabletheonchipLDO. WhensettingI/Ovoltagetobe1.8V,bothDVDDandLDOOmustbeprovidedwithanexternal1.8-Vsupply. 11.5.2 PowerSaveModes ThePCM510xAdevicesoffertwopower-savemodes:standbyandpower-down. When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510xA device automatically enters standbymode. TheDACandlinedriverarealsopowereddown. When BCK and LRCK remain at a low level for more than 1 second, the PCM510xA device automatically enters powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition tothosedisabledinstandbymode. When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA device, or if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup sequenceautomatically. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C–MAY2012–REVISEDMAY2015 www.ti.com 12 Layout 12.1 Layout Guidelines • The PCM510xA family of devices are simple to layout. Most engineers use a shared common ground for an entiredevice.GNDcanbeconsiderAGNDandDGNDconnected. • Good system partitioning should keep digital clock and interface traces away from the analog outputs for highest analog performance. This reduces any high speed clock return currents influencing the analog outputs. • Powersupplyandchargepumpdecouplingcapacitorsshouldbeplacedascloseaspossibletothedevice. • Thetoplayershouldbeusedforroutingsignals,whilstthebottomlayercanbeusedforGND. Bottom Layer Copper Fill (GND) Top Layer Copper Fill (GND) 3.3V 1 CPVDD DVDD 20 12V 2 CAPP DGND 19 3 CPGND LDOO 18 4 CAPM XSMT 17 5 VNEG FMT 16 6 OUTL LRCK 15 Direct to 7 OUTR DIN 14 Processor or 8 AVDD BCK 13 3.3V full high/low 9 AGND SCK 12 for control 10 DEMP FLT 11 pins Figure43. PCM510xLayoutExample 34 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C–MAY2012–REVISEDMAY2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table14.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY PCM5100A Clickhere Clickhere Clickhere Clickhere Clickhere PCM5101A Clickhere Clickhere Clickhere Clickhere Clickhere PCM5102A Clickhere Clickhere Clickhere Clickhere Clickhere PCM5100A-Q1 Clickhere Clickhere Clickhere Clickhere Clickhere PCM5101A-Q1 Clickhere Clickhere Clickhere Clickhere Clickhere PCM5102A-Q1 Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Community Resources E2E™AudioConvertersForumTI E2ECommunity 13.3 Trademarks DirectpathisatrademarkofTexasInstruments,Inc. SystemTwoCascade,AudioPrecisionaretrademarksofAudioPrecision. 13.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,seetheleft-handnavigation. 14.1 Mechanical Data Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:PCM5100A PCM5101A PCM5102APCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1

PACKAGE OPTION ADDENDUM www.ti.com 7-May-2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) PCM5100APW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A & no Sb/Br) PCM5100APWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A & no Sb/Br) PCM5100AQPWRQ1 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 P5100AQ1 & no Sb/Br) PCM5101APW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5101A & no Sb/Br) PCM5101APWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5101A & no Sb/Br) PCM5101AQPWRQ1 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 P5101AQ1 & no Sb/Br) PCM5102APW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A & no Sb/Br) PCM5102APWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A & no Sb/Br) PCM5102AQPWRQ1 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 P5102AQ1 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 7-May-2015 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF PCM5100A, PCM5100A-Q1, PCM5101A, PCM5101A-Q1, PCM5102A, PCM5102A-Q1 : •Catalog: PCM5100A, PCM5101A, PCM5102A •Automotive: PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) PCM5100APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5100AQPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5101APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5101AQPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5102APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5102AQPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) PCM5100APWR TSSOP PW 20 2000 350.0 350.0 43.0 PCM5100AQPWRQ1 TSSOP PW 20 2000 350.0 350.0 43.0 PCM5101APWR TSSOP PW 20 2000 350.0 350.0 43.0 PCM5101AQPWRQ1 TSSOP PW 20 2000 350.0 350.0 43.0 PCM5102APWR TSSOP PW 20 2000 350.0 350.0 43.0 PCM5102AQPWRQ1 TSSOP PW 20 2000 350.0 350.0 43.0 PackMaterials-Page2

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