PCM4220 PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 High-Performance, Two-Channel, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma Analog-to-Digital Converter FEATURES • DigitalHigh-PassFilteringRemovesDCOffset 1 • SupportsLinearPCMOutputData – LeftandRightChannelFiltersMayBe 234 – OutputSamplingRatesfrom8kHzto DisabledIndependently 216kHz • AudioSerialPortInterface • DifferentialVoltageInputs – MasterorSlaveModeOperation • On-ChipVoltageReferenceImproves – SupportsLeft-Justified,I2S™,andTDM Power-SupplyNoiseRejection DataFormats • DynamicPerformance(24-bitwordlength) • OutputWordLengthReduction – DynamicRange(–60dBinput,A-weighted): • OverflowIndicatorsfortheLeftandRight 123dBtypical Channels – DynamicRange(–60dBinput,20kHz • AnalogPowerSupply: bandwidth):121dBtypical +4.0Vnominal – TotalHarmonicDistortion+Noise • DigitalPowerSupply: (–1dBinput,20kHzbandwidth): +3.3Vnominal –108dBtypical • Power-DownMode:4mWtypical – ChannelSeparation:135dB • Package:TQFP-48,RoHScompliant • LowPowerDissipation: APPLICATIONS – 305mWtypicalfor48kHzsamplingrate • DigitalAudioRecordersand – 330mWtypicalfor96kHzsamplingrate MixingDesks – 340mWtypicalfor192kHzsamplingrate • DigitalLiveSoundConsoles • LinearPhaseDigitalDecimationFiltering • DigitalAudioEffectsProcessors – SelectfromClassicorLowGroupDelay • SurroundSoundEncoders FilterResponses • BroadcastStudioEquipment – LowPassbandRipple • DataAcquisitionand Classic:±0.00015dB MeasurementSystems LowGroupDelay:±0.001dB • AudioTestSystems blank • Sonar blank 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. WindowsisaregisteredtrademarkofMicrosoftCorporation. 2 I2SisatrademarkofNXPSemiconductor. 3 Allothertrademarksarethepropertyoftheirrespectiveowners. 4 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com DESCRIPTION The PCM4220 is a high-performance, two-channel analog-to-digital (A/D) converter designed for use in professional audio applications. Offering outstanding dynamic performance, the PCM4220 provides 24-bit linear PCM output data, with support for output word length reduction to 20-, 18-, or 16-bits. The PCM4220 includes three sampling modes, supporting output sampling rates from 8kHz to 216kHz. The PCM4220 is ideal for a varietyofdigitalaudiorecordingandprocessingapplications. Alinearphasedigitaldecimationfiltering engine supports Classic and Low Group Delay filter responses, allowing optimization for either studio or live sound applications. In addition, digital high-pass filtering is provided for DC offset removal. The The PCM4220 is configured using dedicated control pins for selection of sampling modes, audio data formats and word length, decimation filter response, high-pass filter disable, and reset/power-down functions. While providing uncompromising performance, the PCM4220 addresses power concerns with just over 300mW typical total power dissipation, making the device suitable for multi-channel audio systems. The PCM4220 is typically powered from a +4.0V analog supply and a +3.3V digital supply. The digital I/O is logic-level compatible with common digital signal processors, digital interface transmitters, and programmable logic devices. The PCM4220isavailableinaTQFP-48package,whichisRoHS-compliant. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthis datasheet,orseetheTIwebsiteatwww.ti.com ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. VALUE Powersupplies VCC1,VCC2 –0.3Vto+6.0V VDD –0.3Vto+4.0V Digitalinputvoltage AlldigitalinputandI/Opins –0.3V<(VDD+0.3V)<+4.0V Analoginputvoltage VINL+,VINL–,VINR+,VINR– –0.3V<(VCC+0.3V)<+6.0V Inputcurrent(allpinsexceptpowerandground) ±10mA Ambientoperatingtemperature –40°Cto+85°C Storagetemperature –65°Cto+150°C (1) Theselimitsarestressratingsonly.Stressesbeyondtheselimitsmayresultinpermanentdamage.Extendedexposuretoabsolute maximumratingsmaydegradedevicereliability.Normaloperationorperformanceatorbeyondtheselimitsisnotspecifiedorensured. 2 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 ELECTRICAL CHARACTERISTICS: DIGITAL AND DYNAMIC PERFORMANCE AllspecificationsareatT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITALI/OCHARACTERISTICS (Appliestoalldigitalpins) High-levelinputvoltage,VIH 0.7×VDD VDD V Low-levelinputvoltage,VIL 0 0.3×VDD V High-levelinputcurrent,IIH 1 10 m A Low-levelinputcurrent,IIL 1 10 m A High-leveloutputvoltage,VOH IO=–2mA 0.8×VDD VDD V Low-leveloutputvoltage,VOL IO=+2mA 0 0.2×VDD V Inputcapacitance,CIN 3 pF PCMOUTPUTSAMPLINGRATE,fS Normalmode 8 54 kHz DoubleSpeedmode 54 108 kHz QuadSpeedmode 108 216 kHz MASTERCLOCKINPUT Normalmode,MCKI=256fS 2.048 13.824 MHz DoubleSpeedmode,MCKI=128fS 6.912 13.824 MHz QuadSpeedmode,MCKI=64fS 6.912 13.824 MHz DYNAMICPERFORMANCE(1) PCMOutput,NormalMode,fS=48kHz BW=22Hzto20kHz Totalharmonicdistortion+noise(THD+N) f=997Hz,–1dBinput –108 –100 dB f=997Hz,–20dBinput –100 dB f=997Hz,–60dBinput –61 dB Dynamicrange,noweighting f=997Hz,–60dBinput 121 dB Dynamicrange,A-weighted f=997Hz,–60dBinput 118 123 dB Channelseparation f=10kHz,–1dBinput 115 135 dB PCMOutput,DoubleSpeedMode,fS=96kHz BW=22Hzto40kHz Totalharmonicdistortion+noise(THD+N) f=997Hz,–1dBinput –108 dB f=997Hz,–20dBinput –98 dB f=997Hz,–60dBinput –58 dB Dynamicrange,noweighting f=997Hz,–60dBinput 118 dB Dynamicrange,A-weighted f=997Hz,–60dBinput 123 dB Channelseparation f=10kHz,–1dBinput 135 dB PCMOutput,QuadSpeedMode,fS=192kHz BW=22Hzto40kHz Totalharmonicdistortion+noise(THD+N) f=997Hz,–1dBinput –107 dB f=997Hz,–20dBinput –98 dB f=997Hz,–60dBinput –58 dB Dynamicrange,noweighting f=997Hz,–60dBinput 118 dB Dynamicrange,A-weighted f=997Hz,–60dBinput 123 dB Channelseparation f=10kHz,–1dBinput 135 dB PCMOutput,QuadSpeedMode,fS=192kHz BW=22Hzto80kHz Totalharmonicdistortion+noise(THD+N) f=997Hz,–1dBinput –106 dB f=997Hz,–20dBinput –91 dB f=997Hz,–60dBinput –52 dB Dynamicrange,noweighting f=997Hz,–60dBinput 112 dB Dynamicrange,A-weighted f=997Hz,–60dBinput 123 dB Channelseparation f=10kHz,–1dBinput 135 dB (1) TypicalPCMoutputperformanceismeasuredandcharacterizedwithanAudioPrecisionSYS-2722192kHztestsystemanda PCM4222EVMevaluationmodulemodifiedforusewiththePCM4220.Measurementbandwidthandweightingsettingsarenotedinthe ParameterandConditionscolumns.THD+Nismeasuredwithouttheuseofweightingfilters.Mastermodeoperationisutilizedforall typicalperformanceparameters,withthemasterclockinputfrequency(MCKI)setto12.288MHz. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS: DIGITAL AND DYNAMIC PERFORMANCE (continued) AllspecificationsareatT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT DigitalDecimationFilterCharacteristics: ClassicResponse Passband 0.4535×fS Hz Passbandripple ±0.00015 dB Stopband 0.5465×fS Hz Stopbandattenuation –100 dB Groupdelay 39/fS Seconds DigitalDecimationFilterCharacteristics: LowGroupDelayResponse Passband 0.4167×fS Hz Passbandripple ±0.001 dB Stopband 0.5833×fS Hz Stopbandattenuation –90 dB Groupdelay 21/fS Seconds DigitalHigh-PassFilterCharacteristics –3dBcornerfrequency High-passfilterenabled fS/48000 Hz ELECTRICAL CHARACTERISTICS: ANALOG INPUTS, OUTPUTS, AND DC ERROR AllspecificationsareatT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOGINPUTS Full-scaleinputrange Differentialinput ReferencedfromVINL+toVINL–,orVINR+to 5.6 VPP VINR– Perinputpin AppliestoVINL+,VINL–,VINR+,orVINR– 2.8 VPP Inputimpedance AppliestoVINL+,VINL–,VINR+,orVINR– 2.8 kΩ Common-moderejection 100 dB ANALOGOUTPUTS Common-modeoutputvoltage Leftchannel,VCOML MeasuredfromVCOMLtoAGND 0.4875×VCC2 V Rightchannel,VCOMR MeasuredfromVCOMRtoAGND 0.4875×VCC1 V Common-modeoutputcurrent AppliestoVCOMLorVCOMR 200 m A DCERROR Outputoffseterror Digitalhigh-passfilterdisabled 3 mV Offsetdrift Digitalhigh-passfilterdisabled 3.5 m V/°C 4 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 ELECTRICAL CHARACTERISTICS: POWER SUPPLIES AllspecificationsareatT =+25°C,VCC1=VCC2=+4.0V,VDD=+3.3V,andMCKI=12.288MHz,unlessotherwisenoted. A PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT POWERSUPPLIES Recommendedsupplyvoltagerange VCC1,VCC2 0°C<TA≤+85°C +3.8 +4.0 +4.2 V VCC1,VCC2 –40°C≤TA≤0°C +3.9 +4.0 +4.2 V VDD –40°C≤TA≤+85°C +2.4 +3.3 +3.6 V Supplycurrent:power-down RST(pin36)heldlowwithnoclocksapplied ICC1+ICC2 VCC1=VCC2=+4.0V 600 m A IDD VDD=+3.3V 325 m A Supplycurrent:fS=48kHz ICC1+ICC2 VCC1=VCC2=+4.0V 65 75 mA IDD VDD=+3.3V 14 18 mA Supplycurrent:fS=96kHz ICC1+ICC2 VCC1=VCC2=+4.0V 65 mA IDD VDD=+3.3V 21 mA Supplycurrent:fS=192kHz ICC1+ICC2 VCC1=VCC2=+4.0V 65 mA IDD VDD=+3.3V 24 mA Totalpowerdissipation:power-down 3.5 mW Totalpowerdissipation:fS=48kHz 305 360 mW Totalpowerdissipation:fS=96kHz 330 mW Totalpowerdissipation:fS=192kHz 340 mW ELECTRICAL CHARACTERISTICS: AUDIO INTERFACE TIMING AllspecificationsareatT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT AUDIOSERIALPORT LRCKperiod,tLRCKP Alldataformats 4.62 125 m s LRCKhigh/lowtime,tLRCKHL Left-Justified,I2S,andTDMMastermode 0.45×tLRCKP 0.55×tLRCKP m s formats TDMslavemodeformats tBCKP 0.55×tLRCKP m s BCKperiod,tBCKP Left-JustifiedandI2Sdataformats Normalsamplingmode tLRCKP/128 ns DoubleSpeedsamplingmode tLRCKP/64 ns QuadSpeedsamplingmode tLRCKP/64 ns BCKperiod,tBCKP TDMdataformats Normalsamplingmode tLRCKP/256 ns DoubleSpeedsamplingmode tLRCKP/128 ns QuadSpeedsamplingmode tLRCKP/64 ns BCKhigh/lowtime,tBCKHL Alldataformats 0.45×tBCKP 0.55×tBCKP ns Dataoutputdelay,tDO Alldataformats 10 ns Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com LRCK t BCKHL BCK t BCKHL t DO DATA Figure1.AudioSerialPortTiming:Left-JustifiedandI2SDataFormats LRCK t BCKHL BCK t BCKHL t DO DATA Figure2.AudioSerialPortTiming:TDMDataFormats 6 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 PIN CONFIGURATION PFBPACKAGE TQFP-48 (TOPVIEW) R D VCOMR REFGN VREFR DGND FMT0 FMT1 OWL0 OWL1 DGND S/M OVFR OVFL 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 RST VINR- 2 35 MCKI VINR+ 3 34 LRCK VCC1 4 33 BCK AGND 5 32 DATA AGND 6 31 VDD PCM4220 AGND 7 30 DGND AGND 8 29 NC VCC2 9 28 NC VINL- 10 27 NC VINL+ 11 26 SUB0 AGND 12 25 SUB1 13 14 15 16 17 18 19 20 21 22 23 24 VCOML FGNDL VREFL PCMEN HPFDR HPFDL FS0 FS1 DF DGND DGND DGND E R TERMINALFUNCTIONS PIN NAME NO. I/O DESCRIPTION AGND 1 Ground Analogground VINR– 2 Input Rightchannelinverting,2.8V nominalfull-scale PP VINR+ 3 Input Rightchannelnoninverting,2.8V nominalfull-scale PP VCC1 4 Power Analogsupply,+4.0Vnominal AGND 5 Ground Analogground AGND 6 Ground Analogground AGND 7 Ground Analogground AGND 8 Ground Analogground VCC2 9 Power Analogsupply,+4.0Vnominal VINL– 10 Input Leftchannelinverting,2.8V nominalfull-scale PP VINL+ 11 Input Leftchannelnoninverting,2.8V nominalfull-scale PP AGND 12 Ground Analogground VCOML 13 Output Leftchannelcommon-modevoltage,(0.4875×VCC2)nominal REFGNDL 14 Ground Leftchannelreferenceground,connecttoanalogground VREFL 15 Output Leftchannelreferenceoutputfordecouplingpurposesonly PCMEN 16 Input PCMoutputenable(activehigh) HPFDR 17 Input Rightchannelhigh-passfilterdisable(activehigh) HPFDL 18 Input Leftchannelhigh-passfilterdisable(activehigh) Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com TERMINALFUNCTIONS(continued) PIN NAME NO. I/O DESCRIPTION Samplingmodes: FS0=0andFS1=0:Normalmode FS0 19 Input FS0=1andFS1=0:DoubleSpeedmode FS1 20 FS0=0andFS1=1:QuadSpeedmode FS0=1andFS1=1:ReservedSamplingmode Digitaldecimationfilterresponse: DF 21 Input DF=0:Classicfilterresponse DF=1:LowGroupDelayresponse DGND 22 Ground Digitalground DGND 23 Ground Digitalground DGND 24 Ground Digitalground TDMactivesub-frame: SUB0=0andSUB1=0:Sub-frame0 SUB1 25 Input SUB0=1andSUB1=0:Sub-frame1 SUB0 26 SUB0=0andSUB1=1:Sub-frame2 SUB0=1andSUB1=1:Sub-frame3 NC 27 — Noexternalconnection,internallybondedtoESDpad NC 28 — Noexternalconnection,internallybondedtoESDpad NC 29 — Noexternalconnection,internallybondedtoESDpad DGND 30 Ground Digitalground VDD 31 Power Digitalsupply,+3.3Vnominal DATA 32 Output Audioserialportdata BCK 33 I/O Audioserialportbitclock LRCK 34 I/O Audioserialportleft/rightwordclock MCKI 35 Input Masterclock RST 36 Input Resetandpower-down(activelow) OVFL 37 Output Leftchanneloverflowflag(activehigh) OVFR 38 Output Rightchanneloverflowflag(activehigh) AudioserialportSlave/Mastermode: S/M 39 Input S/M=0:Mastermode S/M=1:Slavemode DGND 40 Output Digitalground Outputwordlength: OWL0=0andOWL1=0:24-bits OWL1 41 Input OWL0=1andOWL1=0:18-bits OWL0 42 OWL0=0andOWL1=1:20-bits OWL0=1andOWL1=1:16-bits Audiodataformat: FMT0=0andFMT1=0:Left-justified FMT1 43 Input FMT0=1andFMT1=0:I2S FMT0 44 FMT0=0andFMT1=1:TDM FMT0=1andFMT1=1:TDMwithoneBCKdelay DGND 45 Ground Digitalground VREFR 46 Output Rightchannelreferenceoutputfordecouplingpurposesonly REFGNDR 47 Ground Rightchannelreferenceground,connecttoanalogground VCOMR 48 Output Rightchannelcommon-modevoltage(0.4875×VCC1nominal) 8 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 TYPICAL CHARACTERISTICS AtT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A FFTPLOT FFTPLOT 0 0 f = 48kHz f = 48kHz -20 S -20 S f = 997kHz,-60dB Idle Channel (no input) IN -40 -40 B) -60 B) -60 d d e ( -80 e ( -80 d d u u plit -100 plit -100 m m A -120 A -120 -140 -140 -160 -160 -180 -180 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Figure3. Figure4. THD+NvsINPUTFREQUENCY THD+NvsINPUTAMPLITUDE -60 -60 f = 48kHz f = 48kHz S S -70 Input Amplitude =-1dB -70 fIN= 997Hz BW = 22Hz to 20kHz BW = 22Hz to 20kHz -80 -80 B) FS) d -90 B -90 +N ( N (d D -100 + -100 H D T H T -110 -110 -120 -120 -130 -130 20 100 1k 10k 20k -140 -120 -100 -80 -60 -40 -20 0 Input Frequency (Hz) Input Amplitude (dB) Figure5. Figure6. CHANNELSEPARATIONvsINPUTFREQUENCY LINEARITY 0 0 -20 fS= 48kHz Left Channel fS= 48kHz -20 -40 Right Channel B) n (d -60 S) -40 annel Separatio ---111-02480000 Linearity (dBF -1--068000 h C -160 -120 -180 -200 -140 0 2 4 6 8 10 12 14 16 18 20 -140 -120 -100 -80 -60 -40 -20 0 Input Frequency (kHz) Input Amplitude (dB) Figure7. Figure8. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A FFTPLOT FFTPLOT 0 0 f = 96kHz f = 96kHz -20 fS = 997Hz,-60dB -20 ISdle Channel (no input) IN -40 -40 B) -60 B) -60 d d e ( -80 e ( -80 d d u u plit -100 plit -100 m m A -120 A -120 -140 -140 -160 -160 -180 -180 20 100 1k 10k 50k 20 100 1k 10k 50k Frequency (Hz) Frequency (Hz) Figure9. Figure10. THD+NvsINPUTFREQUENCY THD+NvsINPUTAMPLITUDE -60 -60 fS= 96kHz fS= 96kHz -70 Input Amplitude =-1dB -70 fIN= 997Hz BW = 22Hz to 40kHz BW = 22Hz to 40kHz -80 -80 B) FS) d -90 B -90 +N ( N (d D -100 + -100 H D T H T -110 -110 -120 -120 -130 -130 20 100 1k 10k 40k -140 -120 -100 -80 -60 -40 -20 0 Input Frequency (Hz) Input Amplitude (dB) Figure11. Figure12. CHANNELSEPARATIONvsINPUTFREQUENCY LINEARITY 0 0 -20 fS= 96kHz Left Channel fS= 96kHz -20 -40 Right Channel B) n (d -60 S) -40 paratio -1-0800 y (dBF -60 annel Se --112400 Linearit -1-0800 h C -160 -120 -180 -200 -140 0 5 10 15 20 25 30 35 40 -140 -120 -100 -80 -60 -40 -20 0 Input Frequency (kHz) Input Amplitude (dB) Figure13. Figure14. 10 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 TYPICAL CHARACTERISTICS (continued) AtT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A FFTPLOT FFTPLOT 0 0 f = 192kHz f = 192kHz -20 fS = 997Hz,-60dB -20 IdSle Channel (no input) IN -40 -40 B) -60 B) -60 d d e ( -80 e ( -80 d d u u plit -100 plit -100 m m A -120 A -120 -140 -140 -160 -160 -180 -180 20 100 1k 10k 100k 20 100 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure15. Figure16. THD+NvsINPUTFREQUENCY THD+NvsINPUTAMPLITUDE -60 -60 fS= 192kHz fS= 192kHz -70 Input Amplitude =-1dB -70 f = 997Hz IN BW = 22Hz to 80kHz BW = 22Hz to 80kHz -80 -80 B) FS) d -90 B -90 +N ( N (d D -100 + -100 H D T H T -110 -110 -120 -120 -130 -130 20 100 1k 10k 80k -140 -120 -100 -80 -60 -40 -20 0 Input Frequency (Hz) Input Amplitude (dB) Figure17. Figure18. CHANNELSEPARATIONvsINPUTFREQUENCY LINEARITY 0 0 -20 fS= 192kHz Left Channel fS= 192kHz -20 -40 Right Channel B) n (d -60 S) -40 paratio -1-0800 y (dBF -60 annel Se --112400 Linearit -1-0800 h C -160 -120 -180 -200 -140 0 10 20 30 40 50 60 70 80 -140 -120 -100 -80 -60 -40 -20 0 Input Frequency (kHz) Input Amplitude (dB) Figure19. Figure20. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A FREQUENCYRESPONSE FREQUENCYRESPONSE (Upto20kHz) (Upto40kHz) 0 0 f = 48kHz f = 96kHz S S -0.2 Classic or Low Group Delay Response -0.2 Classic or Low Group Delay Response -0.4 High-Pass Filter Enabled -0.4 High-Pass FilterEnabled Input Amplitude =-1dB Input Amplitude =-1dB -0.6 -0.6 B) B) d -0.8 d -0.8 e ( e ( d -1.0 d -1.0 u u plit -1.2 plit -1.2 m m A -1.4 A -1.4 -1.6 -1.6 -1.8 -1.8 -2.0 -2.0 20 100 1k 10k 20k 20 100 1k 10k 40k Frequency (Hz) Frequency (Hz) Figure21. Figure22. FREQUENCYRESPONSE DIGITALDECIMATIONFILTER,CLASSICRESPONSE (Upto80kHz) OverallFrequencyResponse 0 50 f = 192kHz f = 48kHz -0.2 S S High-Pass Filter Enabled Overall Frequency Response -0.4 Input Amplitude =-1dB 0 -0.6 B) B) mplitude (d ---011...802 mplitude (d -1-0500 A -1.4 A -1.6 -150 -1.8 -2.0 -200 20 100 1k 10k 80k 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Frequency (Hz) Normalized Frequency (f ) S Figure23. Figure24. DIGITALDECIMATIONFILTER,CLASSICRESPONSE DIGITALDECIMATIONFILTER,CLASSICRESPONSE StopBandDetail PassbandRippleDetail 0 2 1 0) e (dB) -50 B/10,00 0 d d -1 plitu de ( m u A -100 plit -2 m A -3 f = 48kHz S Passband Ripple Detail -150 -4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Normalized Frequency (f ) Normalized Frequency (f ) S S Figure25. Figure26. 12 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 TYPICAL CHARACTERISTICS (continued) AtT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A DIGITALDECIMATIONFILTER,LOWGROUPDELAY DIGITALDECIMATIONFILTER,CLASSICRESPONSE RESPONSE TransitionBandDetail OverallFrequencyResponse 0 0 f = 48kHz (fast mode) S Overall Frequency Response -1 -50 B) -2 B) d d e ( e ( d -3 d -100 u u plit plit m m A -4 A -150 -5 f = 48kHz S Transition Band Detail -6 -200 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency (f ) Normalized Frequency (f ) S S Figure27. Figure28. DIGITALDECIMATIONFILTER,LOWGROUPDELAY DIGITALDECIMATIONFILTER,LOWGROUPDELAY RESPONSE RESPONSE StopBandDetail PassbandRippleDetail 0 2.0 f = 48kHz (fast mode) -10 S 1.5 Passband Ripple Detail -20 1.0 -30 0) dB) -40 100 0.5 Amplitude ( ---567000 mplitude (dB/ -0.05 A -1.0 -80 -90 fS= 48kHz (fast mode) -1.5 Stop Band Detail -100 -2.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Normalized Frequency (f ) Normalized Frequency (f ) S S Figure29. Figure30. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) AtT =+25°C,VCC1=VCC2=+4.0V,andVDD=+3.3V,unlessotherwisenoted. A DIGITALDECIMATIONFILTER,LOWGROUPDELAY RESPONSE DIGITALHIGH-PASSFILTER TransitionBandDetail PassbandResponse 0 0.6 High-Pass FilterPassband -0.5 0.4 -1.0 0.2 B) -1.5 B) d d e ( e ( 0 d -2.0 d u u mplit -2.5 mplit -0.2 A A -0.4 -3.0 -3.5 fS= 48kHz (fast mode) -0.6 Transition Band Detail -4.0 -0.8 0.30 0.35 0.40 0.45 0.50 0.55 0.60 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency (f ) Normalized Frequency (f /1000) S S Figure31. Figure32. DIGITALHIGH-PASSFILTER StopBandResponse 0 -20 -40 B) e (d -60 d u plit -80 m A -100 -120 High-Pass FilterStop Band -140 0 0.05 0.10 0.15 0.20 0.25 0.30 Normalized Frequency (f /1000) S Figure33. 14 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 PRODUCT OVERVIEW The PCM4220 is a two-channel, multi-bit delta-sigma (ΔΣ) A/D converter. The 6-bit output from the delta-sigma modulators is routed to the digital decimation filter, where the output of the filter provides linear PCM data. The linear PCM data are output at the audio serial port interface for connection to external processing and logic circuitry. Figure 34 shows a simplified functional block diagram for the PCM4220, highlighting the interconnections betweenthevariousfunctionalblocks. DF HPFDL HPFDR VINL+ Audio LRCK Multi-Bit Digital Serial BCK Delta-Sigma Filters VINL- Port DATA S/M FMT0 VREFL FMT1 REFGNDL OWL0 VCOML Control OWL1 Reference SUB0 and VCOMR SUB1 Status REFGNDR PCMEN VREFR FS0 FS1 OVFL OVFR VINR+ Multi-Bit Delta-Sigma VINR- Reset Master Clock RST MCKI Logic and Timing VCC1VCC2 AGNDAGNDAGNDAGNDAGNDAGND DGNDDGNDDGNDDGNDDGNDDGND VDD Figure34.FunctionalBlockDiagram Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com ANALOG INPUTS The PCM4220 includes two analog inputs, referred to as the left and right channels. Each channel includes a pair of differential voltage input pins. The left channel inputs are named VINL– (pin 10) and VINL+ (pin 11), respectively. The right channel inputs are named VINR– (pin 2) and VINR+ (pin 3), respectively. Each pin of an input pair has a nominal full-scale input of 2.8V . The full-scale input for a given pair is specified as 5.6V PP PP differentialintheElectrical Characteristics table. Figure 35shows the full-scale input range of the PCM4220, with theinputsignalscenteredonthenominalcommon-modevoltageof+1.95V. In a typical application, the front end is driven by a buffer amplifier or microphone/line level preamplifier. Examples are given in the Input Buffer Circuits section of this datasheet. The analog inputs of the PCM4220 may be driven up to the absolute maximum input rating without instability. If the analog input voltage is expected to exceed the absolute maximum input ratings in a given application, it is recommended that input clamping or limiting be added to the analog input circuitry prior to the PCM4220 in order to provide protection against damaging the device. Specifications for the analog inputs are given in the Electrical Characteristics and Absolute MaximumRatingstablesofthisdatasheet. 2.8V Full-Scale PP VINL+ or +1.95V VINR+ VINL- or +1.95V VINR- 2.8V Full-Scale PP Figure35.Full-ScaleAnalogInputRange VOLTAGE REFERENCE The PCM4220 includes an on-chip, band-gap voltage reference. The band-gap output voltage is buffered and then routed to the two delta-sigma modulators. The inclusion of an on-chip reference circuit enhances the power-supply noise rejection of the PCM4220. The buffered reference voltage for each channel is filtered using external capacitors. The capacitors are connected between VREFL (pin 15) and REFGNDL (pin 14) for the left channel, and VREFR (pin 46) and REFGNDR (pin 47) for the right channel. Figure 36 illustrates the recommend referencedecouplingcapacitorvaluesandconnectionscheme. The 10nF to 100nF capacitors in Figure 36 may be metal film or X7R/C0G ceramic chip capacitors. The 100m F capacitorsmaybepolymertantalumchip(KemetT520seriesorequivalent)oraluminumelectrolytic. The VREFL and VREFR pins are not designed for biasing external input circuitry. Two common-mode voltage outputsareprovidedforthispurpose,andarediscussedinthefollowingsection. 16 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 100mF PCM4220 + 10-100nF 46 + VREFR AGND 47 REFGNDR 14 REFGNDL 10-100nF 15 VREFL + AGND 100mF + Figure36.RecommendedReferenceCapacitorConnectionsandValues COMMON-MODE VOLTAGE OUTPUTS The PCM4220 includes two dc common-mode voltage outputs, VCOML (pin 13) and VCOMR (pin 48), which correspondtotheleftandrightinputchannels,respectively.Thecommon-modevoltageisutilizedto bias internal op amps within the modulator section of the PCM4220, and may be used to bias external input circuitry when proper design guidelines are followed. The common-mode voltages are derived from the VCC1 and VCC2 analogpowersuppliesusinginternalvoltagedividers.Thevoltagedivideroutputsarebufferedandthen routed to internalcircuitryandtheVCOMLandVCOMRoutputs. The common-mode output voltage is nominally equal to (0.4875 × VCC1) for VCOMR and (0.4875 × VCC2) for VCOML. Given an analog supply voltage of +4.0V connected to both VCC1 and VCC2, the resulting common-modevoltagesare+1.95V. The common-mode voltage outputs have limited drive capability. If multiple bias points are to be driven, or the external bias nodes are not sufficiently high impedance, an external output buffer is recommended. Figure 37 showsatypicalbufferconfigurationusingtheOPA227.Theop amp utilized in the buffer circuit should exhibit low dcoffsetanddriftcharacteristics,aswellaslowoutputnoise. Direct Connect to High-Z Bias Node (Z > 10MW) PCM4220 L To R Bias Nodes VCOML (Optional) or Precision, Low-Noise Op Amp VCOMR (OPA227or equivalent) 100nF to 1mF Close to IC pins Figure37.Common-ModeOutputConnections Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com MASTER CLOCK INPUT The PCM4220 requires a master clock for operating the internal logic and modulator circuitry. The master clock is supplied from an external source, connected at the MCKI input (pin 35). Table 1 summarizes the requirements for various operating modes of the PCM4220. Referring to Table 1, the term f refers to the PCM4220 PCM S output sampling rate (that is, 48kHz, 96kHz, 192kHz, etc.). Refer to the Electrical Characteristics table for timing specificationsrelatedtothemasterclockinput. Forbestperformance,themasterclockjittershouldbemaintainedbelow40pspeakamplitude. Table1.MasterClockRequirements OPERATINGMODE REQUIREDMASTERCLOCK(MCKI)RATE PCMNormal 256f S PCMDoubleSpeed 128f S PCMQuadSpeed 64f S RESET AND POWER-DOWN OPERATION The PCM4220 includes an external reset input, RST (pin 36), which may be utilized to force an internal reset initialization or power-down sequence. The reset input is active low. Figure 38 shows the required timing for an externalforcedreset. A power-down state for the PCM422 may be initiated by forcing and holding the reset input low for the duration of the desired power-down condition. Minimum power is consumed during this state when all clock inputs for the PCM4220 are forced low. Before releasing the reset input by forcing a high state, the master clock should be enabledsothatthePCM4220canexecutearesetinitializationsequence. While the RST pin is forced low, or during reset initialization, the audio serial port data and clock outputs are drivenlow. 40ns minimum RST 0V Internal 1024 System CLock Periods Reset 0V Required for Initialization MCKI 0V Figure38.ExternalResetSequence DISABLED STATES FOR THE PCM4220 AUDIO SERIAL PORT When PCMEN (pin 16) is driven low, the PCM output is disabled. The audio serial port data and clocks are drivenlow. 18 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 PCM OUTPUT AND SAMPLING MODES The PCM4220 supports 24-bit linear PCM output data when the PCMEN input (pin 16) is forced high. The PCM output is disabled when PCMEN is forced low. The 24-bit output data may be dithered to 20-, 18-, or 16-bits using internal word length reduction circuitry. Refer to the Output Word Length Reduction section of this data sheetforadditionalinformation. The PCM4220 supports three PCM sampling modes, referred to as Normal, Double Speed, and Quad Speed. The sampling mode is determined by the state of the FS0 and FS1 inputs (pins 19 and 20, respectively). Table 2 summarizesthesamplingmodesavailableforthePCM4220. Normal sampling mode supports output sampling rates from 8kHz to 54kHz. The ΔΣ modulator operates with 128xoversamplinginthis mode. Both the Classic and Low Group Delay decimation filter responses are available in Normal mode. The master clock (MCKI) rate must be 256x the desired output sampling rate for Normal operation. The Double Speed sampling mode supports output sampling rates from 54kHz to 108kHz. The delta-sigma modulator operates with 64x oversampling in this mode. Both the Classic and Low Group Delay decimation filter responses are available in Double Speed mode. The master clock (MCKI) rate must be 128x the desired output samplingrateforDoubleSpeedoperation. Quad Speed sampling mode supports output sampling rates from 108kHz to 216kHz. The delta-sigma modulator operateswith32xoversamplinginthismode.OnlytheLowGroupDelay decimation filter response is available in Quad Speed mode. The master clock (MCKI) rate must be 64x the desired output sampling rate for Quad Speed operation. Table2.PCMSamplingModeConfiguration FS1(pin20) FS0(pin19) SAMPLINGMODE LO LO Normal,8kHz≤f ≤54kHz S LO HI DoubleSpeed,54kHz<f ≤108kHz S HI LO QuadSpeed,108kHz<f ≤216kHz S HI HI Reserved AUDIO SERIAL PORT INTERFACE The PCM output mode supports a three-wire synchronous serial interface. This interface includes a serial data output (DATA, pin 32), a serial bit or data clock (BCK, pin 33), and a left/right word clock (LRCK, pin 34). The BCK and LRCK clock pins may be inputs or outputs, depending on the Slave or Master mode configuration. Figure 39 illustrates Slave and Master mode serial port connections to an external audio signal processor or host device. The audio serial port supports four data formats that are illustrated in Figure 40, Figure 42, and Figure 43. The I2S and Left-Justified formats support two channels of audio output data. The TDM data formats can support up to eight channels of audio output data on a single data line. The audio data format is selected using the FMT0 and FMT1 inputs (pins 44 and 43, respectively). Table 3 summarizes the audio data format options. For all formats, audio data are represented as two’s complement binary data, with the MSB transmitted first. Regardless oftheformatselection,audiodataarealwaysclockedoutoftheportonthefallingedgeoftheBCKclock. Table3.PCMAudioDataFormatSelection FMT1(pin43) FMT0(pin44) AUDIODATAFORMAT LO LO Left-Justified LO HI I2S HI LO TDM HI HI TDMwithdatadelayedoneBCKcyclefromLRCKrisingedge The LRCK clock rate should always be operated at the desired output sampling rate, or f . In Slave mode, the S LRCKclockis an input, with the rate set by an external audio bus master (that is, a clock generator, digital signal processor, etc.). In Master mode, the LRCK clock is an output, derived from the master clock input using on-chip clock dividers (as is the BCK clock). The clock divider is configured using the FS0 and FS1 pins, which are discussedinthePCMOutputandSamplingModessectionofthisdatasheet. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com For the I2S and Left-Justified data formats, the BCK clock output rate is fixed in Master mode, with the Normal mode being 128f and the Double and Quad Speed modes being 64f . In Slave Mode, a BCK clock input rate of S S 64f or128f isrecommendedforNormalmode,while64f isrecommendedforDoubleandQuadRatemodes. S S S For the TDM data formats, the BCK rate depends upon the sampling mode for either Slave or Master operation. For Normal sampling, the BCK must be 256f . Double Speed mode requires 128f , while Quad Speed mode S S requires 64f . This requirement limits the maximum number of channels carried by the TDM formats to eight for S Normalmode,fourforDoubleRatemode,andtwoforQuadRatemode. When using the TDM formats, the sub-frame assignment for the device must be selected using the SUB0 and SUB1 inputs (pins 26 and 25, respectively). Table 4 summarizes the sub-frame selection options. A sub-frame contains two 32-bit time slots, with each time slot carrying 24 bits of audio data corresponding to either the left or right channel of the PCM4220. Refer to Figure 41 through Figure 43 for TDM interfacing connections and sub-frame formatting details. For the TDM format with one BCK delay, the serial data output is delayed by one BCKperiodaftertherisingedgeoftheLRCKclock. Table4.TDMSub-frameAssignment SUB1(pin25) SUB0(pin26) SUB-FRAMEASSIGNMENT LO LO Sub-frame0 LO HI Sub-frame1 HI LO Sub-frame2 HI HI Sub-frame3 When using TDM formats with Double Speed sampling, it is recommended that the SUB1 pin be forced low. When using TDM formats with Quad Speed sampling, it is recommended that both the SUB0 and SUB1 pins be forcedlow. For all serial port modes and data formats, when driving capacitive loads greater than 30pF with the data and clock outputs, it is recommended that external buffers be utilized to ensure data and clock integrity at the receivingdevice(s). For specifications regarding audio serial port operation, the reader is referred to the Electrical Characteristics: AudioInterfaceTimingtable,aswellasFigure1andFigure2inthisdatasheet. Audio DSP Audio DSP or or PCM4220 Interface PCM4220 Interface LRCK FSYNC LRCK FSYNC BCK SCLK BCK SCLK DATA DATA DATA DATA MCKI MCLK MCKI MCLK Master Master Clock Clock (a) Slave Mode (S/M = HI) (b) Master Mode (S/M = LO) Figure39.SlaveandMasterModeOperation 20 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 Left Channel Right Channel LRCK BCK DATA MSB LSB MSB LSB (a) Left-Justified Data Format LRCK BCK MSB LSB MSB LSB DATA 2 (b) IS Data Format 1/f S Figure40.Left-JustifiedandI2SDataFormats PCM4220 PCM4220 PCM4220 PCM4220 ((ssuubb--ffrraammee00)) ((ssuubb--ffrraammee11)) ((ssuubb--ffrraammee22)) ((ssuubb--ffrraammee33)) SSllaavvee SSllaavvee SSllaavvee SSllaavvee LLOO SSUUBB00 HHII SSUUBB00 LLOO SSUUBB00 HHII SSUUBB00 LLOO SSUUBB11 LLOO SSUUBB11 HHII SSUUBB11 HHII SSUUBB11 LLRRCCKK LLRRCCKK LLRRCCKK LLRRCCKK BBCCKK DDAATTAA BBCCKK DDAATTAA BBCCKK DDAATTAA BBCCKK DDAATTAA LLRRCCKK BBCCKK DDAATTAA (a) All devices are Slaves. PCM4220 PCM4220 PCM4220 PCM4220 ((ssuubb--ffrraammee00)) ((ssuubb--ffrraammee11)) ((ssuubb--ffrraammee22)) ((ssuubb--ffrraammee33)) MMaasstteerr SSllaavvee SSllaavvee SSllaavvee LLOO SSUUBB00 HHII SSUUBB00 LLOO SSUUBB00 HHII SSUUBB00 LLOO SSUUBB11 LLOO SSUUBB11 HHII SSUUBB11 HHII SSUUBB11 LLRRCCKK LLRRCCKK LLRRCCKK LLRRCCKK BBCCKK DDAATTAA BBCCKK DDAATTAA BBCCKK DDAATTAA BBCCKK DDAATTAA LLRRCCKK BBCCKK DDAATTAA (b) One device is the Master while all other devices are Slaves. Figure41.TDMModeInterfaceConnections(PCMNormalModeShown) Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com LRCK Normal Mode DATA L R L R L R L R Sub-frame 0Sub-frame 1Sub-frame 2Sub-frame 3 One Frame, 1/f S LRCK Double Speed Mode DATA L R L R L R L R Sub-frame 0Sub-frame 1Sub-frame 0Sub-frame 1 One Frame, 1/f One Frame, 1/f S S LRCK Quad Speed Mode DATA L R L R L R L R One Frame One Frame One Frame One Frame 1/f 1/f 1/f 1/f S S S S NOTE:EachLorRchanneltimeslotis32bitslong,with24-bitdataLeft-Justifiedinthetimeslot.AudiodataisMSBfirst.Sub-frame assignmentsforeachPCM4220deviceareselectedbythecorrespondingSUB0andSUB1pinsettings. Figure42.TDMDataFormats:SlaveMode LRCK Normal Mode DATA L R L R L R L R Sub-frame 0Sub-frame 1Sub-frame 2Sub-frame 3 One Frame, 1/f S LRCK Double Speed Mode DATA L R L R L R L R Sub-frame 0Sub-frame 1Sub-frame 0Sub-frame 1 One Frame, 1/f One Frame, 1/f S S LRCK Quad Speed Mode DATA L R L R L R L R One Frame One Frame One Frame One Frame 1/f 1/f 1/f 1/f S S S S NOTE:EachLorRchanneltimeslotis32bitslong,with24-bitdataLeft-Justifiedinthetimeslot.AudiodataisMSBfirst.Sub-frame assignmentsforeachPCM4220deviceareselectedbythecorrespondingSUB0andSUB1pinsettings. Figure43.TDMDataFormats:MasterMode DIGITAL DECIMATION FILTER The PCM4220 digital decimation filter is a linear phase, multistage finite impulse response (FIR) design with two user-selectable filter responses. The decimation filter provides the digital downsampling and low-pass anti-alias filterfunctionsforthePCM4220. The Classic filter response is typical of traditional audio data converters, with Figure 24 through Figure 27 detailing the frequency response, and the related specifications given in the Electrical Characteristics table. The groupdelayfortheClassicfilteris39/f ,or812.5m sforf =48kHzand406.25m sforf =96kHz.TheClassicfilter S S S responseisnotavailablefortheQuadSpeedsamplingmode. 22 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 The Low Group Delay response provides a lower latency option for the decimation filter, and is detailed in Figure28throughFigure31,withtherelevantspecifications given in the Electrical Characteristicstable. The Low Group Delay filter response is available for all sampling modes. The group delay for this filter is 21/f , or 437.5m s S forf =48kHz,218.75m sforf =96kHz,and109.375m sforf =192kHz. S S S The decimation filter response is selected using the DF input (pin 21), with the settings summarized in Table 5. For Quad Speed sampling mode operation, the Low Group Delay filter is always selected, regardless of the DF pinsetting. Table5.DecimationFilterResponseSelection DF(pin21) DECIMATIONFILTERRESPONSE LO Classicresponse,withgroupdelay=39/f S HI LowGroupDelayresponse,withgroupdelay=21/f S DIGITAL HIGH-PASS FILTER The PCM4220 incorporates digital high-pass filters for both the left and right audio channels, with the purpose of removing the ΔΣ modulator dc offset from the audio output data. Figure 32 and Figure 33 detail the frequency response for the digital high-pass filter. The f frequency is approximately f /48000, where f is the PCM –3dB S S outputsamplingrate. Two inputs, HPFDR (pin 17) and HPFDL (pin 18), allow the digital high-pass filter to be enabled or disabled individually for the right and left channels, respectively. Table 6 summarizes the operation of the high-pass filter disablepins. Table6.DigitalHigh-PassFilterConfiguration HPFDR(pin17)orHPFDL(pin18) HIGH-PASSFILTERSTATE LO Enabledforthecorrespondingchannel HI Disabledforthecorrespondingchannel PCM OUTPUT WORD LENGTH REDUCTION The PCM4220 is typically configured to output 24-bit linear PCM audio data. However, internal word length reduction circuitry may be utilized to reduce the 24-bit data to 20-, 18-, or 16-bit data. This reduction is accomplished by using a Triangular PDF dithering function. The OWL0 (pin 42) and OWL1 (pin 41) inputs are utilizedtoselecttheoutputdatawordlength.Table7summarizestheoutputwordlengthconfigurationoptions. Table7.PCMAudioDataWordLengthSelection OWL1(pin41) OWL0(pin42) OUTPUTWORDLENGTH LO LO 24bits LO HI 18bits HI LO 20bits HI HI 16bits OVERFLOW INDICATORS The PCM4220 includes two active-high digital overflow outputs, OVFL (pin 37) and OVFR (pin 38), corresponding to the left and right channels, respectively. These outputs are functional when the PCM output mode is enabled, as the overflow detection circuitry is incorporated into the digital filter engine. The overflow indicators are forced high whenever a digital overflow is detected for a given channel. The overflow indicators may be utilized as clipping flags, and monitored using a host processor or light-emitting diode (LED) indicators. WhendrivingaLED,theoverflowoutputmaybebufferedtoensureadequatedriveforthe LED. A recommended bufferisTexasInstruments'SN74LVC1G125.Equivalentbuffersmaybesubstituted Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com TYPICAL CONNECTIONS Figure 44 provides a typical connection diagram for the PCM4220. Recommended power-supply bypass and reference filter capacitors are shown. These components should be located as close to the corresponding PCM4220 package pins as physically possible. Larger power-supply bypass capacitors may be placed on the bottom side of the printed circuit board (PCB). However, reference decoupling capacitors should be located on thetopsideofthePCBtoavoidissueswithaddedviainductance. As Figure 44 illustrates, the audio host device may be a digital signal processor (DSP), digital audio interface transmitter(DIT),oraprogrammablelogicdevice. PCM4220PFB 100nF to 1mF 1 48 AGND VCOMR 2 47 VINR- REFGNDR Right Channel 100nF Analog Input 3 46 VINR+ VREFR 100mF + 4 VCC1 DGND 45 1+00mF 100nF 5 44 +4.0V AGND FMT0 6 43 AGND FMT1 100nF 7 42 AGND OWL0 From Host, Logic, 8 41 or Manual Controls AGND OWL1 100mF 9 40 + VCC2 DGND 10 39 VINL- S/M Left Channel Analog Input 11 38 VINL+ OVFR 12 37 To Host and/or Clipping Indicators 100nF to 1mF AGND OVFL 13 36 VCOML RST From Host or Master Reset 14 35 REFGNDL MCKI From Audio Master Clock Source 100nF 15 34 VREFL LRCK + 16 PCMEN BCK 33 Audio +3.3V DSP or Host 100mF 17 HPFDR DATA 32 100nF 18 31 From Host, Logic, HPFDL VDD or Manual Controls 19 FS0 DGND 30 100mF 20 FS1 NC 29 + 21 28 DF NC 22 27 DGND NC 23 26 DGND SUB0 Required only for TDM data formats. 24 25 DGND SUB1 These pins are ignored for all other formats. Figure44.TypicalConnectionsforPCMandDSDOutputModes INPUT BUFFER CIRCUITS The PCM4220 is typically preceded in an application by an input buffer or preamplifier circuit. The input circuit is required to perform anti-aliasing filtering, in addition to application-specific analog gain scaling, limiting, or processing that may be needed. At a minimum, first-order, low-pass anti-aliasing filtering is necessary. The input buffer must be able to perform the input filtering requirement, in addition to driving the switched-capacitor inputs of the PCM4220 device. The buffer must have adequate bandwidth, slew rate, settling time, and output drive capabilitytoperformthesetasks. Figure 45 illustrates the input buffer/filter circuit utilized on the PCM4222EVM evaluation module, where the PCM4222 analog input section is identical to the PCM4220. This circuit has been optimized for measurement purposes, so that it does not degrade the dynamic characteristics of the PCM4220. The resistors are primarily 0.1% metal film. The 40.2Ω resistor is 1% tolerance thick film. The 1nF and 2.7nF capacitors may be either PPS 24 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 film or C0G ceramic capacitors; both types perform with equivalent results in this application. Surface-mount devices are utilized throughout because they provide superior performance when combined with a wideband amplifier such as the OPA1632. The DGN package version of the OPA1632 is utilized; this package includes a thermal pad on the bottom side. The thermal pad must be soldered to the PCB ground plane for heat sink and mechanicalsupportpurposes. 270W(0.1%) 1nF -15V 10nF-100nF Full-Scale: 11.76V Differential PP Typical with R = 40W S 6 Analog Input 7 560W(0.1%) 8 5 40.2W(1%) 2 EN VINL-or VINR- 3 560W(0.1%) 1 OPA1632DGN 40.2W(1%) 2.7nF V VINL+ or VINR+ OCM 4 G 2 1 3 From R 10nF-100nF 100nF Buffered VCOM T S +15V Ground 1nF Lift Switch 270W(0.1%) Figure45.DifferentialInputBufferCircuitUtilizingtheOPA1632 Figure 46 demonstrates the same circuit topology of Figure 45, while using standard single or dual op amps. The noise level of this circuit is adequate for obtaining the typical A-weighted dynamic range performance for the PCM4220. However, unweighted performance may suffer, depending upon the op amp noise specifications. Near-typical THD+N can be achieved with this configuration, although this performance also depends on the op amps used for the application. The NE5534A and OPA227 (the lower cost 'A' version) are good candidates from a noise and distortion perspective, and are reasonably priced. More expensive lower-noise models, such as the OPA211, should also work well for this configuration. Feedback and input resistor values may be changed to alter circuit gain. However, it is recommended that all circuit changes be simulated and then tested on the bench usingaworkingprototypetoverifyperformance. Figure 47 illustrates a differential input circuit that employs a noninverting architecture. The total noise and distortion is expected to be higher than that measured for Figure 45 and Figure 46. As with Figure 46, the NE5534A and OPA227 are good candidates for this circuit, although similar op amps should yield equivalent results. A useful tool for simulating the circuits shown here is TINA-TI, a free schematic capture and SPICE-based simulator program available from the Texas Instruments web site. This tool includes macro models for many TI and Burr-Brown branded amplifiers and analog integrated circuits. TINA-TI runs on personal computers using MicrosoftWindows®operatingsystems(Windows2000ornewer). Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com 270W 1nF C1 560W INPUT+ + 40.2W U1 VINL-or VINR- VCOML 100nF 2.7nF or VCOMR 40.2W C2 560W U2 VINL+ or VINR+ INPUT- + 1nF 270W U1, U2 = NE5534A, OPA227, or similar NOTE:C andC provideaccoupling.Theymayberemovedifthedcoffsetfromthecircuitisnegligible. 1 2 Figure46.AlternativeBufferCircuitUsingStandardOpAmps 1.5kW 1nF 40.2W C1 R1W U1 VINL+ or VINR+ INPUT+ + 10kW 2.7nF 10kW C RW 2 2 INPUT- + 40.2W U2 VINL-or VINR- VCOML 1nF or VCOMR U3 1.5kW U1, U2 = NE5534A, OPA227, or similar. U3 = OPA227 or equivalent. NOTE:R andR areoptional.Whenused,valuesmaybeselectedforthedesiredattenuation. 1 2 NOTE:C andC provideaccoupling.Theymayberemovedifthedcoffsetfromthecircuitisnegligible. 1 2 Figure47.NoninvertingDifferentialInputBufferUtilizingStandardOpAmps 26 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 INTERFACING TO DIGITAL AUDIO TRANSMITTERS (AES3, IEC60958-3, and S/PDIF) The serial output of audio analog-to-digital converters is oftentimes interfaced to transmitter devices that encode the serial output data to either the AES3 or IEC60958-3 (or S/PDIF) interface formats. Texas Instruments manufactures several devices that perform this encoding, including the DIT4192, DIX4192, SRC4382, and SRC4392. This section describes and illustrates the audio serial port interface connections required for communications between the PCM4220 and these devices. Register programming details for the DIX4192 and SRC4382/4392arealsoprovided. Figure 48 shows the interface between a PCM4220 and a DIT4192 transmitter. This configuration supports sampling frequencies and encoded frame rates from 8kHz to 216kHz. For this example, the audio data format must be either Left-Justified or I2S; TDM formats are not supported by the DIT4192. In addition, the PCM4220 VDDsupplyandDIT4192VIOsupplymustbethesamevoltage,toensurelogiclevelcompatibility. Figure 49 illustrates the audio serial port interface between the PCM4220 and either a DIX4192 transceiver or SRC4382/SRC4392 combo sample rate converter/transceiver device. Port A of the DIX4192 or SRC4382/SRC4392 is utilized for this example. Data acquired by Port A are sent on to the DIT function block withintheinterfacedeviceforAES3encodingandtransmission. The DIX4192 and SRC4382/SRC4392 are software-configurable, with control register and data buffer settings that determine the operation of internal function blocks. Table 8 and Table 9 summarize the control register settings for the Port A and the DIT function blocks for both A/D Converter Master and Slave modes, respectively. Input sampling and encoded frame rates from 8kHz to 216kHz are supported with the appropriate register settings. Master Clock 512f (Normal) S 256f (Double Speed) S 128f (Quad Speed) S Divided by 2 PCM4220 DIT4192 MCKI BCK SCLK MCLK LRCK SYNC FS1 DATA SDATA CLK0 FS0 CLK1 S/M M/S FS1 FS0 Mode CLK1 CLK0 Mode LO LO Normal LO LO Quad Speed LO HI Double Speed LO HI Double Speed HI LO Quad Speed LO =ADC Master HI LO Reserved HI HI Reserved HI =ADC Slave HI HI Normal Figure48.InterfacingthePCM4220toaDIT4192 Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com DIX4192 or PCM4220 SRC4392 BCK BCKA LRCK LRCKA DATA SDINA MCKI MCLK Divided by 2 512f (Normal) S Master 256f (Double Speed) S Clock 128f (Quad Speed) S NOTE:VDDPCM4220=VIODIX4192orSRC4392. AudiodataformatifI2SorLeftJustified. InterfacesupportsADCSlaveorMasterconfigurations,dependingonDIX4192,SRC4382,orSRC4392registersetup. Figure49.InterfacingthePCM4220toaDIX4192,SRC4382,orSRC4392 Table8.RegisterConfigurationSequenceforanADCMasterModeInterface REGISTERADDRESS(hex) REGISTERDATA(hex) COMMENTS 7F 00 SelectRegisterPage0 00 PortAisSlavemodewithLeft-Justifiedaudiodataformat,or 03 01 PortAisSlavemodewithI2SDataformat 04 00 DefaultforPortASlavemodeoperation 64 DivideMCLKby512forNormalsampling,or 07 24 DivideMCLKby256forDoubleSpeedSampling,or 04 DivideMCLKby128forQuadSpeedsampling 08 00 LineDriverandAESOUTbufferenabled DatabuffersonRegisterPage2arethesourcefortheDITchannel 09 01 status(C)anduser(U)data 01 34 PowerupPortAandtheDIT Table9.RegisterConfigurationSequenceforanADCSlaveModeInterface REGISTERADDRESS(hex) REGISTERDATA(hex) COMMENTS 7F 00 SelectRegisterPage0 08 PortAisMastermodewithLeft-Justifiedaudiodataformat,or 03 09 PortAisMastermodewithI2SDataformat 03 DivideMCLKby512forNormalsampling,or 04 01 DivideMCLKby256forDoubleSpeedsampling,or 00 DivideMCLKby128forQuadSpeedsampling 64 DivideMCLKby512forNormalsampling,or 07 24 DivideMCLKby256forDoubleSpeedSampling,or 04 DivideMCLKby128forQuadSpeedsampling 08 00 LineDriverandAESOUTbufferenabled DatabuffersonRegisterPage2arethesourcefortheDITchannel 09 01 status(C)anduser(U)data 01 34 PowerupPortAandtheDIT 28 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PCM4220 www.ti.com............................................................................................................................................. SBAS407C–DECEMBER2006–REVISEDAUGUST2009 TheDITchannel status (C) and user (U) data bits in register page 2 may be programmed after the DIT block has powered up. To program these bits, disable buffer transfers by setting the BTD bit in control register 0x08 to '1'. Then, select register page 2 using register address 0x7F. You can now load the necessary C and U data registers for the intended application by writing the corresponding data buffer addresses. When you have finished writing the C and U data, select register page 0 using register address 0x7F. Re-enable buffer transfers bysettingtheBTDbitincontrolregister0x08to'0'. Copyright©2006–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):PCM4220

PCM4220 SBAS407C–DECEMBER2006–REVISEDAUGUST2009............................................................................................................................................. www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(October2007)toRevisionC ............................................................................................... Page • CorrectedstatementconcerningdirectiontodrivePCMEN(pin16)todisablePCMoutput.............................................. 18 ChangesfromRevisionA(May2007)toRevisionB...................................................................................................... Page • ChangedFigure26y-axisvaluefrom(dB)to(db/10,000).................................................................................................. 12 • ChangedFigure30y-axisvaluefrom(dB)to(db/1000)..................................................................................................... 13 30 SubmitDocumentationFeedback Copyright©2006–2009,TexasInstrumentsIncorporated ProductFolderLink(s):PCM4220

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) PCM4220PFB ACTIVE TQFP PFB 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 PCM4220 & no Sb/Br) PCM4220PFBR ACTIVE TQFP PFB 48 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 PCM4220 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 28-Nov-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) PCM4220PFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 28-Nov-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) PCM4220PFBR TQFP PFB 48 1000 350.0 350.0 43.0 PackMaterials-Page2

MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 M 0,17 36 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ Gage Plane 6,80 9,20 SQ 8,80 0,25 0,05 MIN 0°–7° 1,05 0,95 0,75 Seating Plane 0,45 0,08 1,20 MAX 4073176/B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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