Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 PCM1808 Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo ADC 1 Features 2 Applications • 24-BitDelta-SigmaStereoA/DConverter(ADC) • DVDRecorder 1 • Single-EndedVoltageInput:3Vp-p • DigitalTV • HighPerformance: • AVAmplifierorReceiver – THD+N: –93dB(Typical) • MDPlayer – SNR:99dB(Typical) • CDRecorder – DynamicRange:99dB(Typical) • MultitrackReceiver • OversamplingDecimationFilter: • ElectricMusicalInstrument – OversamplingFrequency: ×64 3 Description – Pass-BandRipple:±0.05dB The PCM1808 device is a high-performance, low- – Stop-BandAttenuation: –65dB cost, single-chip, stereo analog-to-digital converter – On-ChipHigh-PassFilter:0.91Hz(48kHz) with single-ended analog voltage input. The • FlexiblePCMAudioInterface PCM1808 device uses a delta-sigma modulator with 64-times oversampling and includes a digital – Master-orSlave-ModeSelectable decimation filter and high-pass filter that removes the – DataFormats:24-BitI2S,24-BitLeft-Justified dc component of the input signal. For various • PowerDownandResetbyHaltingSystemClock applications, the PCM1808 device supports master and slave mode and two data formats in serial audio • AnalogAntialiasLPFIncluded interface. • SamplingRate:8kHz–96kHz The PCM1808 device supports the power-down and • SystemClock:256f ,384f ,512f S S S resetfunctionsbymeansofhaltingthesystemclock. • Resolution:24Bits The PCM1808 device is suitable for wide variety of • DualPowerSupplies: cost-sensitive consumer applications requiring good – 5-VforAnalog performance and operation with a 5-V analog supply – 3.3-VforDigital and 3.3-V digital supply. Fabrication of the PCM1808 device uses a highly advanced CMOS process. The • Package:14-PinTSSOP device is available in a small, 14-pin TSSOP package. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) PCM1808 TSSOP(14) 4.40mm×5.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. PCM1808BlockDiagram VINL AnLtiPaFlias DMelotad-uSlaigtomra Serial BCK 1 / 64 Interface LRCK Decimation VREF Reference FWilittehr DOUT High-Pass Mode/ FMT Filter Format V R Antialias Delta-Sigma Control MD1 IN LPF Modulator MD0 1 Power Supply Clock andTiming Control SCKI V AGND DGND V CC DD 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 FeatureDescription.................................................14 2 Applications........................................................... 1 7.4 DeviceFunctionalModes........................................17 3 Description............................................................. 1 8 ApplicationandImplementation........................ 19 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................19 8.2 TypicalApplication .................................................19 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 21 6 Specifications......................................................... 4 10 Layout................................................................... 21 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings ............................................................4 10.1 LayoutGuidelines.................................................21 6.3 RecommendedOperatingConditions.......................4 10.2 LayoutExample....................................................22 6.4 ThermalInformation .................................................5 11 DeviceandDocumentationSupport................. 23 6.5 ElectricalCharacteristics...........................................5 11.1 CommunityResources..........................................23 6.6 TimingRequirements................................................7 11.2 Trademarks...........................................................23 6.7 TypicalCharacteristics............................................11 11.3 ElectrostaticDischargeCaution............................23 7 DetailedDescription............................................ 14 11.4 Glossary................................................................23 7.1 Overview.................................................................14 12 Mechanical,Packaging,andOrderable Information........................................................... 23 7.2 FunctionalBlockDiagram.......................................14 4 Revision History ChangesfromRevisionA(August2006)toRevisionB Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 2 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 5 Pin Configuration and Functions 14-PinTSSOP PWPackage TopView VREF 1 14 VINR AGND 2 13 VINL VCC 3 12 FMT VDD 4 11 MD1 DGND 5 10 MD0 SCKI 6 9 DOUT LRCK 7 8 BCK P0032-02 PinFunctions PIN I/O DESCRIPTION NAME PIN AGND 2 — AnalogGND BCK 8 I/O Audio-databit-clockinputoroutput (1) DGND 5 — DigitalGND DOUT 9 O Audio-datadigitaloutput FMT 12 I Audio-interfaceformatselect (2) LRCK 7 I/O Audio-datalatch-enableinputoroutput (1) MD0 10 I Audio-interfacemodeselect0 (2) MD1 11 I Audio-interfacemodeselect1 (2) SCKI 6 I Systemclockinput;256f ,384f or512f (3) S S S V 3 — Analogpowersupply,5-V CC V 4 — Digitalpowersupply,3.3-V DD V L 13 I Analoginput,L-channel IN V R 14 I Analoginput,R-channel IN V 1 — Reference-voltagedecoupling(=0.5V ) REF CC (1) Schmitt-triggerinputwithinternalpulldown(50-kΩ,typical) (2) Schmitt-triggerinputwithinternalpulldown(50-kΩ,typical),5-Vtolerant (3) Schmitt-triggerinput,5-Vtolerant Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingambienttemperaturerange(unlessotherwisenoted) (1) MIN MAX UNIT V Analogsupplyvoltage –0.3 6.5 V CC V Digitalsupplyvoltage –0.3 4 V DD Groundvoltagedifferences AGND,DGND ±0.1 V LRCK,BCK,DOUT –0.3 (V +0.3V)<4 V DD Digitalinputvoltage SCKI,MD0,MD1,FMT –0.3 6.5 V V L,V R, IN IN Analoginputvoltage –0.3 (V +0.3V)<6.5 V V CC REF Inputcurrent(anypinsexceptsupplies) ±10 mA T Junctiontemperature 150 °C J T Storagetemperature –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) ±4000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101, V allpins(2) ±1500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingambienttemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Analogsupplyvoltage(seePowerSupplyRecommendations) 4.5 5 5.5 V CC V Digitalsupplyvoltage 2.7 3.3 3.6 V DD Analoginputvoltage,fullscale(–0dB) V =5V 3 Vp-p CC V (1) Highinputlogiclevel 2 V VDC IH DD V (1) Lowinputlogiclevel 0 0.8 VDC IL V (2) (3) Highinputlogiclevel 2 5.5 VDC IH V (2) (3) Lowinputlogiclevel 0 0.8 VDC IL Digitalinputlogicfamily TTLcompatible Digitalinputclockfrequency,systemclock 2.048 49.152 MHz Digitalinputclockfrequency,samplingclock 8 96 kHz Digitaloutputloadcapacitance 20 pF T Operatingambienttemperaturerange –40 85 °C A T Junctiontemperature 150 °C J (1) Pins7,8:LRCK,BCK(Schmitt-triggerinput,with50-kΩtypicalpulldownresistor,inslavemode) (2) Pin6:SCKI(Schmitt-triggerinput,5-Vtolerant) (3) Pins10–12:MD0,MD1,FMT(Schmitt-triggerinput,with50-kΩtypicalpulldownresistor,5-Vtolerant) 4 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 6.4 Thermal Information PCM1808 THERMALMETRIC(1) PW(TSSOP) UNIT 14PINS R Junction-to-ambientthermalresistance 89.4 °C/W θJA R Junction-to-case(top)thermalresistance 25.6 °C/W θJC(top) R Junction-to-boardthermalresistance 30.3 °C/W θJB ψ Junction-to-topcharacterizationparameter 1.4 °C/W JT ψ Junction-to-boardcharacterizationparameter 29.8 °C/W JB R Junction-to-case(bottom)thermalresistance N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Electrical Characteristics AllspecificationsatT =25°C,V =5V,V =3.3V,mastermode,f =48kHz,systemclock=512f ,24-bitdata,unless A CC DD S S otherwisenoted PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Resolution 24 Bits DATAFORMAT Audiodatainterfaceformat I2S,left-justified Audiodatabitlength 24 Bits Audiodataformat MSB-first,2scomplement f Samplingfrequency 8 48 96 kHz S 256f 2.048 12.288 24.576 S Systemclockfrequency 384f 3.072 18.432 36.864 MHz S 512f 4.096 24.576 49.152 S INPUTLOGIC V (1) Highinputlogiclevel 2 V VDC IH DD V (1) Lowinputlogiclevel 0 0.8 VDC IL V (2) (3) Highinputlogiclevel 2 5.5 VDC IH V (2) (3) Lowinputlogiclevel 0 0.8 VDC IL I (2) Highinputlogiccurrent V =V ±10 µA IH IN DD I (2) Lowinputlogiccurrent V =0V ±10 µA IL IN I (1) (3) Highinputlogiccurrent V =V 65 100 µA IH IN DD I (1) (3) Lowinputlogiccurrent V =0V ±10 µA IL IN OUTPUTLOGIC V (4) Highoutputlogiclevel I =–4mA 2.8 VDC OH OUT V (4) Lowoutputlogiclevel I =4mA 0.5 VDC OL OUT DCACCURACY %of Gainmismatch,channel-to-channel ±1 ±3 FSR %of Gainerror ±3 ±6 FSR (1) Pins7,8:LRCK,BCK(Schmitt-triggerinput,with50-kΩtypicalpulldownresistor,inslavemode) (2) Pin6:SCKI(Schmitt-triggerinput,5-Vtolerant) (3) Pins10–12:MD0,MD1,FMT(Schmitt-triggerinput,with50-kΩtypicalpulldownresistor,5-Vtolerant) (4) Pins7–9:LRCK,BCK(inmastermode),DOUT Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com Electrical Characteristics (continued) AllspecificationsatT =25°C,V =5V,V =3.3V,mastermode,f =48kHz,systemclock=512f ,24-bitdata,unless A CC DD S S otherwisenoted PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DYNAMICPERFORMANCE (5) V =–0.5dB,f =48kHz –93 –87 IN S V =–0.5dB,f =96kHz (6) –87 IN S THD+N Totalharmonicdistortion+noise dB V =–60dB,f =48kHz –37 IN S V =–60dB,f =96kHz (6) –39 IN S f =48kHz,A-weighted 95 99 S Dynamicrange dBVDC f =96kHz,A-weighted (6) 101 S f =48kHz,A-weighted 95 99 S S/N Signal-to-noiseratio dB f =96kHz,A-weighted (6) 101 S f =48kHz 93 97 S Channelseparation dB f =96kHz (6) 91 S ANALOGINPUT Inputvoltage 0.6V Vp-p CC Centervoltage(V ) 0.5V V REF CC Inputimpedance 60 kΩ Antialiasingfilterfrequencyresponse –3dB 1.3 MHz DIGITALFILTERPERFORMANCE Passband 0.454f Hz S Stopband 0.583f Hz S Pass-bandripple ±0.05 dB Stop-bandattenuation –65 dB Delaytime 17.4/f S 0.019f / HPFfrequencyresponse –3dB S 1000 POWERSUPPLYREQUIREMENTS f =48kHz,96kHz (6) 8.6 11 mA I Analogsupplycurrent (7) S CC Powereddown (8) 1 μA f =48kHz 5.9 8 mA S I Digitalsupplycurrent (7) f =96kHz (6) 10.2 mA DD S Powereddown (8) 150 µA f =48kHz 62 81 S mW Powerdissipation (7) f =96kHz (6) 77 S Powereddown (8) 500 µW (5) TestingofanalogperformancespecificationsusesanaudiomeasurementsystembyAudioPrecision™with400-HzHPFand20-kHz LPFinRMSmode. (6) f =96kHz,systemclock=256f . S S (7) MinimumloadonLRCK(pin7),BCK(pin8),DOUT(pin9) (8) Power-downandresetfunctionsenabledbyhaltingSCKI,BCK,LRCK. 6 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 6.6 Timing Requirements MIN NOM MAX UNIT SYSTEMCLOCKTIMING t Systemclockpulseduration,HIGH 8 ns w(SCKH) t Systemclockpulseduration,LOW 8 ns w(SCKL) Systemclockdutycycle 40% 60% CLOCK-HALTPOWER-DOWNANDRESETTIMING t DelaytimefromSCKIhalttointernalreset 4 µs (CKR) t DelaytimefromSCKIresumetoresetrelease 1024SCKI µs (RST) t DelaytimefromresetreleasetoDOUToutput 8960/f µs (REL) S AUDIODATAINTERFACETIMING(SlaveMode:LRCKandBCKWorkasInputs)(1) t BCKperiod 1/(64f ) ns (BCKP) S t BCKpulseduration,HIGH 1.5×t ns (BCKH) (SCKI) t BCKpulseduration,LOW 1.5×t ns (BCKL) (SCKI) t LRCKsetuptimetoBCKrisingedge 50 ns (LRSU) t LRCKholdtimetoBCKrisingedge 10 ns (LRHD) t LRCHperiod 10 µs (LRCP) t Delaytime,BCKfallingedgetoDOUTvalid –10 40 ns (CKDO) t Delaytime,LRCKedgetoDOUTvalid –10 40 ns (LRDO) t Risetimeofallsignals 20 ns r t Falltimeofallsignals 20 ns f AUDIODATAINTERFACETIMING(MasterMode:LRCKandBCKWorkasOutputs)(2) t BCKperiod 150 1/(64f ) 2000 ns (BCKP) S t BCKpulseduration,HIGH 65 1200 ns (BCKH) t BCKpulseduration,LOW 65 1200 ns (BCKL) t Delaytime,BCKfallingedgetoLRCKvalid –10 20 ns (CKLR) t LRCKperiod 10 1/f 125 ns (LRCP) S t Delaytime,BCKfallingedgetoDOUTvalid –10 20 ns (CKDO) t Delaytime,LRCKedgetoDOUTvalid –10 20 ns (LRDO) t Risetimeofallsignals 20 ns r t Falltimeofallsignals 20 ns f AUDIOCLOCKINTERFACETIMING(MasterMode:BCKWorkasOutputs)(3) t Delaytime,SCKIrisingedgetoBCKedge 5 30 ns (SCKBCK) (1) Timingmeasurementreferencelevelis1.4Vforinputand0.5V foroutput.Riseandfalltimesarefrom10%to90%oftheinput- DD outputsignalswing.LoadcapacitanceofDOUTis20pF.t istheSCKIperiod. (SCKI) (2) Timingmeasurementreferencelevelis0.5V .Riseandfalltimesarefrom10%to90%oftheinput-outputsignalswing.Load DD capacitanceofallsignalsis20pF. (3) Timingmeasurementreferencelevelis1.4Vforinputand0.5V foroutput.LoadcapacitanceofBCKis20pF.Thistimingapplies DD whenSCKIfrequencyislessthan25MHz. tw(SCKH) tw(SCKL) SCKI 2 V SCKI 0.8 V Figure1. SystemClockTiming Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com 2.6 V V 2.2 V DD 1.8 V Reset Reset Release Internal Operation Reset 1024 System Clocks 8960/f S System Clock DOUT Zero Data Normal Data Fade-In Complete Fade-In Start DOUT BPZ (Contents) 48/f or 48/fS IN Figure2. Power-OnTiming 8 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 SCKI Halt SCKI Resume SCKI Fixed to Low or High t Reset: t (CKR) (RST) Clock-Halt Reset Reset Release: t (REL) Internal Operation Operation Reset DOUT Normal Data Zero Data Normal Data Fade-In Complete Fade-In Start DOUT Normal Data BPZ (Contents) 48/f or 48/f IN S Figure3. Clock-HaltPower-DownandResetTiming t(LRCP) LRCK 1.4 V t(BCKL) t(LRSU) t(BCKH) t(LRHD) BCK 1.4 V t(BCKP) t(CKDO) t(LRDO) DOUT Figure4. AudioDataInterfaceTiming(SlaveMode:LRCKandBCKWorkasInputs) Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com t(LRCP) LRCK 0.5 V DD t(BCKL) t(BCKH) t(CKLR) BCK 0.5 V DD t(BCKP) t(CKDO) t(LRDO) 10 DOUT 0.5 V DD Figure5. AudioDataInterfaceTiming(MasterMode:LRCKandBCKWorkasOutputs) SCKI 1.4 V t(SCKBCK) t(SCKBCK) BCK 0.5 VDD Figure6. AudioClockInterfaceTiming(MasterMode:BCKWorksasOutput) 10 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 6.7 Typical Characteristics AllspecificationsatT =25°C,V =5V,V =3.3V,mastermode,f =48kHz,systemclock=512f ,24-bitdata,unless A CC DD S S otherwisenoted. 50 0 −10 0 −20 dB dB −30 − −50 − −40 mplitude−100 mplitude −−6500 A A −70 −150 −80 −90 −100 −200 0 8 16 24 32 0.00 0.25 0.50 0.75 1.00 Normalized Frequency [×fS] G001 Frequency [×fS] G002 Figure7.Decimation-FilterFrequencyResponse Figure8.Decimation-FilterFrequencyResponse OverallCharacteristics Stop-BandAttenuationCharacteristics 0.2 0 −1 0.0 −2 −3 B −0.2 B –4.13 dB at 0.5 f d d S − − −4 e e d −0.4 d −5 u u plit plit −6 m m A −0.6 A −7 −8 −0.8 −9 −1.0 −10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Frequency [×fS] G003 Normalized Frequency [×fS] G004 Figure9.Decimation-FilterFrequencyResponse Figure10.Decimation-FilterFrequencyResponse Pass-BandRippleCharacteristics Transition-BandCharacteristics 0 0.2 −10 0.0 −20 −30 B B −0.2 d −40 d − − de −50 de −0.4 mplitu −60 mplitu A −70 A −0.6 −80 −0.8 −90 −100 −1.0 0.0 0.1 0.2 0.3 0.4 0 1 2 3 4 Normalized Frequency [×fS/1000] G005 Normalized Frequency [×fS/1000] G006 Figure11.High-PassFilterFrequencyResponse Figure12.High-PassFilterFrequencyResponse HPFStop-BandCharacteristics HPFStop-BandCharacteristics Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com Typical Characteristics (continued) AllspecificationsatT =25°C,V =5V,V =3.3V,mastermode,f =48kHz,systemclock=512f ,24-bitdata,unless A CC DD S S otherwisenoted. −87 105 B d − −88 104 e B Nois −89 −d 103 n + −90 NR 102 ortio −91 d S 101 otaTl Harmonic Dist −−−−99995432 ynamic Range an 109990789 SNR Dynamic Range − D N −96 96 + HD −97 95 T −50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100 TA–Free-AirTemperature–°C G007 TA–Free-AirTemperature–°C G008 Figure13.THD+NvsTemperature Figure14.DynamicRangeandSNRvsTemperature B −87 105 d e− −88 104 s n + Noi −−9809 −dB 110032 o R Distorti −91 d SN 101 monic −−9932 ge an 19090 Dynamic Range SNR otal Ha−Tr −−9954 namic Ran 9987 + N −96 Dy 96 HD −97 95 T 4.25 4.50 4.75 5.00 5.25 5.50 5.75 4.25 4.50 4.75 5.00 5.25 5.50 5.75 VCC–Supply Voltage–V G009 VCC–Supply Voltage–V G010 Figure15.THD+NvsSupplyVoltage Figure16.DynamicRangeandSNRvsSupplyVoltage B −87 105 d e− −88 104 Dynamic Range on + Nois −−9809 NR−dB 110032 ▲ SNR armonic Distorti −−−999321 Range and S 11900901 ▲ ▲ otalT H −−9954 (1)System Clock = 384 fS namic 9987 (1)System Clock = 384 fS N− (2)System Clock = 512 fS Dy (2)System Clock = 512 fS D + −96 (3)System Clock = 256 fS 96 (3)System Clock = 256 fS H −97 95 T 44.1(1) 48(2) 96(3) 44.1(1) 48(2) 96(3) fSAMPLECondition−kHz G011 fSAMPLECondition−kHz G012 Figure17.THD+Nvsf Condition Figure18.DynamicRangeandSNRvsf Condition SAMPLE SAMPLE 12 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 Typical Characteristics (continued) AllspecificationsatT =25°C,V =5V,V =3.3V,mastermode,f =48kHz,systemclock=512f ,24-bitdata,unless A CC DD S S otherwisenoted. 0 0 Input Level =−0.5 dB Input Level =−60 dB −20 −20 Data Points = 8192 Data Points = 8192 −40 −40 dB −60 dB −60 − − e e ud −80 ud −80 plit plit m −100 m −100 A A −120 −120 −140 −140 0 5 10 15 20 0 5 10 15 20 f−Frequency−kHz G013 f−Frequency−kHz G014 Figure19.OutputSpectrum(–0.5dB,N=8192) Figure20.OutputSpectrum(–60dB,N=8192) B 0 15 d I e− −10 mA ICC nic Distortion + Nois −−−−54320000 Supply Current− 10 DD mo −60 − otal HTar −−8700 and IDD 5 ((21))SSyysstteemm CClloocckk == 358142 ffSS N− −90 CC (3)System Clock = 256 fS THD + −100−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 I 0 44.1(1) 48(2) 96(3) f Condition−kHz Signal Level−dB SAMPLE G016 G015 Figure22.SupplyCurrentvsf Condition Figure21.OutputSpectrum SAMPLE THD+NvsSignalLevel Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com 7 Detailed Description 7.1 Overview The PCM1808 is high-performance, low-cost, single-chip, stereo analog-to-digital converter with single-ended analog voltage input. The PCM1808 uses a delta-sigma modulator with 64-times oversampling and includes a digital decimation filter and high-pass filter that removes the dc component of the input signal. For various applications, the PCM1808 supports master and slave mode and two data formats in serial audio interface up to 96-kHz sampling. These features are controlled through hardware by pulling pins high or low with resistors or a controller GPIO. The PCM1808 also supports a power-down and reset function by means of halting the system clock. 7.2 Functional Block Diagram VINL AnLtiPaFlias DMelotad-uSlaigtomra Serial BCK 1 / 64 Interface LRCK Decimation VREF Reference FWilittehr DOUT High-Pass Mode/ FMT Filter Format V R Antialias Delta-Sigma Control MD1 IN LPF Modulator MD0 1 Power Supply Clock andTiming Control SCKI V AGND DGND V CC DD 7.3 Feature Description 7.3.1 HardwareControl Pins FMT, MD0, and MD1 allow the device to be controlled by either pullup or pulldown resistors as well as GPIO from a digital IC. These controls allow the option of switching between I2S or left-justified, and in which interfacemodethedeviceoperates. 7.3.2 SystemClock The PCM1808 device supports 256 f , 384 f , and 512 f as system clock, where f is the audio sampling S S S S frequency.ThesystemclockinputmustbeonSCKI(pin6). The PCM1808 device has a system-clock detection circuit which automatically senses if the system-clock operation is at 256 f , 384 f , or 512 f in slave mode. In master mode, control of the system clock frequency S S S must be through the serial control port, which uses MD1 (pin 11) and MD0 (pin 10). An internal circuit automatically divides down the system clock to generate frequencies of 128 f and 64 f , which operate the S S digitalfilterandthedelta-sigmamodulator,respectively. Table1showssometypicalrelationshipsbetweensamplingfrequencyandsystemclockfrequency,andFigure1 showssystemclocktiming. Table1.SamplingFrequencyandSystemClockFrequency SAMPLINGFREQUENCY(kHz) SYSTEMCLOCKFREQUENCY(f )(MHz) SCLK 256f 384f 512f S S S 8 2.048 3.072 4.096 16 4.096 6.144 8.192 32 8.192 12.288 16.384 44.1 11.2896 16.9344 22.5792 14 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 Feature Description (continued) Table1.SamplingFrequencyandSystemClockFrequency(continued) SAMPLINGFREQUENCY(kHz) SYSTEMCLOCKFREQUENCY(f )(MHz) SCLK 256f 384f 512f S S S 48 12.288 18.432 24.576 64 16.384 24.576 32.768 88.2 22.5792 33.8688 45.1584 96 24.576 36.864 49.152 7.3.3 SynchronizationWithDigitalAudioSystem In slave mode, the PCM1808 device operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6). The PCM1808 device does not require a specific phase relationship between LRCK and SCKI, but does require thesynchronizationofLRCKandSCKI. If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48 BCK/frame)duringonesampleperiodduetoLRCKorSCKIjitter,internaloperationoftheADChaltswithin1/f S anddigitaloutputgoestozerodata(BPZcode)untilresynchronizationbetweenLRCKandSCKIoccurs. In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization doesnotoccur,andthepreviouslydescribeddigitaloutputcontrolanddiscontinuitydonotoccur. Figure 23 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data, the PCM1808 device can generate some noise in the audio signal. Also, the transition of normal data to undefined data creates a discontinuity in the digital output data, which can generate some noise in the audio signal. The digital output is valid after resynchronization completes and the time of 32 / f has elapsed. S Because the fade-in operation is performed, it takes additional time of 48 / f or 48 / f to obtain the level in S corresponding to the analog input signal. In the case of loss of synchronization during the fade-in or fade-out operation, the operation stops and DOUT (pin 9) goes to zero data immediately. The fade-in operation resumes frommuteafterthetimeof32/f followingresynchronization. S Resynchronization Resynchronization Synchronization Lost Synchronization Lost Stateof Synchronous Asynchronous Synchronous Asynchronous Synchronous Synchronization 1/f 32/f S S Undefined DOUT Normal Data Zero Data Normal Data Zero Data Normal Data Data Fade-In Complete Fade-In Start Fade-In Restart Normal Data DOUT BPZ (Contents) 32/f S 48/f or 48/f 48/f or 48/f in S in S Figure23. ADCDigitalOutputforLossofSynchronizationandResynchronization Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com 7.3.4 PowerOn The PCM1808 device has an internal power-on-reset circuit, and initialization (reset) occurs automatically when the power supply (V ) exceeds 2.2 V (typical). While V < 2.2 V (typical), and for 1024 system-clock counts DD DD after V > 2.2 V (typical), the PCM1808 device stays in the reset state and the digital output remains zero. After DD release of the reset state, 8960 / f seconds must pass before the digital output becomes valid. Because of the S performingofthefade-inoperation,ittakesadditionaltimeof48/f or48/f toobtainthedatacorrespondingto in S theanaloginputsignal.Figure2 illustratesthepower-ontimingandthedigitaloutput. 7.3.5 SerialAudioDataInterface ThePCM1808deviceinterfacestheaudiosystemthroughLRCK(pin7),BCK(pin8),andDOUT(pin9). 7.3.5.1 InterfaceMode MD1 (pin 11) and MD0 (pin 10) select master mode and slave mode as interface modes, both of which the PCM1808 device supports.Table 2 shows the interface-mode selections. It is necessary to set MD1 and MD0 priortopoweron. In master mode, the PCM1808 device provides the timing of serial audio data communications between the PCM1808 device and the digital audio processor or external circuit. While in slave mode, the PCM1808 device receivesthetimingfordatatransferfromanexternalcontroller. Table2.InterfaceModes MD1(PIN11) MD0(PIN10) INTERFACEMODE Low Low Slavemode(256f ,384f ,512f autodetection) S S S Low High Mastermode(512f ) S High Low Mastermode(384f ) S High High Mastermode(256f ) S 7.3.5.1.1 MasterMode In master mode, BCK and LRCK work as output pins, timing which from the clock circuit of the PCM1808 device controlsthesepins.ThefrequencyofBCKisconstantat64BCK/frame. 7.3.5.1.2 SlaveMode In slave mode, BCK and LRCK work as input pins. The PCM1808 device accepts 64-BCK/frame or 48- BCK/frameformat(onlyfora384-f systemclock),not32-BCK/frameformat. S 7.3.5.2 DataFormat Table3.DataFormat FORMATNO. FMT(Pin12) FORMAT 0 Low I2S,24-bit 1 High Left-justified,24-bit 16 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 Format 0: FMT= LOW 24-Bit, MSB-First, I2S LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 22 23 24 1 2 3 22 23 24 MSB LSB MSB LSB Format 1: FMT= HIGH 24-Bit, MSB-First, Left-Justified LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 22 23 24 1 2 3 22 23 24 1 MSB LSB MSB LSB Figure24. AudioDataFormat(LRCKandBCKWorkasInputsinSlaveMode andasOutputsinMasterMode) 7.3.5.3 InterfaceTiming Figure4 andFigure5illustratetheinterfacetiminginslavemodeandmastermode,respectively. 7.4 Device Functional Modes 7.4.1 Fade-InandFade-OutFunctions The PCM1808 device has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions come into operation in some cases as described in several following sections. Performance of the level changes from 0 dB to mute or mute to 0 dB employs calculated pseudo S-shaped characteristics with zero-cross detection. Because of the zero-cross detection, the time needed for the fade-in and fade-out depends on the analog input frequency (f ). It takes 48 / f to complete the processing. If there is no zero-cross during 8192 / f , in in S a forced DOUT fade-in or fade-out occurs during 48 / f (TIME OUT). Figure 25 illustrates the fade-in and fade- S outoperationprocessing. Fade-In Complete Fade-Out Start Fade-In Start Fade-Out Complete DOUT BPZ (Contents) 48/f or 48/f 48/f or 48/f in S in S Figure25. Fade-InandFade-OutOperations Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com Device Functional Modes (continued) 7.4.2 Clock-HaltPower-DownandResetFunction The PCM1808 device has a power-down and reset function. Halting SCKI (pin 6) in both master and slave modes triggers this function. The function is available any time after power on. Reset and power down occur automatically 4 μs (minimum) after the halt of SCKI. During assertion of the clock-halt reset, the PCM1808 devicestaysintheresetandpower-downmode,withDOUT(pin9)forcedtozero.Releasetheresetandpower- down mode requires the supply of SCKI. The digital output is valid after release of the reset state and elapse of the time of 1024 SCKI + 8960 / f . Performing the fade-in operation takes additional time of 48 / f or 48 / f to S in S attainthelevelcorrespondingtotheanaloginputsignal.Figure3 illustratestheclock-haltresettiming. To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) must synchronize with SCKI within 4480 / f after the resumption of SCKI. If it takes more than 4480 / f for BCK and LRCK to synchronize with SCKI, S S mask SCKI until it again achieves synchronization, taking care of glitch and jitter. See the typical circuit connectiondiagram,Figure26. To avoid ADC performance degradation, assertion of the clock-halt reset is necessary when changing system clockSCKIortheaudiointerfaceclocksBCKandLRCK(samplingratef )onthefly. S 18 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The PCM1808 device is suitable for wide variety of cost-sensitive consumer applications requiring good performanceandoperationwitha5-Vanalogsupplyand3.3-Vdigitalsupply. 8.2 Typical Application PCM1808 C5(3) + 1 V V R 14 (5) + C1(1) R-ch IN REF IN 2 AGND V L 13 + C2(1) L-chIN C (2) IN 4 + 5 V 3 V FMT 12 4 µs(min) CC High/Low 3.3 V C (2)+ 4 VDD MD1 11 Pin 3 Setting 5 DGND MD0 10 Mask 6 SCKI DOUT 9 X1(4) 7 LRCK BCK 8 PLL170x DSP or Audio Processor (1) C1, C2: A 1-μF electrolytic capacitor gives 2.7 Hz (τ = 1 μF × 60 kΩ) cutoff frequency for the input HPF in normal operationandrequiresapower-onsettlingtimewitha60-mstimeconstantinthepower-oninitializationperiod. (2) C3,C4:Bypasscapacitors,0.1-μFceramicand10-μFelectrolytic,dependingonlayoutandpowersupply (3) C5:Recommendedcapacitorsare0.1-μFceramicand10-μFelectrolytic. (4) X1:X1masksthesystemclockinputwhenusingtheclock-haltresetfunctionwithexternalcontrol. (5) Optionalexternalantialiasingfiltercouldberequired,dependingontheapplication. Figure26. TypicalCircuitConnectionDiagram 8.2.1 DesignRequirements Forthisdesignexample,usetheparameterslistedinTable4astheinputparameters. Table4.DesignParameters DESIGNPARAMETER EXAMPLEVALUE Analoginputvoltagerange 0Vp-pto3Vp-p Output PCMaudiodata Systemclockinputfrequency 2.048MHzto49.152MHz Outputsamplingfrequency 8kHzto96kHz Powersupply 3.3Vand5V Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com 8.2.2 DetailedDesignProcedure 8.2.2.1 ControlPins The control pins FMT, MD0, and MD1 should be controlled either by biasing with a 10 kΩ resister to VDD or GND,orbydrivingwithGPIOfromtheDSPoraudioprocessor. 8.2.2.2 MasterClock In this application of the PCM1808 device, a PLL170X series device is used as the master clock source to drive both the PCM1808 and the DSP or audio processor synchronously. With the addition of the AND gate, the operation of the PCM1808 device can be halted by control of the MASK bit. A crystal that operates at the standardaudiomultiplescanalsobeused. 8.2.2.3 DSPorAudioProcessor In this application, the DSP or audio processor is acting as the audio master, and the PCM1808 is acting as the audio slave. This means the DSP or audio processor must be able to output audio clocks that the PCM1808 can usetoprocessaudiosignals. 8.2.2.4 InputFilters For the analog input circuit, an ac coupling capacitor should be placed in series with the input. This will remove the dc component of the input signal. An RC filter can also be implemented to filter out-of-band noise to reduce aliasing.TheequationbelowcanbeusedtocalculatethecutofffrequencyoftheoptionalRCfilterfortheinput. 1 f = C 2pRC (1) 8.2.3 ApplicationCurve 0 Input Level =−0.5 dB −20 Data Points = 8192 −40 dB −60 − e ud −80 plit m −100 A −120 −140 0 5 10 15 20 f−Frequency−kHz G013 Figure27.OutputSpectrum 20 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 9 Power Supply Recommendations The PCM1808 device requires a 5-V nominal supply and a 3.3-V nominal supply. The 5-V supply is for the analog circuitry powered by the V pin. The 3.3-V supply is for the digital circuitry powered by the V pin. The CC DD decouplingcapacitorsforthepowersuppliesshouldbeplacedclosetothedeviceterminals. A V that varies from the nominal 5 V affects the reference voltage for the input. This has a slight impact on the CC dataconversionofthedevice. 10 Layout 10.1 Layout Guidelines 10.1.1 V ,V Pins CC DD Bypass the digital and analog power supply lines to the PCM1808 device to the corresponding ground pins with both 0.1-μF ceramic and 10-μF electrolytic capacitors as close to the pins as possible to maximize the dynamic performanceoftheADC. 10.1.2 AGND,DGNDPins To maximize the dynamic performance of the PCM1808 device, there are no internal connections to the analog and digital grounds. These grounds should have low impedance to avoid digital noise feedback into the analog ground.TheyshouldbeconnecteddirectlytoeachotherunderthePCM1808devicepackagetoreducepotential noiseproblems. 10.1.3 V L,V RPins IN IN V L and V R are single-ended inputs. These inputs have integrated antialias low-pass filters to remove the IN IN high-frequency noise outside the audio band. If the performance of these filters is not adequate for an application, the application requires appropriate external antialiasing filters. An appropriate choice would typically beapassiveRCfilterintherangeof100Ω and0.01 μFto1kΩ and1000pF. 10.1.4 V Pin REF To ensure low source impedance of the ADC references, the recommended capacitors between V and AGND REF are 0.1-μF ceramic and 10-μF electrolytic. These capacitors should be located as close as possible to the V REF pintoreducedynamicerrorsontheADCreferences. 10.1.5 DOUTPin TheDOUTpinhasalargeload-drivecapability,butiftheDOUTlineislong,arecommendedpracticeistolocate a buffer near the PCM1808 device and minimize load capacitance to minimize the digital-analog crosstalk and maximizethedynamicperformanceoftheADC. 10.1.6 SystemClock The quality of the system clock can influence dynamic performance, as the PCM1808 device operates based on a system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference betweensystemclocktransitionandBCKorLRCKtransitioninslavemode. Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:PCM1808

PCM1808 SLES177B–APRIL2006–REVISEDAUGUST2015 www.ti.com 10.2 Layout Example Itisrecommendedtoplaceatoplayergroundpourfor shieldingaroundPCM1808andconnecttolowermainPCB groundplanebymultiplevias OptionalExternalRC AntialiasingCircuit 1μF 10μF 0.1μF + R-chIN 1 V V R 14 REF in + 0.1μF 2 AGND V L 13 L-chIN 10μF in + + 1μF 5 V 3 VCC FMT 12 Makesuretohave groundpourseparating 3.3 V 4 V PCM1808 MD1 11 DD theleft-andright- + channeltracestohelp 10μF 0.1μF 5 DGND MD0 10 preventcrosstalk. 6 SCK DOUT 9 Partconfiguration 7 LRCK BCK 8 ClockSignalsto pullupsorpulldowns DSPorAudio Processor Makesuretohave groundpourseparating theclocksignalsfrom thesurroundingtraces. TopLayerGroundPour ViatoBottomGroundPlane TopLayerSignalTraces PadtoTopLayerGroundPour Figure28. PCM1808LayoutExample 22 SubmitDocumentationFeedback Copyright©2006–2015,TexasInstrumentsIncorporated ProductFolderLinks:PCM1808

PCM1808 www.ti.com SLES177B–APRIL2006–REVISEDAUGUST2015 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.2 Trademarks E2EisatrademarkofTexasInstruments. AudioPrecisionisatrademarkofAudioPrecision,Inc. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.3 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most- current data available for the designated device. This data is subject to change without notice and without revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,seetheleft-handnavigationpane. Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:PCM1808

PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples (1) Drawing Qty (2) (3) (4) PCM1808PW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1808 & no Sb/Br) PCM1808PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1808 & no Sb/Br) PCM1808PWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1808 & no Sb/Br) PCM1808PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1808 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 OTHER QUALIFIED VERSIONS OF PCM1808 : •Automotive: PCM1808-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) PCM1808PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) PCM1808PWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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