Product Sample & Technical Tools & Support & Folder Buy Documents Software Community PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 PCM1802 Single-Ended Analog-Input 24-Bit, 96-kHz Stereo A/D Converter 1 Features 2 Applications • 24-BitDelta-SigmaStereoA/DConverter • AVAmplifierReceivers 1 • Single-EndedVoltageInput:3V • MDPlayers P–P • AntialiasingFilterIncluded • CDRecorders • OversamplingDecimationFilter • MultitrackReceivers – OversamplingFrequency: ×64, ×128 • ElectricMusicalInstruments – Pass-BandRipple:±0.05dB 3 Description – Stop-BandAttenuation: –65dB The PCM1802 is a high-performance, low-cost, – On-ChipHigh-PassFilter:0.84Hz(44.1kHz) single-chip stereo analog-to-digital converter with • HighPerformance single-ended analog voltage input. The PCM1802 – THD+N:96dB(Typical) uses a delta-sigma modulator with 64-times or 128‑times oversampling, and includes a digital – SNR:105dB(Typical) decimation filter and high-pass filter (HPF), which – DynamicRange:105dB(Typical) removes the DC component of the input signal. For • PCMAudioInterface various applications, the PCM1802 supports master and slave modes and four data formats in serial – MasterandSlaveModeSelectable interface. The PCM1802 is suitable for a wide variety – DataFormats:24-BitLeft-Justified;24-BitI2S; of cost-sensitive consumer applications where good 20-bitor24-BitRight-Justified performance, 5-V analog supply, and 3.3-V digital • SamplingRate:16kHzto96kHz supply operation is required. The PCM1802 is fabricated using a highly advanced CMOS process • SystemClock:256f ,384f ,512f ,768f S S S S andisavailableintheDB20-pinSSOPpackage. • DualPowerSupplies:5V(Analog),3.3V(Digital) • Package:20-PinSSOP DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) PCM1802 SSOP(20) 7.20mm×5.30mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. BlockDiagram Single-End 5thOrder BCK VINL /DCioffnevreerntteiarl DMelotad-uSlaigtomra LRCK FSYNC Serial ×1/64 (×1/128) Interface VREF1 Decimation DOUT Reference Filter VREF2 with Mode/ High-Pass Filter Format FMT0 Control FMT1 Single-End 5thOrder MODE0 VINR /Differential Delta-Sigma Converter Modulator MODE1 BYPAS OSR Power Supply Clock and Timing Control PDWN SCKI VCC AGND DGND VDD B0004-07 Copyright © 2016,Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................15 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 22 3 Description............................................................. 1 8.1 ApplicationInformation............................................22 4 RevisionHistory..................................................... 2 8.2 TypicalApplication..................................................22 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 24 6 Specifications......................................................... 4 10 Layout................................................................... 24 6.1 AbsoluteMaximumRatings......................................4 10.1 LayoutGuidelines.................................................24 6.2 ESDRatings..............................................................4 10.2 LayoutExample....................................................25 6.3 RecommendedOperatingConditions.......................4 11 DeviceandDocumentationSupport................. 26 6.4 ThermalInformation..................................................5 11.1 ReceivingNotificationofDocumentationUpdates26 6.5 ElectricalCharacteristics...........................................5 11.2 CommunityResources..........................................26 6.6 TypicalCharacteristics..............................................7 11.3 Trademarks...........................................................26 7 DetailedDescription............................................ 12 11.4 ElectrostaticDischargeCaution............................26 7.1 Overview.................................................................12 11.5 Glossary................................................................26 7.2 FunctionalBlockDiagrams.....................................12 12 Mechanical,Packaging,andOrderable Information........................................................... 26 7.3 FeatureDescription.................................................14 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(January2005)toRevisionD Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • DeletedLeadtemperature(soldering),260°Cfor5s,fromAbsoluteMaximumRatingstable............................................. 4 • AddedThermalInformationtable........................................................................................................................................... 5 • ChangedThermalresistance,R ,valueinThermalInformationtableFrom:115°C/WTo:80.8°C/W............................... 5 θJA 2 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 5 Pin Configuration and Functions DBPackage 20-PinSSOP TopView VINL 1 20 MODE1 VINR 2 19 MODE0 VREF1 3 18 FMT1 VREF2 4 17 FMT0 VCC 5 16 OSR AGND 6 15 SCKI PDWN 7 14 VDD BYPAS 8 13 DGND FSYNC 9 12 DOUT LRCK 10 11 BCK Not to scale PinFunctions PIN I/O DESCRIPTION NAME NO. AGND 6 — AnalogGND BCK 11 I/O Bitclockinputandoutput(1) BYPAS 8 I HPFbypasscontrol.Low:normalmode(DCcut);High:bypassmode(through)(2) DGND 13 — DigitalGND DOUT 12 O Audiodataoutput FMT0 17 I Audiodataformatselect0(seeDataFormat)(2) FMT1 18 I Audiodataformatselect1(seeDataFormat)(2) FSYNC 9 I/O Framesynchronousclockinputandoutput(1) LRCK 10 I/O Samplingclockinputandoutput(1) MODE0 19 I Modeselect0(seeInterfaceMode)(2) MODE1 20 I Modeselect1(seeInterfaceMode)(2) OSR 16 I Oversamplingratioselect.Low:×64f ;High:×128f (2) S S PDWN 7 I Power-downcontrol,active-low(2) SCKI 15 I Systemclockinput;256f ,384f ,512f ,or768f (3) S S S S VCC 5 — Analogpowersupply,5V VDD 14 — Digitalpowersupply,3.3V VINL 1 I Analoginput,L-channel VINR 2 I Analoginput,R-channel VREF1 3 — Reference-1decouplingcapacitor VREF2 4 — Reference-2voltageinput,normallyconnectedtoV CC (1) Schmitt-Triggerinput (2) Schmitt-Triggerinputwithinternalpulldown(50kΩtypically),5-Vtolerant (3) Schmitt-Triggerinput,5-Vtolerant Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT VCC 6.5 Supplyvoltage V VDD 4 Groundvoltagedifferences AGNDandDGND ±0.1 V Supplyvoltagedifference(V –V ) VCCandVDD 3V V CC DD FSYNC,LRCK,BCK,andDOUT –0.3 V +0.3 DD Digitalinputvoltage PDWN,BYPAS,SCKI,OSR,FMT0,FMT1, V –0.3 6.5 MODE0,andMODE1 Analoginputvoltage VINL,VINR,VREF1,andVREF2 –0.3 V +0.3 V CC Inputcurrent(anypinsexceptsupplies) ±10 mA Ambienttemperatureunderbias –40 125 °C Junctiontemperature 150 °C Packagetemperature(IRreflow,peak) 260 °C Storagetemperature,T –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±1500 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Analogsupplyvoltage,V 5 V CC Digitalsupplyvoltage,V 3.3 V DD Analoginputvoltage,full-scale(–0dB) 3 V P–P Digitalinputlogicfamily TTL Samplingclock 8.192 49.152 MHz Digitalinputclockfrequency Systemclock 32 96 kHz Digitaloutputloadcapacitance 20 pF Operatingfree-airtemperature,T –40 85 °C A 4 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 6.4 Thermal Information PCM1802 THERMALMETRIC(1) DB(SSOP) UNIT 20PINS R Junction-to-ambientthermalresistance 80.8 °C/W θJA R Junction-to-case(top)thermalresistance 40 °C/W θJC(top) R Junction-to-boardthermalresistance 37.6 °C/W θJB ψ Junction-to-topcharacterizationparameter 7.2 °C/W JT ψ Junction-to-boardcharacterizationparameter 37 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics T =25°C,V =5V,V =3.3V,mastermode,f =44.1kHz,systemclock=384f ,oversamplingratio=×128,24-bitdata A CC DD S S (unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Resolution 24 Bits DATAFORMAT Left-justified,I2S,or Audiodatainterfaceformat right‑justified Audiodatabitlength 20or24 Bits Audiodataformat MSBfirstor2scomplement f Samplingfrequency 16 44.1 96 kHz S 256f 4.096 11.2896 24.576 S 384f 6.144 16.9344 36.864 S Systemclockfrequency MHz 512f 8.192 22.5792 49.152 S 768f (1) 12.288 33.8688 S INPUTLOGIC V 2 V IH Inputlogiclevel(2) DD V 0 0.8 IL VDC V 2 5.5 IH Inputlogiclevel(3) V 0 0.8 IL I V =V ±10 IH Inputlogiccurrent(4) IN DD I V =0V ±10 IL IN µA I V =V 65 100 IH Inputlogiccurrent(5) IN DD I V =0V ±10 IL IN OUTPUTLOGIC V I =–1mA 2.8 OH Outputlogiclevel(6) OUT VDC V I =1mA 0.5 OL OUT DCACCURACY Gainmismatch, ±1% ±4% FSR channel-to-channel Gainerror ±2% ±6% FSR Bipolarzeroerror HPFbypassed(7) ±2% FSR (1) Maximumsystemclockfrequencyisnotapplicableat768f ,f =96kHz(seeSystemClock). S S (2) AppliestoFSYNC,LRCK,BCK(Schmitt-triggerinputinslavemode)pins. (3) AppliestoPDWN,BYPAS,SCKI,OSR,FMT0,FMT1,MODE0,MODE1(Schmitt-triggerinput,5-Vtolerant)pins. (4) AppliestoFSYNC,LRCK,BCK(Schmitt-triggerinputinslavemode),SCKI(Schmitt-triggerinput)pins. (5) AppliestoPDWN,BYPAS,OSR,FMT0,FMT1,MODE0,MODE1(Schmitt-triggerinput,with50-kΩtypicalpulldownresistor)pins. (6) AppliestoFSYNC,LRCK,BCK(inmastermode),DOUTpins. (7) High-passfilter Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com Electrical Characteristics (continued) T =25°C,V =5V,V =3.3V,mastermode,f =44.1kHz,systemclock=384f ,oversamplingratio=×128,24-bitdata A CC DD S S (unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DYNAMICPERFORMANCE(8) f =44.1kHz,V =–0.5dB 0.0015% 0.003% S IN f =96kHz,V =–0.5dB,systemclock=256f , oSversamplingrINatio=×64(9) S 0.0025% THD+N Totalharmonicdistortion+noise f =44.1kHz,V =–60dB 0.7% S IN f =96kHz,V =–60dB,systemclock=256f , oSversamplingrINatio=×64(9) S 1.2% f =44.1kHz,A-weighted 100 105 S Dynamicrange f =96kHz,A-weighted,systemclock=256f , dB oSversamplingratio=×64(9) S 103 f =44.1kHz,A-weighted 100 105 S Signaltonoiseratio f =96kHz,A-weighted,systemclock=256f , dB oSversamplingratio=×64(9) S 103 f =44.1kHz 96 103 S Channelseparation f =96kHz,systemclock=256f ,oversampling dB rSatio=×64(9) S 98 ANALOGINPUT Inputvoltage 0.6×V V CC P–P V 1 Centervoltage 0.5×V V REF CC Inputimpedance 20 kΩ Antialiasingfilterfrequency –3dB 300 kHz response DIGITALFILTERPERFORMANCE Passband 0.454f Hz S Stopband 0.583f Hz S Pass-bandripple ±0.05 dB Stop-bandattenuation –65 dB Delaytime 17.4/f s S HPFfrequencyresponse –3dB 0.019f mHz S POWERSUPPLYREQUIREMENTS V 4.5 5 5.5 CC Voltage VDC V 2.7 3.3 3.6 DD I V =5V,V =3.3V 24 30 CC CC DD Supplycurrent(10) f =44.1kHzV =5V,V =3.3V 8.3 10 mA S CC DD I DD f =96kHz,V =5V,V =3.3V(8) 17 S CC DD f =44.1kHz,V =5V,V =3.3V 147 183 S CC DD Operation P Powerdissipation f =96kHz,V =5V,V =3.3V(8) 176 mW D S CC DD Powerdown V =5V,V =3.3V 0.5 CC DD (8) AnalogperformancespecificationsaretestedwithSystemTwo™audiomeasurementsystembyAudioPrecision™,using400-HzHPF, 20-kHzLPFfor44.1-kHzoperationor40-kHzLPFfor96-kHzoperationinRMSmode. (9) f =96kHz,systemclock=256f ,oversamplingratio=×64. S S (10) MinimumloadonDOUT,BCK,LRCK,andFSYNC. 6 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 6.6 Typical Characteristics T =25°C,V =5V,V =3.3V,Mastermode,f =44.1kHz,systemclock=384f ,oversamplingratio=×128,and24-bit A CC DD S S data(unlessotherwisenoted). 0.004 110 % − 109 e s Noi B 108 + d Distortion 0.003 and SNR− 110067 Dynamic Range c e 105 moni Rang 104 SNR ar c ot−Tal H 0.002 Dynami 110023 N D+ 101 H T 0.001 100 −50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100 TA−Free-Air Temperature−°C G009 TA−Free-Air Temperature−°C G010 Figure1.TotalHarmonicDistortion+Noise Figure2.DynamicRangeandSNR vsFree-AirTemperature vsFree-AirTemperature 0.004 110 % − 109 e s Noi B 108 Distortion + 0.003 and SNR−d 110067 Dynamic Range c e 105 moni Rang 104 SNR ar c −otal HT 0.002 Dynami 110023 N D+ 101 H T 0.001 100 4.25 4.50 4.75 5.00 5.25 5.50 5.75 4.25 4.50 4.75 5.00 5.25 5.50 5.75 VCC−Supply Voltage−V G011 VCC−Supply Voltage−V G012 Figure3.TotalHarmonicDistortion+Noise Figure4.DynamicRangeandSNRvsSuppyVoltage vsSupplyVoltage 0.004 110 e−% OfSv=e r4s8a mkHpzli,n Sgy Rstaetmio C=l×o1c2k8 =. 256 fS, 109 fOSv=e r4s8a mkHpzli,n Sgy Rstaetmio C=l×o1c2k8 =. 256 fS, Nois fOSv=e r9s6a mkHpzli,n Sgy Rstaetmio C=lo×c6k4 .= 256 fS, B 108 fOSv=e r9s6a mkHpzli,n Sgy Rstaetmio C=l×o6c4k. = 256 fS, + d Distortion 0.003 and SNR− 110067 Dynamic Range c e 105 moni Rang 104 SNR ar c otal H−T 0.002 Dynami 110023 N D+ 101 H T 0.001 100 0 4140.1 4280 9360 40 0 4140.1 4280 9360 40 fSAMPLECondition−kHz G013 fSAMPLECondition−kHz G014 Figure5.TotalHarmonicDistortion+Noise Figure6.DynamicRangeandSNRvsfSAMPLECondition vsf Condition SAMPLE Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com 6.6.1 TypicalCharacteristics:InternalFilter 6.6.1.1 DigitalFilter:DecimationFilterFrequencyResponse T = 25°C, V = 5 V, V = 3.3 V, Master mode, f = 44.1 kHz, system clock = 384 f , oversampling ratio = A CC DD S S ×128,and24-bitdata(unlessotherwisenoted). 50 50 Oversampling Ratio =´128 Oversampling Ratio =×64 0 0 B B d −50 d −50 − − e e d d u u mplit −100 mplit −100 A A −150 −150 −200 −200 0 8 16 24 32 40 48 56 64 0 8 16 24 32 Frequency [×fS] Frequency [×fS] G001 G002 Figure7.AmplitudevsFrequencyOverallCharacteristics Figure8.AmplitudevsFrequencyOverallCharacteristics 0 0.2 −10 0.0 −20 −30 −0.2 B B d −40 d − − de −50 de −0.4 u u mplit −60 mplit A A −0.6 −70 −80 −0.8 −90 Oversampling Oversampling Ratio =×128 and×64 Ratio =×128 and×64 −100 −1.0 0.00 0.25 0.50 0.75 1.00 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency [×fS] G003 Frequency [×fS] G004 Figure9.AmplitudevsFrequencyStop-BandAttenuation Figure10.AmplitudevsFrequencyPass-BandRipple Characteristics Characteristics 8 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 Typical Characteristics: Internal Filter (continued) 6.6.1.2 HPF(High-PassFilter)FrequencyResponse T = 25°C, V = 5 V, V = 3.3 V, Master mode, f = 44.1 kHz, system clock = 384 f , oversampling ratio = A CC DD S S ×128,and24-bitdata(unlessotherwisenoted). 0 0.2 −10 0.0 −20 −30 −0.2 B B d −40 d − − de −50 de −0.4 u u mplit −60 mplit A A −0.6 −70 −80 −0.8 −90 −100 −1.0 0.0 0.1 0.2 0.3 0.4 0 1 2 3 4 Frequency [×fS/1000] G005 Frequency [×fS/1000] G006 Figure11.AmplitudevsFrequencyHPF Figure12.AmplitudevsFrequencyHPF Stop-BandCharacteristics Pass-BandCharacteristics 6.6.1.3 AnalogFilter:AntialiasingFilterFrequenceResponse T = 25°C, V = 5 V, V = 3.3 V, Master mode, f = 44.1 kHz, system clock = 384 f , oversampling ratio = A CC DD S S ×128,and24-bitdata(unlessotherwisenoted). 0 0.0 −5 −0.1 −10 −0.2 −15 −0.3 B B d −20 d −0.4 − − e e d −25 d −0.5 u u mplit −30 mplit −0.6 A A −35 −0.7 −40 −0.8 −45 −0.9 −50 −1.0 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k f−Frequency−Hz f−Frequency−Hz G007 G008 Figure13.AmplitudevsFrequencyAntialiasFilterStop- Figure14.AmplitudevsFrequencyAntialiasFilterPass- BandCharacteristics BandCharacteristics Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com 6.6.2 TypicalCharacteristics:OutputSpectrum T = 25°C, V = 5 V, V = 3.3 V, Master mode, f = 44.1 kHz, system clock = 384 f , oversampling ratio = A CC DD S S ×128,and24-bitdata(unlessotherwisenoted). 0 0 Input Level =−0.5 dB Input Level =−60 dB Data Points = 8192 Data Points = 8192 −20 −20 −40 −40 B B d d − −60 − −60 e e d d u u plit −80 plit −80 m m A A −100 −100 −120 −120 −140 −140 0 5 10 15 20 0 5 10 15 20 f−Frequency−kHz f−Frequency−kHz G015 G016 Figure15.AmplitudevsFrequency Figure16.AmplitudevsFrequency 100 % − e s Noi 10 + n o storti 1 Di c ni o arm 0.1 H al otT − 0.01 N + D H T 0.001 −100−90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level−dB G017 Figure17.TotalHarmonicDistortion+NoisevsSignalLevel 10 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 6.6.3 TypicalCharacteristics:SupplyCurrent T = 25°C, V = 5 V, V = 3.3 V, Master mode, f = 44.1 kHz, system clock = 384 f , oversampling ratio = A CC DD S S ×128,and24-bitdata(unlessotherwisenoted). 30 A 25 ICC m − nt e 20 urr C y ppl 15 u S − d IDD 10 IDD n a ICC 5 OfSv=e r4s8a mkHpzli,n Sgy Rstaetmio C=l×o1c2k8 =. 256 fS, fS= 96 kHz, System Clock = 256 fS, Oversampling Ratio =×64. 0 0 4140.1 4280 9360 40 fSAMPLECondition−kHz G018 Figure18.SupplyCurrentvsf Condition SAMPLE Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com 7 Detailed Description 7.1 Overview The PCM1802 device consists of a reference circuit, two channels of single-ended-to-differential converter, a fifth-order delta-sigma modulator with full differential architecture, a decimation filter with high-pass filter, and a serial interface circuit. Figure 19 illustrates the total architecture of the PCM1802, Figure 20 illustrates the architecture of single-ended-to-differential converter and antialiasing filter, and Figure 21 is the block diagram of the fifth-order delta-sigma modulator and transfer function. An on-chip high-precision reference with one external capacitor provides all reference voltages that are required by the PCM1802 device and defines the full-scale voltage range for both channels. On-chip single-ended-to-differential signal converters save the design, space, and extra parts cost for external signal converters. Full-differential architecture provides a wide dynamic range and excellent power-supply rejection performance. The input signal is sampled at a ×64 or ×128 oversampling rate, thus eliminating an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five integrators using the switched capacitor technique and a comparator, shapes the quantization noise generated by the comparator and 1-bit DAC outside of the audio signal band. The high-order delta-sigma modulation randomizes the modulator outputs and reduces the idle tone level. The 64-f or 128-f , 1-bit stream S S from the delta-sigma modulator is converted to a 1-f , 24-bit or 20-bit digital signal by removing high-frequency S noisecomponentswithadecimationfilter.TheDCcomponentofthesignalisremovedbytheHPF,andtheHPF output is converted to a time-multiplexed serial signal through the serial interface, which provides flexible serial formats. 7.2 Functional Block Diagrams Single-End 5thOrder BCK VINL /Differential Delta-Sigma LRCK Converter Modulator FSYNC Serial ×1/64 (×1/128) Interface VREF1 Decimation DOUT Reference Filter VREF2 with Mode/ High-Pass Filter Format FMT0 Control FMT1 Single-End 5thOrder MODE0 VINR /Differential Delta-Sigma Converter Modulator MODE1 BYPAS OSR Power Supply Clock and Timing Control PDWN SCKI VCC AGND DGND VDD B0004-07 Copyright © 2016,Texas Instruments Incorporated Figure19. BlockDiagram 12 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 Functional Block Diagrams (continued) 1mF VINL 20 kW + 1 − − (+) + + (−) VREF1 Delta-Sigma 3 + Modulator 0.1mF Reference 10mF VREF2 4 VCC 5 S0011-05 Copyright © 2016,Texas Instruments Incorporated Figure20. AnalogFrontEnd(LeftChannel) Analog In X(z) + 1st + − 2nd 3rd + − 4th 5th SW-CAP SW-CAP SW-CAP SW-CAP SW-CAP − Integrator Integrator Integrator Integrator Integrator Qn(z) Digital Out + + + + + + + + Y(z) H(z) Comparator 1-Bit DAC Y(z)=STF(z)∗X(z)+NTF(z)∗Qn(z) Signal Transfer Function STF(z)=H(z)/[1+H(z)] Noise Transfer Function NTF(z)=1/[1+H(z)] B0005-02 Copyright © 2016,Texas Instruments Incorporated Figure21. BlockDiagramofFifth-OrderDelta-SigmaModulator Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com 7.3 Feature Description 7.3.1 HardwareControl The FMT0, FMT1, OSR, BYPASS, MD0, and MD1 pins allow the device to be controlled by tying these pins to GPIOandGNDorVDDfromahostIC.ThesecontrolsallowfullconfigurationofthePCM1802. 7.3.2 Power-OnResetSequence The PCM1802 has an internal power-on reset circuit, and initialization (reset) is performed automatically when the power supply (V ) exceeds 2.2 V (typical). While V < 2.2 V (typical), and for 1024 system-clock counts DD DD after V > 2.2 V (typical), the PCM1802 stays in the reset state and the digital output is forced to zero. The DD digital output is valid after the reset state is released and the time of 4480 / f is passed. Figure 22 illustrates the S internalpower-onresettimingandthedigitaloutputforpower-onreset. 2.6 V VDD 2.2 V 1.8 V Reset Reset Removal Internal Reset 1024 System Clocks 4480 / fS System Clock DOUT Zero Data Normal Data T0014-05 Figure22. InternalPower-OnResetTiming 7.3.3 SystemClock The PCM1802 supports 256 f , 384 f , 512 f , and 768 f as the system clock, where f is the audio sampling S S S S S frequency.ThesystemclockmustbesuppliedonSCKI. The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating at 256 f , 384 f , 512 f , or 768 f in slave mode. In master mode, the system clock frequency must be selected by S S S S MODE0 and MODE1, and 768 f is not available. For system clock inputs of 384 f , 512 f , and 768 f , the S S S S system clock is divided to 256 f automatically, and the 256 f clock operates the delta-sigma modulator and the S S digitalfilter. 14 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 Feature Description (continued) Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Table 2 shows systemclocktiming. Table1.SamplingFrequencyandSystemClockFrequency SAMPLINGRATE SYSTEMCLOCKFREQUENCY(MHz) FREQUENCY(kHz) 256f 384f 512f 768f S S S S 32 8.192 12.288 16.384 24.576 44.1 11.2896 16.9344 22.5792 33.8688 48 12.288 18.432 24.576 36.864 64 16.384 24.576 32.768 49.152 88.2 22.5792 33.8688 45.1584 — 96 24.576 36.864 49.152 — tw(SCKH) tw(SCKL) SCKI 2 V SCKI 0.8 V T0005B07 Table2.SystemClockTiming PARAMETER MIN MAX UNIT t Systemclock-pulseduration,high 7 ns w(SCKH) t Systemclock-pulseduration,low 7 ns w(SCKL) 7.4 Device Functional Modes 7.4.1 PowerDown,HPFBypass,OversamplingControl PDWN controls the entire ADC operation. During power-down mode, both the supply current for the analog portion and the clock signal for the digital portion are shut down, and power dissipation is minimized. DOUT is alsodisabledandnosystemclockisacceptedduringpower-downmode. Table3.Power-DownControl PDWN MODE LOW Power-downmode HIGH Normaloperationmode The built-in function for DC component rejection can be bypassed using the BYPAS control. In bypass mode, the DC components of the analog input signal, such as the internal DC offset, are converted and included in the digitaloutputdata. Table4.HPFBypassControl BYPAS HPF(HIGH-PASSFILTER)MODE LOW Normal(noDCcomponentonDOUT)mode HIGH Bypass(DCcomponentonDOUT)mode OSR controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode is available for f <50kHz,andmustbeusedcarefullyasthedutycycleofthe384f systemclockaffectsperformance. S S Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com Table5.OversamplingControl OSR OVERSAMPLINGRATIO LOW ×64 HIGH ×128(f <50kHz) S 7.4.2 SerialAudioDataInterface ThePCM1802interfaceswiththeaudiosystemthroughBCK,LRCK,FSYNC,andDOUT. 7.4.2.1 DataFormat ThePCM1802supportsfouraudiodataformatsinbothmasterandslavemodes,andtheyareselectedbyFMT1 and FMT0 as shown in Table 6. Figure 23 and Figure 25 illustrate the data formats in slave mode and master mode,respectively. Table6.DataFormat FORMAT FMT1 FMT0 FORMAT 0 0 0 Left-justified,24-bit 1 0 1 I2S,24-bit 2 1 0 Right-justified,24-bit 3 1 1 Right-justified,20-bit 16 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 7.4.2.2 InterfaceTiming Figure24andFigure26illustratetheinterfacetiminginslavemodeandmastermode,respectively. FORMAT 0: FMT[1:0] = 00 24-Bit,MSB-First, Left-Justified FSYNC LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 22 23 24 1 2 3 22 23 24 1 MSB LSB MSB LSB FORMAT 1: FMT[1:0] = 01 24-Bit, MSB-First, I2S FSYNC LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 22 23 24 1 2 3 22 23 24 MSB LSB MSB LSB FORMAT 2: FMT[1:0] = 10 24-Bit, MSB-First, Right-Justified FSYNC LRCK Left-Channel Right-Channel BCK DOUT 24 1 2 3 22 23 24 1 2 3 22 23 24 MSB LSB MSB LSB FORMAT 3: FMT[1:0] = 11 20-Bit, MSB-First, Right-Justified FSYNC LRCK Left-Channel Right-Channel BCK DOUT 20 1 2 3 18 19 20 1 2 3 18 19 20 MSB LSB MSB LSB T0016-12 Figure23. AudioDataFormat(SlaveMode:FSYNC,LRCK,andBCKWorkasInputs) Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com FSYNC 1.4 V t(FSSU) t(FSHD) t(LRCP) LRCK 1.4 V t(BCKL) t(LRSU) t(BCKH) t(LRHD) BCK 1.4 V t(BCKP) t(CKDO) t(LRDO) DOUT 0.5 VDD T0017-01 Timingmeasurementreferencelevelis(V +V )/2.Riseandfalltimesaremeasuredfrom10%to90%ofINto IH IL OUTsignalswing.LoadcapacitanceofDOUTis20pF. Figure24. AudioDataInterfaceTiming(SlaveMode:FSYNC,LRCK,andBCKWorkasInputs) Table7.AudioDataInterfaceTiming:SlaveMode PARAMETER MIN MAX UNIT t BCKperiod 150 ns (BCKP) t BCKpulseduration,high 60 ns (BCKH) t BCKpulseduration,low 60 ns (BCKL) t LRCKsetuptimetoBCKrisingedge 40 ns (LRSU) t LRCKholdtimetoBCKrisingedge 20 ns (LRHD) t LRCKperiod 10 µs (LRCP) t FSYNCsetuptimetoBCKrisingedge 20 ns (FSSU) t FSYNCholdtimetoBCKrisingedge 20 ns (FSHD) t Delaytime,BCKfallingedgetoDOUTvalid –10 20 ns (CKDO) t Delaytime,LRCKedgetoDOUTvalid –10 20 ns (LRDO) t Risetimeofallsignals 10 ns r t Falltimeofallsignals 10 ns f 18 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 FORMAT 0:FMT[1:0]=00 24-Bit, MSB-First, Left-Justified FSYNC LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 22 23 24 1 2 3 22 23 24 1 MSB LSB MSB LSB FORMAT 1: FMT[1:0] = 01 24-Bit, MSB-First, I2S FSYNC LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 22 23 24 1 2 3 22 23 24 MSB LSB MSB LSB FORMAT 2: FMT[1:0] = 10 24-Bit, MSB-First, Right-Justified FSYNC LRCK Left-Channel Right-Channel BCK DOUT 24 1 2 3 22 23 24 1 2 3 22 23 24 MSB LSB MSB LSB FORMAT 3: FMT[1:0] = 11 20-Bit, MSB-First, Right-Justified FSYNC LRCK Left-Channel Right-Channel BCK DOUT 20 1 2 3 18 19 20 1 2 3 18 19 20 MSB LSB MSB LSB T0016-13 Figure25. AudioDataFormat(MasterMode:FSYNC,LRCK,andBCKWorkasOutputs) Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com t(FSYP) FSYNC 0.5 VDD t(CKFS) t(LRCP) LRCK 0.5 VDD t(BCKL) t(BCKH) t(CKLR) BCK 0.5 VDD t(BCKP) t(CKDO) t(LRDO) DOUT 0.5 VDD T0018-01 Timingmeasurementreferencelevelis(V +V )/2.Riseandfalltimesaremeasuredfrom10%to90%ofINto IH IL OUTsignalswing.Loadcapacitanceofallsignalsis20pF. Figure26. AudioDataInterfaceTiming(MasterMode:FSYNC,LRCK,andBCKWorkasOutputs) Table8.AudioDataInterfaceTiming:MasterMode PARAMETER MIN TYP MAX UNIT t BCKperiod 150 1/(64f ) 1200 ns (BCKP) S t BCKpulseduration,high 75 600 ns (BCKH) t BCKpulseduration,low 75 600 ns (BCKL) t Delaytime,BCKfallingedgetoLRCKvalid –10 20 ns (CKLR) t LRCKperiod 10 1/f 80 µs (LRCP) S t Delaytime,BCKfallingedgetoFSYNCvalid –10 20 ns (CKFS) t FSYNCperiod 5 1/(2f ) 40 µs (FSYP) S t Delaytime,BCKfallingedgetoDOUTvalid –10 20 ns (CKDO) t Delaytime,LRCKedgetoDOUTvalid –10 20 ns (LRDO) t Risetimeofallsignals 10 ns r t Falltimeofallsignals 10 ns f 7.4.2.3 SynchronizationWithDigitalAudioSystem In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 does notrequireaspecificphaserelationshipbetweenLRCKandSCKI,butdoesrequirethesynchronizationofLRCK andSCKI. If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 f BCK (±5 BCKs for 48 f BCK) S S during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1 / f and digital S outputisforcedintoBPZcodeuntilresynchronizationbetweenLRCKandSCKIiscompleted. In the case of changes less than ±5 BCKs for 64 BCK per frame (±4 BCKs for 48 BCK per frame), resynchronizationdoesnotoccur. 20 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 Figure 27 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data, some noise might be generated in the audio signal. The transition of normal to undefined data and undefined or zero data to normal creates a data discontinuity in the digital output, which generates some noiseintheaudiosignal. TI recommends setting PDWN low to achieve stable analog performance when the sampling rate, interface mode,dataformat,oroversamplingcontrolischanged. Synchronization Lost Resynchronization State of Synchronization SYNCHRONOUS ASYNCHRONOUS SYNCHRONOUS 1/fS 32/fS UNDEFINED DOUT NORMALDATA ZERO DATA NORMALDATA DATA T0020-05 Figure27. ADCDigitalOutputforLossofSynchronizationandResynchronization 7.4.3 MasterMode In master mode, BCK, LRCK, and FSYNC work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802. The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of this signal indicates the ending point of the data. The frequency of this signal is fixed at 2 × LRCK. The duty cycle ratio depends on data bit length. The frequency of BCK is fixed at 64 × LRCK. The 768-f system clock is not S availableinmastermode. 7.4.4 SlaveMode Inslavemode,BCK,LRCK,andFSYNCworkasinputpins.FSYNCenablestheBCKsignal,andthedevicecan shift out the converted data while FSYNC is HIGH. The PCM1802 accepts the 64-f BCK or the 48-f BCK S S format. The delay of FSYNC from the LRCK transition must be within 16 BCKs for the 64-f BCK format and S within12BCKsforthe48-f BCKformat. S 7.4.5 InterfaceMode ThePCM1802supportsmastermodeandslavemodeasinterfacemodes,andtheyareselectedbyMODE1and MODE0asshowninTable9. In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802 and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for data transferfromanexternalcontroller. Table9.InterfaceMode MODE1 MODE0 INTERFACEMODE 0 0 Slavemode(256f ,384f ,512f ,768f ) S S S S 0 1 Mastermode(512f ) S 1 0 Mastermode(384f ) S 1 1 Mastermode(256f ) S Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The PCM1802 device is suitable for wide variety of cost-sensitive consumer applications requiring good performanceandoperationwitha5-Vanalogsupplyand3.3-Vdigitalsupply. 8.2 Typical Application Figure 28 illustrates a typical circuit connection diagram in which the cutoff frequency of the input HPF is about 8Hz. C1(1) + L-Ch IN 1 VINL MODE1 20 C2(1) + Mode [1:0] R-Ch IN 2 VINR MODE0 19 C5(3) + 3 VREF1 FMT1 18 Control C6(4) + Format [1:0] 4 VREF2 FMT0 17 R1(5) 5 V + C4(2) 5 VCC PCM1802 OSR 16 Oversampling 0 V 6 AGND SCKI 15 System Clock Control Power Down 7 PDWN VDD 14 + C3(2) 3.3 V LCF Bypass 8 BYPAS DGND 13 0 V 9 FSYNC DOUT 12 Data Out 10 LRCK BCK 11 Data Clock Audio Data Processor L/R Clock Frame Sync. S0026-02 Copyright © 2016,Texas Instruments Incorporated (1) C , C : A 1-µF capacitor gives a 8-Hz (τ = 1 µF × 20 kΩ) cutoff frequency for input HPF in normal operation and 1 2 requiresapower-onsettlingtimewitha20-mstimeconstantduringthepower-oninitializationperiod. (2) C ,C :Bypasscapacitors,0.1-µFceramicand10-µFtantalum,dependingonlayoutandpowersupply 3 4 (3) C :TIrecommends0.1-µFceramicand10-µFtantalumcapacitors. 5 (4) C :TIrecommends0.1-µFceramicand10-µFtantalumcapacitorswhenusinganoisyanalogpowersupply.These 6 capacitorarenotrequiredforacleananalogsupply. (5) R : TI recommends a 1-kΩ resistor when using a noisy analog power supply. This resistor is shorted for a clean 1 analogsupply. Figure28. TypicalCircuitConnection 22 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 Typical Application (continued) 8.2.1 DesignRequirements Forthisdesignexample,usetheparameterslistedinTable10 astheinputparameters. Table10.DesignParameters PARAMETER VALUE Analoginputvoltage 0V to3V P–P P–P Output PCMaudiodata Systemclockinputfrequency 2.048MHzto49.152MHz Outputsamplingfrequency 8kHzto96kHz Powersupply 3.3Vand5V 8.2.2 DetailedDesignProcedure 8.2.2.1 ControlPins The FMT, MODE, OSR, and BYPASS control pins are controlled by tying up to VDD, down to GND, or driven withGPIOfromtheDSPoraudioprocessor. 8.2.2.2 DSPorAudioProcessor In this application a DSP or audio processor acts as the audio master, and the PCM1802 acts as the audio slave.ThismeanstheDSPoraudioprocessormustbeabletooutputaudioclocksthatthePCM1802canuseto processaudiosignals. 8.2.2.3 InputFilters For the analog input circuit an AC-coupling capacitor must be placed in series with the input. This removes the DC component of the input signal. An RC filter can also be implemented to filter out of band noise to reduce aliasing.Equation1calculatesthecutofffrequencyoftheoptionalRCfilterfortheinput. 1 f = c 2pRC (1) 8.2.3 ApplicationCurve 0 Input Level =−0.5 dB Data Points = 8192 −20 −40 B d − −60 e d u plit −80 m A −100 −120 −140 0 5 10 15 20 f−Frequency−kHz G015 Figure29.AmplitudevsFrequency Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com 9 Power Supply Recommendations The PCM1802 requires a 5-V nominal supply and a 3.3-V nominal supply. The 5-V supply is for the analog circuitry powered by the VCC pin. The 3.3-V supply is for the digital circuitry powered by the VDD pin. The decouplingcapacitorsforthepowersuppliesmustbeplacedclosetothedevicepins. 10 Layout 10.1 Layout Guidelines 10.1.1 VCCandVDDPins The digital and analog power supply lines to the PCM1802 must be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF tantalum capacitors as close to the pins as possible to maximize the dynamic performanceoftheADC. 10.1.2 AGNDandDGNDPins To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connected internally. These grounds must have low impedance to avoid digital noise feeding back into the analog ground. Theymustbeconnecteddirectlytoeachotherunderthepartstoreducethepotentialnoiseproblem. 10.1.3 VINPins TI recommends a 1-µF capacitor for AC-coupling, which gives an 8-Hz cutoff frequency. A higher full-scale input voltage,ifrequired,canbeaccommodatedbyaddingonlyoneseriesresistortoeachVINpin. 10.1.4 VREF1Pin TI recommends a ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF between VREF1 and AGND to ensure low source impedance for the ADC references. These capacitors must be placed as close as possible totheVREF1pintoreducedynamicerrorsontheADCreferences. 10.1.5 VREF2Pin The differential voltage between VREF2 and AGND sets the analog input full-scale range. TI recommends a ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF between VREF2 and AGND with the insertion of a 1-kΩ resistor between VCC and VREF2 when using a noisy analog power supply. These capacitors and resistor are not required for a clean analog supply. These capacitors must be placed as close as possible to the VREF2 pin to reduce dynamic errors on the ADC references. Full-scale input level is affected by this 1-kΩ resistor,decreasingby3%. 10.1.6 DOUTPin The DOUT pin has enough load drive capability, but TI recommends placing a buffer near the PCM1802 and minimizing load capacitance if the DOUT line is long, to minimize the digital-analog crosstalk and maximize the dynamicperformanceoftheADC. 10.1.7 SystemClock The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on the system clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the time differencebetweenthesystemclocktransitionandtheBCKorLRCKtransition. 24 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PCM1802 www.ti.com SLES023D–DECEMBER2001–REVISEDDECEMBER2016 10.2 Layout Example It is recommended to place a top layer ground pour for shielding around PCM1802 and connect to lower main PCB ground plane by multiple vias Option External RC antialiasing circuit 1 (cid:29)F R-ch IN + L-ch IN 1 VINL MODE1 20 + 1 (cid:29)F Make sure to have 2 VINR MODE0 19 ground pour separating + chantnheel Ltreaftc easn tdo R higehlpt 3 VREF1 FMT1 18 Control prevent crosstalk Bypass Capacitors are + 0.1 uF and 10 uF 4 VREF2 PCM1802 FMT0 17 Mgroakuen dsu proeu tro s heapvaera ting the clock signals from 5V 5 VCC OSR 16 surrounding traces + 10 (cid:29)F 0.1 (cid:29)F 6 AGND SCKI 15 7 PDWN VDD 14 3.3V Control + 8 BYPAS DGND 13 0.1 (cid:29)F 10 (cid:29)F Clock signals to DSP or Audio 9 TEST DOUT 12 Processor 10 LRCK BCK 11 Top Layer Ground Pour Via to bottom Ground Plane Top Layer Signal Traces Pad to top layer ground pour Figure30. LayoutRecommendation Copyright©2001–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:PCM1802

PCM1802 SLES023D–DECEMBER2001–REVISEDDECEMBER2016 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.3 Trademarks E2EisatrademarkofTexasInstruments. SystemTwo,AudioPrecisionaretrademarksofAudioPrecision. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 26 SubmitDocumentationFeedback Copyright©2001–2016,TexasInstrumentsIncorporated ProductFolderLinks:PCM1802

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) PCM1802DB ACTIVE SSOP DB 20 65 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1802 & no Sb/Br) PCM1802DBG4 ACTIVE SSOP DB 20 65 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1802 & no Sb/Br) PCM1802DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1802 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) PCM1802DBR SSOP DB 20 2000 330.0 17.4 8.5 7.6 2.4 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) PCM1802DBR SSOP DB 20 2000 336.6 336.6 28.6 PackMaterials-Page2

PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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