(cid:2)(cid:17)(cid:14)(cid:14)(cid:20)(cid:2)(cid:14)(cid:13)(cid:18)(cid:12) (cid:4)(cid:14)(cid:13)(cid:8)(cid:17)(cid:7)(cid:16)(cid:15) (cid:10)(cid:14)(cid:13)(cid:11) (cid:5)(cid:9)(cid:19)(cid:6)(cid:15) (cid:3)(cid:12)(cid:15)(cid:16)(cid:14)(cid:17)(cid:11)(cid:9)(cid:12)(cid:16)(cid:15) PCM1801 SBAS131C–OCTOBER2000–REVISEDJULY2007 SINGLE-ENDED ANALOG-INPUT 16-BIT STEREO ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • Dual16-BitMonolithicΔΣADC • DVDRecorders • Single-EndedVoltageInput • DVDReceivers • AntialiasingFilterIncluded • AVAmplifierReceivers • 64· OversamplingDecimationFilter: • ElectricMusicalInstruments Pass-BandRipple:– 0.05dB DESCRIPTION Stop-BandAttenuation:–65dB • AnalogPerformance: The PCM1801 is a low-cost, single-chip stereo THD+N:–88dB(typical) analog-to-digital converter (ADC) with single-ended analog voltage inputs. The PCM1801 uses a SNR:93dB(typical) delta-sigma modulator with 64 times oversampling, a DynamicRange:93dB(typical) digital decimation filter, and a serial interface that InternalHigh-PassFilter supportsslavemodeoperationandtwodata formats. • PCMAudioInterface:Left-Justified,I2S The PCM1801 is suitable for a wide variety of • SamplingRate:4kHzto48kHz cost-sensitive consumer applications where good • SystemClock:256f ,384f ,or512f performanceisrequired. S S S • Single5-VPowerSupply • SmallSO-14Package PCM1801 (+) Single-End/ 5th Order VINL Differential Delta-Sigma Converter (−) Modulator BCK Serial Data ×1/64 Interface VREF1 Decimation LRCK Reference and VREF2 High-Pass DOUT Filter Format (−) Control Single-End/ 5th Order FMT VINR Differential Delta-Sigma Converter (+) Modulator BYPAS Clock/Timing Control SCKI Power Supply VCC AGND DGND VDD B0004-02 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SystemTwo,AudioPrecisionaretrademarksofAudioPrecision,Inc. Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2000–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERINGINFORMATION PRODUCT PACKAGE PACKAGE PACKAGE ORDERING TRANSPORT QUANTITY TYPE CODE MARKING NUMBER MEDIA PCM1801U Rails 56 PCM1801U 14-pinSOIC D PCM1801U PCM1801U/2K Tapeandreel 2000 ABSOLUTE MAXIMUM RATINGS Supplyvoltage:V ,V –0.3Vto6.5V DD CC Supplyvoltagedifferences:V ,V – 0.1V DD CC GNDvoltagedifferences:AGND,DGND – 0.1V Digitalinputvoltage –0.3Vto(V +0.3V),<6.5V DD Analoginputvoltage –0.3Vto(V +0.3V),<6.5V CC Inputcurrent(anypinexceptsupplies) – 10mA Powerdissipation 300mW Operatingtemperaturerange –25(cid:176) Cto85(cid:176) C Storagetemperature –55(cid:176) Cto125(cid:176) C Leadtemperature,soldering 260(cid:176) C,5s Packagetemperature(IRreflow,peak) 235(cid:176) C RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange MIN NOM MAX UNIT Analogsupplyvoltage,V 4.5 5 5.5 V CC Digitalsupplyvoltage,V 4.5 5 5.5 V DD Analoginputvoltage,full-scale(–0dB) 2.828 Vp-p Digitalinputlogicfamily TTL Systemclock 8.192 24.576 MHz Digitalinputclockfrequency Samplingclock 32 48 kHz Digitaloutputloadcapacitance 10 pF Operatingfree-airtemperature,T –25 85 (cid:176) C A 2 SubmitDocumentationFeedback

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 PINCONFIGURATION PCM1801 (TOP VIEW) V L 1 14 V 1 IN REF V R 2 13 V 2 IN REF DGND 3 12 AGND V 4 11 V DD CC SCKI 5 10 FMT BCK 6 9 BYPAS LRCK 7 8 DOUT P0005-01 Table1.PINASSIGNMENTS NAME PIN I/O DESCRIPTION AGND 12 – Analogground BCK 6 I Bitclockinput BYPAS 9 I HPFbypasscontrol(1) L:HPFenabled H:HPFdisabled DGND 3 – Digitalground DOUT 8 O Audiodataoutput FMT 10 I Audiodataformat(1) L:MSB-first,left-justified H:MSB-first,I2S LRCK 7 I Samplingclockinput SCKI 5 I Systemclockinput;256f ,384f ,or512f S S S V 11 – Analogpowersupply CC V 4 – Digitalpowersupply DD V L 1 I Analoginput,Lch IN V R 2 I Analoginput,Rch IN V 1 14 – Reference1decouplingcapacitor REF V 2 13 – Reference2decouplingcapacitor REF (1) With100-kW typicalpulldownresistor SubmitDocumentationFeedback 3

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS AllspecificationsatT =25(cid:176) C,V =V =5V,f =44.1kHz,16-bitdata,andSYSCLK=384f ,unlessotherwisenoted. A DD CC S S PCM1801U PARAMETER TESTCONDITIONS MIN TYP MAX UNITS RESOLUTION 16 Bits DIGITALINPUT/OUTPUT V (1) 2 IH Inputlogiclevel VDC V (1) 0.8 IL I (2) – 10 IN Inputlogiccurrent μA I (3) 100 IN V (4) I =–1.6mA 4.5 OH OH Outputlogiclevel VDC V (4) I =3.2mA 0.5 OL OL f Samplingfrequency 4 44.1 48 kHz S 256f 1.024 11.2896 12.288 S Systemclockfrequency 384f 1.536 16.9344 18.432 MHz S 512f 2.048 22.5792 24.576 S DCACCURACY Gainmismatch,channel-to-channel – 1 – 2.5 %ofFSR Gainerror – 2 – 5 %ofFSR Gaindrift – 20 ppmofFSR/(cid:176) C Bipolarzeroerror High-passfilterbypassed – 2 %ofFSR Bipolarzerodrift High-passfilterbypassed – 20 ppmofFSR/(cid:176) C DYNAMICPERFORMANCE(5) FS(–0.5dB) –88 –80 THD+N dB –60dB –90 Dynamicrange A-weighted 90 93 dB Signal-to-noiseratio A-weighted 90 93 dB Channelseparation 87 90 dB ANALOGINPUT Inputrange FS(V =0dB) 2.828 Vp-p IN Centervoltage 2.1 V Inputimpedance 30 kW Antialiasingfilterfrequencyresponse –3dB 150 kHz DIGITALFILTERPERFORMANCE Passband 0.454f Hz S Stopband 0.583f Hz S Pass-bandripple – 0.05 dB Stop-bandattenuation –65 dB Delaytime(latency) 17.4/f s S High-passfrequencyresponse –3dB 0.019f mHz S (1) Pins5,6,7,9,and10(SCKI,BCK,LRCK,BYPAS,andFMT) (2) Pins5,6,7(SCKI,BCK,LRCK)Schmitt-triggerinput (3) Pins9,10(BYPAS,FMT)Schmitt-triggerinputwith100-kW typicalpulldownresistor (4) Pin8(DOUT) (5) f =1kHz,usingtheSystemTwo™audiomeasurementsystembyAudioPrecision™inrmsmodewith20-kHzLPFand400-HzHPF IN intheperformancecalculation. 4 SubmitDocumentationFeedback

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatT =25(cid:176) C,V =V =5V,f =44.1kHz,16-bitdata,andSYSCLK=384f ,unlessotherwisenoted. A DD CC S S PCM1801U PARAMETER TESTCONDITIONS MIN TYP MAX UNITS POWERSUPPLYREQUIREMENTS V 4.5 5 5.5 CC Voltagerange VDC V 4.5 5 5.5 DD Supplycurrent(6) V =V =5V 18 24 mA CC DD Powerdissipation V =V =5V 90 120 mW CC DD TEMPERATURERANGE T Operation –25 85 (cid:176) C A T Storage –55 125 (cid:176) C stg θ Thermalresistance 100 (cid:176) C/W JA (6) NoloadonDOUT(pin8) BLOCKDIAGRAM PCM1801 (+) Single-End/ 5th Order VINL Differential Delta-Sigma Converter (−) Modulator BCK Serial Data ×1/64 Interface VREF1 Decimation LRCK Reference and VREF2 High-Pass DOUT Filter Format (−) Control Single-End/ 5th Order FMT VINR Differential Delta-Sigma Converter (+) Modulator BYPAS Clock/Timing Control SCKI Power Supply VCC AGND DGND VDD B0004-02 SubmitDocumentationFeedback 5

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 ANALOGFRONT-END(SingleChannel) 1 m F VINL 30 kW 1 − + − 1 kW (+) + + Delta-Sigma 1 kW (−) Modulator VREF1 14 4.7 m F + VREF 4.7 m F + VREF2 13 S0011-02 TYPICAL PERFORMANCE CURVES AllspecificationsatT =25(cid:176) C,V =V =5V,f =44.1kHz,andSYSCLK=384f ,unlessotherwisenoted A DD CC S S ANALOG DYNAMIC PERFORMANCE TOTALHARMONICDISTORTION+NOISE DYNAMICRANGEANDSIGNAL-TO-NOISERATIO vs vs TEMPERATURE TEMPERATURE 0.006 3.0 96 96 % % − − B B d d 5 0 B Total Harm. Dist. + Noise at −0. 000...000000345 −60 dB −0.5 dB 222...864 Total Harm. Dist. + Noise at −6 Dynamic Range − dB 999345 SNR Dynamic Range 999543 NR − Signal-to-Noise Ratio − d − − S N N + + D D H H T T 0.002 2.2 92 92 −25 0 25 50 75 100 −25 0 25 50 75 100 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C G001 G002 Figure1. Figure2. 6 SubmitDocumentationFeedback

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 TYPICAL PERFORMANCE CURVES (continued) AllspecificationsatT =25(cid:176) C,V =V =5V,f =44.1kHz,andSYSCLK=384f ,unlessotherwisenoted A DD CC S S TOTALHARMONICDISTORTION+NOISE DYNAMICRANGEANDSIGNAL-TO-NOISERATIO vs vs SUPPLYVOLTAGE SUPPLYVOLTAGE 0.006 3.0 96 96 % % − − B B d d 5 0 B m. Dist. + Noise at −0. 00..000045 −60 dB 22..86 m. Dist. + Noise at −6 mic Range − dB 9945 Dynamic Range 9954 al-to-Noise Ratio − d Total Har 0.003 2.4 Total Har Dyna 93 SNR 93 NR − Sign − −0.5 dB − S N N + + D D H H T T 0.002 2.2 92 92 4.25 4.50 4.75 5.00 5.25 5.50 5.75 4.25 4.50 4.75 5.00 5.25 5.50 5.75 VCC − Supply Voltage − V VCC − Supply Voltage − V G003 G004 Figure3. Figure4. TOTALHARMONICDISTORTION+NOISE DYNAMICRANGEANDSIGNAL-TO-NOISERATIO vs vs SAMPLINGRATE SAMPLINGRATE 0.006 3.0 96 96 % % − − B B d d m. Dist. + Noise at −0.5 00..000045 −60 dB 22..86 m. Dist. + Noise at −60 mic Range − dB 9945 Dynamic Range 9954 al-to-Noise Ratio − dB − Total Har 0.003 2.4 − Total Har Dyna 93 SNR 93 SNR − Sign N N + −0.5 dB + D D H H T T 0.002 2.2 92 92 32 44.1 48 32 44.1 48 Sampling Rate − kHz Sampling Rate − kHz G005 G006 Figure5. Figure6. SubmitDocumentationFeedback 7

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 TYPICAL PERFORMANCE CURVES (continued) AllspecificationsatT =25(cid:176) C,V =V =5V,f =44.1kHz,andSYSCLK=384f ,unlessotherwisenoted A DD CC S S SUPPLY CURRENT SUPPLYCURRENT SUPPLYCURRENT vs vs TEMPERATURE SUPPLYVOLTAGE 20 20 ICC + IDD ICC + IDD 16 16 A A m m − − ent 12 ent 12 Curr ICC Curr ICC y y pl pl p 8 p 8 u u − S IDD − S C C IDD C C I I 4 4 0 0 −25 0 25 50 75 100 4.25 4.50 4.75 5.00 5.25 5.50 5.75 TA − Free-Air Temperature − °C VCC − Supply Voltage − V G007 G008 Figure7. Figure8. SUPPLYCURRENT vs SAMPLINGRATE 20 ICC + IDD 16 A m − ent 12 ICC urr C y pl p 8 u S − C IDD C I 4 0 0 10 20 30 40 50 Sampling Rate − kHz G009 Figure9. 8 SubmitDocumentationFeedback

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 TYPICAL PERFORMANCE CURVES (continued) AllspecificationsatT =25(cid:176) C,V =V =5V,f =44.1kHz,andSYSCLK=384f ,unlessotherwisenoted A DD CC S S OUTPUT SPECTRUM FULL-SCALEFFT –60dBFSFFT 0 0 −20 −20 −40 −40 B B d d − −60 − −60 e e d d u u plit −80 plit −80 m m A A −100 −100 −120 −120 −140 −140 0 5 10 15 20 0 5 10 15 20 f − Frequency − kHz f − Frequency − kHz G010 G011 Figure10. Figure11. TOTALHARMONICDISTORTION+NOISE TOTALHARMONICDISTORTION+NOISE vs vs AMPLITUDE FREQUENCY 100 0.1 % % − − e e s s oi 10 oi N N + + n n stortio 1 stortio 0.01 Di Di c c ni ni o o m 0.1 m ar ar H H 0.001 al al ot ot T T − 0.01 − N N + + D D H H T T 0.001 0.0001 −100 −80 −60 −40 −20 0 20 100 1k 10k 20k Amplitude − dBV f − Frequency − Hz G012 G013 Figure12. Figure13. SubmitDocumentationFeedback 9

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 TYPICAL PERFORMANCE CURVES (continued) AllspecificationsatT =25(cid:176) C,V =V =5V,f =44.1kHz,andSYSCLK=384f ,unlessotherwisenoted A DD CC S S DECIMATION FILTER OVERALLCHARACTERISTICS STOP-BANDATTENUATIONCHARACTERISTICS 0 0 −20 −50 B B d d −40 − − e e d −100 d u u mplit mplit −60 A A −150 −80 −200 −100 0 8 16 24 32 0.00 0.25 0.50 0.75 1.00 Normalized Frequency [× fS Hz] Normalized Frequency [× fS Hz] G014 G015 Figure14. Figure15. PASS-BANDRIPPLECHARACTERISTICS TRANSITIONBANDCHARACTERISTICS 0.2 0 −1 0.0 −2 −3 −0.2 B B d d −4 − − e e d −0.4 d −5 u u mplit mplit −6 A A −0.6 −7 −8 −0.8 −9 −4.13 dB at 0.5 fS −1.0 −10 0.0 0.1 0.2 0.3 0.4 0.5 0.45 0.47 0.49 0.51 0.53 0.55 Normalized Frequency [× fS Hz] Normalized Frequency [× fS Hz] G016 G017 Figure16. Figure17. 10 SubmitDocumentationFeedback

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 TYPICAL PERFORMANCE CURVES (continued) AllspecificationsatT =25(cid:176) C,V =V =5V,f =44.1kHz,andSYSCLK=384f ,unlessotherwisenoted A DD CC S S HIGH-PASS FILTER HIGH-PASSFILTERRESPONSE HIGH-PASSFILTERRESPONSE 0 0.2 −10 0.0 −20 −30 −0.2 B B d −40 d − − e e d −50 d −0.4 u u mplit −60 mplit A A −0.6 −70 −80 −0.8 −90 −100 −1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency [× fS/1000 Hz] Normalized Frequency [× fS/1000 Hz] G018 G019 Figure18. Figure19. ANTIALIASING FILTER ANTIALIASINGFILTER ANTIALIASINGFILTER STOP-BANDCHARACTERISTICS PASS-BANDCHARACTERISTICS 0 0.2 0.0 −10 −0.2 B B d −20 d − − e e d d −0.4 u u mplit −30 mplit A A −0.6 −40 −0.8 −50 −1.0 1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k f − Frequency − Hz f − Frequency − Hz G020 G021 Figure20. Figure21. SubmitDocumentationFeedback 11

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 THEORY OF OPERATION The PCM1801 consists of a band-gap reference, two channels of a single-to-differential converter, a fully differential5th-orderdelta-sigma modulator, a decimation filter (including digital high-pass), and a serial interface circuit. The block diagram illustrates the total architecture of the PCM1801, and the analog front-end diagram illustrates the architecture of the single-to-differential converter and the antialiasing filter. Figure 22 illustrates the architectureofthe5th-orderdelta-sigmamodulatorandtransferfunctions. An internal high-precision reference with two external capacitors provides all reference voltages which are requiredby the converter, and defines the full-scale voltage range of both channels. The internal single-ended to differential voltage converter saves the design, space, and extra parts needed for external circuitry required by many delta-sigma converters. The internal full-differential architecture provides a wide dynamic range and excellentpower-supplyrejectionperformance. The input signal is sampled at a 64· oversampling rate, eliminating the need for a sample-and-hold circuit and simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a 1-bit digital-to-analog converter (DAC). The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs,reducingidletonelevels. The 64-f , 1-bit stream from the modulator is converted to 1-f , 16-bit digital data by the decimation filter, which S S also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a digital high-pass filter, and the filtered output is converted to time-multiplexed serial signals through a serial interfacewhichprovidesflexibleserialformats. Analog In X(z) + 1st + − 2nd 3rd + − 4th 5th SW-CAP SW-CAP SW-CAP SW-CAP SW-CAP − Integrator Integrator Integrator Integrator Integrator Qn(z) Digital Out + + + + + + + + Y(z) H(z) Comparator 1-Bit DAC Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function STF(z) = H(z) / [1 + H(z)] Noise Transfer Function NTF(z) = 1 / [1 + H(z)] B0005-01 Figure22.SimplifiedDiagramofthePCM18015th-OrderDelta-SigmaModulator SYSTEM CLOCK The system clock for the PCM1801 must be either 256 f , 384 f or 512 f , where f is the audio sampling S S, S S frequency.ThesystemclockmustbesuppliedonSCKI(pin5). The PCM1801 also has a system clock detection circuit that automatically senses if the system clock is operatingat256f ,384f ,or512f . S S S When a 384-f or 512-f system clock is used, the PCM1801 automatically divides the clock down to 256 f S S S internally. This 256-f clock is used to operate the digital filter and the modulator. Table 2 lists the relationship of S typicalsamplingfrequenciesandsystemclockfrequencies.Figure23illustratesthesystemclocktiming. 12 SubmitDocumentationFeedback

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 Table2.SystemClockFrequencies SAMPLINGRATEFREQUENCY SYSTEMCLOCKFREQUENCY (kHz) 256f 384f 512f s s s 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 tCLKIH tCLKIL 2 V SCKI 0.8 V T0005-04 Systemclockpulseduration,HIGH t 12ns(min) (CLKIH) Systemclockpulseduration,LOW t 12ns(min) (CLKIL) Figure23.SystemClockTiming POWER-ON RESET The PCM1801 has an internal power-on reset circuit, which initializes (resets) when the supply voltage (V /V ) exceeds 4 V (typical). Because the system clock is used as the clock signal for the reset circuit, the CC DD system clock must be supplied as soon as power is applied; more specifically, the device must receive at least threesystemclockcyclesbeforeV >4V.WhileV /V <4V(typical)andfor1024systemclockcycles after DD CC DD V /V > 4 V, the PCM1801 stays in the reset state and the digital output is forced to zero. The digital output is CC DD valid 18,436 f periods after release from the reset state. Figure 24 illustrates the internal power-on reset timing S andthedigitaloutputforpower-onreset. 4.4 V VCC / VDD 4 V 3.6 V Reset Reset Removal Internal Reset 3 Clocks Minimum 1024 System Clocks 18436 / fS System Clock DOUT Zero Data Normal Data(1) T0014-02 (1) Thetransientresponse(exponentiallyattenuatedsignalfrom– 0.2%dcofFSRwitha200-mstimeconstant)appears initially. Figure24.InternalPower-OnResetTiming SubmitDocumentationFeedback 13

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 SERIAL AUDIO DATA INTERFACE ThePCM1801interfacestheaudiosystemthroughBCK(pin6),LRCK(pin7),andDOUT(pin8). The PCM1801 accepts 64-BCK/LRCK, 48-BCK/LRCK (only for a 384-f system clock) or 32-BCK/LRCK format S for the left-justified format. And the PCM1801 accepts the 64-BCK/LRCK or 48-BCK/LRCK format (only for a 384-f systemclock)forI2Sformat. S DATAFORMAT The PCM1801 supports two audio data formats in slave mode, which are selected by the FMT control input (pin 10) as shown in Table 3. Figure 25 illustrates the data format. If the application system cannot ensure an effective system clock prior to power up of the PCM1801, the FMT pin must be held LOW until the power-on resetsequenceiscompleted.Inthiscase,iftheI2Sformat(FMT=HIGH)isrequiredin the application, FMT can besetHIGHafterthepower-onresetsequenceiscompleted. Table3.DataFormat FMT DATAFORMAT 0(L) 16-bit,left-justified 1(H) 16-bit,I2S FMT = L 16-Bit, MSB-First, Left-Justified LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 14 15 16 1 2 3 14 15 16 1 MSB LSB MSB LSB FMT = H 16-Bit, MSB-First, I2S LRCK Left-Channel Right-Channel BCK DOUT 1 2 3 14 15 16 1 2 3 14 15 16 MSB LSB MSB LSB T0016-03 Figure25.AudioDataFormat 14 SubmitDocumentationFeedback

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 INTERFACETIMING Figure26illustratestheinterfacetiming. t(LRCP) LRCK 1.4 V t(BCKL) t(LRSU) t(BCKH) t(LRHD) BCK 1.4 V t(BCKP) t(CKDO) t(LRDO) DOUT 0.5 VDD T0017-02 DESCRIPTION SYMBOL MIN TYP MAX UNITS BCKperiod t 300 ns (BCKP) BCKpulseduration,HIGH t 120 ns (BCKH) BCKpulseduration,LOW t 120 ns (BCKL) LRCKsetuptimetoBCKrisingedge t 80 ns (LRSU) LRCKholdtimetoBCKrisingedge t 40 ns (LRHD) LRCKperiod t 20 μs (LRCP) Delaytime,BCKfallingedgetoDOUTvalid t –20 40 ns (CKDO) Delaytime,LRCKedgetoDOUTvalid t –20 40 ns (LRDO) Risingtimeofallsignals t 20 ns (RISE) Fallingtimeofallsignals t 20 ns (FALL) NOTE: Timing measurement reference level is (V + V )/2. Rising and falling time is IH IL measuredfrom10%to90%oftheI/Osignalswing.LoadcapacitanceoftheDOUT signalis20pF. Figure26.AudioDataInterfaceTiming SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM The PCM1801 operates with LRCK synchronized to the system clock (SCKI). The PCM1801 does not require a specificphaserelationshipbetweenLRCKandSCKI,but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than 6 bit clocks (BCK) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/f and the digital output is forced to BPZ until S resynchronization between LRCK and SCKI is completed. In case of changes less than 5 bit clocks (BCK), resynchronization does not occur and the previously described digital output control and discontinuity do not occur. Figure 27 illustrates the ADC digital output for lost synchronization and resynchronization. During undefined data, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal makes a discontinuity of data on the digital output and may generate somenoiseintheaudiosignal. SubmitDocumentationFeedback 15

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 Synchronization Lost Resynchronization State of Synchronization Synchronous Asynchronous Synchronous 1/fS 32/fS Undefined DOUT Normal Data Zero Data Normal Data(1) Data T0020-02 (1) Thetransientresponse(exponentiallyattenuatedsignalfrom– 0.2%dcofFSRwith200-mstimeconstant)appears initially. Figure27.ADCDigitalOutputforLossofSynchronizationandRe-Synchronization HPFBypassControl The built-in function for dc component rejection can be bypassed by BYPAS (pin 9) control (see Table 4). In bypass mode, the dc component of the input analog signal, the internal dc offset, etc., are also converted and outputinthedigitaloutputdata. Table4.HPFBypassControl BYPAS HIGH-PASSFILTER(HPF)MODE Low Normal(dccut)mode High Bypass(through)mode APPLICATION INFORMATION BOARD DESIGN AND LAYOUT CONSIDERATIONS V ,V PINS CC DD The digital and analog power supply lines to the PCM1801 should be bypassed to the corresponding ground pins with both 0.1-μF ceramic and 10-μF tantalum capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. Although the PCM1801 has two power lines to maximize the potential of dynamic performance, using one common power supply is recommended to avoid unexpected power supply problems,suchaslatch-upduetopowersupplysequencing. AGND,DGNDPINS To maximize the dynamic performance of the PCM1801, the analog and digital grounds are not internally connected. These points should have low impedance to avoid digital noise feedback into the analog ground. They should be connected directly to each other under the PCM1801 package to reduce potential noise problems. V PINS IN A 1.0-μF tantalum capacitor is recommended as an ac-coupling capacitor, which establishes a 5.3-Hz cutoff frequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding a seriesresistortotheV pins. IN V PINS REF To ensure low source impedance, 4.7-μF tantalum capacitors are recommended from V 1 to AGND and from REF V 2 to AGND. These capacitors should be located as close as possible to the V 1 and V 2 pins to reduce REF REF REF dynamicerrorsontheADCreferences. 16 SubmitDocumentationFeedback

PCM1801 www.ti.com SBAS131C–OCTOBER2000–REVISEDJULY2007 APPLICATION INFORMATION (continued) DOUTPIN The DOUT pin has a large load-drive capability, but locating a buffer near the PCM1801 and minimizing load capacitance is recommended in order to minimize the digital-analog crosstalk and maximize the dynamic performanceoftheADC. FMTPIN In general, the FMT pin is used for audio data format selection by tying up DGND or V in accordance with DD interface requirements. If the application system cannot ensure an effective system clock prior to power up of the PCM1801 when I2S format is required, then the FMT pin must be set HIGH after the power-on reset sequence. This input control can be accomplished easily by connecting a C-R delay circuit with a delay time greaterthan1mstotheFMTpin. SYSTEMCLOCK The quality of the system clock can influence dynamic performance in the PCM1801. The duty cycle, jitter, and threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure to supply the audio clocks results in a power dissipation increase of up to three times normal dissipation and may degradelong-termreliabilityifthemaximumpowerdissipationlimitisexceeded. TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 28 is a typical connection diagram illustrating a circuit for which the input HPF cutoff frequency is about 5Hz. C1(1) + + C6(3) Lch In 1 VINL VREF1 14 C2(1) + + C5(3) Rch In 2 VINR VREF2 13 3 DGND AGND 12 0 V C3(2) C4(2) 4 VDD VCC 11 +5 V System Clock 5 SCKI FMT 10 Format Pin Program Data Clock 6 BCK BYPAS 9 Bypass or Control Audio Latch Enable 7 LRCK DOUT 8 Data Processor Data Out S0013-01 (1) C1andC2:A1-μFcapacitorgivesa5.3-Hz(τ=1μF*30kW )cutofffrequencyfortheinputHPFinnormaloperation andrequiresapower-onsettingtimeof30msatpowerup. (2) C3 and C4: Bypass capacitors, 0.1-μF ceramic and 10-μF tantalum or aluminum electrolytic, depending on layout andpowersupply (3) C5andC6:4.7-μFtantalumoraluminumelectrolyticcapacitors Figure28.TypicalCircuitConnection SubmitDocumentationFeedback 17

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) PCM1801U ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM PCM1801U & no Sb/Br) PCM1801U/2K ACTIVE SOIC D 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM PCM1801U & no Sb/Br) PCM1801U/2KG4 ACTIVE SOIC D 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM PCM1801U & no Sb/Br) PCM1801UG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM PCM1801U & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Dec-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) PCM1801U/2K SOIC D 14 2000 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Dec-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) PCM1801U/2K SOIC D 14 2000 367.0 367.0 38.0 PackMaterials-Page2

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