PCM1741 PCM1741 www.ti.com +3.3V Single-Supply, 24-Bit, 96kHz Sampling Enhanced Multilevel, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS (cid:1) 24-BIT RESOLUTION (cid:1) AV RECEIVERS (cid:1) ANALOG PERFORMANCE (V = +3.3V): (cid:1) DVD MOVIE PLAYERS CC Dynamic Range: 98dB typ (cid:1) DVD ADD-ON CARDS FOR HIGH-END PCs SNR: 98dB typ (cid:1) HDTV RECEIVERS THD+N: 0.005% typ (cid:1) CAR AUDIO SYSTEMS Full-Scale Output: 2.05Vp-p typ (cid:1) OTHER APPLICATIONS REQUIRING 24-BIT (cid:1) 8x OVERSAMPLING DIGITAL FILTER: AUDIO Stopband Attenuation: –55dB ± Passband Ripple: 0.03dB DESCRIPTION (cid:1) SAMPLING FREQUENCY: 5kHz to 100kHz The PCM1741 is a CMOS, monolithic, integrated circuit (cid:1) SYSTEM CLOCK: 256, 384, 512, 768f with S which includes stereo Digital-to-Analog Converters Auto Detect (DACs) and support circuitry in a small SSOP-16 package. (cid:1) ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO The data converters utilize Texas Instrument’s enhanced DATA multilevel delta-sigma architecture that employs fourth- (cid:1) DATA FORMATS: Standard, I2S, and Left- order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved toler- Justified ance to clock jitter. The PCM1741 accepts industry standard (cid:1) USER-PROGRAMMABLE MODE CONTROLS: audio data formats with 16- to 24-bit data, providing easy Digital Attenuation: 0dB to –63dB, 0.5dB/Step interfacing to audio DSP and decoder chips. Sampling rates Digital De-Emphasis up to 100kHz are supported. A full set of user-program- Digital Filter Roll-Off: Sharp or Slow mable functions are accessible through a 3-wire serial control port that supports register write functions. Soft Mute Zero Flags for Each Output (cid:1) 3.3V SINGLE POWER SUPPLY (cid:1) 5V TOLERANT DIGITAL INPUTS (cid:1) SMALL SSOP-16 PACKAGE Copyright © 2000, Texas Instruments Incorporated SBAS175 Printed in U.S.A. December, 2000

SPECIFICATIONS All specifications at T = +25°C, V = 5.0V, V = 3.3V, f = 44.1kHz, system clock = 384f , and 24-bit data, unless otherwise noted. A CC DD S S PCM1741E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 24 Bits DATA FORMAT Audio Data Interface Formats Standard, I2S, Left-Justified Audio Data Bit Length 16-, 18-, 20-, 24-Bits Selectable Audio Data Format MSB-First, Binary Two’s Complement Sampling Frequency (f ) 5 100 kHz S System Clock Frequency 256, 384, 512, 768f S DIGITAL INPUT/OUTPUT Logic Family TTL-Compatible Input Logic Level V 2.0 VDC IH V 0.8 VDC IL Input Logic Current I (1) V = V 10 µA IH IN DD I (1) V = 0V –10 µA IL IN I (2) V = V 65 100 µA IH IN DD I (2) V = 0V –10 µA IL IN Output Logic Level V (3) I = –2mA 2.4 VDC OH OH V (3) I = +2mA 1.0 VDC OL OL DYNAMIC PERFORMANCE(4) PCM1741E THD+N at V = 0dB f = 44.1kHz 0.005 0.01 % OUT S f = 96kHz 0.007 % S THD+N at V = –60dB f = 44.1kHz 1.6 % OUT S f = 96kHz 2.0 % S Dynamic Range EIAJ, A-Weighted, f = 44.1kHz 92 98 dB S A-Weighted, f = 96kHz 96 dB S Signal-to-Noise Ratio EIAJ, A-Weighted, f = 44.1kHz 92 98 dB S A-Weighted, f = 96kHz 96 dB S Channel Separation f = 44.1kHz 90 96 dB S f = 96kHz 94 dB S Level Linearity Error V = –90dB ±0.5 dB OUT DC ACCURACY Gain Error ±1.0 ±6 % of FSR Gain Mismatch, Channel-to-Channel ±1.0 ±3 % of FSR Bipolar Zero Error V = 0.5 V at Bipolar Zero ±30 ±60 mV OUT CC ANALOG OUTPUT Output Voltage Full Scale (0dB) 62% of V Vp-p CC Center Voltage 50% of V VDC CC Load Impedance AC Load 5 kΩ DIGITAL FILTER PERFORMANCE Filter Characteristics 1, Sharp Roll-Off Passband ±0.03dB 0.454f S Passband –3dB 0.487f S Stopband 0.546f dB S Passband Ripple ±0.03 dB Stopband Attenuation Stopband = 0.546f –50 dB S Stopband Attenuation Stopband = 0.567f –55 S Filter Characteristics 2, Slow Roll-Off Passband ±0.5dB 0.198f S Passband –3dB 0.390f S Stopband 0.884f S Passband Ripple ±0.5 dB Stopband Attenuation Stopband = 0.884f –40 dB S Delay Time 20/f sec S De-Emphasis Error ±0.1 dB 2 PCM1741 SBAS175

SPECIFICATIONS (Cont.) All specifications at T = +25°C, V = 5.0V, V = 3.3V, system clock = 384f (f = 44.1kHz), and 24-bit data, unless otherwise noted. A CC DD S S PCM1741E PARAMETER CONDITIONS MIN TYP MAX UNITS ANALOG FILTER PERFORMANCE Frequency Response f = 20kHz –0.03 dB f = 44kHz –0.20 dB POWER SUPPLY REQUIREMENTS(4) Voltage Range, V +2.7 +3.3 +3.6 VDC DD V +2.7 +3.0 +3.6 VDC CC Supply Current, I f = 44.1kHz 6.0 10 mA DD S f = 96kHz 13.0 mA S I f = 44.1kHz 7.0 11 mA CC S f = 96kHz 7.0 mA S Power Dissipation f = 44.1kHz 43 88 mW S f = 96kHz 66 mW S TEMPERATURE RANGE Operation Temperature –25 +85 °C Thermal Resistance θ SSOP-16 115 °C/W JA NOTES: (1) Pins 1, 2, 3, 16 (SCK, BCK, LRCK, DATA). (2) Pins 13-15 (MD, MC, ML). (3) Pins 11, 12 (ZEROR, ZEROL). (4) Analog performance specifications are tested with a Shibasoku #725 THD Meter with 400Hz HPF on, 30kHz LPF on, and an average mode with 20kHz bandwidth limiting. The load connected to the analog output is 5kΩ or larger, via capacitive coupling. ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC Power Supply Voltage, VDD..............................................................+4.0V DISCHARGE SENSITIVITY V ..............................................................+6.5V CC Ground Voltage Differences..............................................................±0.1V This integrated circuit can be damaged by ESD. Burr-Brown Digital Input Voltage................................................–0.3V to (6.5V + 0.3V) Input Current (except power supply)...............................................±10mA recommends that all integrated circuits be handled with Ambient Temperature Under Bias..................................–40°C to +125°C appropriate precautions. Failure to observe proper handling Storage Temperature......................................................–55°C to +150°C and installation procedures can cause damage. Junction Temperature....................................................................+150°C Lead Temperature (soldering, 5s)................................................. +260°C ESD damage can range from subtle performance degradation Package Temperature (IR reflow, 10s)..........................................+235°C to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA PCM1741E SSOP-16 322 –25°C to +85°C PCM1741E PCM1741E Rails " " " " " PCM1741E/2K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM1741E/2K” will yield a single 2000-piece Tape and Reel. PCM1741 3 SBAS175

BLOCK DIAGRAM BCK Audio LRCK Serial DAC Output Amp and VOUTL Port Low-Pass Filter 8x DATA Oversampling Enhanced Digital Filter Multilevel with Delta-Sigma V Function Modulator COM ML Controller Serial Output Amp and DAC MC Control Low-Pass Filter V R OUT Port MD System Clock System Clock SCK Zero Detect Power Supply Manager L R D D C D RO RO VD GN VC GN E E D A Z Z PIN CONFIGURATION PIN ASSIGNMENTS TOP VIEW SSOP PIN NAME TYPE FUNCTION 1 BCK IN Audio Data Bit Clock Input.(1) 2 DATA IN Audio Data Digital Input.(1) 3 LRCK IN L-Channel and R-Channel Audio Data Latch En- BCK 1 16 SCK able Input.(1) 4 DGND – Digital Ground DATA 2 15 ML 5 V – Digital Power Supply, +3.3V DD LRCK 3 14 MC 6 VCC – Analog Power Supply, +3.3V 7 V L OUT Analog Output for L-Channel. OUT DGND 4 13 MD PCM1741 8 VOUTR OUT Analog Output for R-Channel. V 5 12 ZEROL/NA 9 AGND – Analog Ground DD 10 V – Common Voltage Decoupling. V 6 11 ZEROR/ZEROA COM CC 11 ZEROR/ OUT Zero Flag Output for R-Channel/Zero Flag Output V L 7 10 V ZEROA for L/R-Channel. OUT COM 12 ZEROL/NA OUT Zero Flag Output for L-Channel/No Assign. V R 8 9 AGND OUT 13 MD IN Mode Control Data Input.(2) 14 MC IN Mode Control Clock Input.(2) 15 ML IN Mode Control Latch Input.(2) 16 SCK IN System Clock Input. NOTES: (1) Schmitt-trigger input, 5V tolerant. (2) Schmitt-trigger with internal pull-down, 5V tolerant. 4 PCM1741 SBAS175

TYPICAL PERFORMANCE CURVES All specifications at T = +25°C, V = V = 3.3V, system clock = 384f (f = 44.1kHz), and 24-bit input data, unless otherwise noted. A CC DD S S DIGITAL FILTER Digital Filter (De-Emphasis Off FREQUENCY RESPONSE PASSBAND FREQUENCY RESPONSE (Sharp Roll-Off) (Sharp Roll-Off) 0 0.05 0.04 –20 0.03 –40 0.02 dB) –60 dB) 0.01 de ( de ( 0 plitu –80 plitu –0.01 m m A –100 A –0.02 –0.03 –120 –0.04 –140 –0.05 0 1 2 3 4 0 0.1 0.2 0.3 0.4 0.5 Frequency (x f ) Frequency (x f ) S S FREQUENCY RESPONSE (Slow Roll-Off) TRANSITION CHARACTERISTICS (Slow Roll-Off) 0 5 4 –20 3 –40 2 B) B) 1 d –60 d de ( de ( 0 u u plit –80 plit –1 m m A –100 A –2 –3 –120 –4 –140 –5 0 1 2 3 4 0 0.1 0.2 0.3 0.4 0.5 Frequency (x f ) Frequency (x f ) S S De-Emphasis DE-EMPHASIS (f = 32kHz) DE-EMPHASIS ERROR (f = 32kHz) S S 0.0 0.5 –1.0 0.4 –2.0 0.3 –3.0 0.2 –4.0 0.1 B) B) Level (d ––56..00 Error (d –00..01 –7.0 –0.2 –8.0 –0.3 –9.0 –0.4 –10.0 –0.5 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 Frequency (kHz) Frequency (kHz) PCM1741 5 SBAS175

TYPICAL PERFORMANCE CURVES (Cont.) All specifications at T = +25°C, V = V = 3.3V, system clock = 384f (f = 44.1kHz), and 24-bit input data, unless otherwise noted. A CC DD S S De-Emphasis (Cont.) DE-EMPHASIS (f = 44.1kHz) DE-EMPHASIS ERROR (f = 44.1kHz) S S 0.0 0.5 –1.0 0.4 –2.0 0.3 –3.0 0.2 –4.0 0.1 B) B) Level (d ––56..00 Error (d –00..01 –7.0 –0.2 –8.0 –0.3 –9.0 –0.4 –10.0 –0.5 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 Frequency (kHz) Frequency (kHz) DE-EMPHASIS (f = 48kHz) DE-EMPHASIS ERROR (f = 48kHz) S S 0.0 0.5 –1.0 0.4 –2.0 0.3 –3.0 0.2 –4.0 0.1 B) B) Level (d ––56..00 Error (d –00..01 –7.0 –0.2 –8.0 –0.3 –9.0 –0.4 –10.0 –0.5 0 2 4 6 8 10 12 14 16 18 22 0 2 4 6 8 10 12 14 16 18 22 Frequency (kHz) Frequency (kHz) ANALOG DYNAMIC PERFORMANCE All specifications at T = +25°C, V = 5.0V, V = 3.3V, and 24-bit input data, unless otherwise noted. A CC DD Supply-Voltage Characteristics THD+N vs V DYNAMIC RANGE vs V CC CC 10 106 –60dB/96kHz, 384fS 104 102 1 –60dB/44.1kHz, 384fS dB) 100 44.1kHz, 384fS %) ge ( 98 N ( 0.1 an 96 + R THD 0dB/96kHz, 384fS namic 9942 96kHz, 384fS 0.01 Dy 90 88 0dB/44.1kHz, 384f S 0.001 86 2.4 2.7 3 3.3 3.6 3.9 2.4 2.7 3 3.3 3.6 3.9 V (V) V (V) CC CC 6 PCM1741 SBAS175

TYPICAL PERFORMANCE CURVES (Cont.) All specifications at T = +25°C, V = V = 3.3V, and 24-bit input data, unless otherwise noted. A CC DD Supply-Voltage Characteristics (Cont.) SNR vs V CHANNEL SEPARATION vs V CC CC 106 106 104 104 102 102 44.1kHz, 384f B) 100 S d 100 n ( B) 98 atio 98 44.1kHz, 384fS R (d 96 epar 96 SN 94 96kHz, 384fS el S 94 92 n 92 n 90 Cha 90 96kHz, 384fS 88 88 86 86 2.4 2.7 3 3.3 3.6 3.9 4.2 2.4 2.7 3 3.3 3.6 3.9 V (V) V (V) CC CC Temperature Characteristics THD+N vs T DYNAMIC RANGE vs T A A 10 106 –60dB/96kHz, 384f S 104 102 1 B) 100 44.1kHz, 384fS –60dB/44.1kHz, 384f d %) S ge ( 98 N ( 0.1 an 96 + R THD 0dB/96kHz, 384fS namic 9942 96kHz, 384fS 0.01 Dy 90 88 0dB/44.1kHz, 384f S 0.001 86 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) SNR vs T CHANNEL SEPARATION vs T A A 106 106 104 104 102 102 100 44.1kHz, 384fS dB) 100 n ( 44.1kHz, 384f 98 o 98 S B) ati R (d 96 epar 96 N 94 S 94 S 96kHz, 384fS el 92 n 92 90 Chan 90 96kHz, 384fS 88 88 86 86 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) PCM1741 7 SBAS175

SYSTEM CLOCK AND RESET POWER-ON RESET FUNCTIONS FUNCTIONS The PCM1741 includes a power-on reset function, as shown in Figure 2. With the system clock active, and V > 2.0V (typical DD SYSTEM CLOCK INPUT 1.6V to 2.4V), the power-on reset function will be enabled. The initialization sequence requires 1024 system clocks from the The PCM1741 requires a system clock for operating the time V > 2.0V. After the initialization period, the PCM1741 digital interpolation filters and multilevel delta-sigma modu- DD will be set to its reset default state, as described in the Mode lators. The system clock is applied at the SCK input (pin 16). Control Register section of this data sheet. Table I shows examples of system clock frequencies for common audio sampling rates. During the reset period (1024 system clocks), the analog Figure 1 shows the timing requirements for the system clock outputs are forced to the bipolar zero level, or V /2. After CC input. For optimal performance, it is important to use a clock the reset period, the internal register is initialized in the next source with low phase jitter and noise. The PLL1700 multi- 1/f period and, if SCK, BCK, and LRCK are provided S clock generator from Texas Instruments is an excellent choice continuously, the PCM1741 provides proper analog output for providing the PCM1741 system clock. with unit group delay against the input data. SYSTEM CLOCK FREQUENCY (f ) (MHz) SCLK SAMPLING FREQUENCY 256f 384f 512f 768f S S S S 8kHz 2.0480 3.0720 4.0960 6.1440 16kHz 4.0960 6.1440 8.1920 12.2880 32kHz 8.1920 12.2880 16.3840 24.5760 44.1kHz 11.2896 16.9344 22.5792 33.8688 48kHz 12.2880 18.4320 24.5760 36.8640 88.2kHz 22.5792 33.8688 45.1584 See Note (1) 96kHz 24.5760 36.8640 49.1520 See Note (1) NOTE: (1) The 768f system clock rate is not supported for f > 64kHz. S S TABLE I.System Clock Rates for Common Audio Sampling Frequencies. t SCKH “H” 2.0V System Clock 0.8V “L” tSCKL System clock pulse cycle time(1) System Clock Pulse Width HIGH t : 7ns (min) SCKH System Clock Pulse Width LOW t : 7ns (min) SCKL NOTE: (1) 1/256f , 1/384f , 1/512f , and 1/768f . S S S S FIGURE 1. System Clock Input Timing. 2.4V VDD 2.0V 1.6V 0V Reset Reset Removal Internal Reset Don't Care 1024 System Clocks System Clock FIGURE 2. Power-On Reset Timing. 8 PCM1741 SBAS175

AUDIO SERIAL INTERFACE held when the sampling rate clock of LRCK is changed or SCK and/or BCK is broken at least for one clock cycle. If The audio serial interface for the PCM1741 is comprised of SCK, BCK, and LRCK are provided continuously after this a 3-wire synchronous serial port. It includes LRCK (pin 3), hold condition, the internal operation will be resynchronized BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit automatically, less than 3/f period. In this resynchronize clock, and is used to clock the serial data present on DATA S period, and following 3/f , analog output is forced to the into the audio interface’s serial shift register. Serial data is S bipolar zero level, or V /2. External resetting is not required. clocked into the PCM1741 on the rising edge of BCK. CC LRCK is the serial audio left/right word clock used to latch serial data into the serial audio interface’s internal registers. AUDIO DATA FORMATS AND TIMING Both LRCK and BCK should be synchronous to the The PCM1741 supports industry-standard audio data formats, system clock. Ideally, it is recommended that LRCK and including Standard, I2S, and Left-Justified, as shown in BCK be derived from the system clock input, SCK. LRCK Figure 3. Data formats are selected using the format bits, is operated at the sampling frequency, f . BCK may be FMT[2:0], in Control Register 20. The default data format is S operated at 32, 48, or 64 times the sampling frequency (I2S 24-bit left justified. All formats require Binary Two’s Comple- format except BCK = 32f ). Internal operation of the ment, MSB-first audio data. See Figure 4 for a detailed timing S PCM1741 is synchronized with LRCK. Accordingly, it is diagram of the serial audio interface. (1) Standard Data Format: L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32, 48 or 64fS) 16-Bit Right-Justified, BCK = 48fS or 64fS DATA 14 15 16 1 2 3 14 15 16 1 2 3 14 15 16 16-Bit Right-Justified, BCK = 32fS MSB LSB MSB LSB DATA 14 15 16 1 2 3 14 15 16 1 2 3 14 15 16 MSB LSB MSB LSB 18-Bit Right-Justified DATA 16 17 18 1 2 3 16 17 18 1 2 17 18 MSB LSB MSB LSB 20-Bit Right-Justified DATA 18 19 20 1 2 3 18 19 20 1 2 3 18 19 20 MSB LSB MSB LSB 24-Bit Right-Justified DATA 22 23 24 1 2 3 22 23 24 1 2 3 22 23 24 MSB LSB MSB LSB (2) I2S Data Format: L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK (= 48 or 64fS) DATA 1 2 3 N-2N-1 N 1 2 3 N-2N-1 N 1 2 MSB LSB MSB LSB (3) Left-Justified Data Format: L-Channel = HIGH, R-Channel = LOW 1/fS L-Channel LRCK R-Channel BCK (= 32, 48 or 64fS) DATA 1 2 3 N-2N-1 N 1 2 3 N-2N-1 N 1 2 MSB LSB MSB LSB FIGURE 3. Audio Data Input Formats. PCM1741 9 SBAS175

LRCK 50% of V DD t t t BCH BCL LB BCK 50% of V DD t t BCY BL DATA 50% of V DD t t DS DH SYMBOL PARAMETER MIN MAX UNITS t BCK Pulse Cycle Time 32, 48, or 64f(1) BCY S t BCK High Level Time 35 ns BCH t BCK Low Level Time 35 ns BCL t BCK Rising Edge to LRCK Edge 10 ns BL t LRCK Falling Edge to BCK Rising Edge 10 ns LB t DATA Set Up Time 10 ns DS t DATA Hold Time 10 ns DH NOTE: (1) f is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.) S FIGURE 4. Audio Interface Timing. SERIAL CONTROL INTERFACE the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by The serial control interface is a 3-wire serial port that IDX[6:0]. operates asynchronously to the serial audio interface. The serial control interface is utilized to program the on-chip Figure 6 shows the functional timing diagram for writing the mode registers. The control interface includes MD (pin 13), serial control port. ML is held at a logic “1” state until a MC (pin 14), and ML (pin 15). MD is the serial data input, register needs to be written. To start the register write cycle, used to program the mode registers, MC is the serial bit ML is set to logic “0”. Sixteen clocks are then provided on clock, used to shift data into the control port, and ML is the MC, corresponding to the 16 bits of the control data word on control port latch clock. MD. After the sixteenth clock cycle has completed, ML is set to logic “1” to latch the data into the indexed mode control register. REGISTER WRITE OPERATION All write operations for the serial control port use 16-bit data CONTROL INTERFACE TIMING REQUIREMENTS words. Figure 5 shows the control data word format. The most significant bit must be a “0”. There are seven bits, See Figure 7 for a detailed timing diagram of the serial labeled IDX[6:0], that set the register index (or address) for control interface. These timing parameters are critical for proper control port operation. MSB LSB 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 Register Index (or Address) Register Data FIGURE 5. Control Data Word Format for MDI. ML MC MD X 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 IDX6 FIGURE 6. Register Write Operation. 10 PCM1741 SBAS175

MODE CONTROL REGISTERS section of this data sheet. Table II lists the available mode User-Programmable Mode Controls control functions, along with their reset default conditions and associated register index. The PCM1741 includes a number of user-programmable Register Map functions that are accessed via control registers. The regis- ters are programmed using the Serial Control Interface that The mode control register map is shown in Table III. Each was previously discussed in the “Serial Control Interface” register includes an index (or address) indicated by the IDX[6:0] bits. t MHH ML 50% of VDD t t tMLS MCH MCL tMLH MC 50% of VDD t MCY LSB MD 50% of V DD t t MDS MCH SYMBOL PARAMETER MIN TYP MAX UNITS t MC Pulse Cycle Time 100 ns MCY t MC Low Level Time 50 ns MCL t MC High Level Time 50 ns MCH t ML High Level Time Note (2) ns MHH t ML Falling Edge to MC Rising Edge 20 ns MLS t ML Hold Time(1) 20 ns MLH t MD Hold Time 15 ns MDH t MD Set Up Time 20 ns MDS 3 NOTES: (1) MC rising edge for LSB to ML rising edge. (2)256•f sec (min), fS = Sampling Rate. S FIGURE 7. Control Interface Timing. FUNCTION RESET DEFAULT CONTROL REGISTER INDEX, IDX[6:0] Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps 0dB, No Attenuation 16 and 17 AT1[7:0], AT2[7:0] Soft Mute Control Mute Disabled 18 MUT[2:0] Oversampling Rate Control (64 or 128f ) 64f Oversampling 18 OVER S S DAC Operation Control DAC1 and DAC2 Enabled 19 DAC[2:1] De-Emphasis Function Control De-Emphasis Disabled 19 DM12 De-Emphasis Sample Rate Selection 44.1kHz 19 DMF[1:0] Audio Data Format Control 24-Bit Left Justified 20 FMT[2:0] Digital Filter Roll-Off Control Sharp Roll-Off 20 FLT Zero Flag Function Select L-/R-Channel Independent 22 AZRO Output Phase Select Normal Phase 22 DREV Zero Flag Polarity Select High 22 ZREV TABLE II. User-Programmable Mode Controls. IDX (B8-B14) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 10 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 H 11 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 H 12 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) OVER RSV(1) RSV(1) RSV(1) RSV(1) MUT2 MUT1 H 13 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) DMF1 DMF0 DM12 RSV(1) RSV(1) DAC2 DAC1 H 14 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) FLT RSV(1) RSV(1) FMT2 FMT1 FMT0 H 15 21 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) H 16 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) AZRO ZREV DREV H NOTE: (1) RSV = Reserved for test operation. It should be set to “0” when in regular operation. TABLE III. Mode Control Register Map. PCM1741 11 SBAS175

REGISTER DEFINITIONS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 Register 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 ATx[7:0] Digital Attenuation Level Setting where x = 1 or 2, corresponding to the DAC output V L (x = 1) and V R (x = 2). OUT OUT Default Value: 1111 1111 B Each DAC channel (V L and V R) includes a digital attenuator function. The attenuation level may be OUT OUT set from 0dB to –63dB, in 0.5dB steps. Changes in attentuator levels are made by incrementing or decrementing, by one step (0.5dB), for every 8/f time interval until the programmed attenuator setting is S reached. Alternatively, the attenuator level may be set to infinite attenuation (or mute). The attenuation data for each channel can be set individually. The attenuation level may be set using the formula below. Attenuation Level (dB) = 0.5 (ATx[7:0] – 255) DEC where: ATx[7:0] = 0 through 255 DEC for: ATx[7:0] = 0 through 128, the attenuator is set to infinite attenuation. DEC The following table shows attenuator levels for various settings. ATx[7:0] Decimal Value Attenuator Level Setting 1111 1111 255 0dB, No Attenuation (default) B 1111 1110 254 –0.5dB B 1111 1101 253 –1.0dB B 1000 0011 131 –62.0dB B 1000 0010 130 –62.5dB B 1000 0001 129 –63.0dB B 1000 0000 128 Mute B • • • • • • • • • 0000 0000 0 Mute B B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV OVER RSV RSV RSV RSV MUT2 MUT1 MUTx Soft Mute Control Where x = 1 or 2, corresponding to the DAC output V L (x = 1) and V R (x = 2). OUT OUT Default Value: 0 MUTx = 0 Mute Disabled (default) MUTx = 1 Mute Enabled The mute bits, MUT1 and MUT2, are used to enable or disable the Soft Mute function for the corresponding DAC outputs, V L and V R. The Soft Mute function is incorporated into the digital attenuators. When OUT OUT Mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When Mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output will be decreased from the current setting to the infinite attenuation setting, one attenuator step (0.5dB) at a time. This provides a “pop”-free muting of the DAC output. By setting MUTx = 0, the attenuator will be increased one step at a time to a previously programmed attenuation level. OVER Oversampling Rate Control Default Value: 0 OVER = 0 64x Oversampling (default) OVER = 1 128x Oversampling The OVER bit is used to control the oversampling rate of the delta-sigma DACs. 12 PCM1741 SBAS175

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DM12 RSV RSV DAC2 DAC1 DACx DAC Operation Control where x = 1 or 2, corresponding to the DAC output V L (x = 1) or V R (x = 2). OUT OUT Default Value: 0 DACx = 0 DAC Operation Enabled (default) DACx = 1 DAC Operation Disabled The DAC operation controls are used to enable and disable the DAC outputs, V L and V R. When OUT OUT DACx = 0, the corresponding output will generate the audio waveform dictated by the data present on the DATA pin. When DACx = 1, the corresponding output will be set to the bipolar zero level, or V /2. CC DM12 Digital De-Emphasis Function Control Default Value: 0 DM12 = 0 De-Emphasis Disabled (default) DM12 = 1 De-Emphasis Enabled The DM12 bit is used to enable or disable the Digital De-Emphasis function. Refer to the Typical Performance Curves of this data sheet for more information. DMF[1:0] Sampling Frequency Selection for the De-Emphasis Function Default Value: 00 DMF[1:0] De-Emphasis Same Rate Selection 00 44.1kHz (default) 01 48kHz 10 32kHz 11 Reserved The DMF[1:0] bits are used to select the sampling frequency used for the Digital De-Emphasis function when it is enabled. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 20 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0 FMT[2:0] Audio Interface Data Format Default Value: 101 The FMT[2:0] bits are used to select the data format for the serial audio interface. The following table shows the available format options. FMT[2:0] Audio Data Format Selection 000 24-Bit Standard Format, Right-Justified Data 001 20-Bit Standard Format, Right-Justified Data 010 18-Bit Standard Format, Right-Justified Data 011 16-Bit Standard Format, Right-Justified Data 100 I2S Format, 16- to 24-bits 101 Left-Justified Format, 16- to 24-Bits (default) 110 Reserved 111 Reserved PCM1741 13 SBAS175

Register 20 (Cont.) FLT Digital Filter Roll-Off Control Default Value: 0 FLT = 0 Sharp Roll-Off (default) FLT = 1 Slow Roll-Off The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Two filter roll-off sections are available: Sharp or Slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 22 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV AZRO ZREV DREV DREV Output Phase Select Default Value: 0 DREV = 0 Normal Output (default) DREV = 1 Inverted Output The DREV bit is used to set the output phase of V L and V R. OUT OUT ZREV Zero Flag Polarity Select Default Value: 0 ZREV = 0 Zero Flag Pins HIGH at a Zero Detect (default) ZREV = 1 Zero Flag Pins LOW at a Zero Detect The ZREV bit allows the user to select the active polarity of Zero Flag pins. AZRO Zero Flag Function Select Default Value: 0 AZRO = 0 L-/R-Channel Independent Zero Flag (default) AZRO = 1 L-/R-Channel Common Zero Flag Register22 (Cont.) The AZRO bit allows the user to select the function of Zero Flag pins. AZRO = 0: Pin11: ZEROR; Zero Flag Output for R-Channel Pin12: ZEROL; Zero Flag Output for L-Channel AZRO = 1: Pin11: ZEROA; Zero Flag Output for L-/R-Channel Pin12: NA; No Assign 14 PCM1741 SBAS175

ANALOG OUTPUTS ANALOG FILTER PERFORMANCE The PCM1741 includes two independent output channels: (100Hz-10MHz) V L and V R. These are unbalanced outputs, each capable OUT OUT 0 of driving 2.05Vp-p typical into a 5kΩ AC-coupled load. The internal output amplifiers for V L and V R are biased to the –10 DC common-mode (or bipolarO zUeTro) voltaOgUe,T equal to VCC/2. e (dB) –20 The output amplifiers include an RC continuous-time filter that ns po –30 helps to reduce the out-of-band noise energy present at the es R DAC outputs, due to the noise shaping characteristics of the –40 PCM1741’s delta-sigma DACs. The frequency response of this –50 filter is shown in Figure 8. By itself, this filter is not enough to –60 attenuate the out-of-band noise to an acceptable level for many 0.1 1 10 100 1K 10K applications, therefore, an external low-pass filter is required to Frequency (kHz) provide sufficient out-of-band noise rejection. Further discus- sion of DAC post-filter circuits is provided in the Applications FIGURE 8. Output Filter Frequency Response. Information section of this data sheet. V OUTPUT nominally biased to a DC voltage level equal to V /2. This COM CC One unbuffered common-mode voltage output pin, V pin may be used to bias external circuits. Figure 9 shows an COM (pin 10), is brought out for decoupling purposes. This pin is example of using the VCOM pin for external biasing applica- tions. R A = –1, where A = – 2 PCM1741 10µF R R2 R C1 VCC V V R1 1 3 2 V x OUT + 1/2 1 Filtered C2 3 OPA2342 Output V COM + 10µF x = L or R (a) Using V to Bias a Single-Supply Filter Stage COM V PCM1741 CC Buffered OPA342 V V COM COM + 10µF (b) Using a Voltage Follower to Buffer V when Biasing Multiple Nodes COM FIGURE 9. Biasing External Circuits Using the V Pin. COM PCM1741 15 SBAS175

ZERO FLAGS POWER SUPPLIES AND GROUNDING Zero Detect Condition The PCM1741 requires a +3.3V analog supply (V ) and a CC +3.3V digital supply (V ). The +3.3V supply (V ) is used to Zero Detection for each output channel is independent from DD CC power the DAC analog and output filter circuitry, while the the other. If the data for a given channel remains at a “0” +3.3V (V ) supply is used to power the digital filter and serial level for 1024 sample periods (or LRCK clock periods), a DD interface circuitry. For best performance, the +3.3V (V ) Zero Detect condition exists for that channel. DD supply should be derived from the +3.3V (V ) supply using a CC Zero Output Flags linear regulator, as shown in Figure 11. Given that a Zero Detect condition exists for one or more Proper power-supply bypassing is shown in Figure 10. The channels, the Zero Flag pins for those channels will be set to 10µF capacitors should be tantalum or aluminum electrolytic, a logic “1” state. There are Zero Flag pins for each channel: while the 0.1µF capacitors are ceramic (X7R type is recom- ZEROL (pin 12) and ZEROR (pin 11). These pins can be used mended for surface-mount applications). to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor, or other digitally controlled functions. R The active polarity of Zero Flag output can be inverted by AV ≈ – R2 setting the ZREV bit of Control Register 22 to “1”. The reset R2 C1 1 default is active high output, or ZREV = 0. R1 R3 2 VIN 1 R4 Tsehleec tLe-dc bhyan sneettli nagn tdh eR A-cZhRaOnn beilt ocfo Cmomnotrno l ZReergoi sFtelra g2 2c taon “ 1b”e. C2 3 OPA2134 VOUT The reset default is L-channel and R-channel independent Zero Flag, or AZRO = 0. FIGURE 10. Dual-Supply Filter Circuit. APPLICATIONS INFORMATION DAC OUTPUT FILTER CIRCUITS CONNECTION DIAGRAMS Delta-sigma DACs utilize noise-shaping techniques to im- A basic connection diagram is shown in Figure 11, with the prove in-band Signal-to-Noise Ratio (SNR) performance at necessary power-supply bypassing and decoupling compo- the expense of generating increased out-of-band noise above nents. Texas Instruments recommends using the component the Nyquist Frequency, or f /2. The out-of-band noise must values shown in Figure 11 for all designs. S be low-pass filtered in order to provide the optimal converter The use of series resistors (22Ω to 100Ω) are recommended performance. This is accomplished by a combination of for the SCK, LRCK, BCK, and DATA inputs. The series on-chip and external low-pass filtering. resistor combines with stray PCB and device input capaci- Figures 9(a) and 10 show the recommended external low- tance to form a low-pass filter that reduces high-frequency pass active filter circuits for single- and dual-supply applica- noise emissions and helps to dampen glitches and ringing tions. These circuits are second-order Butterworth filters present on clock and data lines. 1 BCK SCK 16 System Clock PCM Audio Data 2 DATA ML 15 Input Mode 3 LRCK MC 14 Control + 10µF 4 DGND MD 13 +3.3V 5 VDD ZEROL/NA 12 Zero Mute Regulator 6 VCC ZEROR/ZEROA 11 Control + 10µF 7 VOUTL VCOM 10 +10µF 8 VOUTR AGND 9 +3.3V Post LPF Post LPF L-Chan OUT R-Chan OUT FIGURE 11. Basic Connection Diagram. 16 PCM1741 SBAS175

using a Multiple FeedBack (MFB) circuit arrangement that PCB LAYOUT GUIDELINES reduces sensitivity to passive component variations over frequency and temperature. For more information regarding A typical PCB floor plan for the PCM1741 is shown in MFB active filter design, please refer to Burr-Brown Appli- Figure 12. A ground plane is recommended, with the analog cations Bulletin #34 AB-034 (SBFA001), available from our and digital sections being isolated from one another using a web site at http://www.ti.com. split or cut in the circuit board. The PCM1741 should be oriented with the digital I/O pins facing the ground plane Since the overall system performance is defined by the split/cut to allow for short, direct connections to the digital quality of the DACs and their associated analog output audio interface and control signals originating from the circuitry, high-quality audio op amps are recommended for digital section of the board. the active filters. The OPA2353 and OPA2134 dual op amps from Texas Instruments are recommended for use with the PCM1741, see Figures 9(a) and 10. Digital Power Analog Power +VD DGND AGND+3.3V +VS –VS REG V CC V Digital Logic DD and DGND Output Audio Circuits Processor PCM1741 Digital Ground AGND Analog DIGITAL SECTION ANALOG SECTION Ground Return Path for Digital Signals FIGURE 12. Recommended PCB Layout. PCM1741 17 SBAS175

Separate power supplies are recommended for the digital THEORY OF OPERATION and analog sections of the board. This prevents the switching noise present on the digital supply from contaminating the The delta-sigma section of the PCM1741 is based on an analog power supply and degrading the dynamic perfor- 8-level amplitude quantizer and a fourth-order noise shaper. This mance of the PCM1741. In cases where a common +3.3V section converts the oversampled input data to 8-level delta-sigma supply must be used for the analog and digital sections, an format. A block diagram of the 8-level delta-sigma modulator is inductance (RF choke, ferrite bead) should be placed be- shown in Figure 14. This 8-level delta-sigma modulator has the tween the analog and digital +3.3V supply connections to advantage of stability and clock jitter sensitivity over the typical avoid coupling of the digital switching noise into the analog one-bit (2-level) delta-sigma modulator. The combined circuitry. Figure 13 shows the recommended approach for oversampling rate of the delta-sigma modulator and the interpo- single-supply applications. lation filter is 64fS. Power Supplies RF Choke or Ferrite Bead +3.3V AGND +V –V S S REG V V DD CC V DD DGND Output Circuits PCM1741 AGND Common Ground DIGITAL SECTION ANALOG SECTION FIGURE 13. Single-Supply PCB Layout. – + 8fS + Z–1 + Z–1 + Z–1 + Z–1 + 8-Level Quantizer 64f S FIGURE 14. 8-Level Delta-Sigma Modulator. 18 PCM1741 SBAS175

QUANTIZATION NOISE SPECTRUM QUANTIZATION NOISE SPECTRUM (64x Oversampling) (128x Oversampling) 0 0 –20 –20 –40 –40 B) –60 B) –60 d d de ( –80 de ( –80 u u plit –100 plit –100 m m A –120 A –120 –140 –140 –160 –160 –180 –180 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Frequency (f ) Frequency (f ) S S FIGURE 15. Quantization Noise Spectrum. The theoretical quantization noise performance of the KEY PERFORMANCE PARAMETERS 8-level delta-sigma modulator is shown in Figure 15. The en- AND MEASUREMENT hanced multilevel delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, This section provides information on how to measure key with the simulated jitter sensitivity, as shown in Figure 16. dynamic performance parameters for the PCM1741. In all cases, an Audio Precision System Two Cascade or equivalent audio measurement system is utilized to perform the testing. JITTER DEPENDENCE (64x Oversampling) 125 TOTAL HARMONIC DISTORTION + NOISE 120 Total Harmonic Distortion + Noise (THD+N) is a significant B) 115 figure of merit for audio DACs, since it takes into account e (d both harmonic distortion and all noise sources within a ng 110 specified measurement bandwidth. The true rms value of the a mic R 105 dshisotworst itohne atensdt sneotiuspe fiosr rTefHeDrre+dN tmo eaass uTrHemDe+nNts.. Figure 17 a n Dy 100 For the PCM1741, THD+N is measured with a full-scale, 1kHz digital sine wave as the test stimulus at the input of the 95 DAC. The digital generator is set to a 24-bit audio word 90 length and a sampling frequency of 44.1kHz or 96kHz. The 0 100 200 300 400 500 600 digital generator output is taken from the unbalanced Jitter (ps) S/PDIF connector of the measurement system. The S/PDIF FIGURE 16. Jitter Sensitivity. Evaluation Board DEM-DAI1741 2nd-Order S/PDIF PCM1741 Low-Pass Receiver Filter f = 54kHz or 108kHz –3dB Analyzer 20kHz Digital and Apogee Generator S/PDIF Display Filter Band Limit Notch Filter Output 0dBFS, rms Mode HPF = 22Hz f = 1kHz C 1kHz Sine Wave LPF = 30kHz FIGURE 17. Test Setup for THD+N Measurements. PCM1741 19 SBAS175

data is transmitted via a coaxial cable to the digital audio The measurement setup for the dynamic range measurement receiver on the DEM-DAI1741 demo board. The receiver is is shown in Figure 18, and is similar to the THD+N test then configured to output 24-bit data in either I2S or left- setup discussed previously. The differences include the band justified data format. The DAC audio interface format is limit filter selection, the additional A-Weighting filter, and programmed to match the receiver output format. The ana- the –60dBFS input level. log output is then taken from the DAC post filter and IDLE CHANNEL SIGNAL-TO-NOISE RATIO connected to the analog analyzer input of the measurement The SNR test provides a measure of the noise floor of the system. The analog input is band limited using filters resi- DAC. The input to the DAC is all “0”s data, and the DAC’s dent in the analyzer. The resulting THD+N is measured by Infinite Zero Detect Mute function must be disabled (default the analyzer and displayed by the measurement system. condition at power up for the PCM1741). This ensures that DYNAMIC RANGE the delta-sigma modulator output is connected to the output Dynamic range is specified as A-Weighted, THD+N mea- amplifier circuit so that idle tones (if present) can be ob- sured with a –60dBFS, 1kHz digital sine wave stimulus at served and effect the SNR measurement. The dither function the input of the DAC. This measurement is designed to give of the digital generator must also be disabled to ensure an all a good indicator of how the DAC will perform given a low- “0”s data stream at the input of the DAC. The measurement level input signal. setup for SNR is identical to that used for dynamic range, with the exception of the input signal level (see the notes provided in Figure 18). Evaluation Board DEM-DAI1741 2nd-Order S/PDIF PCM1741(1) Low-Pass Receiver Filter f = 54kHz –3dB Analyzer Digital A-Weight and Generator Filter(1) S/PDIF Display Band Limit Notch Filter Output 0% Full-Scale, rms Mode HPF = 22Hz f = 1kHz C Dither Off (SNR) LPF = 22kHz –60dBFS, Option = A-Weighting(2) 1kHz Sine Wave (Dynamic Range) NOTES: (1) Infinite Zero Detect Mute disabled. (2) Results without A-Weighting will be approxi- mately 3dB worse. FIGURE 18. Test Setup for Dynamic Range and SNR Measurements. 20 PCM1741 SBAS175

PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2008 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty PCM1741E ACTIVE SSOP/ DBQ 16 75 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM QSOP noSb/Br) PCM1741E/2K ACTIVE SSOP/ DBQ 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM QSOP noSb/Br) PCM1741E/2KG4 ACTIVE SSOP/ DBQ 16 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM QSOP noSb/Br) PCM1741EG4 ACTIVE SSOP/ DBQ 16 75 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM QSOP noSb/Br) (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) PCM1741E/2K SSOP/ DBQ 16 2000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 QSOP PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) PCM1741E/2K SSOP/QSOP DBQ 16 2000 346.0 346.0 29.0 PackMaterials-Page2

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