® PCM1733 PCM1733 Stereo Audio TM DIGITAL-TO-ANALOG CONVERTER 18 Bits, 96kHz Sampling FEATURES DESCRIPTION l COMPLETE STEREO DAC: Includes Digital The PCM1733 is a complete low cost stereo audio Filter and Output Amp digital-to-analog converter (DAC), operating off of a l DYNAMIC RANGE: 95dB 256fS or 384fS system clock. The DAC contains a 3rd- order SD modulator, a digital interpolation filter, and l MULTIPLE SAMPLING FREQUENCIES: an analog output amplifier. The PCM1733 accepts 16kHz to 96kHz 18-bit input data in either normal or I2S formats. l 8X OVERSAMPLING DIGITAL FILTER The digital filter performs an 8X interpolation function l SYSTEM CLOCK: 256f /384f and includes de-emphasis at 44.1kHz. The PCM1733 S S l NORMAL OR I2S DATA INPUT FORMATS can accept digital audio sampling frequencies from 16kHz to 96kHz, always at 8X oversampling. l SMALL 14-PIN SOIC PACKAGE The PCM1733 is ideal for low-cost, CD-quality con- sumer audio applications. BCKIN Multi-level(cid:13) Low-pass(cid:13) VOUTL Serial(cid:13) Delta-Sigma(cid:13) DAC Filter LRCIN Input(cid:13) Modulator I/F DIN 8X Oversampling(cid:13) CAP Digital Filter Multi-level(cid:13) V R Delta-Sigma(cid:13) DAC Low-pass(cid:13) OUT Modulator Filter Mode(cid:13) FORMAT Control(cid:13) I/F DM Power Supply 256f /384f S S SCKI V GND CC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1998 Burr-Brown Corporation PDS-11435A PPCrinMted 1in 7U.3S.3A. January, 1998 SBAS088

SPECIFICATIONS All specifications at +25(cid:176)C, +VCC = +5V, fS = 44.1kHz, and 18-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1733 PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 18 Bits DATA FORMAT Audio Data Interface Format Standard/I2S Audio Data Format Two’s Binary Complement Sampling Frequency (fS) 16 96 kHz Internal System Clock Frequency 256fS/384fS DIGITAL INPUT/OUTPUT Logic Level TTL Input Logic Level VIH(1) 2.0 VDC V (1) 0.8 VDC IL Input Logic Current: IIN(1) – 0.8 m A DYNAMIC PERFORMANCE(2) f = 991kHz THD+N at FS (0dB) –83 –78 dB THD+N at –60dB –32 dB Dynamic Range EIAJ, A-weighted 90 95 dB Signal-to-Noise Ratio EIAJ, A-weighted 90 97 dB Channel Separation 88 95 dB DC ACCURACY Gain Error – 1.0 – 5.0 % of FSR Gain Mismatch, Channel-to-Channel – 1.0 – 5.0 % of FSR Bipolar Zero Error VOUT = VCC/2 at BPZ – 20 – 50 mV ANALOG OUTPUT Output Voltage Full Scale (0dB) 0.62 x V Vp-p CC Center Voltage VCC/2 VDC Load Impedance AC Load 10 kW DIGITAL FILTER PERFORMANCE Passband 0.445 fS Stopband 0.555 fS Passband Ripple – 0.17 dB Stopband Attenuation –35 dB Delay Time 11.125/fS sec INTERNAL ANALOG FILTER –3dB Bandwidth 100 kHz Passband Response f = 20kHz –0.16 dB POWER SUPPLY REQUIREMENTS Voltage Range 4.5 5 5.5 VDC Supply Current 13 18 mA Power Dissipation 65 90 mW TEMPERATURE RANGE Operation –25 +85 (cid:176)C Storage –55 +125 (cid:176)C NOTES: (1) Pins 1, 2, 3, 12, 13, 14: LRCIN, DIN, BCKIN, DM, FORMAT, SCKI. (2) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM1733 2

PIN CONFIGURATION PIN ASSIGNMENTS TOP VIEW SOIC PIN NAME I/O FUNCTION 1(1) LRCIN IN Sample Rate Clock Input 2(1) DIN IN Audio Data Input 3(1) BCKIN IN Bit Clock Input for Audio Data. LRCIN(cid:13) 1(cid:13) 14(cid:13) SCKI(cid:13) 4 NC — No Connection DIN(cid:13) 2(cid:13) 13(cid:13) FORMAT(cid:13) 5 CAP — Common Pin of Analog Output Amp BCKIN(cid:13) 3(cid:13) 12(cid:13) DM(cid:13) 6 VOUTR OUT Right-Channel Analog Output 7 GND — Ground NC(cid:13) 4(cid:13) PCM1733 11(cid:13) NC(cid:13) 8 VCC — Power Supply CAP(cid:13) 5(cid:13) 10(cid:13) NC(cid:13) 9 VOUTL OUT Left-Channel Analog Output V R(cid:13) 6(cid:13) 9(cid:13) V L(cid:13) 10 NC — No Connection OUT OUT GND 7 8 V 11 NC — No Connection CC 12(2) DM IN De-emphasis Control HIGH:De-emphasis ON LOW: De-emphasis OFF 13(2) FORMAT IN Audio Data Format Select HIGH: I2S Data Format LOW: Standard Data Format PACKAGE INFORMATION 14 SCKI IN System Clock Input (256fS or 384fS) PACKAGE DRAWING NOTES: (1) Schmitt Trigger input. (2) Schmitt Trigger input with internal PRODUCT PACKAGE NUMBER(1) pull-up. PCM1733U 14 Pin SOIC 235 ELECTROSTATIC NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown ABSOLUTE MAXIMUM RATINGS recommends that all integrated circuits be handled with Power Supply Voltage.......................................................................+6.5V appropriate precautions. Failure to observe proper handling +VCC to +VDD Difference...................................................................– 0.1V and installation procedures can cause damage. Input Logic Voltage..................................................–0.3V to (VDD + 0.3V) Power Dissipation..........................................................................290mW ESD damage can range from subtle performance degradation Operating Temperature Range.........................................–25(cid:176)C to +85(cid:176)C Storage Temperature......................................................–55(cid:176)C to +125(cid:176)C to complete device failure. Precision integrated circuits may Lead Temperature (soldering, 5s)..................................................+260(cid:176)C be more susceptible to damage because very small parametric Thermal Resistance, qJA..............................................................+90(cid:176)C/W changes could cause the device not to meet its published specifications. ® 3 PCM1733

TYPICAL PERFORMANCE CURVES At TA = +25(cid:176)C, +VCC = +5V, fS = 44.1kHz, SYSCLK = 256fS, unless otherwise noted. DYNAMIC PERFORMANCE THD+N vs TEMPERATURE SNR, DYNAMIC RANGE vs TEMPERATURE 0.009(cid:13) 3.2(cid:13) 99(cid:13) 99(cid:13) 0.008(cid:13) 3.1(cid:13) 98(cid:13) SNR 98(cid:13) 0.007(cid:13) 0dB 3.0(cid:13) +N at 0dB (%) 000...000000654(cid:13)(cid:13)(cid:13) –60dB 222...987(cid:13)(cid:13)(cid:13) N at –60dB (%) SNR (dB) 9976(cid:13)(cid:13) 9976(cid:13)(cid:13) mic Range (dB) THD 00..000032(cid:13)(cid:13) 22..65(cid:13)(cid:13) THD+ 95(cid:13) 95(cid:13) Dyna 94(cid:13) 94(cid:13) 0.001(cid:13) 2.4(cid:13) Dynamic Range 0 2.3 93 93 –25 0 25 50 75 85 100 –25 0 25 50 75 85 100 Temperature (°C) Temperature (°C) THD+N vs POWER SUPPLY SNR, DYNAMIC RANGE vs POWER SUPPLY 0.009(cid:13) 3.2(cid:13) 99(cid:13) 99(cid:13) 0.008(cid:13) 3.1(cid:13) 98(cid:13) 98(cid:13) +N at 0dB (%) 0000....000000007654(cid:13)(cid:13)(cid:13)(cid:13) 0dB 3222....0987(cid:13)(cid:13)(cid:13)(cid:13) N at –60dB (%) SNR (dB) 9976(cid:13)(cid:13) SNR 9976(cid:13)(cid:13) mic Range (dB) HD 0.003(cid:13) 2.6(cid:13) D+ 95(cid:13) 95(cid:13) na T 0.002(cid:13) 2.5(cid:13) TH Dy –60dB 94(cid:13) Dynamic Range 94(cid:13) 0.001(cid:13) 2.4(cid:13) 0 2.3 93(cid:13) 93(cid:13) 4.5 4.75 5.0 5.25 5.5 4.5 4.75 5.0 5.25 5.5 VCC (V) (cid:13) VCC (V) (cid:13) THD+N vs SAMPLING RATE SNR, DYNAMIC RANGE vs SAMPLING RATE 0.016(cid:13) 5.2(cid:13) 98(cid:13) 98(cid:13) 97(cid:13) 97(cid:13) SNR 0.014(cid:13) 4.7(cid:13) 96(cid:13) 96(cid:13) +N at 0dB (%) 0.00.1021(cid:13)(cid:13) 0dB 43..27(cid:13)(cid:13) N AT –60dB (%) SNR (dB) 99995432(cid:13)(cid:13)(cid:13)(cid:13) Dynamic Range 99995432(cid:13)(cid:13)(cid:13)(cid:13) mic Range (dB) THD 0.008(cid:13) 3.2(cid:13) HD+ 91(cid:13) 91(cid:13) Dyna T 90(cid:13) 90(cid:13) 0.006(cid:13) 2.7(cid:13) –60dB 89(cid:13) 89(cid:13) 0.004 2.2 88 88 44.1 48 88.2 96 44.1 48 88.2 96 Sampling Rate (kHz) Sampling Rate (kHz) ® PCM1733 4

TYPICAL PERFORMANCE CURVES At TA = +25(cid:176)C, +VCC = +VDD = +5V, fS = 44.1kHz, and 18-bit input data, SYSCLK = 384fS, unless otherwise noted. DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTIC PASSBAND RIPPLE CHARACTERISTIC 0(cid:13) 0(cid:13) –20(cid:13) –0.2(cid:13) –40(cid:13) –0.4(cid:13) dB dB –60(cid:13) –0.6(cid:13) –80(cid:13) –0.8(cid:13) –100 –1 0 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS 0 0.1134fS 0.2268fS 0.3402fS 0.4535fS Frequency (Hz) Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) DE-EMPHASIS FREQUENCY ERROR (44.1kHz) 0(cid:13) 0.6(cid:13) –2(cid:13) 0.4(cid:13) –4(cid:13) 0.2(cid:13) B) B) Level (d –6(cid:13) Error (d 0.0(cid:13) –8(cid:13) –0.2(cid:13) –10(cid:13) –0.4(cid:13) –12 –0.6 0 5 10 15 20 25 0 4999.8375 9999.675 14999.5125 19999.35 Frequency (kHz) Frequency (kHz) ® 5 PCM1733

1/fs L_ch LRCIN (pin 1) R_ch BCKIN (pin 3) AUDIO DATA WORD = 18-BIT DIN (pin 2) 16 17 18 1 2 3 16 17 18 1 2 3 16 17 18 MSB LSB MSB LSB FIGURE 1. “Normal” Data Input Timing. 1/fs L_ch LRCIN (pin 1) R_ch BCKIN (pin 3) AUDIO DATA WORD = 18-BIT DIN (pin 2) 1 2 3 16 17 18 1 2 3 16 17 18 1 2 MSB LSB MSB LSB FIGURE 2. “I2S” Data Input Timing. LRCKIN 1.4V t t t BCH BCL LB BCKIN 1.4V tBCY tBL DIN 1.4V tDS tDH BCKIN Pulse Cycle Time(cid:13) : t : 100ns (min)(cid:13) BCY(cid:13) BCKIN Pulse Width High(cid:13) : t : 50ns (min)(cid:13) BCH(cid:13) BCKIN Pulse Width Low(cid:13) : t : 50ns (min)(cid:13) BCL(cid:13) BCKIN Rising Edge to LRCIN Edge(cid:13) : t : 30ns (min)(cid:13) BL(cid:13) LRCIN Edge to BCKIN Rising Edge(cid:13) : t : 30ns (min)(cid:13) LB(cid:13) DIN Set-up Time(cid:13) : t : 30ns (min)(cid:13) DS(cid:13) DIN Hold Time : t : 30ns (min) DH FIGURE 3. Audio Data Input Timing. SYSTEM CLOCK tSCKIH The system clock for PCM1733 must be either 256fS or 384f , where f is the audio sampling frequency (LRCIN), 2.0V S S SCKI typically 32kHz, 44.1kHz or 48kHz. The system clock is 0.8V used to operate the digital filter and the noise shaper. The t system clock input (SCKI) is at pin 14. Timing conditions SCKIL for SCKI are shown in Figure 4. System Clock Pulse Width High t 13ns (min) SCKIH System Clock Pulse Width Low tSCKIL 13ns (min) FIGURE 4. System Clock Timing Requirements. ® PCM1733 6

PCM1733 has a system clock detection circuit which auto- FORMAT matically detects the frequency, either 256f or 384f . The S S 0 Normal Format (MSB-first, right-justified) system clock should be synchronized with LRCIN (pin 1), 1 I2S Format (Philips serial data protocol) but PCM1733 can compensate for phase differences. If the TABLE II. Input Format Selection. phase difference between LRCIN and system clock is greater than – 6 bit clocks (BCKIN), the synchronization is per- formed automatically. The analog outputs are forced to a RESET bipolar zero state (V /2) during the synchronization func- PCM1733 has an internal power-on reset circuit. The internal CC tion. Table I shows the typical system clock frequency power-on reset initializes (resets) when the supply voltage inputs for the PCM1733. V > 2.2V (typ). The power-on reset has an initialization CC period equal to 1024 system clock periods after V > 2.2V. CC SYSTEM CLOCK During the initialization period, the outputs of the DAC are SAMPLING FREQUENCY (MHz) invalid, and the analog outputs are forced to VCC/2. Figure 6 RATE (LRCIN) 256fS 384fS illustrates the power-on reset and reset-pin reset timing. 32kHz 8.192 12.288 44.1kHz 11.2896 16.9340 DE-EMPHASIS CONTROL 48kHz 12.288 18.432 TABLE I. System Clock Frequencies vs Sampling Rate. Pin 12 (DM) enables PCM1733’s de-emphasis function. De- emphasis operates only at 44.1kHz. TYPICAL CONNECTION DIAGRAM Figure 5 illustrates the typical connection diagram for DM PCM1733 used in a stand-alone application. 0 De-emphasis OFF 1 De-emphasis ON (44.1kHz) TABLE III. De-emphasis Control Selection. INPUT DATA FORMAT PCM1733 can accept input data in either normal (MSB-first, right-justified) or I2S formats. When pin 13 (FORMAT) is LOW, normal data format is selected; a HIGH on pin 13 selects I2S format. +5V Analog 7 8 GND V 2(cid:13) CC 9(cid:13) Post(cid:13) PCM(cid:13) 3(cid:13) DBCINK(cid:13)IN(cid:13) VOCUATPL 5(cid:13) + LPF Lch Analog Out Audio Data(cid:13) 1 (cid:13) 10µF Processor LRCIN PCM1733 VOUTR 6 PLPosFt(cid:13) Rch Analog Out 14 13(cid:13) SCKI FORMAT(cid:13) 256f/384f CLK 12 Mode Control S S DM FIGURE 5. Typical Connection Diagram. 2.6V VCC 2.2V 1.8V Reset Reset Removal Internal Reset 1024 system (= SCKI) clocks SCKI Clock FIGURE 6. Internal Power-On Reset Timing. ® 7 PCM1733

APPLICATION CONSIDERATIONS INTERNAL ANALOG FILTER FREQUENCY RESPONSE(cid:13) (20Hz~24kHz, Expanded Scale) DELAY TIME 1.0 There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a 0.5 delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling dB 0 rate. The following equation expresses the delay time of PCM1733: T = 11.125 x 1/f –0.5 D S For f = 44.1kHz, T = 11.125/44.1kHz = 251.4m s S D Applications using data from a disc or tape source, such as –1.0 20 100 1k 10k 24k CD audio, CD-Interactive, Video CD, DAT, Minidisc, Frequency (Hz) etc., generally are not affected by delay time. For some professional applications such as broadcast audio for stu- dios, it is important for total delay time to be less than 2ms. FIGURE 7. Low Pass Filter Frequency Response. OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1733 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure INTERNAL ANALOG FILTER FREQUENCY RESPONSE(cid:13) (10Hz~10MHz) to use such a filter will result in higher THD+N and lower 10 SNR and Dynamic Range readings than are found in the 5 specifications. The low pass filter removes out of band 0 –5 noise. Although it is not audible, it may affect dynamic –10 specification numbers. –15 B –20 The performance of the internal low pass filter from DC to d –25 24kHz is shown in Figure 7. The higher frequency rolloff of –30 the filter is shown in Figure 8. If the user’s application has –35 –40 the PCM1733 driving a wideband amplifier, it is recom- –45 mended to use an external low pass filter. A simple 3rd- –50 order filter is shown in Figure 9. For some applications, a –55 –60 passive RC filter or 2nd-order filter may be adequate. 10 100 1k 10k 100k 1M 10M Frequency (Hz) BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible FIGURE 8. Low Pass Filter Wideband Frequency Response. to the unit. It is also recommended to include a 0.1m F ceramic capacitor in parallel with the 10m F tantalum bypass capacitor. GAIN vs FREQUENCY 6(cid:9)(cid:13) 90(cid:13) Gain –14(cid:13) 0(cid:13) + 10kW 10kW 151000kWpF OPA134 Gain (dB) ––3544(cid:13)(cid:13) ––9108(cid:13)0(cid:13) Phase (°) VSIN 680pF 100pF Phase – –74(cid:13) –270(cid:13) –94 –360 100 1k 10k 100k 1M Frequency (Hz) FIGURE 9. 3rd-Order LPF. ® PCM1733 8

+ + + + + + In Z–1 Z–1 Z–1 8fS(cid:13) – – 18-Bit + + + 5-level Quantizer 4(cid:13) 3(cid:13) Out 2(cid:13) 48f (384f )(cid:13) S S 1(cid:13) 64f (256f ) S S 0 FIGURE 10. 5-Level DS Modulator Block Diagram. THEORY OF OPERATION The delta-sigma section of PCM1733 is based on a 5-level 5-LEVEL DELTA SIGMA MODULATOR amplitude quantizer and a 3rd-order noise shaper. This 20(cid:13) section converts the oversampled input data to 5-level delta- 0(cid:13) sigma format. A block diagram of the 5-level delta-sigma –20(cid:13) modulator is shown in Figure 10. This 5-level delta-sigma –40(cid:13) modulator has the advantage of stability and clock jitter over B) d –60(cid:13) tThhee t ycopmicabli noende -obviet r(s2a-mlepvleinl)g d realttea -osifg tmhea dmeoltdau-slaigtomr.a modu- Gain (– –80(cid:13) –100(cid:13) lator and the internal 8X interpolation filter is 96f for a S 384f system clock, and 64f for a 256f system clock. The –120(cid:13) S S S theoretical quantization noise performance of the 5-level –140(cid:13) delta-sigma modulator is shown in Figure 11. –160 0 5 10 15 20 25 Frequency (kHz) FIGURE 11. Quantization Noise Spectrum. ® 9 PCM1733

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) PCM1733U ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM PCM1733U & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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