PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 24-Bit, 192-kHz Sampling, Enhanced Multilevel, Delta-Sigma, Audio Digital-to-Analog Converter FEATURES APPLICATIONS 1 • 24-BitResolution • IntegratedA/VReceivers 2345 • AnalogPerformance: • DVDMovieandAudioPlayers – DynamicRange:105dBTypical • HDTVReceivers • CarAudioSystems – SNR:105dBTypical • DVDAdd-OnCardsforHigh-EndPCs – THD+N:0.002%Typical • DigitalAudioWorkstations – Full-ScaleOutput:3.9V Typical PP • OtherMultichannelAudioSystems • 4x/8xOversamplingInterpolationFilter: – Stop-BandAttenuation:–50dB DESCRIPTION – PassbandRipple:±0.04dB The PCM1680 is a CMOS, monolithic integrated • SamplingFrequency:5kHzto200kHz circuit which features eight 24-bit audio • SystemClock:128f ,192f ,256f ,384f ,512 digital-to-analog converters (DACs) and support S S S S f ,768f ,or1152f withAutodetect circuitry in a small SSOP-28. The DACs use TI's S S S enhanced multilevel delta-sigma (ΔΣ) architecture to • ZeroFlagsforSelectableChannel achieve excellent signal-to-noise performance and a Combinations hightolerancetoclockjitter. • SerialPort(SPI™/I2C™)forModeControl The PCM1680 accepts industry-standard audio data • User-ProgrammableFunctions: formats with 16-bit to 24-bit audio data. Sampling – FlexibleAudioDataFormats rates up to 200 kHz are supported. The PCM1680 – Right-Justified,I2S™,andLeft-Justified provides a full set of user-programmable functions through a serial control port, using an SPI or I2C – 16-,18-,20-,and24-BitAudioData interface. – DigitalAttenuation:ModeSelectable – 0dBto–63dB,0.5-dB/step – 0dBto–100dB,1-dB/step – SoftMute – DigitalDe-Emphasis – DigitalFilterRoll-Off:SharporSlow • SinglePower-SupplyOperation:5-VAnalog, 5-VDigital • Package:SSOP-28(150mil) • Pin-CompatiblewithPCM1780 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SystemTwo,AudioPrecisionaretrademarksofAudioPrecision,Inc. 2 SPIisatrademarkofMotorola. 3 I2C,I2SaretrademarksofNXPSemiconductors. 4 Allothertrademarksarethepropertyoftheirrespectiveowners. 5 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2005–2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com ThisintegratedcircuitcanbedamagedbyESD.TexasInstrumentsrecommendsthatallintegratedcircuitsbehandledwith appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.ESDdamagecan rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemoresusceptibleto damagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ABSOLUTE MAXIMUM RATINGS(1) Overoperatingfree-airtemperaturerange,unlessotherwisenoted. PCM1680 UNIT Supplyvoltage:V 1,V 2,V –0.3to6.5 V CC CC DD Supplyvoltagedifferences:V 1,V 2,V ±0.1 V CC CC DD Groundvoltagedifferences:AGND1,AGND2,DGND ±0.1 V Inputvoltagetodigitalpins –0.3toV +0.3,<6.5 V DD Inputvoltagetoanalogpins –0.3toV +0.3,<6.5 V CC Inputcurrent(allpinsexceptsupplies) ±10 mA Operatingtemperature –40to+110 °C Storagetemperature –55to+150 °C Junctiontemperature +150 °C Leadtemperature(soldering,5seconds) +260 °C Packagetemperature(IRreflow,peak) +260 °C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. RECOMMENDED OPERATING CONDITIONS Overoperatingfree-airtemperaturerange. MIN NOM MAX UNIT Analogsupplyvoltage,V 1,V 2 4.75 5 5.25 V CC CC Digitalsupplyvoltage,V 4.75 5 5.25 V DD Digitalinputlogicfamily TTL Systemclock 8.192 36.864 MHz Digitalinputclockfrequency Samplingclock 32 192 kHz Analogoutputloadresistance 5 kΩ Analogoutputloadcapacitance 50 pF Digitaloutputloadcapacitance 20 pF Operatingfree-airtemperature,T –25 +70 °C A ELECTRICAL CHARACTERISTICS AllspecificationsatT =+25°C,V =V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted. A CC DD S S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT RESOLUTION 24 Bits DATAFORMAT Audiodatainterfaceformat Right-justified,I2S,left-justified Audiodatabitlength 16-,18-,20-,or24-bits,selectable Audiodataformat MSB-first,twoscomplement f Samplingfrequency 5 200 kHz S 128,192,256,384, Systemclockfrequency 512,768,1152f S 2 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatT =+25°C,V =V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted. A CC DD S S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DIGITALINPUT/OUTPUT Logicfamily TTL-compatible V 2 IH Inputlogiclevel V DC V 0.8 IL I (1) V =V 10 IH IN CC I (1) V =0V –10 IL Inputlogiccurrent IN m A I (2) V =V 65 100 IH IN CC I (2) V =0V –10 IL IN V (3) I =–1mA 2.4 OH OH Outputlogiclevel V V (4) I =1mA 0.4 DC OL OL DYNAMICPERFORMANCE(5) V =0dB,f =48kHz 0.002 0.008 OUT S V =0dB,f =96kHz,system OUT S 0.003 THD+N Totalharmonicdistortion+noise clock=256f % S V =0dB,f =192kHz,system OUT S 0.004 clock=128f S EIAJ,A-weighted,f =48kHz 100 105 S A-weighted,f =96kHz,system S 103 Dynamicrange clock=256f dB S A-weighted,f =192kHz,system S 102 clock=128f S EIAJ,A-weighted,f =48kHz 100 105 S A-weighted,f =96kHz,system S 103 SNR Signal-to-noiseratio clock=256f dB S A-weighted,f =192kHz,system S 102 clock=128f S f =48kHz 94 103 S Channelseparation f =96kHz,systemclock=256f 101 dB S S f =192kHz,systemclock=128f 100 S S DCACCURACY Gainerror ±1 ±6 %ofFSR Gainmismatch,channel-to-channel ±1 ±6 %ofFSR Bipolarzeroerror V =0.486V atBPZinput ±30 ±80 mV OUT CC ANALOGOUTPUT Outputvoltage Full-scale(–0dB) 0.78V V CC PP Bipolarzerovoltage 0.486V V CC DC Loadimpedance AC-coupledload 5 kΩ DIGITALFILTERPERFORMANCE FilterCharacteristics(SharpRoll-Off) Passband ±0.04dB 0.454 f S Stopband 0.546 f S Passbandripple ±0.04 dB Stop-bandattenuation Stopband=0.546f –50 dB S (1) Pins5,6,7,8,11,12,13:SCK,DATA1,BCK,LRCK,DATA2,DATA3,DATA4. (2) Pins2,3,4,14:MS/ADR,MC/SCL,MD/SDA,MSEL. (3) Pins1,28:ZERO1,ZERO2. (4) Pins1,4,28:ZERO1,MD/SDA,ZERO2. (5) AnalogperformancecharacteristicsaremeasuredusingtheSystemTwo™CascadeaudiomeasurementsystembyAudioPrecision™. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatT =+25°C,V =V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted. A CC DD S S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DIGITALFILTERPERFORMANCE(continued) FilterCharacteristics(SlowRoll-Off) Passband ±0.5dB 0.198 f S Stopband 0.884 f S Passbandripple ±0.5 dB Stop-bandattenuation Stopband=0.884f –35 dB S Delaytime 20/f S De-emphasiserror ±0.1 dB ANALOGFILTERPERFORMANCE at20kHz –0.02 Frequencyresponse dB at44kHz –0.07 POWER-SUPPLYREQUIREMENTS V 4.75 5 5.25 DD Voltagerange V DC V 4.75 5 5.25 CC f =48kHz 91 110 S I +I Supplycurrent f =96kHz,systemclock=256f 102 mA DD CC S S f =192kHz,systemclock=128f 106 S S f =48kHz 455 605 S Powerdissipation f =96kHz,systemclock=256f 510 mW S S f =192kHz,systemclock=128f 530 S S TEMPERATURERANGE Operatingtemperature –25 +70 °C q Thermalresistance 70 °C/W JA DBQPACKAGE SSOP-28,QSOP-28 (TOPVIEW) ZERO1 1 28 ZERO2 MS/ADR 2 27 V 1 OUT MC/SCL 3 26 V 2 OUT MD/SDA 4 25 V COM SCK 5 24 AGND2 DATA1 6 23 V 2 CC BCK 7 22 V 3 OUT LRCK 8 21 V 4 OUT V 9 20 V 5 DD OUT DGND 10 19 V 6 OUT DATA2 11 18 AGND1 DATA3 12 17 V 1 CC DATA4 13 16 V 7 OUT MSEL 14 15 V 8 OUT 4 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 TERMINALFUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AGND1 18 – Analogground AGND2 24 – Analogground BCK 7 I Shiftclockinputforserialaudiodata(1) DATA1 6 I SerialaudiodatainputforV 1andV 2(1) OUT OUT DATA2 11 I SerialaudiodatainputforV 3andV 4(1) OUT OUT DATA3 12 I SerialaudiodatainputforV 5andV 6(1) OUT OUT DATA4 13 I SerialaudiodatainputforV 7andV 8(1) OUT OUT DGND 10 – Digitalground LRCK 8 I Leftandrightclockinput.Thefrequencyofthisclockisequaltothesamplingrate,f .(1) S MC/SCL 3 I ShiftclockinputforSPI,serialclockinputforI2C(1)(2) MD/SDA 4 I/O SerialdatainputforSPI,serialdatainput/outputforI2C(1)(2)(3) MS/ADR 2 I SelectinputforSPI,addressinputforI2C(1)(4) MSEL 14 I I2C/SPIselect(1)(4) SCK 5 I Systemclockinput.Inputfrequencyis128,192,256,384,512,768,or1152f .(1) S V 1 17 – Analogpowersupply,5V CC V 2 23 – Analogpowersupply,5V CC V 25 – Commonvoltageoutput.Thispinshouldbebypassedwitha10-m FcapacitortoAGND. COM V 9 – Digitalpowersupply,5V DD V 1 27 O VoltageoutputforaudiosignalcorrespondingtoL-chonDATA1 OUT V 2 26 O VoltageoutputforaudiosignalcorrespondingtoR-chonDATA1 OUT V 3 22 O VoltageoutputforaudiosignalcorrespondingtoL-chonDATA2 OUT V 4 21 O VoltageoutputforaudiosignalcorrespondingtoR-chonDATA2 OUT V 5 20 O VoltageoutputforaudiosignalcorrespondingtoL-chonDATA3 OUT V 6 19 O VoltageoutputforaudiosignalcorrespondingtoR-chonDATA3 OUT V 7 16 O VoltageoutputforaudiosignalcorrespondingtoL-chonDATA4 OUT V 8 15 O VoltageoutputforaudiosignalcorrespondingtoR-chonDATA4 OUT ZERO1 1 O Zero-flagoutput1 ZERO2 28 O Zero-flagoutput2 (1) Schmitt-triggerinput. (2) Pull-downinSPImode. (3) Open-drainoutputinI2Cmode. (4) Pull-down. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com FunctionalBlockDiagram Output Amp and VOUT1 DAC BCK Low-Pass Filter LRCK Output Amp and VOUT2 DAC Serial Low-Pass Filter DATA1 (1, 2) Input DATA2 (3, 4) I/F DAC Output Amp and VOUT3 Low-Pass Filter DATA3 (5, 6) DATA4 (7, 8) 8(cid:1) Output Amp and VCOM ODviegristaalm Fpilltienrg EMnuhltainlecveedl DAC Low-Pass Filter VOUT4 With Delta-Sigma Function Modulator DAC Output Amp and Controller Low-Pass Filter VOUT5 MS/ADR Output Amp and MC/SCL DAC Low-Pass Filter VOUT6 MD/SDA Function Control Output Amp and I/F DAC Low-Pass Filter VOUT7 MSEL Output Amp and DAC Low-Pass Filter VOUT8 System Clock System Clock SCK Zero Detect Power Supply Manager 1 2 D D 1 1 2 2 ERO ERO VD DGN VCC GND VCC GND Z Z A A B0033-01 6 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 TYPICAL CHARACTERISTICS: DIGITAL FILTER (DE-EMPHASIS OFF) AllspecificationsatT =+25°C,V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted. A CC S S FREQUENCYRESPONSE PASSBANDFREQUENCYRESPONSE (SHARPROLL-OFF) (SHARPROLL-OFF) 0 0.05 0.04 −20 0.03 −40 0.02 B B d d 0.01 – −60 – e e d d 0.00 u u mplit −80 mplit −0.01 A A −100 −0.02 −0.03 −120 −0.04 −140 −0.05 0 1 2 3 4 0.0 0.1 0.2 0.3 0.4 0.5 Frequency [× fS] Frequency [× fS] G001 G002 Figure1. Figure2. FREQUENCYRESPONSE TRANSITIONCHARACTERISTICS (SLOWROLL-OFF) (SLOWROLL-OFF) 0 5 4 −20 3 −40 2 B B d d 1 – −60 – e e d d 0 u u mplit −80 mplit −1 A A −100 −2 −3 −120 −4 −140 −5 0 1 2 3 4 0.0 0.1 0.2 0.3 0.4 0.5 Frequency [× fS] Frequency [× fS] G003 G004 Figure3. Figure4. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS: DE-EMPHASIS FILTER AllspecificationsatT =+25°C,V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted. A CC S S DE-EMPHASIS DE-EMPHASISERROR 0 0.5 fS = 32 kHz fS = 32 kHz −1 0.4 −2 0.3 dB −3 dB 0.2 – – el −4 or 0.1 v r Le Er s −5 s 0.0 si si a a ph −6 ph −0.1 m m E E e- −7 e- −0.2 D D −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 f – Frequency – kHz f – Frequency – kHz G005 G006 Figure5. Figure6. DE-EMPHASIS DE-EMPHASISERROR 0 0.5 fS = 44.1 kHz fS = 44.1 kHz −1 0.4 −2 0.3 dB −3 dB 0.2 – – el −4 or 0.1 v r Le Er s −5 s 0.0 si si a a ph −6 ph −0.1 m m E E e- −7 e- −0.2 D D −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 f – Frequency – kHz f – Frequency – kHz G007 G008 Figure7. Figure8. 8 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 TYPICAL CHARACTERISTICS: DE-EMPHASIS FILTER (continued) AllspecificationsatT =+25°C,V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted. A CC S S DE-EMPHASIS DE-EMPHASISERROR 0 0.5 fS = 48 kHz fS = 48 kHz −1 0.4 −2 0.3 dB −3 dB 0.2 – – el −4 or 0.1 v r Le Er s −5 s 0.0 si si a a ph −6 ph −0.1 m m E E e- −7 e- −0.2 D D −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 f – Frequency – kHz f – Frequency – kHz G009 G010 Figure9. Figure10. TYPICAL CHARACTERISTICS: ANALOG FILTER AllspecificationsatT =25C,V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted A CC S S ANALOGFILTERPERFORMANCE 10 0 −10 B −20 d − e d −30 u plit m −40 A −50 −60 −70 1 10 100 1k 10k f − Frequency − kHz G011 Figure11. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE AllspecificationsatT =25C,V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted A CC S S Supply Voltage Characteristics TOTALHARMONICDISTORTION+NOISE DYNAMICRANGE vs vs SUPPLYVOLTAGE SUPPLYVOLTAGE 0.01 110 % − e 108 s oi N + n 106 o B orti – d Dist nge 104 monic mic Ra 102 Har yna al D 100 ot T − N 98 + D H T 0.001 96 4.75 5.00 5.25 4.75 5.00 5.25 VCC − Supply Voltage − V VCC – Supply Voltage – V G012 G013 Figure12. Figure13. SIGNAL-TO-NOISERATIO CHANNELSEPARATION vs vs SUPPLYVOLTAGE SUPPLYVOLTAGE 110 110 108 108 B d atio − 106 – dB 106 R n oise 104 ratio 104 N a o- ep Signal-t 102 annel S 102 R – 100 Ch 100 N S 98 98 96 96 4.75 5.00 5.25 4.75 5.00 5.25 VCC – Supply Voltage – V VCC – Supply Voltage – V G014 G015 Figure14. Figure15. 10 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE (continued) AllspecificationsatT =25C,V =5V,f =48kHz,systemclock=512f ,and24-bitdata,unlessotherwisenoted A CC S S Temperature Characteristics TOTALHARMONICDISTORTION+NOISE DYNAMICRANGE vs vs TEMPERATURE TEMPERATURE 0.01 110 % − e 108 s oi N + n 106 o B orti – d Dist nge 104 monic mic Ra 102 Har yna al D 100 ot T − N 98 + D H T 0.001 96 −25 0 25 50 75 −25 0 25 50 75 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C G016 G017 Figure16. Figure17. SIGNAL-TO-NOISERATIO CHANNELSEPARATION vs vs TEMPERATURE TEMPERATURE 110 110 108 108 B d atio − 106 – dB 106 R n oise 104 ratio 104 N a o- ep Signal-t 102 annel S 102 R – 100 Ch 100 N S 98 98 96 96 −25 0 25 50 75 −25 0 25 50 75 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C G018 G019 Figure18. Figure19. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com SYSTEM CLOCK INPUT The PCM1680 requires a system clock for operating the digital interpolation filters and multilevel ΔΣ modulators. The system clock is applied at the SCK (pin 5) input. Table 1 shows examples of system clock frequencies for commonaudiosamplingrates. Figure 20 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. Texas Instruments’ PLL170x multi-clock generator is an excellentchoiceforprovidingthePCM1680systemclocksource. Table1.SystemClockFrequenciesforCommonAudioSamplingFrequencies SAMPLING SYSTEMCLOCKFREQUENCY(f ),MHz SCK FREQUENCY 128f 192f 256f 384f 512f 768f 1152f S S S S S S S 8kHz 1.024 1.536 2.048 3.072 4.096 6.144 9.216 16kHz 2.048 3.072 4.096 6.144 8.192 12.288 18.432 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 36.864 44.1kHz 5.6448 8.4672 11.2896 16.9344 22.5792 33.8688 —(1) 48kHz 6.144 9.216 12.288 18.432 24.576 36.864 —(1) 88.2kHz 11.2896 16.9344 22.5792 33.8688 —(1) —(1) —(1) 96kHz 12.288 18.432 24.576 36.864 —(1) —(1) —(1) 192kHz 24.576 36.864 —(1) —(1) —(1) —(1) —(1) (1) Thissystemclockfrequencyisnotsupportedforthegivensamplingfrequency. tw(SCKH) H 2 V System Clock 0.8 V L System Clock tw(SCKL) Pulse Cycle Time(1) T0005A08 (1) 1/128f ,1/192f ,1/256f ,1/384f ,1/512f ,1/768f ,or1/1152f . S S S S S S S PARAMETER MIN MAX UNIT t Systemclockpulseduration,HIGH 7 ns w(SCKH) t Systemclockpulseduration,LOW 7 ns w(SCKL) Figure20.SystemClockTiming 12 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 POWER-ON-RESET FUNCTION The PCM1680 includes a power-on-reset function. Figure 21 shows the operation of this function. With the system clock active and V > 3 V (typical, 2.2 V to 3.7 V), the power-on-reset function is enabled. The CC initialization sequence requires 3072 system clocks from the time V > 3 V (typical, 2.2 V to 3.7 V). After the CC initialization period, the PCM1680 is set to its reset default state, as described in the Mode Control Registers sectionofthisdatasheet. During the reset period (3072 system clocks), the analog output is forced to the common voltage (V ), or COM V /2. After the reset period, the internal registers are initialized in the next 1/f period and if SCK, BCK, and CC S LRCK are provided continuously, the PCM1680 provides the proper analog output with group delay correspondingtotheinputdata. 3.7 V VCC 3 V 2.2 V 0 V Reset Reset Release Internal Reset Don’t Care 3072 System Clocks System Clock T0014-06 Figure21.Power-On-ResetTiming AUDIO SERIAL INTERFACE TheaudioserialinterfaceforthePCM1680consistsofa 6-wire synchronous serial port. It includes LRCK (pin 8), BCK (pin 7), and DATA1 (pin 6), DATA2 (pin 11), DATA3 (pin 12), and DATA4 (pin 13). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA1, DATA2, DATA3, and DATA4 into the audio interface serial shift register. Serial data are clocked into the PCM1680 on the rising edge of BCK. LRCK is the serialaudioleft/rightwordclock.Itisusedtolatchserialdataintotheserialaudiointerfaceinternalregisters. Both LRCK and BCK must be synchronous with the system clock. Ideally, it is recommended that LRCK and BCK are derived from the system clock input, SCK. LRCK is operated at the sampling frequency, f . BCK can be S operatedat32,48,or64timesthesamplingfrequency. Internal operation of the PCM1680 is synchronized with LRCK. Accordingly, internal operation is suspended when the sampling rate clock, LRCK, is changed or when SCK and/or BCK is interrupted at least for a 3-bit clock cycle. If SCK, BCK, and LRCK are provided continuously after this suspended condition, the internal operation is resynchronizedautomaticallywithinthefollowing3/f period.Externalresettingisnotrequired. S Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com AUDIO DATA FORMATS AND TIMING The PCM1680 supports industry-standard audio data formats, including right-justified, I2S, and left-justified. The dataformatsareshowninFigure22.Dataformatsareselectedusingtheformatbits,FMT[2:0], located in control register 9 of the PCM1680. The default data format is 24-bit left-justified. All formats require binary twos complement,MSB-firstaudiodata.Figure22showsadetailedtimingdiagramfortheserialaudiointerface. DATA1, DATA2, DATA3, and DATA4 each carry two audio channels, designated as the left and right channels. The left-channel data always precedes the right-channel data in the serial data stream for all data formats. Table2showsthemappingofthedigitalinputdatatotheanalogoutputpins. Table2.AudioInputDatatoAnalogOutputMapping DATAINPUT CHANNEL ANALOGOUTPUT Left V 1 OUT DATA1 Right V 2 OUT Left V 3 OUT DATA2 Right V 4 OUT Left V 5 OUT DATA3 Right V 6 OUT Left V 7 OUT DATA4 Right V 8 OUT 14 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 (1) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) 16-Bit Right-Justified, BCK = 32 fS DATA 14 15 16 1 2 3 14 15 16 1 2 3 14 15 16 MSB LSB MSB LSB 16-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 14 15 16 1 2 3 14 15 16 1 2 3 14 15 16 MSB LSB MSB LSB 18-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 16 17 18 1 2 3 16 17 18 1 2 3 16 17 18 MSB LSB MSB LSB 20-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 18 19 20 1 2 3 18 19 20 1 2 3 18 19 20 MSB LSB MSB LSB 24-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 22 23 24 1 2 3 22 23 24 1 2 3 22 23 24 MSB LSB MSB LSB (2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 N–2 N–1 N 1 2 3 N–2 N–1 N 1 2 MSB LSB MSB LSB (3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS, or 64 fS) DATA 1 2 3 N–2 N–1 N 1 2 3 N–2 N–1 N 1 2 MSB LSB MSB LSB T0009-02 Figure22.AudioDataInputFormats Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com LRCK 1.4 V t(BCH) t(BCL) t(LS) BCK 1.4 V t(BCY) t(LH) DATA1, DATA2, 1.4 V DATA3, DATA4 t(DS) t(DH) T0010-04 PARAMETER MIN UNIT t BCKpulsecycletime 1/(32f ),1/(48f ),1/(64f )(1) (BCY) S S S t BCKpulseduration,HIGH 35 ns (BCH) t BCKpulseduration,LOW 35 ns (BCL) t LRCKsetuptimetoBCKrisingedge 10 ns (LS) t LRCKholdtimetoBCKrisingedge 10 ns (LH) t DATA1,DATA2,DATA3,DATA4setuptime 10 ns (DS) t DATA1,DATA2,DATA3,DATA4holdtime 10 ns (DH) (1) f isthesamplingfrequency. S Figure23.AudioInterfaceTiming OVERSAMPLING RATE CONTROL The PCM1680 automatically controls the oversampling rate of the delta-sigma DACs using the system clock frequency. The oversampling rate is set to 64x oversampling with an 1152-f , 768-f , or 512-f system clock; 32x S S S oversamplingwitha384-f or256-f systemclock;and16xoversamplingwitha192-f or128-f systemclock. S S S S ZERO FLAG The PCM1680 has two zero-flag pins, ZERO1 (pin 1) and ZERO2 (pin 28), which are assigned to the combinations A through D as shown in Table 3. Zero-flag combinations are selected using the zero-flag combination bits, AZRO[1:0], located in control register 13 of the PCM1680. If the input data of the L-channel and/or R-channel of all assigned channels remain at a logic-0 level for 1024 sampling periods (LRCK clock periods), ZERO1 and ZERO2 are set to a logic-1 state, or high level. If the input data of any of the assigned channelscontainalogic-1,ZERO1,andZERO2aresettoalogic-0stateimmediately. The active polarity of the zero-flag output can be inverted by setting the ZREV bit of control register 10 to 1. The resetdefaultisactive-highoutputorZREV=0. Table3.Zero-FlagOutputCombinations ZERO-FLAGCOMBINATION ZERO1(PIN1) ZERO2(PIN28) A DATA1L-ch DATA1R-ch B N/A DATA[1:4] C DATA4 DATA[1:3] D DATA1 DATA[2:4] 16 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 MODE CONTROL The PCM1680 has many programmable functions which can be controlled in the software control mode. The functions are controlled by programming and reading the internal registers using the SPI or I2C interface. These two interfaces for mode control can be selected by MSEL (pin 14). The functions of pins 2, 3, and 4 are changed byMSELselectionasshowninTable4. Table4.InterfaceModeControl PINFUNCTION MSEL INTERFACEMODE PIN2 PIN3 PIN4 LOW SPI MS MC MD HIGH I2C ADR SCL SCA SPICONTROLINTERFACE The SPI control interface of the PCM1680 is a 3-wire synchronous serial port that operates asynchronously to the serial audio interface. The SPI control interface is used to program the on-chip mode registers. The control interface includes MD (pin 4), MC (pin 3), and MS (pin 2). MD is the serial data input, used to program the mode registers. MC is the control port for the serial bit clock, used to shift in the serial data, and MS is the control port formodecontrolselect,whichisusedtoenablethemodecontrol. REGISTERWRITEOPERATION All write operations for the serial control port use 16-bit data words. Figure 24 shows the control data word format. The most significant bit is a fixed '0' for the write operation. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to theregisterspecifiedbyIDX[6:0]. Figure 25 shows the functional timing diagram for writing to the serial control port. MS is held at a logic-1 state until a register must be written. To start the register write cycle, MS is set to logic-0. 16 clock cycles are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the completion of the 16th clockcycle,MSissettologic-1tolatchthedataintotheindexedmodecontrolregister. MSB LSB 000 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 Register Index (or Address) Register Data R0001-01 Figure24.ControlDataWordFormatforMD MS MC MD X 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 IDX6 T0048-01 Figure25.WriteOperationTiming Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com INTERFACETIMINGREQUIREMENTS Figure 26 shows a detailed timing diagram for the serial control interface. Special attention to the setup and hold times is required. Also, t and t , which define minimum delays between edges of the MS and MC clocks, (MSS) (MSH) requirespecialattention.Thesetimingparametersarecriticalforpropercontrolportoperation. t(MHH) MS t(MSS) t(MCL) t(MCH) t(MSH) MC t(MCY) LSB MD t(MDS) t(MDH) T0013-03 PARAMETER MIN UNIT t MCpulsecycletime 100 ns (MCY) t MCpulseduration,LOW 50 ns (MCL) t MCpulseduration,HIGH 50 ns (MCH) t MSpulseduration,HIGH (1) (MHH) t MSfallingedgetoMCrisingedge 20 ns (MSS) t MSholdtime,MCrisingedgeforLSBtoMSrisingedge 20 ns (MSH) t MDholdtime 15 ns (MDH) t MDsetuptime 20 ns (MDS) (1) 3/(256f ),f :samplingrate S S Figure26.InterfaceTiming I2C INTERFACE The PCM1680 supports the I2C serial bus and data transmission protocol for standard mode as a slave device. ThisprotocolisexplainedintheI2Cspecification2.0.The PCM1680 does not support a board-to-board interface. Figure27showstheI2Cframeworkforbasicreadandwriteoperations. SLAVEADDRESS MSB LSB 1 0 0 1 1 0 ADR R/W The PCM1680 has seven bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to 100110. The next bit of the address byte is the device select bit, which can be user-defined using the ADR terminal. A maximum of two PCM1680s can be connected on the same bus at one time. Each PCM1680 respondswhenitreceivesitsownslaveaddress. 18 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 PACKETPROTOCOL A master device must control packet protocol, which consists of a start condition, slave address, read/write bit, data if writing or acknowledge if reading, and a stop condition. The PCM1680 supports only slave receivers and slavetransmitters. SDA SCL St 1−7 8 9 1−8 9 1−8 9 9 Sp Slave Address R/W ACK DATA ACK DATA ACK ACK R/W: Read Operation if 1; Otherwise, Write Operation Start ACK: Acknowledgement of a Byte if 0 Stop Condition Condition DATA: 8 Bits (Byte) NACK: Not Acknowledgement if 1 Write Operation Transmitter M M M S M S M S S M Data Type St Slave Address W ACK DATA ACK DATA ACK ACK Sp Read Operation Transmitter M M M S S M S M M M Data Type St Slave Address R ACK DATA ACK DATA ACK NACK Sp M: Master Device S: Slave Device St: Start Condition Sp: Stop Condition W: Write R: Read T0049-01 Figure27.BasicI2CFramework WRITEOPERATION A master can write to any PCM1680 registers using a single access. The master sends a PCM1680 slave address with a write bit, a register address, and the data. When undefined registers are accessed, the PCM1680 sendsanacknowledgment,butthewriteoperationdoesnotoccur.Figure28isadiagramofthewriteoperation. Transmitter M M M S M S M S M Data Type St Slave Address W ACK Reg Address ACK Write Data ACK Sp M: Master Device S: Slave Device St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition R0002-01 Figure28.WriteOperation READOPERATION A master can read any PCM1680 register using a single access. The master sends a PCM1680 slave address with a read bit after transferring the register address. Then the PCM1680 transfers the data in the register specified.Figure29isadiagramofthereadoperation. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com Transmitter M M M S M S M M M S S M M Data Type St Slave Address W ACK Reg Address ACK Sr Slave Address R ACK Read Data NACK Sp M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge W: Write R: Read R0002-02 NOTE: Theslaveaddressaftertherepeatedstartconditionmustbethesameasthepreviousslaveaddress. Figure29.ReadOperation TIMING DIAGRAM Start Repeated Start Stop t(D-HD) t(SDA-F) t(BUF) t(D-SU) t(SDA-R) t(P-SU) SDA t(SCL-R) t(RS-HD) t(LOW) SCL t(S-HD) t(HI) t(RS-SU) t(SCL-F) T0050-01 PARAMETER MIN MAX UNIT f SCLclockfrequency 100 kHz (SCL) t BusfreetimebetweenaSTOPandSTARTcondition 4.7 m s (BUF) t LowperiodoftheSCLclock 4.7 m s (LOW) t HighperiodoftheSCLclock 4 m s (HI) t Setuptimefor(repeated)STARTcondition 4.7 m s (RS-SU) t(S-HD) Holdtimefor(repeated)STARTcondition 4 m s t (RS-HD) t Datasetuptime 250 ns (D-SU) t Dataholdtime 0 900 ns (D-HD) t RisetimeofSCLsignal 20+0.1C 1000 ns (SCL-R) B RisetimeofSCLsignalafterarepeatedSTARTconditionandafter t 20+0.1C 1000 ns (SCL-R1) anacknowledgebit B t FalltimeofSCLsignal 20+0.1C 1000 ns (SCL-F) B t RisetimeofSDAsignal 20+0.1C 1000 ns (SDA-R) B t FalltimeofSDAsignal 20+0.1C 1000 ns (SDA-F) B t SetuptimeforSTOPcondition 4 m s (P-SU) C CapacitiveloadforSDAandSCLlines 400 pF B Noisemarginathighlevelforeachconnecteddevice V 0.2V V NH (includinghysteresis) DD Figure30.InterfaceTiming 20 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 MODE CONTROL REGISTERS USER-PROGRAMMABLEMODECONTROLS The PCM1680 includes a number of user-programmable functions which are accessed via control registers. The registers are programmed using the serial control interface which is discussed in the Mode Control section of this data sheet. Table 5 lists the available mode control functions, along with the respective reset default conditions andassociatedregisterindex. REGISTERMAP The mode control register map is shown in Table 6. The MSB of all registers is fixed to 0. Each register also includesanindex(oraddress)indicatedbytheIDX[6:0]bits. RESERVEDREGISTERS Registers 0, 11, and 15 are reserved for factory use. To ensure proper operation, the user should not write to theseregisters. Table5.User-ProgrammableModeControls FUNCTION RESETDEFAULT REGISTER BIT Digitalattenuationcontrol,0dBto–63dB AT1[7:0],AT2[7:0],AT3[7:0],AT4[7:0], 0dB,noattenuation 1–6,16,17 in0.5-dBsteps AT5[7:0],AT6[7:0],AT7[7:0],AT8[7:0] Softmutecontrol Mutedisabled 7,18 MUT[6:1],MUT[8:7] DAC1–DAC8operationcontrol DAC1–DAC8enabled 8,19 DAC[6:1],DAC[8:7] Audiodataformatcontrol 24-bit,left-justified 9 FMT[2:0] Digitalfilterroll-offcontrol Sharproll-off 9 FLT De-emphasisofallchannels De-emphasisall-channelfunctioncontrol 10 DMC disabled De-emphasisall-channelsamplerate 44.1kHz 10 DMF[1:0] selection Outputphaseselect Normalphase 10 DREV Zero-flagpolarityselect High 10 ZREV Softwareresetcontrol Resetdisabled 10 SRST Oversamplingratecontrol x64,x32,x16 12 OVER ZERO1:DATA1Lch Zero-flagcombinationselect 13 AZRO[1:0] ZERO2:DATA1Rch Digitalattenuationmodeselect 0to–63dB,0.5-dBstep 13 DAMS Zero-detectstatus(read-only,I2C N/A 14 ZERO[8:1] interfaceonly) Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com Table6.ModeControlRegisterMap IDX (B8–B14) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 01h 1 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 02h 2 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 03h 3 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 04h 4 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 05h 5 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 06h 6 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 07h 7 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 08h 8 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 09h 9 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) FLT RSV(1) RSV(1) FMT2 FMT1 FMT0 0Ah 10 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST ZREV DREV DMF1 DMF0 RSV(1) RSV(1) DMC 0Ch 12 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) 0Dh 13 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DAMS AZRO1 AZRO0 RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) 0Eh 14 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 10h 16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT77 AT76 AT75 AT74 AT73 AT72 AT71 AT70 11h 17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80 12h 18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) MUT8 MUT7 13h 19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) RSV(1) DAC8 DAC7 (1) Reservedfortestoperation.Itshouldbesetto'0'duringnormaloperation. 22 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 REGISTER DEFINITIONS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER1 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 REGISTER2 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 REGISTER3 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 REGISTER4 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 REGISTER5 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 REGISTER6 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 REGISTER16 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT77 AT76 AT75 AT74 AT73 AT72 AT711 AT70 REGISTER17 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80 ATx[7:0]:DigitalAttenuationLevelSetting Wherex=1–8,correspondingtotheDACoutputV x.Defaultvalue:11111111b. OUT ATTENUATIONLEVELSETTING ATx[7:0] DECIMALVALUE DAMS=0 DAMS=1 11111111b 255 0dB,noattenuation(default) 0dB,noattenuation(default) 11111110b 254 –0.5dB –1dB 11111101b 253 –1dB –2dB : : : : 10011100b 156 –49.5dB –99dB 10011011b 155 –50dB –100dB 10011010b 154 –50.5dB Mute : : : : 10000010b 130 –62.5dB Mute 10000001b 129 –63dB Mute 10000000b 128 Mute Mute : : : : 00000000b 0 Mute Mute Each DAC output, V 1 through V 8, has a digital attenuation function. The attenuation level can be set from OUT OUT 0 dB to R dB, in S-dB steps. Changes in attenuation levels are made by incrementing or decrementing by one step (S-dB) for every 8/f time interval until the programmed attenuation setting is reached. Alternatively, the S attenuation level can be set to infinite attenuation (or mute). Range (R) and step (S) are –63 and 0.5, respectively, for DAMS = 0 and –100 and 1, respectively, for DAMS = 1. The DAMS bit is defined in register 13. The attenuation data for each channel can be set individually. The attenuation level can be calculated using the followingformula: Attenuationlevel(dB)=S×(ATx[7:0] –255) DEC Where ATx[7:0] = 0 through 255. For ATx[7:0] = 0 through 128 with DAMS = 0 or for ATx[7:0] = 0 DEC DEC DEC through154withDAMS=1,theattenuationissettoinfiniteattenuation(mute). Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER7 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 REGISTER18 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV MUT8 MUT7 MUTx:SoftMuteControl Wherex=1–8,correspondingtotheDACoutputV x.Defaultvalue:0 OUT MUTx=0 Mutedisabled(default) MUTx=1 Muteenabled The mute bits, MUT1 through MUT8, are used to enable or disable the soft mute function for the corresponding DAC outputs, V 1 through V 8. The soft mute function is incorporated into the digital attenuators. When OUT OUT mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite-attenuation setting one attenuator step (S-dB) at a time. This provides a quiet, pop-free muting of the DAC output. On returning from soft mute, by setting MUTx = 0, the attenuator is increased one step at a time to thepreviouslyprogrammedattenuatorlevel.Thestepsize,S,is0.5dBforDAMS=0and1dBforDAMS=1. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER8 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 REGISTER19 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV RSV RSV RSV DAC8 DAC7 DACx:DACOperationControl Wherex=1–8,correspondingtotheDACoutputV x.Defaultvalue:0 OUT DACx=0 DACoperationenabled(default) DACx=1 DACoperationdisabled The DAC operation controls are used to enable and disable the DAC outputs, V 1 through V 8. When OUT OUT DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input isswitchedtothedccommonvoltage(V ),equaltoV /2. COM CC 24 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER9 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT RSV RSV FMT2 FMT1 FMT0 FLT:DigitalFilterRoll-OffControl Defaultvalue:0 FLT=0 Sharproll-off(default) FLT=1 Slowroll-off The FLT bit allows users to select the digital filter roll-off that is best suited to their application. Two filter roll-off selections are available: sharp or slow. The filter responses for these selections are shown in the Typical Characteristicssectionofthisdatasheet. FMT[2:0]:AudioInterfaceDataFormat Defaultvalue:101b FMT[2:0] AudioDataFormatSelection 000 24-bitright-justifiedformat,standarddata 001 20-bitright-justifiedformat,standarddata 010 18-bitright-justifiedformat,standarddata 011 16-bitright-justifiedformat,standarddata 100 I2Sformat,16-to24-bit 101 Left-justifiedformat,16-to24-bit(default) 110 Reserved 111 Reserved TheFMT[2:0]bitsareusedtoselectthedataformatfortheserialaudiointerface. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER10 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST ZREV DREV DMF1 DMF0 RSV RSV DMC SRST:Reset Defaultvalue:0 SRST=0 Resetdisabled(default) SRST=1 Resetenabled The SRST bit is used to enable or disable the soft reset function. The operation is the same as the power-on-reset function with the exception of the reset period, which is 1024 system clocks for the SRST function.Allregistersareinitialized. ZREV:Zero-FlagPolaritySelect Defaultvalue:0 ZREV=0 Zero-flagpinshighatazerodetect(default) ZREV=1 Zero-flagpinslowatazerodetect TheZREVbitallowstheusertoselectthepolarityofthezero-flagpins. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com DREV:OutputPhaseSelect Defaultvalue:0 DREV=0 Normaloutput(default) DREV=1 Invertedoutput TheDREVbitistheoutputanalogsignalphasecontrol. DMF[1:0]:SamplingFrequencySelectionfortheDe-EmphasisFunction Defaultvalue:00b DMF[1:0] De-EmphasisSamplingRateSelection 00 44.1kHz(default) 01 48kHz 10 32kHz 11 Reserved The DMF[1:0] bits select the sampling frequency used for the digital de-emphasis function when it is enabled. The de-emphasis curves are shown in the Typical Characteristics section of this data sheet. The preceding table showstheavailablesamplingfrequencies. DMC:DigitalDe-EmphasisAll-ChannelFunctionControl Defaultvalue:0 DMC=0 De-emphasisdisabledforallchannels(default) DMC=1 De-emphasisenabledforallchannels TheDMCbitisusedtoenableordisablethede-emphasisfunctionforallchannels. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER12 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV RSV RSV RSV RSV RSV RSV OVER:OversamplingRateControl Defaultvalue:0 Systemclockfrequency=512f ,768f ,or1152f S S S OVER=0 x64oversampling(default) OVER=1 x128oversampling(applicableonlyifsamplingclockfrequency≤24kHz) Systemclockfrequency=256f or384f S S OVER=0 x32oversampling(default) OVER=1 x64oversampling(applicableonlyifsamplingclockfrequency≤48kHz) Systemclockfrequency=128f or192f . S S OVER=0 x16oversampling(default) OVER=1 x32oversampling(applicableonlyifsamplingclockfrequency≤96kHz) TheOVERbitisusedtocontroltheoversamplingrateoftheΔΣDACs. SettingOVER=1isrecommendedunderthefollowingconditions: • Systemclockfrequency=512f ,768f ,or1152f andsamplingclockfrequency≤24kHz S S S • Systemclockfrequency=256f or384f andsamplingclockfrequency≤48kHz S S • Systemclockfrequency=128f or192f andsamplingclockfrequency≤96kHz S S 26 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER13 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DAMS AZRO1 AZRO0 RSV RSV RSV RSV RSV DAMS:DigitalAttenuationModeSelect Defaultvalue:0 DAMS=0 Finestep,0.5dB/stepfor0to–63dBrange(default) DAMS=1 Widerange,1dB/stepfor0to–100dBrange TheDAMSbitisusedtoselectthedigitalattenuationmode. AZRO[1:0]:Zero-FlagChannel-CombinationSelect Defaultvalue:00b AZRO[1:0] Zero-FlagChannel-CombinationSelect 00 CombinationA(ZERO1:DATA1L-ch,ZERO2:DATA1R-ch)(default) 01 CombinationB(ZERO1:N/A,ZERO2:DATA1–DATA4) 10 CombinationC(ZERO1:DATA4,ZERO2:DATA1–DATA3) 11 CombinationD(ZERO1:DATA1,ZERO2:DATA2–DATA4) TheAZRO[1:0]bitsareusedtoselectthezero-flagchannelcombinationsforZERO1andZERO2. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER14 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 ZERO[8:1]:Zero-DetectStatus(Read-Only,I2CInterfaceOnly) Defaultvalue:N/A The ZERO[8:1] bits show the status of zero detect for each channel. The status is set to '1' by detecting a zero statewithoutregardtotheZREVbitsetting. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com ANALOG OUTPUTS The PCM1680 includes eight independent output channels, V 1 through V 8. These channels are OUT OUT unbalanced outputs, each capable of driving 3.9 V typical into a 5-kΩ ac load with V = 5 V. The internal PP CC outputamplifiersforV 1throughV 8arebiasedtothedccommonvoltage,equalto0.5×V . OUT OUT CC The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise-shaping characteristics of the PCM1680 ΔΣ DACs. The frequency response of this filter is shown in Figure 11. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for most applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Application Informationsectionofthisdatasheet. V OUTPUT COM One unbuffered common voltage output pin, V (pin 25), is brought out for decoupling purposes. This pin is COM nominally biased to the dc common voltage, equal to V /2. If this pin is to be used to bias external circuitry, a CC voltage follower is required for buffering purposes. Figure 31 shows an example of using the V pin for COM externalbiasingapplications. R A (cid:2)(cid:1) 2 V R 1 PCM1680 R2 C1 VCC R1 R3 2 VOUTX – R4 1 + OPA2134 C2 3 + R5 VCOM + To Additional OPA337 Low-Pass + C3 − Filter Circuits 10 m F S0056-01 Figure31.Single-SupplyFilterCircuitUsingV forExternalBiasingApplications COM 28 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 APPLICATION INFORMATION CONNECTION DIAGRAMS A basic connection diagram is shown in Figure 32, with the necessary power-supply bypassing and decoupling components. Texas Instruments’ PLL170x is used to generate the system clock input at SCK, as well as generating the clock for the audio signal processor. The use of series resistors (22 Ω to 100 Ω) is recommended for SCK, LRCK, BCK, DATA1, DATA2, DATA3, and DATA4. The series resistor combines with the stray printed circuit board (PCB) capacitance and device input capacitance to form a low-pass filter that removes high-frequencynoisefromthedigitalsignal,thusreducinghigh-frequencyemission. 1 ZERO1 ZERO2 28 + C1 2 MS/ADR VOUT1 27 m C or m P + C2 3 MC/SCL VOUT2 26 4 MD/SDA VCOM 25 + R1 C12 5 SCK AGND2 24 L PLL170x 27-MHz R4 6 DATA1 VCC2 23 C11 R Master + C3 Clock 7 BCK VOUT3 22 LF R3 8 LRCK PCM1680VOUT4 21 + C4 LoOwu-tPpausts RF R2 C9 + C5 Filter 9 VDD VOUT5 20 LS Audio DSP 10 DGND VOUT6 19 + C6 RS or R5 CTR Decoder 11 DATA2 AGND1 18 SUB R6 12 DATA3 VCC1 17 R7 C10 + C7 13 DATA4 VOUT7 16 + C8 14 MSEL VOUT8 15 C13 5 V Analog + 0 V C1−C8: 4.7-m F to 10-m F Electrolytic Typical C9−C11: 1-m F Ceramic Typical C12, C13: 10-m F Electrolytic Typical R1−R7: 22 W to 100 W Typical S0057-01 Figure32.BasicConnectionDiagram Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com POWER SUPPLY AND GROUNDING The PCM1680 requires 5 V for the analog supply and digital supply. The 5-V supply is used to power not only the DAC analog and output filter circuitry, but also the digital filter and serial interface circuitry. For best performance,a5-Vsupplyusingalinearregulatorisrecommended. Fourcapacitorsarerequiredforsupplybypassing, as shown in Figure 32. These capacitors should be located as close as possible to the PCM1680 package. The 10-m F capacitor should be tantalum or aluminum electrolytic, whilethethree1-m Fcapacitorsareceramic. DAC OUTPUT FILTER CIRCUITS ΔΣ DACs use noise shaping techniques to improve in-band signal-to-noise ratio (SNR) performance at the expense of generating increased out-of-band noise above the Nyquist frequency, or f /2. The out-of-band noise S must be low-pass filtered in order to provide optimal converter performance. This is accomplished by a combinationofon-chipandexternallow-passfiltering. Figure 31 and Figure 33 show the recommended external low-pass active filter circuits for dual- and single-supply applications. These circuits are second-order Butterworth filters using a multiple-feedback (MFB) circuit arrangement, which reduces sensitivity to passive component variations over frequency and temperature. For more information regarding MFB active filter design, see Dynamic Performance Testing of Digital Audio D/A Converters(SBAA055). Because the overall system performance is defined by the quality of the DACs and their associated analog output circuitry, high-quality audio operational amplifiers are recommended for the active filters. Texas Instruments’ OPA2134 and OPA2353 dual operational amplifiers are shown in Figure 31 and Figure 33, and are recommendedforusewiththePCM1680. R2 C1 R1 R3 2 VIN – R4 1 3 OPA2134 VOUT C2 + R A (cid:2)(cid:1) 2 V R 1 S0053-01 Figure33.Dual-SupplyFilterCircuit PCB LAYOUT GUIDELINES A typical PCB floor plan for the PCM1680 is shown in Figure 34. A ground plane is recommended, with the analoganddigitalsectionsbeingisolatedfromoneanotherusingasplitorcut in the circuit board. The PCM1680 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections tothedigitalaudiointerfaceandcontrolsignalsoriginatingfromthedigitalsectionoftheboard. Separate power supplies are recommended for the digital and analog sections of the board. This separation prevents the switching noise present on the digital supply from contaminating the analog power supply and degrading the dynamic performance of the PCM1680. In cases where a common 5-V supply must be used for theanalog and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital 5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 35 showstherecommendedapproachforsingle-supplyapplications. 30 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PCM1680 www.ti.com.................................................................................................................................................. SLES133B–MARCH2005–REVISEDOCTOBER2008 Digital Power Analog Power +VD DGND AGND +5VA +VS –VS VDD VCC Digital Logic and DGND Output Audio Circuits Processor PCM1680 Digital Ground AGND Analog Digital Section Analog Section Ground Return Path for Digital Signals B0031-02 Figure34.RecommendedPCBLayout Power Supplies RF Choke or Ferrite Bead +5V AGND +VS –VS VDD VDD VCC Digital Logic and DGND Output Audio Circuits Processor PCM1680 AGND Common Digital Section Analog Section Ground B0032-02 Figure35.Single-SupplyPCBLayout Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):PCM1680

PCM1680 SLES133B–MARCH2005–REVISEDOCTOBER2008.................................................................................................................................................. www.ti.com Revision History ChangesfromRevisionA(August2006)toRevisionB ................................................................................................ Page • Changed0.49V to0.486V intheDCAccuracysectionoftheElectricalCharacteristicstable.................................... 3 CC CC • Correctedfootnote1inFigure26........................................................................................................................................ 18 32 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):PCM1680

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) PCM1680DBQ ACTIVE SSOP DBQ 28 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 70 PCM1680 & no Sb/Br) PCM1680DBQG4 ACTIVE SSOP DBQ 28 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 70 PCM1680 & no Sb/Br) PCM1680DBQR ACTIVE SSOP DBQ 28 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -25 to 70 PCM1680 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) PCM1680DBQR SSOP DBQ 28 2000 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) PCM1680DBQR SSOP DBQ 28 2000 367.0 367.0 38.0 PackMaterials-Page2

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