PCF8593 Low power clock and calendar Rev. 04 — 6 October 2010 Product data sheet 1. General description The PCF8593 is a CMOS1 clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte. The built-in 32.768kHz oscillator circuit and the first 8bytes of the RAM are used for the clock, calendar, and counter functions. The next 8 bytes can be programmed as alarm registers or used as free RAM space. 2. Features and benefits (cid:132) I2C-bus interface operating supply voltage: 2.5 V to 6.0 V (cid:132) Clock operating supply voltage 1.0Vto6.0 V at 0°Cto+70°C (cid:132) 8 bytes scratchpad RAM (when alarm not used) (cid:132) Data retention voltage: 1.0 V to 6.0 V (cid:132) External RESET input resets I2C interface only (cid:132) Operating current (at f = 0Hz, 32 kHz time base, V =2.0V): typical1 μA SCL DD (cid:132) Clock function with four year calendar (cid:132) Universal timer with alarm and overflow indication (cid:132) 24hour or12hour format (cid:132) 32.768kHz or 50Hz time base (cid:132) Serial input and output bus (I2C-bus) (cid:132) Automatic word address incrementing (cid:132) Programmable alarm, timer, and interrupt function (cid:132) Space-saving SO8 package available (cid:132) Slave addresses: A3h for reading, A2h for writing 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF8593P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF8593T SO8 plastic small outline package; 8 leads; SOT96-1 body width 3.9 mm 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section14.

PCF8593 NXP Semiconductors Low power clock and calendar 4. Marking Table 2. Marking codes Type number Marking code PCF8593P PCF8593P PCF8593T 8583T 5. Block diagram VDD OSCI OSCILLATOR DIVIDER OSCO 00h control/status INT 01h hundredth second 02h seconds 03h minutes CONTROL RESET RESET LOGIC 04h hours 05h year/date PCF8593 06h weekdays/months 07h timer SCL 08h alarm control I2C-BUS ADDRESS INTERFACE REGISTER to alarm or RAM SDA 0Fh 013aaa379 VSS Fig 1. Block diagram of PCF8593 PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 2 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 6. Pinning information 6.1 Pinning OSCI 1 8 VDD OSCO 2 7 INT PCF8593P RESET 3 6 SCL VSS 4 5 SDA 013aaa380 Top view. For mechanical details, see Figure24. Fig 2. Pin configuration for DIP8 (PCF8593P) OSCI 1 8 VDD OSCO 2 7 INT PCF8593T RESET 3 6 SCL VSS 4 5 SDA 013aaa381 Top view. For mechanical details, see Figure25. Fig 3. Pin configuration for SO8 (PCF8593T) 6.2 Pin description Table 3. Pin description Symbol Pin Type Description DIP8 SO8 (PCF8593P) (PCF8593T) OSCI 1 1 input oscillator input, 50 Hz or event-pulse input OSCO 2 2 output oscillator output RESET 3 3 input reset V 4 4 supply ground supply voltage SS SDA 5 5 input/output serial data line SCL 6 6 input serial clock line INT 7 7 output open-drain interrupt output (active LOW) V 8 8 supply supply voltage DD PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 3 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 7. Functional description The PCF8593 contains sixteen 8 bit registers with an 8 bit auto-incrementing address register, an on-chip 32.768kHz oscillator circuit, a frequency divider and a serial two-line bidirectional I2C-bus interface. The first 8 registers (memory addresses 00hto07h) are designed as addressable 8bit parallel registers. The first register (memory address00h) is used as a control and status register. The memory addresses 01hto07h are used as counters for the clock function. The memory addresses 08hto0Fh may be programmed as alarm registers or used as free RAM locations. 7.1 Counter function modes When the control and status register is programmed, a 32.768kHz clock mode, a 50Hz clock mode or an event-counter mode can be selected. In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and weekday are stored in a Binary Coded Decimal (BCD) format. The timer register stores up to 99 days. The event counter mode is used to count pulses applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data. When one of the counters is read (memory locations 01hto07h), the contents of all counters are strobed into capture latches at the beginning of a read cycle. Therefore, faulty reading of the counter during a carry condition is prevented. When a counter is written, other counters are not affected. 7.2 Alarm function modes By setting the alarm enable bit of the control and status register the alarm control register (address08h) is activated. By setting the alarm control register, a dated alarm, a daily alarm, a weekday alarm, or a timer alarm may be programmed. In the clock modes, the timer register (address07h) may be programmed to count hundredths of a second, seconds, minutes, hours, or days. Days are counted when an alarm is not programmed. Whenever an alarm event occurs the alarm flag of the control and status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open-drain interrupt output is switched on (active LOW) when the alarm or timer flag is set (enabled). The flags remain set until directly reset by a write operation. When the alarm is disabled (bit2 of control and status registerset logic0) the alarm registers at addresses 08hto0Fh may be used as free RAM. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 4 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 7.3 Control and status register The control and status register is defined as the memory location 00h with free access for reading and writing via the I2C-bus. All functions and options are controlled by the contents of the control and status register (see Figure4). MSB LSB memory location 00h 7 6 5 4 3 2 1 0 timer flag: 50 % duty factor seconds flag if alarm enable bit is logic 0 alarm flag:50 % duty factor minutes flag if alarm enable bit is logic 0 alarm enable bit: logic 0: alarm disabled: flags toggle alarm control register to disabled (memory locations 08h to 0Fh are free RAM space) logic 1: enable alarm control register (memory location 08h is the alarm control register) mask flag: logic 0: read locations 05h to 06h unmasked logic 1: read date and month count directly function mode: 00 clock mode 32.768 kHz 01 clock mode 50 Hz 10 event-counter mode 11 test modes hold last count flag: logic 0: count logic 1: store and hold last count in capture latches stop counting flag: 013aaa382 logic 0: count pulses logic 1: stop counting, reset divider Fig 4. Control and status register PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 5 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 7.4 Counter registers The format for 24hour or 12hour clock modes can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in Figure5. MSB LSB memory location 04h (hours counter) 7 6 5 4 3 2 1 0 hours in BCD format: unit place ten's place (0 to 2 binary) AM/PM flag: logic 0: AM logic 1: PM format: 013aaa383 logic 0: 24 hour format, AM/PM flag remains unchanged logic 1: 12 h format, AM/PM flag will be updated Fig 5. Format of the hours counter The year and date are stored in memory location 05h (see Figure6). The weekdays and months are in memory location 06h (see Figure7). MSB LSB memory location 05h (year/date) 7 6 5 4 3 2 1 0 days in BCD format: unit place ten's place (0 to 3 binary) year (0 to 3 binary, read as logic 0 if the mask flag is set) 013aaa384 Fig 6. Format of the year and date counter MSB LSB memory location 06h (weekdays/months) 7 6 5 4 3 2 1 0 months in BCD format: unit place ten's place weekdays (0 to 6 binary, read as logic 0 if the mask flag is set) 013aaa385 Fig 7. Format of the weekdays and month counter When reading these memory locations the year and weekdays are masked out when the mask flag of the control and status register is set. This allows the user to read the date and month count directly. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 6 of 35

PCF8593 NXP Semiconductors Low power clock and calendar In the event-counter mode, events are stored in BCD format. D5 is the most significant and D0 the least significant digit. The divider is by-passed. In the different modes the counter registers are programmed and arranged as shown in Figure8. Counter cycles are listed in Table4. control/status control/status 00h hundredth of a second D1 D0 01h 1/10 s 1/100 s seconds D3 D2 02h 10 s 1 s minutes 10 min 1 min D5 D4 03h hours free 04h 10 h 1 h year/date free 05h 10 day 1 day weekdays/months free 06h 10 month 1 month timer timer T1 T0 07h 10 day 1 day alarm control alarm control 08h hundredth of a second alarm alarm alarm 09h 1/10 s 1/100 s D1 D0 alarm seconds D3 D2 0Ah alarm minutes D5 D4 0Bh alarm hours 0Ch free alarm date free 0Dh alarm month free 0Eh alarm timer alarm timer 0Fh CLOCK MODES EVENT COUNTER 013aaa386 Fig 8. Register arrangement PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 7 of 35

PCF8593 NXP Semiconductors Low power clock and calendar Table 4. Cycle length of the time counters, clock modes Unit Counting cycle Carry to next unit Contents of month calendar hundredths of a second 00 to 99 99 to 00 - seconds 00 to 59 59 to 00 - minutes 00 to 59 59 to 00 - hours (24) 00 to 23 23 to 00 - hours (12) 12 am - - 01 am to 11 am - - 12 pm - - 01 pm to 11 pm 11 pm to 12 am - date 01 to 31 31 to 01 1, 3, 5, 7, 8, 10, and 12 01 to 30 30 to 01 4, 6, 9, and 11 01 to 29 29 to 01 2, year = 0 01 to 28 28 to 01 2, year = 1, 2, and 3 months 01 to 12 12 to 01 - year 0 to 3 - - weekdays 0 to 6 6 to 0 - timer 00 to 99 no carry - 7.5 Alarm control register When the alarm enable bit of the control and status register is set (address 00h, bit2) the alarm control register (address 08h) is activated. All alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see Figure9). PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 8 of 35

PCF8593 NXP Semiconductors Low power clock and calendar MSB LSB memory location 08h 7 6 5 4 3 2 1 0 timer function: 000 no timer 001 hundredths of a second 010 seconds 011 minutes 100 hours 101 days 110 not used 111 test mode, all counters in parallel timer interrupt enable: 0 timer flag, no interrupt 1 timer flag, interrupt clock alarm function: 00 no clock alarm 01 daily alarm 10 weekday alarm 11 dated alarm timer alarm enable: 0 no timer alarm 1 timer alarm alarm interrupt enable: 013aaa387 (only valid when alarm enable in the control and status register is set) 0 alarm flag, no interrupt 1 alarm flag, interrupt Fig 9. Alarm control registers, clock mode 7.6 Alarm registers All alarm registers are allocated with a constant address offset of 08h to the corresponding counter registers (see Figure8). An alarm signal is generated when the contents of the alarm registers match bit-by-bit the contents of the involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday and month register selects the weekdays on which an alarm is activated (see Figure10). Remark: In the 12hour mode, bits6 and7 of the alarm hours register must be the same as the hours counter. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 9 of 35

PCF8593 NXP Semiconductors Low power clock and calendar MSB LSB 7 6 5 4 3 2 1 0 memory location 0Eh (alarm_weekday/month) weekday 0 enabled when set weekday 1 enabled when set weekday 2 enabled when set weekday 3 enabled when set weekday 4 enabled when set weekday 5 enabled when set weekday 6 enabled when set not used 013aaa375 Fig 10. Selection of alarm weekdays 7.7 Timer The timer (location07h) is enabled by setting the control and status register to XX0XX1XX. The timer counts up from 0 (or a programmed value) to99. On overflow, the timer resets to0. The timer flag (LSB of control and status register) is set on overflow of the timer. This flag must be reset by software. The inverted value of this flag can be transferred to the external interrupt by setting bit3 of the alarm control register. Additionally, a timer alarm can be programmed by setting the timer alarm enable (bit6 of the alarm control register). When the value of the timer equals a pre-programmed value in the alarm timer register (location0Fh), the alarm flag is set (bit1 of the control and status register). The inverted value of the alarm flag can be transferred to the external interrupt by enabling the alarm interrupt (bit6 of the alarm control register). Resolution of the timer is programmed via the 3LSBs of the alarm control register (see Figure11). PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 10 of 35

PCF8593 NXP Semiconductors Low power clock and calendar MUX mode oscillator select CLOCK/CALENDAR counter control ALARM TIMER clock alarm timer timer alarm control alarm overflow control 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CONTROL/STATUS ALARM CONTROL REGISTER (1) REGISTER alarm timer overflow interrupt interrupt INT 013aaa377 (1) If the alarm enable bit of the control and status register is reset (logic 0), a 1 Hz signal is observed on the interrupt pin INT. Fig 11. Alarm and timer interrupt logic diagram 7.8 Event counter mode Event counter mode is selected by bits4 and5 which are logic10 in the control and status register. The event counter mode is used to count pulses externally applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6digits of data, which are stored as 6hexadecimal values located in the registers1h,2h, and3h. Therefore, up to 1million events may be recorded. An event counter alarm occurs when the event counter registers match the value programmed in the registers 9h, Ah, and Bh, and the event alarm is enabled (bits4 and5 which are logic01 in the alarm control register). In this event, the alarm flag (bit1 of the control and status register) is set. The inverted value of this flag can be transferred to the interrupt pin (pin7) by setting the alarm interrupt enable in the alarm control register. In PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 11 of 35

PCF8593 NXP Semiconductors Low power clock and calendar this mode, the timer (location07h) increments once for every one, one hundred, ten thousand, or 1 million events, depending on the value programmed in bits0,1 and2 of the alarm control register. In all other events, the timer functions are as in the clock mode. MSB LSB memory location 08h 7 6 5 4 3 2 1 0 reset state: 0000 0000 timer function: 000 no timer 001 units 010 100 011 10 000 100 1 000 000 101 not allowed 110 not allowed 111 test mode, all counters in parallel timer interrupt enable: 0 timer flag, no interrupt 1 timer flag, interrupt clock alarm function: 00 no event alarm 01 event alarm 10 not allowed 11 not allowed timer alarm enable: 0 no timer alarm 1 timer alarm alarm interrupt enable: 013aaa376 0 alarm flag, no interrupt 1 alarm flag, interrupt Fig 12. Alarm control register, event counter mode 7.9 Interrupt control The conditions for activating the output INT (active LOW) are determined by appropriate programming of the alarm control register. These conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. An interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interrupt is enabled. In all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt. In the clock mode, if the alarm enable is not activated (alarm enable bit of the control and status register is logic0), the interrupt output toggles at 1 Hz with a 50% duty cycle (may be used for calibration). The OFF voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 V. A logic diagram of the interrupt output is shown in Figure11. 7.10 Oscillator and divider A 32.768kHz quartz crystal has to be connected to OSCI and OSCO. A trimmer capacitor between OSCI and V is used for tuning the oscillator (see Section11.1). A 100Hz clock DD signal is derived from the quartz oscillator for the clock counters. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 12 of 35

PCF8593 NXP Semiconductors Low power clock and calendar In the 50Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high-impedance state. This allows the user to feed the 50Hz reference frequency or an external high speed event signal into the input OSCI. 7.10.1 Designing When designing the printed-circuit board layout, keep the oscillator components as close to the IC package as possible, and keep all other signal lines as far away as possible. In applications involving tight packing of components, shielding of the oscillator may be necessary. AC coupling of extraneous signals can introduce oscillator inaccuracy. 7.11 Initialization Note that immediately following power-on, all internal registers are undefined and, following a RESET pulse on pin3, must be defined via software. Attention should be paid to the possibility that the device may be initially in event-counter mode, in which event the oscillator will not operate. Over-ride can be achieved via software. Reset is accomplished by applying an external RESET pulse (active LOW) at pin3. When reset occurs only the I2C-bus interface is reset. The control and status register and all clock counters are not affected by RESET. RESET must return HIGH during device operation. An RC combination can also be utilized to provide a power-on RESET signal at pin3. In this event, the values of the PCF8593 must fulfil the following relationship to guarantee power-on reset (see Figure13). VDD RR VDD reset input RESET CR PCF8593 013aaa388 To avoid overload of the internal diode by falling V , an external diode should be added in parallel DD to RR if CR ≥ 0.2 μF. Note that RC must be evaluated with the actual VDD of the application, as their value will be V rise-time dependent. DD Fig 13. PCF8593 reset RESET input must be input must be ≤0.3V when V reaches V (or higher). DD DD DD(min) It is recommended to set the stop counting flag of the control and status register before loading the actual time into the counters. Loading of illegal states may lead to a temporary clock malfunction. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 13 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 8. Characteristics of the I2C-bus 8.1 Characteristics The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy. 8.1.1 Bit transfer One data bit is transferred during each clock pulse (see Figure14). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as a control signal. SDA SCL data line change stable; of data data valid allowed mbc621 Fig 14. Bit transfer 8.1.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. ALOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure15). SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 15. Definition of start and stop conditions 8.1.3 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver (see Figure16). The device that controls the message is the master; and the devices which are controlled by the master are the slaves. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 14 of 35

PCF8593 NXP Semiconductors Low power clock and calendar SDA SCL MASTER SLAVE SLAVE MASTER MASTER TRANSMITTER RECEIVER TRANSMITTER TRANSMITTER TRANSMITTER RECEIVER RECEIVER RECEIVER mba605 Fig 16. System configuration 8.1.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure17. data output by transmitter not acknowledge data output by receiver acknowledge SCL from 1 2 8 9 master S clock pulse for START acknowledgement condition mbc602 Fig 17. Acknowledgement on the I2C-bus PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 15 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 8.2 I2C-bus protocol 8.2.1 Addressing Before any data is transmitted on the I2C-bus, the device which must respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The clock and calendar acts as a slave receiver or slave transmitter. The clock signal SCL is only an input signal but the data signal SDA is a bidirectional line. The clock and calendar slave address is shown in Table5. Table 5. I2C slave address byte Slave address Bit 7 6 5 4 3 2 1 0 MSB LSB 1 0 1 0 0 0 1 R/W 8.2.2 Clock and calendar READ or WRITE cycles The I2C-bus configuration for the different PCF8593 READ and WRITE cycles is shown in Figure18, Figure19 and Figure20. acknowledgement acknowledgement acknowledgement from slave from slave from slave S SLAVE ADDRESS 0 A REGISTER ADDRESS A DATA A P R/W n bytes auto increment memory register address 013aaa346 Fig 18. Master transmits to slave receiver (WRITE mode) PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 16 of 35

PCF8593 NXP Semiconductors Low power clock and calendar acknowledgement acknowledgement acknowledgement acknowledgement from slave from slave from slave from slave S SLAVE ADDRESS 0 A REGISTER ADDRESS A S SLAVE ADDRESS 1 A DATA A n bytes R/W R/W auto increment (1) memory register address no acknowledgement from master DATA 1 P last byte auto increment memory register address 013aaa041 (1) At this moment master transmitter becomes master receiver and PCF8593 slave receiver becomes slave transmitter. Fig 19. Master reads after setting word address (write word address; READ data) acknowledgement acknowledgement no acknowledgement from slave from master from master S SLAVE ADDRESS 1 A DATA A DATA 1 P R/W n bytes last byte auto increment auto increment register address register address 013aaa347 Fig 20. Master reads slave immediately after first byte (READ mode) PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 17 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V supply voltage −0.8 +0.7 V DD I supply current - 50 mA DD I ground supply current - 50 mA SS V input voltage −0.8 V + 0.8 V I DD I input current - 10 mA I I output current - 10 mA O P total power dissipation - 300 mW tot P output power - 50 mW o V electrostatic discharge HBM [1] - ±3000 V ESD voltage MM [2] - ±300 V I latch-up current [3] - 100 mA lu T storage temperature [4] −65 +150 °C stg T ambient temperature operating device −40 +85 °C amb [1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”. [2] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”. [3] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (T ). amb(max) [4] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be stored at a temperature of +8°C to +45°C and a humidity of 25% to 75%. For long term storage products deviant conditions are described in that document. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 18 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 10. Characteristics 10.1 Static characteristics Table 7. Static charac teristics V = 2.5 Vto 6.0 V; V = 0 V; T = −40 °C to +85 °C unless otherwise specified. DD SS amb Symbol Parameter Conditions Min Typ[1] Max Unit V supply voltage operating mode DD I2C-bus active 2.5 - 6.0 V I2C-bus inactive 1.0 - 6.0 V quartz oscillator T = 0 °C to +70 °C [2] 1.0 - 6.0 V amb T = −40 °C to +85 °C [2] 1.2 - 6.0 V amb I supply current operating mode DD f = 100 kHz clock mode [3] - - 200 μA SCL clock mode; f = 0 Hz SCL V = 2.0 V - 1.0 8.0 μA DD V = 5.0 V - 4 15 μA DD Pin SDA, SCL and INT V LOW-level input voltage 0 - 0.3V V IL DD V HIGH-level input voltage 0.7V - V V IH DD DD I LOW-level output current V =0.4V 3 - - mA OL OL I input leakage current V = V or V −1 - +1 μA LI I DD SS C input capacitance [4] - - 7 pF I Pins OSCI and RESET I input leakage current V = V or V −250 - +250 nA LI I DD SS Pin INT I LOW-level output current V = 0.4 V 1 - - mA OL OL I input leakage current V = V or V −1 - +1 μA LI I DD SS Pin SCL I input leakage current V = V or V −1 - +1 μA LI I DD SS C input capacitance [4] - - 7 pF I [1] Typical values measured at Tamb = 25 °C. [2] When the device is powered on, V must exceed the specified minimum value by 300mV to guarantee correct start-up of the DD oscillator. [3] Event counter mode: supply current dependant upon input frequency. [4] Tested on a sample basis. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 19 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 001aam493 8 lDD (μA) 6 4 2 0 0 2 4 6 VDD (V) fSCL = 32 kHz; Tamb = 25 °C Fig 21. Typical supply current in clock mode as a function of supply voltage PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 20 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 10.2 Dynamic characteristics Table 8. Dynamic cha racteristics V = 2.5 V to 6.0 V; V = 0 V; T = −40 °C to +85 °C unless otherwise specified. DD SS amb Symbol Parameter Conditions Min Typ Max Unit Oscillator C capacitance on pin OSCO 20 25 30 pF OSCO Δf /f relative oscillator frequency for ΔV = 100 mV; T =25°C; - 0.2 - ppm osc osc DD amb variation V = 1.5 V DD f external clock frequency [1] - - 1 MHz clk(ext) Quartz crystal parameters (f = 32.768 kHz) R series resistance - - 40 kΩ S C parallel load capacitance - 10 - pF L C trimmer capacitance 5 - 25 pF trim I2C-bus timing (see Figure21)[2] f SCL clock frequency - - 100 kHz SCL t pulse width of spikes that - - 100 ns SP must be suppressed by the input filter t bus free time between a 4.7 - - μs BUF STOP and START condition t set-up time for a repeated 4.7 - - μs SU;STA START condition t hold time (repeated) START 4.0 - - μs HD;STA condition t LOW period of the SCL clock 4.7 - - μs LOW t HIGH period of the SCL clock 4.0 - - μs HIGH t rise time of both SDA and - - 1.0 μs r SCL signals t fall time of both SDA and SCL - - 0.3 μs f signals t data set-up time 250 - - ns SU;DAT t data hold time 0 - - ns HD;DAT t data valid time - - 3.4 μs VD;DAT t set-up time for STOP 4.0 - - μs SU;STO condition [1] Event counter mode only. [2] All timing values are valid within the operating supply voltage, ambient temperature range, reference to V and V and with an input IL IH voltage swing of V to V . SS DD PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 21 of 35

PCF8593 NXP Semiconductors Low power clock and calendar START BIT 7 BIT 6 BIT 0 ACKNOWLEDGE STOP PROTOCOL CONDITION MSB (A6) LSB (A) CONDITION (S) (A7) (R/W) (P) tSU;STA tLOW tHIGH 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO mbd820 Fig 22. I2C-bus timing diagram; rise and fall times refer to V and V IL IH PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 22 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 11. Application information 11.1 Oscillator frequency adjustment 11.1.1 Method 1: Fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. The frequency is best measured via the 1Hz signal which can be programmed to occur at the interrupt output (pin 7). The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ±5×10−6). Average deviations of ±5 minutes per year can be achieved. 11.1.2 Method 2: OSCI trimmer Using the alarm function (via the I2C-bus) a signal faster than the 1 Hz is generated at the interrupt output for fast setting of a trimmer. Procedure: • Power the device on • Apply RESET. Routine: • Set clock to time t and set alarm to time t + Δt • at time t + Δt (interrupt) repeat routine. 11.1.3 Method 3: Direct measurement Direct measurement of oscillator output (allowing for test probe capacitance). PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 23 of 35

PCF8593 NXP Semiconductors Low power clock and calendar RESET VDD SDA RESET VDD MASTER TRANSMITTER/ 1 F RECEIVER SCL VSS VDD RESET SCL CLOCK/CALENDAR OSCI PCF8593 SDA OSCO VSS VDD R R R: pull-up resistor tr R = Cb SDA SCL (I2C-bus) 013aaa389 Fig 23. Application example PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 24 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 12. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 D ME e n a pl g n eati A2 A s L A1 c Z w M b1 e (e ) 1 MH b b2 8 5 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. mAi n1 . mAa 2x . b b1 b2 c D(1) E(1) e e1 L ME MH w mZa(1x). 1.73 0.53 1.07 0.36 9.8 6.48 3.60 8.25 10.0 mm 4.2 0.51 3.2 2.54 7.62 0.254 1.15 1.14 0.38 0.89 0.23 9.2 6.20 3.05 7.80 8.3 inches 0.17 0.02 0.13 0.068 0.021 0.042 0.014 0.39 0.26 0.1 0.3 0.14 0.32 0.39 0.01 0.045 0.045 0.015 0.035 0.009 0.36 0.24 0.12 0.31 0.33 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT97-1 050G01 MO-001 SC-504-8 03-02-13 Fig 24. Package outline SOT97-1 (DIP8) of PCF8593P PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 25 of 35

PCF8593 NXP Semiconductors Low power clock and calendar SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 8 5 Q A2 A1 (A 3 ) A pin 1 index θ Lp 1 4 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 5.0 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 4.8 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.20 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.19 0.15 0.228 0.016 0.024 0.012 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT96-1 076E03 MS-012 03-02-18 Fig 25. Package outline SOT96-1 (SO8) of PCF8593T PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 26 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 27 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure26) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table9 and10 Table 9. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 10. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure26. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 28 of 35

PCF8593 NXP Semiconductors Low power clock and calendar maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 29 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 14. Abbreviations Table 11. Abbreviations Acronym Description AM Ante Meridiem BCD Binary Coded Decimal CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model I2C Inter-Integrated Circuit bus IC Integrated Circuit LSB Least Significant Bit MM Machine Model MSB Most Significant Bit MSL Moisture Sensitivity Level MUX Multiplexer PCB Printed-Circuit Board PM Post Meridiem POR Power-On Reset PPM Parts Per Million RF Radio Frequency RAM Random Access Memory SCL Serial Clock Line SDA Serial DAta line SMD Surface-Mount Device PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 30 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 15. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [7] JESD78 — IC Latch-Up Test [8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [9] NX3-00092 — NXP store and transport requirements [10] SNV-FA-01-02 — Marking Formats Integrated Circuits [11] UM10204 — I2C-bus specification and user manual PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 31 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 16. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8593 v.4 20101006 Product data sheet - PCF8593_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. PCF8593_3 19970325 Product specification - PCF8593_2 PCF8593_2 19940829 Product specification - PCF8593_1 PCF8593_1 19940606 Product specification - - PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 32 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 17.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of Draft — The document is a draft version only. The content is still under NXP Semiconductors products in such equipment or applications and internal review and subject to formal approval, which may result in therefore such inclusion and/or use is at the customer’s own risk. modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these information included herein and shall have no liability for the consequences of products are for illustrative purposes only. NXP Semiconductors makes no use of such information. representation or warranty that such applications will be suitable for the specified use without further testing or modification. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended Customers are responsible for the design and operation of their applications for quick reference only and should not be relied upon to contain detailed and and products using NXP Semiconductors products, and NXP Semiconductors full information. For detailed and full information see the relevant full data accepts no liability for any assistance with applications or customer product sheet, which is available on request via the local NXP Semiconductors sales design. It is customer’s sole responsibility to determine whether the NXP office. In case of any inconsistency or conflict with the short data sheet, the Semiconductors product is suitable and fit for the customer’s applications and full data sheet shall prevail. products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate Product specification — The information and data provided in a Product design and operating safeguards to minimize the risks associated with their data sheet shall define the specification of the product as agreed between applications and products. NXP Semiconductors and its customer, unless NXP Semiconductors and NXP Semiconductors does not accept any liability related to any default, customer have explicitly agreed otherwise in writing. In no event however, damage, costs or problem which is based on any weakness or default in the shall an agreement be valid in which the NXP Semiconductors product is customer’s applications or products, or the application or use by customer’s deemed to offer functions and qualities beyond those described in the third party customer(s). Customer is responsible for doing all necessary Product data sheet. testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and 17.3 Disclaimers the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in be accurate and reliable. However, NXP Semiconductors does not give any the Absolute Maximum Ratings System of IEC60134) will cause permanent representations or warranties, expressed or implied, as to the accuracy or damage to the device. Limiting values are stress ratings only and (proper) completeness of such information and shall have no liability for the operation of the device at these or any other conditions above those given in consequences of use of such information. the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or In no event shall NXP Semiconductors be liable for any indirect, incidental, repeated exposure to limiting values will permanently and irreversibly affect punitive, special or consequential damages (including - without limitation - lost the quality and reliability of the device. profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such Terms and conditions of commercial sale — NXP Semiconductors damages are based on tort (including negligence), warranty, breach of products are sold subject to the general terms and conditions of commercial contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise Notwithstanding any damages that customer might incur for any reason agreed in a valid written individual agreement. In case an individual whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement is concluded only the terms and conditions of the respective customer for the products described herein shall be limited in accordance agreement shall apply. NXP Semiconductors hereby expressly objects to with the Terms and conditions of commercial sale of NXP Semiconductors. applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without No offer to sell or license — Nothing in this document may be interpreted or limitation specifications and product descriptions, at any time and without construed as an offer to sell products that is open for acceptance or the grant, notice. This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or to the publication hereof. other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior safety-critical systems or equipment, nor in applications where failure or authorization from national authorities. PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 33 of 35

PCF8593 NXP Semiconductors Low power clock and calendar Non-automotive qualified products — Unless this data sheet expressly own risk, and (c) customer fully indemnifies NXP Semiconductors for any states that this specific NXP Semiconductors product is automotive qualified, liability, damages or failed product claims resulting from customer design and the product is not suitable for automotive use. It is neither qualified nor tested use of the product for automotive applications beyond NXP Semiconductors’ in accordance with automotive testing or application requirements. NXP standard warranty and NXP Semiconductors’ product specifications. Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 17.4 Trademarks In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks (a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP B.V. NXP Semiconductors’ specifications such use shall be solely at customer’s 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF8593 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 6 October 2010 34 of 35

PCF8593 NXP Semiconductors Low power clock and calendar 19. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 30 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 15 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32 4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 17 Legal information . . . . . . . . . . . . . . . . . . . . . . 33 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 17.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 33 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 18 Contact information . . . . . . . . . . . . . . . . . . . . 34 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7.1 Counter function modes. . . . . . . . . . . . . . . . . . 4 19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 Alarm function modes. . . . . . . . . . . . . . . . . . . . 4 7.3 Control and status register . . . . . . . . . . . . . . . . 5 7.4 Counter registers . . . . . . . . . . . . . . . . . . . . . . . 6 7.5 Alarm control register. . . . . . . . . . . . . . . . . . . . 8 7.6 Alarm registers. . . . . . . . . . . . . . . . . . . . . . . . . 9 7.7 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.8 Event counter mode. . . . . . . . . . . . . . . . . . . . 11 7.9 Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 12 7.10 Oscillator and divider . . . . . . . . . . . . . . . . . . . 12 7.10.1 Designing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.11 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Characteristics of the I2C-bus . . . . . . . . . . . . 14 8.1 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.2 Start and stop conditions . . . . . . . . . . . . . . . . 14 8.1.3 System configuration . . . . . . . . . . . . . . . . . . . 14 8.1.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.2 Clock and calendar READ or WRITE cycles . 16 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 19 10.1 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 10.2 Dynamic characteristics . . . . . . . . . . . . . . . . . 21 11 Application information. . . . . . . . . . . . . . . . . . 23 11.1 Oscillator frequency adjustment. . . . . . . . . . . 23 11.1.1 Method 1: Fixed OSCI capacitor. . . . . . . . . . . 23 11.1.2 Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 23 11.1.3 Method 3: Direct measurement . . . . . . . . . . . 23 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 25 13 Soldering of SMD packages . . . . . . . . . . . . . . 27 13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 27 13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 27 13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 27 13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 28 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 October 2010 Document identifier: PCF8593

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: PCF8593P,112 PCF8593T/1,112 PCF8593T/1,118