PCF8563 Real-time clock/calendar Rev. 11 — 26 October 2015 Product data sheet 1. General description The PCF8563 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption. A programmable clock output, interrupt output, and voltage-low detector are also provided. All addresses and data are transferred serially via a two-line bidirectional I2C-bus. Maximum bus speed is 400kbit/s. The register address is incremented automatically after each written or read data byte. 2. Features and benefits  Provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768kHz quartz crystal  Century flag  Clock operating voltage: 1.0Vto5.5V at room temperature  Low backup current; typical 0.25Aat V =3.0V and T =25C DD amb  400kHz two-wire I2C-bus interface (at V =1.8Vto5.5V) DD  Programmable clock output for peripheral devices (32.768kHz, 1.024kHz, 32Hz,and 1Hz)  Alarm and timer functions  Integrated oscillator capacitor  Internal Power-On Reset (POR)  I2C-bus slave address: read A3h and write A2h  Open-drain interrupt pin 3. Applications  Mobile telephones  Portable instruments  Electronic metering  Battery powered products 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section18.

PCF8563 NXP Semiconductors Real-time clock/calendar 4. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF8563BS/4 HVSON10 plastic thermal enhanced very thin small outline SOT650-1 package; noleads; 10 terminals; body330.85mm PCF8563T/5 SO8 plastic small outline package; 8leads; SOT96-1 body width 3.9mm PCF8563T/F4[1] SO8 plastic small outline package; 8leads; SOT96-1 body width 3.9mm PCF8563TS/4[2] TSSOP8 plastic thin shrink small outline package; 8leads; SOT505-1 body width 3mm PCF8563TS/5 TSSOP8 plastic thin shrink small outline package; 8leads; SOT505-1 body width 3mm [1] Not recommended for new designs. Replacement part is PCF8563T/5. [2] Not recommended for new designs. Replacement part is PCF8563TS/5. 5. Marking Table 2. Marking codes Type number Marking code PCF8563BS/4 8563S PCF8563T/5 PCF8563 PCF8563T/F4 8563T PCF8563TS/4 8563 PCF8563TS/5 P8563 PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 2 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 6. Block diagram OSCI OSCILLATOR DIVIDER CLOCK OUT CLKOUT 32.768 kHz OSCO CONTROL MONITOR 00 CONTROL_STATUS_1 (1) 01 CONTROL_STATUS_2 0D CLKOUT_CONTROL POWER ON RESET TIME 02 VL_SECONDS 03 MINUTES VDD 04 HOURS 05 DAYS VSS 06 WEEKDAYS 07 CENTURY_MONTHS 08 YEARS WATCH DOG ALARM FUNCTION 09 MINUTE_ALARM 0A HOUR_ALARM SDA I2C-BUS 0B DAY_ALARM SCL INTERFACE 0C WEEKDAY_ALARM INTERRUPT INT TIMER FUNCTION 0E TIMER_CONTROL PCF8563 0F TIMER 001aah658 (1) C ; values see Table30. OSCO Fig 1. Block diagram of PCF8563 PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 3 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 7. Pinning information 7.1 Pinning terminal 1 index area OSCI 1 10 n.c. OSCO 2 9 VDD n.c. 3 PCF8563BS 8 CLKOUT OSCI 1 8 VDD INT 4 7 SCL OSCO 2 7 CLKOUT PCF8563T VSS 5 6 SDA INT 3 6 SCL 001aaf981 VSS 4 5 SDA Transparent top view 001aaf975 For mechanical details, see Figure29. Top view. For mechanical details, see Figure30. Fig 2. Pin configuration for HVSON10 Fig 3. Pin configuration for SO8 (PCF8563BS) (PCF8563T) OSCI 1 8 VDD OSCO 2 7 CLKOUT PCF8563TS INT 3 6 SCL VSS 4 5 SDA 001aaf976 Top view. For mechanical details, see Figure31. Fig 4. Pin configuration for TSSOP8 (PCF8563TS) PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 4 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 7.2 Pin description Table 3. Pin description Symbol Pin Description SO8, TSSOP8 HVSON10 OSCI 1 1 oscillator input OSCO 2 2 oscillator output INT 3 4 interrupt output (open-drain; active LOW) V 4 5[1] ground SS SDA 5 6 serial data input and output SCL 6 7 serial clock input CLKOUT 7 8 clock output, open-drain V 8 9 supply voltage DD n.c. - 3, 10 not connected; do not connect and do not use as feed through [1] The die paddle (exposed pad) is connected to V through high ohmic (non-conductive) silicon attach and SS should be electrically isolated. It is good engineering practice to solder the exposed pad to an electrically isolated PCB copper pad for better heat transfer but it is not required as the RTC doesn’t consume much power. In no case should traces be run under the package exposed pad. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 5 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 8. Functional description The PCF8563 contains sixteen 8-bit registers with an auto-incrementing register address, an on-chip 32.768kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real-Time Clock (RTC) and calender, a programmable clock output, a timer, an alarm, a voltage-low detector, and a 400kHz I2C-bus interface. All 16registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address00hand01h) are used as control and/or status registers. The memory addresses02h through08h are used as counters for the clock function (seconds up to years counters). Address locations09h through0Ch contain alarm registers which define the conditions for an alarm. Address0Dh controls the CLKOUT output frequency. 0Ehand0Fh are the Timer_control and Timer registers, respectively. The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm, Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is written or read, the contents of all time counters are frozen. Therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented. 8.1 CLKOUT output A programmable square wave is available at the CLKOUT pin. Operation is controlled by the register CLKOUT_control at address0Dh. Frequencies of 32.768kHz (default), 1.024kHz, 32Hz, and 1Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance. 8.2 Register organization Table 4. Formatted re gisters overview Bit positions labelled asx are not relevant. Bit positions labelled withN should always be written with logic0; if read they could be either logic0 or logic1. After reset, all registers are set according to Table27. Address Register name Bit 7 6 5 4 3 2 1 0 Control and status registers 00h Control_status_1 TEST1 N STOP N TESTC N N N 01h Control_status_2 N N N TI_TP AF TF AIE TIE Time and date registers 02h VL_seconds VL SECONDS (0 to 59) 03h Minutes x MINUTES (0 to 59) 04h Hours x x HOURS (0 to 23) 05h Days x x DAYS (1 to 31) 06h Weekdays x x x x x WEEKDAYS (0 to 6) 07h Century_months C x x MONTHS (1 to 12) 08h Years YEARS (0 to 99) PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 6 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Table 4. Formatted registers overview …continued Bit positions labelled asx are not relevant. Bit positions labelled withN should always be written with logic0; if read they could be either logic0 or logic1. After reset, all registers are set according to Table27. Address Register name Bit 7 6 5 4 3 2 1 0 Alarm registers 09h Minute_alarm AE_M MINUTE_ALARM (0 to 59) 0Ah Hour_alarm AE_H x HOUR_ALARM (0 to 23) 0Bh Day_alarm AE_D x DAY_ALARM (1 to 31) 0Ch Weekday_alarm AE_W x x x x WEEKDAY_ALARM (0 to 6) CLKOUT control register 0Dh CLKOUT_control FE x x x x x FD[1:0] Timer registers 0Eh Timer_control TE x x x x x TD[1:0] 0Fh Timer TIMER[7:0] 8.3 Control registers 8.3.1 Register Control_status_1 Table 5. Control_stat us_1 - control and status register 1 (address00h) bit description Bit Symbol Value Description Reference 7 TEST1 0[1] normal mode Section8.9 must be set to logic 0 during normal operations 1 EXT_CLK test mode 6 N 0[2] unused 5 STOP 0[1] RTC source clock runs Section8.10 1 all RTC divider chain flip-flops are asynchronously set to logic0; the RTC clock is stopped (CLKOUT at 32.768kHz is still available) 4 N 0[2] unused 3 TESTC 0 Power-On Reset (POR) override facility is disabled; set to logic0 for Section8.11.1 normal operation 1[1] Power-On Reset (POR) override may be enabled 2to0 N 000[2] unused [1] Default value. [2] Bits labeled as N should always be written with logic 0. 8.3.2 Register Control_status_2 Table 6. Control_stat us_2 - control and status register 2 (address01h) bit description Bit Symbol Value Description Reference 7to5 N 000[1] unused 4 TI_TP 0[2] INT is active whenTF is active (subject to the status of TIE) Section8.3.2.1 and 1 INT pulses active according to Table7 (subject to the status of TIE); Section8.8 Remark: note that if AFandAIE are active then INT will be permanently active PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 7 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Table 6. Control_status_2 - control and status register 2 (address01h) bit description …continued Bit Symbol Value Description Reference 3 AF 0[2] read: alarm flag inactive Section8.3.2.1 write: alarm flag is cleared 1 read: alarm flag active write: alarm flag remains unchanged 2 TF 0[2] read: timer flag inactive write: timer flag is cleared 1 read: timer flag active write: timer flag remains unchanged 1 AIE 0[2] alarm interrupt disabled 1 alarm interrupt enabled 0 TIE 0[2] timer interrupt disabled 1 timer interrupt enabled [1] Bits labeled as N should always be written with logic 0. [2] Default value. 8.3.2.1 Interrupt output BitsTF andAF: When an alarm occurs, AF is settologic 1. Similarly, at the end of a timer countdown, TFis settologic 1. These bits maintain their value until overwritten using the interface. If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access. TI_TP TE TF: TIMER to interface: TIE e.g. AIE read TF COUNTDOWN COUNTER SET 0 0 1 PULSE 1 CLEAR GENERATOR 2 TRIGGER CLEAR INT from interface: clear TF AIE AF: ALARM to interface: FLAG read AF set alarm SET flag AF CLEAR from interface: clear AF 013aaa087 When bits TIE and AIE are disabled, pin INT will remain high-impedance. Fig 5. Interrupt scheme BitsTIE andAIE: These bits activate or deactivate the generation of an interrupt when TForAF is asserted, respectively. The interrupt is the logicalOR of these two conditions when both AIE and TIE are set. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 8 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies (see Table7). Table 7. INT operation (bitTI_TP=1)[1] Source clock (Hz) INT period(s) n=1[2] n>1[2] 4096 1⁄ 1⁄ 8192 4096 64 1⁄ 1⁄ 128 64 1 1⁄ 1⁄ 64 64 1⁄ 1⁄ 1⁄ 60 64 64 [1] TFandINT become active simultaneously. [2] n=loaded countdown value. Timer stops when n=0. 8.4 Time and date registers The majority of the registers are coded in the BCD format to simplify application use. 8.4.1 Register VL_seconds Table 8. VL_seconds - seconds and clock integrity status register (address02h) bit description Bit Symbol Value Place value Description 7 VL 0 - clock integrity is guaranteed 1[1] - integrity of the clock information is not guaranteed 6to4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format, see Table9 3 to 0 0to9 unit place [1] Start-up value. Table 9. Seconds coded in BCD format Seconds value Upper-digit (ten’s place) Digit (unit place) (decimal) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 9 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 8.4.1.1 Voltage-low detector and clock monitor The PCF8563 has an on-chip voltage-low detector (see Figure6). When V drops below DD V , bitVL in the VL_seconds register is set to indicate that the integrity of the clock low information is no longer guaranteed. The VLflag can only be cleared by using the interface. mgr887 VDD normal power operation period of battery operation Vlow t VL set Fig 6. Voltage-low detection TheVL flag is intended to detect the situation when V is decreasing slowly, for example DD under battery operation. Should the oscillator stop or V reach V before power is DD low re-asserted, then theVL flag is set. This will indicate that the time may be corrupted. 8.4.2 Register Minutes Table 10. Minutes - minutes register (address03h) bit description Bit Symbol Value Place value Description 7 - - - unused 6to4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 3 to 0 0to9 unit place 8.4.3 Register Hours Table 11. Hours - hours register (address04h) bit description Bit Symbol Value Place value Description 7 to 6 - - - unused 5to4 HOURS 0to2 ten’s place actual hours coded in BCD format 3to0 0to9 unit place 8.4.4 Register Days Table 12. Days - days register (address05h) bit description Bit Symbol Value Place value Description 7 to 6 - - - unused 5to4 DAYS[1] 0to3 ten’s place actual day coded in BCD format 3to0 0to9 unit place [1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by4, including the year00. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 10 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 8.4.5 Register Weekdays Table 13. Weekdays - weekdays register (address06h) bit description Bit Symbol Value Description 7 to 3 - - unused 2to0 WEEKDAYS 0to6 actual weekday values, seeTable14 Table 14. Weekday assignments Day[1] Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] Definition may be re-assigned by the user. 8.4.6 Register Century_months Table 15. Century_months - century flag and months register (address07h) bit description Bit Symbol Value Place value Description 7 C[1] 0[2] - indicates the century isx 1 - indicates the century isx+1 6 to 5 - - - unused 4 MONTHS 0to 1 ten’s place actual month coded in BCD format, see Table16 3 to 0 0 to 9 unit place [1] This bit may be re-assigned by the user. [2] This bit is toggled when the register Years overflows from 99 to 00. Table 16. Month assignmentsin BCD format Month Upper-digit Digit (unit place) (ten’s place) Bit4 Bit3 Bit2 Bit1 Bit0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 11 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Table 16. Month assignments …continuedin BCD format Month Upper-digit Digit (unit place) (ten’s place) Bit4 Bit3 Bit2 Bit1 Bit0 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 8.4.7 Register Years Table 17. Years - years register (08h) bit description Bit Symbol Value Place value Description 7to4 YEARS 0to9 ten’s place actual year coded in BCD format[1] 3to0 0to9 unit place [1] When the register Years overflows from 99 to 00, the century bit C in the register Century_months is toggled. 8.5 Setting and reading the time Figure7 shows the data flow and data dependencies starting from the 1 Hz clock tick. 1 Hz tick SECONDS MINUTES HOURS LEAP Y EAR CALCULATION DAYS WEEKDAY MONTHS YEARS C 013aaa092 Fig 7. Data flow for the time function During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers, during the read cycle PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 12 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure8). t < 1 s START SLAVE ADDRESS DATA DATA STOP 013aaa215 Fig 8. Access time for read/write operations As a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted. As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. A similar problem exists when reading. A roll over may occur between reads thus giving the minutes from one moment and the hours from the next. Recommended method for reading the time: 1. Send a START condition and the slave address for write (A2h). 2. Set the address pointer to 2 (VL_seconds) by sending 02h. 3. Send a RESTART condition or STOP followed by START. 4. Send the slave address for read (A3h). 5. Read VL_seconds. 6. Read Minutes. 7. Read Hours. 8. Read Days. 9. Read Weekdays. 10. Read Century_months. 11. Read Years. 12. Send a STOP condition. 8.6 Alarm registers 8.6.1 Register Minute_alarm Table 18. Minute_alarm - minute alarm register (address09h) bit description Bit Symbol Value Place value Description 7 AE_M 0 - minute alarm is enabled 1[1] - minute alarm is disabled 6to4 MINUTE_ALARM 0to5 ten’s place minute alarm information coded in BCD format 3 to 0 0 to 9 unit place PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 13 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar [1] Default value. 8.6.2 Register Hour_alarm Table 19. Hour_alarm - hour alarm register (address0Ah) bit description Bit Symbol Value Place value Description 7 AE_H 0 - hour alarm is enabled 1[1] - hour alarm is disabled 6 - - - unused 5to4 HOUR_ALARM 0to2 ten’s place hour alarm information coded in BCD format 3 to 0 0 to 9 unit place [1] Default value. 8.6.3 Register Day_alarm Table 20. Day_alarm - day alarm register (address0Bh) bit description Bit Symbol Value Place value Description 7 AE_D 0 - day alarm is enabled 1[1] - day alarm is disabled 6 - - - unused 5to4 DAY_ALARM 0to3 ten’s place day alarm information coded in BCD format 3 to 0 0 to 9 unit place [1] Default value. 8.6.4 Register Weekday_alarm Table 21. Weekday_alarm - weekday alarm register (address0Ch) bit description Bit Symbol Value Description 7 AE_W 0 weekday alarm is enabled 1[1] weekday alarm is disabled 6 to 3 - - unused 2to0 WEEKDAY_ALARM 0to6 weekday alarm information [1] Default value. 8.6.5 Alarm flag By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1. The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the interface. The registers at addresses 09h through 0Ch contain alarm information. When one or more of these registers is loaded with minute, hour, day or weekday, and its corresponding AE_x is logic 0, then that information is compared with the current minute, hour, day, and weekday. When all enabled comparisons first match, the alarm flag (AF in register Control_2) is set to logic 1. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 14 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the INT pin follows the condition of bit AF. AF will remain set until cleared by the interface. Once AF has been cleared, it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their AE_x bit at logic 1 are ignored. check now signal example AEN_M AEN_M = 1 MINUTE ALARM = 1 MINUTE TIME 0 AEN_H HOUR ALARM = HOUR TIME set alarm flag AF(1) AEN_D DAY ALARM = DAY TIME AEN_W WEEKDAY ALARM = 013aaa088 WEEKDAY TIME (1) Only when all enabled alarm settings are matching. It’s only on increment to a matched case that the alarm flag is set, see Section8.6.5. Fig 9. Alarm function block diagram 8.7 Register CLKOUT_control and clock output Frequencies of 32.768kHz (default), 1.024kHz, 32Hz, and 1Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Table 22. CLKOUT_control - CLKOUT control register (address0Dh) bit description Bit Symbol Value Description 7 FE 0 the CLKOUT output is inhibited and CLKOUT output is set high-impedance 1[1] the CLKOUT output is activated 6 to 2 - - unused 1to0 FD[1:0] frequency output at pinCLKOUT 00[1] 32.768kHz 01 1.024kHz 10 32Hz 11 1Hz [1] Default value. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 15 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 8.8 Timer function The 8-bit countdown timer at address0Fh is controlled by the Timer_control register at address0Eh. The Timer_control register determines one of 4source clock frequencies for the timer (4096Hz,64Hz,1Hz, or 1⁄ Hz), and enables or disables the timer. The timer 60 counts down from a software-loaded 8-bit binary value. At the end of every countdown, the timer sets the timer flag TF. TheTF may only be cleared by using the interface. The assertedTF can be used to generate an interrupt on pin INT. The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the state ofTF. BitTI_TP is used to control this mode selection. When reading the timer, the current countdown value is returned. 8.8.1 Register Timer_control Table 23. Timer_control - timer control register (address0Eh) bit description Bit Symbol Value Description 7 TE 0[1] timer is disabled 1 timer is enabled 6 to 2 - - unused 1to0 TD[1:0] timer source clock frequency select[2] 00 4.096kHz 01 64Hz 10 1Hz 11[2] 1⁄ Hz 60 [1] Default value. [2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to 1⁄ Hz for power saving. 60 8.8.2 Register Timer Table 24. Timer - timer value register (address0Fh) bit description Bit Symbol Value Description 7to0 TIMER[7:0] 00htoFFh countdown period in seconds: n CountdownPeriod = --------------------------------------------------------------- SourceClockFrequency where n is the countdown value T able 25. Timer register bits value range Bit 7 6 5 4 3 2 1 0 128 64 32 16 8 4 2 1 The register Timer is an 8-bit binary countdown timer. It is enabled and disabled via the Timer_control register bitTE. The source clock for the timer is also selected by the Timer_control register. Other timer properties such as interrupt generation are controlled via the register Control_status_2. For accurate read back of the count down value, it is recommended to read the register twice and check for consistent results, since it is not possible to freeze the countdown timer counter during read back. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 16 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 8.9 EXT_CLK test mode A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bitTEST1 in register Control_status_1. Then pinCLKOUT becomes an input. The test mode replaces the internal 64Hz signal with the signal applied to pinCLKOUT. Every64 positive edges applied to pinCLKOUT will then generate an increment of one second. The signal applied to pinCLKOUT should have a minimum pulse width of 300ns and a maximum period of 1000ns. The internal 64Hz clock, now sourced from CLKOUT, is divided down to 1Hz by a 26divide chain called a prescaler. The prescaler can be set into a known state by using bitSTOP. When bitSTOP is set, the prescaler is reset to0 (STOP must be cleared before the prescaler can operate again). From a STOP condition, the first 1second increment will take place after 32positive edges on CLKOUT. Thereafter, every 64positive edges will cause a one-second increment. Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. 8.9.1 Operation example: 1. Set EXT_CLK test mode (Control_status_1, bitTEST1=1). 2. Set STOP (Control_status_1, bitSTOP=1). 3. Clear STOP (Control_status_1, bitSTOP=0). 4. Set time registers to desired value. 5. Apply 32clock pulses to CLKOUT. 6. Read time registers to see the first change. 7. Apply 64clock pulses to CLKOUT. 8. Read time registers to see the second change. Repeat steps 7and8 for additional increments. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 17 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 8.10 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler (F to F ) to be held in reset and 2 14 thus no 1Hz ticks will be generated (see Figure10). The time circuits can then be set and will not increment until the STOP bit is released (see Figure11 and Table26). OSCILLATOR STOP reset DETECTOR z z H H z z 32768 F0 16384 F1 8192 H F2 4096 H F13 2 Hz F14 OSCILLATOR 1 Hz tick RESET RESET RESET STOP 1 Hz 32 Hz CLKOUT source 1024 Hz 32768 Hz 013aaa089 Fig 10. STOP bit functional diagram The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop the generation of 1.024kHz, 32Hz, and 1Hz. The lower two stages of the prescaler (F and F ) are not reset; and because the I2C-bus 0 1 is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between zero and one 8.192 kHz cycle (see Figure11). 8192 Hz stop released 0 μs to 122 μs 001aaf912 Fig 11. STOP bit release timing PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 18 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Table 26. First increme nt of time circuits after STOP bit release Bit Prescaler bits [1] 1Hz tick Time Comment STOP F F -F to F hh:mm:ss 0 1 2 14 Clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally STOP bit is activated by user. F F are not reset and values cannot be predicted externally 0 1 1 XX-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen New time is set by user 1 XX-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen STOP bit is released by user 0 XX-0 0000 0000 0000 08:00:00 prescaler is now running s XX-1 0000 0000 0000 5 08:00:00 - 3 9 7 XX-0 1000 0000 0000 0 08:00:00 - 5 0. XX-1 1000 0000 0000 o 08:00:00 - 3 t : 81 : : 7 0 11-1 1111 1111 1110 0.5 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of F14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : : : s 11-1 1111 1111 1111 00 08:00:01 - 0 0 00-0 0000 0000 0000 0 08:00:01 - 0 1. 10-0 0000 0000 0000 08:00:01 - : : : 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of F14 increments the time circuits 013aaa076 [1] F is clocked at 32.768 kHz. 0 The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The uncertainty is caused by the prescaler bits F and F not being reset 0 1 (see Table26) and the unknown state of the 32kHz clock. 8.11 Reset The PCF8563 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I2C-bus logic is initialized including the address pointer and all registers are set according to Table27. I2C-bus communication is not possible during reset. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 19 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Table 27. Register reset value[1] Address Register name Bit 7 6 5 4 3 2 1 0 00h Control_status_1 0 0 0 0 1 0 0 0 01h Control_status_2 0 0 0 0 0 0 0 0 02h VL_seconds 1 x x x x x x x 03h Minutes x x x x x x x x 04h Hours x x x x x x x x 05h Days x x x x x x x x 06h Weekdays x x x x x x x x 07h Century_months x x x x x x x x 08h Years x x x x x x x x 09h Minute_alarm 1 x x x x x x x 0Ah Hour_alarm 1 x x x x x x x 0Bh Day_alarm 1 x x x x x x x 0Ch Weekday_alarm 1 x x x x x x x 0Dh CLKOUT_control 1 x x x x x 0 0 0Eh Timer_control 0 x x x x x 1 1 0Fh Timer x x x x x x x x [1] Registers marked x are undefined at power-up and unchanged by subsequent resets. 8.11.1 Power-On Reset (POR) override The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I2C-bus pins, SDA and SCL, are toggled in a specific order as shown in Figure12. All timings are required minimums. Once the override mode has been entered, the device immediately stops, being reset, and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus access. The override mode may be cleared by writing logic0 to TESTC. TESTC must be set to logic1 before re-entry into the override mode is possible. Setting TESTC to logic0 during normal operation has no effect except to prevent entry into the POR override mode. 500 ns 2000 ns SDA SCL 8 ms power-on override active mgm664 Fig 12. POR override sequence PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 20 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 9. Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure13). SDA SCL data line change stable; of data data valid allowed mbc621 Fig 13. Bit transfer 9.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. ALOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure14). SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 14. Definition of START and STOP conditions 9.3 System configuration A device generating a message is a transmitter; a device receiving a message is a receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves (see Figure15). PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 21 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar SDA SCL MASTER SLAVE SLAVE MASTER MASTER TRANSMITTER RECEIVER TRANSMITTER TRANSMITTER TRANSMITTER RECEIVER RECEIVER RECEIVER mba605 Fig 15. System configuration 9.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure16. data output by transmitter not acknowledge data output by receiver acknowledge SCL from 1 2 8 9 master S clock pulse for START acknowledgement condition mbc602 Fig 16. Acknowledgement on the I2C-bus PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 22 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 9.5 I2C-bus protocol 9.5.1 Addressing Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. Two slave addresses are reserved for the PCF8563: Read: A3h (10100011) Write: A2h (10100010) The PCF8563 slave address is illustrated in Figure17. 1 0 1 0 0 0 1 R/W group 1 group 2 mce189 Fig 17. Slave address 9.5.2 Clock and calendar READ or WRITE cycles The I2C-bus configuration for the different PCF8563 READ and WRITE cycles is shown in Figure18, Figure19 and Figure20. The register address is a 4-bit value that defines which register is to be accessed next. The upper four bits of the register address are not used. acknowledgement acknowledgement acknowledgement from slave from slave from slave S SLAVE ADDRESS 0 A REGISTER ADDRESS A DATA A P R/W n bytes auto increment memory register address 013aaa346 Fig 18. Master transmits to slave receiver (WRITE mode) PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 23 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar acknowledgement acknowledgement acknowledgement acknowledgement from slave from slave from slave from master S SLAVE ADDRESS 0 A REGISTER ADDRESS A S SLAVE ADDRESS 1 A DATA A n bytes R/W R/W auto increment memory register address (1) no acknowledgement from master DATA 1 P last byte auto increment memory register address 013aaa041 (1) At this moment master transmitter becomes master receiver and PCF8563 slave receiver becomes slave transmitter. Fig 19. Master reads after setting register address (write register address; READ data) acknowledgement acknowledgement no acknowledgement from slave from master from master S SLAVE ADDRESS 1 A DATA A DATA 1 P R/W n bytes last byte auto increment auto increment register address register address 013aaa347 Fig 20. Master reads slave immediately after first byte (READ mode) PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 24 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 9.6 Interface watchdog timer t < 1 s data START SLAVE ADDRESS DATA DATA STOP WD timer WD timer tracking time running time counters frozen running counters 013aaa420 a. Correct data transfer: read or write 1 s < t < 2 s data transfer fail data START SLAVE ADDRESS DATA DATA WD timer WD timer tracking WD trips time running time counters frozen running counters 013aaa421 b. Incorrect data transfer; read or write Fig 21. Interface watchdog timer During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface, the PCF8563 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid slave address is transmitted, then the PCF8563 will automatically clear the interface and allow the time counting circuits to continue counting. The watchdog will trigger between 1 s and 2 s after receiving a valid slave address. Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 25 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 10. Internal circuitry OSCI VDD OSCO CLKOUT INT SCL VSS SDA PCF8563 013aaa348 Fig 22. Device diode protection diagram PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 26 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 11. Limiting values Table 28. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +6.5 V DD I supply current 50 +50 mA DD V input voltage on pinsSCL,SDA, 0.5 +6.5 V I and OSCI V output voltage on pinsCLKOUT andINT 0.5 +6.5 V O I input current at any input 10 +10 mA I I output current at any output 10 +10 mA O P total power dissipation - 300 mW tot V electrostatic discharge voltage HBM ESD HVSON10 (PCF8563BS/4) [1] - 3500 V SO8 (PCF8563T/F4) [1] TSSOP8 (PCF8563TS/4) [1] SO8 (PCF8563T/5) [1] - 2000 V TSSOP8 (PCF8563TS/5) [1] - CDM - HVSON10 (PCF8563BS/4) [2] - 2000 V - SO8 (PCF8563T/F4) [2] 1000 V - SO8 (PCF8563T/5) [2] 1500 V TSSOP8 (PCF8563TS/4) [2] 1500 V TSSOP8 (PCF8563TS/5) [2] 1750 V I latch-up current [3] - 200 mA lu T storage temperature [4] 65 +150 C stg T ambient temperature operating device 40 +85 C amb [1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”. [2] Pass level; Charged-Device Model (CDM), according to Ref. 6 “JESD22-C101”. [3] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (T ). amb(max) [4] According to the NXP store and transport requirements (see Ref. 9 “UM10569”) the devices should be stored at a temperature of +8C to +45C and a humidity of 25% to 75%. For long term storage products deviant conditions are described in that document. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 27 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 12. Static characteristics Table 29. Static charac teristics V =1.8V to 5.5V; V =0V; T =40C to +85C; f =32.768kHz; quartz R =40k; C =8pF; unless otherwise DD SS amb osc s L specified. Symbol Parameter Conditions Min Typ Max Unit Supplies V supply voltage interface inactive; [1] 1.0 - 5.5 V DD f =0Hz; SCL T =25C amb interface active; 1.8 - 5.5 V f =400kHz SCL clock data integrity; V - 5.5 V low T =25C amb I supply current interface active DD f =400kHz - - 800 A SCL f =100kHz - - 200 A SCL interface inactive (f =0Hz); CLKOUT [2] SCL disabled; T =25C amb V =5.0V - 275 550 nA DD V =3.0V - 250 500 nA DD V =2.0V - 225 450 nA DD interface inactive (f =0Hz); CLKOUT [2] SCL disabled; T =40Cto +85C amb V =5.0V - 500 750 nA DD V =3.0V - 400 650 nA DD V =2.0V - 400 600 nA DD interface inactive (f =0Hz); CLKOUT [2] SCL enabled at 32kHz; T =25C amb V =5.0V - 825 1600 nA DD V =3.0V - 550 1000 nA DD V =2.0V - 425 800 nA DD interface inactive (f =0Hz); CLKOUT [2] SCL enabled at 32kHz; T =40Cto +85C amb V =5.0V - 950 1700 nA DD V =3.0V - 650 1100 nA DD V =2.0V - 500 900 nA DD Inputs V LOW-level input 0.5 - +0.3V V IL DD voltage V HIGH-level 0.7V - 5.5 V IH DD input voltage I input leakage V =V or V 1 0 +1 A LI I DD SS current C input [3] - - 7 pF i capacitance PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 28 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Table 29. Static characteristics …continued V =1.8V to 5.5V; V =0V; T =40C to +85C; f =32.768kHz; quartz R =40k; C =8pF; unless otherwise DD SS amb osc s L specified. Symbol Parameter Conditions Min Typ Max Unit Outputs I LOW-level output sink current; OL output current V =0.4V; V =5V OL DD on pin SDA 3 - - mA on pin INT 1 - - mA on pin CLKOUT 1 - - mA I output leakage V =V or V 1 0 +1 A LO O DD SS current Voltage detector V low voltage T =25C; sets bit VL; see Figure6 - 0.9 1.0 V low amb [1] For reliable oscillator start-up at power on use V greater than 1.3V. If powered up at 1.0V the oscillator will start but it might be a bit DD slow, especially if at high temperature. Normally the power supply is not 1.0V at start up and only comes at the end of battery discharge. V min of 1.0V is specified so that the customer can calculate how large a battery or capacitor they need for their application. V min DD DD of 1.3V or greater is needed to ensure speedy oscillator start-up time. [2] Timer source clock=1⁄60Hz, level of pinsSCL andSDA is VDD or VSS. [3] Tested on sample basis. mgr888 mgr889 1 1 IDD IDD (μA) (μA) 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 0 2 4 6 0 2 4 6 VDD (V) VDD (V) Tamb=25C; Timer=1minute. Tamb=25C; Timer=1minute. Fig 23. Supply current I as a function of supply Fig 24. Supply current I as a function of supply DD DD voltage V ; CLKOUT disabled voltage V ; CLKOUT=32kHz DD DD PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 29 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar mgr890 mgr891 1 IDD (μA) 4 frequency 0.8 deviation (ppm) 2 0.6 0 0.4 −2 0.2 −4 0 −40 0 40 80 T (°C) 120 0 2 4 VDD (V) 6 VDD=3V; Timer=1minute. Tamb=25C; normalized to VDD=3V. Fig 25. Supply current I as a function of Fig 26. Frequency deviation as a function of supply DD temperature T; CLKOUT=32kHz voltage V DD 13. Dynamic characteristics Table 30. Dynamic cha racteristics V =1.8V to 5.5V; V =0V; T =40C to +85C; f =32.768kHz; quartz R =40k; C =8pF; unless otherwise DD SS amb osc s L specified. Symbol Parameter Conditions Min Typ Max Unit Oscillator C capacitance on pin OSCO 15 25 35 pF OSCO f /f relative oscillator frequency variation V =200mV; - 0.2 - ppm osc osc DD T =25C amb Quartz crystal parameters (f=32.768kHz) R series resistance - - 100 k s C load capacitance parallel [1] 7 - 12.5 pF L C trimmer capacitance external; 5 - 25 pF trim on pin OSCI CLKOUT output  duty cycle on pin CLKOUT [2] - 50 - % CLKOUT I2C-bus timing characteristics (see Figure27)[3][4] f SCL clock frequency [5] - - 400 kHz SCL t hold time (repeated) START condition 0.6 - - s HD;STA t set-up time for a repeated START condition 0.6 - - s SU;STA t LOW period of the SCL clock 1.3 - - s LOW t HIGH period of the SCL clock 0.6 - - s HIGH t rise time of both SDA and SCL signals r standard-mode - - 1 s fast-mode - - 0.3 s PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 30 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Table 30. Dynamic characteristics …continued V =1.8V to 5.5V; V =0V; T =40C to +85C; f =32.768kHz; quartz R =40k; C =8pF; unless otherwise DD SS amb osc s L specified. Symbol Parameter Conditions Min Typ Max Unit t fall time of both SDA and SCL signals - - 0.3 s f t bus free time between a STOP and START 1.3 - - s BUF condition C capacitive load for each bus line - - 400 pF b t data set-up time 100 - - ns SU;DAT t data hold time 0 - - ns HD;DAT t set-up time for STOP condition 0.6 - - s SU;STO t spike pulse width on bus - - 50 ns w(spike) C C  [1] C is a calculation of C and C in series: C = --------t--r--i--m------------O---S---C----O-----. L trim OSCO L C +C  trim OSCO [2] Unspecified for fCLKOUT=32.768kHz. [3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to V and V with an input voltage IL IH swing of VSS to VDD. [4] A detailed description of the I2C-bus specification is given in Ref. 11 “UM10204”. [5] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second. SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 27. I2C-bus timing waveforms PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 31 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 14. Application information VDD SDA MASTER TRANSMITTER/ RECEIVER SCL 1 F 100 nF VDD SCL CLOCK CALENDAR OSCI PCF8563 OSCO VSS SDA VDD R R R: pull-up resistor tr R = Cb SDA SCL (I2C-bus) mgm665 Fig 28. Application diagram 14.1 Quartz frequency adjustment 14.1.1 Method 1: fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768kHz signal available after power-on at pinCLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5ppm). Average deviations of 5minutes per year can be easily achieved. 14.1.2 Method 2: OSCI trimmer Using the 32.768kHz signal available after power-on at pinCLKOUT, fast setting of a trimmer is possible. 14.1.3 Method 3: OSCO output Direct measurement of OSCO out (accounting for test probe capacitance). PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 32 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 15. Package outline HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.85 mm SOT650-1 0 1 2 mm scale X D B A A A1 E c detail X terminal 1 index area C terminal 1 e1 index area e b v M C A B y1 C y 1 5 w M C L Eh 10 6 Dh DIMENSIONS (mm are the original dimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 L v w y y1 0.05 0.30 3.1 2.55 3.1 1.75 0.55 mm 1 0.2 0.5 2 0.1 0.05 0.05 0.1 0.00 0.18 2.9 2.15 2.9 1.45 0.30 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 01-01-22 SOT650-1 - - - MO-229 - - - 02-02-08 Fig 29. Package outline SOT650-1 (HVSON10) of PCF8563BS PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 33 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 8 5 Q A2 A1 (A 3 ) A pin 1 index θ Lp 1 4 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 5.0 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 4.8 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.20 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.19 0.15 0.228 0.016 0.024 0.012 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT96-1 076E03 MS-012 03-02-18 Fig 30. Package outline SOT96-1 (SO8) of PCF8563T PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 34 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 D E A X c y HE v M A Z 8 5 A2 A1 (A3) A pin 1 index θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.95 0.25 0.45 0.28 3.1 3.1 0.65 5.1 0.94 0.7 0.1 0.1 0.1 0.70 6° 0.05 0.80 0.25 0.15 2.9 2.9 4.7 0.4 0.35 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-04-09 SOT505-1 03-02-18 Fig 31. Package outline SOT505-1 (TSSOP8) of PCF8563TS PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 35 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 36 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 17.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure32) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table31 and32 Table 31. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 32. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure32. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 37 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 33. Abbreviations Acronym Description BCD Binary Coded Decimal CDM Charged-Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit LSB Least Significant Bit MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board POR Power-On Reset RTC Real-Time Clock SCL Serial CLock line SDA Serial DAta line SMD Surface Mount Device PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 38 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 19. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [6] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [7] JESD78 — IC Latch-Up Test [8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [9] UM10569 — NXP store and transport requirements [10] SNV-FA-01-02 — Marking Formats Integrated Circuits [11] UM10204 — I2C-bus specification and user manual PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 39 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 20. Revision history Table 34. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8563 v.11 20151026 Product data sheet - PCF8563 v.10 Modifications: • Removed DIP8 package • Table3: Corrected Table note1 • Table28, Table note4: Corrected “the devices have to be stored” to “the devices should be stored” • Table29: – Deleted Table note1 from V f = 400 kHz DD SCL – V : Corrected V to 0.5 IL SS – V : Corrected V to 5.5 IH DD – Corrected Table note1 PCF8563 v.10 20120403 Product data sheet - PCF8563 v.9 Modifications: • Adjusted marking codes • Adjusted text for FE = 0 in Table22 PCF8563 v.9 20110616 Product data sheet - PCF8563 v.8 PCF8563 v.8 20101118 Product data sheet - PCF8563 v.7 PCF8563 v.7 20100723 Product data sheet - PCF8563_6 PCF8563_6 20080221 Product data sheet - PCF8563_5 PCF8563_5 20070717 Product data sheet - PCF8563-04 PCF8563-04 20040312 Product data - PCF8563-03 (939775012999) PCF8563-03 20030414 Product data - PCF8563-02 (939775011158) PCF8563-02 19990416 Product data - PCF8563_N_1 (939775004855) PCF8563_N_1 19980325 Objective specification - - (939775003282) PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 40 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 21.2 Definitions Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Draft — The document is a draft version only. The content is still under malfunction of an NXP Semiconductors product can reasonably be expected internal review and subject to formal approval, which may result in to result in personal injury, death or severe property or environmental modifications or additions. NXP Semiconductors does not give any damage. NXP Semiconductors and its suppliers accept no liability for representations or warranties as to the accuracy or completeness of inclusion and/or use of NXP Semiconductors products in such equipment or information included herein and shall have no liability for the consequences of applications and therefore such inclusion and/or use is at the customer’s own use of such information. risk. Short data sheet — A short data sheet is an extract from a full data sheet Applications — Applications that are described herein for any of these with the same product type number(s) and title. A short data sheet is intended products are for illustrative purposes only. NXP Semiconductors makes no for quick reference only and should not be relied upon to contain detailed and representation or warranty that such applications will be suitable for the full information. For detailed and full information see the relevant full data specified use without further testing or modification. sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their deemed to offer functions and qualities beyond those described in the applications and products. Product data sheet. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the 21.3 Disclaimers customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Limited warranty and liability — Information in this document is believed to Semiconductors products in order to avoid a default of the applications and be accurate and reliable. However, NXP Semiconductors does not give any the products or of the application or use by customer’s third party representations or warranties, expressed or implied, as to the accuracy or customer(s). NXP does not accept any liability in this respect. completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC60134) will cause permanent source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in In no event shall NXP Semiconductors be liable for any indirect, incidental, the Recommended operating conditions section (if present) or the punitive, special or consequential damages (including - without limitation - lost Characteristics sections of this document is not warranted. Constant or profits, lost savings, business interruption, costs related to the removal or repeated exposure to limiting values will permanently and irreversibly affect replacement of any products or rework charges) whether or not such the quality and reliability of the device. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of NXP Semiconductors products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 41 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar Export control — This document as well as the item(s) described herein own risk, and (c) customer fully indemnifies NXP Semiconductors for any may be subject to export control regulations. Export might require a prior liability, damages or failed product claims resulting from customer design and authorization from competent authorities. use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, Translations — A non-English (translated) version of a document is for the product is not suitable for automotive use. It is neither qualified nor tested reference only. The English version shall prevail in case of any discrepancy in accordance with automotive testing or application requirements. NXP between the translated and English versions. Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 21.4 Trademarks In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks (a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP Semiconductors N.V. NXP Semiconductors’ specifications such use shall be solely at customer’s 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 42 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 23. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4. Formatted registers overview . . . . . . . . . . . . . .6 Table 5. Control_status_1 - control and status register 1 (address00h) bit description . . . . . . . . . . . . . . .7 Table 6. Control_status_2 - control and status register 2 (address01h) bit description . . . . . . . . . . . . . . .7 Table 7. INT operation (bitTI_TP=1)[1]. . . . . . . . . . . . . .9 Table 8. VL_seconds - seconds and clock integrity status register (address02h) bit description . . . . . . . .9 Table 9. Seconds coded in BCD format . . . . . . . . . . . . .9 Table 10. Minutes - minutes register (address03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 11. Hours - hours register (address04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 12. Days - days register (address05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 13. Weekdays - weekdays register (address06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 14. Weekday assignments. . . . . . . . . . . . . . . . . . .11 Table 15. Century_months - century flag and months register (address07h) bit description. . . . . . . .11 Table 16. Month assignmentsin BCD format. . . . . . . . . .11 Table 17. Years - years register (08h) bit description. . . .12 Table 18. Minute_alarm - minute alarm register (address09h) bit description . . . . . . . . . . . . . .13 Table 19. Hour_alarm - hour alarm register (address0Ah) bit description. . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 20. Day_alarm - day alarm register (address0Bh) bit description. . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 21. Weekday_alarm - weekday alarm register (address0Ch) bit description . . . . . . . . . . . . . .14 Table 22. CLKOUT_control - CLKOUT control register (address0Dh) bit description . . . . . . . . . . . . . .15 Table 23. Timer_control - timer control register (address0Eh) bit description . . . . . . . . . . . . . .16 Table 24. Timer - timer value register (address0Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 25. Timer register bits value range. . . . . . . . . . . . .16 Table 26. First increment of time circuits after STOP bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 27. Register reset value[1] . . . . . . . . . . . . . . . . . . .20 Table 28. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 29. Static characteristics . . . . . . . . . . . . . . . . . . . .28 Table 30. Dynamic characteristics. . . . . . . . . . . . . . . . . .30 Table 31. SnPb eutectic process (from J-STD-020D) . . .37 Table 32. Lead-free process (from J-STD-020D) . . . . . .37 Table 33. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 34. Revision history . . . . . . . . . . . . . . . . . . . . . . . .40 PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 43 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 24. Figures Fig 1. Block diagram of PCF8563 . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration for HVSON10 (PCF8563BS) . . .4 Fig 3. Pin configuration for SO8 (PCF8563T) . . . . . . . . .4 Fig 4. Pin configuration for TSSOP8 (PCF8563TS). . . . .4 Fig 5. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . .8 Fig 6. Voltage-low detection. . . . . . . . . . . . . . . . . . . . . .10 Fig 7. Data flow for the time function. . . . . . . . . . . . . . .12 Fig 8. Access time for read/write operations . . . . . . . . .13 Fig 9. Alarm function block diagram. . . . . . . . . . . . . . . .15 Fig 10. STOP bit functional diagram . . . . . . . . . . . . . . . .18 Fig 11. STOP bit release timing. . . . . . . . . . . . . . . . . . . .18 Fig 12. POR override sequence . . . . . . . . . . . . . . . . . . .20 Fig 13. Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Fig 14. Definition of START and STOP conditions. . . . . .21 Fig 15. System configuration. . . . . . . . . . . . . . . . . . . . . .22 Fig 16. Acknowledgement on the I2C-bus. . . . . . . . . . . .22 Fig 17. Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Fig 18. Master transmits to slave receiver (WRITE mode). . . . . . . . . . . . . . . . . . . . . . . . . . .23 Fig 19. Master reads after setting register address (write register address; READ data) . . . . . . . . . . . . . . .24 Fig 20. Master reads slave immediately after first byte (READ mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Fig 21. Interface watchdog timer. . . . . . . . . . . . . . . . . . .25 Fig 22. Device diode protection diagram. . . . . . . . . . . . .26 Fig 23. Supply current I as a function of supply voltage DD V ; CLKOUT disabled . . . . . . . . . . . . . . . . . . . .29 DD Fig 24. Supply current I as a function of supply voltage DD V ; CLKOUT=32kHz. . . . . . . . . . . . . . . . . . . .29 DD Fig 25. Supply current I as a function of temperature DD T; CLKOUT=32kHz. . . . . . . . . . . . . . . . . . . . . .30 Fig 26. Frequency deviation as a function of supply voltage V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DD Fig 27. I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .31 Fig 28. Application diagram. . . . . . . . . . . . . . . . . . . . . . .32 Fig 29. Package outline SOT650-1 (HVSON10) of PCF8563BS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Fig 30. Package outline SOT96-1 (SO8) of PCF8563T. .34 Fig 31. Package outline SOT505-1 (TSSOP8) of PCF8563TS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Fig 32. Temperature profiles for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PCF8563 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 11 — 26 October 2015 44 of 45

PCF8563 NXP Semiconductors Real-time clock/calendar 25. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 9.5 I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . 23 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 9.5.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.5.2 Clock and calendar READ or WRITE cycles. 23 3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9.6 Interface watchdog timer . . . . . . . . . . . . . . . . 25 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 26 5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 12 Static characteristics . . . . . . . . . . . . . . . . . . . 28 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 13 Dynamic characteristics. . . . . . . . . . . . . . . . . 30 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 14 Application information . . . . . . . . . . . . . . . . . 32 14.1 Quartz frequency adjustment. . . . . . . . . . . . . 32 8 Functional description . . . . . . . . . . . . . . . . . . . 6 14.1.1 Method1: fixed OSCI capacitor. . . . . . . . . . . 32 8.1 CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 6 14.1.2 Method2: OSCI trimmer . . . . . . . . . . . . . . . . 32 8.2 Register organization . . . . . . . . . . . . . . . . . . . . 6 14.1.3 Method3: OSCO output . . . . . . . . . . . . . . . . 32 8.3 Control registers. . . . . . . . . . . . . . . . . . . . . . . . 7 8.3.1 Register Control_status_1 . . . . . . . . . . . . . . . . 7 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 33 8.3.2 Register Control_status_2 . . . . . . . . . . . . . . . . 7 16 Handling information . . . . . . . . . . . . . . . . . . . 36 8.3.2.1 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . . 8 17 Soldering of SMD packages. . . . . . . . . . . . . . 36 8.4 Time and date registers . . . . . . . . . . . . . . . . . . 9 17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 36 8.4.1 Register VL_seconds. . . . . . . . . . . . . . . . . . . . 9 17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 36 8.4.1.1 Voltage-low detector and clock monitor . . . . . 10 17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 37 8.4.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10 17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 37 8.4.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.4.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 10 19 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.4.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 11 8.4.6 Register Century_months. . . . . . . . . . . . . . . . 11 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 40 8.4.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12 21 Legal information . . . . . . . . . . . . . . . . . . . . . . 41 8.5 Setting and reading the time. . . . . . . . . . . . . . 12 21.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 41 8.6 Alarm registers. . . . . . . . . . . . . . . . . . . . . . . . 13 21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.6.1 Register Minute_alarm. . . . . . . . . . . . . . . . . . 13 21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.6.2 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 14 21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.6.3 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 14 22 Contact information . . . . . . . . . . . . . . . . . . . . 42 8.6.4 Register Weekday_alarm. . . . . . . . . . . . . . . . 14 23 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.6.5 Alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 24 Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.7 Register CLKOUT_control and clock output. . 15 8.8 Timer function. . . . . . . . . . . . . . . . . . . . . . . . . 16 25 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.8.1 Register Timer_control. . . . . . . . . . . . . . . . . . 16 8.8.2 Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 16 8.9 EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 17 8.9.1 Operation example: . . . . . . . . . . . . . . . . . . . . 17 8.10 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18 8.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.11.1 Power-On Reset (POR) override . . . . . . . . . . 20 9 Characteristics of the I2C-bus . . . . . . . . . . . . 21 9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 START and STOP conditions. . . . . . . . . . . . . 21 9.3 System configuration . . . . . . . . . . . . . . . . . . . 21 9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 October 2015 Document identifier: PCF8563

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: PCF8563BS/4,118 PCF8563T/F4,112 PCF8563T/F4,118 PCF8563TS/4,118 PCF8563T/5,518 PCF8563TS/5,118