PCF85063TP Tiny Real-Time Clock/calendar Rev. 4 — 6 May 2015 Product data sheet 1. General description The PCF85063TP is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption. An offset register allows fine-tuning of the clock. All addresses and data are transferred serially via the two-line bidirectional I2C-bus. Maximum bus speed is 400kbit/s. The register address is incremented automatically after each written or read data byte. For a selection of NXP Real-Time Clocks, see Table35 on page43 2. Features and benefits  Provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768kHz quartz crystal  Clock operating voltage: 0.9Vto5.5V  Low current: typical 0.22Aat V =3.3V and T =25C DD amb  400kHz two-line I2C-bus interface (at V =1.8Vto5.5V) DD  Programmable clock output for peripheral devices (32.768kHz, 16.384kHz, 8.192kHz, 4.096kHz, 2.048 kHz, 1.024kHz, and 1Hz)  Selectable integrated oscillator load capacitors for C =7pF or C =12.5pF L L  Minute and half minute interrupt  Oscillator stop detection function  Internal Power-On Reset (POR)  Programmable offset register for frequency adjustment 3. Applications  Digital still camera  Digital video camera  Printers  Copy machines  Mobile equipment  Battery powered devices 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section21.

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 4. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF85063TP HWSON8 plastic thermal enhanced very very thin SOT1069-2 small outline package; no leads; 8 terminals; body 2  3  0.75 mm 4.1 Ordering options Table 2. Ordering opt ions Product type number Orderable part number Sales item Delivery form IC (12NC) revision PCF85063TP/1 PCF85063TP/1Z 935297365147 tape and reel, 7 inch 1 5. Marking Table 3. Marking codes Product type number Marking code PCF85063TP/1 063 6. Block diagram (cid:50)(cid:54)(cid:38)(cid:50) (cid:22)(cid:21)(cid:3)(cid:78)(cid:43)(cid:93) (cid:39)(cid:44)(cid:57)(cid:44)(cid:39)(cid:40)(cid:53) (cid:38)(cid:47)(cid:50)(cid:38)(cid:46)(cid:3)(cid:50)(cid:56)(cid:55) (cid:38)(cid:47)(cid:46)(cid:50)(cid:56)(cid:55) (cid:50)(cid:54)(cid:38)(cid:44)(cid:47)(cid:47)(cid:36)(cid:55)(cid:50)(cid:53) (cid:50)(cid:54)(cid:38)(cid:44) (cid:38)(cid:47)(cid:50)(cid:38)(cid:46) (cid:51)(cid:50)(cid:58)(cid:40)(cid:53)(cid:16)(cid:50)(cid:49) (cid:38)(cid:36)(cid:47)(cid:44)(cid:37)(cid:53)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:53)(cid:40)(cid:54)(cid:40)(cid:55) (cid:50)(cid:41)(cid:41)(cid:54)(cid:40)(cid:55) (cid:57)(cid:39)(cid:39) (cid:54)(cid:60)(cid:54)(cid:55)(cid:40)(cid:48) (cid:44)(cid:49)(cid:55)(cid:40)(cid:53)(cid:53)(cid:56)(cid:51)(cid:55) (cid:44)(cid:49)(cid:55) (cid:38)(cid:50)(cid:49)(cid:55)(cid:53)(cid:50)(cid:47) (cid:38)(cid:50)(cid:49)(cid:55)(cid:53)(cid:50)(cid:47) (cid:57)(cid:54)(cid:54) (cid:54)(cid:39)(cid:36) (cid:79)(cid:21)(cid:38)(cid:16)(cid:37)(cid:56)(cid:54) (cid:53)(cid:40)(cid:36)(cid:47)(cid:16)(cid:55)(cid:44)(cid:48)(cid:40) (cid:44)(cid:49)(cid:55)(cid:40)(cid:53)(cid:41)(cid:36)(cid:38)(cid:40) (cid:38)(cid:47)(cid:50)(cid:38)(cid:46) (cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:54)(cid:38)(cid:47) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:20)(cid:21) Fig 1. Block diagram of PCF85063TP PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 2 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 7. Pinning information 7.1 Pinning (cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:20) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:50)(cid:54)(cid:38)(cid:44) (cid:20) (cid:27) (cid:57)(cid:39)(cid:39) (cid:50)(cid:54)(cid:38)(cid:50) (cid:21) (cid:26) (cid:38)(cid:47)(cid:46)(cid:50)(cid:56)(cid:55) (cid:44)(cid:49)(cid:55) (cid:22) (cid:25) (cid:54)(cid:38)(cid:47) (cid:57)(cid:54)(cid:54) (cid:23) (cid:24) (cid:54)(cid:39)(cid:36) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:20)(cid:22) (cid:55)(cid:85)(cid:68)(cid:81)(cid:86)(cid:83)(cid:68)(cid:85)(cid:72)(cid:81)(cid:87)(cid:3)(cid:87)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) For mechanical details, see Figure27. Fig 2. Pin configuration for HWSON8 (PCF85063TP) 7.2 Pin description Table 4. Pin description Input or input/output pins must always be at a defined level (V or V ) unless otherwise specified. SS DD Symbol Pin Type Description OSCI 1 input oscillator input OSCO 2 output oscillator output INT 3 output interrupt output (open-drain) VSS 4[1] supply ground supply voltage SDA 5 input/output serial data line SCL 6 input serial clock input CLKOUT 7 output clock output (push-pull) VDD 8 supply supply voltage [1] The die paddle (exposed pad) is connected to V and should be electrically isolated. SS PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 3 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8. Functional description The PCF85063TP contains 11 8-bit registers with an auto-incrementing register address, an on-chip 32.768kHz oscillator with integrated capacitors, a frequency divider which provides the source clock for the Real-Time Clock (RTC) and calender, and an I2C-bus interface with a maximum data rate of 400kbit/s. The built-in address register will increment automatically after each read or write of a data byte up to the register 0Ah. After register 0Ah, the auto-incrementing will wrap around to address 00h (see Figure3). (cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85) (cid:19)(cid:19)(cid:75) (cid:19)(cid:20)(cid:75) (cid:19)(cid:21)(cid:75) (cid:68)(cid:88)(cid:87)(cid:82)(cid:16)(cid:76)(cid:81)(cid:70)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:19)(cid:22)(cid:75) (cid:17)(cid:17)(cid:17) (cid:19)(cid:27)(cid:75) (cid:19)(cid:28)(cid:75) (cid:19)(cid:36)(cid:75) (cid:90)(cid:85)(cid:68)(cid:83)(cid:3)(cid:68)(cid:85)(cid:82)(cid:88)(cid:81)(cid:71) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:20)(cid:23) Fig 3. Handling address registers All 11registers (see Table5) are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00h and 01h) are used as control and status register. The register at address 02h is an offset register allowing the fine-tuning of the clock; and at 03h is a free RAM byte. The addresses04h through0Ah are used as counters for the clock function (seconds up to years counters). The Seconds, Minutes, Hours, Days, Months, and Years registers are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is written or read, the contents of all time counters are frozen. Therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 4 of 52

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P N roduct d CF85063TP Table 5. Regist8e.r1s ovR erevgieiwsters organization XP S ata Bit positions labeled as- are not implemented. After reset, all registers are set according to Table8 on page10. em sh Address Register name Bit Reference ic e e o t 7 6 5 4 3 2 1 0 n d Control and status registers u c 00h Control_1 EXT_TEST - STOP SR - CIE 12_24 CAP_SEL Section8.2.1 t o r 01h Control_2 - - MI HMI TF COF[2:0] Section8.2.2 s 02h Offset MODE OFFSET[6:0] Section8.2.3 03h RAM_byte B[7:0] Section8.2.4 Time and date registers A ll inform 04h Seconds OS SECONDS (0 to 59) Section8.3.1 Rev. 4 — 6 May 2015 ation provided in this document is subject to legal disclaim 0000008A7569hhhhhh YWDMHMeaoioenayuneursrtsksthedssays Y-----EARS (0 to 9---M-9)INUTES (0 to-DH- 5AO9YAU)SMR P(S1M (t0o t3o1 2)H-M3OO) UiNnR T2SH4 S (h1 o( 1tuo rt o1m- 21o)2 di)ne 12 hour mWoEdEeKDAYS (0to6) SSSSSSeeeeeeccccccttttttiiiiiioooooonnnnnn888888......333333......235674 ers. T in y © R P N e XP a C Sem l-T iconductors N.V. 2015. A ime Clock/c F8506 5 of 52 ll rights reserved. alendar 3TP

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.2 Control registers 8.2.1 Register Control_1 Table 6. Control_1 - c ontrol and status register 1 (address00h) bit description Bit Symbol Value Description Reference 7 EXT_TEST external clock test mode Section8.2.1.1 0[1] normal mode 1 external clock test mode 6 - 0 unused - 5 STOP STOP bit Section8.2.1.2 0[1] RTC clock runs 1 RTC clock is stopped; all RTC divider chain flip-flops are asynchronously set logic0 4 SR software reset Section8.2.1.3 0[1] no software reset 1 initiate software reset[2]; this bit always returns a 0 when read 3 - 0 unused - 2 CIE correction interrupt enable Section8.2.3 0[1] no correction interrupt generated 1 interrupt pulses are generated at every correction cycle 1 12_24 12 or 24 hour mode Section8.3.3 0[1] 24 hour mode is selected 1 12 hour mode is selected 0 CAP_SEL internal oscillator capacitor selection for - quartz crystals with a corresponding load capacitance 0[1] 7 pF 1 12.5 pF [1] Default value. [2] For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section8.2.1.3). PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 6 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.2.1.1 EXT_TEST: external clock test mode A test mode is available which allows for on-board testing. In this mode, it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bitEXT_TEST in register Control_1. Then pinCLKOUT becomes an input. The test mode replaces the internal clock signal with the signal applied to pinCLKOUT. The signal applied to pinCLKOUT should have a minimum pulse width of 300ns and a maximum period of 1000ns. The internal clock, now sourced from CLKOUT, is divided down to 1Hz by a 26divide chain called a prescaler. The prescaler can be set into a known state by using bitSTOP. When bitSTOP is set, the prescaler is reset to0. (STOP must be cleared before the prescaler can operate again.) From a stop condition, the first 1second increment will take place after 32positive edges on pin CLKOUT. Thereafter, every 64positive edges cause a 1second increment. Remark: Entry into test mode is not synchronized to the internal 64Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. Operation example: 1. Set EXT_TEST test mode (register Control_1, bitEXT_TEST=1) 2. Set STOP (register Control_1, bitSTOP=1) 3. Clear STOP (register Control_1, bitSTOP=0) 4. Set time registers to desired value 5. Apply 32clock pulses to pin CLKOUT 6. Read time registers to see the first change 7. Apply 64clock pulses to pin CLKOUT 8. Read time registers to see the second change Repeat 7and8 for additional increments. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 7 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.2.1.2 STOP: STOP bit function The function of the STOP bit (see Figure4) is to allow for accurate starting of the time circuits. The STOP bit function causes the upper part of the prescaler (F to F ) to be 2 14 held in reset and thus no 1Hz ticks are generated. It also stops the output of clock frequencies lower than 8kHz on pin CLKOUT. (cid:50)(cid:54)(cid:38)(cid:44)(cid:47)(cid:47)(cid:36)(cid:55)(cid:50)(cid:53)(cid:3)(cid:54)(cid:55)(cid:50)(cid:51) (cid:86)(cid:72)(cid:87)(cid:87)(cid:76)(cid:81)(cid:74)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:50)(cid:54)(cid:3)(cid:73)(cid:79)(cid:68)(cid:74) (cid:39)(cid:40)(cid:55)(cid:40)(cid:38)(cid:55)(cid:50)(cid:53) (cid:50)(cid:54)(cid:38)(cid:44)(cid:47)(cid:47)(cid:36)(cid:55)(cid:50)(cid:53) (cid:22)(cid:21)(cid:26)(cid:25)(cid:27)(cid:3)(cid:43)(cid:93) (cid:41)(cid:19) (cid:20)(cid:25)(cid:22)(cid:27)(cid:23)(cid:3)(cid:43)(cid:93) (cid:41)(cid:20) (cid:27)(cid:20)(cid:28)(cid:21)(cid:3)(cid:43)(cid:93) (cid:41)(cid:21) (cid:23)(cid:19)(cid:28)(cid:25)(cid:3)(cid:43)(cid:93) (cid:41)(cid:20)(cid:22) (cid:21)(cid:3)(cid:43)(cid:93) (cid:41)(cid:20)(cid:23) (cid:20)(cid:3)(cid:43)(cid:93)(cid:3)(cid:87)(cid:76)(cid:70)(cid:78) (cid:53)(cid:40)(cid:54)(cid:40)(cid:55) (cid:53)(cid:40)(cid:54)(cid:40)(cid:55) (cid:53)(cid:40)(cid:54)(cid:40)(cid:55) (cid:54)(cid:55)(cid:50)(cid:51) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:20)(cid:24) Fig 4. STOP bit functional diagram The time circuits can then be set and do not increment until the STOP bit is released (see Figure5 and Table7). PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 8 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar Table 7. First increme nt of time circuits after STOP bit release Bit Prescaler bits [1] 1Hz tick Time Comment STOP F F -F to F hh:mm:ss 0 1 2 14 Clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally STOP bit is activated by user. F F are not reset and values cannot be predicted externally 0 1 1 XX-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen New time is set by user 1 XX-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen STOP bit is released by user 0 XX-0 0000 0000 0000 08:00:00 prescaler is now running XX-1 0000 0000 0000 08:00:00 - XX-0 1000 0000 0000 08:00:00 - (cid:19)(cid:17)(cid:24)(cid:19)(cid:26)(cid:27)(cid:20)(cid:22) XX-1 1000 0000 0000 (cid:87)(cid:82) 08:00:00 - (cid:19)(cid:17)(cid:24)(cid:19)(cid:26)(cid:28)(cid:22)(cid:24)(cid:3)(cid:86) : : : 11-1 1111 1111 1110 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of F14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : : : 11-1 1111 1111 1111 (cid:20)(cid:17)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:3)(cid:86) 08:00:01 - 00-0 0000 0000 0000 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : : : 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of F14 increments the time circuits (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:20)(cid:25) [1] F is clocked at 32.768 kHz. 0 The lower two stages of the prescaler (F and F ) are not reset. And because the I2C-bus 0 1 is asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is between zero and one 8.192 kHz cycle (see Figure5). (cid:27)(cid:20)(cid:28)(cid:21)(cid:3)(cid:43)(cid:93) (cid:86)(cid:87)(cid:82)(cid:83)(cid:3)(cid:85)(cid:72)(cid:79)(cid:72)(cid:68)(cid:86)(cid:72)(cid:71) (cid:19)(cid:3)(cid:151)(cid:86)(cid:3)(cid:87)(cid:82)(cid:3)(cid:20)(cid:21)(cid:21)(cid:3)(cid:151)(cid:86) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:20)(cid:26) Fig 5. STOP bit release timing The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The uncertainty is caused by the prescaler bits F and F not being reset 0 1 (see Table7) and the unknown state of the 32kHz clock. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 9 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.2.1.3 Software reset A reset is automatically generated at power-on. A reset can also be initiated with the software reset command. Software reset command means setting bits 6, 4, and 3 in register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit sequence 01011000 (58h), see Figure6. (cid:86)(cid:79)(cid:68)(cid:89)(cid:72)(cid:3)(cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:53)(cid:18)(cid:58) (cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86)(cid:3)(cid:19)(cid:19)(cid:75) (cid:86)(cid:82)(cid:73)(cid:87)(cid:90)(cid:68)(cid:85)(cid:72)(cid:3)(cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:24)(cid:27)(cid:75) (cid:54)(cid:39)(cid:36) (cid:86) (cid:20) (cid:19) (cid:20) (cid:19) (cid:19) (cid:19) (cid:20) (cid:19) (cid:36) (cid:19) (cid:19) (cid:19) (cid:19) (cid:19) (cid:19) (cid:19) (cid:19) (cid:36) (cid:19) (cid:20) (cid:19) (cid:20) (cid:20) (cid:19) (cid:19) (cid:19) (cid:36) (cid:51)(cid:18)(cid:54) (cid:54)(cid:38)(cid:47) (cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:81)(cid:68)(cid:79) (cid:85)(cid:72)(cid:86)(cid:72)(cid:87)(cid:3)(cid:86)(cid:76)(cid:74)(cid:81)(cid:68)(cid:79) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:20)(cid:27) Fig 6. Software reset command In reset state all registers are set according to Table8 and the address pointer returns to address 00h. Table 8. Register reset values Address Register name Bit 7 6 5 4 3 2 1 0 00h Control_1 0 0 0 0 0 0 0 0 01h Control_2 0 0 0 0 0 0 0 0 02h Offset 0 0 0 0 0 0 0 0 03h RAM_byte 0 0 0 0 0 0 0 0 04h Seconds 1 0 0 0 0 0 0 0 05h Minutes 0 0 0 0 0 0 0 0 06h Hours 0 0 0 0 0 0 0 0 07h Days 0 0 0 0 0 0 0 1 08h Weekdays 0 0 0 0 0 1 1 0 09h Months 0 0 0 0 0 0 0 1 0Ah Years 0 0 0 0 0 0 0 0 The PCF85063TP resets to: Time — 00:00:00 Date — 20000101 Weekday — Saturday PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 10 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.2.2 Register Control_2 Table 9. Control_2 - control and status register 2 (address01h) bit description Bit Symbol Value Description 7 to 6 - 00 unused 5 MI minute interrupt 0[1] disabled 1 enabled 4 HMI half minute interrupt 0[1] disabled 1 enabled 3 TF timer flag 0[1] no timer interrupt generated 1 flag set when timer interrupt generated 2 to 0 COF[2:0] see Table11 CLKOUT control [1] Default value. 8.2.2.1 MI and HMI: minute and half minute interrupt The minute interrupt (bit MI) and half minute interrupt (bit HMI) are pre-defined timers for generating interrupt pulses on pin INT; see Figure7. The timers are running in sync with the seconds counter (see Table19 on page17). The minute and half minute interrupts must only be used when the frequency offset is set to normal mode (MODE=0), see Section8.2.3. In normal mode, the interrupt pulses on pin INT are 1⁄ s wide. 64 When starting MI, the first interrupt will be generated after 1 second to 59 seconds. When starting HMI, the first interrupt will be generated after 1 second to 29 seconds. Subsequent periods do not have such a delay. The timers can be enabled independently from one another. However, a minute interrupt enabled on top of a half minute interrupt is not distinguishable. (cid:86)(cid:72)(cid:70)(cid:82)(cid:81)(cid:71)(cid:86)(cid:3)(cid:70)(cid:82)(cid:88)(cid:81)(cid:87)(cid:72)(cid:85) (cid:24)(cid:27) (cid:24)(cid:28) (cid:24)(cid:28) (cid:19)(cid:19) (cid:19)(cid:19) (cid:19)(cid:20) (cid:80)(cid:76)(cid:81)(cid:88)(cid:87)(cid:72)(cid:86)(cid:3)(cid:70)(cid:82)(cid:88)(cid:81)(cid:87)(cid:72)(cid:85) (cid:20)(cid:20) (cid:20)(cid:21) (cid:44)(cid:49)(cid:55)(cid:3)(cid:90)(cid:75)(cid:72)(cid:81)(cid:3)(cid:48)(cid:44)(cid:3)(cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:71) (cid:55)(cid:41)(cid:3)(cid:90)(cid:75)(cid:72)(cid:81)(cid:3)(cid:48)(cid:44)(cid:3)(cid:72)(cid:81)(cid:68)(cid:69)(cid:79)(cid:72)(cid:71) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:20)(cid:28) In this example, the TF flag is not cleared after an interrupt. Fig 7. INT example for MI PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 11 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar Table 10. Effect of bits MI and HMI on INT generation Minute interrupt (bit MI) Half minute interrupt (bit HMI) Result 0 0 no interrupt generated 1 0 an interrupt every minute 0 1 an interrupt every 30 s 1 1 an interrupt every 30 s The duration of the timer is affected by the register Offset (see Section8.2.3). Only when OFFSET[6:0] has the value 00h the periods are consistent. 8.2.2.2 TF: timer flag The timer flag (bit TF) is set logic 1 on the first trigger of MI or HMI and remains set until it is cleared by command. 8.2.2.3 COF[2:0]: Clock output frequency A programmable square wave is available at pinCLKOUT. Operation is controlled by the COF[2:0] bits in the register Control_2. Frequencies of 32.768kHz (default) down to 1Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Pin CLKOUT is a push-pull output and enabled at power-on. CLKOUT can be disabled by setting COF[2:0] to 111. When disabled, the CLKOUT is LOW. The duty cycle of the selected clock is not controlled but due to the nature of the clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50. The STOP bit function can also affect the CLKOUT signal, depending on the selected frequency. When the STOP bit is set logic 1, the CLKOUT pin generates a continuous LOW for those frequencies that can be stopped. For more details of the STOP bit function, see Section8.2.1.2. Table 11. CLKOUT frequency selection COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1] Effect of STOP bit 000[2] 32768 60:40 to 40:60 no effect 001 16384 50:50 no effect 010 8192 50:50 no effect 011 4096 50:50 CLKOUT = LOW 100 2048 50:50 CLKOUT = LOW 101 1024 50:50 CLKOUT = LOW 110 1[3] 50:50 CLKOUT = LOW 111 CLKOUT = LOW - - [1] Duty cycle definition: %HIGH-level time: %LOW-level time. [2] Default value. [3] 1Hz clock pulses are affected by offset correction pulses. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 12 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.2.3 Register Offset The PCF85063TP incorporates an offset register (address 02h) which can be used to implement several functions, such as: • Accuracy tuning • Aging adjustment • Temperature compensation Table 12. Offset - offset register (address02h) bit description Bit Symbol Value Description 7 MODE offset mode 0[1] normal mode: offset is made once every two hours 1 course mode: offset is made every 4 minutes 6to 0 OFFSET[6:0] see Table13 offset value [1] Default value. For MODE=0, each LSB introduces an offset of 4.34ppm. For MODE=1, each LSB introduces an offset of 4.069ppm. The offset value is coded in two’s complement giving a range of +63LSB to64LSB. Table 13. Offset values OFFSET[6:0] Offset value in Offset value in ppm decimal Normal mode Fast mode MODE=0 MODE=1 0111111 +63 +273.420 +256.347 0111110 +62 +269.080 +252.278 : : : : 0000010 +2 +8.680 +8.138 0000001 +1 +4.340 +4.069 0000000[1] 0 0[1] 0[1] 1111111 1 4.340 4.069 1111110 2 8.680 8.138 : : : : 1000001 63 273.420 256.347 1000000 64 277.760 260.416 [1] Default value. The correction is made by adding or subtracting clock correction pulses, thereby changing the period of a single second but not by changing the oscillator frequency. It is possible to monitor when correction pulses are applied. To enable correction interrupt generation, bit CIE (register Control_1) has to be set logic1. At every correction cycle a pulse is generated on pin INT. The pulse width depends on the correction mode. If multiple correction pulses are applied, an interrupt pulse is generated for each correction pulse applied. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 13 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.2.3.1 Correction when MODE=0 The correction is triggered once every two hours and then correction pulses are applied once per minute until the programmed correction values have been implemented. Table 14. Correction pulses for MODE=0 Correction value Update every nth hour Minute Correction pulses on INT per minute[1] +1 or 1 2 00 1 +2 or 2 2 00 and 01 1 +3 or 3 2 00, 01, and 02 1 : : : : +59 or 59 2 00 to 58 1 +60 or 60 2 00 to 59 1 +61 or 61 2 00 to 59 1 2nd and next hour 00 1 +62 or 62 2 00 to 59 1 2nd and next hour 00 and 01 1 +63 or 63 02 00 to 59 1 2nd and next hour 00, 01, and 02 1 64 02 00 to 59 1 2nd and next hour 00, 01, 02, and 03 1 [1] The correction pulses on pin INT are 1⁄ s wide. 64 In MODE=0, any timer or clock output using a frequency below 64 Hz is affected by the clock correction (see Table15). T able 15. Effect of correction pulseson frequencies for MODE=0 Frequency (Hz) Effect of correction CLKOUT 32768 no effect 16384 no effect 8192 no effect 4096 no effect 2048 no effect 1024 no effect 1 affected Timer source clock 4096 no effect 64 no effect 1 affected 1⁄ affected 60 8.2.3.2 Correction when MODE=1 The correction is triggered once every four minutes and then correction pulses are applied once per second up to a maximum of 60 pulses. When correction values greater than 60 pulses are used, additional correction pulses are made in the 59th second. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 14 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar Clock correction is made more frequently in MODE =1; however, this can result in higher power consumption. Table 16. Correction pulses for MODE=1 Correction value Update every nth Second Correction pulses on minute INT per second[1] +1 or 1 2 00 1 +2 or 2 2 00 and 01 1 +3 or 3 2 00, 01, and 02 1 : : : : +59 or 59 2 00 to 58 1 +60 or 60 2 00 to 59 1 +61 or 61 2 00 to 58 1 2 59 2 +62 or 62 2 00 to 58 1 2 59 3 +63 or 63 2 00 to 58 1 2 59 4 64 2 00 to 58 1 2 59 5 [1] The correction pulses on pin INT are 1⁄ s wide. For multiple pulses, they are repeated at an interval of 1024 1⁄ s. 512 In MODE=1, any timer source clock using a frequency below 1.024 kHz is also affected by the clock correction (see Table17). T able 17. Effect of correction pulseson frequencies for MODE=1 Frequency (Hz) Effect of correction CLKOUT 32768 no effect 16384 no effect 8192 no effect 4096 no effect 2048 no effect 1024 no effect 1 affected Timer source clock 4096 no effect 64 affected 1 affected 1⁄ affected 60 PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 15 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.2.3.3 Offset calibration workflow The calibration offset has to be calculated based on the time. Figure8 shows the workflow how the offset register values can be calculated: (cid:86)(cid:68)(cid:80)(cid:83)(cid:79)(cid:72)(cid:3)(cid:70)(cid:68)(cid:79)(cid:70)(cid:88)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:29) (cid:48)(cid:72)(cid:68)(cid:86)(cid:88)(cid:85)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:73)(cid:85)(cid:72)(cid:84)(cid:88)(cid:72)(cid:81)(cid:70)(cid:92)(cid:3)(cid:82)(cid:81)(cid:3)(cid:83)(cid:76)(cid:81)(cid:3)(cid:38)(cid:47)(cid:46)(cid:50)(cid:56)(cid:55)(cid:29) (cid:73)(cid:80)(cid:72)(cid:68)(cid:86) (cid:22)(cid:21)(cid:26)(cid:25)(cid:27)(cid:17)(cid:23)(cid:27)(cid:3)(cid:43)(cid:93) (cid:38)(cid:82)(cid:81)(cid:89)(cid:72)(cid:85)(cid:87)(cid:3)(cid:87)(cid:82)(cid:3)(cid:87)(cid:76)(cid:80)(cid:72)(cid:29) (cid:87)(cid:80)(cid:72)(cid:68)(cid:86)(cid:3)(cid:32)(cid:3)(cid:20)(cid:3)(cid:18)(cid:3)(cid:73)(cid:80)(cid:72)(cid:68)(cid:86) (cid:22)(cid:19)(cid:17)(cid:24)(cid:20)(cid:26)(cid:20)(cid:22)(cid:20)(cid:3)(cid:151)(cid:86) (cid:38)(cid:68)(cid:79)(cid:70)(cid:88)(cid:79)(cid:68)(cid:87)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:71)(cid:76)(cid:73)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72)(cid:3)(cid:87)(cid:82)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:76)(cid:71)(cid:72)(cid:68)(cid:79) (cid:83)(cid:72)(cid:85)(cid:76)(cid:82)(cid:71)(cid:3)(cid:82)(cid:73)(cid:3)(cid:20)(cid:3)(cid:18)(cid:3)(cid:22)(cid:21)(cid:26)(cid:25)(cid:27)(cid:17)(cid:19)(cid:19)(cid:29)(cid:3) (cid:39)(cid:80)(cid:72)(cid:68)(cid:86)(cid:3)(cid:32)(cid:3)(cid:20)(cid:3)(cid:18)(cid:3)(cid:22)(cid:21)(cid:26)(cid:25)(cid:27)(cid:3)(cid:16)(cid:3)(cid:87)(cid:80)(cid:72)(cid:68)(cid:86) (cid:19)(cid:17)(cid:19)(cid:19)(cid:19)(cid:23)(cid:23)(cid:26)(cid:3)(cid:151)(cid:86) (cid:38)(cid:68)(cid:79)(cid:70)(cid:88)(cid:79)(cid:68)(cid:87)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:83)(cid:83)(cid:80)(cid:3)(cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:70)(cid:82)(cid:80)(cid:83)(cid:68)(cid:85)(cid:72)(cid:71) (cid:87)(cid:82)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:80)(cid:72)(cid:68)(cid:86)(cid:88)(cid:85)(cid:72)(cid:71)(cid:3)(cid:89)(cid:68)(cid:79)(cid:88)(cid:72)(cid:29)(cid:3) (cid:40)(cid:83)(cid:83)(cid:80)(cid:3)(cid:32)(cid:3)(cid:20)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:19)(cid:3)(cid:238)(cid:3)(cid:39)(cid:80)(cid:72)(cid:68)(cid:86)(cid:3)(cid:3)(cid:18)(cid:3)(cid:87)(cid:80)(cid:72)(cid:68)(cid:86) (cid:20)(cid:23)(cid:17)(cid:25)(cid:23)(cid:27)(cid:3)(cid:83)(cid:83)(cid:80) (cid:38)(cid:68)(cid:79)(cid:70)(cid:88)(cid:79)(cid:68)(cid:87)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:82)(cid:73)(cid:73)(cid:86)(cid:72)(cid:87)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:3)(cid:89)(cid:68)(cid:79)(cid:88)(cid:72)(cid:29) (cid:48)(cid:82)(cid:71)(cid:72)(cid:3)(cid:32)(cid:3)(cid:19)(cid:3)(cid:11)(cid:79)(cid:82)(cid:90)(cid:3)(cid:83)(cid:82)(cid:90)(cid:72)(cid:85)(cid:12)(cid:29) (cid:50)(cid:73)(cid:73)(cid:86)(cid:72)(cid:87)(cid:3)(cid:89)(cid:68)(cid:79)(cid:88)(cid:72)(cid:3)(cid:32)(cid:3)(cid:40)(cid:83)(cid:83)(cid:80)(cid:3)(cid:18)(cid:3)(cid:23)(cid:17)(cid:22)(cid:23) (cid:22)(cid:17)(cid:22)(cid:26)(cid:24)(cid:3) (cid:22)(cid:3)(cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:83)(cid:88)(cid:79)(cid:86)(cid:72)(cid:86) (cid:68)(cid:85)(cid:72)(cid:3)(cid:81)(cid:72)(cid:72)(cid:71)(cid:72)(cid:71) (cid:48)(cid:82)(cid:71)(cid:72)(cid:3)(cid:32)(cid:3)(cid:20)(cid:3)(cid:11)(cid:73)(cid:68)(cid:86)(cid:87)(cid:3)(cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81)(cid:12) (cid:50)(cid:73)(cid:73)(cid:86)(cid:72)(cid:87)(cid:3)(cid:89)(cid:68)(cid:79)(cid:88)(cid:72)(cid:3)(cid:32)(cid:3)(cid:40)(cid:83)(cid:83)(cid:80)(cid:3)(cid:18)(cid:3)(cid:23)(cid:17)(cid:19)(cid:25)(cid:28) (cid:22)(cid:17)(cid:25)(cid:19)(cid:19)(cid:3) (cid:23)(cid:3)(cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:83)(cid:88)(cid:79)(cid:86)(cid:72)(cid:86) (cid:68)(cid:85)(cid:72)(cid:3)(cid:81)(cid:72)(cid:72)(cid:71)(cid:72)(cid:71) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:22)(cid:26)(cid:24) Fig 8. Offset calibration calculation workflow PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 16 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:11)(cid:21)(cid:12) (cid:11)(cid:20)(cid:12) (cid:11)(cid:22)(cid:12) (cid:16)(cid:25) (cid:16)(cid:23) (cid:16)(cid:21) (cid:19) (cid:21) (cid:23) (cid:25) (cid:27) (cid:20)(cid:19) (cid:20)(cid:21) (cid:20)(cid:23) (cid:20)(cid:25) (cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:73)(cid:87)(cid:72)(cid:85) (cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:68)(cid:73)(cid:87)(cid:72)(cid:85) (cid:80)(cid:72)(cid:68)(cid:86)(cid:88)(cid:85)(cid:72)(cid:71)(cid:18)(cid:70)(cid:68)(cid:79)(cid:70)(cid:88)(cid:79)(cid:68)(cid:87)(cid:72)(cid:71) (cid:3)(cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:76)(cid:81)(cid:3) (cid:3)(cid:70)(cid:82)(cid:85)(cid:85)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:76)(cid:81)(cid:3) (cid:71)(cid:72)(cid:89)(cid:76)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:3)(cid:3)(cid:20)(cid:23)(cid:17)(cid:25)(cid:23)(cid:27)(cid:3)(cid:83)(cid:83)(cid:80) (cid:48)(cid:50)(cid:39)(cid:40)(cid:3)(cid:32)(cid:3)(cid:20) (cid:48)(cid:50)(cid:39)(cid:40)(cid:3)(cid:32)(cid:3)(cid:19) (cid:3)(cid:3)(cid:16)(cid:20)(cid:17)(cid:25)(cid:21)(cid:27)(cid:3)(cid:83)(cid:83)(cid:80) (cid:3)(cid:3)(cid:3)(cid:14)(cid:20)(cid:17)(cid:25)(cid:21)(cid:27)(cid:3)(cid:83)(cid:83)(cid:80) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:22)(cid:26)(cid:20) With the offset calibration an accuracy of 2ppm (0.5  offset per LSB) can be reached (see Table13). 1ppm corresponds to a time deviation of 0.0864seconds per day. (1) 3 correction pulses in MODE=0 correspond to 13.02ppm. (2) 4 correction pulses in MODE=1correspond to 16.276ppm. (3) Reachable accuracy zone. Fig 9. Result of offset calibration 8.2.4 Register RAM_byte The PCF85063TP provides a free RAM byte, which can be used for any purpose, for example, status byte of the system. Table 18. RAM_byte - 8-bit RAM register (address 03h) bit description Bit Symbol Value Description 7 to 0 B[7:0] 00000000[1] to RAM content 11111111 [1] Default value. 8.3 Time and date registers Most of the registers are coded in the BCD format to simplify application use. 8.3.1 Register Seconds Table 19. Seconds - seconds register (address04h) bit description Bit Symbol Value Place value Description 7 OS oscillator stop 0 - clock integrity is guaranteed 1[1] - clock integrity is not guaranteed; oscillator has stopped or has been interrupted 6to4 SECONDS 0[1] to 5 ten’s place actual seconds coded in BCD format, see Table20 3 to 0 0[1]to9 unit place [1] Default value. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 17 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar Table 20. Seconds coded in BCD format Seconds value in Upper-digit (ten’s place) Digit (unit place) decimal Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00[1] 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 [1] Default value. 8.3.1.1 OS: Oscillator stop When the oscillator of the PCF85063TP is stopped, the OS flag is set. The oscillator can be stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to ground. The oscillator is considered to be stopped during the time between power-on and stable crystal resonance. This time can be in the range of 200ms to 2s depending on crystal type, temperature, and supply voltage. The flag remains set until cleared by command (see Figure10). If the flag cannot be cleared, then the oscillator is not running. This method can be used to monitor the oscillator and to determine if the supply voltage has reduced to the point where oscillation fails. (cid:50)(cid:54)(cid:3)(cid:32)(cid:3)(cid:20)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:73)(cid:79)(cid:68)(cid:74)(cid:3)(cid:70)(cid:68)(cid:81)(cid:3)(cid:81)(cid:82)(cid:87)(cid:3)(cid:69)(cid:72)(cid:3)(cid:70)(cid:79)(cid:72)(cid:68)(cid:85)(cid:72)(cid:71) (cid:50)(cid:54)(cid:3)(cid:32)(cid:3)(cid:20)(cid:3)(cid:68)(cid:81)(cid:71)(cid:3)(cid:73)(cid:79)(cid:68)(cid:74)(cid:3)(cid:70)(cid:68)(cid:81)(cid:3)(cid:69)(cid:72)(cid:3)(cid:70)(cid:79)(cid:72)(cid:68)(cid:85)(cid:72)(cid:71) (cid:57)(cid:39)(cid:39) (cid:82)(cid:86)(cid:70)(cid:76)(cid:79)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81) (cid:50)(cid:54)(cid:3)(cid:73)(cid:79)(cid:68)(cid:74)(cid:3)(cid:86)(cid:72)(cid:87)(cid:3)(cid:90)(cid:75)(cid:72)(cid:81) (cid:50)(cid:54)(cid:3)(cid:73)(cid:79)(cid:68)(cid:74) (cid:82)(cid:86)(cid:70)(cid:76)(cid:79)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:86)(cid:87)(cid:82)(cid:83)(cid:86) (cid:50)(cid:54)(cid:3)(cid:73)(cid:79)(cid:68)(cid:74)(cid:3)(cid:70)(cid:79)(cid:72)(cid:68)(cid:85)(cid:72)(cid:71) (cid:69)(cid:92)(cid:3)(cid:86)(cid:82)(cid:73)(cid:87)(cid:90)(cid:68)(cid:85)(cid:72) (cid:87) (cid:82)(cid:86)(cid:70)(cid:76)(cid:79)(cid:79)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:81)(cid:82)(cid:90)(cid:3)(cid:86)(cid:87)(cid:68)(cid:69)(cid:79)(cid:72) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:21)(cid:19) Fig 10. OS flag PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 18 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.3.2 Register Minutes Table 21. Minutes - minutes register (address05h) bit description Bit Symbol Value Place value Description 7 - 0 - unused 6to4 MINUTES 0[1] to 5 ten’s place actual minutes coded in BCD format 3 to 0 0[1]to9 unit place [1] Default value. 8.3.3 Register Hours Table 22. Hours - hours register (address06h) bit description Bit Symbol Value Place value Description 7 to 6 - 00 - unused 12 hour mode[1] 5 AMPM AM/PM indicator 0[2] - AM 1 - PM 4 HOURS 0[2]to1 ten’s place actual hours in 12 hour mode coded in BCD format 3to0 0[2]to9 unit place 24 hour mode[1] 5to4 HOURS 0[2]to2 ten’s place actual hours in 24 hour mode coded in BCD format 3to0 0[2]to9 unit place [1] Hour mode is set by the 12_24 bit in register Control_1. [2] Default value. 8.3.4 Register Days Table 23. Days - days register (address07h) bit description Bit Symbol Value Place value Description 7 to 6 - 00 - unused 5to4 DAYS[1] 0[2]to3 ten’s place actual day coded in BCD format 3to0 0[3]to9 unit place [1] If the year counter contains a value, which is exactly divisible by4 (including the year00), the PCF85063TP compensates for leap years by adding a 29th day to February. [2] Default value. [3] Default value is 1. 8.3.5 Register Weekdays Table 24. Weekdays - weekdays register (address08h) bit description Bit Symbol Value Description 7 to 3 - 00000 unused 2to0 WEEKDAYS 0to6 actual weekday values, seeTable25 PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 19 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar Table 25. Weekday assignments Day[1] Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday[2] 1 1 0 [1] Definition may be reassigned by the user. [2] Default value. 8.3.6 Register Months Table 26. Months - months register (address09h) bit description Bit Symbol Value Place value Description 7 to 5 - 000 - unused 4 MONTHS 0to 1 ten’s place actual month coded in BCD format, see Table27 3 to 0 0 to 9 unit place Table 27. Month assignmentsin BCD format Month Upper-digit Digit (unit place) (ten’s place) Bit4 Bit3 Bit2 Bit1 Bit0 January[1] 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 [1] Default value. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 20 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 8.3.7 Register Years Table 28. Years - years register (0Ah) bit description Bit Symbol Value Place value Description 7to4 YEARS 0[1]to9 ten’s place actual year coded in BCD format 3to0 0[1]to9 unit place [1] Default value. 8.4 Setting and reading the time Figure11 shows the data flow and data dependencies starting from the 1 Hz clock tick. (cid:20)(cid:3)(cid:43)(cid:93)(cid:3)(cid:87)(cid:76)(cid:70)(cid:78) (cid:54)(cid:40)(cid:38)(cid:50)(cid:49)(cid:39)(cid:54) (cid:48)(cid:44)(cid:49)(cid:56)(cid:55)(cid:40)(cid:54) (cid:20)(cid:21)(cid:66)(cid:21)(cid:23)(cid:3)(cid:75)(cid:82)(cid:88)(cid:85)(cid:3)(cid:80)(cid:82)(cid:71)(cid:72) (cid:43)(cid:50)(cid:56)(cid:53)(cid:54) (cid:47)(cid:40)(cid:36)(cid:51)(cid:3)(cid:60)(cid:40)(cid:36)(cid:53) (cid:39)(cid:36)(cid:60)(cid:54) (cid:58)(cid:40)(cid:40)(cid:46)(cid:39)(cid:36)(cid:60) (cid:38)(cid:36)(cid:47)(cid:38)(cid:56)(cid:47)(cid:36)(cid:55)(cid:44)(cid:50)(cid:49) (cid:48)(cid:50)(cid:49)(cid:55)(cid:43)(cid:54) (cid:60)(cid:40)(cid:36)(cid:53)(cid:54) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:21)(cid:20) Fig 11. Data flow for the time function During read/write operations, the time counting circuits (memory locations 04h through 0Ah) are blocked. The blocking prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure12). PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 21 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:87)(cid:3)(cid:31)(cid:3)(cid:20)(cid:3)(cid:86) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55) (cid:54)(cid:47)(cid:36)(cid:57)(cid:40)(cid:3)(cid:36)(cid:39)(cid:39)(cid:53)(cid:40)(cid:54)(cid:54) (cid:39)(cid:36)(cid:55)(cid:36) (cid:39)(cid:36)(cid:55)(cid:36) (cid:54)(cid:55)(cid:50)(cid:51) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:21)(cid:21) Fig 12. Access time for read/write operations Because of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted. As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time will increment between the two accesses. A similar problem exists when reading. A roll-over may occur between reads thus giving the minutes from one moment and the hours from the next. Recommended method for reading the time: 1. Send a START condition and the slave address (see Table29 on page25) for write (A2h) 2. Set the address pointer to 4 (Seconds) by sending 04h 3. Send a RESTART condition or STOP followed by START 4. Send the slave address for read (A3h) 5. Read Seconds 6. Read Minutes 7. Read Hours 8. Read Days 9. Read Weekdays 10. Read Months 11. Read Years 12. Send a STOP condition PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 22 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 9. Characteristics of the I2C-bus interface The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time are interpreted as a control signal (see Figure13). (cid:54)(cid:39)(cid:36) (cid:54)(cid:38)(cid:47) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72)(cid:3) (cid:70)(cid:75)(cid:68)(cid:81)(cid:74)(cid:72)(cid:3) (cid:86)(cid:87)(cid:68)(cid:69)(cid:79)(cid:72)(cid:30)(cid:3) (cid:82)(cid:73)(cid:3)(cid:71)(cid:68)(cid:87)(cid:68)(cid:3) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:89)(cid:68)(cid:79)(cid:76)(cid:71) (cid:68)(cid:79)(cid:79)(cid:82)(cid:90)(cid:72)(cid:71) (cid:80)(cid:69)(cid:70)(cid:25)(cid:21)(cid:20) Fig 13. Bit transfer 9.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. ALOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure14). (cid:54)(cid:39)(cid:36) (cid:54)(cid:39)(cid:36) (cid:54)(cid:38)(cid:47) (cid:54)(cid:38)(cid:47) (cid:54) (cid:51) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55)(cid:3)(cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81) (cid:54)(cid:55)(cid:50)(cid:51)(cid:3)(cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81) (cid:80)(cid:69)(cid:70)(cid:25)(cid:21)(cid:21) Fig 14. Definition of START and STOP conditions 9.3 System configuration A device generating a message is a transmitter; a device receiving a message is a receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves (see Figure15). PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 23 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:48)(cid:36)(cid:54)(cid:55)(cid:40)(cid:53)(cid:3) (cid:54)(cid:47)(cid:36)(cid:57)(cid:40)(cid:3) (cid:48)(cid:36)(cid:54)(cid:55)(cid:40)(cid:53)(cid:3) (cid:54)(cid:47)(cid:36)(cid:57)(cid:40)(cid:3) (cid:48)(cid:36)(cid:54)(cid:55)(cid:40)(cid:53)(cid:3) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53)(cid:18)(cid:3) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53)(cid:18)(cid:3) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53)(cid:18)(cid:3) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:54)(cid:39)(cid:36) (cid:54)(cid:38)(cid:47) (cid:80)(cid:74)(cid:68)(cid:27)(cid:19)(cid:26) Fig 15. System configuration 9.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered) • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition Acknowledgement on the I2C-bus is shown in Figure16. (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:82)(cid:88)(cid:87)(cid:83)(cid:88)(cid:87)(cid:3) (cid:69)(cid:92)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87)(cid:87)(cid:72)(cid:85) (cid:81)(cid:82)(cid:87)(cid:3)(cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:82)(cid:88)(cid:87)(cid:83)(cid:88)(cid:87)(cid:3) (cid:69)(cid:92)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:85) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:54)(cid:38)(cid:47)(cid:3)(cid:73)(cid:85)(cid:82)(cid:80)(cid:3) (cid:20) (cid:21) (cid:27) (cid:28) (cid:80)(cid:68)(cid:86)(cid:87)(cid:72)(cid:85) (cid:54) (cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:83)(cid:88)(cid:79)(cid:86)(cid:72)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55)(cid:3) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81) (cid:80)(cid:69)(cid:70)(cid:25)(cid:19)(cid:21) Fig 16. Acknowledgement on the I2C-bus PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 24 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 9.5 I2C-bus protocol 9.5.1 Addressing One I2C-bus slave address (1010001) is reserved for the PCF85063TP. The entire I2C-bus slave address byte is shown in Table29. Table 29. I2C slave address byte Slave address Bit 7 6 5 4 3 2 1 0 MSB LSB 1 0 1 0 0 0 1 R/W After a START condition, the I2C slave address has to be sent to the PCF85063TP device. The R/W bit defines the direction of the following single or multiple byte data transfer (R/W=0for writing, R/W=1for reading). For the format and the timing of the START condition (S), the STOP condition (P) and the acknowledge bit (A) refer to the I2C-bus characteristics (see Ref. 12 “UM10204”). In the write mode, a data transfer is terminated by sending either the STOP condition or the START condition of the next data transfer. 9.5.2 Clock and calendar READ or WRITE cycles The I2C-bus configuration for the different PCF85063TP READ and WRITE cycles is shown in Figure17 and Figure18. The register address is a 4-bit value that defines which register will be accessed next. The upper 4 bits of the register address are not used. (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:73)(cid:85)(cid:82)(cid:80)(cid:3)(cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:73)(cid:85)(cid:82)(cid:80)(cid:3)(cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:73)(cid:85)(cid:82)(cid:80)(cid:3)(cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:54) (cid:20) (cid:19) (cid:20) (cid:19) (cid:19) (cid:19) (cid:20) (cid:19) (cid:36) (cid:36) (cid:36) (cid:51)(cid:18)(cid:54) (cid:86)(cid:79)(cid:68)(cid:89)(cid:72)(cid:3)(cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:90)(cid:85)(cid:76)(cid:87)(cid:72)(cid:3)(cid:69)(cid:76)(cid:87) (cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:3)(cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:19)(cid:3)(cid:87)(cid:82)(cid:3)(cid:81) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55)(cid:18) (cid:19)(cid:19)(cid:75)(cid:3)(cid:87)(cid:82)(cid:3)(cid:19)(cid:36)(cid:75) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:69)(cid:92)(cid:87)(cid:72)(cid:86) (cid:54)(cid:55)(cid:50)(cid:51) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:21)(cid:22) Fig 17. Master transmits to slave receiver (WRITE mode) PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 25 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:73)(cid:85)(cid:82)(cid:80)(cid:3)(cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:73)(cid:85)(cid:82)(cid:80)(cid:3)(cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:86)(cid:72)(cid:87)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85) (cid:54) (cid:20) (cid:19) (cid:20) (cid:19) (cid:19) (cid:19) (cid:20) (cid:19) (cid:36) (cid:36) (cid:51) (cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:86)(cid:79)(cid:68)(cid:89)(cid:72)(cid:3)(cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:90)(cid:85)(cid:76)(cid:87)(cid:72)(cid:3)(cid:69)(cid:76)(cid:87) (cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:3)(cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:54)(cid:55)(cid:50)(cid:51) (cid:19)(cid:19)(cid:75)(cid:3)(cid:87)(cid:82)(cid:3)(cid:19)(cid:36)(cid:75) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:73)(cid:85)(cid:82)(cid:80)(cid:3)(cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:73)(cid:85)(cid:82)(cid:80)(cid:3)(cid:80)(cid:68)(cid:86)(cid:87)(cid:72)(cid:85) (cid:81)(cid:82)(cid:3)(cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:85)(cid:72)(cid:68)(cid:71)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85) (cid:54) (cid:20) (cid:19) (cid:20) (cid:19) (cid:19) (cid:19) (cid:20) (cid:20) (cid:36) (cid:39)(cid:36)(cid:55)(cid:36)(cid:3)(cid:37)(cid:60)(cid:55)(cid:40) (cid:36) (cid:47)(cid:36)(cid:54)(cid:55)(cid:3)(cid:39)(cid:36)(cid:55)(cid:36)(cid:3)(cid:37)(cid:60)(cid:55)(cid:40) (cid:36) (cid:51) (cid:71)(cid:68)(cid:87)(cid:68) (cid:86)(cid:79)(cid:68)(cid:89)(cid:72)(cid:3)(cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:85)(cid:72)(cid:68)(cid:71)(cid:3)(cid:69)(cid:76)(cid:87) (cid:19)(cid:3)(cid:87)(cid:82)(cid:3)(cid:81)(cid:3)(cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:69)(cid:92)(cid:87)(cid:72)(cid:86) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:21)(cid:23) (cid:68)(cid:88)(cid:87)(cid:82)(cid:3)(cid:76)(cid:81)(cid:70)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:68)(cid:88)(cid:87)(cid:82)(cid:3)(cid:76)(cid:81)(cid:70)(cid:85)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:3)(cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) (cid:80)(cid:72)(cid:80)(cid:82)(cid:85)(cid:92)(cid:3)(cid:85)(cid:72)(cid:74)(cid:76)(cid:86)(cid:87)(cid:72)(cid:85)(cid:3)(cid:68)(cid:71)(cid:71)(cid:85)(cid:72)(cid:86)(cid:86) For multimaster configurations and to fasten the communication, the STOP-START sequence can be replaced by a repeated START (Sr). Fig 18. Master reads after setting register address (WRITE register address; READ data) PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 26 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 10. Internal circuitry (cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:57)(cid:39)(cid:39) (cid:50)(cid:54)(cid:38)(cid:44) (cid:38)(cid:47)(cid:46)(cid:50)(cid:56)(cid:55) (cid:50)(cid:54)(cid:38)(cid:50) (cid:54)(cid:38)(cid:47) (cid:44)(cid:49)(cid:55) (cid:54)(cid:39)(cid:36) (cid:57)(cid:54)(cid:54) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:21)(cid:24) Fig 19. Device diode protection diagram of PCF85063TP 11. Safety notes CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST61340-5, JESD625-A or equivalent standards. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 27 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 12. Limiting values Table 30. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +6.5 V DD I supply current 50 +50 mA DD V input voltage on pinsSCL, SDA, OSCI 0.5 +6.5 V I V output voltage 0.5 +6.5 V O I input current at any input 10 +10 mA I I output current at any output 10 +10 mA O P total power dissipation - 300 mW tot V electrostatic discharge HBM [1] - 5000 V ESD voltage CDM [2] - 1500 V I latch-up current [3] - 200 mA lu T storage temperature [4] 65 +150 C stg T ambient temperature operating device 40 +85 C amb [1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”. [2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”. [3] Pass level; latch-up testing, according to Ref. 9 “JESD78” at maximum ambient temperature (T ). amb(max) [4] According to the store and transport requirements (see Ref. 14 “UM10569”) the devices have to be stored at a temperature of +8C to +45C and a humidity of 25% to 75%. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 28 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 13. Characteristics Table 31. Static charac teristics V =0.9V to 5.5V; V =0V; T =40C to +85C; f =32.768kHz; quartz R =60k; C =7pF; unless otherwise DD SS amb osc s L specified. Symbol Parameter Conditions Min Typ Max Unit Supplies V supply voltage interface inactive; [1] 0.9 - 5.5 V DD f =0Hz SCL interface active; [1] 1.8 - 5.5 V f =400kHz SCL I supply current V =3.3V [2] DD DD interface inactive; f =0Hz SCL T =25C - 220 450 nA amb T =50C [3] - 250 500 nA amb T =85C - 470 600 nA amb interface active; - 18 50 A f =400kHz SCL Inputs[4] V input voltage V - 5.5 V I SS V LOW-level input voltage V - 0.3V V IL SS DD V HIGH-level input voltage 0.7V - V V IH DD DD I input leakage current V = V or V - 0 - A LI I SS DD post ESD event 0.15 - +0.15 A C input capacitance [5] - - 7 pF i Outputs V HIGH-level output voltage on pin CLKOUT 0.8V - V V OH DD DD V LOW-level output voltage on pins SDA, INT, V - 0.2V V OL SS DD CLKOUT I HIGH-level output current output source current; 1 3 - mA OH V = 2.9 V; OH V = 3.3 V; DD on pin CLKOUT I LOW-level output current output sink current; OL V =0.4V; OL V =3.3V DD on pin SDA 3 8.5 - mA on pin INT 2 6 - mA on pin CLKOUT 1 3 - mA PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 29 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar Table 31. Static characteristics …continued V =0.9V to 5.5V; V =0V; T =40C to +85C; f =32.768kHz; quartz R =60k; C =7pF; unless otherwise DD SS amb osc s L specified. Symbol Parameter Conditions Min Typ Max Unit Oscillator f /f relative oscillator frequency V =200mV; - 0.075 - ppm osc osc DD variation T =25C amb C integrated load capacitance on pins OSCO, OSCI [6] L(itg) C =7pF 4.2 7 9.8 pF L C =12.5pF 7.5 12.5 17.5 pF L R series resistance - - 100 k s [1] For reliable oscillator start-up at power-on: V =V +0.3V. DD(po)min DD(min) [2] Timer source clock=1⁄ Hz, level of pinsSCL andSDA is V or V . 60 DD SS [3] Tested on sample basis. [4] The I2C-bus interface of PCF85063TP is 5V tolerant. [5] Implicit by design. C C  [6] Integrated load capacitance, C , is a calculation of C and C in series: C = --------O----S---C---I----------O----S---C---O------. L(itg) OSCI OSCO Litg C +C  OSCI OSCO (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:24)(cid:26)(cid:23)(cid:19) (cid:24)(cid:19) (cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:11)(cid:11)(cid:11)(cid:151)(cid:151)(cid:151)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:23)(cid:19) (cid:22)(cid:19) (cid:11)(cid:20)(cid:12) (cid:21)(cid:19) (cid:11)(cid:21)(cid:12) (cid:20)(cid:19) (cid:19) (cid:19) (cid:20)(cid:19)(cid:19) (cid:21)(cid:19)(cid:19) (cid:22)(cid:19)(cid:19) (cid:23)(cid:19)(cid:19) (cid:24)(cid:19)(cid:19) (cid:73)(cid:54)(cid:38)(cid:47)(cid:3)(cid:11)(cid:78)(cid:43)(cid:93)(cid:12) Tamb=25C; CLKOUT disabled. (1) VDD=5.0V. (2) VDD=3.3V. Fig 20. Typical I with respect to f DD SCL PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 30 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:24)(cid:26)(cid:22)(cid:26) (cid:27)(cid:19)(cid:19) (cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:11)(cid:11)(cid:11)(cid:81)(cid:81)(cid:81)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:25)(cid:19)(cid:19) (cid:23)(cid:19)(cid:19) (cid:11)(cid:20)(cid:12) (cid:11)(cid:21)(cid:12) (cid:21)(cid:19)(cid:19) (cid:19) (cid:16)(cid:24)(cid:19) (cid:16)(cid:22)(cid:19) (cid:16)(cid:20)(cid:19) (cid:20)(cid:19) (cid:22)(cid:19) (cid:24)(cid:19) (cid:26)(cid:19) (cid:28)(cid:19) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:11)(cid:158)(cid:38)(cid:12) C =7pF; CLKOUT disabled. L(itg) (1) V =5.5V. DD (2) VDD=3.3V. (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:24)(cid:26)(cid:22)(cid:27) (cid:20)(cid:19)(cid:19)(cid:19) (cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:11)(cid:11)(cid:11)(cid:81)(cid:81)(cid:81)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:27)(cid:19)(cid:19) (cid:25)(cid:19)(cid:19) (cid:11)(cid:20)(cid:12) (cid:23)(cid:19)(cid:19) (cid:11)(cid:21)(cid:12) (cid:21)(cid:19)(cid:19) (cid:19) (cid:16)(cid:24)(cid:19) (cid:16)(cid:22)(cid:19) (cid:16)(cid:20)(cid:19) (cid:20)(cid:19) (cid:22)(cid:19) (cid:24)(cid:19) (cid:26)(cid:19) (cid:28)(cid:19) (cid:55)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:11)(cid:158)(cid:38)(cid:12) CL(itg)=12.5pF; CLKOUT disabled. (1) VDD=5.5V. (2) VDD=3.3V. Fig 21. Typical I as a function of temperature DD PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 31 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:24)(cid:26)(cid:22)(cid:28) (cid:20)(cid:21) (cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:11)(cid:11)(cid:11)(cid:151)(cid:151)(cid:151)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:20)(cid:19) (cid:11)(cid:11)(cid:20)(cid:20)(cid:12)(cid:12) (cid:11)(cid:11)(cid:21)(cid:21)(cid:12)(cid:12) (cid:27) (cid:11)(cid:20)(cid:12) (cid:25) (cid:11)(cid:21)(cid:12) (cid:23) (cid:21) (cid:19) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:11)(cid:57)(cid:12) Tamb=25C; fCLKOUT=32768 Hz. (1) 47pF CLKOUT load. (2) 22pF CLKOUT load. (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:24)(cid:26)(cid:23)(cid:20) (cid:24)(cid:19)(cid:19) (cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:11)(cid:11)(cid:11)(cid:81)(cid:81)(cid:81)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:23)(cid:19)(cid:19) (cid:22)(cid:19)(cid:19) (cid:11)(cid:20)(cid:12) (cid:11)(cid:21)(cid:12) (cid:21)(cid:19)(cid:19) (cid:20)(cid:19)(cid:19) (cid:19) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:11)(cid:57)(cid:12) Tamb=25C; CLKOUT disabled. (1) CL(itg)=12.5pF. (2) CL(itg)=7pF. Fig 22. Typical I with respect to V DD DD PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 32 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:24)(cid:27)(cid:23)(cid:20) (cid:27)(cid:19)(cid:19) (cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:11)(cid:11)(cid:11)(cid:81)(cid:81)(cid:81)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:11)(cid:11)(cid:11)(cid:20)(cid:20)(cid:20)(cid:12)(cid:12)(cid:12) (cid:25)(cid:19)(cid:19) (cid:11)(cid:11)(cid:11)(cid:21)(cid:21)(cid:21)(cid:12)(cid:12)(cid:12) (cid:23)(cid:19)(cid:19) (cid:11)(cid:11)(cid:11)(cid:22)(cid:22)(cid:22)(cid:12)(cid:12)(cid:12) (cid:11)(cid:11)(cid:11)(cid:23)(cid:23)(cid:23)(cid:12)(cid:12)(cid:12) (cid:21)(cid:19)(cid:19) (cid:19) (cid:21)(cid:19) (cid:22)(cid:19) (cid:23)(cid:19) (cid:24)(cid:19) (cid:25)(cid:19) (cid:26)(cid:19) (cid:27)(cid:19) (cid:28)(cid:19) (cid:20)(cid:19)(cid:19) (cid:53)(cid:54)(cid:3)(cid:11)(cid:78)(cid:159)(cid:12) V =3.3V; CLKOUT disabled. DD (1) CL(itg)=12.5pF; 50C; maximum value. (2) CL(itg)=7pF; 50 C; maximum value. (3) CL(itg)=12.5pF; 25C; typical value. (4) CL(itg)=7pF; 25 C; typical value. Fig 23. I with respect to quartz R DD S (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:24)(cid:26)(cid:23)(cid:22) (cid:22) (cid:507)(cid:507)(cid:507)(cid:73)(cid:73)(cid:73)(cid:82)(cid:82)(cid:82)(cid:86)(cid:86)(cid:86)(cid:70)(cid:70)(cid:70) (cid:11)(cid:11)(cid:11)(cid:83)(cid:83)(cid:83)(cid:83)(cid:83)(cid:83)(cid:80)(cid:80)(cid:80)(cid:12)(cid:12)(cid:12) (cid:20)(cid:17)(cid:24) (cid:19) (cid:11)(cid:20)(cid:12) (cid:11)(cid:21)(cid:12) (cid:16)(cid:20)(cid:17)(cid:24) (cid:16)(cid:22) (cid:19) (cid:20) (cid:21) (cid:22) (cid:23) (cid:24) (cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:11)(cid:57)(cid:12) Tamb=25C. (1) CL(itg)=7pF. (2) CL(itg)=12.5pF. Fig 24. Oscillator frequency variation with respect to V DD PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 33 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar Table 32. I2C-bus char acteristics V =1.8V to 5.5V; V =0V; T =40C to +85C; f =32.768kHz; quartz R =60k; C =7pF; unless otherwise DD SS amb osc s L specified. All timing values are valid within the operating supply voltage and temperature range and referenced to V and V IL IH with an input voltage swing of V to V [1]. SS DD Symbol Parameter Conditions Min Max Unit C capacitive load for - 400 pF b each bus line f SCL clock frequency [2] 0 400 kHz SCL t hold time (repeated) 0.6 - s HD;STA START condition t set-up time for a 0.6 - s SU;STA repeated START condition t LOW period of the 1.3 - s LOW SCL clock t HIGH period of the 0.6 - s HIGH SCL clock t rise time of both SDA 20 300 ns r and SCL signals t fall time of both SDA [3][4] 20 (V /5.5V) 300 ns f DD and SCL signals t bus free time between 1.3 - s BUF a STOP and START condition t data set-up time 100 - ns SU;DAT t data hold time 0 - ns HD;DAT t set-up time for STOP 0.6 - s SU;STO condition t data valid time 0 0.9 s VD;DAT t data valid 0 0.9 s VD;ACK acknowledge time t pulse width of spikes 0 50 ns SP that must be suppressed by the input filter [1] A detailed description of the I2C-bus specification is given in Ref. 12 “UM10204”. [2] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second. [3] A device must internally provide a hold time of at least 300ns for the SDA signal (with respect to the V of the SCL signal) to bridge IH(min) the undefined region of the falling edge of SCL. [4] The maximum t for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t is specified at f f 250ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t. f PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 34 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:54)(cid:55)(cid:36)(cid:53)(cid:55)(cid:3) (cid:69)(cid:76)(cid:87)(cid:3)(cid:26)(cid:3) (cid:54)(cid:55)(cid:50)(cid:51)(cid:3) (cid:69)(cid:76)(cid:87)(cid:3)(cid:25)(cid:3) (cid:69)(cid:76)(cid:87)(cid:3)(cid:19)(cid:3) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72)(cid:3) (cid:83)(cid:85)(cid:82)(cid:87)(cid:82)(cid:70)(cid:82)(cid:79) (cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:48)(cid:54)(cid:37)(cid:3) (cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3) (cid:11)(cid:36)(cid:25)(cid:12) (cid:11)(cid:53)(cid:18)(cid:58)(cid:12) (cid:11)(cid:36)(cid:12) (cid:11)(cid:54)(cid:12) (cid:11)(cid:36)(cid:26)(cid:12) (cid:11)(cid:51)(cid:12) (cid:87)(cid:54)(cid:56)(cid:30)(cid:54)(cid:55)(cid:36) (cid:87)(cid:47)(cid:50)(cid:58) (cid:87)(cid:43)(cid:44)(cid:42)(cid:43) (cid:20)(cid:18)(cid:73)(cid:54)(cid:38)(cid:47) (cid:54)(cid:38)(cid:47) (cid:87)(cid:37)(cid:56)(cid:41) (cid:87)(cid:73) (cid:87)(cid:85) (cid:54)(cid:39)(cid:36) (cid:87)(cid:43)(cid:39)(cid:30)(cid:54)(cid:55)(cid:36) (cid:87)(cid:54)(cid:56)(cid:30)(cid:39)(cid:36)(cid:55) (cid:87)(cid:43)(cid:39)(cid:30)(cid:39)(cid:36)(cid:55) (cid:87)(cid:57)(cid:39)(cid:30)(cid:39)(cid:36)(cid:55) (cid:87)(cid:57)(cid:39)(cid:30)(cid:36)(cid:38)(cid:46) (cid:87)(cid:54)(cid:56)(cid:30)(cid:54)(cid:55)(cid:50) (cid:3)(cid:19)(cid:20)(cid:22)(cid:68)(cid:68)(cid:68)(cid:23)(cid:20)(cid:26) Fig 25. I2C-bus timing diagram; rise and fall times refer to 30% and 70% PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 35 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 14. Application information (cid:57)(cid:39)(cid:39) (cid:54)(cid:39)(cid:36) (cid:48)(cid:36)(cid:54)(cid:55)(cid:40)(cid:53) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53)(cid:18) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:54)(cid:38)(cid:47) (cid:20)(cid:3)(cid:41) (cid:20)(cid:19)(cid:19)(cid:3)(cid:81)(cid:41) (cid:57)(cid:39)(cid:39) (cid:44)(cid:49)(cid:55) (cid:54)(cid:38)(cid:47) (cid:50)(cid:54)(cid:38)(cid:44) (cid:57)(cid:39)(cid:39) (cid:51)(cid:38)(cid:41)(cid:27)(cid:24)(cid:19)(cid:25)(cid:22)(cid:55)(cid:51) (cid:50)(cid:54)(cid:38)(cid:50) (cid:54)(cid:39)(cid:36) (cid:53) (cid:53) (cid:53)(cid:29)(cid:3)(cid:83)(cid:88)(cid:79)(cid:79)(cid:16)(cid:88)(cid:83)(cid:3)(cid:85)(cid:72)(cid:86)(cid:76)(cid:86)(cid:87)(cid:82)(cid:85) (cid:57)(cid:54)(cid:54) (cid:87)(cid:85) (cid:53)(cid:3)(cid:32) (cid:38)(cid:69) (cid:54)(cid:39)(cid:36) (cid:54)(cid:38)(cid:47) (cid:11)(cid:44)(cid:21)(cid:38)(cid:16)(cid:69)(cid:88)(cid:86)(cid:12) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:23)(cid:23)(cid:21)(cid:26) A 1 farad super capacitor combined with a low V diode can be used as a standby or back-up F supply. With the RTC in its minimum power configuration i.e. timer off and CLKOUT off, the RTC may operate for weeks. Fig 26. Application diagram for PCF85063TP PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 36 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 15. Package outline (cid:43)(cid:58)(cid:54)(cid:50)(cid:49)(cid:27)(cid:29)(cid:3)(cid:83)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:3)(cid:87)(cid:75)(cid:72)(cid:85)(cid:80)(cid:68)(cid:79)(cid:3)(cid:72)(cid:81)(cid:75)(cid:68)(cid:81)(cid:70)(cid:72)(cid:71)(cid:3)(cid:89)(cid:72)(cid:85)(cid:92)(cid:3)(cid:89)(cid:72)(cid:85)(cid:92)(cid:3)(cid:87)(cid:75)(cid:76)(cid:81)(cid:3)(cid:86)(cid:80)(cid:68)(cid:79)(cid:79)(cid:3)(cid:82)(cid:88)(cid:87)(cid:79)(cid:76)(cid:81)(cid:72)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:30)(cid:3)(cid:81)(cid:82)(cid:3)(cid:79)(cid:72)(cid:68)(cid:71)(cid:86)(cid:30) (cid:27)(cid:3)(cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:86)(cid:30)(cid:3)(cid:69)(cid:82)(cid:71)(cid:92)(cid:3)(cid:21)(cid:3)(cid:91)(cid:3)(cid:22)(cid:3)(cid:91)(cid:3)(cid:19)(cid:17)(cid:26)(cid:24)(cid:3)(cid:80)(cid:80) (cid:54)(cid:50)(cid:55)(cid:20)(cid:19)(cid:25)(cid:28)(cid:16)(cid:21) (cid:59) (cid:39) (cid:37) (cid:36) (cid:36)(cid:21) (cid:40) (cid:36) (cid:36)(cid:20) (cid:36)(cid:22) (cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:20) (cid:71)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:59) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:72)(cid:20) (cid:38) (cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:20) (cid:89) (cid:38) (cid:36) (cid:37) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:72) (cid:69) (cid:90) (cid:38) (cid:92)(cid:20)(cid:38) (cid:92) (cid:20) (cid:23) (cid:47) (cid:46) (cid:40)(cid:21) (cid:27) (cid:24) (cid:39)(cid:21) (cid:19) (cid:20) (cid:21)(cid:3)(cid:80)(cid:80) (cid:86)(cid:70)(cid:68)(cid:79)(cid:72) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86) (cid:56)(cid:81)(cid:76)(cid:87) (cid:36)(cid:11)(cid:20)(cid:12) (cid:36)(cid:20) (cid:36)(cid:21) (cid:36)(cid:22) (cid:69) (cid:39)(cid:11)(cid:20)(cid:12) (cid:39)(cid:21) (cid:40)(cid:11)(cid:20)(cid:12) (cid:40)(cid:21) (cid:72) (cid:72)(cid:20) (cid:46) (cid:47) (cid:89) (cid:90) (cid:92) (cid:92)(cid:20) (cid:80)(cid:68)(cid:91) (cid:19)(cid:17)(cid:27)(cid:19) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:25)(cid:24) (cid:19)(cid:17)(cid:22)(cid:19) (cid:21)(cid:17)(cid:20) (cid:20)(cid:17)(cid:25) (cid:22)(cid:17)(cid:20) (cid:20)(cid:17)(cid:25) (cid:19)(cid:17)(cid:23)(cid:19) (cid:19)(cid:17)(cid:23)(cid:24) (cid:80)(cid:80) (cid:81)(cid:82)(cid:80) (cid:19)(cid:17)(cid:26)(cid:24) (cid:19)(cid:17)(cid:19)(cid:21) (cid:19)(cid:17)(cid:24)(cid:24) (cid:19)(cid:17)(cid:21) (cid:19)(cid:17)(cid:21)(cid:24) (cid:21)(cid:17)(cid:19) (cid:20)(cid:17)(cid:24) (cid:22)(cid:17)(cid:19) (cid:20)(cid:17)(cid:24) (cid:19)(cid:17)(cid:24) (cid:20)(cid:17)(cid:24) (cid:19)(cid:17)(cid:22)(cid:24) (cid:19)(cid:17)(cid:23)(cid:19) (cid:19)(cid:17)(cid:20) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:19)(cid:24) (cid:80)(cid:76)(cid:81) (cid:19)(cid:17)(cid:26)(cid:19) (cid:19)(cid:17)(cid:19)(cid:19) (cid:19)(cid:17)(cid:23)(cid:24) (cid:19)(cid:17)(cid:20)(cid:27) (cid:20)(cid:17)(cid:28) (cid:20)(cid:17)(cid:23) (cid:21)(cid:17)(cid:28) (cid:20)(cid:17)(cid:23) (cid:19)(cid:17)(cid:22)(cid:19) (cid:19)(cid:17)(cid:22)(cid:24) (cid:49)(cid:82)(cid:87)(cid:72) (cid:20)(cid:17)(cid:3)(cid:51)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:3)(cid:82)(cid:85)(cid:3)(cid:80)(cid:72)(cid:87)(cid:68)(cid:79)(cid:3)(cid:83)(cid:85)(cid:82)(cid:87)(cid:85)(cid:88)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:82)(cid:73)(cid:3)(cid:19)(cid:17)(cid:19)(cid:26)(cid:24)(cid:3)(cid:80)(cid:80)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:83)(cid:72)(cid:85)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72)(cid:3)(cid:68)(cid:85)(cid:72)(cid:3)(cid:81)(cid:82)(cid:87)(cid:3)(cid:76)(cid:81)(cid:70)(cid:79)(cid:88)(cid:71)(cid:72)(cid:71)(cid:17) (cid:86)(cid:82)(cid:87)(cid:20)(cid:19)(cid:25)(cid:28)(cid:16)(cid:21)(cid:66)(cid:83)(cid:82) (cid:50)(cid:88)(cid:87)(cid:79)(cid:76)(cid:81)(cid:72) (cid:53)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72)(cid:86) (cid:40)(cid:88)(cid:85)(cid:82)(cid:83)(cid:72)(cid:68)(cid:81) (cid:44)(cid:86)(cid:86)(cid:88)(cid:72)(cid:3)(cid:71)(cid:68)(cid:87)(cid:72) (cid:89)(cid:72)(cid:85)(cid:86)(cid:76)(cid:82)(cid:81) (cid:44)(cid:40)(cid:38) (cid:45)(cid:40)(cid:39)(cid:40)(cid:38) (cid:45)(cid:40)(cid:44)(cid:55)(cid:36) (cid:83)(cid:85)(cid:82)(cid:77)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81) (cid:19)(cid:28)(cid:16)(cid:20)(cid:20)(cid:16)(cid:20)(cid:27) (cid:54)(cid:50)(cid:55)(cid:20)(cid:19)(cid:25)(cid:28)(cid:16)(cid:21) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:48)(cid:50)(cid:16)(cid:21)(cid:21)(cid:28) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:20)(cid:21)(cid:16)(cid:19)(cid:23)(cid:16)(cid:20)(cid:27) Fig 27. Package outline SOT1069-2 (HWSON8) of PCF85063TP PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 37 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent standards. 17. Packing information 17.1 Tape and reel information For tape and reel packing information, see Ref. 11 “SOT1069-2_147”. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 38 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 39 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure28) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table33 and34 Table 33. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 34. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure28. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 40 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Footprint information PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 41 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar (cid:41)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87)(cid:3)(cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:85)(cid:72)(cid:73)(cid:79)(cid:82)(cid:90)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:73)(cid:3)(cid:43)(cid:58)(cid:54)(cid:50)(cid:49)(cid:27)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72) (cid:54)(cid:50)(cid:55)(cid:20)(cid:19)(cid:25)(cid:28)(cid:16)(cid:21) (cid:42)(cid:91) (cid:39) (cid:51) (cid:38) (cid:81)(cid:54)(cid:51)(cid:91) (cid:43)(cid:92) (cid:42)(cid:92) (cid:54)(cid:51)(cid:92)(cid:3) (cid:54)(cid:47)(cid:92) (cid:37)(cid:92) (cid:36)(cid:92) (cid:81)(cid:54)(cid:51)(cid:92) (cid:54)(cid:51)(cid:91)(cid:3) (cid:54)(cid:47)(cid:91) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:83)(cid:68)(cid:86)(cid:87)(cid:72)(cid:3)(cid:71)(cid:72)(cid:83)(cid:82)(cid:86)(cid:76)(cid:87) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71)(cid:3)(cid:83)(cid:79)(cid:88)(cid:86)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:83)(cid:68)(cid:86)(cid:87)(cid:72) (cid:82)(cid:70)(cid:70)(cid:88)(cid:83)(cid:76)(cid:72)(cid:71)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:39)(cid:44)(cid:48)(cid:40)(cid:49)(cid:54)(cid:44)(cid:50)(cid:49)(cid:54)(cid:3)(cid:76)(cid:81)(cid:3)(cid:80)(cid:80) (cid:51) (cid:36)(cid:92) (cid:37)(cid:92) (cid:38) (cid:39) (cid:54)(cid:47)(cid:91) (cid:54)(cid:47)(cid:92) (cid:54)(cid:51)(cid:91) (cid:54)(cid:51)(cid:92) (cid:42)(cid:91) (cid:42)(cid:92) (cid:43)(cid:92) (cid:81)(cid:54)(cid:51)(cid:91) (cid:81)(cid:54)(cid:51)(cid:92) (cid:19)(cid:17)(cid:24) (cid:22)(cid:17)(cid:23)(cid:24) (cid:21)(cid:17)(cid:21) (cid:19)(cid:17)(cid:25)(cid:21)(cid:24) (cid:19)(cid:17)(cid:21)(cid:24) (cid:20)(cid:17)(cid:25) (cid:20)(cid:17)(cid:25) (cid:19)(cid:17)(cid:25) (cid:19)(cid:17)(cid:25) (cid:21)(cid:17)(cid:21)(cid:24) (cid:22)(cid:17)(cid:21)(cid:24) (cid:22)(cid:17)(cid:26) (cid:20) (cid:20) (cid:20)(cid:21)(cid:16)(cid:19)(cid:21)(cid:16)(cid:19)(cid:28) (cid:44)(cid:86)(cid:86)(cid:88)(cid:72)(cid:3)(cid:71)(cid:68)(cid:87)(cid:72) (cid:86)(cid:82)(cid:87)(cid:20)(cid:19)(cid:25)(cid:28)(cid:16)(cid:21)(cid:66)(cid:73)(cid:85) (cid:20)(cid:21)(cid:16)(cid:19)(cid:21)(cid:16)(cid:21)(cid:21) Fig 29. Footprint information for reflow soldering of SOT1069-2 (HWSON8) of PCF85063TP PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 42 of 52

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P N roduct d CF85063TP 20. Appendix XP S ata 20.1 Real-Time Clock selection em sh ic ee Table 35. Selection of Real-Time Clocks o t n Type name Alarm, Timer, Interrupt Interface I , Battery Timestamp, AEC-Q100 Special features Packages d DD u Watchdog output typical (nA) backup tamper input compliant c t PCF85063TP - 1 I2C 220 - - - basic functions only, no HXSON8 o r alarm s PCF85063A X 1 I2C 220 - - - tiny package SO8, DFN2626-10, TSSOP8 PCF85063B X 1 SPI 220 - - - tiny package DFN2626-10 All inform PCF85263A X 2 I2C 230 X X - btimacek uspta,m stpo,p bwaatttecrhy 1⁄100s STSOS8O, TPS8S, OP10, Rev. 4 — 6 May 2015 ation provided in this document is subject to legal disclaim PPPPCCCCFFFF8828515532326366333ABB XXXX 1222 SISS2PPPCIII 122203330000 -XXX -XXX ---- l6b6bbtttoiiimmm44aaaw ccceeeBBekkk syyuuussstttppptttee aaap,,, mmm oRRssswtttpppAAooo,,,eMMppp bbbrwww aaa1aaattt0tttttteeeccc0rrrhhhyyyn 111A⁄⁄⁄111 i000n000 sss,, TDTDTDTDSSSSFFFFSSSSNNNNOOOO22226666PPPP2222111166660400----,,,,1111 TH0000SVSQOFPN81,6 ers. operation PCF8523 X 2 I2C 150 X - - lowest power 150nA in SO8, HVSON8, operation, FM+ 1MHz TSSOP14, WLCSP T PCF8563 X 1 I2C 250 - - - - SO8, TSSOP8, in y © HVSON10 R P N e XP PCA8565 X 1 I2C 600 - - grade 1 high robustness, TSSOP8, HVSON10 a C Semiconductors N.V. 2015. A PPCCAF88556645AA XX 11 II22CC 620500 -- -- -- TTiinnaattmmeeggbbrraattee44dd00 ooCCsscc ttiioollllaa 11ttoo22rr55 ccaaCCppss, WWLLCCSSPP l-Time Clock/c F8506 43 of 52 ll rights reserved. alendar 3TP

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P Table 35. Selection of Real-Time Clocks …continued N roduct d CF85063TP Type name AWlaatrcmh,d Toigmer, Ionutetprruutpt Interface ItDyDp,ical (nA) Bbaacttkeurpy Ttaimmpesetra imnppu,t AcoEmCp-Qli1a0n0t Special features Packages XP S ata PCF2127 X 1 I2C and 500 X X - temperature SO16 em sh SPI compensated, quartz built ic ee in, calibrated, 512 Byte o t RAM n d PCF2127A X 1 I2C and 500 X X - temperature SO20 u c SPI compensated, quartz built t o in, calibrated, 512 Byte r s RAM PCF2129 X 1 I2C and 500 X X - temperature SO16 SPI compensated, quartz built in, calibrated A ll inform PCF2129A X 1 SI2PCI and 500 X X - tceommppeernastuartee d, quartz built SO20 Rev. 4 — 6 May 2015 ation provided in this document is subject to legal disclaim PPCCAA221112295 XX 11 ISS2PPCII and 580200 X- X- ggrraaddee 31 ticiThnneoia,,gmmm hccbpaap relleoiirbbnbarr4sutaau0asttreetteenddC de ,st oqs ,u1a2r5tz bCuilt TSSOS1O6P14 ers. T in y © R P N e XP a C Sem l-T iconductors N.V. 2015. A ime Clock/c F8506 44 of 52 ll rights reserved. alendar 3TP

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 21. Abbreviations Table 36. Abbreviations Acronym Description BCD Binary Coded Decimal CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit LSB Least Significant Bit MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board POR Power-On Reset RTC Real-Time Clock SCL Serial CLock line SDA Serial DAta line SMD Surface Mount Device PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 45 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 22. References [1] AN10365 — Surface mount reflow soldering description [2] AN10366 — HVQFN application information [3] AN11247 — Improved timekeeping accuracy with PCF85063, PCF8523 and PCF2123 using an external temperature sensor [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [6] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [9] JESD78 — IC Latch-Up Test [10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [11] SOT1069-2_147 — HWSON8; Reel pack, SMD, 7", packing information [12] UM10204 — I2C-bus specification and user manual [13] UM10301 — User Manual for NXP Real Time Clocks PCF85x3, PCA8565 and PCF2123, PCA2125 [14] UM10569 — Store and transport requirements [15] UM10698 — User manual for I2C-bus RTC demo board OM11059A PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 46 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 23. Revision history Table 37. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF85063TP v.4 20150506 Product data sheet - PCF85063TP v.3 Modifications: • Corrected rise and fall time specification according to the I2C standard, see Table32 • Adjusted Section8.2.3 • Enhanced Section8.2.2.1 PCF85063TP v.3 20130711 Product data sheet - PCF85063TP v.2 PCF85063TP v.2 20130415 Product data sheet - PCF85063TP v.1 PCF85063TP v.1 20130122 Objective data sheet - - PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 47 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 24. Legal information 24.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 24.2 Definitions Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Draft — The document is a draft version only. The content is still under malfunction of an NXP Semiconductors product can reasonably be expected internal review and subject to formal approval, which may result in to result in personal injury, death or severe property or environmental modifications or additions. NXP Semiconductors does not give any damage. NXP Semiconductors and its suppliers accept no liability for representations or warranties as to the accuracy or completeness of inclusion and/or use of NXP Semiconductors products in such equipment or information included herein and shall have no liability for the consequences of applications and therefore such inclusion and/or use is at the customer’s own use of such information. risk. Short data sheet — A short data sheet is an extract from a full data sheet Applications — Applications that are described herein for any of these with the same product type number(s) and title. A short data sheet is intended products are for illustrative purposes only. NXP Semiconductors makes no for quick reference only and should not be relied upon to contain detailed and representation or warranty that such applications will be suitable for the full information. For detailed and full information see the relevant full data specified use without further testing or modification. sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their deemed to offer functions and qualities beyond those described in the applications and products. Product data sheet. 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NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC60134) will cause permanent source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in In no event shall NXP Semiconductors be liable for any indirect, incidental, the Recommended operating conditions section (if present) or the punitive, special or consequential damages (including - without limitation - lost Characteristics sections of this document is not warranted. Constant or profits, lost savings, business interruption, costs related to the removal or repeated exposure to limiting values will permanently and irreversibly affect replacement of any products or rework charges) whether or not such the quality and reliability of the device. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of NXP Semiconductors products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 48 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar Export control — This document as well as the item(s) described herein own risk, and (c) customer fully indemnifies NXP Semiconductors for any may be subject to export control regulations. Export might require a prior liability, damages or failed product claims resulting from customer design and authorization from competent authorities. use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, Translations — A non-English (translated) version of a document is for the product is not suitable for automotive use. It is neither qualified nor tested reference only. The English version shall prevail in case of any discrepancy in accordance with automotive testing or application requirements. NXP between the translated and English versions. Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 24.4 Trademarks In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks (a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP Semiconductors N.V. NXP Semiconductors’ specifications such use shall be solely at customer’s 25. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 49 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 26. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2 Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3 Table 5. Registers overview . . . . . . . . . . . . . . . . . . . . . .5 Table 6. Control_1 - control and status register 1 (address00h) bit description . . . . . . . . . . . . . . .6 Table 7. First increment of time circuits after STOP bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 8. Register reset values . . . . . . . . . . . . . . . . . . . .10 Table 9. Control_2 - control and status register 2 (address01h) bit description . . . . . . . . . . . . . .11 Table 10. Effect of bits MI and HMI on INT generation . .12 Table 11. CLKOUT frequency selection . . . . . . . . . . . . .12 Table 12. Offset - offset register (address02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 13. Offset values . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 14. Correction pulses for MODE=0 . . . . . . . . . . .14 Table 15. Effect of correction pulseson frequencies for MODE=0. . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 16. Correction pulses for MODE=1 . . . . . . . . . . .15 Table 17. Effect of correction pulseson frequencies for MODE=1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 18. RAM_byte - 8-bit RAM register (address 03h) bit description. . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 19. Seconds - seconds register (address04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 20. Seconds coded in BCD format . . . . . . . . . . . .18 Table 21. Minutes - minutes register (address05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 22. Hours - hours register (address06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 23. Days - days register (address07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 24. Weekdays - weekdays register (address08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 25. Weekday assignments. . . . . . . . . . . . . . . . . . .20 Table 26. Months - months register (address09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 27. Month assignmentsin BCD format. . . . . . . . . .20 Table 28. Years - years register (0Ah) bit description. . . .21 Table 29. I2C slave address byte . . . . . . . . . . . . . . . . . . .25 Table 30. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 31. Static characteristics . . . . . . . . . . . . . . . . . . . .29 Table 32. I2C-bus characteristics. . . . . . . . . . . . . . . . . . .34 Table 33. SnPb eutectic process (from J-STD-020D) . . .40 Table 34. Lead-free process (from J-STD-020D) . . . . . .40 Table 35. Selection of Real-Time Clocks. . . . . . . . . . . . .43 Table 36. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .45 Table 37. Revision history . . . . . . . . . . . . . . . . . . . . . . . .47 PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 50 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 27. Figures Fig 1. Block diagram of PCF85063TP. . . . . . . . . . . . . . .2 Fig 2. Pin configuration for HWSON8 (PCF85063TP). . .3 Fig 3. Handling address registers . . . . . . . . . . . . . . . . . .4 Fig 4. STOP bit functional diagram . . . . . . . . . . . . . . . . .8 Fig 5. STOP bit release timing. . . . . . . . . . . . . . . . . . . . .9 Fig 6. Software reset command. . . . . . . . . . . . . . . . . . .10 Fig 7. INT example for MI . . . . . . . . . . . . . . . . . . . . . . .11 Fig 8. Offset calibration calculation workflow. . . . . . . . .16 Fig 9. Result of offset calibration . . . . . . . . . . . . . . . . . .17 Fig 10. OS flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Fig 11. Data flow for the time function. . . . . . . . . . . . . . .21 Fig 12. Access time for read/write operations . . . . . . . . .22 Fig 13. Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Fig 14. Definition of START and STOP conditions. . . . . .23 Fig 15. System configuration. . . . . . . . . . . . . . . . . . . . . .24 Fig 16. Acknowledgement on the I2C-bus. . . . . . . . . . . .24 Fig 17. Master transmits to slave receiver (WRITE mode). . . . . . . . . . . . . . . . . . . . . . . . . . .25 Fig 18. Master reads after setting register address (WRITE register address; READ data) . . . . . . . .26 Fig 19. Device diode protection diagram of PCF85063TP. . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Fig 20. Typical I with respect to f . . . . . . . . . . . . . .30 DD SCL Fig 21. Typical I as a function of temperature . . . . . . .31 DD Fig 22. Typical I with respect to V . . . . . . . . . . . . . .32 DD DD Fig 23. I with respect to quartz R . . . . . . . . . . . . . . . .33 DD S Fig 24. Oscillator frequency variation with respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 DD Fig 25. I2C-bus timing diagram; rise and fall times refer to 30% and 70% . . . . . . . . . . . . . . . . . . . .35 Fig 26. Application diagram for PCF85063TP. . . . . . . . .36 Fig 27. Package outline SOT1069-2 (HWSON8) of PCF85063TP. . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Fig 28. Temperature profiles for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Fig 29. Footprint information for reflow soldering of SOT1069-2 (HWSON8) of PCF85063TP . . . . . .42 PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 6 May 2015 51 of 52

PCF85063TP NXP Semiconductors Tiny Real-Time Clock/calendar 28. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29 3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14 Application information . . . . . . . . . . . . . . . . . 36 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 37 4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2 16 Handling information . . . . . . . . . . . . . . . . . . . 38 5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 17 Packing information . . . . . . . . . . . . . . . . . . . . 38 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 17.1 Tape and reel information . . . . . . . . . . . . . . . 38 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 18 Soldering of SMD packages. . . . . . . . . . . . . . 39 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 18.1 Introduction to soldering. . . . . . . . . . . . . . . . . 39 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 18.2 Wave and reflow soldering. . . . . . . . . . . . . . . 39 8 Functional description . . . . . . . . . . . . . . . . . . . 4 18.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 39 8.1 Registers organization . . . . . . . . . . . . . . . . . . . 5 18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 40 8.2 Control registers. . . . . . . . . . . . . . . . . . . . . . . . 6 19 Footprint information . . . . . . . . . . . . . . . . . . . 41 8.2.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 6 20 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2.1.1 EXT_TEST: external clock test mode. . . . . . . . 7 20.1 Real-Time Clock selection. . . . . . . . . . . . . . . 43 8.2.1.2 STOP: STOP bit function . . . . . . . . . . . . . . . . . 8 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.2.1.3 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 10 22 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 11 8.2.2.1 MI and HMI: minute and half minute interrupt. 11 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . 47 8.2.2.2 TF: timer flag . . . . . . . . . . . . . . . . . . . . . . . . . 12 24 Legal information . . . . . . . . . . . . . . . . . . . . . . 48 8.2.2.3 COF[2:0]: Clock output frequency . . . . . . . . . 12 24.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 48 8.2.3 Register Offset . . . . . . . . . . . . . . . . . . . . . . . . 13 24.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2.3.1 Correction when MODE=0 . . . . . . . . . . . . . . 14 24.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2.3.2 Correction when MODE=1 . . . . . . . . . . . . . . 14 24.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.2.3.3 Offset calibration workflow . . . . . . . . . . . . . . . 16 25 Contact information . . . . . . . . . . . . . . . . . . . . 49 8.2.4 Register RAM_byte . . . . . . . . . . . . . . . . . . . . 17 26 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3 Time and date registers . . . . . . . . . . . . . . . . . 17 27 Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3.1 Register Seconds. . . . . . . . . . . . . . . . . . . . . . 17 8.3.1.1 OS: Oscillator stop . . . . . . . . . . . . . . . . . . . . . 18 28 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.3.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 19 8.3.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 19 8.3.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 19 8.3.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 19 8.3.6 Register Months. . . . . . . . . . . . . . . . . . . . . . . 20 8.3.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 21 8.4 Setting and reading the time. . . . . . . . . . . . . . 21 9 Characteristics of the I2C-bus interface . . . . 23 9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 START and STOP conditions. . . . . . . . . . . . . 23 9.3 System configuration . . . . . . . . . . . . . . . . . . . 23 9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.5 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 25 9.5.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.5.2 Clock and calendar READ or WRITE cycles . 25 10 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 27 11 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 May 2015 Document identifier: PCF85063TP

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: PCF85063TP/1,118 PCF85063TP/1Z