PCAL6408A Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers Rev. 3.2 — 19 April 2017 Product data sheet 1. General description The PCAL6408A is an 8-bit general-purpose I/O expander that provides remote I/O expansion for most microcontroller families via the I2C-bus interface. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, pushbuttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. The PCAL6408A has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/O voltages is required. Its wide V range of 1.65V to 5.5V on the dual power rail allows seamless DD communications with next-generation low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side. There are two supply voltages for PCAL6408A: V and V . V DD(I2C-bus) DD(P) DD(I2C-bus) provides the supply voltage for the interface at the master side (for example, a microcontroller) and the V provides the supply for core circuits and PortP. The DD(P) bidirectional voltage level translation in the PCAL6408A is provided through V . DD(I2C-bus) V should be connected to the V of the external SCL/SDA lines. This indicates DD(I2C-bus) DD the V level of the I2C-bus to the PCAL6408A, while the voltage level on PortP of the DD PCAL6408A is determined by the V . DD(P) The PCAL6408A contains the PCA6408A register set of 8-bit Configuration, Input, Output, and Polarity Inversion registers and additionally, the PCAL6408A has Agile I/O, which are additional features specifically designed to enhance the I/O. These additional features are: programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. The PCAL6408A is a pin-to-pin replacement to the PCA6408A, however, the PCAL6408A powers up with all I/O interrupts masked. This mask default allows for a board bring-up free of spurious interrupts at power-up. At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register, saving external logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete components.

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander The system master can reset the PCAL6408A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part. The PCAL6408A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. Thus, the PCAL6408A can remain a simple slave device. The input latch feature holds or latches the input pin state and keeps the logic values that created the interrupt until the master can service the interrupt. This minimizes the host’s interrupt service response for fast moving inputs. The device PortP outputs have 25mA sink capabilities for directly driving LEDs while consuming low device current. One hardware pin (ADDR) can be used to program and vary the fixed I2C-bus address and allow up to two devices to share the same I2C-bus or SMBus. 2. Features and benefits  I2C-bus to parallel port expander  Operating power supply voltage range of 1.65V to 5.5V  Allows bidirectional voltage-level translation and GPIO expansion between: 1.8V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V PortP 2.5V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V PortP 3.3V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V PortP 5V SCL/SDA and 1.8V, 2.5V, 3.3V or 5V PortP  Low standby current consumption of 1A  Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs V = 0.18V (typical) at 1.8V hys V = 0.25V (typical) at 2.5V hys V = 0.33V (typical) at 3.3V hys V = 0.5V (typical) at 5V hys  5V tolerant I/O ports  ActiveLOW reset input (RESET)  Open-drain activeLOW interrupt output (INT)  400kHz Fast-mode I2C-bus  Internal power-on reset  Power-up with all channels configured as inputs  No glitch on power-up  Noise filter on SCL/SDA inputs  Latched outputs with 25mA drive maximum capability for directly driving LEDs  Latch-up performance exceeds 100mA per JESD78, ClassII PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 2 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander  ESD protection exceeds JESD22 2000V Human-Body Model (A114-A) 1000V Charged-Device Model (C101)  Packages offered: HVQFN16, TSSOP16, XQFN16, XFBGA16(1.6mm1.6mm0.5mm), X2QFN16 (LGA, Land Grid Array) 1.6 mm x 1.6 mm x 0.35 mm 2.1 Agile I/O features  Software backward compatible with PCA6408A with interrupts disabled at power-up  Pin-to-pin drop-in replacement for PCA6408A  Output port configuration: bank selectable push-pull or open-drain output stages  Interrupt status: read-only register identifies the source of an interrupt  Bit-wise I/O programming features: Output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance applications Input latch: Input Port register values changes are kept until the Input Port register is read Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable Pull-up/pull-down selection: 100k pull-up/pull-down resistor selection Interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious interrupts 3. Ordering information Table 1. Ordering info rmation Type number Topside Package marking Name Description Version PCAL6408ABS L8A HVQFN16 plastic thermal enhanced very thin quad flat package; noleads; SOT758-1 16terminals; body330.85mm PCAL6408APW PL6408A TSSOP16 plastic thin shrink small outline package; 16leads; SOT403-1 bodywidth4.4mm PCAL6408AHK L8 XQFN16 plastic, extremely thin quad flat package; noleads; 16terminals; SOT1161-1 body1.802.600.50mm PCAL6408AEX L8 XFBGA16[1] plastic, extremely thin fine-pitch ball grid array package; 16balls; SOT1354-1 body1.61.60.5mm PCAL6408AEX1 18X[2] X2QFN16 plastic, thermal enhanced super thin land grid array or quad flat SOT1896-1 package; no leads; 16 terminals; body 1.6 1.6 0.35 mm [1] XFBGA16 package is discontinued with lifetime buy November 2016; new designs must use X2QFN16 package. [2] “X” rotates from 1 to 5 and indicates the work week of the indicated month PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 3 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 3.1 Ordering options Table 2. Ordering opt ions Type number Orderable Package Packing method Minimum Temperature partnumber orderquantity PCAL6408ABS PCAL6408ABSHP HVQFN16 Reel 13” Q2/T3 6000 T =40C to +85C amb *standardmark SMD PCAL6408APW PCAL6408APWJ TSSOP16 Reel 13” Q1/T1 2500 T =40C to +85C amb *standardmark SMD PCAL6408AHK PCAL6408AHKX XQFN16 Reel 7” Q1/T1 4000 T =40C to +85C amb *standardmark SMD PCAL6408AEX PCAL6408AEXX XFBGA16[1] Reel 7” Q1/T1 5000 T =40C to +85C amb *standardmark SMD PCAL6408AEX1 PCAL6408AEX1Z X2QFN16 Reel 7” Q2/T1 5000 T =40C to +85C amb *standardmark SMD [1] XFBGA16 package is discontinued with lifetime buy November 2016; new designs must use X2QFN16 package. 4. Block diagram PCAL6408A INTERRUPT INT LP FILTER LOGIC ADDR P0 to P7 SCL INPUT I2C-BUS SHIFT I/O FILTER CONTROL REGISTER 8 BITS PORT SDA VDD(I2C-bus) write pulse read pulse VDD(P) POWER-ON I/O control RESET RESET VSS 002aah085 All I/Os are set to inputs at reset. Fig 1. Block diagram (positive logic) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 4 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 5. Pinning information 5.1 Pinning us) b C- DR D(I2 D(P) A terminal 1 D D D D A V V S index area 6 5 4 3 1 1 1 1 RESET 1 12 SCL VDD(I2C-bus) 1 16 VDD(P) ADDR 2 15 SDA P0 2 11 INT PCAL6408ABS RESET 3 14 SCL P1 3 10 P7 P0 4 13 INT PCAL6408APW P2 4 9 P6 P1 5 12 P7 P2 6 11 P6 5 6 7 8 P3 7 10 P5 3 S 4 5 P S P P VSS 8 9 P4 V 002aah087 002aah086 Transparent top view The exposed center pad, if used, must be connected only as a secondary VSS or must be left electrically open. Fig 2. Pin configuration for TSSOP16 Fig 3. Pin configuration for HVQFN16 PCAL6408AHK s) u b C- DR D(I2 D(P) A D D D D terminal 1 A V V S index area 6 5 4 3 1 1 1 1 RESET 1 12 SCL P0 2 11 INT P1 3 10 P7 P2 4 9 P6 5 6 7 8 3 S 4 5 002aah088 P S P P V Transparent top view Fig 4. Pin configuration for XQFN16 PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 5 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander PCAL6408AEX1 ball A1 PCAL6408AEX terminal 1 index area index area 1 2 3 4 1 2 3 4 A A B B C C D D 002aah675 aaa-026716 Transparent top view Transparent top view Fig 5. Pin configuration for Fig 6. Pin configuration for 1.6mm1.6mm XFBGA16 1.6mm1.6mm X2QFN16 EX1 land grid array (cid:20) (cid:21) (cid:22) (cid:23) (cid:36) (cid:53)(cid:40)(cid:54)(cid:40)(cid:55) (cid:57)(cid:39)(cid:39)(cid:11)(cid:44)(cid:21)(cid:38)(cid:16)(cid:69)(cid:88)(cid:86)(cid:12) (cid:57)(cid:39)(cid:39)(cid:11)(cid:51)(cid:12) (cid:54)(cid:38)(cid:47) (cid:37) (cid:51)(cid:19) (cid:36)(cid:39)(cid:39)(cid:53) (cid:54)(cid:39)(cid:36) (cid:44)(cid:49)(cid:55) (cid:38) (cid:51)(cid:21) (cid:51)(cid:20) (cid:51)(cid:26) (cid:51)(cid:25) (cid:39) (cid:51)(cid:22) (cid:57)(cid:54)(cid:54) (cid:51)(cid:23) (cid:51)(cid:24) (cid:19)(cid:19)(cid:21)(cid:68)(cid:68)(cid:75)(cid:25)(cid:26)(cid:25) (cid:55)(cid:85)(cid:68)(cid:81)(cid:86)(cid:83)(cid:68)(cid:85)(cid:72)(cid:81)(cid:87)(cid:3)(cid:87)(cid:82)(cid:83)(cid:3)(cid:89)(cid:76)(cid:72)(cid:90) Fig 7. Ball mapping for 1.6mm 1.6mmXFBGA16/X2QFN16 5.2 Pin description Table 3. Pin descripti on Symbol Pin Description TSSOP16 HVQFN16 XQFN16 XFBGA16, X2QFN16 V 1 15 15 A2 Supply voltage of I2C-bus. Connect directly to the V of DD(I2C-bus) DD the external I2C master. Provides voltage-level translation. ADDR 2 16 16 B2 Address input. Connect directly to V or ground. DD(P) RESET 3 1 1 A1 ActiveLOW reset input. Connect to V through a DD(I2C-bus) pull-up resistor if no active connection is used. P0[1] 4 2 2 B1 PortP input/output 0. P1[1] 5 3 3 C2 PortP input/output 1. P2[1] 6 4 4 C1 PortP input/output 2. P3[1] 7 5 5 D1 PortP input/output 3. V 8 6 6 D2 Ground. SS P4[1] 9 7 7 D3 PortP input/output 4. P5[1] 10 8 8 D4 PortP input/output 5. P6[1] 11 9 9 C4 PortP input/output 6. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 6 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 3. Pin description …continued Symbol Pin Description TSSOP16 HVQFN16 XQFN16 XFBGA16, X2QFN16 P7[1] 12 10 10 C3 PortP input/output 7. INT 13 11 11 B4 Interrupt output. Connect to V through a pull-up DD(I2C-bus) resistor. SCL 14 12 12 A4 Serial clock bus. Connect to V through a pull-up DD(I2C-bus) resistor. SDA 15 13 13 B3 Serial data bus. Connect to V through a pull-up DD(I2C-bus) resistor. V 16 14 14 A3 Supply voltage of PCAL6408A for PortP. DD(P) [1] All I/O are configured as input at power-on. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 7 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 6. Voltage translation Table4 shows how to set up V levels for the necessary voltage translation between the DD I2C-bus and the PCAL6408A. Table 4. Voltage translation V (SDA and SCL of I2C master) V (PortP) DD(I2C-bus) DD(P) 1.8V 1.8V 1.8V 2.5V 1.8V 3.3V 1.8V 5V 2.5V 1.8V 2.5V 2.5V 2.5V 3.3V 2.5V 5V 3.3V 1.8V 3.3V 2.5V 3.3V 3.3V 3.3V 5V 5V 1.8V 5V 2.5V 5V 3.3V 5V 5V 7. Functional description Refer to Figure 1 “Block diagram (positive logic)”. 7.1 Device address The address of the PCAL6408A is shown in Figure8. slave address AD 0 1 0 0 0 0 R/W DR fixed programmable 002aaf539 Fig 8. PCAL6408A address ADDR is the hardware address package pin and is held to either HIGH (logic1) or LOW (logic0) to assign one of the two possible slave addresses. The last bit of the slave address defines the operation (read or write) to be performed. AHIGH (logic1) selects a read operation, while a LOW (logic0) selects a write operation. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 8 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.2 Interface definition Table 5. Interface definition Byte Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C-bus slave address L H L L L L ADDR R/W I/O data bus P7 P6 P5 P4 P3 P2 P1 P0 7.3 Pointer register and command byte Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCAL6408A. 2bits of this data byte state the operation (read or write) and the internal registers (Input, Output, PolarityInversion, or Configuration) that are affected. Bit6 in conjunction with the lower 3bits of the Command byte are used to point to the extended features of the device (AgileI/O). This register is ‘write only’. B7 B6 B5 B4 B3 B2 B1 B0 002aaf540 Fig 9. Pointer register bits Table 6. Command by te Pointer register bits Command byte Register Protocol Power-up default B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 00h Input port read byte xxxxxxxx[1] 0 0 0 0 0 0 0 1 01h Output port read/write byte 11111111 0 0 0 0 0 0 1 0 02h Polarity Inversion read/write byte 00000000 0 0 0 0 0 0 1 1 03h Configuration read/write byte 11111111 0 1 0 0 0 0 0 0 40h Output drive strength 0 read/write byte 11111111 0 1 0 0 0 0 0 1 41h Output drive strength 1 read/write byte 11111111 0 1 0 0 0 0 1 0 42h Input latch read/write byte 00000000 0 1 0 0 0 0 1 1 43h Pull-up/pull-down enable read/write byte 00000000 0 1 0 0 0 1 0 0 44h Pull-up/pull-down selection read/write byte 11111111 0 1 0 0 0 1 0 1 45h Interrupt mask read/write byte 11111111 0 1 0 0 0 1 1 0 46h Interrupt status read byte 00000000 0 1 0 0 1 1 1 1 4Fh Output port configuration read/write byte 00000000 [1] Undefined. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 9 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.4 Register descriptions 7.4.1 Input port register (00h) The Input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port register is read only; writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. An Input port register read operation is performed as described in Section 8.2 “Read commands”. Table 7. Input port register (address 00h) Bit 7 6 5 4 3 2 1 0 Symbol I7 I6 I5 I4 I3 I2 I1 I0 Default X X X X X X X X 7.4.2 Output port register (01h) The Output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from this register reflect the value that was written to this register, not the actual pin value. Table 8. Output port register (address 01h) Bit 7 6 5 4 3 2 1 0 Symbol O7 O6 O5 O4 O3 O2 O1 O0 Default 1 1 1 1 1 1 1 1 7.4.3 Polarity inversion register (02h) The Polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with ‘1’), the corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the corresponding port pin’s original polarity is retained. Table 9. Polarity inversion register (address 02h) Bit 7 6 5 4 3 2 1 0 Symbol N7 N6 N5 N4 N3 N2 N1 N0 Default 0 0 0 0 0 0 0 0 7.4.4 Configuration register (03h) The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Table 10. Configuration register (address 03h) Bit 7 6 5 4 3 2 1 0 Symbol C7 C6 C5 C4 C3 C2 C1 C0 Default 1 1 1 1 1 1 1 1 PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 10 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.4.5 Output drive strength registers (40h, 41h) The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example, Port7 is controlled by register41 CC7 (bits [7:6]), Port 6 is controlled by register41 CC6 (bits [5:4]). The output drive level of the GPIO is programmed 00b=0.25, 01b=0.5, 10b=0.75 or 11b=1 of the drive capability of the I/O. SeeSection 9.2 “Output drive strength control” for more details. Table 11. Current control register (address 40h) Bit 7 6 5 4 3 2 1 0 Symbol CC3 CC2 CC1 CC0 Default 1 1 1 1 1 1 1 1 Table 12. Current control register (address 41h) Bit 7 6 5 4 3 2 1 0 Symbol CC7 CC6 CC5 CC4 Default 1 1 1 1 1 1 1 1 7.4.6 Input latch register (42h) The Input latch register enables and disables the input latch of the I/O pins. These registers are effective only when the pin is configured as an input port. When an input latch register bit is 0, the corresponding input pin state is not latched. A state change in the corresponding input pin generates an interrupt. A read of the input port register clears the interrupt. If the input goes back to its initial logic state before the input port register is read, then the interrupt is cleared. See Figure14. When an input latch register bit is 1, the corresponding input pin state is latched. A change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0). A read of the input port register clears the interrupt. If the input pin returns to its initial logic state before the input port register is read, then the interrupt is not cleared and the corresponding bit of the input port register keeps the logic value that initiated the interrupt. See Figure15. For example, if the P4 input was as logic0 and the input goes to logic1 then back to logic0, the input port register captures this change and an interrupt is generated (if unmasked). When the read is performed on the inputport register, the interrupt is cleared, assuming there were no additional input(s) that have changed, and bit4 of the input port register reads‘1’. The next read of the input port register bit4 should now read ‘0’. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state. A read of the input port register reflects only the change of state of the latched input and also clears the interrupt. The interrupt is not cleared if the input latch register changes from latched to non-latched configuration. If the input pin is changed from latched to non-latched input, a read from the input port register reflects the current port logic level. If the input pin is changed from non-latched to latched input, the read from the input port register reflects the latched logic level. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 11 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 13. Input latch register (address 42h) Bit 7 6 5 4 3 2 1 0 Symbol L7 L6 L5 L4 L3 L2 L1 L0 Default 0 0 0 0 0 0 0 0 7.4.7 Pull-up/pull-down enable register (43h) This register allows the user to enable or disable pull-up/pull-down resistors on the I/O pins. Setting the bit to logic1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the resistors are disconnected when the outputs are configured as open-drain outputs (see Section7.4.11). Use the pull-up/pull-down selection registers to select either a pull-up or pull-down resistor. Table 14. Pull-up/pull-down enable register (address 43h) Bit 7 6 5 4 3 2 1 0 Symbol PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Default 0 0 0 0 0 0 0 0 7.4.8 Pull-up/pull-down selection register (44h) The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to logic1 selects a 100k pull-up resistor for that I/O pin. Setting a bit to logic0 selects a 100k pull-down resistor for that I/O pin. If the pull-up/down feature is disconnected, writing to this register has no effect on I/O pin. Typical value is 100k with minimum of 50k and maximum of 150k. Table 15. Pull-up/pull-down selection register (address 44h) Bit 7 6 5 4 3 2 1 0 Symbol PUD7 PUD6 PUD5 PUD4 PUD3 PUD2 PUD1 PUD0 Default 1 1 1 1 1 1 1 1 7.4.9 Interrupt mask register (45h) Interrupt mask register is set to logic1 upon power-on, disabling interrupts during system start-up. Interrupts may be enabled by setting corresponding mask bits to logic0. If an input changes state and the corresponding bit in the Interrupt mask register is set to 1, the interrupt is masked and the interrupt pin (INT) is not asserted. If the corresponding bit in the Interrupt mask register is set to 0, the interrupt pin is asserted. When an input changes state and the resulting interrupt is masked (interrupt mask bit is1), setting the input mask register bit to 0 causes the interrupt pin to be asserted. Ifthe interrupt mask bit of an input that is currently the source of an interrupt is set to 1, the interrupt pin is de-asserted. Table 16. Interrupt mask register (address 45h) Bit 7 6 5 4 3 2 1 0 Symbol M7 M6 M5 M4 M3 M2 M1 M0 Default 1 1 1 1 1 1 1 1 PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 12 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.4.10 Interrupt status register (46h) This read-only register is used to identify the source of an interrupt. When read, a logic1 indicates that the corresponding input pin was the source of the interrupt. A logic0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit returns logic0. Table 17. Interrupt status register (address 46h) Bit 7 6 5 4 3 2 1 0 Symbol S7 S6 S5 S4 S3 S2 S1 S0 Default 0 0 0 0 0 0 0 0 7.4.11 Output port configuration register (4Fh) The output port configuration register selects port-wise push-pull or open-drain I/O stage. A logic0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure10). A logic1 configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended command sequence is to program this register (4Fh) before the Configuration register (03h) sets the port pins as outputs. Table 18. Output port configuration register (address 4Fh) Bit 7 6 5 4 3 2 1 0 Symbol reserved ODEN Default 0 0 0 0 0 0 0 0 PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 13 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.5 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above V to a maximum of 5.5V. DD If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Outputportregister. In this case, there are low-impedance paths between the I/O pin and either V or V . The external voltage applied to this I/O pin should not exceed the DD(P) SS recommended levels for proper operation. data from output port shift register configuration register data register VDD(P) data from D Q Q1 ESD shift register protection FF write diode configuration CK Q D Q P0 to P7 pulse FF Q2 ESD protection write pulse CK diode output port VSS register D Q input port FF register data read pulse CK VDD(P) INTERRUPT input port MASK to INT register PULL-UP/PULL-DOWN 100 kΩ CONTROL D Q input latch register LATCH data from D Q EN shift register read pulse FF input port write input latch latch pulse CK polarity inversion register data from D Q shift register FF write polarity CK pulse 002aah089 On power-up or reset, all registers return to default values. Fig 10. Simplified schematic of the I/Os (P0 to P7) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 14 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 7.6 Power-on reset When power (from 0V) is applied to V , an internal power-on reset holds the DD(P) PCAL6408A in a reset condition until V has reached V . At that time, the reset DD(P) POR condition is released and the PCAL6408A registers and I2C-bus/SMBus state machine initialize to their default states. After that, V must be lowered to below V and back DD(P) POR up to the operating voltage for a power-reset cycle. See Section 9.3 “Power-on reset requirements”. 7.7 Reset input (RESET) The RESET input can be asserted to initialize the system while keeping the V at its DD(P) operating level. A reset can be accomplished by holding the RESET pin LOW for a minimum of t . The PCAL6408A registers and I2C-bus/SMBus state machine are w(rst) changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O levels at the Pport can be changed externally or through the master. This input requires a pull-up resistor to V if no active connection is used. DD(I2C-bus) 7.8 Interrupt output (INT) An interrupt is generated by any rising or falling edge of the port inputs in the Inputmode. After time t , the signal INT is valid. Resetting the interrupt circuit is achieved when v(INT) data on the port is changed to the original setting or when data is read from the port that generated the interrupt (see Figure14). Resetting occurs in the Readmode at the acknowledge (ACK) or notacknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input port register. The INT output has an open-drain structure and requires a pull-up resistor to V or DD(P) V depending on the application. INT should be connected to the voltage source DD(I2C-bus) of the device that requires the interrupt information. When using the input latch feature, the input pin state is latched. The interrupt is reset only when data is read from the port that generated the interrupt. The reset occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 15 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 8. Bus transactions The PCAL6408A is an I2C-bus slave device. Data is exchanged between the master and PCAL6408A through write and read commands using I2C-bus. The two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Write commands Data is transmitted to the PCAL6408A by sending the device address and setting the Least Significant Bit (LSB) to a logic0 (see Figure8 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. SCL 1 2 3 4 5 6 7 8 9 STOP condition slave address command byte data to port AD SDA S 0 1 0 0 0 0 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P DR START condition R/W acknowledge acknowledge acknowledge from slave from slave from slave write to port tv(Q) data out from port DATA 1 VALID 002aaf825 Fig 11. Write to Output port register SCL 1 2 3 4 5 6 7 8 9 STOP condition slave address command byte data to register AD SDA S 0 1 0 0 0 0 0 A 0 1/0 0 0 0 1/0 1/0 1/0 A DATA 1 A P DR START condition R/W acknowledge acknowledge acknowledge from slave from slave from slave 002aah090 Fig 12. Write to Configuration or Polarity inversion registers PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 16 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 8.2 Read commands To read data from the PCAL6408A, the bus master must first send the PCAL6408A address with the least significant bit set to a logic0 (see Figure8 for device address). The command byte is sent after the address and determines which register is to be accessed. After a restart the device address is sent again, but this time the LSB is set to a logic1. Data from the register defined by the command byte then is sent by the PCAL6408A (see Figure13 and Figure14). Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. slave address command byte SDA S 0 1 0 0 0 0 AD 0 A 0 0 0 0 0 0 1 1/0 A (cont.) DR START condition R/W acknowledge acknowledge from slave from slave slave address data from register data from register (cont.) S 0 1 0 0 0 0 AD 1 A DATA (first byte) A DATA (last byte) NA P DR (repeated) R/W acknowledge no acknowledge STOP START condition acknowledge from master from master condition from slave at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter 002aaf827 Fig 13. Read from register SCL 1 2 3 4 5 6 7 8 9 no acknowledge from master slave address data from port data from port SDA S 0 1 0 0 0 0 AD 1 A DATA 1 A DATA 4 1 P DR START condition R/W acknowledge from slave acknowledge from master STOP read from condition port data into DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 port th(D) tsu(D) INT is cleared by read from port INT STOP not needed to clear INT tv(INT) trst(INT) 002aaf828 Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from Pport (see Figure13). Fig 14. Read Input port register (non-latched) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 17 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander SCL 1 2 3 4 5 6 7 8 9 no acknowledge from master slave address data from port data from port SDA S 0 1 0 0 0 0 AD 1 A DATA 1 A DATA 2 1 P DR START condition R/W acknowledge from slave acknowledge from master STOP read from condition port data into DATA 1 DATA 2 DATA 1 port th(D) tsu(D) INT is cleared by read from port INT STOP not needed to clear INT tv(INT) trst(INT) 002aah091 Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from Pport (see Figure13). Fig 15. Read Input port register (latch enabled) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 18 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 9. Application design-in information VDD(I2C-bus) VDD(P) VDD(I2C-bus) = 1.8 V 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ (× 3) VDD VDD(I2C-bus) VDD(P) ALARM(1) MASTER P0 SUBSYSTEM 1 CONTROLLER (e.g., alarm system) SCL SCL SDA SDA A INT INT RESET RESET P1 enable controlled switch VSS PCAL6408A B P2 P3 ADDR P4 KEYPAD P5 P6 P7 VSS 002aah092 Device address configured as 0100000x for this example. P0 and P2 through P4 are configured as inputs. P1 and P5 through P7 are configured as outputs. (1) Resistors are required for inputs (on Pport) that may float. If a driver to an input will never let the input float, a resistor is not needed. Outputs (in the Pport) do not need pull-up resistors. Fig 16. Typical application 9.1 Minimizing I when I/Os control LEDs DD When the I/Os are used to control LEDs, normally they are connected to V through a DD resistor as shown in Figure16. The LED acts as a diode, so when the LED is off, the I/O V is about 1.2V less than V . The I parameter in Table 23 “Static characteristics” I DD DD shows how I increases as V becomes lower than V . Designs that must minimize DD I DD current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V when the LED is off. DD Figure17 shows a high-value resistor in parallel with the LED. Figure18 shows V less DD than the LED supply voltage by at least 1.2V. Both of these methods maintain the I/O V I at or above V and prevent additional supply current consumption when the LED is off. DD PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 19 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 3.3 V 5 V VDD VDD(P) LED 100 kΩ VDD(P) LED Pn Pn 002aah278 002aah279 Fig 17. High-value resistor in parallel Fig 18. Device supplied by a lower voltage withthe LED 9.2 Output drive strength control The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad. Figure19 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the current control register. When the Current Control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50%. PMOS_EN0 VDD(P) PMOS_EN1 PMOS_EN[3:0] Current Control DECODER register NMOS_EN[3:0] PMOS_EN2 Configuration register PMOS_EN3 P0 to P7 Output port register NMOS_EN3 NMOS_EN2 NMOS_EN1 NMOS_EN0 002aah093 Fig 19. Simplified output stage PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 20 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through V and V package inductance DD SS and creates noise (some radiated, but more critically Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time creates ground and supply noise. The output drive strength control through the Output Drive Strength registers allows the user to mitigate SSN issues without the need of additional external components. 9.3 Power-on reset requirements In the event of a glitch or data corruption, PCAL6408A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is poweredon for the first time in an application. The two types of power-on reset are shown in Figure20 and Figure21. VDD(P) ramp-up ramp-down re-ramp-up td(rst) time (dV/dt)r (dV/dt)f time to re-ramp (dV/dt)r when VDD(P) drops below 0.2 V or to VSS 002aag960 Fig 20. V is lowered below 0.2V or 0V and then ramped up to V DD DD VDD(P) ramp-down ramp-up VI drops below POR levels td(rst) time time to re-ramp (dV/dt)f when VDD(P) drops (dV/dt)r to VPOR(min) − 50 mV 002aag961 Fig 21. V is lowered below the POR threshold, then ramped back up to V DD DD Table19 specifies the performance of the power-on reset feature for PCAL6408A for both types of power-on reset. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 21 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 19. Recommend ed supply sequencing and ramp rates T =25C (unless otherwise noted). Not tested; specified by design. amb Symbol Parameter Condition Min Typ Max Unit (dV/dt) fall rate of change of voltage Figure20 0.1 - 2000 ms f (dV/dt) rise rate of change of voltage Figure20 0.1 - 2000 ms r t reset delay time Figure20; re-ramp time when 1 - - s d(rst) V drops below 0.2V or to V DD(P) SS Figure21; re-ramp time when 1 - - s V drops to V 50mV DD(P) POR(min) V glitch supply voltage difference Figure22 [1] - - 1.0 V DD(gl) t supply voltage glitch pulse width Figure22 [2] - - 10 s w(gl)VDD V power-on reset trip voltage falling V 0.7 - - V POR(trip) DD(P) rising V - - 1.4 V DD(P) [1] Level that VDD(P) can glitch down to with a ramp rate of 0.4s/V, but not cause a functional disruption when tw(gl)VDD<1s. [2] Glitch width that will not cause a functional disruption when VDD(gl)=0.5VDD(P). Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (t ) and glitch height (V ) are dependent on each w(gl)VDD DD(gl) other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure22 and Table19 provide more information on how to measure these specifications. VDD(P) ∆VDD(gl) time tw(gl)VDD 002aag962 Fig 22. Glitch width and glitch height V is critical to the power-on reset. V is the voltage level at which the reset condition POR POR is released and all the registers and the I2C-bus/SMBus state machine are initialized to their default states. The value of V differs based on the V being lowered to or from POR DD 0V. Figure23 and Table19 provide more details on this specification. VDD(P) VPOR (rising VDD(P)) VPOR (falling VDD(P)) time POR time 002aag963 Fig 23. Power-on reset voltage (V ) POR PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 22 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 9.4 Device current consumption with internal pull-up and pull-down resistors The PCAL6408A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. Since these pull-up and pull-down resistors are internal to the device itself, they contribute to the current consumption of the device and must be considered in the overall system design. The pull-up or pull-down function is selected in register 44h, while the resistor is connected by the enable register 43h. The configuration of the resistors is shown in Figure10. If the resistor is configured as a pull-up, that is, connected to V , a current flows from the DD V pin through the resistor to ground when the pin is held LOW. This current appears DD(P) as additional I upsetting any current consumption measurements. DD In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH, current flows from the power supply through the pin to the V pin. While this current is SS not measured as part of I , one must be mindful of the 200mA limiting value through DD V . SS The pull-up and pull-down resistors are simple resistors and the current is linear with voltage. The resistance specification for these devices spans from 50k with a nominal 100k value. Any current flow through these resistors is additive by the number of pins held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure27 for a graph of supply current versus the number of pull-up resistors. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 23 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 10. Limiting values Table 20. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V I2C-bus supply voltage 0.5 +6.5 V DD(I2C-bus) V supply voltage portP 0.5 +6.5 V DD(P) V input voltage [1] 0.5 +6.5 V I V output voltage [1] 0.5 +6.5 V O I input clamping current ADDR, RESET, SCL; V <0V - 20 mA IK I I output clamping current INT; V <0V - 20 mA OK O I input/output clamping current Pport; V <0VorV >V - 20 mA IOK O O DD(P) SDA; V <0VorV >V - 20 mA O O DD(I2C-bus) I LOW-level output current continuous; Pport; V =0V to V - 50 mA OL O DD(P) continuous; SDA, INT; V =0V to V - 25 mA O DD(I2C-bus) I HIGH-level output current continuous; Pport; V =0V to V - 25 mA OH O DD(P) I supply current continuous through V - 200 mA DD SS I supply current port P continuous through V - 160 mA DD(P) DD(P) I I2C-bus supply current continuous through V - 10 mA DD(I2C-bus) DD(I2C-bus) T storage temperature 65 +150 C stg [1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 11. Recommended operating conditions Table 21. Operating co nditions Symbol Parameter Conditions Min Max Unit V I2C-bus supply voltage 1.65 5.5 V DD(I2C-bus) V supply voltage portP 1.65 5.5 V DD(P) V HIGH-level input voltage SCL, SDA, RESET 0.7V 5.5 V IH DD(I2C-bus) ADDR, P7toP0 0.7V 5.5 V DD(P) V LOW-level input voltage SCL, SDA, RESET 0.5 0.3V V IL DD(I2C-bus) ADDR, P7toP0 0.5 0.3V V DD(P) I HIGH-level output current P7toP0 - 10 mA OH I LOW-level output current P7toP0 - 25 mA OL T ambient temperature operating in freeair 40 +85 C amb PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 24 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 12. Thermal characteristics Table 22. Thermal cha racteristics Symbol Parameter Conditions Max Unit Z transient thermal impedance fromjunctionto ambient TSSOP16 package [1] 108 K/W th(j-a) HVQFN16 package [1] 53 K/W XQFN16 package [1] 184 K/W [1] The package thermal impedance is calculated in accordance with JESD51-7. 13. Static characteristics Table 23. Static charac teristics T =40C to +85C; V =1.65V to 5.5V; unless otherwise specified. amb DD(I2C-bus) Symbol Parameter Conditions Min Typ[1] Max Unit V input clamping voltage I =18mA; V =1.65V to 5.5V 1.2 - - V IK I DD(P) V power-on reset voltage V =V or V ; I =0mA; [2] - 1 1.4 V POR I DD(P) SS O V =1.65Vto5.5V DD(P) V HIGH-level output Pport; I =8mA; CCX=11b OH OH voltage[3] V =1.65V 1.2 - - V DD(P) V =2.3V 1.8 - - V DD(P) V =3V 2.6 - - V DD(P) V =4.5V 4.1 - - V DD(P) Pport; I =2.5mA and CCX=00b; OH I =5mA and CCX=01b; OH I =7.5mA and CCX=10b; OH I =10mA and CCX=11b; OH V =1.65V 1.1 - - V DD(P) V =2.3V 1.7 - - V DD(P) V =3V 2.5 - - V DD(P) V =4.5V 4.0 - - V DD(P) V LOW-level Pport; I =8mA; CCX=11b OL OL outputvoltage[3] V =1.65V - - 0.45 V DD(P) V =2.3V - - 0.25 V DD(P) V =3V - - 0.25 V DD(P) V =4.5V - - 0.2 V DD(P) Pport; I =2.5mA and CCX=00b; OL I =5mA and CCX=01b; OL I =7.5mA and CCX=10b; OL I =10mA and CCX=11b; OL V =1.65V - - 0.5 V DD(P) V =2.3V - - 0.3 V DD(P) V =3V - - 0.25 V DD(P) V =4.5V - - 0.2 V DD(P) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 25 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 23. Static characteristics …continued T =40C to +85C; V =1.65V to 5.5V; unless otherwise specified. amb DD(I2C-bus) Symbol Parameter Conditions Min Typ[1] Max Unit I LOW-level output current V =0.4V; V =1.65V to 5.5V [4] OL OL DD(P) SDA 3 - - mA INT 3 15[5] - mA I input current V =1.65V to 5.5V I DD(P) SCL, SDA, RESET; V =V or V - - 1 A I DD(I2C-bus) SS ADDR; V =V or V - - 1 A I DD(P) SS I HIGH-level input current Pport; V =V ; V =1.65V to 5.5V - - 1 A IH I DD(P) DD(P) I LOW-level input current Pport; V =V ; V =1.65V to 5.5V - - 1 A IL I SS DD(P) I supply current I +I ; Operating mode; DD DD(I2C-bus) DD(P) SDA, Pport, ADDR, RESET; V onSDA and RESET=V or V ; I DD(I2C-bus) SS V onPport and ADDR=V or V ; I DD(P) SS I =0mA;I/O=inputs; f =400kHz O SCL V =3.6V to 5.5V - 10 25 A DD(P) V =2.3V to 3.6V - 6.5 15 A DD(P) V =1.65V to 2.3V - 4 9 A DD(P) I +I ; Standby mode; DD(I2C-bus) DD(P) SCL, SDA, Pport, ADDR, RESET; V on SCL, SDA and RESET=V or V ; I DD(I2C-bus) SS V on Pport and ADDR=V ; I DD(P) I =0mA;I/O=inputs; f =0kHz O SCL V =3.6V to 5.5V - 1.5 7 A DD(P) V =2.3V to 3.6V - 1 3.2 A DD(P) V =1.65V to 2.3V - 0.5 1.7 A DD(P) Active mode; I +I ; DD(I2C-bus) DD(P) Pport, ADDR, RESET; V on RESET=V ; I DD(I2C-bus) V on Pport and ADDR=V ; I DD(P) I =0mA;I/O=inputs; O f =400kHz, continuous register read SCL V =3.6V to 5.5V - 60 125 A DD(P) V =2.3V to 3.6V - 40 75 A DD(P) V =1.65V to 2.3V - 20 45 A DD(P) with pull-ups enabled; I +I ; Pport, ADDR, RESET; DD(I2C-bus) DD(P) V on SCL, SDA and RESET=V or V ; I DD(I2C-bus) SS V on Pport=V ; I SS V on ADDR=V or V ; I DD(I2C-bus) SS I =0mA;I/O=inputs with pull-up enabled; O f =0kHz SCL V =1.65V to 5.5V - 0.55 0.75 mA DD(P) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 26 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 23. Static characteristics …continued T =40C to +85C; V =1.65V to 5.5V; unless otherwise specified. amb DD(I2C-bus) Symbol Parameter Conditions Min Typ[1] Max Unit I additional quiescent SCL, SDA, RESET; - - 25 A DD supply current[6] one input at V 0.6V, DD(I2C-bus) other inputs at V or V ; DD(I2C-bus) SS V =1.65Vto5.5V DD(P) Pport, ADDR; - - 80 A one input at V 0.6V, DD(P) otherinputs at V or V ; DD(P) SS V =1.65Vto5.5V DD(P) C input capacitance SCL; V =V or V ; - 6 7 pF i I DD(I2C-bus) SS V =1.65Vto5.5V DD(P) C input/output capacitance SDA; V =V or V ; - 7 8 pF io I/O DD(I2C-bus) SS V =1.65Vto5.5V DD(P) Pport; V =V or V ; - 7.5 8.5 pF I/O DD(P) SS V =1.65Vto5.5V DD(P) R internal pull-up resistance input/output 50 100 150 k pu(int) R internal pull-down input/output 50 100 150 k pd(int) resistance [1] All typical values are at nominal supply voltage (1.8V, 2.5V, 3.3V or 5V VDD) and Tamb=25C. [2] When power (from 0V) is applied to V , an internal power-on reset holds the PCAL6408A in a reset condition until V has DD(P) DD(P) reached VPOR. At that time, the reset condition is released, and the PCAL6408A registers and I2C-bus/SMBus state machine initialize to their default states. After that, V must be lowered to below 0.2V and back up to the operating voltage for a power-reset cycle. DD(P) [3] The total current sourced by all I/Os must be limited to 80mA. [4] Each I/O must be externally limited to a maximum of 25mA, for a device total of 200mA. [5] Typical value for Tamb=25C. VOL=0.4V and VDD=3.3V. Typical value for VDD<2.5V, VOL=0.6V. [6] Internal pull-up/pull-down resistor disabled. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 27 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 13.1 Typical characteristics 002aag973 002aag974 20 1400 (IμDAD) IDD(stb) (nA) 16 VDD(P) = 5.5 V VDD(P) = 55..50 VV 1000 53..06 VV 12 33..63 VV 800 3.3 V 2.5 V 2.3 V 600 8 400 2.5 V 4 2.3 V VDD(P) =1 .16.58 VV 200 11..86 5V V 0 0 −40 −15 10 35 60 85 −40 −15 10 35 60 85 Tamb (°C) Tamb (°C) Fig 24. Supply current versus ambient temperature Fig 25. Standby supply current versus ambienttemperature 002aag975 002aah245 20 600 (IμDAD) IDD(P) Tamb = −4205 °°CC 16 (μA) 85 °C 400 12 8 200 4 0 0 1.5 2.5 3.5 4.5 5.5 0 2 4 6 8 VDD(P) (V) number of I/O held LOW Tamb=25C VDD(P)=5V Fig 26. Supply current versus supply voltage Fig 27. Supply current versus number of I/O held LOW PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 28 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 002aaf578 002aaf579 35 35 Isink Isink (mA) (mA) 30 30 Tamb = −40 °C Tamb = −40 °C 25 25 °C 25 25 °C 85 °C 85 °C 20 20 15 15 10 10 5 5 0 0 0 0.1 0.2 0.3 0 0.1 0.2 0.3 VOL (V) VOL (V) a. V =1.65V b. V =1.8V DD(P) DD(P) 002aaf580 002aaf581 50 60 Isink (mA) Isink Tamb = −40 °C 40 (mA) 25 °C Tamb = −40 °C 85 °C 25 °C 40 30 85 °C 20 20 10 0 0 0 0.1 0.2 0.3 0 0.1 0.2 0.3 VOL (V) VOL (V) c. V =2.5V d. V =3.3V DD(P) DD(P) 002aaf582 002aaf583 70 70 Isink Isink (mA) (mA) 60 Tamb = −40 °C 60 Tamb = −40 °C 25 °C 25 °C 50 85 °C 50 85 °C 40 40 30 30 20 20 10 10 0 0 0 0.1 0.2 0.3 0 0.1 0.2 0.3 VOL (V) VOL (V) e. V =5.0V f. V =5.5V DD(P) DD(P) Fig 28. I/O sink current versus LOW-level output voltage with CCX.X = 11b PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 29 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 002aaf561 002aaf562 30 35 Isource Isource (mA) 30 Tamb = −40 °C (mA) Tamb = −40 °C 25 °C 25 °C 25 85 °C 20 85 °C 20 15 10 10 5 0 0 0 0.2 0.4 0.6 0 0.2 0.4 0.6 VDD(P) − VOH (V) VDD(P) − VOH (V) a. V =1.65V b. V =1.8V DD(P) DD(P) 002aaf563 002aaf564 60 70 Isource Isource (mA) 60 Tamb = −40 °C (mA) 25 °C Tamb = −4205 °°CC 50 85 °C 40 85 °C 40 30 20 20 10 0 0 0 0.2 0.4 0.6 0 0.2 0.4 0.6 VDD(P) − VOH (V) VDD(P) − VOH (V) c. V =2.5V d. V =3.3V DD(P) DD(P) 002aaf565 002aaf566 90 90 Is(mouArc)e Tamb = −40 °C Is(mouArc)e Tamb = −40 °C 25 °C 25 °C 85 °C 85 °C 60 60 30 30 0 0 0 0.2 0.4 0.6 0 0.2 0.4 0.6 VDD(P) − VOH (V) VDD(P) − VOH (V) e. V =5.0V f. V =5.5V DD(P) DD(P) Fig 29. I/O source current versus HIGH-level output voltage with CCX.X = 11b PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 30 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 002aah056 002aah057 120 200 (VmOVL) VDD(P) − VOH (mV) 100 160 (1) 80 120 VDD(P) = 1.8 V 5 V 60 (2) 80 40 (4) 40 20 (3) 0 0 −40 −15 10 35 60 85 −40 −15 10 35 60 85 Tamb (°C) Tamb (°C) (1) VDD(P) = 1.8V; Isink=10mA Isource=10mA (2) VDD(P) = 5V; Isink=10mA (3) V = 1.8V; I =1mA DD(P) sink (4) VDD(P) = 5V; Isink=1mA Fig 30. LOW-level output voltage versus temperature Fig 31. I/O high voltage versus temperature PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 31 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 14. Dynamic characteristics Table 24. I2C-bus inter face timing requirements Over recommended operating freeair temperature range, unless otherwise specified. See Figure32. Symbol Parameter Conditions Standard-mode Fast-mode I2C-bus Unit I2C-bus Min Max Min Max f SCL clock frequency 0 100 0 400 kHz SCL t HIGH period of the SCL clock 4 - 0.6 - s HIGH t LOW period of the SCL clock 4.7 - 1.3 - s LOW t pulse width of spikes that must 0 50 0 50 ns SP besuppressed by the input filter t data set-up time 250 - 100 - ns SU;DAT t data hold time 0 - 0 - ns HD;DAT t rise time of both SDA and SCL signals - 1000 20 300 ns r t fall time of both SDA and SCL signals - 300 20 300 ns f (V /5.5V) DD t bus free time between a STOP and 4.7 - 1.3 - s BUF START condition t set-up time for a repeated START 4.7 - 0.6 - s SU;STA condition t hold time (repeated) START condition 4 - 0.6 - s HD;STA t set-up time for STOP condition 4 - 0.6 - s SU;STO t data valid time SCL LOW to - 3.45 - 0.9 s VD;DAT SDA output valid t data valid acknowledge time ACK signal from - 3.45 - 0.9 s VD;ACK SCL LOW to SDA (out) LOW Table 25. Reset timing requirements Over recommended operating freeair temperature range, unless otherwise specified. See Figure35. Symbol Parameter Conditions Standard-mode Fast-mode Unit I2C-bus I2C-bus Min Max Min Max t reset pulse width 30 - 30 - ns w(rst) t reset recovery time 200 - 200 - ns rec(rst) t reset time 600 - 600 - ns rst PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 32 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 26. Switching ch aracteristics Over recommended operating freeair temperature range; C 100pF; unless otherwise specified. See Figure34. L Symbol Parameter Conditions Standard-mode Fast-mode Unit I2C-bus I2C-bus Min Max Min Max t valid time on pin INT from Pport to INT - 1 - 1 s v(INT) t reset time on pin INT from SCL to INT - 1 - 1 s rst(INT) t data output valid time from SCL to Pport - 400 - 400 ns v(Q) t data input set-up time from Pport to SCL 0 - 0 - ns su(D) t data input hold time from Pport to SCL 300 - 300 - ns h(D) 15. Parameter measurement information VDD(I2C-bus) RL = 1 kΩ SDA DUT CL = 50 pF 002aag977 a. SDA load configuration two bytes for read Input port register(1) STOP START Address Address R/W ACK Data Data STOP condition condition Bit 7 Bit 1 Bit 0 (A) Bit 7 Bit 0 condition (P) (S) (MSB) (LSB) (MSB) (LSB) (P) 002aag952 b. Transaction format tLOW tHIGH tSP 0.7 × VDD(I2C-bus) SCL 0.3 × VDD(I2C-bus) tBUF tr tf tVD;DAtTf(o) tVD;ACK tSU;STA tSU;STO 0.7 × VDD(I2C-bus) SDA 0.3 × VDD(I2C-bus) tf tr tVD;ACK tHD;STA tSU;DAT tHD;DAT repeat START condition STOP condition 002aag978 c. Voltage waveforms C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR10MHz; Zo=50; tr/tf30ns. All parameters and waveforms are not applicable to all devices. Byte 1 = I2C-bus address; Byte 2, byte3 = Pport data. (1) See Figure14. Fig 32. I2C-bus interface load circuit and voltage waveforms PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 33 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander VDD(I2C-bus) RL = 4.7 kΩ INT DUT CL = 100 pF 002aag979 a. Interrupt load configuration acknowledge acknowledge no acknowledge from slave from slave from master START condition R/W STOP 8 bits (one data byte) condition slave address from port data from port AD SDA S 0 1 0 0 0 0 1 A DATA 1 A DATA 2 1 P DR SCL 1 2 3 4 5 6 7 8 9 B trst(INT) trst(INT) B INT A tv(INT) A tsu(D) data into ADDRESS DATA 1 DATA 2 port 0.7 × VDD(I2C-bus) INT 0.5 × VDD(I2C-bus) SCL R/W A 0.3 × VDD(I2C-bus) tv(INT) trst(INT) Pn 0.5 × VDD(P) INT 0.5 × VDD(I2C-bus) View A - A View B - B 002aag980 b. Voltage waveforms C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR10MHz; Zo=50; tr/tf30ns. All parameters and waveforms are not applicable to all devices. Fig 33. Interrupt load circuit and voltage waveforms PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 34 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Pn 500 Ω DUT 2 × VDD(P) CL = 50 pF 500 Ω 002aag981 a. Pport load configuration 0.7 × VDD(I2C-bus) SCL P0 A P7 0.3 × VDD(I2C-bus) SDA tv(Q) Pn unstable last stable bit data 002aag982 b. Write mode (R/W=0) 0.7 × VDD(I2C-bus) SCL P0 A P7 0.3 × VDD(I2C-bus) tsu(D) th(D) Pn 0.5 × VDD(P) 002aag983 c. Read mode (R/W=1) C includes probe and jig capacitance. L tv(Q) is measured from 0.7VDD(I2C-bus) on SCL to 50% I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR10MHz; Zo=50; tr/tf30ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. Fig 34. Pport load circuit and voltage waveforms PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 35 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander VDD(I2C-bus) RL = 1 kΩ SDA Pn 500 Ω DUT DUT 2 × VDD(P) CL = 50 pF CL = 50 pF 500 Ω 002aag977 002aag981 a. SDA load configuration b. Pport load configuration START SCL ACK or read cycle SDA 0.3 × VDD(I2C-bus) trst RESET 0.5 × VDD(I2C-bus) trec(rst) tw(rst) trec(rst) trst Pn 0.5 × VDD(P) 002aag984 c. RESET timing C includes probe and jig capacitance. L All inputs are supplied by generators having the following characteristics: PRR10MHz; Zo=50; tr/tf30ns. The outputs are measured one at a time, with one transition per measurement. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices. Fig 35. Reset load circuits and voltage waveforms PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 36 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 16. Package outline (cid:55)(cid:54)(cid:54)(cid:50)(cid:51)(cid:20)(cid:25)(cid:29)(cid:3)(cid:83)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:3)(cid:87)(cid:75)(cid:76)(cid:81)(cid:3)(cid:86)(cid:75)(cid:85)(cid:76)(cid:81)(cid:78)(cid:3)(cid:86)(cid:80)(cid:68)(cid:79)(cid:79)(cid:3)(cid:82)(cid:88)(cid:87)(cid:79)(cid:76)(cid:81)(cid:72)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:30)(cid:3)(cid:20)(cid:25)(cid:3)(cid:79)(cid:72)(cid:68)(cid:71)(cid:86)(cid:30)(cid:3)(cid:69)(cid:82)(cid:71)(cid:92)(cid:3)(cid:90)(cid:76)(cid:71)(cid:87)(cid:75)(cid:3)(cid:23)(cid:17)(cid:23)(cid:3)(cid:80)(cid:80)(cid:3) (cid:54)(cid:50)(cid:55)(cid:23)(cid:19)(cid:22)(cid:16)(cid:20)(cid:3) (cid:39)(cid:3) (cid:40)(cid:3) (cid:36)(cid:3) (cid:59)(cid:3) (cid:70)(cid:3) (cid:92)(cid:3) (cid:43)(cid:3)(cid:40)(cid:3) (cid:89)(cid:3)(cid:48)(cid:3) (cid:36)(cid:3) (cid:61)(cid:3) (cid:20)(cid:25)(cid:3) (cid:28)(cid:3) (cid:52)(cid:3) (cid:36)(cid:3)(cid:21)(cid:3) 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(cid:21)(cid:17)(cid:3)(cid:51)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:3)(cid:76)(cid:81)(cid:87)(cid:72)(cid:85)(cid:79)(cid:72)(cid:68)(cid:71)(cid:3)(cid:83)(cid:85)(cid:82)(cid:87)(cid:85)(cid:88)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:82)(cid:73)(cid:3)(cid:19)(cid:17)(cid:21)(cid:24)(cid:3)(cid:80)(cid:80)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:83)(cid:72)(cid:85)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72)(cid:3)(cid:68)(cid:85)(cid:72)(cid:3)(cid:81)(cid:82)(cid:87)(cid:3)(cid:76)(cid:81)(cid:70)(cid:79)(cid:88)(cid:71)(cid:72)(cid:71)(cid:17)(cid:3) (cid:50)(cid:56)(cid:55)(cid:47)(cid:44)(cid:49)(cid:40)(cid:3) (cid:3)(cid:53)(cid:40)(cid:41)(cid:40)(cid:53)(cid:40)(cid:49)(cid:38)(cid:40)(cid:54)(cid:3) (cid:40)(cid:56)(cid:53)(cid:50)(cid:51)(cid:40)(cid:36)(cid:49)(cid:3) (cid:44)(cid:54)(cid:54)(cid:56)(cid:40)(cid:3)(cid:39)(cid:36)(cid:55)(cid:40)(cid:3) (cid:57)(cid:40)(cid:53)(cid:54)(cid:44)(cid:50)(cid:49)(cid:3) (cid:3)(cid:44)(cid:40)(cid:38)(cid:3) (cid:3)(cid:45)(cid:40)(cid:39)(cid:40)(cid:38)(cid:3) (cid:3)(cid:45)(cid:40)(cid:44)(cid:55)(cid:36)(cid:3) (cid:51)(cid:53)(cid:50)(cid:45)(cid:40)(cid:38)(cid:55)(cid:44)(cid:50)(cid:49)(cid:3) (cid:28)(cid:28)(cid:16)(cid:20)(cid:21)(cid:16)(cid:21)(cid:26)(cid:3) (cid:3)(cid:54)(cid:50)(cid:55)(cid:23)(cid:19)(cid:22)(cid:16)(cid:20)(cid:3) (cid:3)(cid:48)(cid:50)(cid:16)(cid:20)(cid:24)(cid:22)(cid:3) (cid:19)(cid:22)(cid:16)(cid:19)(cid:21)(cid:16)(cid:20)(cid:27)(cid:3) Fig 36. Package outline SOT403-1 (TSSOP16) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 37 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander (cid:43)(cid:57)(cid:52)(cid:41)(cid:49)(cid:20)(cid:25)(cid:29)(cid:3)(cid:83)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:3)(cid:87)(cid:75)(cid:72)(cid:85)(cid:80)(cid:68)(cid:79)(cid:3)(cid:72)(cid:81)(cid:75)(cid:68)(cid:81)(cid:70)(cid:72)(cid:71)(cid:3)(cid:89)(cid:72)(cid:85)(cid:92)(cid:3)(cid:87)(cid:75)(cid:76)(cid:81)(cid:3)(cid:84)(cid:88)(cid:68)(cid:71)(cid:3)(cid:73)(cid:79)(cid:68)(cid:87)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:30)(cid:3)(cid:81)(cid:82)(cid:3)(cid:79)(cid:72)(cid:68)(cid:71)(cid:86)(cid:30)(cid:3) (cid:20)(cid:25)(cid:3)(cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:86)(cid:30)(cid:3)(cid:69)(cid:82)(cid:71)(cid:92)(cid:3)(cid:22)(cid:3)(cid:91)(cid:3)(cid:22)(cid:3)(cid:91)(cid:3)(cid:19)(cid:17)(cid:27)(cid:24)(cid:3)(cid:80)(cid:80)(cid:3) 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(cid:40)(cid:3)(cid:11)(cid:20)(cid:12)(cid:3) (cid:40)(cid:75)(cid:3) (cid:72)(cid:3) (cid:72)(cid:20)(cid:3) (cid:72)(cid:21)(cid:3) (cid:47)(cid:3) (cid:89)(cid:3) (cid:90)(cid:3) (cid:92)(cid:3) (cid:92)(cid:20)(cid:3) (cid:19)(cid:17)(cid:19)(cid:24)(cid:3) (cid:19)(cid:17)(cid:22)(cid:19)(cid:3) (cid:22)(cid:17)(cid:20)(cid:3) (cid:20)(cid:17)(cid:26)(cid:24)(cid:3) (cid:22)(cid:17)(cid:20)(cid:3) (cid:20)(cid:17)(cid:26)(cid:24)(cid:3) (cid:19)(cid:17)(cid:24)(cid:3) (cid:80)(cid:80)(cid:3) (cid:20)(cid:3) (cid:19)(cid:17)(cid:21)(cid:3) (cid:19)(cid:17)(cid:24)(cid:3) (cid:20)(cid:17)(cid:24)(cid:3) (cid:20)(cid:17)(cid:24)(cid:3) (cid:19)(cid:17)(cid:20)(cid:3) (cid:19)(cid:17)(cid:19)(cid:24)(cid:3) (cid:19)(cid:17)(cid:19)(cid:24)(cid:3) (cid:19)(cid:17)(cid:20)(cid:3) (cid:19)(cid:17)(cid:19)(cid:19)(cid:3) (cid:19)(cid:17)(cid:20)(cid:27)(cid:3) (cid:21)(cid:17)(cid:28)(cid:3) (cid:20)(cid:17)(cid:23)(cid:24)(cid:3) (cid:21)(cid:17)(cid:28)(cid:3) (cid:20)(cid:17)(cid:23)(cid:24)(cid:3) (cid:19)(cid:17)(cid:22)(cid:3) (cid:49)(cid:82)(cid:87)(cid:72)(cid:3) (cid:20)(cid:17)(cid:3)(cid:51)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:3)(cid:82)(cid:85)(cid:3)(cid:80)(cid:72)(cid:87)(cid:68)(cid:79)(cid:3)(cid:83)(cid:85)(cid:82)(cid:87)(cid:85)(cid:88)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:82)(cid:73)(cid:3)(cid:19)(cid:17)(cid:19)(cid:26)(cid:24)(cid:3)(cid:80)(cid:80)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:83)(cid:72)(cid:85)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72)(cid:3)(cid:68)(cid:85)(cid:72)(cid:3)(cid:81)(cid:82)(cid:87)(cid:3)(cid:76)(cid:81)(cid:70)(cid:79)(cid:88)(cid:71)(cid:72)(cid:71)(cid:17)(cid:3)(cid:3) (cid:50)(cid:56)(cid:55)(cid:47)(cid:44)(cid:49)(cid:40)(cid:3) (cid:3)(cid:53)(cid:40)(cid:41)(cid:40)(cid:53)(cid:40)(cid:49)(cid:38)(cid:40)(cid:54)(cid:3) (cid:40)(cid:56)(cid:53)(cid:50)(cid:51)(cid:40)(cid:36)(cid:49)(cid:3) (cid:44)(cid:54)(cid:54)(cid:56)(cid:40)(cid:3)(cid:39)(cid:36)(cid:55)(cid:40)(cid:3) (cid:57)(cid:40)(cid:53)(cid:54)(cid:44)(cid:50)(cid:49)(cid:3) (cid:3)(cid:44)(cid:40)(cid:38)(cid:3) (cid:3)(cid:45)(cid:40)(cid:39)(cid:40)(cid:38)(cid:3) (cid:3)(cid:45)(cid:40)(cid:44)(cid:55)(cid:36)(cid:3) (cid:51)(cid:53)(cid:50)(cid:45)(cid:40)(cid:38)(cid:55)(cid:44)(cid:50)(cid:49)(cid:3) (cid:19)(cid:21)(cid:16)(cid:19)(cid:22)(cid:16)(cid:21)(cid:24)(cid:3) (cid:3)(cid:54)(cid:50)(cid:55)(cid:26)(cid:24)(cid:27)(cid:16)(cid:20)(cid:3) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16)(cid:3) (cid:48)(cid:50)(cid:16)(cid:21)(cid:21)(cid:19)(cid:3) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16)(cid:3) (cid:19)(cid:21)(cid:16)(cid:20)(cid:19)(cid:16)(cid:21)(cid:20)(cid:3) Fig 37. Package outline SOT758-1 (HVQFN16) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 38 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander (cid:59)(cid:52)(cid:41)(cid:49)(cid:20)(cid:25)(cid:29)(cid:3)(cid:83)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:15)(cid:3)(cid:72)(cid:91)(cid:87)(cid:85)(cid:72)(cid:80)(cid:72)(cid:79)(cid:92)(cid:3)(cid:87)(cid:75)(cid:76)(cid:81)(cid:3)(cid:84)(cid:88)(cid:68)(cid:71)(cid:3)(cid:73)(cid:79)(cid:68)(cid:87)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:30)(cid:3)(cid:81)(cid:82)(cid:3)(cid:79)(cid:72)(cid:68)(cid:71)(cid:86)(cid:30)(cid:3) (cid:20)(cid:25)(cid:3)(cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:86)(cid:30)(cid:3)(cid:69)(cid:82)(cid:71)(cid:92)(cid:3)(cid:20)(cid:17)(cid:27)(cid:19)(cid:3)(cid:91)(cid:3)(cid:21)(cid:17)(cid:25)(cid:19)(cid:3)(cid:91)(cid:3)(cid:19)(cid:17)(cid:24)(cid:19)(cid:3)(cid:80)(cid:80) (cid:54)(cid:50)(cid:55)(cid:20)(cid:20)(cid:25)(cid:20)(cid:16)(cid:20) (cid:59) (cid:39) (cid:37) (cid:36) (cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:20)(cid:3) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:40) (cid:36) (cid:36)(cid:20) (cid:36)(cid:22) (cid:71)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:59) (cid:72)(cid:20) (cid:38) (cid:89) (cid:38) (cid:36) (cid:37) (cid:72) (cid:69) (cid:90) (cid:38) (cid:92)(cid:20)(cid:38) (cid:92) (cid:24) (cid:27) (cid:47) (cid:23) (cid:28) (cid:72) (cid:72)(cid:21) (cid:20) (cid:20)(cid:21) (cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:20)(cid:3) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:20)(cid:25) (cid:20)(cid:22) (cid:47)(cid:20) (cid:19) (cid:20) (cid:21)(cid:3)(cid:80)(cid:80) (cid:86)(cid:70)(cid:68)(cid:79)(cid:72) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86) (cid:56)(cid:81)(cid:76)(cid:87)(cid:11)(cid:20)(cid:12) (cid:36) (cid:36)(cid:20) (cid:36)(cid:22) (cid:69) (cid:39) (cid:40) (cid:72) (cid:72)(cid:20) (cid:72)(cid:21) (cid:47) (cid:47)(cid:20) (cid:89) (cid:90) (cid:92) (cid:92)(cid:20) (cid:80)(cid:68)(cid:91)(cid:3) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:19)(cid:24)(cid:3) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3) (cid:20)(cid:17)(cid:28)(cid:3) (cid:21)(cid:17)(cid:26)(cid:3) (cid:19)(cid:17)(cid:23)(cid:24)(cid:3) (cid:19)(cid:17)(cid:24)(cid:24)(cid:3) (cid:80)(cid:80) (cid:81)(cid:82)(cid:80)(cid:3) (cid:3) (cid:19)(cid:17)(cid:20)(cid:21)(cid:26) (cid:19)(cid:17)(cid:21)(cid:19)(cid:3) (cid:20)(cid:17)(cid:27)(cid:3) (cid:21)(cid:17)(cid:25)(cid:3) (cid:19)(cid:17)(cid:23) (cid:20)(cid:17)(cid:21) (cid:20)(cid:17)(cid:21) (cid:19)(cid:17)(cid:23)(cid:19)(cid:3) (cid:19)(cid:17)(cid:24)(cid:19)(cid:3) (cid:19)(cid:17)(cid:20) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:19)(cid:24) (cid:80)(cid:76)(cid:81) (cid:19)(cid:17)(cid:19)(cid:19) (cid:19)(cid:17)(cid:20)(cid:24) (cid:20)(cid:17)(cid:26) (cid:21)(cid:17)(cid:24) (cid:19)(cid:17)(cid:22)(cid:24) (cid:19)(cid:17)(cid:23)(cid:24) (cid:49)(cid:82)(cid:87)(cid:72)(cid:3) (cid:20)(cid:17)(cid:3)(cid:51)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:3)(cid:82)(cid:85)(cid:3)(cid:80)(cid:72)(cid:87)(cid:68)(cid:79)(cid:3)(cid:83)(cid:85)(cid:82)(cid:87)(cid:85)(cid:88)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:82)(cid:73)(cid:3)(cid:19)(cid:17)(cid:19)(cid:26)(cid:24)(cid:3)(cid:80)(cid:80)(cid:3)(cid:80)(cid:68)(cid:91)(cid:76)(cid:80)(cid:88)(cid:80)(cid:3)(cid:83)(cid:72)(cid:85)(cid:3)(cid:86)(cid:76)(cid:71)(cid:72)(cid:3)(cid:68)(cid:85)(cid:72)(cid:3)(cid:81)(cid:82)(cid:87)(cid:3)(cid:76)(cid:81)(cid:70)(cid:79)(cid:88)(cid:71)(cid:72)(cid:71)(cid:17) (cid:86)(cid:82)(cid:87)(cid:20)(cid:20)(cid:25)(cid:20)(cid:16)(cid:20)(cid:66)(cid:83)(cid:82) (cid:50)(cid:88)(cid:87)(cid:79)(cid:76)(cid:81)(cid:72)(cid:3) (cid:53)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72)(cid:86) (cid:40)(cid:88)(cid:85)(cid:82)(cid:83)(cid:72)(cid:68)(cid:81)(cid:3) (cid:44)(cid:86)(cid:86)(cid:88)(cid:72)(cid:3)(cid:71)(cid:68)(cid:87)(cid:72) (cid:89)(cid:72)(cid:85)(cid:86)(cid:76)(cid:82)(cid:81) (cid:44)(cid:40)(cid:38) (cid:45)(cid:40)(cid:39)(cid:40)(cid:38) (cid:45)(cid:40)(cid:44)(cid:55)(cid:36) (cid:83)(cid:85)(cid:82)(cid:77)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81) (cid:19)(cid:28)(cid:16)(cid:20)(cid:21)(cid:16)(cid:21)(cid:27)(cid:3) (cid:54)(cid:50)(cid:55)(cid:20)(cid:20)(cid:25)(cid:20)(cid:16)(cid:20) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:19)(cid:28)(cid:16)(cid:20)(cid:21)(cid:16)(cid:21)(cid:28) Fig 38. Package outline SOT1161-1 (XQFN16) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 39 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander (cid:59)(cid:41)(cid:37)(cid:42)(cid:36)(cid:20)(cid:25)(cid:29)(cid:3)(cid:83)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:15)(cid:3)(cid:72)(cid:91)(cid:87)(cid:85)(cid:72)(cid:80)(cid:72)(cid:79)(cid:92)(cid:3)(cid:87)(cid:75)(cid:76)(cid:81)(cid:3)(cid:73)(cid:76)(cid:81)(cid:72)(cid:16)(cid:83)(cid:76)(cid:87)(cid:70)(cid:75)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:3)(cid:74)(cid:85)(cid:76)(cid:71)(cid:3)(cid:68)(cid:85)(cid:85)(cid:68)(cid:92)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:30)(cid:3)(cid:20)(cid:25)(cid:3)(cid:69)(cid:68)(cid:79)(cid:79)(cid:86)(cid:3) (cid:54)(cid:50)(cid:55)(cid:20)(cid:22)(cid:24)(cid:23)(cid:16)(cid:20) (cid:39) (cid:37) (cid:36) (cid:69)(cid:68)(cid:79)(cid:79)(cid:3)(cid:36)(cid:20) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:36)(cid:21) (cid:36) (cid:40) (cid:36)(cid:20) (cid:71)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:59) (cid:72)(cid:20) (cid:38) (cid:145)(cid:3)(cid:89) (cid:38) (cid:36) (cid:37) (cid:72) (cid:69) (cid:92)(cid:20)(cid:38) (cid:92) (cid:145)(cid:3)(cid:90) (cid:38) (cid:39) (cid:72) (cid:38) (cid:72)(cid:21) (cid:37) (cid:36) (cid:69)(cid:68)(cid:79)(cid:79)(cid:3)(cid:36)(cid:20) (cid:20) (cid:21) (cid:22) (cid:23) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:59) (cid:19) (cid:21)(cid:3)(cid:80)(cid:80) (cid:86)(cid:70)(cid:68)(cid:79)(cid:72) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:11)(cid:80)(cid:80)(cid:3)(cid:68)(cid:85)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:82)(cid:85)(cid:76)(cid:74)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:71)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:12) (cid:56)(cid:81)(cid:76)(cid:87) (cid:36) (cid:36)(cid:20) (cid:36)(cid:21) (cid:69) (cid:39) (cid:40) (cid:72) (cid:72)(cid:20) (cid:72)(cid:21) (cid:89) (cid:90) (cid:92) (cid:92)(cid:20) (cid:80)(cid:68)(cid:91) (cid:19)(cid:17)(cid:24) (cid:19)(cid:17)(cid:20)(cid:24) (cid:19)(cid:17)(cid:22)(cid:24) (cid:19)(cid:17)(cid:21)(cid:19)(cid:24) (cid:20)(cid:17)(cid:26) (cid:20)(cid:17)(cid:26) (cid:80)(cid:80) (cid:81)(cid:82)(cid:80) (cid:19)(cid:17)(cid:20)(cid:19) (cid:19)(cid:17)(cid:22)(cid:23) (cid:19)(cid:17)(cid:20)(cid:26)(cid:24) (cid:20)(cid:17)(cid:25) (cid:20)(cid:17)(cid:25) (cid:19)(cid:17)(cid:23) (cid:20)(cid:17)(cid:21) (cid:20)(cid:17)(cid:21) (cid:19)(cid:17)(cid:20)(cid:24) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:19)(cid:27) (cid:19)(cid:17)(cid:20) (cid:80)(cid:76)(cid:81) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:22)(cid:22) (cid:19)(cid:17)(cid:20)(cid:23)(cid:24) (cid:20)(cid:17)(cid:24) (cid:20)(cid:17)(cid:24) (cid:86)(cid:82)(cid:87)(cid:20)(cid:22)(cid:24)(cid:23)(cid:16)(cid:20)(cid:66)(cid:83)(cid:82) (cid:50)(cid:88)(cid:87)(cid:79)(cid:76)(cid:81)(cid:72) (cid:53)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72)(cid:86) (cid:40)(cid:88)(cid:85)(cid:82)(cid:83)(cid:72)(cid:68)(cid:81) (cid:44)(cid:86)(cid:86)(cid:88)(cid:72)(cid:3)(cid:71)(cid:68)(cid:87)(cid:72) (cid:89)(cid:72)(cid:85)(cid:86)(cid:76)(cid:82)(cid:81) (cid:44)(cid:40)(cid:38) (cid:45)(cid:40)(cid:39)(cid:40)(cid:38) (cid:45)(cid:40)(cid:44)(cid:55)(cid:36) (cid:83)(cid:85)(cid:82)(cid:77)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81) (cid:20)(cid:22)(cid:16)(cid:19)(cid:22)(cid:16)(cid:21)(cid:25) (cid:54)(cid:50)(cid:55)(cid:20)(cid:22)(cid:24)(cid:23)(cid:16)(cid:20) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:20)(cid:22)(cid:16)(cid:19)(cid:27)(cid:16)(cid:21)(cid:26) Fig 39. Package outline SOT1354-1 (XFBGA16) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 40 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander (cid:59)(cid:21)(cid:52)(cid:41)(cid:49)(cid:20)(cid:25)(cid:29)(cid:3)(cid:83)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:15)(cid:3)(cid:87)(cid:75)(cid:72)(cid:85)(cid:80)(cid:68)(cid:79)(cid:3)(cid:72)(cid:81)(cid:75)(cid:68)(cid:81)(cid:70)(cid:72)(cid:71)(cid:3)(cid:86)(cid:88)(cid:83)(cid:72)(cid:85)(cid:3)(cid:87)(cid:75)(cid:76)(cid:81)(cid:3)(cid:84)(cid:88)(cid:68)(cid:71)(cid:3)(cid:73)(cid:79)(cid:68)(cid:87)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:30)(cid:3)(cid:81)(cid:82)(cid:3)(cid:79)(cid:72)(cid:68)(cid:71)(cid:86)(cid:30) (cid:20)(cid:25)(cid:3)(cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:86)(cid:30)(cid:3)(cid:20)(cid:17)(cid:25)(cid:3)(cid:91)(cid:3)(cid:20)(cid:17)(cid:25)(cid:3)(cid:91)(cid:3)(cid:19)(cid:17)(cid:22)(cid:24)(cid:3)(cid:80)(cid:80)(cid:3)(cid:69)(cid:82)(cid:71)(cid:92) (cid:54)(cid:50)(cid:55)(cid:20)(cid:27)(cid:28)(cid:25)(cid:16)(cid:20) (cid:59) (cid:39) (cid:37) (cid:36) (cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:20) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:36) (cid:36)(cid:20) (cid:40) (cid:36)(cid:21) (cid:71)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:59) (cid:72)(cid:20) (cid:38) (cid:47) (cid:72) (cid:69) (cid:145)(cid:3)(cid:89) (cid:38) (cid:36) (cid:37) (cid:92)(cid:20)(cid:38) (cid:92) (cid:145)(cid:3)(cid:90) (cid:38) (cid:39) (cid:69) (cid:38) (cid:72) (cid:72)(cid:20) (cid:37) (cid:47)(cid:20) (cid:36) (cid:20) (cid:21) (cid:22) (cid:23) (cid:38)(cid:3)(cid:19)(cid:17)(cid:20)(cid:19) (cid:69)(cid:20) (cid:87)(cid:72)(cid:85)(cid:80)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:20) (cid:47) (cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:19) (cid:20) (cid:21) (cid:86)(cid:70)(cid:68)(cid:79)(cid:72) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:11)(cid:80)(cid:80)(cid:3)(cid:68)(cid:85)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:82)(cid:85)(cid:76)(cid:74)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:71)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:12) (cid:56)(cid:81)(cid:76)(cid:87) (cid:36) (cid:36)(cid:20) (cid:36)(cid:21) (cid:69) (cid:69)(cid:20) (cid:39) (cid:40) (cid:72) (cid:72)(cid:20) (cid:47) (cid:47)(cid:20) (cid:89) (cid:90) (cid:92) (cid:80)(cid:68)(cid:91) (cid:19)(cid:17)(cid:23)(cid:19) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:21)(cid:21) (cid:19)(cid:17)(cid:21)(cid:26) (cid:20)(cid:17)(cid:26)(cid:19) (cid:20)(cid:17)(cid:26)(cid:19) (cid:80)(cid:80) (cid:81)(cid:82)(cid:80) (cid:19)(cid:17)(cid:22)(cid:24) (cid:19)(cid:17)(cid:20)(cid:19) (cid:19)(cid:17)(cid:20)(cid:26) (cid:19)(cid:17)(cid:21)(cid:21) (cid:20)(cid:17)(cid:25)(cid:19) (cid:20)(cid:17)(cid:25)(cid:19) (cid:19)(cid:17)(cid:23)(cid:19) (cid:20)(cid:17)(cid:21) (cid:19)(cid:17)(cid:20)(cid:21) (cid:19)(cid:17)(cid:19)(cid:25)(cid:24) (cid:19)(cid:17)(cid:20)(cid:24) (cid:19)(cid:17)(cid:19)(cid:24) (cid:19)(cid:17)(cid:20)(cid:19) (cid:80)(cid:76)(cid:81) (cid:19)(cid:17)(cid:22)(cid:19) (cid:19)(cid:17)(cid:19)(cid:19) (cid:19)(cid:17)(cid:20)(cid:21) (cid:19)(cid:17)(cid:20)(cid:26) (cid:20)(cid:17)(cid:24)(cid:19) (cid:20)(cid:17)(cid:24)(cid:19) (cid:86)(cid:82)(cid:87)(cid:20)(cid:27)(cid:28)(cid:25)(cid:16)(cid:20)(cid:66)(cid:83)(cid:82) (cid:50)(cid:88)(cid:87)(cid:79)(cid:76)(cid:81)(cid:72) (cid:53)(cid:72)(cid:73)(cid:72)(cid:85)(cid:72)(cid:81)(cid:70)(cid:72)(cid:86) (cid:40)(cid:88)(cid:85)(cid:82)(cid:83)(cid:72)(cid:68)(cid:81) (cid:44)(cid:86)(cid:86)(cid:88)(cid:72)(cid:3)(cid:71)(cid:68)(cid:87)(cid:72) (cid:89)(cid:72)(cid:85)(cid:86)(cid:76)(cid:82)(cid:81) (cid:44)(cid:40)(cid:38) (cid:45)(cid:40)(cid:39)(cid:40)(cid:38) (cid:45)(cid:40)(cid:44)(cid:55)(cid:36) (cid:83)(cid:85)(cid:82)(cid:77)(cid:72)(cid:70)(cid:87)(cid:76)(cid:82)(cid:81) (cid:20)(cid:25)(cid:16)(cid:19)(cid:27)(cid:16)(cid:20)(cid:26) (cid:54)(cid:50)(cid:55)(cid:20)(cid:27)(cid:28)(cid:25)(cid:16)(cid:20) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:16)(cid:3)(cid:16)(cid:3)(cid:16) (cid:20)(cid:25)(cid:16)(cid:19)(cid:27)(cid:16)(cid:20)(cid:28) Fig 40. Package outline SOT1896-1 (X2QFN16) PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 41 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 42 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure41) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table27 and28 Table 27. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 28. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure41. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 43 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 41. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 44 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 18. Soldering: PCB footprints (cid:41)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87)(cid:3)(cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:85)(cid:72)(cid:73)(cid:79)(cid:82)(cid:90)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:73)(cid:3)(cid:43)(cid:57)(cid:52)(cid:41)(cid:49)(cid:20)(cid:25)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72) (cid:54)(cid:50)(cid:55)(cid:26)(cid:24)(cid:27)(cid:16)(cid:20) (cid:43)(cid:91) (cid:42)(cid:91) (cid:39) (cid:51) (cid:19)(cid:17)(cid:19)(cid:21)(cid:24) (cid:19)(cid:17)(cid:19)(cid:21)(cid:24) (cid:38) (cid:11)(cid:19)(cid:17)(cid:20)(cid:19)(cid:24)(cid:12) (cid:54)(cid:51)(cid:91) (cid:81)(cid:54)(cid:51)(cid:91) (cid:54)(cid:51)(cid:92) (cid:82)(cid:87) (cid:43)(cid:92) (cid:42)(cid:92) (cid:92)(cid:3)(cid:87) (cid:81)(cid:54)(cid:51)(cid:92) (cid:54)(cid:47)(cid:92) (cid:37)(cid:92) (cid:36)(cid:92) (cid:51) (cid:54) (cid:54)(cid:51)(cid:91)(cid:3)(cid:87)(cid:82)(cid:87) (cid:54)(cid:47)(cid:91) (cid:37)(cid:91) (cid:36)(cid:91) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:83)(cid:68)(cid:86)(cid:87)(cid:72)(cid:3)(cid:71)(cid:72)(cid:83)(cid:82)(cid:86)(cid:76)(cid:87) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71)(cid:3)(cid:83)(cid:79)(cid:88)(cid:86)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:83)(cid:68)(cid:86)(cid:87)(cid:72) (cid:82)(cid:70)(cid:70)(cid:88)(cid:83)(cid:76)(cid:72)(cid:71)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:81)(cid:54)(cid:51)(cid:91) (cid:81)(cid:54)(cid:51)(cid:92) (cid:21) (cid:21) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:76)(cid:81)(cid:3)(cid:80)(cid:80) (cid:51) (cid:36)(cid:91) (cid:36)(cid:92) (cid:37)(cid:91) (cid:37)(cid:92) (cid:38) (cid:39) (cid:54)(cid:47)(cid:91) (cid:54)(cid:47)(cid:92) (cid:54)(cid:51)(cid:91)(cid:3)(cid:87)(cid:82)(cid:87) (cid:54)(cid:51)(cid:92)(cid:3)(cid:87)(cid:82)(cid:87) (cid:54)(cid:51)(cid:91) (cid:54)(cid:51)(cid:92) (cid:42)(cid:91) (cid:42)(cid:92) (cid:43)(cid:91) (cid:43)(cid:92) (cid:19)(cid:17)(cid:24)(cid:19) (cid:23)(cid:17)(cid:19)(cid:19) (cid:23)(cid:17)(cid:19)(cid:19) (cid:21)(cid:17)(cid:21)(cid:19) (cid:21)(cid:17)(cid:21)(cid:19) (cid:19)(cid:17)(cid:28)(cid:19) (cid:19)(cid:17)(cid:21)(cid:23) (cid:20)(cid:17)(cid:24)(cid:19) (cid:20)(cid:17)(cid:24)(cid:19) (cid:19)(cid:17)(cid:28)(cid:19) (cid:19)(cid:17)(cid:28)(cid:19) (cid:19)(cid:17)(cid:22)(cid:19) (cid:19)(cid:17)(cid:22)(cid:19) (cid:22)(cid:17)(cid:22)(cid:19) (cid:22)(cid:17)(cid:22)(cid:19) (cid:23)(cid:17)(cid:21)(cid:24) (cid:23)(cid:17)(cid:21)(cid:24) (cid:20)(cid:21)(cid:16)(cid:19)(cid:22)(cid:16)(cid:19)(cid:26) (cid:44)(cid:86)(cid:86)(cid:88)(cid:72)(cid:3)(cid:71)(cid:68)(cid:87)(cid:72) (cid:86)(cid:82)(cid:87)(cid:26)(cid:24)(cid:27)(cid:16)(cid:20)(cid:66)(cid:73)(cid:85) (cid:20)(cid:21)(cid:16)(cid:19)(cid:22)(cid:16)(cid:19)(cid:27) Fig 42. PCB footprint for SOT758-1 (HVQFN16); reflow soldering PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 45 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander (cid:41)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87)(cid:3)(cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:85)(cid:72)(cid:73)(cid:79)(cid:82)(cid:90)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:73)(cid:3)(cid:55)(cid:54)(cid:54)(cid:50)(cid:51)(cid:20)(cid:25)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72) (cid:54)(cid:50)(cid:55)(cid:23)(cid:19)(cid:22)(cid:16)(cid:20) (cid:43)(cid:91) (cid:42)(cid:91) (cid:51)(cid:21) (cid:11)(cid:19)(cid:17)(cid:20)(cid:21)(cid:24)(cid:12) (cid:11)(cid:19)(cid:17)(cid:20)(cid:21)(cid:24)(cid:12) (cid:43)(cid:92) (cid:42)(cid:92) (cid:37)(cid:92) (cid:36)(cid:92) (cid:38) (cid:39)(cid:21)(cid:3)(cid:11)(cid:23)(cid:91)(cid:12) (cid:51)(cid:20) (cid:39)(cid:20) (cid:42)(cid:72)(cid:81)(cid:72)(cid:85)(cid:76)(cid:70)(cid:3)(cid:73)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87)(cid:3)(cid:83)(cid:68)(cid:87)(cid:87)(cid:72)(cid:85)(cid:81)(cid:3) (cid:53)(cid:72)(cid:73)(cid:72)(cid:85)(cid:3)(cid:87)(cid:82)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:3)(cid:82)(cid:88)(cid:87)(cid:79)(cid:76)(cid:81)(cid:72)(cid:3)(cid:71)(cid:85)(cid:68)(cid:90)(cid:76)(cid:81)(cid:74)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:79)(cid:68)(cid:92)(cid:82)(cid:88)(cid:87) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71) (cid:82)(cid:70)(cid:70)(cid:88)(cid:83)(cid:76)(cid:72)(cid:71)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:39)(cid:44)(cid:48)(cid:40)(cid:49)(cid:54)(cid:44)(cid:50)(cid:49)(cid:54)(cid:3)(cid:76)(cid:81)(cid:3)(cid:80)(cid:80) (cid:51)(cid:20) (cid:51)(cid:21) (cid:36)(cid:92) (cid:37)(cid:92) (cid:38) (cid:39)(cid:20) (cid:39)(cid:21) (cid:42)(cid:91) (cid:42)(cid:92) (cid:43)(cid:91) (cid:43)(cid:92) (cid:19)(cid:17)(cid:25)(cid:24)(cid:19) (cid:19)(cid:17)(cid:26)(cid:24)(cid:19) (cid:26)(cid:17)(cid:21)(cid:19)(cid:19) (cid:23)(cid:17)(cid:24)(cid:19)(cid:19) (cid:20)(cid:17)(cid:22)(cid:24)(cid:19) (cid:19)(cid:17)(cid:23)(cid:19)(cid:19) (cid:19)(cid:17)(cid:25)(cid:19)(cid:19) (cid:24)(cid:17)(cid:25)(cid:19)(cid:19) (cid:24)(cid:17)(cid:22)(cid:19)(cid:19) (cid:24)(cid:17)(cid:27)(cid:19)(cid:19) (cid:26)(cid:17)(cid:23)(cid:24)(cid:19) (cid:86)(cid:82)(cid:87)(cid:23)(cid:19)(cid:22)(cid:16)(cid:20)(cid:66)(cid:73)(cid:85) Fig 43. PCB footprint for SOT403-1 (TSSOP16); reflow soldering PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 46 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander (cid:41)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87)(cid:3)(cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:85)(cid:72)(cid:73)(cid:79)(cid:82)(cid:90)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:73)(cid:3)(cid:59)(cid:52)(cid:41)(cid:49)(cid:20)(cid:25)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72) (cid:54)(cid:50)(cid:55)(cid:20)(cid:20)(cid:25)(cid:20)(cid:16)(cid:20) (cid:21)(cid:17)(cid:22)(cid:24) (cid:21)(cid:17)(cid:20)(cid:3)(cid:38)(cid:56) (cid:20)(cid:17)(cid:25)(cid:24) (cid:19)(cid:17)(cid:23)(cid:3)(cid:11)(cid:20)(cid:21)(cid:238)(cid:12) (cid:19)(cid:17)(cid:23)(cid:24) (cid:19)(cid:17)(cid:21)(cid:21)(cid:3) (cid:38)(cid:56)(cid:3) (cid:11)(cid:20)(cid:25)(cid:238)(cid:12) (cid:20)(cid:17)(cid:27)(cid:3) (cid:21)(cid:17)(cid:28)(cid:3) (cid:22)(cid:17)(cid:20)(cid:24) (cid:20)(cid:17)(cid:25)(cid:24) (cid:38)(cid:56) (cid:38)(cid:56) (cid:19)(cid:17)(cid:28)(cid:3) (cid:38)(cid:56) (cid:20)(cid:3) (cid:38)(cid:56) (cid:83)(cid:79)(cid:68)(cid:70)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71)(cid:3)(cid:83)(cid:79)(cid:88)(cid:86)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:83)(cid:68)(cid:86)(cid:87)(cid:72) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:85)(cid:72)(cid:86)(cid:76)(cid:86)(cid:87)(cid:15)(cid:3)(cid:19)(cid:17)(cid:19)(cid:25)(cid:21)(cid:24)(cid:3)(cid:68)(cid:85)(cid:82)(cid:88)(cid:81)(cid:71)(cid:3)(cid:70)(cid:82)(cid:83)(cid:83)(cid:72)(cid:85) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:83)(cid:68)(cid:86)(cid:87)(cid:72)(cid:3)(cid:71)(cid:72)(cid:83)(cid:82)(cid:86)(cid:76)(cid:87)(cid:15)(cid:3)(cid:16)(cid:19)(cid:17)(cid:19)(cid:21)(cid:3)(cid:68)(cid:85)(cid:82)(cid:88)(cid:81)(cid:71)(cid:3)(cid:70)(cid:82)(cid:83)(cid:83)(cid:72)(cid:85)(cid:15)(cid:3) (cid:70)(cid:79)(cid:72)(cid:68)(cid:85)(cid:68)(cid:81)(cid:70)(cid:72)(cid:15)(cid:3)(cid:19)(cid:17)(cid:20)(cid:21)(cid:24)(cid:3)(cid:68)(cid:85)(cid:82)(cid:88)(cid:81)(cid:71)(cid:3)(cid:82)(cid:70)(cid:70)(cid:88)(cid:83)(cid:76)(cid:72)(cid:71)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:86)(cid:87)(cid:72)(cid:81)(cid:70)(cid:76)(cid:79)(cid:3)(cid:87)(cid:75)(cid:76)(cid:70)(cid:78)(cid:81)(cid:72)(cid:86)(cid:86)(cid:3)(cid:19)(cid:17)(cid:20)(cid:3) (cid:82)(cid:3)(cid:70)(cid:70)(cid:88)(cid:83)(cid:76)(cid:72)(cid:71)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:76)(cid:81)(cid:3)(cid:80)(cid:80) (cid:86)(cid:82)(cid:87)(cid:20)(cid:20)(cid:25)(cid:20)(cid:16)(cid:20)(cid:66)(cid:73)(cid:85) Fig 44. PCB footprint for SOT1161-1 (XQFN16); reflow soldering PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 47 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander (cid:41)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87)(cid:3)(cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:85)(cid:72)(cid:73)(cid:79)(cid:82)(cid:90)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:73)(cid:3)(cid:59)(cid:21)(cid:52)(cid:41)(cid:49)(cid:20)(cid:25)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:3) (cid:54)(cid:50)(cid:55)(cid:20)(cid:27)(cid:28)(cid:25)(cid:16)(cid:20) (cid:20)(cid:17)(cid:27)(cid:20) (cid:19)(cid:17)(cid:22)(cid:26) (cid:19)(cid:17)(cid:22) (cid:19)(cid:17)(cid:22)(cid:21) (cid:83)(cid:76)(cid:81)(cid:3)(cid:36)(cid:20) (cid:19)(cid:17)(cid:23)(cid:21)(cid:24) (cid:19)(cid:17)(cid:23) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19)(cid:17)(cid:22)(cid:26) (cid:19)(cid:17)(cid:22) (cid:19)(cid:17)(cid:21)(cid:24) (cid:19)(cid:17)(cid:22)(cid:21) (cid:19)(cid:17)(cid:23)(cid:21)(cid:24) (cid:20)(cid:17)(cid:27)(cid:20) (cid:19)(cid:17)(cid:19)(cid:27) (cid:19)(cid:17)(cid:23) (cid:19)(cid:17)(cid:20)(cid:24) (cid:19)(cid:17)(cid:20)(cid:24) (cid:19)(cid:17)(cid:19)(cid:27) (cid:82)(cid:70)(cid:70)(cid:88)(cid:83)(cid:76)(cid:72)(cid:71)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:85)(cid:72)(cid:86)(cid:76)(cid:86)(cid:87) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71)(cid:86) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:83)(cid:68)(cid:86)(cid:87)(cid:72) (cid:39)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:3)(cid:76)(cid:81)(cid:3)(cid:80)(cid:80) (cid:20)(cid:25)(cid:16)(cid:19)(cid:27)(cid:16)(cid:20)(cid:21) (cid:44)(cid:86)(cid:86)(cid:88)(cid:72)(cid:3)(cid:71)(cid:68)(cid:87)(cid:72) (cid:86)(cid:82)(cid:87)(cid:20)(cid:27)(cid:28)(cid:25)(cid:16)(cid:20)(cid:66)(cid:73)(cid:85) (cid:20)(cid:25)(cid:16)(cid:19)(cid:28)(cid:16)(cid:19)(cid:25) Fig 45. PCB footprint for SOT1896-1 (X2QFN16); reflow soldering PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 48 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 19. Abbreviations Table 29. Abbreviations Acronym Description ESD ElectroStatic Discharge FET Field-Effect Transistor GPIO General-Purpose Input/Output I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light-Emitting Diode LSB Least Significant Bit MSB Most Significant Bit PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus 20. Revision history Table 30. Revision history Document ID Release date Data sheet status Change notice Supersedes PCAL6408A v.3.2 20170419 Product data sheet - PCAL6408A v.3.1 Modifications: • Removed “PCAL6408AEX1/X2QFN16” from Figure 5 “Pin configuration for 1.6mm´1.6mm XFBGA16” • Added Figure 6 “Pin configuration for 1.6mm´1.6mm X2QFN16 EX1 land grid array” • Table 1 “Ordering information”, PCAL6408AEX1 topside mark changed from “18” to “18X”; added Table note2 indicating topside marking work week; added “land grid array” to description • Table 3 “Pin description”, XFBGA16, X2QFN16: Corrected pin assignment from “D5” to “D4” PCAL6408A v.3.1 20161102 Product data sheet - PCAL6408A v.3 Modifications: • Added PCAL6408AEX1 PCAL6408A v.3 20130918 Product data sheet - PCAL6408A v.2 PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 49 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Table 30. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes Modifications: • Section 2 “Features and benefits”, 17th bullet item: added “XFBGA16” • Table 1 “Ordering information”: added Type number PCAL6408AEX • Table 2 “Ordering options”: added Type number PCAL6408AEX • Added (new) Figure5 “Pin configuration for 1.6mm1.6mm XFBGA16” • Added (new) Figure6 “Ball mapping for 1.6mm1.6mmXFBGA16” • Table 3 “Pin description”: added column “XFBGA16” • Table 6 “Command byte”, register “Output port configuration”: – Pointer register bits corrected from “01000111” to “01001111” (correction to documentation, no functional change to device) – Command byte corrected from “47h” to “4Fh” (correction to documentation, no functional change to device) • Section 7.4.11 “Output port configuration register (4Fh)”: – register number corrected from “47h” to “4Fh” in Section title (correction to documentation, no functional change to device) – first paragraph, third sentence: register number corrected from “(47h)” to “(4Fh)” (correction to documentation, no functional change to device) – register number corrected from “47h” to “4Fh” in title of Table18 (correction to documentation, no functional change to device) • Added (new) Figure 39 “Package outline SOT1354-1 (XFBGA16)” PCAL6408A v.2 20121206 Product data sheet - PCAL6408A v.1 PCAL6408A v.1 20120906 Product data sheet - - PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 50 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 21.2 Definitions Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Draft — The document is a draft version only. The content is still under malfunction of an NXP Semiconductors product can reasonably be expected internal review and subject to formal approval, which may result in to result in personal injury, death or severe property or environmental modifications or additions. NXP Semiconductors does not give any damage. NXP Semiconductors and its suppliers accept no liability for representations or warranties as to the accuracy or completeness of inclusion and/or use of NXP Semiconductors products in such equipment or information included herein and shall have no liability for the consequences of applications and therefore such inclusion and/or use is at the customer’s own use of such information. risk. Short data sheet — A short data sheet is an extract from a full data sheet Applications — Applications that are described herein for any of these with the same product type number(s) and title. A short data sheet is intended products are for illustrative purposes only. NXP Semiconductors makes no for quick reference only and should not be relied upon to contain detailed and representation or warranty that such applications will be suitable for the full information. For detailed and full information see the relevant full data specified use without further testing or modification. sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their deemed to offer functions and qualities beyond those described in the applications and products. Product data sheet. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the 21.3 Disclaimers customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Limited warranty and liability — Information in this document is believed to Semiconductors products in order to avoid a default of the applications and be accurate and reliable. However, NXP Semiconductors does not give any the products or of the application or use by customer’s third party representations or warranties, expressed or implied, as to the accuracy or customer(s). NXP does not accept any liability in this respect. completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC60134) will cause permanent source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in In no event shall NXP Semiconductors be liable for any indirect, incidental, the Recommended operating conditions section (if present) or the punitive, special or consequential damages (including - without limitation - lost Characteristics sections of this document is not warranted. Constant or profits, lost savings, business interruption, costs related to the removal or repeated exposure to limiting values will permanently and irreversibly affect replacement of any products or rework charges) whether or not such the quality and reliability of the device. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of NXP Semiconductors products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 51 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander Export control — This document as well as the item(s) described herein own risk, and (c) customer fully indemnifies NXP Semiconductors for any may be subject to export control regulations. Export might require a prior liability, damages or failed product claims resulting from customer design and authorization from competent authorities. use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, Translations — A non-English (translated) version of a document is for the product is not suitable for automotive use. It is neither qualified nor tested reference only. The English version shall prevail in case of any discrepancy in accordance with automotive testing or application requirements. NXP between the translated and English versions. Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 21.4 Trademarks In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks (a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP B.V. NXP Semiconductors’ specifications such use shall be solely at customer’s 22. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCAL6408A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 3.2 — 19 April 2017 52 of 53

PCAL6408A NXP Semiconductors Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander 23. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 15 Parameter measurement information. . . . . . 33 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 37 2.1 Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 3 17 Soldering of SMD packages. . . . . . . . . . . . . . 42 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 42 3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 4 17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 42 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42 17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 18 Soldering: PCB footprints . . . . . . . . . . . . . . . 45 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 Voltage translation. . . . . . . . . . . . . . . . . . . . . . . 8 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 49 7 Functional description . . . . . . . . . . . . . . . . . . . 8 21 Legal information . . . . . . . . . . . . . . . . . . . . . . 51 7.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 8 21.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 51 7.2 Interface definition . . . . . . . . . . . . . . . . . . . . . . 9 21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.3 Pointer register and command byte . . . . . . . . . 9 21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.4 Register descriptions . . . . . . . . . . . . . . . . . . . 10 21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.4.1 Input port register (00h) . . . . . . . . . . . . . . . . . 10 22 Contact information . . . . . . . . . . . . . . . . . . . . 52 7.4.2 Output port register (01h). . . . . . . . . . . . . . . . 10 23 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.4.3 Polarity inversion register (02h) . . . . . . . . . . . 10 7.4.4 Configuration register (03h) . . . . . . . . . . . . . . 10 7.4.5 Output drive strength registers (40h, 41h) . . . 11 7.4.6 Input latch register (42h). . . . . . . . . . . . . . . . . 11 7.4.7 Pull-up/pull-down enable register (43h) . . . . . 12 7.4.8 Pull-up/pull-down selection register (44h). . . . 12 7.4.9 Interrupt mask register (45h) . . . . . . . . . . . . . 12 7.4.10 Interrupt status register (46h). . . . . . . . . . . . . 13 7.4.11 Output port configuration register (4Fh) . . . . . 13 7.5 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 Reset input (RESET) . . . . . . . . . . . . . . . . . . . 15 7.8 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 15 8 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 16 8.1 Write commands. . . . . . . . . . . . . . . . . . . . . . . 16 8.2 Read commands . . . . . . . . . . . . . . . . . . . . . . 17 9 Application design-in information . . . . . . . . . 19 9.1 Minimizing I when I/Os control LEDs . . . . . 19 DD 9.2 Output drive strength control . . . . . . . . . . . . . 20 9.3 Power-on reset requirements. . . . . . . . . . . . . 21 9.4 Device current consumption with internal pull-up and pull-down resistors. . . . . . . . . . . . . . . . . . 23 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24 11 Recommended operating conditions. . . . . . . 24 12 Thermal characteristics . . . . . . . . . . . . . . . . . 25 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 25 13.1 Typical characteristics . . . . . . . . . . . . . . . . . . 28 14 Dynamic characteristics. . . . . . . . . . . . . . . . . 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 April 2017 Document identifier: PCAL6408A

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: PCAL6408AHKX PCAL6408ABSHP PCAL6408APWJ PCAL6408AEXX PCAL6408AEX1Z