PCA9626 24-bit Fm+ I2C-bus 100 mA 40 V LED driver Rev. 5 — 19 June 2014 Product data sheet 1. General description The PCA9626 is an I2C-bus controlled 24-bit LED driver optimized for voltage switch dimming and blinking 100mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individualPWM controller that operates at 97kHz with a duty cycle that is adjustable from 0% to 99.6% to allow the LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) groupPWM controller has both a fixed frequency of 190Hz and an adjustable frequency between 24Hz to once every 10.73seconds with a duty cycle that is adjustable from 0% to 99.6% that is used to either dim or blink all LEDs with the same value. Each LED output can be off, on (no PWM control), set at its individualPWM controller value or at both individual and group PWM controller values. The PCA9626 operates with a supply voltage range of 2.3V to 5.5V and the 100mA open-drain outputs allow voltages up to 40V. The PCA9626 is one of the first LED controller devices in a new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequency (up to 1MHz) and more densely populated bus operation (up to 4000pF). The activeLOW Output Enable input pin (OE) blinks all the LED outputs and can be used to externally PWM the outputs, which is useful when multiple devices must be dimmed or blinked together without using software control. Software programmable LED Group and three Sub Call I2C-bus addresses allow all or defined groups of PCA9626 devices to respond to a common I2C-bus address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C-bus commands. Seven hardware address pins allow up to 126devices on the same bus. The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9626 through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to their default state causing the output NAND FETs to be OFF (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition. In addition to these features found in PCA9633, PCA9634, PCA9635, PCA9622 and PCA9624, a new feature to control LED output pattern is incorporated in the PCA9626. A new control byte called ‘Chase Byte’ allows enabling or disabling of selective LED outputs depending on the value of the Chase Byte. This feature greatly reduces the number of bytes to be sent to the PCA9626 when repetitive patterns must be displayed as in creating a marquee chasing effect. If the PCA9626 on-chip 100mA NAND FETs do not provide enough current or voltage to drive the LEDs, then the PCA9634 and the PCA9635 with larger current or higher voltage external drivers can be used.

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 2. Features and benefits  24 LED drivers. Each output programmable at: Off On Programmable LED brightness Programmable group dimming/blinking mixed with individual LED brightness  1MHz Fast-mode Plus compatible I2C-bus interface with 30mA high drive capability on SDA output for driving high capacitive buses  256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness using a 97kHz PWM signal  256-step group brightness control allows general dimming (using a 190Hz PWM signal) from fully off to maximum brightness (default)  256-step group blinking with frequency programmable from 24Hz to 10.73s and dutycycle from 0% to 99.6%  24 open-drain outputs can sink between 0mA to 100mA and are tolerant to a maximum off state voltage of 40V. No input function.  Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).  Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of the LEDs  7 hardware address pins allow 126 PCA9626 devices to be connected to the same I2C-bus and to be individually programmed  4 software programmable I2C-bus addresses (one LED Group Call address and three LED Sub Call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for ‘All Call’ so that all the PCA9626s on the I2C-bus can be addressed at the same time and the second register used for three different addresses so that 1⁄ of all devices on the bus can be addressed at the 3 same time in a group). Software enable and disable for I2C-bus address.  A Chase Byte allows execution of predefined ON/OFF pattern for the 24 LED outputs  Software Reset feature (SWRSTCall) allows the device to be reset through the I2C-bus  25MHz internal oscillator requires no external components  Internal power-on reset  Noise filter on SDA/SCL inputs  No glitch on power-up  Supports hot insertion  Low standby current  Operating power supply voltage (V ) range of 2.3V to 5.5V DD  5.5V tolerant inputs on non-LED pins  40C to +85C operation  ESD protection exceeds 2000V HBM per JESD22-A114 and 1000V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA  Packages offered: LQFP48 PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 2 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 3. Applications  RGB or RGBA LED drivers  LED status information  LED displays  LCD backlights  Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering info rmation Type number Topside Package mark Name Description Version PCA9626B PCA9626 LQFP48 plastic low profile quad flat package; 48leads; body771.4mm SOT313-2 4.1 Ordering options Table 2. Ordering opt ions Type number Orderable Package Packing method Minimum Temperature partnumber orderquantity PCA9626B PCA9626B,118 LQFP48 Reel 13” Q1/T1 2000 T = 40C to +85C amb *Standard mark SMD PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 3 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 5. Block diagram A0 A1 A2 A3 A4 A5 A6 SCL INPUT FILTER SDA I2C-BUS CONTROL PCA9626 POWER-ON VDD RESET VSS LED STATE SELECT REGISTER PWM REGISTER X LEDn BRIGHTNESS CONTROL 97 kHz 24.3 kHz GRPFREQ MUX/ FET CONTROL DRIVER REGISTER GRPPWM 25 MHz REGISTER OSCILLATOR 190 Hz '0' – permanently OFF '1' – permanently ON OE 002aad608 Remark: Only one LED output shown for clarity. Fig 1. Block diagram of PCA9626 PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 4 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 6. Pinning information 6.1 Pinning 3 2 1 0 2 2 2 2 SS 1 0 SS ED ED ED ED DD DA CL SS V A A V L L L L V S S V 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 VSS 1 36 VSS LED0 2 35 LED19 LED1 3 34 LED18 LED2 4 33 LED17 LED3 5 32 LED16 VSS 6 PCA9626B 31 VSS VSS 7 30 VSS LED4 8 29 LED15 LED5 9 28 LED14 LED6 10 27 LED13 LED7 11 26 LED12 VSS 12 25 VSS 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 002aad662 2 3 4 S 8 9 0 1 S 5 6 E A A A S D D 1 1 S A A O V E E D D V L L E E L L Fig 2. Pin configuration for LQFP48 6.2 Pin description Table 3. Pin description Symbol Pin Type Description LED22 43 O LED driver 22 LED23 44 O LED driver 23 V 1, 6, 7, 12, 16, 21, 25, power supply supply ground SS 30, 31, 36, 37, 45, 48 A0 46 I address input 0 A1 47 I address input 1 LED0 2 O LED driver 0 LED1 3 O LED driver 1 LED2 4 O LED driver 2 LED3 5 O LED driver 3 LED4 8 O LED driver 4 LED5 9 O LED driver 5 LED6 10 O LED driver 6 LED7 11 O LED driver 7 A2 13 I address input 2 A3 14 I address input 3 PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 5 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver Table 3. Pin description …continued Symbol Pin Type Description A4 15 I address input 4 LED8 17 O LED driver 8 LED9 18 O LED driver 9 LED10 19 O LED driver 10 LED11 20 O LED driver 11 A5 22 I address input 5 A6 23 I address input 6 OE 24 I active LOW output enable LED12 26 O LED driver 12 LED13 27 O LED driver 13 LED14 28 O LED driver 14 LED15 29 O LED driver 15 LED16 32 O LED driver 16 LED17 33 O LED driver 17 LED18 34 O LED driver 18 LED19 35 O LED driver 19 SCL 38 I serial clock line SDA 39 I/O serial data line V 40 power supply supply voltage DD LED20 41 O LED driver 20 LED21 42 O LED driver 21 PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 6 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7. Functional description Refer to Figure 1 “Block diagram of PCA9626”. 7.1 Device addresses Following a START condition, the bus master must output the address of the slave it is accessing. There are a maximum of 128 possible programmable addresses using the 7 hardware address pins. Two of these addresses, Software Reset and LED All Call, cannot be used because their default power-up state is ON, leaving a maximum of 126 addresses. Using other reserved addresses, as well as any other Sub Call address, reduces the total number of possible addresses even further. 7.1.1 Regular I2C-bus slave address The I2C-bus slave address of the PCA9626 is shown in Figure3. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW externally. Remark: Using reserved I2C-bus addresses interferes with other devices, but only if the devices are on the bus and/or the bus is open to other I2C-bus systems at some later date. In a closed system where the designer controls the address assignment these addresses can be used since the PCA9626 treats them like any other address. The LEDAllCall, Software Rest and PCA9564 or PCA9665 slave address (if on the bus) can never be used for individual device addresses. • PCA9626 LED All Call address (1110000) and Software Reset (00000110) which are active on start-up • PCA9564 (0000000) or PCA9665 (1110000) slave address which is active on start-up • ‘reserved for future use’ I2C-bus addresses (0000011, 11111XX) • slave devices that use the 10-bit addressing scheme (11110XX) • slave devices that are designed to respond to the General Call address (0000000) • High-speed mode (Hs-mode) master code (00001XX) slave address A6 A5 A4 A3 A2 A1 A0 R/W hardware selectable 002aab319 Fig 3. Slave address The last bit of the address byte defines the operation to be performed. When set to logic1 a read is selected, while a logic0 selects a write operation. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 7 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.1.2 LED All Call I2C-bus address • Default power-up value (ALLCALLADR register): E0h or 1110000 • Programmable through I2C-bus (volatile programming) • At power-up, LED All Call I2C-bus address is enabled. PCA9626 sends an ACK when E0h (R/W=0) or E1h (R/W=1) is sent by the master. See Section 7.3.9 “ALLCALLADR, LED All Call I2C-bus address” for more detail. Remark: The default LED All Call I2C-bus address (E0h or 1110000) must not be used as a regular I2C-bus slave address since this address is enabled at power-up. All of the PCA9626s on the I2C-bus acknowledge the address if sent by the I2C-bus master. 7.1.3 LED Sub Call I2C-bus addresses • 3 different I2C-bus addresses can be used • Default power-up values: – SUBADR1 register: E2h or 1110001 – SUBADR2 register: E4h or 1110010 – SUBADR3 register: E8h or 1110100 • Programmable through I2C-bus (volatile programming) • At power-up, Sub Call I2C-bus addresses are disabled. PCA9626 does not send an ACK when E2h (R/W=0) or E3h (R/W=1), E4h (R/W=0) or E5h (R/W=1), or E8h(R/W=0) or E9h (R/W=1) is sent by the master. See Section 7.3.8 “SUBADR1 to SUBADR3, I2C-bus subaddress1to3” for more detail. Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus slave addresses as long as they are disabled. 7.1.4 Software Reset I2C-bus address The address shown in Figure4 is used when a reset of the PCA9626 must be performed by the master. The Software Reset address (SWRST Call) must be used with R/W=logic0. If R/W=logic1, the PCA9626 does not acknowledge the SWRST. See Section 7.6 “Software reset” for more detail. R/W 0 0 0 0 0 1 1 0 002aab416 Fig 4. Software Reset address Remark: The Software Reset I2C-bus address is a reserved address and cannot be used as a regular I2C-bus slave address or as an LED AllCall or LED Sub Call address. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 8 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.2 Control register Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master sends a byte to the PCA9626, which is stored in the Control register. The lowest 6bits are used as a pointer to determine which register is accessed (D[5:0]). The highest bit is used as Auto-Increment Flag (AIF). This bit along with the MODE1 register bit5 and bit6 provide the Auto-Increment feature. Bit6 of the Control register is not used. register address AIF X D5 D4 D3 D2 D1 D0 Don't care Auto-Increment Flag 002aad610 reset state = 80h Remark: The Control register does not apply to the Software Reset I2C-bus address. Fig 5. Control register When the Auto-Increment Flag is set (AIF=logic1), the six low-order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values of MODE1 register. T able 4. Auto-Increment options AIF AI1[1] AI0[1] Function 0 0 0 no Auto-Increment 1 0 0 Auto-Increment for all registers. D[5:0] roll over to 0h after the last register 26h is accessed. 1 0 1 Auto-Increment for individual brightness registers only. D[5:0] roll over to 2h after the last register (19h) is accessed. 1 1 0 Auto-Increment for global control registers and CHASE register. D[5:0] rollover to 1Ah after the last register (1Ch) is accessed. 1 1 1 Auto-Increment for individual brightness registers; global control registers and CHASE register. D[5:0] roll over to 2h after the last register (1Ch) is accessed. [1] AI1 and AI0 come from MODE1 register. Remark: Other combinations not shown in Table4 (AIF + AI[1:0] = 001b, 010b, 011b and 111b) are reserved and must not be used for proper device operation. AIF+AI[1:0]=000b is used when the same register must be accessed several times during a single I2C-bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation. AIF+AI[1:0]=100b is used when all the registers must be sequentially accessed, for example, power-up programming. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 9 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver AIF+AI[1:0]=101b is used when the 16 LED drivers must be individually programmed with different values during the same I2C-bus communication, for example, changing color setting to another color setting. AIF+AI[1:0]=110b is used when the LED drivers must be globally programmed with different settings during the same I2C-bus communication, for example, global brightness or blinking change. AIF+AI[1:0]=111b is used when the 16LED drivers must be individually programmed with different values in addition to global programming. Only the 6 least significant bits D[5:0] are affected by the AIF, AI1 and AI0 bits. When the Control register is written, the register entry point determined by D[5:0] is the first register that is addressed (read or write operation), and can be anywhere between 0h and 26h (as defined in Table5). When AIF=1, the Auto-Increment Flag is set and the rollover value at which the register increment stops and goes to the next one is determined by AIF, AI1 and AI2. See Table4 for rollover values. For example, if MODE1 register bit AI1=0 and AI0=1 and if the Control register = 10010010, then the register addressing sequence is (in hexadecimal): 1213…190203…1902… as long as the master keeps sending or reading data. 7.3 Register definitions Table 5. Register sum mary[1] Register number D5 D4 D3 D2 D1 D0 Name Type Function 00h 0 0 0 0 0 0 MODE1 read/write Mode register 1 01h 0 0 0 0 0 1 MODE2 read/write Mode register 2 02h 0 0 0 0 1 0 PWM0 read/write brightness control LED0 03h 0 0 0 0 1 1 PWM1 read/write brightness control LED1 04h 0 0 0 1 0 0 PWM2 read/write brightness control LED2 05h 0 0 0 1 0 1 PWM3 read/write brightness control LED3 06h 0 0 0 1 1 0 PWM4 read/write brightness control LED4 07h 0 0 0 1 1 1 PWM5 read/write brightness control LED5 08h 0 0 1 0 0 0 PWM6 read/write brightness control LED6 09h 0 0 1 0 0 1 PWM7 read/write brightness control LED7 0Ah 0 0 1 0 1 0 PWM8 read/write brightness control LED8 0Bh 0 0 1 0 1 1 PWM9 read/write brightness control LED9 0Ch 0 0 1 1 0 0 PWM10 read/write brightness control LED10 0Dh 0 0 1 1 0 1 PWM11 read/write brightness control LED11 0Eh 0 0 1 1 1 0 PWM12 read/write brightness control LED12 0Fh 0 0 1 1 1 1 PWM13 read/write brightness control LED13 10h 0 1 0 0 0 0 PWM14 read/write brightness control LED14 11h 0 1 0 0 0 1 PWM15 read/write brightness control LED15 12h 0 1 0 0 1 0 PWM16 read/write brightness control LED16 13h 0 1 0 0 1 1 PWM17 read/write brightness control LED17 14h 0 1 0 1 0 0 PWM18 read/write brightness control LED18 PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 10 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver Table 5. Register summary[1] …continued Register number D5 D4 D3 D2 D1 D0 Name Type Function 15h 0 1 0 1 0 1 PWM19 read/write brightness control LED19 16h 0 1 0 1 1 0 PWM20 read/write brightness control LED20 17h 0 1 0 1 1 1 PWM21 read/write brightness control LED21 18h 0 1 1 0 0 0 PWM22 read/write brightness control LED22 19h 0 1 1 0 0 1 PWM23 read/write brightness control LED23 1Ah 0 1 1 0 1 0 GRPPWM read/write group duty cycle control 1Bh 0 1 1 0 1 1 GRPFREQ read/write group frequency 1Ch 0 1 1 1 0 0 CHASE read/write chase control 1Dh 0 1 1 1 0 1 LEDOUT0 read/write LED output state 0 1Eh 0 1 1 1 1 0 LEDOUT1 read/write LED output state 1 1Fh 0 1 1 1 1 1 LEDOUT2 read/write LED output state 2 20h 1 0 0 0 0 0 LEDOUT3 read/write LED output state 3 21h 1 0 0 0 0 1 LEDOUT4 read/write LED output state 4 22h 1 0 0 0 1 0 LEDOUT5 read/write LED output state 5 23h 1 0 0 0 1 1 SUBADR1 read/write I2C-bus subaddress 1 24h 1 0 0 1 0 0 SUBADR2 read/write I2C-bus subaddress 2 25h 1 0 0 1 0 1 SUBADR3 read/write I2C-bus subaddress 3 26h 1 0 0 1 1 0 ALLCALLADR read/write LED All Call I2C-bus address [1] Only D[5:0]=000000to100110 are allowed and are acknowledged. D[5:0]=100111 to 111111 are reserved and may not be acknowledged. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 11 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.3.1 Mode register 1, MODE1 Table 6. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access Value Description 7 AI2 read only 0 Register Auto-Increment disabled. 1* Register Auto-Increment enabled. 6 AI1 R/W 0* Auto-Increment bit1=0. Auto-increment range as defined in Table4. 1 Auto-Increment bit1=1. Auto-increment range as defined in Table4. 5 AI0 R/W 0* Auto-Increment bit0=0. Auto-increment range as defined in Table4. 1 Auto-Increment bit0=1. Auto-increment range as defined in Table4. 4 SLEEP[1] R/W 0 Normal mode[2]. 1* Low-power mode. Oscillator off[3]. 3 SUB1 R/W 0* PCA9626 does not respond to I2C-bus subaddress 1. 1 PCA9626 responds to I2C-bus subaddress 1. 2 SUB2 R/W 0* PCA9626 does not respond to I2C-bus subaddress 2. 1 PCA9626 responds to I2C-bus subaddress 2. 1 SUB3 R/W 0* PCA9626 does not respond to I2C-bus subaddress 3. 1 PCA9626 responds to I2C-bus subaddress 3. 0 ALLCALL R/W 0 PCA9626 does not respond to LED All Call I2C-bus address. 1* PCA9626 responds to LED All Call I2C-bus address. [1] Bit 4 must be programmed with logic 0 for proper device operation. [2] It takes 500s max. for the oscillator to be up and running once SLEEP bit has been set to logic0. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500s window. [3] No blinking or dimming is possible when the oscillator is off. 7.3.2 Mode register 2, MODE2 Table 7. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. Bit Symbol Access Value Description 7 - read only 0* reserved 6 - read only 0* reserved 5 DMBLNK R/W 0* group control = dimming. 1 group control = blinking. 4 INVRT read only 0* reserved 3 OCH R/W 0* outputs change on STOP command[1] 1 outputs change on ACK 2 - read only 1* reserved 1 - read only 0* reserved 0 - read only 1* reserved PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 12 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver [1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9626. Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only. 7.3.3 PWM0 to PWM23, individual brightness control Table 8. PWM0toPWM23 - PWM registers 0to23 (address 02h to 19h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 02h PWM0 7:0 IDC0[7:0] R/W 00000000* PWM0 Individual Duty Cycle 03h PWM1 7:0 IDC1[7:0] R/W 00000000* PWM1 Individual Duty Cycle 04h PWM2 7:0 IDC2[7:0] R/W 00000000* PWM2 Individual Duty Cycle 05h PWM3 7:0 IDC3[7:0] R/W 00000000* PWM3 Individual Duty Cycle 06h PWM4 7:0 IDC4[7:0] R/W 00000000* PWM4 Individual Duty Cycle 07h PWM5 7:0 IDC5[7:0] R/W 00000000* PWM5 Individual Duty Cycle 08h PWM6 7:0 IDC6[7:0] R/W 00000000* PWM6 Individual Duty Cycle 09h PWM7 7:0 IDC7[7:0] R/W 00000000* PWM7 Individual Duty Cycle 0Ah PWM8 7:0 IDC8[7:0] R/W 00000000* PWM8 Individual Duty Cycle 0Bh PWM9 7:0 IDC9[7:0] R/W 00000000* PWM9 Individual Duty Cycle 0Ch PWM10 7:0 IDC10[7:0] R/W 00000000* PWM10 Individual Duty Cycle 0Dh PWM11 7:0 IDC11[7:0] R/W 00000000* PWM11 Individual Duty Cycle 0Eh PWM12 7:0 IDC12[7:0] R/W 00000000* PWM12 Individual Duty Cycle 0Fh PWM13 7:0 IDC13[7:0] R/W 00000000* PWM13 Individual Duty Cycle 10h PWM14 7:0 IDC14[7:0] R/W 00000000* PWM14 Individual Duty Cycle 11h PWM15 7:0 IDC15[7:0] R/W 00000000* PWM15 Individual Duty Cycle 12h PWM16 7:0 IDC16[7:0] R/W 00000000* PWM16 Individual Duty Cycle 13h PWM17 7:0 IDC17[7:0] R/W 00000000* PWM17 Individual Duty Cycle 14h PWM18 7:0 IDC18[7:0] R/W 00000000* PWM18 Individual Duty Cycle 15h PWM19 7:0 IDC19[7:0] R/W 00000000* PWM19 Individual Duty Cycle 16h PWM20 7:0 IDC20[7:0] R/W 00000000* PWM20 Individual Duty Cycle 17h PWM21 7:0 IDC21[7:0] R/W 00000000* PWM21 Individual Duty Cycle 18h PWM22 7:0 IDC22[7:0] R/W 00000000* PWM22 Individual Duty Cycle 19h PWM23 7:0 IDC23[7:0] R/W 00000000* PWM23 Individual Duty Cycle A 97kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6%dutycycle=LED output at maximum brightness). Applicable to LED outputs programmed with LDRx=10 or 11 (LEDOUT0 to LEDOUT5 registers). IDCx7:0 duty cycle = --------------------------- (1) 256 PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 13 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.3.4 GRPPWM, group duty cycle control Table 9. GRPPWM - Group brightness control register (address 1Ah) bit description Legend: * default value Address Register Bit Symbol Access Value Description 1Ah GRPPWM 7:0 GDC[7:0] R/W 11111111 GRPPWM register When DMBLNK bit (MODE2 register) is programmed with logic0, a 190Hz fixed frequency signal is superimposed with the 97kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’. General brightness for the 16 outputs is controlled through 256 linear steps from 00h (0%duty cycle=LED output off) to FFh (99.6% duty cycle=maximum brightness). Applicable to LED outputs programmed with LDRx=11 (LEDOUT0 to LEDOUT5 registers). When DMBLNK bit is programmed with logic1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 24Hz to 10.73s) and GRPPWM the duty cycle (ON/OFF ratio in%). GDC7:0 duty cycle = -------------------------- (2) 256 7.3.5 GRPFREQ, group frequency Table 10. GRPFREQ - Group Frequency register (address 1Bh) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 1Bh GRPFREQ 7:0 GFRQ[7:0] R/W 00000000* GRPFREQ register GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK=0. Applicable to LED outputs programmed with LDRx=11 (LEDOUT0 to LEDOUT5 registers). Blinking period is controlled through 256 linear steps from 00h (41ms, frequency 24Hz) to FFh (10.73s). GFRQ7:0+1 global blinking period = ----------------------------------------s (3) 24 PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 14 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.3.6 CHASE control Table 11. CHASE - Chase pattern control register (address 1Ch) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 1Ch CHASE 7:0 CHC[7:0] R/W 00000000* CHASE register CHASE is used to program the LED output ON/OFF pattern. The contents of the CHASE register is used to enable one of the LED output patterns, as indicated in Table12. By repeated, sequential access to this table via the CHASE register, a chase pattern, forexample, marquee effect, can be easily programmed with minimal number of commands. Once the CHASE register is accessed, the data bytes that follow are used as an index value to pick the LED output patterns defined by Table 12 “CHASE sequence”. This register always updates on ACK. It is used to gate the OE signal at each of the LEDn pins such that: • OE=1: all LEDs are off • OE=0: those LEDs corresponding to the Xs in Table12 are on Any write to this register takes effect at the ACK. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 15 of 48

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P N rodu CA9626 TXa =b leen 1a2b.ledC; eHmApStyE cseellq =u edniscaebled. XP ct d Command Hex LED channel Description S a e ta sh 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 mic ee 00 00 X X X X X X X X X X X X X X X X X X X X X X X X all LEDs ON o t n 01 01 all LEDs OFF d u 02 02 X X X X X X X X X X X X 1⁄2 chase B c t 03 03 X X X X X X X X X X X X 1⁄ chase A o 2 r s 04 04 X X X X X X X X 1⁄ chase C 3 05 05 X X X X X X X X 1⁄ chase B 3 06 06 X X X X X X X X 1⁄ chase A 3 A 07 07 X LTR_0_ON ll inform (1LefttoRight_START) Rev. 5 — 19 June 2014 ation provided in this document is subject to legal disclaimers. 00111111111890234567 0000000110189ACDEF0B X X X X X X X X X X LLLLLLLLLLTTTTTTTTTTRRRRRRRRRR__________9123456781_________0OOOOOOOOO_ONNNNNNNNNN 24-bit Fm + 18 12 X LTR_11_ON I2 C 19 13 X LTR_12_ON - b u © 20 14 X LTR_13_ON s NX 1 P Semiconductors N.V. 2014. A 2222223451 1111167895 X X X X X LLLLLTTTTTRRRRR_____1111145678_____OOOOONNNNN 00 mA 40 V LE PCA9 16 of 48 ll rights reserved. 2267 11AB X X LLTTRR__1290__OONN D driver 626

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P Table 12. CHASE sequence …continued N rodu CA9626 X = enabled; empty cell = disabled. XP ct d Command Hex LED channel Description S ata 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 em sh 28 1C X LTR_21_ON ic e e o t 29 1D X LTR_22_ON n d 30 1E X LTR_23_ON u c (1LefttoRight_END) t o 31 1F X X 2LefttoRight_START r s 32 20 X X 33 21 X X 34 22 X X All inform 3356 2234 X X X X Rev. 5 — 19 June 2014 ation provided in this document is subject to legal disclaimers. 333444444789012345 22222222256789ABCD X X X X X X X X X X X X X X X X X X X X X 23LLeeffttttooRRiigghhtt__ESNTADRT 24-bit Fm 46 2E X X X + I2 47 2F X X X C - b 48 30 X X X u © s NX 49 31 X X X 1 17 of 48 P Semiconductors N.V. 2014. All rights reserved. 555555012345 333333234567 X X X X X X X X X X X X X X X X X X X X X X X 34LLeeffttttooRRiigghhtt__ESNTADRT 00 mA 40 V LED driver PCA9626

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P Table 12. CHASE sequence …continued N rodu CA9626 X = enabled; empty cell = disabled. XP ct d Command Hex LED channel Description S ata 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 em sh 56 38 X X X X 4LefttoRight_END ic e e o t 57 39 X X X X X 5LefttoRight_START n d 58 3A X X X X X u c 59 3B X X X X X t o r 60 3C X X X X X s 61 3D X X X X 5LefttoRight_END 62 3E X X X X X X 6LefttoRight_START 63 3F X X X X X X A ll inform 64 40 X X X X X X Rev. 5 — 19 June 2014 ation provided in this document is subject to legal disclaimers. 66666777775678901234 4444444444123456789A X X X X X X X X X X X X XX XX XX XX XX XX 16LImepftlotodeR_igShTtA_ERNTD 24-bit Fm + 75 4B X X I2 C 76 4C X X - b 77 4D X X 1Implode_END u © s NXP Semiconductors N.V. 2014. A 7788889012 44555EF012 X X X X X X X X X X X X X X X X X X X X 2Implode_START 100 mA 40 V LE PCA9 18 of 48 ll rights reserved. 8834 5534 X XX XX X 2Implode_END D driver 626

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P Table 12. CHASE sequence …continued N rodu CA9626 X = enabled; empty cell = disabled. XP ct d Command Hex LED channel Description S ata 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 em sh 85 55 X X X X X X 3Implode_START ic e e o t 86 56 X X X X X X n d 87 57 X X X X X X u c 88 58 X X X X X X t o r 89 59 X X X X s 90 5A X X 3Implode_END 91 5B X X X X X X X X 4Implode_START 92 5C X X X X X X X X A ll inform 93 5D X X X X X X X X Rev. 5 — 19 June 2014 ation provided in this document is subject to legal disclaimers. 999999111100004567890123 66665566664567EF0123 XXXXXXXX XXXXXXX XXXXXX XXXXX XXXX XXX XX X X XX XX X 4LeftI mtop Rloidgeh_t_EWNIDPE_START 24-bit Fm + 104 68 X X X X X X X X X I2 C 105 69 X X X X X X X X X X - b 106 6A X X X X X X X X X X X u © s NXP Semiconductors N.V. 2014. A 111111100010789 66666BCDFE XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXX XXX XX X 100 mA 40 V LE PCA9 19 of 48 ll rights reserved. 111123 7701 XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX X D driver 626

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P Table 12. CHASE sequence …continued N rodu CA9626 X = enabled; empty cell = disabled. XP ct d Command Hex LED channel Description S ata 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 em sh 114 72 X X X X X X X X X X X X X X X X X X X ic e e o t 115 73 X X X X X X X X X X X X X X X X X X X X n d 116 74 X X X X X X X X X X X X X X X X X X X X X u c 117 75 X X X X X X X X X X X X X X X X X X X X X X t o r 118 76 X X X X X X X X X X X X X X X X X X X X X X X s 119 77 X X X X X X X X X X X X X X X X X X X X X X X X Left to Right_WIPE_END 120 78 X Right to Left_WIPE_START 121 79 X X A ll inform 122 7A X X X Rev. 5 — 19 June 2014 ation provided in this document is subject to legal disclaimers. 111111111123332222223456789012 88887777781234BCDEF0 X XX XXX XXXX XXXXX XXXXXX XXXXXXX XXXXXXXX XXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX 24-bit Fm + 133 85 X X X X X X X X X X X X X X I2 C 134 86 X X X X X X X X X X X X X X X - b 135 87 X X X X X X X X X X X X X X X X u © s NXP Semiconductors N.V. 2014. A 111113333467890 8888889ABC X XX XXX XXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX 100 mA 40 V LE PCA9 20 of 48 ll rights reserved. 141 8D X X X X X X X X X X X X X X X X X X X X X X D driver 626

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P Table 12. CHASE sequence …continued N rodu CA9626 X = enabled; empty cell = disabled. XP ct d Command Hex LED channel Description S ata 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 em sh 142 8E X X X X X X X X X X X X X X X X X X X X X X X ic e e o t 143 8F X X X X X X X X X X X X X X X X X X X X X X X X Right to Left_WIPE_END n d 144 90 All LED outputs disabled for u c CHASE byte = 90h to FFh. t o Reserved for future use. r CHASE byte = FFh is used s to exit the CHASE mode.[1] [1] When the PCA9626 exits from the CHASE mode, the previous states of the LED outputs are retained. A ll inform Rev. 5 — 19 June 2014 ation provided in this document is subject to legal disclaimers. 24-bit Fm + I2 C - b u © s NX 1 P Semiconductors N.V. 2014. A 00 mA 40 V LE PCA9 21 of 48 ll rights reserved. D driver 626

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.3.7 LEDOUT0 to LEDOUT5, LED driver output state Table 13. LEDOUT0 to LEDOUT5 - LED driver output state register (address 1Dh to 22h) bitdescription Legend: * default value. Address Register Bit Symbol Access Value Description 1Dh LEDOUT0 7:6 LDR3 R/W 00* LED3 output state control 5:4 LDR2 R/W 00* LED2 output state control 3:2 LDR1 R/W 00* LED1 output state control 1:0 LDR0 R/W 00* LED0 output state control 1Eh LEDOUT1 7:6 LDR7 R/W 00* LED7 output state control 5:4 LDR6 R/W 00* LED6 output state control 3:2 LDR5 R/W 00* LED5 output state control 1:0 LDR4 R/W 00* LED4 output state control 1Fh LEDOUT2 7:6 LDR11 R/W 00* LED11 output state control 5:4 LDR10 R/W 00* LED10 output state control 3:2 LDR9 R/W 00* LED9 output state control 1:0 LDR8 R/W 00* LED8 output state control 20h LEDOUT3 7:6 LDR15 R/W 00* LED15 output state control 5:4 LDR14 R/W 00* LED14 output state control 3:2 LDR13 R/W 00* LED13 output state control 1:0 LDR12 R/W 00* LED12 output state control 21h LEDOUT4 7:6 LDR19 R/W 00* LED19 output state control 5:4 LDR18 R/W 00* LED18 output state control 3:2 LDR17 R/W 00* LED17 output state control 1:0 LDR16 R/W 00* LED16 output state control 22h LEDOUT5 7:6 LDR23 R/W 00* LED23 output state control 5:4 LDR22 R/W 00* LED22 output state control 3:2 LDR21 R/W 00* LED21 output state control 1:0 LDR20 R/W 00* LED20 output state control LDRx=00 — LED driver x is off (default power-up state). LDRx=01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). LDRx=10 — LED driver x individual brightness can be controlled through its PWMx register. LDRx=11 — LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 22 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.3.8 SUBADR1 to SUBADR3, I2C-bus subaddress 1 to 3 Table 14. SUBADR1toSUBADR3 - I2C-bus subaddress registers 0to3 (address 23h to 25h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 23h SUBADR1 7:1 A1[7:1] R/W 1110001* I2C-bus subaddress 1 0 A1[0] R only 0* reserved 24h SUBADR2 7:1 A2[7:1] R/W 1110010* I2C-bus subaddress 2 0 A2[0] R only 0* reserved 25h SUBADR3 7:1 A3[7:1] R/W 1110100* I2C-bus subaddress 3 0 A3[0] R only 0* reserved Subaddresses are programmable through the I2C-bus. Default power-up values are E2h, E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0). Once subaddresses have been programmed to their right values, SUBx bits must be set to logic1 in order to have the device acknowledging these addresses (MODE1 register). Only the 7MSBs representing the I2C-bus subaddress are valid. The LSB in SUBADRx register is a read-only bit (0). When SUBx is set to logic1, the corresponding I2C-bus subaddress can be used during either an I2C-bus read or write sequence. 7.3.9 ALLCALLADR, LED All Call I2C-bus address Table 15. ALLCALLADR - LED All Call I2C-bus address register (address 26h) bit description Legend: * default value. Address Register Bit Symbol Access Value Description 26h ALLCALLADR 7:1 AC[7:1] R/W 1110000* ALLCALL I2C-bus address register 0 AC[0] R only 0* reserved The LED All Call I2C-bus address allows all the PCA9626s on the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to logic1 (power-up default state)). This address is programmable through the I2C-bus and can be used during either an I2C-bus read or write sequence. The register address can also be programmed as a SubCall. Only the 7MSBs representing the All Call I2C-bus address are valid. The LSB in ALLCALLADR register is a read-only bit (0). If ALLCALL bit=0, the device does not acknowledge the address programmed in register ALLCALLADR. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 23 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.4 Active LOW output enable input The activeLOW output enable (OE) pin, allows enabling or disabling all the LED outputs at the same time. • When a LOW level is applied to OE pin, all the LED outputs are enabled as defined by the CHASE register. • When a HIGH level is applied to OE pin, all the LED outputs are high-impedance. The OE pin can be used as a synchronization signal to switch on/off several PCA9626 devices at the same time. This requires an external clock reference that provides blinking period and the duty cycle. The OE pin can also be used as an external dimming control signal. The frequency of the external clock must be high enough not to be seen by the human eye, and the duty cycle value determines the brightness of the LEDs. Remark: Do not use OE as an external blinking control signal when internal global blinking is selected (DMBLNK=1, MODE2 register) since it results in an undefined blinking pattern. Do not use OE as an external dimming control signal when internal global dimming is selected (DMBLNK=0, MODE2 register) since it results in an undefined dimming pattern. Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs using HIGH level applied to OE pin. 7.5 Power-on reset When power is applied to V , an internal power-on reset holds the PCA9626 in a reset DD condition until V has reached V . At this point, the reset condition is released and the DD POR PCA9626 registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, V must be lowered below DD 0.2V to reset the device. 7.6 Software reset The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The SWRST Call function is defined as the following: 1. A START command is sent by the I2C-bus master. 2. The reserved SWRST I2C-bus address ‘0000011’ with the R/W bit set to ‘0’ (write) is sent by the I2C-bus master. 3. The PCA9626 device(s) acknowledge(s) after seeing the SWRST Call address ‘00000110’ (06h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to the I2C-bus master. 4. Once the SWRST Call address has been sent and acknowledged, the master sends 2bytes with 2 specific values (SWRST data byte1 and byte2): a. Byte 1=A5h: the PCA9626 acknowledges this value only. If byte1 is not equal to A5h, the PCA9626 does not acknowledge it. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 24 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver b. Byte 2=5Ah: the PCA9626 acknowledges this value only. If byte2 is not equal to 5Ah, then the PCA9626 does not acknowledge it. If more than 2bytes of data are sent, the PCA9626 does not acknowledge any more. 5. Once the right 2bytes (SWRST data byte1 and byte2 only) have been sent and correctly acknowledged, the master sends a STOP command to end the SWRSTCall: the PCA9626 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (t ). BUF The I2C-bus master must interpret a non-acknowledge from the PCA9626 (at any time) as a ‘SWRST Call Abort’. The PCA9626 does not initiate a reset of its registers. This happens only when the format of the SWRST Call sequence is not correct. 7.7 Individual brightness control with group dimming/blinking A 97kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED. On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED outputs): • A lower 190Hz fixed frequency signal with programmable duty cycle (8 bits, 256steps) is used to provide a global brightness control. • A programmable frequency signal from 24Hz to 1⁄ Hz (8 bits, 256 steps) with 10.73 programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control. 508 510 512 1 2 3 4 5 6 7 8 9 10 11 12 507 509 511 1 2 3 4 5 6 7 8 9 10 11 Brightness Control signal (LEDn) N × 40 ns with N = (0 to 255) M × 256 × 2 × 40 ns (PWMx Register) with M = (0 to 255) (GRPPWM Register) 256 × 40 ns = 10.24 μs (97.6 kHz) Group Dimming signal 256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 resulting Brightness + Group Dimming signal 002aab417 Minimum pulse width for LEDn Brightness Control is 40ns. Minimum pulse width for Group Dimming is 20.48s. When M=1 (GRPPWM register value), the resulting LEDn Brightness Control + GroupDimming signal has 2 pulses of the LED Brightness Control signal (pulse width=N40ns, with ‘N’ defined in PWMx register). This resulting Brightness+GroupDimming signal above shows a resulting Control signal with M=4 (8 pulses). Fig 6. Brightness + Group Dimming signals PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 25 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 8. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure7). (cid:54)(cid:39)(cid:36) (cid:54)(cid:38)(cid:47) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:79)(cid:76)(cid:81)(cid:72)(cid:3) (cid:70)(cid:75)(cid:68)(cid:81)(cid:74)(cid:72)(cid:3) (cid:86)(cid:87)(cid:68)(cid:69)(cid:79)(cid:72)(cid:30)(cid:3) (cid:82)(cid:73)(cid:3)(cid:71)(cid:68)(cid:87)(cid:68)(cid:3) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:89)(cid:68)(cid:79)(cid:76)(cid:71) (cid:68)(cid:79)(cid:79)(cid:82)(cid:90)(cid:72)(cid:71) (cid:80)(cid:69)(cid:68)(cid:25)(cid:19)(cid:26) Fig 7. Bit transfer 8.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure8). (cid:54)(cid:39)(cid:36) (cid:54)(cid:38)(cid:47) (cid:54) (cid:51) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55)(cid:3)(cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81) (cid:54)(cid:55)(cid:50)(cid:51)(cid:3)(cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81) (cid:80)(cid:69)(cid:68)(cid:25)(cid:19)(cid:27)(cid:3) Fig 8. Definition of START and STOP conditions 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure9). PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 26 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver (cid:54)(cid:39)(cid:36) (cid:54)(cid:38)(cid:47) (cid:48)(cid:36)(cid:54)(cid:55)(cid:40)(cid:53)(cid:3) (cid:54)(cid:47)(cid:36)(cid:57)(cid:40)(cid:3) (cid:54)(cid:47)(cid:36)(cid:57)(cid:40)(cid:3) (cid:48)(cid:36)(cid:54)(cid:55)(cid:40)(cid:53)(cid:3) (cid:48)(cid:36)(cid:54)(cid:55)(cid:40)(cid:53)(cid:3) (cid:44)(cid:21)(cid:38)(cid:16)(cid:37)(cid:56)(cid:54)(cid:3) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53)(cid:18)(cid:3) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53)(cid:18)(cid:3) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53) (cid:55)(cid:53)(cid:36)(cid:49)(cid:54)(cid:48)(cid:44)(cid:55)(cid:55)(cid:40)(cid:53)(cid:18)(cid:3) (cid:48)(cid:56)(cid:47)(cid:55)(cid:44)(cid:51)(cid:47)(cid:40)(cid:59)(cid:40)(cid:53) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:53)(cid:40)(cid:38)(cid:40)(cid:44)(cid:57)(cid:40)(cid:53) (cid:54)(cid:47)(cid:36)(cid:57)(cid:40) (cid:19)(cid:19)(cid:21)(cid:68)(cid:68)(cid:68)(cid:28)(cid:25)(cid:25) Fig 9. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of 8bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:82)(cid:88)(cid:87)(cid:83)(cid:88)(cid:87)(cid:3) (cid:69)(cid:92)(cid:3)(cid:87)(cid:85)(cid:68)(cid:81)(cid:86)(cid:80)(cid:76)(cid:87)(cid:87)(cid:72)(cid:85) (cid:81)(cid:82)(cid:87)(cid:3)(cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72)(cid:3) (cid:71)(cid:68)(cid:87)(cid:68)(cid:3)(cid:82)(cid:88)(cid:87)(cid:83)(cid:88)(cid:87)(cid:3) (cid:69)(cid:92)(cid:3)(cid:85)(cid:72)(cid:70)(cid:72)(cid:76)(cid:89)(cid:72)(cid:85) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:54)(cid:38)(cid:47)(cid:3)(cid:73)(cid:85)(cid:82)(cid:80)(cid:3)(cid:80)(cid:68)(cid:86)(cid:87)(cid:72)(cid:85) (cid:20) (cid:21) (cid:27) (cid:28) (cid:54) (cid:70)(cid:79)(cid:82)(cid:70)(cid:78)(cid:3)(cid:83)(cid:88)(cid:79)(cid:86)(cid:72)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3) (cid:54)(cid:55)(cid:36)(cid:53)(cid:55)(cid:3) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72)(cid:80)(cid:72)(cid:81)(cid:87) (cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81) (cid:19)(cid:19)(cid:21)(cid:68)(cid:68)(cid:68)(cid:28)(cid:27)(cid:26) Fig 10. Acknowledgement on the I2C-bus PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 27 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 9. Bus transactions slave address control register data for register D[5:0](1) S A6 A5 A4 A3 A2 A1 A0 0 A X X D5 D4 D3 D2 D1 D0 A A P START condition R/W Auto-Increment flag acknowledge acknowledge from slave from slave acknowledge from slave STOP condition 002aad612 (1) See Table5 for register definition. Fig 11. Write to a specific register slave address control register MODE1 register MODE2 register S A6 A5 A4 A3 A2 A1 A0 0 A 1 X 0 0 0 0 0 0 A A A (cont.) MODE1 START condition R/W register selection acknowledge acknowledge acknowledge from slave from slave from slave acknowledge Auto-Increment on from slave SUBADR3 register ALLCALLADR register (cont.) A A P acknowledge acknowledge from slave from slave STOP condition 002aad613 Fig 12. Write to all registers using the Auto-Increment feature PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 28 of 48

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P P N rodu CA9626 XP ct d S a e ta m sh ic e e o t n d u c t o r s slave address control register PWM0 register data PWM1 register data All inform S A6 A5 A4 A3 A2 A1 A0 0 A 1 X 0 0 0 0 1 0 A A A (cont.) Rev. 5 — 19 June 2014 ation provided in this document is subject to legal disclaimers. (cSoTnAt.)RT coPnWditMio2n2 registeaar ccdkkffarnrnotooaommwwR lls/eseWlldadagvgvAeeee AuPtoW-InMc2re3m rreeeggniists totPeenaWrr c sdMkfearnlo0teoamcrwet ilgsoelindasgtveAeer roaflrlcookmvneP osrWwlalMveed0g reegistera cdkafrnatoaocmkwfrn loseomldawgv lsAeeeldagvee PWM22 regisatecakrf crndokfoarmnwotoa mlswel dalsegvldaeegvAee PWM23 registearc dkfarnotoamw lsecl0oda0ngvS2AdeeaTiatOido6PPn14 24-bit Fm + I2 C - b u © s NX 1 P Semiconductors N.V. 2014. A 00 mA 40 V LE PCA9 29 of 48 ll rights reserved. Fig 13. MThuisl teipxalem wpleri taesssu tmoe Isn dthiavti dAIuFa+l BAIr[i1g:0h]t=ne1s01sb r.egisters only using the Auto-Increment feature D driver 626

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver ReSTART slave address control register condition slave address data from MODE1 register S A6 A5 A4 A3 A2 A1 A0 0 A 1 X 0 0 0 0 0 0 A Sr A6 A5 A4 A3 A2 A1 A0 1 A A (cont.) MODE1 START condition R/W register selection acknowledge R/W acknowledge from slave from master acknowledge Auto-Increment on acknowledge from slave from slave data from data from data from MODE2 register data from PWM0 ALLCALLADR register MODE1 register (cont.) A A A A (cont.) acknowledge acknowledge acknowledge acknowledge from master from master from master from master data from last read byte (cont.) A P not acknowledge STOP from master condition 002aad615 This example assumes that MODE1[5]=0 and MODE1[6]=0. Fig 14. Read all registers using the Auto-Increment feature slave address(1) control register new LED All Call I2C address(2) sequence (A) S A6 A5 A4 A3 A2 A1 A0 0 A 1 X 1 0 0 1 1 0 A 1 0 1 0 1 0 1 X A P ALLCALLADR START condition R/W register selection acknowledge acknowledge from slave from slave acknowledge from slave Auto-Increment on STOP condition the 16 LEDs are on at the acknowledge(3) LED All Call I2C address control register LEDOUT register (LED fully ON) sequence (B) S 1 0 1 0 1 0 1 0 A X X X 0 1 0 0 0 A 0 1 0 1 0 1 0 1 A P LEDOUT START condition R/W register selection acknowledge acknowledge from the from the acknowledge 4 devices 4 devices from the 4 devices STOP condition 002aad616 (1) In this example, several PCA9626s are used and the same sequence (A) (above) is sent to each of them. (2) ALLCALL bit in MODE1 register is previously set to 1 for this example. (3) OCH bit in MODE2 register is previously set to 1 for this example. Fig 15. LED All Call I2C-bus address programming and LED All Call sequence example PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 30 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 10. Application design-in information up to 40 V VDD = 2.5 V, 3.3 V or 5.0 V 10 kΩ 10 kΩ 10 kΩ(1) I2C-BUS/SMBus MASTER VDD SDA SDA LED0 SCL SCL LED1 LED2 OE OE LED3 PCA9626 LED light bar up to 40 V LED4 LED5 LED6 LED7 LED light bar uupp ttoo 4400 VV LED8 LED9 LED10 LED11 LED light bar up to 40 V LED12 LED13 LED14 LED15 LED light bar up to 40 V LED16 LED17 LED18 A0 LED19 A1 A2 LED light bar up to 40 V A3 LED20 A4 LED21 A5 LED22 A6 VSS LED23 VSS 002aad607 (1) OE requires pull-up resistor if control signal from the master is open-drain. I2C-bus address = 0010101x. Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs using HIGH level applied to OE pin. Fig 16. Typical application PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 31 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 10.1 Junction temperature calculation A device junction temperature can be calculated when the ambient temperature or the case temperature is known. When the ambient temperature is known, the junction temperature is calculated using Equation4 and the ambient temperature, junction to ambient thermal resistance and power dissipation. T = T +R P (4) j amb thj-a tot where: T = junction temperature j T = ambient temperature amb R = junction to ambient thermal resistance th(j-a) P = (device) total power dissipation tot When the case temperature is known, the junction temperature is calculated using Equation5 and the case temperature, junction to case thermal resistance and power dissipation. T = T +R P (5) j case thj-c tot where: T = junction temperature j T = case temperature case R = junction to case thermal resistance th(j-c) P = (device) total power dissipation tot Here are two examples regarding how to calculate the junction temperature using junction to case and junction to ambient thermal resistance. In the first example (Section10.1.1), given the operating condition and the junction to ambient thermal resistance, the junction temperature of PCA9626B, in the LQFP48 package, is calculated for a system operating condition in 50C1 ambient temperature. In the second example (Section10.1.2), based on a specific customer application requirement where only the case temperature is known, applying the junction to case thermal resistance equation, the junction temperature of the PCA9626B, in the LQFP48 package, is calculated. 1. 50C is a typical temperature inside an enclosed system. The designers should feel free, as needed, to perform their own calculation using the examples. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 32 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 10.1.1 Example 1: T calculation when T is known (PCA9626B, LQFP48) j amb R = 63C/W th(j-a) T = 50C amb LED output low voltage (LED V ) = 0.5V OL LED output current per channel = 80mA Number of outputs = 24 I = 18mA DD(max) V = 5.5V DD(max) I2C-bus clock (SCL) maximum sink current = 25mA I2C-bus data (SDA) maximum sink current = 25mA 1. Find P (device total power dissipation): tot – output total power = 80mA240.5V = 960mW – chip core power consumption = 18mA5.5V = 99mW – SCL power dissipation = 25mA 0.4V = 10mW – SDA power dissipation = 25mA 0.4V = 10mW P = (960+99+10+10)mW = 1079mW tot 2. Find T (junction temperature): j T = (T +R P ) = (50C + 63C/W1079mW) = 118C j amb th(j-a) tot 10.1.2 Example 2: T calculation where only T is known j case This example uses a customer-specific application of the PCA9626B, 24-channel LED controller in the LQFP48 package, where only the case temperature (T ) is known. case T = T + R P , where: j case th(j-c) tot R = 18C/W th(j-c) T (measured) = 94.6C case V of LED ~ 0.5V OL I = 18mA DD(max) V = 5.5V DD(max) LED output voltage LOW = 0.5V LED output current: 60mA on 1 port = (60mA1) 50mA on 6 ports = (50mA6) 40mA on 2 ports = (40mA2) 20mA on 12 ports = (20mA12) 1mA on 3 ports = (1mA3) I2C-bus maximum sink current on clock line = 25mA I2C-bus maximum sink current on data line = 25mA PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 33 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 1. Find P (device total power dissipation) tot – output current (60mA1port); output power (60mA10.5V) = 30mW – output current (50mA6ports); output power (50mA60.5V) = 150mW – output current (40mA2ports); output power (40mA20.5V) = 40mW – output current (20mA12ports); output power (20mA120.5V) = 120mW – output current (1mA3ports); output power (1mA30.5V) = 1.5mW Output total power = 341.5mW – chip core power consumption = 18mA5.5V = 99mW – SCL power dissipation = 25mA0.4V = 10mW – SDA power dissipation = 25mA0.4V = 10mW P (device total power dissipation) = 460.5mW tot 2. Find T (junction temperature): j T = T + R  P = 94.6C + 18C/W  460.5mW = 102.9C j case th(j-a) tot 11. Limiting values Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +6.0 V DD V voltage on an input/output pin V 0.5 5.5 V I/O SS V LED driver voltage V 0.5 40 V drv(LED) SS I output current on pin LEDn - 100 mA O(LEDn) I total LOW-level output current LED driver outputs; [1] 2400 - mA OL(tot) V =0.5V OL I ground supply current per V pin - 800 mA SS SS P total power dissipation T =25C - 1.8 W tot amb T =85C - 0.72 W amb P/ch power dissipation per channel T =25C - 100 mW amb T =85C - 45 mW amb T junction temperature [2] - +125 C j T storage temperature 65 +150 C stg T ambient temperature operating 40 +85 C amb [1] Each bit must be limited to a maximum of 100mA and the total package limited to 2400mA due to internal busing limits. [2] Refer to Section10.1 for calculation. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 34 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver Table 17. LQFP48 power dissipation and output current capability Measurement LQFP48 T = 25C amb maximum power dissipation (chip+output drivers) 1590mW maximum power dissipation (outputdrivers only) 1460mW maximum drive current perchannel 1460 mW ----------------------------------- = 121.7 mA[1] 24-bit0.5 V T = 60C amb maximum power dissipation (chip+output drivers) 1030mW maximum power dissipation (outputdrivers only) 901mW maximum drive current perchannel 901 mW ----------------------------------- = 75.1 mA 24-bit0.5 V T = 80C amb maximum power dissipation (chip+output drivers) 714mW maximum power dissipation (outputdrivers only) 585mW maximum drive current perchannel 585 mW ----------------------------------- = 48.8 mA 24-bit0.5 V [1] This value signifies package ability to handle more than 100mA per output driver. The device maximum current rating per output is 100mA. 12. Thermal characteristics Table 18. Thermal characteristics Symbol Parameter Conditions Typ Unit R thermal resistance from junction to ambient LQFP48 [1] 63 C/W th(j-a) R thermal resistance from junction to case LQFP48 [1] 18 C/W th(j-c) [1] Calculated in accordance with JESD51-7. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 35 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 13. Static characteristics Table 19. Static charac teristics V =2.3V to 5.5V; V =0V; T =40Cto+85C; unless otherwise specified. DD SS amb Symbol Parameter Conditions Min Typ Max Unit Supply V supply voltage 2.3 - 5.5 V DD I supply current on pin V ; operatingmode; DD DD noload; f =1MHz SCL V =2.7V - 0.5 4 mA DD V =3.6V - 1.5 6 mA DD V =5.5V - 13 18 mA DD I standby current on pin V ; stb DD noload;f =0Hz; SCL I/O=inputs; V =V I DD V =2.7V - 0.5 5 A DD V =3.6V - 1.0 10 A DD V =5.5V - 6 15 A DD V power-on reset voltage no load; V =V or V [1] - 1.70 2.0 V POR I DD SS Input SCL; input/output SDA V LOW-level input voltage 0.5 - +0.3V V IL DD V HIGH-level input voltage 0.7V - 5.5 V IH DD I LOW-level output current V =0.4V; V =2.3V 20 - - mA OL OL DD V =0.4V; V =5.0V 30 - - mA OL DD I leakage current V =V or V 1 - +1 A L I DD SS C input capacitance V =V - 6 10 pF i I SS LED driver outputs V LED driver voltage 0 - 40 V drv(LED) I LOW-level output current V =0.5V; V 4.5V [2] 100 - - mA OL OL DD I HIGH-level output leakage V =5V - - 1 A LOH drv(LED) current V =40V - 1 15 A drv(LED) R ON-state resistance V =40V; V =2.3V - 2 5  on drv(LED) DD C output capacitance - 15 40 pF o OE input V LOW-level input voltage 0.5 - +0.8 V IL V HIGH-level input voltage 0.7V - 5.5 V IH DD I input leakage current 1 - +1 A LI C input capacitance - 3.7 5 pF i Address inputs V LOW-level input voltage 0.5 - +0.3V V IL DD V HIGH-level input voltage 0.7V - 5.5 V IH DD I input leakage current 1 - +1 A LI C input capacitance - 3.7 5 pF i [1] V must be lowered to 0.2V in order to reset part. DD PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 36 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver [2] Each bit must be limited to a maximum of 100mA and the total package limited to 2400mA due to internal busing limits. 14. Dynamic characteristics Table 20. Dynamic cha racteristics Symbol Parameter Conditions Standard-mode Fast-mode Fast-mode Unit I2C-bus I2C-bus Plus I2C-bus Min Max Min Max Min Max f SCL clock frequency 0 100 0 400 0 1000 kHz SCL t bus free time 4.7 - 1.3 - 0.5 - s BUF between a STOP and START condition t hold time (repeated) 4.0 - 0.6 - 0.26 - s HD;STA START condition t set-up time for a 4.7 - 0.6 - 0.26 - s SU;STA repeated START condition t set-up time for STOP 4.0 - 0.6 - 0.26 - s SU;STO condition t data hold time 0 - 0 - 0 - ns HD;DAT t data valid [1] 0.3 3.45 0.1 0.9 0.05 0.45 s VD;ACK acknowledge time t data valid time [2] 0.3 3.45 0.1 0.9 0.05 0.45 s VD;DAT t data set-up time 250 - 100 - 50 - ns SU;DAT t LOW period of the 4.7 - 1.3 - 0.5 - s LOW SCL clock t HIGH period of the 4.0 - 0.6 - 0.26 - s HIGH SCL clock t fall time of both SDA [3][4] - 300 20+0.1C [5] 300 - 120 ns f b and SCL signals t rise time of both SDA - 1000 20+0.1C [5] 300 - 120 ns r b and SCL signals t pulse width of spikes [6] - 50 - 50 - 50 ns SP that must be suppressed by the input filter Output propagation delay t LOW to HIGH OE to LEDn; - - - - - 150 ns PLH propagation delay MODE2[1:0]=01 t HIGH to LOW OE to LEDn; - - - - - 150 ns PHL propagation delay MODE2[1:0]=01 PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 37 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver Table 20. Dynamic characteristics …continued Symbol Parameter Conditions Standard-mode Fast-mode Fast-mode Unit I2C-bus I2C-bus Plus I2C-bus Min Max Min Max Min Max Output port timing t delay time from SCL SCL to LEDn; - - - - - 450 ns d(SCL-Q) todata output MODE2[3]=1; outputs change on ACK t delay time from SDA SDA to LEDn; - - - - - 450 ns d(SDA-Q) todata output MODE2[3]=0; outputs change on STOP condition [1] t =time for Acknowledgement signal from SCL LOW to SDA (out) LOW. VD;ACK [2] t =minimum time for SDA data out to be valid following SCL LOW. VD;DAT [3] A master device must internally provide a hold time of at least 300ns for the SDA signal (refer to the V of the SCL signal) in order to IL bridge the undefined region of SCL’s falling edge. [4] The maximum tf for the SDA and SCL bus lines is specified at 300ns. The maximum fall time (tf) for the SDA output stage is specified at 250ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [5] C =total capacitance of one bus line in pF. b [6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. (cid:19)(cid:17)(cid:26)(cid:3)(cid:238)(cid:3)(cid:57)(cid:39)(cid:39) (cid:54)(cid:39)(cid:36) (cid:19)(cid:17)(cid:22)(cid:3)(cid:238)(cid:3)(cid:57)(cid:39)(cid:39) (cid:87)(cid:37)(cid:56)(cid:41) (cid:87)(cid:85) (cid:87)(cid:73) (cid:87)(cid:43)(cid:39)(cid:30)(cid:54)(cid:55)(cid:36) (cid:87)(cid:54)(cid:51) (cid:87)(cid:47)(cid:50)(cid:58) (cid:19)(cid:17)(cid:26)(cid:3)(cid:238)(cid:3)(cid:57)(cid:39)(cid:39) (cid:54)(cid:38)(cid:47) (cid:19)(cid:17)(cid:22)(cid:3)(cid:238)(cid:3)(cid:57)(cid:39)(cid:39) (cid:87)(cid:43)(cid:39)(cid:30)(cid:54)(cid:55)(cid:36) (cid:87)(cid:54)(cid:56)(cid:30)(cid:54)(cid:55)(cid:36) (cid:87)(cid:54)(cid:56)(cid:30)(cid:54)(cid:55)(cid:50) (cid:51) (cid:54) (cid:87)(cid:43)(cid:39)(cid:30)(cid:39)(cid:36)(cid:55) (cid:87)(cid:43)(cid:44)(cid:42)(cid:43) (cid:87)(cid:54)(cid:56)(cid:30)(cid:39)(cid:36)(cid:55) (cid:54)(cid:85) (cid:51) (cid:19)(cid:19)(cid:21)(cid:68)(cid:68)(cid:68)(cid:28)(cid:27)(cid:25) Fig 17. Definition of timing PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 38 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver (cid:54)(cid:55)(cid:36)(cid:53)(cid:55) (cid:69)(cid:76)(cid:87)(cid:3)(cid:26) (cid:54)(cid:55)(cid:50)(cid:51) (cid:69)(cid:76)(cid:87)(cid:3)(cid:25) (cid:69)(cid:76)(cid:87)(cid:3)(cid:20) (cid:69)(cid:76)(cid:87)(cid:3)(cid:19) (cid:68)(cid:70)(cid:78)(cid:81)(cid:82)(cid:90)(cid:79)(cid:72)(cid:71)(cid:74)(cid:72) (cid:83)(cid:85)(cid:82)(cid:87)(cid:82)(cid:70)(cid:82)(cid:79) (cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81) (cid:48)(cid:54)(cid:37) (cid:70)(cid:82)(cid:81)(cid:71)(cid:76)(cid:87)(cid:76)(cid:82)(cid:81) (cid:11)(cid:36)(cid:25)(cid:12) (cid:11)(cid:39)(cid:20)(cid:12) (cid:11)(cid:39)(cid:19)(cid:12) (cid:11)(cid:36)(cid:12) (cid:11)(cid:54)(cid:12) (cid:11)(cid:36)(cid:26)(cid:12) (cid:11)(cid:51)(cid:12) (cid:87)(cid:54)(cid:56)(cid:30)(cid:54)(cid:55)(cid:36) (cid:87)(cid:47)(cid:50)(cid:58) (cid:87)(cid:43)(cid:44)(cid:42)(cid:43) (cid:20)(cid:3)(cid:18)(cid:3)(cid:73)(cid:54)(cid:38)(cid:47) (cid:54)(cid:38)(cid:47) (cid:19)(cid:17)(cid:26)(cid:3)(cid:238)(cid:3)(cid:57)(cid:39)(cid:39) (cid:19)(cid:17)(cid:22)(cid:3)(cid:238)(cid:3)(cid:57)(cid:39)(cid:39) (cid:87)(cid:37)(cid:56)(cid:41) (cid:87)(cid:73) (cid:87)(cid:85) (cid:54)(cid:39)(cid:36) (cid:19)(cid:17)(cid:26)(cid:3)(cid:238)(cid:3)(cid:57)(cid:39)(cid:39) (cid:19)(cid:17)(cid:22)(cid:3)(cid:238)(cid:3)(cid:57)(cid:39)(cid:39) (cid:87)(cid:43)(cid:39)(cid:30)(cid:54)(cid:55)(cid:36) (cid:87)(cid:54)(cid:56)(cid:30)(cid:39)(cid:36)(cid:55) (cid:87)(cid:43)(cid:39)(cid:30)(cid:39)(cid:36)(cid:55) (cid:87)(cid:57)(cid:39)(cid:30)(cid:39)(cid:36)(cid:55) (cid:87)(cid:57)(cid:39)(cid:30)(cid:36)(cid:38)(cid:46) (cid:87)(cid:54)(cid:56)(cid:30)(cid:54)(cid:55)(cid:50) (cid:19)(cid:19)(cid:21)(cid:68)(cid:68)(cid:69)(cid:21)(cid:27)(cid:24) Rise and fall times refer to V and V . IL IH Fig 18. I2C-bus timing diagram 15. Test information VDD open GND VDD RL 500 Ω VI VO PULSE DUT GENERATOR RT C50L pF 002aab284 RL = Load resistor for LEDn. RL for SDA and SCL > 1k (3mA or less current). CL = Load capacitance includes jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 19. Test circuitry for switching times PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 39 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 16. Package outline (cid:47)(cid:52)(cid:41)(cid:51)(cid:23)(cid:27)(cid:29)(cid:3)(cid:83)(cid:79)(cid:68)(cid:86)(cid:87)(cid:76)(cid:70)(cid:3)(cid:79)(cid:82)(cid:90)(cid:3)(cid:83)(cid:85)(cid:82)(cid:73)(cid:76)(cid:79)(cid:72)(cid:3)(cid:84)(cid:88)(cid:68)(cid:71)(cid:3)(cid:73)(cid:79)(cid:68)(cid:87)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:30)(cid:3)(cid:23)(cid:27)(cid:3)(cid:79)(cid:72)(cid:68)(cid:71)(cid:86)(cid:30)(cid:3)(cid:69)(cid:82)(cid:71)(cid:92)(cid:3)(cid:26)(cid:3)(cid:91)(cid:3)(cid:26)(cid:3)(cid:91)(cid:3)(cid:20)(cid:17)(cid:23)(cid:3)(cid:80)(cid:80)(cid:3) (cid:54)(cid:50)(cid:55)(cid:22)(cid:20)(cid:22)(cid:16)(cid:21)(cid:3) (cid:70)(cid:3) (cid:92)(cid:3) (cid:59)(cid:3) (cid:22)(cid:25)(cid:3) (cid:21)(cid:24)(cid:3) (cid:36)(cid:3) (cid:22)(cid:26)(cid:3) (cid:21)(cid:23)(cid:3) (cid:61)(cid:3)(cid:40)(cid:3) (cid:72)(cid:3) (cid:40)(cid:3) (cid:43)(cid:3)(cid:40)(cid:3) (cid:36)(cid:3) (cid:36)(cid:3)(cid:21)(cid:3)(cid:36)(cid:3)(cid:20)(cid:3) (cid:11)(cid:36)(cid:3)(cid:22)(cid:3)(cid:3)(cid:12)(cid:3) (cid:90)(cid:3)(cid:48)(cid:3) (cid:537)(cid:3) (cid:83)(cid:76)(cid:81)(cid:3)(cid:20)(cid:3)(cid:76)(cid:81)(cid:71)(cid:72)(cid:91)(cid:3) (cid:69)(cid:3)(cid:83)(cid:3) (cid:47)(cid:3)(cid:83)(cid:3) (cid:23)(cid:27)(cid:3)(cid:3) (cid:20)(cid:22)(cid:3) (cid:47)(cid:3) (cid:71)(cid:72)(cid:87)(cid:68)(cid:76)(cid:79)(cid:3)(cid:59)(cid:3) (cid:20)(cid:3) (cid:20)(cid:21)(cid:3) (cid:61)(cid:3)(cid:39)(cid:3) (cid:89)(cid:3)(cid:48)(cid:3) (cid:36)(cid:3) (cid:72)(cid:3) (cid:90)(cid:3)(cid:48)(cid:3) (cid:69)(cid:3)(cid:83)(cid:3) (cid:39)(cid:3) (cid:37)(cid:3) (cid:43)(cid:3)(cid:39)(cid:3) (cid:89)(cid:3)(cid:48)(cid:3) (cid:37)(cid:3) (cid:19)(cid:3) (cid:21)(cid:17)(cid:24)(cid:3) (cid:24)(cid:3)(cid:80)(cid:80)(cid:3) (cid:86)(cid:70)(cid:68)(cid:79)(cid:72)(cid:3) (cid:39)(cid:44)(cid:48)(cid:40)(cid:49)(cid:54)(cid:44)(cid:50)(cid:49)(cid:54)(cid:3)(cid:11)(cid:80)(cid:80)(cid:3)(cid:68)(cid:85)(cid:72)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:82)(cid:85)(cid:76)(cid:74)(cid:76)(cid:81)(cid:68)(cid:79)(cid:3)(cid:71)(cid:76)(cid:80)(cid:72)(cid:81)(cid:86)(cid:76)(cid:82)(cid:81)(cid:86)(cid:12)(cid:3) (cid:36)(cid:3) (cid:56)(cid:49)(cid:44)(cid:55)(cid:3) (cid:80)(cid:68)(cid:91)(cid:17)(cid:3) (cid:36)(cid:3)(cid:20)(cid:3) (cid:36)(cid:3)(cid:21)(cid:3) (cid:36)(cid:3)(cid:22)(cid:3) (cid:69)(cid:3)(cid:83)(cid:3) (cid:70)(cid:3) (cid:39)(cid:3)(cid:11)(cid:20)(cid:12)(cid:3) (cid:40)(cid:3)(cid:11)(cid:20)(cid:12)(cid:3) (cid:72)(cid:3) (cid:43)(cid:39)(cid:3)(cid:3) (cid:43)(cid:40)(cid:3)(cid:3) (cid:47)(cid:3) (cid:47)(cid:3)(cid:83)(cid:3) (cid:89)(cid:3) (cid:90)(cid:3) (cid:92)(cid:3) (cid:61)(cid:3)(cid:39)(cid:3)(cid:11)(cid:20)(cid:12)(cid:3) (cid:61)(cid:3)(cid:40)(cid:3)(cid:11)(cid:20)(cid:12)(cid:3) (cid:537)(cid:3) (cid:80)(cid:80)(cid:3) (cid:20)(cid:17)(cid:25)(cid:3) (cid:19)(cid:19)(cid:17)(cid:17)(cid:21)(cid:19)(cid:19)(cid:24)(cid:3)(cid:3) (cid:20)(cid:20)(cid:17)(cid:17)(cid:23)(cid:22)(cid:24)(cid:24)(cid:3)(cid:3) (cid:19)(cid:17)(cid:21)(cid:24)(cid:3) (cid:19)(cid:19)(cid:17)(cid:17)(cid:21)(cid:20)(cid:26)(cid:26)(cid:3)(cid:3) (cid:19)(cid:19)(cid:17)(cid:17)(cid:20)(cid:20)(cid:27)(cid:21)(cid:3)(cid:3) (cid:26)(cid:25)(cid:17)(cid:17)(cid:20)(cid:28)(cid:3)(cid:3) (cid:26)(cid:25)(cid:17)(cid:17)(cid:20)(cid:28)(cid:3)(cid:3) (cid:19)(cid:17)(cid:24)(cid:3) (cid:28)(cid:27)(cid:17)(cid:17)(cid:20)(cid:27)(cid:24)(cid:24)(cid:3)(cid:3) (cid:28)(cid:27)(cid:17)(cid:17)(cid:20)(cid:27)(cid:24)(cid:24)(cid:3)(cid:3) (cid:20)(cid:3) (cid:19)(cid:19)(cid:17)(cid:17)(cid:26)(cid:23)(cid:24)(cid:24)(cid:3)(cid:3) (cid:19)(cid:17)(cid:21)(cid:3) (cid:19)(cid:17)(cid:20)(cid:21)(cid:3) (cid:19)(cid:17)(cid:20)(cid:3) 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(cid:3)(cid:53)(cid:40)(cid:41)(cid:40)(cid:53)(cid:40)(cid:49)(cid:38)(cid:40)(cid:54)(cid:3) (cid:40)(cid:56)(cid:53)(cid:50)(cid:51)(cid:40)(cid:36)(cid:49)(cid:3) (cid:44)(cid:54)(cid:54)(cid:56)(cid:40)(cid:3)(cid:39)(cid:36)(cid:55)(cid:40)(cid:3) (cid:57)(cid:40)(cid:53)(cid:54)(cid:44)(cid:50)(cid:49)(cid:3) (cid:3)(cid:44)(cid:40)(cid:38)(cid:3) (cid:3)(cid:45)(cid:40)(cid:39)(cid:40)(cid:38)(cid:3) (cid:3)(cid:45)(cid:40)(cid:44)(cid:55)(cid:36)(cid:3) (cid:51)(cid:53)(cid:50)(cid:45)(cid:40)(cid:38)(cid:55)(cid:44)(cid:50)(cid:49)(cid:3) (cid:19)(cid:19)(cid:16)(cid:19)(cid:20)(cid:16)(cid:20)(cid:28)(cid:3) (cid:3)(cid:54)(cid:50)(cid:55)(cid:22)(cid:20)(cid:22)(cid:16)(cid:21)(cid:3) (cid:20)(cid:22)(cid:25)(cid:40)(cid:19)(cid:24)(cid:3) (cid:48)(cid:54)(cid:16)(cid:19)(cid:21)(cid:25)(cid:3) (cid:19)(cid:22)(cid:16)(cid:19)(cid:21)(cid:16)(cid:21)(cid:24)(cid:3) Fig 20. Package outline SOT313-2 (LQFP48) PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 40 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 41 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure21) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table21 and22 Table 21. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 22. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure21. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 42 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 43 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 19. Soldering: PCB footprints (cid:41)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87)(cid:3)(cid:76)(cid:81)(cid:73)(cid:82)(cid:85)(cid:80)(cid:68)(cid:87)(cid:76)(cid:82)(cid:81)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:85)(cid:72)(cid:73)(cid:79)(cid:82)(cid:90)(cid:3)(cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:76)(cid:81)(cid:74)(cid:3)(cid:82)(cid:73)(cid:3)(cid:47)(cid:52)(cid:41)(cid:51)(cid:23)(cid:27)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72) (cid:54)(cid:50)(cid:55)(cid:22)(cid:20)(cid:22)(cid:16)(cid:21) (cid:43)(cid:91) (cid:42)(cid:91) (cid:51)(cid:21) (cid:51)(cid:20) (cid:11)(cid:19)(cid:17)(cid:20)(cid:21)(cid:24)(cid:12) (cid:43)(cid:92) (cid:42)(cid:92) (cid:37)(cid:92) (cid:36)(cid:92) (cid:38) (cid:39)(cid:21)(cid:3)(cid:11)(cid:27)(cid:238)(cid:12) (cid:39)(cid:20) (cid:37)(cid:91) (cid:36)(cid:91) (cid:42)(cid:72)(cid:81)(cid:72)(cid:85)(cid:76)(cid:70)(cid:3)(cid:73)(cid:82)(cid:82)(cid:87)(cid:83)(cid:85)(cid:76)(cid:81)(cid:87)(cid:3)(cid:83)(cid:68)(cid:87)(cid:87)(cid:72)(cid:85)(cid:81)(cid:3) (cid:53)(cid:72)(cid:73)(cid:72)(cid:85)(cid:3)(cid:87)(cid:82)(cid:3)(cid:87)(cid:75)(cid:72)(cid:3)(cid:83)(cid:68)(cid:70)(cid:78)(cid:68)(cid:74)(cid:72)(cid:3)(cid:82)(cid:88)(cid:87)(cid:79)(cid:76)(cid:81)(cid:72)(cid:3)(cid:71)(cid:85)(cid:68)(cid:90)(cid:76)(cid:81)(cid:74)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:68)(cid:70)(cid:87)(cid:88)(cid:68)(cid:79)(cid:3)(cid:79)(cid:68)(cid:92)(cid:82)(cid:88)(cid:87) (cid:86)(cid:82)(cid:79)(cid:71)(cid:72)(cid:85)(cid:3)(cid:79)(cid:68)(cid:81)(cid:71) (cid:82)(cid:70)(cid:70)(cid:88)(cid:83)(cid:76)(cid:72)(cid:71)(cid:3)(cid:68)(cid:85)(cid:72)(cid:68) (cid:39)(cid:44)(cid:48)(cid:40)(cid:49)(cid:54)(cid:44)(cid:50)(cid:49)(cid:54)(cid:3)(cid:76)(cid:81)(cid:3)(cid:80)(cid:80) (cid:51)(cid:20) (cid:51)(cid:21) (cid:36)(cid:91) (cid:36)(cid:92) (cid:37)(cid:91) (cid:37)(cid:92) (cid:38) (cid:39)(cid:20) (cid:39)(cid:21) (cid:42)(cid:91) (cid:42)(cid:92) (cid:43)(cid:91) (cid:43)(cid:92) (cid:19)(cid:17)(cid:24)(cid:19)(cid:19) (cid:19)(cid:17)(cid:24)(cid:25)(cid:19) (cid:20)(cid:19)(cid:17)(cid:22)(cid:24)(cid:19) (cid:20)(cid:19)(cid:17)(cid:22)(cid:24)(cid:19) (cid:26)(cid:17)(cid:22)(cid:24)(cid:19) (cid:26)(cid:17)(cid:22)(cid:24)(cid:19) (cid:20)(cid:17)(cid:24)(cid:19)(cid:19) (cid:19)(cid:17)(cid:21)(cid:27)(cid:19) (cid:19)(cid:17)(cid:24)(cid:19)(cid:19) (cid:26)(cid:17)(cid:24)(cid:19)(cid:19) (cid:26)(cid:17)(cid:24)(cid:19)(cid:19) (cid:20)(cid:19)(cid:17)(cid:25)(cid:24)(cid:19) (cid:20)(cid:19)(cid:17)(cid:25)(cid:24)(cid:19) (cid:86)(cid:82)(cid:87)(cid:22)(cid:20)(cid:22)(cid:16)(cid:21)(cid:66)(cid:73)(cid:85) Fig 22. PCB footprint for SOT313-2 (LQFP48); reflow soldering PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 44 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 20. Abbreviations Table 23. Abbreviations Acronym Description ACK Acknowledge CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge FET Field-Effect Transistor HBM Human Body Model I2C-bus Inter-Integrated Circuit bus LED Light Emitting Diode LSB Least Significant Bit MM Machine Model MSB Most Significant Bit PCB Printed-Circuit Board PWM Pulse Width Modulation RGB Red/Green/Blue RGBA Red/Green/Blue/Amber SMBus System Management Bus 21. Revision history Table 24. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9626 v.5 20140619 Product data sheet - PCA9626 v.4 Modifications: • Section 7.2 “Control register”, 11th paragraph, last sentence changed from “2021…26012 …190203…1902…” to “1213…190203…1902…” • Table 5 “Register summary[1]”: deleted (old) Table note [2] • Table 6 “MODE1 - Mode register 1 (address 00h) bit description”: added (new) Table note [1] and its cross-reference at SLEEP bit (bit 4) PCA9626 v.4 20140514 Product data sheet - PCA9626 v.3 PCA9626 v.3 20120906 Product data sheet - PCA9626 v.2 PCA9626 v.2 20090831 Product data sheet - PCA9626 v.1 PCA9626 v.1 20090602 Product data sheet - - PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 45 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 22.2 Definitions Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Draft — The document is a draft version only. The content is still under malfunction of an NXP Semiconductors product can reasonably be expected internal review and subject to formal approval, which may result in to result in personal injury, death or severe property or environmental modifications or additions. NXP Semiconductors does not give any damage. NXP Semiconductors and its suppliers accept no liability for representations or warranties as to the accuracy or completeness of inclusion and/or use of NXP Semiconductors products in such equipment or information included herein and shall have no liability for the consequences of applications and therefore such inclusion and/or use is at the customer’s own use of such information. risk. Short data sheet — A short data sheet is an extract from a full data sheet Applications — Applications that are described herein for any of these with the same product type number(s) and title. A short data sheet is intended products are for illustrative purposes only. NXP Semiconductors makes no for quick reference only and should not be relied upon to contain detailed and representation or warranty that such applications will be suitable for the full information. For detailed and full information see the relevant full data specified use without further testing or modification. sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their deemed to offer functions and qualities beyond those described in the applications and products. Product data sheet. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the 22.3 Disclaimers customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Limited warranty and liability — Information in this document is believed to Semiconductors products in order to avoid a default of the applications and be accurate and reliable. However, NXP Semiconductors does not give any the products or of the application or use by customer’s third party representations or warranties, expressed or implied, as to the accuracy or customer(s). NXP does not accept any liability in this respect. completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC60134) will cause permanent source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in In no event shall NXP Semiconductors be liable for any indirect, incidental, the Recommended operating conditions section (if present) or the punitive, special or consequential damages (including - without limitation - lost Characteristics sections of this document is not warranted. Constant or profits, lost savings, business interruption, costs related to the removal or repeated exposure to limiting values will permanently and irreversibly affect replacement of any products or rework charges) whether or not such the quality and reliability of the device. damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the changes to information published in this document, including without purchase of NXP Semiconductors products by customer. limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 46 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver Export control — This document as well as the item(s) described herein own risk, and (c) customer fully indemnifies NXP Semiconductors for any may be subject to export control regulations. Export might require a prior liability, damages or failed product claims resulting from customer design and authorization from competent authorities. use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, Translations — A non-English (translated) version of a document is for the product is not suitable for automotive use. It is neither qualified nor tested reference only. The English version shall prevail in case of any discrepancy in accordance with automotive testing or application requirements. NXP between the translated and English versions. Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 22.4 Trademarks In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks (a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP Semiconductors N.V. NXP Semiconductors’ specifications such use shall be solely at customer’s 23. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 June 2014 47 of 48

PCA9626 NXP Semiconductors 24-bit Fm+ I2C-bus 100 mA 40 V LED driver 24. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 12 Thermal characteristics . . . . . . . . . . . . . . . . . 35 3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 13 Static characteristics . . . . . . . . . . . . . . . . . . . 36 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 14 Dynamic characteristics. . . . . . . . . . . . . . . . . 37 4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3 15 Test information . . . . . . . . . . . . . . . . . . . . . . . 39 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 17 Handling information . . . . . . . . . . . . . . . . . . . 41 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 18 Soldering of SMD packages. . . . . . . . . . . . . . 41 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 18.1 Introduction to soldering. . . . . . . . . . . . . . . . . 41 7 Functional description . . . . . . . . . . . . . . . . . . . 7 18.2 Wave and reflow soldering. . . . . . . . . . . . . . . 41 7.1 Device addresses. . . . . . . . . . . . . . . . . . . . . . . 7 18.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 41 7.1.1 Regular I2C-bus slave address. . . . . . . . . . . . . 7 18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 42 7.1.2 LED All Call I2C-bus address . . . . . . . . . . . . . . 8 19 Soldering: PCB footprints . . . . . . . . . . . . . . . 44 7.1.3 LED Sub Call I2C-bus addresses. . . . . . . . . . . 8 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.1.4 Software Reset I2C-bus address . . . . . . . . . . . 8 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . 45 7.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3 Register definitions. . . . . . . . . . . . . . . . . . . . . 10 22 Legal information . . . . . . . . . . . . . . . . . . . . . . 46 7.3.1 Mode register 1, MODE1 . . . . . . . . . . . . . . . . 12 22.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 46 7.3.2 Mode register 2, MODE2 . . . . . . . . . . . . . . . . 12 22.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3.3 PWM0 to PWM23, individual brightness 22.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 46 control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 22.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.3.4 GRPPWM, group duty cycle control. . . . . . . . 14 23 Contact information . . . . . . . . . . . . . . . . . . . . 47 7.3.5 GRPFREQ, group frequency . . . . . . . . . . . . . 14 24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.3.6 CHASE control. . . . . . . . . . . . . . . . . . . . . . . . 15 7.3.7 LEDOUT0 to LEDOUT5, LED driver output state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3.8 SUBADR1 to SUBADR3, I2C-bus subaddress1to3. . . . . . . . . . . . . . . . . . . . . . 23 7.3.9 ALLCALLADR, LED All Call I2C-bus address. 23 7.4 Active LOW output enable input. . . . . . . . . . . 24 7.5 Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 24 7.6 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 24 7.7 Individual brightness control with group dimming/blinking. . . . . . . . . . . . . . . . . . . . . . . 25 8 Characteristics of the I2C-bus . . . . . . . . . . . . 26 8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.1 START and STOP conditions. . . . . . . . . . . . . 26 8.2 System configuration . . . . . . . . . . . . . . . . . . . 26 8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 28 10 Application design-in information . . . . . . . . . 31 10.1 Junction temperature calculation . . . . . . . . . . 32 10.1.1 Example 1: T calculation when T is known j amb (PCA9626B, LQFP48) . . . . . . . . . . . . . . . . . . 33 10.1.2 Example 2: T calculation where only T is j case known. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 June 2014 Document identifier: PCA9626

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: PCA9626B,118 PCA9626BS,518