PCA9574 8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt Rev. 5 — 25 September 2014 Product data sheet 1. General description The PCA9574 is a CMOS device that provides 8bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery powered mobile applications and was developed to enhance the NXP family of I2C-bus I/O expanders. The improvements include lower supply current, lower operating voltage of 1.1V to 3.6V, dual and separate supply rails to allow voltage level translation anywhere between 1.1V and 3.6V, 400kHz clock frequency, and smaller packaging. Any of the eightI/O ports can be configured as an input or output independent of each other and default on start-up to inputs. I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum; for example in battery powered mobile applications and clamshell devices for interfacing to sensors, pushbuttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. PCA9574 has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/Os is required. The core of PCA9574 can operate at a voltage as low as 1.1V while the I/O bank can operate in the range 1.1V to 3.6V. Bus-hold with programmable on-chip pull-up or pull-down feature for I/Os is also provided. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity inversion register (activeHIGH or activeLOW operation). Either a bus-hold function or pull-up/pull-down feature can be selected by programming corresponding registers. The bus-hold provides a valid logic level when the I/O bus is not actively driven. When bus-hold feature is not selected, the I/O ports can be configured to have pull-up or pull-down by programming the pull-up/pull-down configuration register. An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted each time a change occurs on an input port unless that port is masked (default=masked). A ‘GPIO All Call’ command allows programming multiple PCA9574s at the same time even if they have different individual I2C-bus addresses. This allows optimal code programming when more than one device needs to be programmed with the same instruction or if all outputs need to be turned on or off at the same time. The internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the eightI/Os as inputs, sets the registers to their default values and initializes the device state machine. The I/O bank is held in its default state when the logic supply (V ) is off. DD One address select pin allows up to two PCA9574 devices to be connected with two different addresses on the same I2C-bus.

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO The PCA9574 is available in TSSOP16 and HVQFN16 packages and is specified over the 40C to +85C industrial temperature range. 2. Features and benefits  400kHz I2C-bus serial interface  Compliant with I2C-bus Standard-mode (100kHz)  Separate supply rails for core logic and I/O bank provides voltage level shifting  1.1V to 3.6V operation with level shifting feature  Very low standby current: <1A  8 configurable I/O pins that default to inputs at power-up  Outputs: Totempole: 1mA source and 3mA sink Independently programmable 100k pull-up or pull-down for each I/O pin Open-drain activeLOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs  Inputs: Programmable bushold provides valid logic level when inputs are not actively driven Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up Polarity inversion register allows inversion of the polarity of the I/O pins when read  Active LOW reset (RESET) input pin resets device to power-up default state  GPIO All Call address allows programming of more than one device at the same time with the same parameters  2 programmable slave addresses using 1 address pin  40C to +85C operation  ESD protection exceeds 7000V HBM per JESD22-A114 and 1000V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA  Packages offered: TSSOP16 and HVQFN16 3. Applications  Cell phones  Media players  Multi voltage environments  Battery operated mobile gadgets  Motherboards  Servers  RAID systems  Industrial control  Medical equipment  PLCs PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 2 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO  Gaming machines  Instrumentation and test measurement 4. Ordering information Table 1. Ordering info rmation Type number Topside Package marking Name Description Version PCA9574PW PCA9574 TSSOP16 plastic thin shrink small outline package; 16leads; SOT403-1 bodywidth4.4mm PCA9574BS P74 HVQFN16 plastic thermal enhanced very thin quad flat package; SOT758-1 noleads; 16terminals; body330.85mm 4.1 Ordering options Table 2. Ordering opt ions Type number Orderable part Package Packing method Minimum order Temperature range number quantity PCA9574PW PCA9574PW,118 TSSOP16 Reel 13” Q1/T1 2500 T = 40C to +85C amb *standard mark SMD PCA9574BS PCA9574BS,118 HVQFN16 Reel 13” Q1/T1 6000 T = 40C to +85C amb *standard mark SMD 5. Block diagram PCA9574 VDD(IO) P0 A0 P1 8-bit P2 SSDCAL FINILPTUETR I2C-BUS/SMBus OINUPTUPUT/T P3 CONTROL PORTS P4 write pulse P5 read pulse P6 VDD P7 POWER-ON RESET RESET VDD VSS LP INT FILTER 002aad054 Remark: All I/Os are set to inputs at power-up and RESET. Fig 1. Block diagram of PCA9574 PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 3 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO data from output port shift register register data configuration register VDD(IO) data from D Q Q1 shift register FF write D Q configuration CK Q pulse FF P0 to P7 write pulse CK Q2 ESD protection output port diode register input port register VSS D Q input port FF register data read pulse CK INTERRUPT to INT MASK VDD(IO) BUS-HOLD AND 100 kΩ PULL-UP/PULL-DOWN CONTROL polarity inversion register data from D Q polarity shift register inversion FF register data write polarity CK pulse 002aad066 Fig 2. Simplified schematic of the I/Os (P0 to P7) PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 4 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 6. Pinning information 6.1 Pinning PCA9574BS itnedrmexin aarle 1a A0 INT VDD SDA 6 5 4 3 1 1 1 1 RESET 1 12 SCL INT 1 16 VDD P0 2 11 P7 A0 2 15 SDA P1 3 10 P6 RESET 3 14 SCL P0 4 13 P7 P2 4 9 P5 PCA9574PW P1 5 12 P6 5 6 7 8 P2 6 11 P5 P3 7 10 P4 P3 VSS D(IO) P4 002aad053 VSS 8 9 VDD(IO) VD 002aad052 Transparent top view Fig 3. Pin configuration for TSSOP16 Fig 4. Pin configuration for HVQFN16 PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 5 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 6.2 Pin description Table 3. Pin descripti on Symbol Pin Type Description TSSOP16 HVQFN16 INT 1 15 O active LOW interrupt output; activeLOWSMBus alert output A0 2 16 I address input RESET 3 1 I activeLOW reset input P0 4 2 I/O input/output 0 P1 5 3 I/O input/output 1 P2 6 4 I/O input/output 2 P3 7 5 I/O input/output 3 V 8 6[1] ground supply ground SS V 9 7 power supply I/O bank supply voltage DD(IO) P4 10 8 I/O input/output 4 P5 11 9 I/O input/output 5 P6 12 10 I/O input/output 6 P7 13 11 I/O input/output 7 SCL 14 12 I serial clock line SDA 15 13 I/O serial data line V 16 14 power supply supply voltage DD [1] HVQFN16 package die supply ground is connected to both V pin and exposed center pad. V pin must be connected to supply SS SS ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. 7. Functional description 7.1 Device address Following a START condition the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9574 is shown in Figure5. Slave address pin A0 chooses 1 of 2 slave addresses: 40h or 42h. slave address 0 1 0 0 0 0 A0 R/W fixed hardware selectable 002aad055 Fig 5. PCA9574 device address The last bit of the first byte defines the operation to be performed. When set to logic1 a read is selected, while logic0 selects a write operation. PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 6 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.2 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9574, which will be stored in the Command register. AI X X X X D2 D1 D0 Auto-Increment flag register address 002aad056 Reset state = 00h Remark: The Command register does not apply to Software Reset I2C-bus address. Fig 6. Command register The lowest three bits are used as a pointer to determine which register will be accessed. Only a command register code with the three least significant bits equal to the eight allowable values as defined in Table 4 “Register summary” will be acknowledged. Reserved or undefined command codes will not be acknowledged. At power-up, this register defaults to 00h, with the AI bit set to ‘0’, and the lowest 3 bits set to ‘0’. If the Auto-Increment flag is set (AI=1), the three least significant bits of the Command register are automatically incremented after a read or write. This allows the user to program and/or read the eight command registers (listed in Table4) sequentially. It will then rollover to register 00h after the last register is accessed and the selected registers will be overwritten or re-read. If the Auto-Increment flag is cleared (AI=0), the three least significant bits are not incremented after data is read or written, only one register will be repeatedly read or written. 7.3 Register definitions Table 4. Register summary Register D2 D1 D0 Name Type Function number 00h 0 0 0 IN read only Input port register 01h 0 0 1 INVRT read/write Polarity inversion register 02h 0 1 0 BKEN read/write Bus-hold enable register 03h 0 1 1 PUPD read/write Pull-up/pull-down selector register 04h 1 0 0 CFG read/write Port configuration register 05h 1 0 1 OUT read/write Output port register 06h 1 1 0 MSK read/write Interrupt mask register 07h 1 1 1 INTS read only Interrupt status register 7.4 Writing to port registers Data is transmitted to the PCA9574 by sending the device address and setting the least significant bit to logic0 (see Figure5 for device address). The command byte is sent after the address and determines which register will receive the data following the command byte. Each 8-bit register may be updated independently of the other registers. PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 7 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.5 Reading the port registers In order to read data from the PCA9574, the bus master must first send the PCA9574 address with the least significant bit set to a logic0 (see Figure5 for device address). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again but this time, the least significant bit is set to logic1. Data from the register defined by the command byte will then be sent by the PCA9574. Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read using the auto-increment feature. 7.5.1 Register 0 - Input port register This register is read-only. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register will be acknowledged but will have no effect. The default ‘X’ is determined by the externally applied logic level. Table 5. Register 0 - Input port register (address 00h) bit description Bit Symbol Access Value Description 7 I0.7 read only X determined by externally applied logic level 6 I0.6 read only X 5 I0.5 read only X 4 I0.4 read only X 3 I0.3 read only X 2 I0.2 read only X 1 I0.1 read only X 0 I0.0 read only X 7.5.2 Register 1 - Polarity inversion register This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. Table 6. Register 1 - Polarity inversion register (address 01h) bit description Legend: * default value. Bit Symbol Access Value Description 7 N0.7 R/W 0* inverts polarity of Input port register data 6 N0.6 R/W 0* 0 = Input port register data retained (default value) 5 N0.5 R/W 0* 1 = Input port register data inverted 4 N0.4 R/W 0* 3 N0.3 R/W 0* 2 N0.2 R/W 0* 1 N0.1 R/W 0* 0 N0.0 R/W 0* PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 8 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register Bit0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit0 to logic1 enables bus-hold feature for the I/O bank. In this mode, the pull-up/pull-downs will be disabled. Setting the bit0 to logic0 disables bus-hold feature. Bit1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins. Setting the bit1 to logic1 enables selection of pull-up/pull-down using Register3. Setting the bit1 to logic0 disables pull-up/pull-downs on the I/O pins and contents of Register3 will have no effect on the I/O. Table 7. Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit description Legend: * default value. Bit Symbol Access Value Description 7 E0.7 R/W X not used 6 E0.6 R/W X 5 E0.5 R/W X 4 E0.4 R/W X 3 E0.3 R/W X 2 E0.2 R/W X 1 E0.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the I/O pins 0 = disables pull-up/pull-downs on the I/O pins and contents of Register3 will have no effect on the I/O (default value) 1 = enables selection of pull-up/pull-down using Register3 0 E0.0 R/W 0* allows user to enable/disable the bus-hold feature for the I/O pins 0 = disables bus-hold feature (default value) 1 = enables bus-hold feature PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 9 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.5.4 Register 3 - Pull-up/pull-down selector register When bus-hold feature is not selected and bit1 of Register2 is set to logic1, the I/O port can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic1 will select a 100k pull-up resistor for that I/O pin. Setting a bit to logic0 will select a 100k pull-down resistor for that I/O pin. If the bus-hold feature is enabled, writing to this register will have no effect on pull-up/pull-down selection. Table 8. Register 3 - Pull-up/pull-down selector register (address 03h) bit description Legend: * default value. Bit Symbol Access Value Description 7 P0.7 R/W 1* configures I/O port pin to have pull-up or pull-down when bus-hold feature not selected and bit1 of Register2 is 6 P0.6 R/W 1* logic1 5 P0.5 R/W 1* 0 = selects a 100k pull-down resistor for that I/O pin 4 P0.4 R/W 1* 1 = selects a 100k pull-up resistor for that I/O pin 3 P0.3 R/W 1* (default value) 2 P0.2 R/W 1* 1 P0.1 R/W 1* 0 P0.0 R/W 1* 7.5.5 Register 4 - Configuration register This register configures the direction of the I/O pins. If a bit in this register is set (written with logic1), the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with logic0), the corresponding port pin is enabled as an output. At reset, the device’s ports are inputs. Table 9. Register 4 - Configuration register (address 04h) bit description Legend: * default value. Bit Symbol Access Value Description 7 C0.7 R/W 1* configures the direction of the I/O pins 6 C0.6 R/W 1* 0 = corresponding port pin enabled as an output 5 C0.5 R/W 1* 1 = corresponding port pin configured as input (default value) 4 C0.4 R/W 1* 3 C0.3 R/W 1* 2 C0.2 R/W 1* 1 C0.1 R/W 1* 0 C0.0 R/W 1* PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 10 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.5.6 Register 5 - Output port register This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register4. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 10. Register 5 - Output port register (address 05h) bit description Legend: * default value. Bit Symbol Access Value Description 7 O0.7 R/W 0* reflects outgoing logic levels of pins defined as outputs by Register 4 6 O0.6 R/W 0* 5 O0.5 R/W 0* 4 O0.4 R/W 0* 3 O0.3 R/W 0* 2 O0.2 R/W 0* 1 O0.1 R/W 0* 0 O0.0 R/W 0* 7.5.7 Register 6 - Interrupt mask register All the bits of Interrupt mask register are set to logic1 upon power-on or software reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to logic0. Table 11. Register 6 - Interrupt mask register (address 06h) bit description Legend: * default value. Bit Symbol Access Value Description 7 M0.7 R/W 1* enable or disable interrupts 6 M0.6 R/W 1* 0 = enable interrupt 5 M0.5 R/W 1* 1 = disable interrupt (default value) 4 M0.4 R/W 1* 3 M0.3 R/W 1* 2 M0.2 R/W 1* 1 M0.1 R/W 1* 0 M0.0 R/W 1* PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 11 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.5.8 Register 7 - Interrupt status register This register is read-only. It is used to identify the source of interrupt. Remark: If the interrupts are masked, this register will return all zeros. Table 12. Register 7 - Interrupt status register (address 07h) bit description Legend: * default value. Bit Symbol Access Value Description 7 S0.7 read only 0* identifies source of interrupt 6 S0.6 read only 0* 5 S0.5 read only 0* 4 S0.4 read only 0* 3 S0.3 read only 0* 2 S0.2 read only 0* 1 S0.1 read only 0* 0 S0.0 read only 0* 7.6 Power-on reset When power is applied to V , an internal Power-On Reset (POR) holds the PCA9574 in DD a reset condition until V has reached V . At that point, the reset condition is released DD POR and the PCA9574 registers and state machine will initialize to their default states. The power-on reset typically completes the reset and enables the part by the time the power supply is above V . However, when it is required to reset the part by lowering the power POR supply, it is necessary to lower it below 0.2V. 7.7 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of t . The w(rst) PCA9574 registers and I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. 7.8 Software reset The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The Software Reset sequence is defined as following: 1. A START command is sent by the I2C-bus master. 2. The reserved General Call I2C-bus address ‘0000000’ with the R/W bit set to 0 (write) is sent by the I2C-bus master. 3. The PCA9574 device(s) acknowledge(s) after seeing the General Call address ‘00000000’ (00h) only. If the R/W bit is set to logic1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the General Call address has been sent and acknowledged, the master sends 1byte. The value of the byte must be equal to 06h.The PCA9574 acknowledges this value only. If the byte is not equal to 06h, the PCA9574 does not acknowledge it. If more than 1byte of data is sent, the PCA9574 does not acknowledge anymore. PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 12 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9574 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed. The I2C-bus master must interpret a non-acknowledge from the PCA9574 (at any time) as a ‘Software Reset Abort’. The PCA9574 does not initiate a software reset. 7.9 Interrupt output (INT) The open-drain activeLOW interrupt is activated when one of the port pins changes state and the port pin is configured as an input and the interrupt on it is not masked. The interrupt is deactivated when the port pin input returns to its previous state or the Input Port register is read. It is highly recommended to program the MSK register, and the CFG registers during the initialization sequence after power-up, since any change to them during Normal mode operation may cause undesirable interrupt events to happen. Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input port register. Only a read of the Input port register that contains the bit(s) image of the input(s) that generated the interrupt clears the interrupt condition. 7.10 Standby The PCA9574 goes into standby when the I2C-bus is idle. Standby supply current is lower than 1.0A (typical). PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 13 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 8. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure7). SDA SCL data line change stable; of data data valid allowed mba607 Fig 7. Bit transfer 8.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure8). SDA SCL S P START condition STOP condition mba608 Fig 8. Definition of START and STOP conditions 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure9). PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 14 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO SDA SCL MASTER SLAVE SLAVE MASTER MASTER I2C-BUS TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER RECEIVER RECEIVER RECEIVER SLAVE 002aaa966 Fig 9. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eightbits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S clock pulse for START acknowledgement condition 002aaa987 Fig 10. Acknowledgement on the I2C-bus PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 15 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 9. Bus transactions Data is transmitted to the PCA9574 registers using ‘Write Byte’ transfers (see Figure11 and Figure12). Data is read from the PCA9574 registers using ‘Read Byte’ transfers (see Figure13 and Figure14). SCL 1 2 3 4 5 6 7 8 9 STOP condition slave address command byte data to port SDA S 0 1 0 0 0 0 A0 0 A 0 0 0 0 0 1 0 1 A DATA 1 A P START condition R/W acknowledge acknowledge acknowledge from slave from slave from slave write to port tv(Q) data out from port DATA 1 VALID 002aad057 Fig 11. Write to Output port register SCL 1 2 3 4 5 6 7 8 9 STOP condition slave address command byte data to register SDA S 0 1 0 0 0 0 A0 0 A 0 0 0 0 0 X X X A DATA A P START condition R/W acknowledge acknowledge acknowledge from slave from slave from slave data to register 002aad058 Fig 12. Write to Polarity inversion, Bus-hold enable, Pull-up/pull-down selector, Configuration, Interrupt mask and Interrupt status registers PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 16 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO slave address SDA S 0 1 0 0 0 0 A0 0 A command byte A (cont.) START condition R/W acknowledge from slave acknowledge from slave slave address data from register data from register (cont.) S 0 1 0 0 0 0 A0 1 A DATA (first byte) A DATA (last byte) NA P (repeated) R/W acknowledge no acknowledge STOP START condition from master from master condition acknowledge from slave at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter 002aad059 Fig 13. Read from register DATA 2 data into DATA 3 DATA 4 port th(D) tsu(D) INT tv(INT) trst(INT) SCL 1 2 3 4 5 6 7 8 9 no acknowledge from master slave address data from port data from port SDA S 0 1 0 0 0 0 A0 1 A DATA 1 A DATA 4 1 P START condition R/W acknowledge acknowledge STOP from slave from master condition read from port 002aad060 This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. Fig 14. Read Input port register PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 17 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 10. Application design-in information VDD(IO) = 3.6 V VDD = 1.1 V to 3.6 V 1.6 kΩ 1.6 kΩ 1.1 kΩ 2 kΩ SUBSYSTEM 4 (e.g., RF module) VDD VDD VDD(IO) CTRL MASTER CONTROLLER PCA9574 SUBSYSTEM 1 SCL SCL P0 (e.g., temp. sensor) SDA SDA P1 INT INT INT P2 RESET RESET RESET P3 SUBSYSTEM 2 P4 (e.g., counter) VSS P5 P6 A A0 P7 enable controlled switch VSS (e.g., CBT device) B ALARM SUBSYSTEM 3 (e.g., alarm system) VDD(IO) 002aad061 Device address configured as 01000000b for this example. P0, P2, P3 configured as outputs. P1, P4, P5 configured as inputs. P6, P7 are not used and must be configured as outputs. Fig 15. Typical application 11. Limiting values Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +4.0 V DD V input/output supply voltage V 0.5 V +0.5 V DD(IO) SS DD I input/output current - 5 mA I/O I input current - 20 mA I I supply current - 90 mA DD I ground supply current - 90 mA SS P total power dissipation - 75 mW tot T storage temperature 65 +150 C stg T ambient temperature 40 +85 C amb PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 18 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 12. Static characteristics Table 14. Static charac teristics V =1.1V to 3.6V; V =1.1V to 3.6V; V =0V; T =40C to +85C; unless otherwise specified. DD DD(IO) SS amb Symbol Parameter Conditions Min Typ Max Unit Supplies V supply voltage 1.1 - 3.6 V DD V input/output supply voltage 1.1 - V +0.5 V DD(IO) DD I supply current operating mode; V =3.6V; - 135 200 A DD DD noload; f =100kHz; I/O=inputs SCL I LOW-level standby current Standby mode; V =3.6V; noload; - 0.25 1 A stbL DD V =V ; f =0kHz; I/O=inputs I SS SCL I HIGH-level standby current Standby mode; V =3.6V; noload; - 0.25 1 A stbH DD V =V ; f =0kHz; I/O=inputs I DD SCL V power-on reset voltage no load; V =V or V (rising V ) - 0.8 1.0 V POR I DD SS DD Input SCL; input/output SDA V LOW-level input voltage 0.5 - +0.3V V IL DD V HIGH-level input voltage 0.7V - 3.6 V IH DD I LOW-level output current V =0.2V; V =1.1V 1 - - mA OL OL DD V =0.4V; V =2.3V 3 - - mA OL DD I leakage current V =V or V 1 - +1 A L I DD SS C input capacitance V =V - 6 10 pF i I SS I/Os V LOW-level input voltage 0.5 - +0.3V V IL DD(IO) V HIGH-level input voltage 0.7V - 3.6 V IH DD(IO) I HIGH-level output current V =0.9V; V =1.1V 1 - - mA OH OH DD(IO) I LOW-level output current V =0.2V; V =1.1V 1 - - mA OL OL DD(IO) V =0.5V; V =3.6V 2 3 - mA OL DD(IO) V HIGH-level output voltage I =1mA; V =1.1V 0.8 - - V OH OH DD(IO) I HIGH-level input leakage V =3.6V; V =V - - 1 A LIH DD(IO) I DD(IO) current I LOW-level input leakage V =3.6V; V =V - - 1 A LIL DD(IO) I SS current C input capacitance - 3.7 5 pF i C output capacitance - 3.7 5 pF o Interrupt INT I LOW-level output current V =0.4V; V =1.1V 3 - - mA OL OL DD Select input A0; RESET V LOW-level input voltage 0.5 - +0.3V V IL DD V HIGH-level input voltage 0.7V - 3.6 V IH DD I input leakage current V =V or V 1 - +1 A LI I DD SS PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 19 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 002aae765 002aae766 3.0 4.0 VOH VOH (V) (V) 3.0 2.0 2.0 1.0 1.0 0 0 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 Tamb (°C) Tamb (°C) Fig 16. V at V =3.3V, V =1.2V, I =1mA Fig 17. V at V =3.3V, V =3.3V, I =1mA OH DD DD(IO) OH OH DD DD(IO) OH PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 20 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 13. Dynamic characteristics Table 15. Dynamic cha racteristics V =1.1V to 3.6V; V =1.1V to 3.6V; V =0V; T =40C to +85C; unless otherwise specified. DD DD(IO) SS amb Symbol Parameter Conditions Standard-mode Fast-mode I2C-bus Unit I2C-bus Min Max Min Max f SCL clock frequency 0 100 0 400 kHz SCL t bus free time between a STOP and 4.7 - 1.3 - s BUF START condition t hold time (repeated) START condition 4.0 - 0.6 - s HD;STA t set-up time for a repeated START 4.7 - 0.6 - s SU;STA condition t set-up time for STOP condition 4.0 - 0.6 - s SU;STO t data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s VD;ACK t data hold time 0 - 0 - ns HD;DAT t data valid time [2] 300 - 50 - ns VD;DAT t data set-up time 250 - 100 - ns SU;DAT t LOW period of the SCL clock 4.7 - 1.3 - s LOW t HIGH period of the SCL clock 4.0 - 0.6 - s HIGH t fall time of both SDA and SCL signals - 300 20+0.1C [3] 300 ns f b t rise time of both SDA and SCL signals - 1000 20+0.1C [3] 300 ns r b t pulse width of spikes that must be - 50 - 50 ns SP suppressed by the input filter Port timing t data output valid time - 200 - 200 ns v(Q) t data input set-up time 150 - 150 - ns su(D) t data input hold time 1 - 1 - s h(D) Interrupt timing t valid time on pin INT - 4 - 4 s v(INT) t reset time on pin INT - 4 - 4 s rst(INT) Reset t reset pulse width 6 - 6 - ns w(rst) t reset recovery time 0 - 0 - ns rec(rst) t SDA reset time Figure19 - 450 - 450 ns rst(SDA) t GPIO reset time Figure19 - 450 - 450 ns rst(GPIO) [1] t = time for acknowledgement signal from SCL LOW to SDA (out) LOW. VD;ACK [2] t = minimum time for SDA data out to be valid following SCL LOW. VD;DAT [3] C = total capacitance of one bus line in pF. b PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 21 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 0.7 × VDD SDA 0.3 × VDD tBUF tr tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD tHD;STA tSU;STA tSU;STO P S tHD;DAT tHIGH tSU;DAT Sr P 002aaa986 Fig 18. Definition of timing START ACK or read cycle SCL SDA 30 % trst RESET 50 % 50 % 50 % trec(rst) tw(rst) trst 50 % P0 to P7 output off 002aad062 Fig 19. Reset timing PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 22 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 14. Test information 2VDD open VDD RL VSS 500 Ω VI VO PULSE DUT GENERATOR RT C50L pF 500 Ω(1) 002aad582 R = load resistance. L CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. (1) For SDA, no 500 pull-down. Fig 20. Test circuitry for switching times PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 23 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE v M A Z 16 9 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 8 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 54..19 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..4006 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT403-1 MO-153 03-02-18 Fig 21. Package outline SOT403-1 (TSSOP16) PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 24 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm SOT758-1 D B A terminal 1 index area E A A1 c detail X e1 C 1/2 e v M C A B y1 C y e b w M C 5 8 L 4 9 e Eh e2 1/2 e 1 12 terminal 1 16 13 index area Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAa(1x). A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1 0.05 0.30 3.1 1.75 3.1 1.75 0.5 mm 1 0.2 0.5 1.5 1.5 0.1 0.05 0.05 0.1 0.00 0.18 2.9 1.45 2.9 1.45 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 02-03-25 SOT758-1 - - - MO-220 - - - 02-10-21 Fig 22. Package outline SOT758-1 (HVQFN16) PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 25 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 26 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure23) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table16 and17 Table 16. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 17. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure23. PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 27 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 18. Abbreviations Acronym Description CBT Cross Bar Technology CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge GPIO General Purpose Input/Output HBM Human Body Model I/O Input/Output I2C-bus Inter-Integrated Circuit bus IC Integrated Circuit LED Light Emitting Diode LP Low Pass PCB Printed-Circuit Board PLC Programmable Logic Controller POR Power-On Reset RAID Redundant Array of Independent Discs SMBus System Management Bus PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 28 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 19. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9574 v.5 20140925 Product data sheet - PCA9574 v.4 Modifications: • Deleted PCA9574HK and associated package type XQFN16 (SOT1161-1) • Added Table 2 “Ordering options” PCA9574 v.4 20120425 Product data sheet - PCA9574 v.3 PCA9574 v.3 20110622 Product data sheet - PCA9574 v.2 PCA9574 v.2 20090727 Product data sheet - PCA9574 v.1 PCA9574 v.1 20080515 Product data sheet - - PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 29 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 30 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO Export control — This document as well as the item(s) described herein NXP Semiconductors’ specifications such use shall be solely at customer’s may be subject to export control regulations. Export might require a prior own risk, and (c) customer fully indemnifies NXP Semiconductors for any authorization from competent authorities. liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ Non-automotive qualified products — Unless this data sheet expressly standard warranty and NXP Semiconductors’ product specifications. states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested Translations — A non-English (translated) version of a document is for in accordance with automotive testing or application requirements. NXP reference only. The English version shall prevail in case of any discrepancy Semiconductors accepts no liability for inclusion and/or use of between the translated and English versions. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 20.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9574 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 5 — 25 September 2014 31 of 32

PCA9574 NXP Semiconductors 8-bit I2C-bus and SMBus, level translating, low voltage GPIO 22. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 26 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 27 3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3 20 Legal information . . . . . . . . . . . . . . . . . . . . . . 30 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 30 20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 21 Contact information . . . . . . . . . . . . . . . . . . . . 31 7 Functional description . . . . . . . . . . . . . . . . . . . 6 22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 Command register . . . . . . . . . . . . . . . . . . . . . . 7 7.3 Register definitions. . . . . . . . . . . . . . . . . . . . . . 7 7.4 Writing to port registers. . . . . . . . . . . . . . . . . . . 7 7.5 Reading the port registers . . . . . . . . . . . . . . . . 8 7.5.1 Register 0 - Input port register . . . . . . . . . . . . . 8 7.5.2 Register 1 - Polarity inversion register . . . . . . . 8 7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.5.4 Register 3 - Pull-up/pull-down selector register 10 7.5.5 Register 4 - Configuration register . . . . . . . . . 10 7.5.6 Register 5 - Output port register. . . . . . . . . . . 11 7.5.7 Register 6 - Interrupt mask register . . . . . . . . 11 7.5.8 Register 7 - Interrupt status register. . . . . . . . 12 7.6 Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 12 7.7 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.8 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 12 7.9 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 13 7.10 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Characteristics of the I2C-bus . . . . . . . . . . . . 14 8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 START and STOP conditions. . . . . . . . . . . . . 14 8.2 System configuration . . . . . . . . . . . . . . . . . . . 14 8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 16 10 Application design-in information . . . . . . . . . 18 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 13 Dynamic characteristics. . . . . . . . . . . . . . . . . 21 14 Test information. . . . . . . . . . . . . . . . . . . . . . . . 23 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 24 16 Handling information. . . . . . . . . . . . . . . . . . . . 26 17 Soldering of SMD packages . . . . . . . . . . . . . . 26 17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 26 17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 September 2014 Document identifier: PCA9574

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: PCA9574BS,118 PCA9574PW,112 PCA9574PW,118