PCA9538 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset Rev. 8 — 8 November 2017 Product data sheet 1. General description The PCA9538 is a 16-pin CMOS device that provides 8bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications and was developed to enhance the NXPSemiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push-buttons, LEDs, fans, etc. The PCA9538 consists of an 8-bit Configuration register (input or output selection), 8-bitInput Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register (activeHIGH or activeLOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and different address range. The PCA9538 open-drain interrupt output (INT) is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without de-powering the device. Two hardware pins (A0 and A1) vary the fixed I2C-bus address and allow up to four devices to share the same I2C-bus/SMBus. 2. Features and benefits  8-bit I2C-bus GPIO with interrupt and reset  Operating power supply voltage range of 2.3V to 5.5V (3.0V to 5.5V forPCA9538PW/Q900)  5V tolerant I/Os  Polarity Inversion register  Active LOW interrupt output  Active LOW reset input  Low standby current  Noise filter on SCL/SDA inputs  No glitch on power-up

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset  Internal power-on reset  8 I/O pins which default to 8 inputs  0Hz to 400kHz clock frequency  ESD protection exceeds 2000V HBM per JESD22-A114 and 1000V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA  Offered in three different packages: SO16, TSSOP16 and HVQFN16 3. Ordering information Table 1. Ordering info rmation Type number Topside Package marking Name Description Version PCA9538BS 9538 HVQFN16 plastic thermal enhanced very thin quad flat package; SOT629-1 noleads; 16terminals; body440.85mm PCA9538D PCA9538D SO16 plastic small outline package; 16leads; SOT162-1 bodywidth7.5mm PCA9538PW PCA9538 TSSOP16 plastic thin shrink small outline package; 16leads; SOT403-1 bodywidth4.4mm PCA9538PW/Q900[1] PCA9538 TSSOP16 plastic thin shrink small outline package; 16leads; SOT403-1 bodywidth4.4mm [1] PCA9538PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP. 3.1 Ordering options Table 2. Ordering opt ions Type number Orderable partnumber Package Packing method Minimum Temperature order quantity PCA9538BS PCA9538BS,118 HVQFN16 Reel pack, SMD, 6000 T =40C to +85C amb 13-inch PCA9538D PCA9538D,112 SO16 Tube, bulk pack 1920 T =40C to +85C amb PCA9538D,118 SO16 Reel pack, SMD, 1000 T =40C to +85C amb 13-inch PCA9538PW PCA9538PW,112 TSSOP16 Tube, bulk pack 2400 T =40C to +85C amb PCA9538PW,118 TSSOP16 Reel pack, SMD, 2500 T =40C to +85C amb 13-inch PCA9538PW/Q900 PCA9538PW/Q900,118 TSSOP16 Reel pack, SMD, 2500 T =40C to +125C amb 13-inch PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 2 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 4. Block diagram A0 IO0 A1 8-bit IO1 IO2 SCL INPUT I2C-BUS/SMBus INPUT/ IO3 SDA FILTER CONTROL write pulse OPUOTRPTUST IO4 IO5 IO6 read pulse IO7 VDD POWER-ON VDD RESET RESET VSS PCA9538 LP INT FILTER 002aae667 Remark: All I/Os are set to inputs at reset. Fig 1. Block diagram of PCA9538 PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 3 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 5. Pinning information 5.1 Pinning A0 1 16 VDD A0 1 16 VDD A1 2 15 SDA A1 2 15 SDA RESET 3 14 SCL RESET 3 14 SCL IO0 4 13 INT IO0 4 PCA9538PW 13 INT PCA9538D IO1 5 12 IO7 IO1 5 PCA9538PW/Q900 12 IO7 IO2 6 11 IO6 IO2 6 11 IO6 IO3 7 10 IO5 IO3 7 10 IO5 VSS 8 9 IO4 VSS 8 9 IO4 002aae668 002aae669 Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16 D A terminal 1 1 0 D D A A V S index area 6 5 4 3 1 1 1 1 RESET 1 12 SCL IO0 2 11 INT PCA9538BS IO1 3 10 IO7 IO2 4 9 IO6 5 6 7 8 3 S 4 5 O S O O 002aae670 I V I I Transparent top view Fig 4. Pin configuration for HVQFN16 PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 4 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 5.2 Pin description Table 3. Pin description Symbol Pin Description SO16, TSSOP16 HVQFN16 A0 1 15 address input 0 A1 2 16 address input 1 RESET 3 1 activeLOW reset input IO0 4 2 input/output 0 IO1 5 3 input/output 1 IO2 6 4 input/output 2 IO3 7 5 input/output 3 V 8 6[1] supply ground SS IO4 9 7 input/output 4 IO5 10 8 input/output 5 IO6 11 9 input/output 6 IO7 12 10 input/output 7 INT 13 11 interrupt output (open-drain) SCL 14 12 serial clock line SDA 15 13 serial data line V 16 14 supply voltage DD [1] HVQFN16 package die supply ground is connected to both the V pin and the exposed center pad. The SS VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 5 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6. Functional description Refer to Figure 1 “Block diagram of PCA9538”. 6.1 Device address slave address 1 1 1 0 0 A1 A0 R/W fixed hardware selectable 002aae707 Fig 5. PCA9538 address 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the registers will be written or read. Table 4. Command byte Command Protocol Function 0 read byte Input Port register 1 read/write byte Output Port register 2 read/write byte Polarity Inversion register 3 read/write byte Configuration register 6.2.2 Register 0 - Input Port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. Table 5. Register 0 - Input Port register bit description Legend: * default value. Bit Symbol Access Value Description 7 I7 read only X* value ‘X’ is determined by externally applied logiclevel 6 I6 read only X* 5 I5 read only X* 4 I4 read only X* 3 I3 read only X* 2 I2 read only X* 1 I1 read only X* 0 I0 read only X* PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 6 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.3 Register 1 - Output Port register This register reflects the outgoing logic levels of the pins defined as outputs by Register3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 6. Register 1 - Output Port register bit description Legend: * default value. Bit Symbol Access Value Description 7 O7 R 1* reflects outgoing logic levels of pins defined as outputs by Register3 6 O6 R 1* 5 O5 R 1* 4 O4 R 1* 3 O3 R 1* 2 O2 R 1* 1 O1 R 1* 0 O0 R 1* 6.2.4 Register 2 - Polarity Inversion register This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a 0), the Input Port data polarity is retained. Table 7. Register 2 - Polarity Inversion register bit description Legend: * default value. Bit Symbol Access Value Description 7 N7 R/W 0* inverts polarity of Input Port register data 6 N6 R/W 0* 0 = Input Port register data retained (default value) 5 N5 R/W 0* 1 = Input Port register data inverted 4 N4 R/W 0* 3 N3 R/W 0* 2 N2 R/W 0* 1 N1 R/W 0* 0 N0 R/W 0* PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 7 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.2.5 Register 3 - Configuration register This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs. Table 8. Register 3 - Configuration register bit description Legend: * default value. Bit Symbol Access Value Description 7 C7 R/W 1* configures the directions of the I/O pins 6 C6 R/W 1* 0 = corresponding port pin enabled as an output 5 C5 R/W 1* 1 = corresponding port pin configured as an input (default value) 4 C4 R/W 1* 3 C3 R/W 1* 2 C2 R/W 1* 1 C1 R/W 1* 0 C0 R/W 1* 6.3 Power-on reset When power is applied to V , an internal Power-On Reset (POR) holds the PCA9538 in DD a reset condition until V has reached V . At that point, the reset condition is released DD POR and the PCA9538 registers and state machine will initialize to their default states. Thereafter, V must be lowered below 0.2V to reset the device. DD For a power reset cycle, V must be lowered below 0.2V and then restored to the DD operating voltage. 6.4 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of t . w(rst) ThePCA9538 registers and SMBus/I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to V if no active connection is used. DD 6.5 Interrupt output The open-drain interrupt output (INT) is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is de-activated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 8 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.6 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above V to a maximum of 5.5V. DD If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either V or V . DD SS data from output port shift register register data configuration register VDD data from D Q Q1 shift register FF write D Q configuration CK Q pulse FF I/O pin write pulse CK Q2 output port input port VSS register register D Q input port FF register data read pulse CK to INT polarity inversion register data from D Q polarity shift register inversion FF register data write polarity CK pulse 002aad723 Remark: At power-on reset, all registers return to default values. Fig 6. Simplified schematic of IO0 to IO7 PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 9 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.7 Bus transactions Data is transmitted to the PCA9538 registers using the write mode as shown in Figure7 and Figure8. Data is read from the PCA9538 registers using the read mode as shown in Figure9 and Figure10. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. SCL 1 2 3 4 5 6 7 8 9 STOP condition slave address command byte data to port SDA S 1 1 1 0 0 A1 A0 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P START condition R/W acknowledge acknowledge acknowledge from slave from slave from slave write to port tv(Q) data out from port DATA 1 VALID 002aae708 Expanded diagram is shown in Figure18. Fig 7. Write to output port register SCL 1 2 3 4 5 6 7 8 9 STOP condition slave address command byte data to register SDA S 1 1 1 0 0 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A DATA 1 A P START condition R/W acknowledge acknowledge acknowledge from slave from slave from slave data to register 002aae709 Fig 8. Write to configuration or polarity inversion registers PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 10 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset slave address SDA S 1 1 1 0 0 A1 A0 0 A COMMAND BYTE A (cont.) START condition R/W acknowledge acknowledge from slave from slave slave address data from register data from register (cont.) S 1 1 1 0 0 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P (repeated) R/W acknowledge no acknowledge STOP START condition acknowledge from master from master condition from slave at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter 002aae710 Fig 9. Read from register SCL 1 2 3 4 5 6 7 8 9 no acknowledge from master slave address data from port data from port SDA S 1 1 1 0 0 A1 A0 1 A DATA 1 A DATA 4 NA P START condition R/W acknowledge acknowledge STOP from slave from master condition read from port data into DATA 1 DATA 2 DATA 3 DATA 4 port th(D) tsu(D) INT tv(INT) trst(INT) 002aae711 This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. Expanded diagram is shown in Figure17. Fig 10. Read input port register PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 11 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 7. Application design-in information VDD (5 V) 10 kΩ 10 kΩ 10 kΩ 10 kΩ 2 kΩ 1(×0 03 )kΩ (eS.gU.B, t-eSmYpS TsEenMs o1r) VDD VDD MASTER INT PCA9538 CONTROLLER SCL SCL IO0 SUB-SYSTEM 2 SDA SDA IO1 (e.g., counter) INT INT IO2 RESET RESET RESET IO3 A VSS IO4 controlled enable switch IO5 (e.g., CBT device) A1 IO6 B A0 IO7 SUB-SYSTEM 3 VSS (e.g., alarm system) ALARM VDD 002aae712 Device address is 1110000x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used and need 100k pull-up resistors to protect them from floating. Fig 11. Typical application PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 12 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 7.1 Minimizing I when the I/Os are used to control LEDs DD When the I/Os are used to control LEDs, they are normally connected to V through a DD resistor as shown in Figure11. Since the LED acts as a diode, when the LED is off the I/OV is about 1.2V less than V . The supply current, I , increases as V becomes I DD DD I lower than V . DD Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V when the LED is off. DD Figure12 shows a high value resistor in parallel with the LED. Figure13 shows V less DD than the LED supply voltage by at least 1.2V. Both of these methods maintain the I/OV I at or above V and prevents additional supply current consumption when the LED is off. DD 3.3 V 5 V VDD VDD LED 100 kΩ VDD LED IOn IOn 002aac660 002aac661 Fig 12. High value resistor in parallel with Fig 13. Device supplied by a lower voltage the LED 8. Limiting values Table 9. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +6.0 V DD I input current - 20 mA I V voltage on an input/output pin V 0.5 5.5 V I/O SS I output current on pin IOn - 50 mA O(IOn) I supply current - 85 mA DD I ground supply current - 100 mA SS P total power dissipation - 200 mW tot T storage temperature 65 +150 C stg T ambient temperature operating amb all devices except PCA9538PW/Q900 40 +85 C PCA9538PW/Q900 40 +125 C T maximum junction temperature - +125 C j(max) PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 13 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 9. Static characteristics Table 10. Static charac teristics for all devices except PCA9538PW/Q900 V =2.3V to 5.5V; V =0V; T =40C to +85C; unless otherwise specified. DD SS amb Symbol Parameter Conditions Min Typ Max Unit Supplies V supply voltage 2.3 - 5.5 V DD I supply current operating mode; V =5.5V; - 104 175 A DD DD noload; f =100kHz SCL I LOW-level standby current Standby mode; V =5.5V; - 0.25 1 A stbL DD noload; V =V ; I SS f =0kHz; I/O=inputs SCL I HIGH-level standby current Standby mode; V =5.5V; - 0.25 1 A stbH DD noload; V =V ; I DD f =0kHz; I/O=inputs SCL V power-on reset voltage noload; V =V or V [1] - 1.7 2.2 V POR I DD SS Input SCL; input/output SDA V LOW-level input voltage 0.5 - +0.3V V IL DD V HIGH-level input voltage 0.7V - 5.5 V IH DD I LOW-level output current V =0.4V 3 7 - mA OL OL I leakage current V =V =V 1 - +1 A L I DD SS C input capacitance V =V - 5 10 pF i I SS I/Os V LOW-level input voltage 0.5 - +0.8 V IL V HIGH-level input voltage 2.0 - 5.5 V IH I LOW-level output current V =0.5V OL OL V =2.3V [2] 8 10 - mA DD V =3.0V [2] 8 14 - mA DD V =4.5V [2] 8 17 - mA DD V =0.7V OL V =2.3V [2] 10 13 - mA DD V =3.0V [2] 10 19 - mA DD V =4.5V [2] 10 24 - mA DD V HIGH-level output voltage I =8mA OH OH V =2.3V [3] 1.8 - - V DD V =3.0V [3] 2.6 - - V DD V =4.5V [3] 4.1 - - V DD I =10mA OH V =2.3V [3] 1.7 - - V DD V =3.0V [3] 2.5 - - V DD V =4.5V [3] 4.0 - - V DD I input leakage current V =V =V 1 - +1 A LI I DD SS C input capacitance - 5 10 pF i PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 14 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 10. Static characteristics for all devices except PCA9538PW/Q900 …continued V =2.3V to 5.5V; V =0V; T =40C to +85C; unless otherwise specified. DD SS amb Symbol Parameter Conditions Min Typ Max Unit Interrupt INT I LOW-level output current V =0.4V 3 13 - mA OL OL Select inputs A0, A1, RESET V LOW-level input voltage 0.5 - +0.8 V IL V HIGH-level input voltage 2.0 - 5.5 V IH I input leakage current 1 - +1 A LI [1] V must be lowered to 0.2V in order to reset part. DD [2] Each I/O must be externally limited to a maximum of 25mA and the device must be limited to a maximum current of 100mA. [3] The total current sourced by all I/Os must be limited to 85mA. Table 11. Static charac teristics for PCA9538PW/Q900 AEC-Q100 compliant device V =3.0 V to 5.5 V; V =0V; T =40C to +125C; unless otherwise specified. DD SS amb Symbol Parameter Conditions Min Typ Max Unit Supplies V supply voltage 3.0 - 5.5 V DD I supply current operating mode; V =5.5V; - 104 175 A DD DD noload; f =100kHz SCL I LOW-level standby current Standby mode; V =5.5V; - 0.25 1 A stbL DD noload; V =V ; I SS f =0kHz; I/O=inputs SCL I HIGH-level standby current Standby mode; V =5.5V; - 0.25 1 A stbH DD noload; V =V ; I DD f =0kHz; I/O=inputs SCL V power-on reset voltage noload; V =V or V [1] - 1.7 2.2 V POR I DD SS Input SCL; input/output SDA V LOW-level input voltage 0.5 - +0.3V V IL DD V HIGH-level input voltage 0.7V - 5.5 V IH DD I LOW-level output current, SDA V =0.4V OL OL V =5.5V 3 7 - mA DD V =3.0V 2.5 - - mA DD I leakage current V =V =V 1 - +1 A L I DD SS C input capacitance V =V - 5 10 pF i I SS I/Os V LOW-level input voltage 0.5 - +0.8 V IL V HIGH-level input voltage 2.0 - 5.5 V IH I LOW-level output current V =0.5V OL OL V =4.5V [2] 8 17 - mA DD V =3.0V [2] 7.5 - - mA DD V =0.7V OL V =4.5V [2] 10 24 - mA DD V =3.0V [2] 9.5 - - mA DD PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 15 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset Table 11. Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device …continued V =3.0 V to 5.5 V; V =0V; T =40C to +125C; unless otherwise specified. DD SS amb Symbol Parameter Conditions Min Typ Max Unit V HIGH-level output voltage I =8 mA OH OH V =4.5V [3] 4.1 - - V DD V =3.0V [3] 2.5 - - V DD I =10 mA OH V =4.5V [3] 4.0 - - V DD V =3.0V [3] 2.4 - - V DD I input leakage current V =V =V 1 - +1 A LI I DD SS C input capacitance - 5 10 pF i Interrupt INT I LOW-level output current V =0.4V 3 13 - mA OL OL Select inputs A0, A1, RESET V LOW-level input voltage 0.5 - +0.8 V IL V HIGH-level input voltage 2.0 - 5.5 V IH I input leakage current 1 - +1 A LI [1] V must be lowered to 0.2V in order to reset part. DD [2] Each I/O must be externally limited to a maximum of 25mA and the device must be limited to a maximum current of 100mA. [3] The total current sourced by all I/Os must be limited to 85mA. PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 16 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 10. Dynamic characteristics Table 12. Dynamic cha racteristics Symbol Parameter Conditions Standard-mode Fast-mode I2C-bus Unit I2C-bus Min Max Min Max f SCL clock frequency 0 100 0 400 kHz SCL t bus free time between a STOP and 4.7 - 1.3 - s BUF START condition t hold time (repeated) START condition 4.0 - 0.6 - s HD;STA t set-up time for a repeated START 4.7 - 0.6 - s SU;STA condition t set-up time for STOP condition 4.0 - 0.6 - s SU;STO t data hold time 0 - 0 - ns HD;DAT t data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s VD;ACK t data valid time [2] 300 - 50 - ns VD;DAT t data set-up time 250 - 100 - ns SU;DAT t LOW period of the SCL clock 4.7 - 1.3 - s LOW t HIGH period of the SCL clock 4.0 - 0.6 - s HIGH t rise time of both SDA and SCL signals - 1000 20+0.1C [3] 300 ns r b t fall time of both SDA and SCL signals - 300 20+0.1C [3] 300 ns f b t pulse width of spikes that must be - 50 - 50 ns SP suppressed by the input filter Port timing t data output valid time - 200 - 200 ns v(Q) t data input set-up time 100 - 100 - ns su(D) t data input hold time 1 - 1 - s h(D) Interrupt timing t valid time on pin INT - 4 - 4 s v(INT) t reset time on pin INT - 4 - 4 s rst(INT) RESET t reset pulse width 4 - 4 - ns w(rst) t reset recovery time 0 - 0 - ns rec(rst) t reset time 400 - 400 - ns rst [1] t = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. VD;ACK [2] t = minimum time for the SDA data out to be valid following SCL LOW. VD;DAT [3] C = total capacitance of one bus line in pF. b PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 17 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 0.7 × VDD SDA 0.3 × VDD tBUF tr tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD tHD;STA tSU;STA tSU;STO P S tHD;DAT tHIGH tSU;DAT Sr P 002aaa986 Fig 14. Definition of timing START bit 7 STOP bit 6 bit 1 bit 0 acknowledge protocol condition MSB condition (A6) (D1) (D0) (A) (S) (A7) (P) tSU;STA tLOW tHIGH 1 / fSCL SCL 0.7 × VDD 0.3 × VDD tBUF tf tr SDA 0.7 × VDD 0.3 × VDD tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab285 Rise and fall times refer to V and V . IL IH Fig 15. I2C-bus timing diagram START ACK or read cycle SCL SDA 30 % trst RESET 50 % 50 % 50 % trec(rst) tw(rst) trst after reset, IOn 50 % I/Os reconfigured as inputs 002aad732 Fig 16. Definition of RESET timing PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 18 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 70 % SCL 2 1 0 A P 30 % SDA tsu(D) th(D) input 50 % tv(INT) trst(INT) INT 002aae641 Fig 17. Expanded view of read input port register 70 % SCL 2 1 0 A P SDA tv(Q) output 50 % 002aad735 Fig 18. Expanded view of write to output port register PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 19 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 11. Test information VDD open VDD RL VSS 500 Ω VI VO PULSE DUT GENERATOR RT C50L pF 002aab880 R = load resistor. L CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 19. Test circuitry for switching times RL S1 2VDD from output under test open 500 Ω GND CL RL 50 pF 500 Ω 002aac226 Fig 20. Test circuit T able 13. Test data Test Load Switch R C L L t 500 50pF 2V v(Q) DD PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 20 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 12. Package outline SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c y HE v M A Z 16 9 Q A2 A A1 (A 3 ) pin 1 index θ Lp L 1 8 detail X e w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.3 2.45 0.49 0.32 10.5 7.6 10.65 1.1 1.1 0.9 mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1 0.1 2.25 0.36 0.23 10.1 7.4 10.00 0.4 1.0 0.4 8o 0.012 0.096 0.019 0.013 0.41 0.30 0.419 0.043 0.043 0.035 0o inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004 0.004 0.089 0.014 0.009 0.40 0.29 0.394 0.016 0.039 0.016 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT162-1 075E03 MS-013 03-02-19 Fig 21. Package outline SOT162-1 (SO16) PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 21 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE v M A Z 16 9 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 8 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 54..19 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..4006 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT403-1 MO-153 03-02-18 Fig 22. Package outline SOT403-1 (TSSOP16) PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 22 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm SOT629-1 D B A terminal 1 index area A A1 E c detail X e1 C 1/2 e e b v M C A B y1 C y 5 8 w M C L 9 4 e Eh e2 1/2 e 1 12 terminal 1 index area 16 13 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1 0.05 0.38 4.1 2.25 4.1 2.25 0.75 mm 1 0.2 0.65 1.95 1.95 0.1 0.05 0.05 0.1 0.00 0.23 3.9 1.95 3.9 1.95 0.50 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 01-08-08 SOT629-1 - - - MO-220 - - - 02-10-22 Fig 23. Package outline SOT629-1 (HVQFN16) PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 23 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 13. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 24 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure24) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table14 and15 Table 14. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 15. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure24. PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 25 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 26 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 15. Soldering: PCB footprints Footprint information for reflow soldering of SO16 package SOT162-1 Hx Gx P2 (0.125) (0.125) Hy Gy By Ay C D2 (4x) P1 D1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 1.270 1.320 11.200 6.400 2.400 0.700 0.800 10.040 8.600 11.900 11.450 sot162-1_fr Fig 25. PCB footprint for SOT162-1 (SO16); reflow soldering PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 27 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset Footprint information for reflow soldering of TSSOP16 package SOT403-1 Hx Gx P2 (0.125) (0.125) Hy Gy By Ay C D2 (4x) P1 D1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450 sot403-1_fr Fig 26. PCB footprint for SOT403-1 (TSSOP16); reflow soldering PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 28 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset Footprint information for reflow soldering of HVQFN16 package SOT629-1 Hx Gx D P 0.025 0.025 C (0.105) SPx nSPx SPy ot Hy Gy y t SLy By Ay P nSPy S SPx tot SLx Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area nSPx nSPy 2 2 Dimensions in mm P Ax Ay Bx By C D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hx Hy 0.650 5.000 5.000 2.800 2.800 1.100 0.300 2.000 2.000 1.200 1.200 0.450 0.450 4.300 4.300 5.250 5.250 07-05-07 Issue date sot629-1_fr 09-06-15 Fig 27. PCB footprint for SOT629-1 (HVQFN16); reflow soldering PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 29 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 16. Abbreviations Table 16. Abbreviations Acronym Description ACPI Advanced Configuration and Power Interface CBT Cross-Bar Technology CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge FET Field-Effect Transistor FF Flip-Flop GPIO General Purpose Input/Output HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light Emitting Diode LP Low-Pass POR Power-On Reset SMBus System Management Bus PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 30 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 17. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9538v.8 20171108 Product data sheet 201710002I PCA9538v.7 Modifications: • Table 10 “Static characteristics for all devices except PCA9538PW/Q900”, Table 11 “Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device”: Corrected V typ and max POR limit PCA9538v.7 20141126 Product data sheet PCA9538v.6 Modifications: • Table 11 “Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device”: updated I OL and V ; changed operating power supply voltage range from “5.0 V  10 %” to “3.0 V to 5.5 V” OH for PCA9538PW/Q900 PCA9538v.6 20130206 Product data sheet PCA9538v.5 PCA9538v.5 20090528 Product data sheet - PCA9538v.4 PCA9538v.4 20060921 Product data sheet - PCA9538v.3 PCA9538v.3 20041005 Product data sheet - PCA9538v.2 (939775014176) PCA9538v.2 20040930 Objective data sheet - PCA9538v.1 (939775014049) PCA9538v.1 20040820 Objective data sheet - - (939775012881) PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 31 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 32 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset Export control — This document as well as the item(s) described herein own risk, and (c) customer fully indemnifies NXP Semiconductors for any may be subject to export control regulations. Export might require a prior liability, damages or failed product claims resulting from customer design and authorization from competent authorities. use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, Translations — A non-English (translated) version of a document is for the product is not suitable for automotive use. It is neither qualified nor tested reference only. The English version shall prevail in case of any discrepancy in accordance with automotive testing or application requirements. NXP between the translated and English versions. Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 18.4 Trademarks In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks (a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP Semiconductors N.V. NXP Semiconductors’ specifications such use shall be solely at customer’s 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9538 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. Product data sheet Rev. 8 — 8 November 2017 33 of 34

PCA9538 NXP Semiconductors 8-bit I2C-bus and SMBus low power I/O port with interrupt and reset 20. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.1 Command byte. . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.2 Register0 - Input Port register. . . . . . . . . . . . . 6 6.2.3 Register 1 - Output Port register. . . . . . . . . . . . 7 6.2.4 Register 2 - Polarity Inversion register . . . . . . . 7 6.2.5 Register 3 - Configuration register . . . . . . . . . . 8 6.3 Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.5 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . . 8 6.6 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.7 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 10 7 Application design-in information . . . . . . . . . 12 7.1 Minimizing I when the I/Os are used to control DD LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 17 11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 20 12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 21 13 Handling information. . . . . . . . . . . . . . . . . . . . 24 14 Soldering of SMD packages . . . . . . . . . . . . . . 24 14.1 Introduction to soldering. . . . . . . . . . . . . . . . . 24 14.2 Wave and reflow soldering. . . . . . . . . . . . . . . 24 14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 24 14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 25 15 Soldering: PCB footprints. . . . . . . . . . . . . . . . 27 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 30 17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 31 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 32 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32 18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 33 19 Contact information. . . . . . . . . . . . . . . . . . . . . 33 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 November 2017 Document identifier: PCA9538

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: PCA9538BS,118 PCA9538D,112 PCA9538D,118 PCA9538PW,112 PCA9538PW,118 PCA9538PW/Q900,118