PCA9512A; PCA9512B Level shifting hot swappable I2C-bus and SMBus bus buffer Rev. 6 — 1 March 2013 Product data sheet 1. General description The PCA9512A/B is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3V and 5V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7V to 5.5V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9512A/B provides bidirectional buffering, keeping the backplane and card capacitances isolated. Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated 13Dec2010), so the PCA9512B will be discontinued in the near future and is not recommended for new designs. The PCA9512A/B risetime accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9512A/B incorporates a digital input pin that enables and disables the rise time accelerators on all four SDAn and SCLn pins. During insertion, the PCA9512A/B SDAn and SCLn pins are precharged to 1V to minimize the current required to charge the parasitic capacitance of the chip. The incremental offset design of the PCA9510A/11A/12A/12B/13A/14A I/O drivers allows them to be connected to another PCA9510A/11A/12A/12B/13A/14A device in series or in parallel and to the I2C compliant side of static offset bus buffers, but not to the static offset side of those bus buffers. 2. Features and benefits  Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems  Compatible with I2C-bus Standard mode, I2C-bus Fast mode, and SMBus standards  Built-in V/t rise time accelerators on all SDA and SCL lines (0.6V threshold) with ability to disable V/t risetime accelerator through the ACC pin for lightly loaded systems, requires the bus pull-up voltage and respective supply voltage (V or V ) CC CC2 to be the same  5V to 3.3V level translation with optimum noise margin  High-impedance SDAn and SCLn pins for V orV =0V CC CC2  1V precharge on all SDAn and SCLn pins  Supports clock stretching and multiple master arbitration and synchronization

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer  Operating power supply voltage range: 2.7V to 5.5V  0Hz to 400kHz clock frequency  ESD protection exceeds 2000V HBM per JESD22-A114 and 1000V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA  Packages offered: SO8, TSSOP8 (MSOP8) 3. Applications  cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system 4. Feature selection Table 1. Feature sele ction chart Feature PCA9510A PCA9511A PCA9512A/B PCA9513A PCA9514A Idle detect yes yes yes yes yes High-impedance SDAn, SCLn pins for V =0V yes yes yes yes yes CC Rise time accelerator circuitry on SDAn and SCLn pins - yes yes yes yes Rise time accelerator circuitry hardware disable pin for - - yes - - lightly loaded systems Rise time accelerator threshold 0.8V versus 0.6V - - - yes yes improves noise margin Ready open-drain output yes yes - yes yes Two V pins to support 5V to 3.3V level translation - - yes - - CC with improved noise margins 1V precharge on all SDAn and SCLn pins in only yes yes - - 92A current source on SCLIN and SDAIN for PICMG - - - yes - applications PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 2 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 5. Ordering information Table 2. Ordering info rmation Type number Topside Package mark Name Description Version PCA9512AD PA9512A SO8 plastic small outline package; 8leads; body width 3.9mm SOT96-1 PCA9512BD PA9512B PCA9512ADP 9512A TSSOP8[1] plastic thin shrink small outline package; 8leads; body width 3mm SOT505-1 PCA9512BDP 9512B [1] Also known as MSOP8. 5.1 Ordering options Table 3. Ordering opt ions Type number Orderable Package Packing method Minimum Temperature range partnumber order quantity PCA9512AD PCA9512AD,112 SO8 standard marking * 2000 T =40C to +85C amb IC’stube-DSC bulk pack PCA9512AD,118 SO8 reel 13” Q1/T1 2500 T =40C to +85C amb *standardmarkSMD PCA9512BD PCA9512BD,118 SO8 reel 13” Q1/T1 2500 T =40C to +85C amb *standardmarkSMD PCA9512ADP PCA9512ADP,118 TSSOP8 reel 13” Q1/T1 2500 T =40C to +85C amb *standardmarkSMD PCA9512BDP PCA9512BDP,118 TSSOP8 reel 13” Q1/T1 2500 T =40C to +85C amb *standardmarkSMD PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 3 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 6. Block diagram PCA9512A/B VCC VCC2 2 mA 2 mA SLEW RATE SLEW RATE ACC DETECTOR DETECTOR BACKPLANE-TO-CARD SDAIN SDAOUT CONNECTION CONNECT CONNECT CONNECT 100 kΩ 100 kΩ RCH1 RCH3 1 VOLT PRECHARGE 100 kΩ 100 kΩ RCH2 RCH4 2 mA 2 mA SLEW RATE SLEW RATE ACC ACC DETECTOR DETECTOR BACKPLANE-TO-CARD SCLIN SCLOUT CONNECTION CONNECT CONNECT LEVEL SHIFTER STOP BIT AND BUS IDLE 0.5 μA 0.55VCC/ 0.55VCC/ 0.45VCC 0.45VCC 20 pF CONNECT CONNECT 100 μs UVLO UVLO RD DELAY QB S GND 0.5 pF 002aag555 Fig 1. Block diagram of PCA9512A/B PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 4 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 7. Pinning information 7.1 Pinning VCC2 1 8 VCC VCC2 1 8 VCC SCLOUT 2 PCA9512AD 7 SDAOUT SCLOUT 2 PCA9512ADP 7 SDAOUT SCLIN 3 PCA9512BD 6 SDAIN SCLIN 3 PCA9512BDP 6 SDAIN GND 4 5 ACC GND 4 5 ACC 002aab789 002aab790 Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8 7.2 Pin description Table 4. Pin description Symbol Pin Description V 1 Supply voltage for devices on the card I2C-bus. Connect pull-up resistors CC2 from SDAOUT and SCLOUT to this pin. SCLOUT 2 serial clock output to and from the SCL bus on the card SCLIN 3 serial clock input to and from the SCL bus on the backplane GND 4 ground supply; connect this pin to a ground plane for best results. ACC 5 CMOS threshold digital input pin that enables and disables the risetime accelerators on all four SDAn and SCLn pins. ACC enables all accelerators when set to V , and turns them off when set to GND. CC2 SDAIN 6 serial data input to and from the SDA bus on the backplane SDAOUT 7 serial data output to and from the SDA bus on the card V 8 supply voltage; from the backplane, connect pull-up resistors from SDAIN CC and SCLIN to this pin. 8. Functional description Refer to Figure 1 “Block diagram of PCA9512A/B”. Both the PCA9512A and PCA9512B use identical silicon (PCN201012007F dated 13Dec2010), so the PCA9512B will be discontinued in the near future and is not recommended for new designs. Customers should continue using the PCA9512A or move to the PCA9512A during the next refresh if they are currently using the PCA9512B. Description of the PCA9512A operation applies equally to the PCA9512B for the remainder of this data sheet. 8.1 Start-up When the PCA9512A is powered up, either V or V may rise first, within a short time CC CC2 of each other and either may be more positive or they may be equal, however the PCA9512A will not leave the undervoltage lockout or initialization state until both V and CC V have gone above 2.5V. If either V or V drops below 2.0V it will return to the CC2 CC CC2 undervoltage lockout state. PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 5 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer In the undervoltage lockout state the connection circuitry is disabled, the rise time accelerators are disabled, and the precharge circuitry is also disabled. After both V and CC V are valid, independent of which is higher, the PCA9512A/B enters the initialization CC2 state; during this state the 1V precharge circuitry is activated and pulls up the SDAn and SCLn pins to 1V through individual 100k nominal resistors. At the end of the initialization state the ‘Stop bit and bus idle’ detect circuit is enabled. When all the SDAn and SCLn pins have been HIGH for the bus idle time or when all pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, the connect circuitry is activated, connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1V precharge circuitry is disabled when the connection is made, unless the ACC pin is LOW; the rise time accelerators are enabled at this time also. 8.2 Connect circuitry Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as SCLIN and SCLOUT become identical, with each acting as a bidirectional buffer that isolates the input bus capacitance from the output bus capacitance while communicating. If V V , then a level shifting function is performed between input and output. A LOW CC CC2 forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the PCA9512A/B. The same is also true for the SCLn pins. Noise between 0.7V and V CC CC on the SDAIN and SCLIN pins, and 0.7V and V on the SDAOUT and SCLOUT pins CC2 CC2 is generally ignored because a falling edge is only recognized when it falls below 0.7V CC for SDAIN and SCLIN (or 0.7V for SDAOUT and SCLOUT pins) with a slew rate of at CC2 least 1.25V/s. When a falling edge is seen on one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small voltage above the falling pin. The driver will pull the pin down at a slew rate determined by the driver and the load. The first falling pin may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial pull-down rate will continue until it is LOW. If the first falling pin has a slow slew rate, then the second pin will be pulled down at its initial slew rate only until it is just above the first pin voltage then they will both continue down at the slew rate of the first. Once both sides are LOW they will remain LOW until all the external drivers have stopped driving LOWs. If both sides are being driven LOW to the same (or nearly the same) value by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving, that pin will rise and rise above the nominal offset voltage until the internal driver catches up and pulls it back down to the offset voltage. This bounce is worst for low capacitances and low resistances, and may become excessive. When the last external driver stops driving a LOW, that pin will bounce up and settle out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the RC time constant. As long as the slew rate is at least 1.25V/s, when the pin voltage exceeds 0.6V, the rise time accelerator circuits are turned on and the pull-down driver is turned off. If the ACC pin is LOW, the rise time accelerator circuits will be disabled, but the pull-down driver will still turn off. 8.3 Maximum number of devices in series Each buffer adds about 0.1V dynamic level offset at 25C with the offset larger at higher temperatures. Maximum offset (V ) is 0.150V with a 10k pull-up resistor. The LOW offset level at the signal origination end (master) is dependent upon the load and the only specification point is the I2C-bus specification of 3mA will produce V <0.4V, although if OL lightly loaded the V may be ~0.1V. Assuming V =0.1V and V =0.1V, the level OL OL offset after four buffers would be 0.5V, which is only about 0.1V below the threshold of the PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 6 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer rising edge accelerator (about 0.6V). With great care a system with four buffers may work, but as the V moves up from 0.1V, noise or bounces on the line will result in firing OL the rising edge accelerator thus introducing false clock edges. Generally it is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset. The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull-down off. If the V is above ~0.6V and a rising edge is IL detected, the pull-down will turn off and will not turn back on until a falling edge is detected. buffer A buffer B MASTER SLAVE B common node buffer C SLAVE C 002aab581 Fig 4. System with 3 buffers connected to common node Consider a system with three buffers connected to a common node and communication between the Master and Slave B that are connected at either end of bufferA and bufferB in series as shown in Figure4. Consider if the V at the input of bufferA is 0.3V and the OL V of SlaveB (when acknowledging) is 0.4V with the direction changing from Master to OL SlaveB and then from SlaveB to Master. Before the direction change you would observe V at the input of bufferA of 0.3V and its output, the common node, is ~0.4V. The output IL of bufferB and bufferC would be ~0.5V, but SlaveB is driving 0.4V, so the voltage at SlaveB is 0.4V. The output of bufferC is ~0.5V. When the Master pull-down turns off, the input of bufferA rises and so does its output, the common node, because it is the only part driving the node. The common node will rise to 0.5V before bufferB’s output turns on, if the pull-up is strong the node may bounce. If the bounce goes above the threshold for the rising edge accelerator ~0.6V the accelerators on both bufferA and bufferC will fire contending with the output of bufferB. The node on the input of bufferA will go HIGH as will the input node of bufferC. After the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to ~0.5V because the bufferB is still on. The voltage at both the Master and SlaveC nodes would then fall to ~0.6V until SlaveB turned off. This would not cause a failure on the data line as long as the return to 0.5V on the common node (~0.6V at the Master and SlaveC) occurred before the data setup time. If this were the SCL line, the parts on bufferA and bufferC would see a false clock rather than a stretched clock, which would cause a system error. PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 7 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 8.4 Propagation delays The delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. If the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides. The t may be PLH negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. The t can never be negative because the output does not start to fall until the input is PHL below 0.7V (or 0.7V for SDAOUT and SCLOUT), and the output turn-ON has a CC CC2 non-zero delay, and the output has a limited maximum slew rate, and even if the input slew rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage. The maximum t occurs when the input is driven LOW with PHL zero delay and the output is still limited by its turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature, V or V and process, as well as the load current and the CC CC2 load capacitance. 8.5 Rise time accelerators During positive bus transactions, a 2mA current source is switched on to quickly slew the SDA and SCL lines HIGH once the input level of 0.6V for the PCA9512A is exceeded. The rising edge rate should be at least 1.25V/s to guarantee turn on of the accelerators. The built-in V/t rise time accelerators on all SDA and SCL lines requires the bus pull-up voltage and respective supply voltage (V or V ) to be the same. The built-in V/t CC CC2 rise time accelerators can be disabled through the ACC pin for lightly loaded systems. 8.6 ACC boost current enable Users having lightly loaded systems may wish to disable the rise time accelerators. Driving this pin to ground turns off the rise time accelerators on all four SDAn and SCLn pins. Driving this pin to the V voltage enables normal operation of the rise time CC2 accelerators. 8.7 Resistor pull-up value selection The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25V/s on the SDAn and SCLn pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value using the formula given in Equation1: V –0.6 R 800103----C----C-----m---i--n----------------- (1) PU  C  where R is the pull-up resistor value in , V is the minimum V voltage in volts, PU CC(min) CC and C is the equivalent bus capacitance in picofarads. PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 8 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer In addition, regardless of the bus capacitance, always choose R 65.7 k for PU V =5.5V maximum, R 45k for V =3.6V maximum. The start-up circuitry CC PU CC requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. See the curves in Figure5 and Figure6 for guidance in resistor pull-up selection. 002aae782 50 RPU (kΩ) Rmax = 45 kΩ 40 (1) 30 rise time = 300 ns(2) 20 rise time = 20 ns 10 Rmin = 1 kΩ 0 0 100 200 300 400 Cb (pF) (1) Unshaded area indicates recommended pull-up, for rise time<300ns, with rise time accelerator turned on. (2) Rise time accelerator off. Fig 5. Bus requirements for 3.3V systems 002aae783 70 RPU (kΩ) Rmax = 65.7 kΩ 60 50 (1) 40 rise time = 300 ns(2) 30 20 rise time = 20 ns 10 Rmin = 1.7 kΩ 0 0 100 200 300 400 Cb (pF) (1) Unshaded area indicates recommended pull-up, for rise time<300ns, with rise time accelerator turned on. (2) Rise time accelerator off. Fig 6. Bus requirements for 5V systems PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 9 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 8.8 Hot swapping and capacitance buffering application Figure7 through Figure9 illustrate the usage of the PCA9512A in applications that take advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making risetime and falltime requirements difficult to meet. Placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the PCA9512A drives the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10pF, the connector, trace, and all additional cards on the backplane. See Application Note AN10160, ‘Hot Swap Bus Buffer’ for more information on applications and technical assistance. BACKPLANE CONNECTOR BACKPLANE I/O PERIPHERAL CARD 1 R POWER SUPPLY VCC2 TO HOT SWAP C1 EC 0.01 μF R4 R5 R6 BD_SEL N 10 kΩ 10 kΩ 10 kΩ N O R3 PCA9512A VCC ED C 5.1 Ω VCC VCC2SDAOUT CARD1_SDA SDA R SDAIN SCLOUT CARD1_SCL E SCL G SCLIN ACC G C2 0.01 μF GND A T S R1 R2 10 kΩ 10 kΩ I/O PERIPHERAL CARD 2 R POWER SUPPLY TO HOT SWAP C3 EC 0.01 μF R8 R9 R10 N 10 kΩ 10 kΩ 10 kΩ N O R7 PCA9512A ED C 5.1 Ω VCC VCC2SDAOUT CARD2_SDA R SDAIN SCLOUT CARD2_SCL E G SCLIN ACC G C4 0.01 μF GND A T S I/O PERIPHERAL CARD N R POWER SUPPLY TO HOT SWAP C5 EC 0.01 μF R12 R13 R14 N 10 kΩ 10 kΩ 10 kΩ N O R11 PCA9512A ED C 5.1 Ω VCC VCC2SDAOUT CARDN_SDA R SDAIN SCLOUT CARDN_SCL E G SCLIN ACC G C6 0.01 μF GND A T S 002aab791 Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure5 and Figure6. Fig 7. Hot swapping multiple I/O cards into a backplane using the PCA9512A in a cPCI, VME, and AdvancedTCA system PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 10 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer BACKPLANE CONNECTOR BACKPLANE I/O PERIPHERAL CARD 1 R VCC2 TO C1 EC 0.01 μF R4 R5 R6 N 10 kΩ 10 kΩ 10 kΩ N O R3 PCA9512A VCC ED C 5.1 Ω VCC VCC2SDAOUT CARD1_SDA SDA R SDAIN SCLOUT CARD1_SCL E SCL G SCLIN ACC G C2 0.01 μF GND A T S R1 R2 10 kΩ 10 kΩ I/O PERIPHERAL CARD 2 R O T C3 EC 0.01 μF R8 R9 R10 N 10 kΩ 10 kΩ 10 kΩ N O R7 PCA9512A ED C 5.1 Ω VCC VCC2SDAOUT CARD2_SDA R SDAIN SCLOUT CARD2_SCL E G SCLIN ACC G C4 0.01 μF GND A T S 002aab792 Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure5 and Figure6. Fig 8. Hot swapping multiple I/O cards into a backplane using the PCA9512A with a custom connector VCC (5 V) CARD_VCC (3 V) C2 C1 R1 R4 0.01 μF 0.01 μF R3 R2 10 kΩ 10 kΩ 10 kΩ 10 kΩ VCC VCC2 SDA SDAIN SDAOUT CARD_SDA SCL SCLIN SCLOUT CARD_SCL PCA9512A ACC GND 002aab793 Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure5 and Figure6. Fig 9. 5V to 3.3V level translator and bus buffer PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 11 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 8.9 Voltage level translator discussion 8.9.1 Summary There are two popular configurations for the interface of low voltage logic (i.e., core processor with 3.3V supply) to standard bus levels (i.e., I2C-bus with 5V supply). A single FET transistor and two additional resistors may be used effectively, or an application-specific IC part requiring no external components and no additional resistors. The FET solution becomes problematic as the low voltage logic levels trend downwards. The FET solution will stop working completely when the FET specification is no longer matched to the LOW level logic supply voltage requirements. The dominant advantage of the FET solution is cost, but the IC part provides additional advantages to the design, which increases reliability to the end user. 8.9.2 Why do level translation? Advances in processing technology require lower supply voltages, due to reduced clearances in the fabrication technology. Lower supply voltages drive down signal swings, or require that on die high voltage I/O sections are added, creating larger die area, or greater I/O pin count. Existing standards for interoperability of equipment connected by cables or between subsystems require higher voltage signal swings (typically 5V). An external voltage level translator solves these problems, but requires additional parts. 8.10 Limitations of the FET voltage level translator 8.10.1 V , gate-source threshold voltage GSth When the VA input is logic LOW, the FET is turned on, pulling VB output LOW. This can only occur when the threshold voltage of the FET is less than the VA supply voltage minus the maximum level of the VA signal, VAIL. Using CMOS logic thresholds of 0.3and 0.7times the supply, and a 1.1V VA gives a worst-case of just 330mV, much less than V of the popular 2N7002 FET. GSth V ; I = 250A; V =V ; 1.1V (min.)/1.6V (typ.)/2.1V (max.) GSth D DS GS Additionally, the FET threshold voltage is specified in the linear region of the FET, with weak conduction. Ideally the FET should have very low ON-resistance. For the 2N7002, this is specified at 5V V (not the 1V available in this application). Note that the GS ON-resistance decreases rapidly as V is increased beyond the V specification. GS GSth Unintended operation in the linear region further compromises logic level noise immunity. 8.10.2 FET body diode voltage The FET is required to conduct in both directions, as the I2C-bus is bidirectional. When the VB input is logicLOW, the body diode of the FET conducts first, pulling the FET source LOW along with the FET drain, until the FET conducts. During this transition the forward voltage drop of the body diode reduces the available FET gain to source bias. The body diode is specified: V , source-drain voltage; I =115mA; V =0V; 0.47V (min.)/0.75V (typ.)/1.1V SD S GS (max.) Conduction of the FET body diode impacts both the delay time and logic transition speed. PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 12 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 8.11 Additional system compromises • Additional parts • Additional assembly cost • Reduced system reliability due to complexity • Reduced logic level noise margin (immunity) • Sensitivity to ground offsets between sub-systems (cable links, for example) • Increased loading on the low voltage side (must carry the high voltage side sinkcurrent) • ESD robustness 9. Application design-in information VCC CARD_VCC (3 V) (5 V) C2 C1 R1 R2 0.01 μF 0.01 μF R3 R4 R5 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ VCC VCC2 SDAIN SDAOUT SDA CARD_SDA SCLIN SCLOUT SCL CARD_SCL PCA9512A ACC GND 002aab794 Fig 10. Typical application PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 13 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 10. Limiting values Table 5. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +7 V CC V supply voltage 2[1] 0.5 +7 V CC2 V voltage on any other pin 0.5 +7 V n I input current [2] - 20 mA I I input/output current [3] - 50 mA I/O T operating temperature 40 +85 C oper T storage temperature 65 +125 C stg T solder point temperature 10s maximum - 300 C sp T maximum junction temperature - 125 C j(max) [1] Card side supply voltage. [2] Maximum current for inputs. [3] Maximum current for I/O pins. 11. Characteristics Table 6. Characterist ics V = 2.7V to 5.5V; T =40C to +85C; unless otherwise specified. CC amb Symbol Parameter Conditions Min Typ Max Unit Power supply V supply voltage [1] 2.7 - 5.5 V CC V supply voltage 2[2] [1] 2.7 - 5.5 V CC2 I supply current V =5.5V; - 1.8 3.6 mA CC CC V =V =0V SDAIN SCLIN I supply current 2 V =5.5V; - 1.7 2.9 mA CC2 CC V =V =0V SDAOUT SCLOUT Start-up circuitry V precharge voltage SDA, SCL floating [1] 0.8 1.1 1.2 V pch t enable time on power-up [3] - 180 - s en t idle time [1][4] 50 140 250 s idle Rise time accelerators I transient boosted pull-up positive transition on SDA, SCL; [5][6] 1 2 - mA trt(pu) current V =0.7V ; V =2.7V; ACC CC2 CC slewrate=1.25V/s V disable threshold voltage 0.3V 0.5V - V th(dis)(ACC) CC2 CC2 onpin ACC V enable threshold voltage - 0.5V 0.7V V th(en)(ACC) CC2 CC2 onpin ACC I input current on pin ACC 1 0.1 +1 A I(ACC) t on/off propagation delay - 5 - ns PD(on/off)(ACC) onpin ACC PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 14 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer Table 6. Characteristics …continued V = 2.7V to 5.5V; T =40C to +85C; unless otherwise specified. CC amb Symbol Parameter Conditions Min Typ Max Unit Input-output connection V offset voltage 10k to V on SDA, SCL; [1][7] 0 115 175 mV offset CC V =3.3V; V =3.3V; CC CC2 V =0.2V I C input capacitance digital; guaranteed by design, - - 10 pF i not subject to test V LOW-level output voltage V =0V; SDAn, SCLn pins; [1] 0 0.3 0.4 V OL I I =3mA; V =2.7V; sink CC V =2.7V CC2 I input leakage current SDAn, SCLn pins; V =5.5V; 1 - +1 A LI CC V =5.5V CC2 System characteristics f SCL clock frequency [8] 0 - 400 kHz SCL t bus free time between a [8] 1.3 - - s BUF STOP and START condition t hold time (repeated) [8] 0.6 - - s HD;STA START condition t set-up time for a repeated [8] 0.6 - - s SU;STA START condition t set-up time for STOP [8] 0.6 - - s SU;STO condition t data hold time [8] 300 - - ns HD;DAT t data set-up time [8] 100 - - ns SU;DAT t LOW period of the SCL [8] 1.3 - - s LOW clock t HIGH period of the SCL [8] 0.6 - - s HIGH clock t fall time of both SDA and [8][9] 20+0.1C - 300 ns f b SCL signals t rise time of both SDA and [8][9] 20+0.1C - 300 ns r b SCL signals [1] This specification applies over the full operating temperature range. [2] Card side supply voltage. [3] The enable time is from power-up of VCC and VCC22.7V to when idle or stop time begins. [4] Idle time is from when SDAn and SCLn are HIGH after enable time has been met. [5] I varies with temperature and V voltage, as shown in Section 11.1 “Typical performance characteristics”. trt(pu) CC [6] Input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage to the positive supply rail. [7] The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pull-up resistor and V voltage is shown in Section 11.1 “Typical performance characteristics”. CC [8] Guaranteed by design, not production tested. [9] C = total capacitance of one bus line in pF. b PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 15 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 11.1 Typical performance characteristics 002aab795 002aab796 2.15 12 ICC (mA) VCC = 5.5 V I(trmt(pAu)) 3.3 V 1.95 2.7 V VCC = 5 V 8 1.75 4 3.3 V 1.55 2.7 V 1.35 0 −40 +25 +90 −40 +25 +90 Tamb (°C) Tamb (°C) I (pin 1) typical current averages 0.1mA less than I CC2 CC on pin 8. Fig 11. I versus temperature Fig 12. I versus temperature CC trt(pu) 002aab589 002aab591 90 350 VCC = 5.5 V tPHL VO − VI (ns) (mV) 80 250 2.7 V 3.3 V 70 150 VCC = 5 V 3.3 V 60 50 −40 +25 +90 0 10 20 30 40 Tamb (°C) RPU (kΩ) Ci=Co>100pF; RPU(in)=RPU(out)=10k VCC=3.3V or 5.5V Fig 13. Input/output t versus temperature Fig 14. Connection circuitry V V PHL O I PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 16 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 12. Test information VCC VCC RL 10 kΩ VI VO PULSE DUT GENERATOR RT 1C0L0 pF 002aab595 R = load resistor L CL = load capacitance includes jig and probe capacitance R = termination resistance should be equal to the output impedance Z of the pulse generator T o Fig 15. Test circuitry for switching times PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 17 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 13. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 8 5 Q A2 A1 (A 3 ) A pin 1 index θ Lp 1 4 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 5.0 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 4.8 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.20 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.19 0.15 0.228 0.016 0.024 0.012 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT96-1 076E03 MS-012 03-02-18 Fig 16. Package outline SOT96-1 (SO8) PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 18 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 D E A X c y HE v M A Z 8 5 A2 A1 (A3) A pin 1 index θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.95 0.25 0.45 0.28 3.1 3.1 0.65 5.1 0.94 0.7 0.1 0.1 0.1 0.70 6° 0.05 0.80 0.25 0.15 2.9 2.9 4.7 0.4 0.35 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-04-09 SOT505-1 03-02-18 Fig 17. Package outline SOT505-1 (TSSOP8) PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 19 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 20 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure18) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table7 and8 Table 7. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 8. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure18. PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 21 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 18. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Soldering: PCB footprints 5.50 0.60 (8×) 1.30 4.00 6.60 7.00 1.27 (6×) solder lands occupied area placement accuracy ± 0.25 Dimensions in mm sot096-1_fr Fig 19. PCB footprint for SOT96-1 (SO8); reflow soldering PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 22 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 1.20 (2×) 0.60 (6×) 0.3 (2×) enlarged solder land 1.30 4.00 6.60 7.00 1.27 (6×) 5.50 board direction solder lands solder resist occupied area placement accurracy ± 0.25 Dimensions in mm sot096-1_fw Fig 20. PCB footprint for SOT96-1 (SO8); wave soldering 3.600 2.950 0.725 0.125 0.125 5.750 3.600 3.200 5.500 1.150 0.600 0.450 0.650 solder lands occupied area Dimensions in mm sot505-1_fr Fig 21. PCB footprint for SOT505-1 (TSSOP8); reflow soldering PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 23 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 16. Abbreviations Table 9. Abbreviations Acronym Description AdvancedTCA Advanced Telecommunications Computing Architecture AVL Approved Vendor List CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor cPCI compact Peripheral Component Interface ESD Electrostatic Discharge FET Field-Effect Transistor HBM Human Body Model I2C-bus Inter-Integrated Circuit bus IC Integrated Circuit PCI Peripheral Component Interface PICMG PCI Industrial Computer Manufacturers Group SMBus System Management Bus VME VERSAModule Eurocard 17. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9512A_PCA9512B v.6 20130301 Product data sheet - PCA9512A_PCA9512B v.5 Modifications: • Section 1 “General description”: second paragraph re-written • Section 2 “Features and benefits”: 11th bullet item: deleted “200V MM per JESD22-A115” • Added Section 5.1 “Ordering options” • Figure 1 “Block diagram of PCA9512A/B”: added “LEVEL SHIFTER” block • Section 8 “Functional description”: added (new) second paragraph • Figure 10 “Typical application”: changed type number from “PCA9512A/B” to “PCA9512A” • Added Section 8.9 “Voltage level translator discussion” • Added Section 8.10 “Limitations of the FET voltage level translator” • Added Section 8.11 “Additional system compromises” • Added Section 15 “Soldering: PCB footprints” PCA9512A_PCA9512B v.5 20110105 Product data sheet - PCA9512A v.4 PCA9512A v.4 20090819 Product data sheet - PCA9512A v.3 PCA9512A v.3 20090720 Product data sheet - PCA9512A v.2 PCA9512A v.2 20090528 Product data sheet - PCA9512A v.1 PCA9512A v.1 20051007 Product data sheet - - PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 24 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 25 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer Export control — This document as well as the item(s) described herein own risk, and (c) customer fully indemnifies NXP Semiconductors for any may be subject to export control regulations. Export might require a prior liability, damages or failed product claims resulting from customer design and authorization from competent authorities. use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, Translations — A non-English (translated) version of a document is for the product is not suitable for automotive use. It is neither qualified nor tested reference only. The English version shall prevail in case of any discrepancy in accordance with automotive testing or application requirements. NXP between the translated and English versions. Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 18.4 Trademarks In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks (a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners. product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP B.V. NXP Semiconductors’ specifications such use shall be solely at customer’s 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9512A_PCA9512B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 — 1 March 2013 26 of 27

PCA9512A; PCA9512B NXP Semiconductors Level shifting hot swappable I2C-bus and SMBus bus buffer 20. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 25 18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 19 Contact information . . . . . . . . . . . . . . . . . . . . 26 4 Feature selection. . . . . . . . . . . . . . . . . . . . . . . . 2 20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 5 8.1 Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 Connect circuitry. . . . . . . . . . . . . . . . . . . . . . . . 6 8.3 Maximum number of devices in series. . . . . . . 6 8.4 Propagation delays. . . . . . . . . . . . . . . . . . . . . . 8 8.5 Rise time accelerators . . . . . . . . . . . . . . . . . . . 8 8.6 ACC boost current enable . . . . . . . . . . . . . . . . 8 8.7 Resistor pull-up value selection . . . . . . . . . . . . 8 8.8 Hot swapping and capacitance buffering application . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.9 Voltage level translator discussion . . . . . . . . . 12 8.9.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.9.2 Why do level translation?. . . . . . . . . . . . . . . . 12 8.10 Limitations of the FET voltage level translator . . . . . . . . . . . . . . . . . . . . . . . . 12 8.10.1 V , gate-source threshold voltage . . . . . . . 12 GSth 8.10.2 FET body diode voltage . . . . . . . . . . . . . . . . . 12 8.11 Additional system compromises. . . . . . . . . . . 13 9 Application design-in information . . . . . . . . . 13 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 11 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 14 11.1 Typical performance characteristics. . . . . . . . 16 12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 17 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 18 14 Soldering of SMD packages . . . . . . . . . . . . . . 20 14.1 Introduction to soldering. . . . . . . . . . . . . . . . . 20 14.2 Wave and reflow soldering. . . . . . . . . . . . . . . 20 14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 20 14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 21 15 Soldering: PCB footprints. . . . . . . . . . . . . . . . 22 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24 17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 March 2013 Document identifier: PCA9512A_PCA9512B