PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 11 January 2013 Product data sheet 1. General description NPN/NPN low V Breakthrough In Small Signal (BISS) transistor in a leadless CEsat medium power DFN2020-6 (SOT1118) Surface-Mounted Device (SMD) plastic package. NPN/PNP complement: PBSS4130PANP. PNP/PNP complement: PBSS5130PAP. 2. Features and benefits • Very low collector-emitter saturation voltage V CEsat • High collector current capability I and I C CM • High collector current gain h at high I FE C • Reduced Printed-Circuit Board (PCB) requirements • High energy efficiency due to less heat generation • AEC-Q101 qualified 3. Applications • Load switch • Battery-driven devices • Power management • Charging circuits • Power switches (e.g. motors, fans) 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per transistor V collector-emitter open base - - 30 V CEO voltage I collector current - - 1 A C I peak collector current single pulse; t ≤ 1 ms - - 2 A CM p Per transistor R collector-emitter I = 1 A; I = 0.1 A; pulsed; t ≤ 300 µs; - - 190 mΩ CEsat C B p saturation resistance δ ≤ 0.02 ; T = 25 °C amb

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 E1 emitter TR1 6 5 4 C1 B2 E2 2 B1 base TR1 TR2 3 C2 collector TR2 7 8 TR1 4 E2 emitter TR2 1 2 3 E1 B1 C2 5 B2 base TR2 Transparenttopview sym140 6 C1 collector TR1 DFN2020-6 (SOT1118) 7 C1 collector TR1 8 C2 collector TR2 6. Ordering information Table 3. Ordering information Type number Package Name Description Version PBSS4130PAN DFN2020-6 plastic thermal enhanced ultra thin small outline package; no SOT1118 leads; 6 terminals; body 2 x 2 x 0.65 mm 7. Marking Table 4. Marking codes Type number Marking code PBSS4130PAN 2D 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor V collector-base voltage open emitter - 30 V CBO V collector-emitter voltage open base - 30 V CEO V emitter-base voltage open collector - 7 V EBO I collector current - 1 A C I peak collector current single pulse; t ≤ 1 ms - 2 A CM p I base current - 0.3 A B PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 2 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor Symbol Parameter Conditions Min Max Unit I peak base current single pulse; t ≤ 1 ms - 1 A BM p Ptot total power dissipation Tamb ≤ 25 °C [1] - 370 mW [2] - 570 mW [3] - 530 mW [4] - 700 mW [5] - 450 mW [6] - 760 mW [7] - 700 mW [8] - 1450 mW Per device Ptot total power dissipation Tamb ≤ 25 °C [1] - 510 mW [2] - 780 mW [3] - 730 mW [4] - 960 mW [5] - 620 mW [6] - 1040 mW [7] - 960 mW [8] - 2000 mW T junction temperature - 150 °C j T ambient temperature -55 150 °C amb T storage temperature -65 150 °C stg [1] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [3] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint. [4] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [5] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint. [6] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [7] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint. [8] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 3 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 006aad165 1.5 (1) Ptot (W) 1.0 (2) (3)(4) (5) 0.5 (6) (7) (8) 0 -75 -25 25 75 125 175 Tamb (°C) 2 (1) 4-layer PCB 70 µm, mounting pad for collector 1 cm 2 (2) FR4 PCB 70 µm, mounting pad for collector 1 cm (3) 4-layer PCB 70 µm, standard footprint 2 (4) 4-layer PCB 35 µm, mounting pad for collector 1 cm 2 (5) FR4 PCB 35 µm, mounting pad for collector 1 cm (6) 4-layer PCB 35 µm, standard footprint (7) FR4 PCB 70 µm, standard footprint (8) FR4 PCB 35 µm, standard footprint Fig. 1. Per transistor: power derating curves 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Per transistor Rth(j-a) thermal resistance in free air [1] - - 338 K/W from junction to [2] - - 219 K/W ambient [3] - - 236 K/W [4] - - 179 K/W [5] - - 278 K/W [6] - - 164 K/W [7] - - 179 K/W [8] - - 86 K/W R thermal resistance - - 30 K/W th(j-sp) from junction to solder point PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 4 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor Symbol Parameter Conditions Min Typ Max Unit Per device Rth(j-a) thermal resistance in free air [1] - - 245 K/W from junction to [2] - - 160 K/W ambient [3] - - 171 K/W [4] - - 130 K/W [5] - - 202 K/W [6] - - 120 K/W [7] - - 130 K/W [8] - - 63 K/W [1] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [3] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint. [4] Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [5] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint. [6] Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. [7] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint. [8] Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm2. 103 006aad166 Zth(j-a) duty cycle = 1 (K/W) 0.75 0.5 102 0.33 0.2 0.1 0.05 10 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) FR4 PCB 35 µm, standard footprint Fig. 2. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 5 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 103 006aad167 Zth(j-a) (K/W) duty cycle = 1 0.75 102 0.5 0.33 0.2 0.1 0.05 10 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) 2 FR4 PCB 35 µm, mounting pad for collector 1 cm Fig. 3. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values 103 006aad168 Zth(j-a) (K/W) duty cycle = 1 0.75 102 0.5 0.33 0.2 0.1 0.05 10 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) 4-layer PCB 35 µm, standard footprint Fig. 4. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 6 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 103 006aad169 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.5 0.33 0.2 0.1 10 0.05 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) 2 4-layer PCB 35 µm, mounting pad for collector 1 cm Fig. 5. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values 103 006aac610 Zth(j-a) (K/W) duty cycle = 1 0.75 102 0.5 0.33 0.2 0.1 0.05 10 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) FR4 PCB 70 µm, standard footprint Fig. 6. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 7 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 103 006aac611 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.5 0.33 0.2 0.1 10 0.05 0.02 0 0.01 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) 2 FR4 PCB 70 µm, mounting pad for collector 1 cm Fig. 7. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values 103 006aad170 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.5 0.33 0.2 0.1 10 0.05 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) 4-layer PCB 70 µm, standard footprint Fig. 8. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 8 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 102 006aad171 duty cycle = 1 0.75 Zth(j-a) 0.5 (K/W) 0.33 0.2 10 0.1 0.05 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) 2 4-layer PCB 70 µm, mounting pad for collector 1 cm Fig. 9. Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration; typical values 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit Per transistor I collector-base cut-off V = 24 V; I = 0 A; T = 25 °C - - 100 nA CBO CB E amb current V = 24 V; I = 0 A; T = 150 °C - - 50 µA CB E j I emitter-base cut-off V = 5 V; I = 0 A; T = 25 °C - - 100 nA EBO EB C amb current h DC current gain V = 2 V; I = 100 mA; pulsed; 240 370 - FE CE C t ≤ 300 µs; δ ≤ 0.02 ; T = 25 °C p amb V = 2 V; I = 500 mA; pulsed; 210 320 - CE C t ≤ 300 µs; δ ≤ 0.02 ; T = 25 °C p amb V = 2 V; I = 1 A; pulsed; t ≤ 300 µs; 180 270 - CE C p δ ≤ 0.02 ; T = 25 °C amb V collector-emitter I = 500 mA; I = 50 mA; T = 25 °C - 75 100 mV CEsat C B amb saturation voltage I = 1 A; I = 50 mA; pulsed; - 155 200 mV C B t ≤ 300 µs; δ ≤ 0.02 ; T = 25 °C p amb I = 1 A; I = 100 mA; pulsed; - 150 190 mV C B t ≤ 300 µs; δ ≤ 0.02 ; T = 25 °C p amb R collector-emitter I = 1 A; I = 0.1 A; pulsed; t ≤ 300 µs; - - 190 mΩ CEsat C B p saturation resistance δ ≤ 0.02 ; T = 25 °C amb PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 9 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor Symbol Parameter Conditions Min Typ Max Unit V base-emitter saturation I = 500 mA; I = 50 mA; T = 25 °C - - 1 V BEsat C B amb voltage I = 1 A; I = 50 mA; pulsed; - - 1.1 V C B t ≤ 300 µs; δ ≤ 0.02 ; T = 25 °C p amb I = 1 A; I = 100 mA; pulsed; - - 1.1 V C B t ≤ 300 µs; δ ≤ 0.02 ; T = 25 °C p amb V base-emitter turn-on V = 2 V; I = 0.5 A; pulsed; - - 0.9 V BEon CE C voltage t ≤ 300 µs; δ ≤ 0.02 ; T = 25 °C p amb t delay time V = 10 V; I = 500 mA; I = 25 mA; - 15 - ns d CC C Bon I = -25 mA; T = 25 °C t rise time Boff amb - 30 - ns r t turn-on time - 45 - ns on t storage time - 310 - ns s t fall time - 55 - ns f t turn-off time - 365 - ns off f transition frequency V = 10 V; I = 50 mA; f = 100 MHz; 90 165 - MHz T CE C T = 25 °C amb C collector capacitance V = 10 V; I = 0 A; i = 0 A; - 7.5 10 pF c CB E e f = 1 MHz; T = 25 °C amb 006aad172 006aad173 600 2.0 IC IB= 10 mA 9 8 hFE (1) (A) 7 1.6 6 400 5 (2) 1.2 4 3 0.8 2 200 (3) 0.4 1 0 0 10-1 1 10 102 103 104 0 1 2 3 4 5 IC (mA) VCE (V) V = 2 V T = 25 °C CE amb (1) T = 100 °C amb Fig. 11. Collector current as a function of collector- (2) T = 25 °C amb emitter voltage; typical values (3) T = −55 °C amb Fig. 10. DC current gain as a function of collector current; typical values PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 10 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 006aad174 006aad175 1.2 1.2 VBEsat VBE (V) (V) 1.0 (1) 0.8 (1) 0.8 (2) (2) (3) 0.6 (3) 0.4 0.4 0 0.2 10-1 1 10 102 103 104 10-1 1 10 102 103 104 IC (mA) IC (mA) V = 2 V I /I = 20 CE C B (1) T = −55 °C (1) T = −55 °C amb amb (2) T = 25 °C (2) T = 25 °C amb amb (3) T = 100 °C (3) T = 100 °C amb amb Fig. 12. Base-emitter voltage as a function of collector Fig. 13. Base-emitter saturation voltage as a function of current; typical values collector current; typical values 006aad176 006aad177 1 1 VCEsat VCEsat (V) (V) 10-1 10-1 (1) (1) (2) (2) 10-2 10-2 (3) (3) 10-3 10-3 10-1 1 10 102 103 104 10-1 1 10 102 103 104 IC (mA) IC (mA) I /I = 20 T = 25 °C C B amb (1) T = 100 °C (1) I /I = 100 amb C B (2) T = 25 °C (2) I /I = 50 amb C B (3) T = −55 °C (3) I /I = 10 amb C B Fig. 14. Collector-emitter saturation voltage as a Fig. 15. Collector-emitter saturation voltage as a function of collector current; typical values function of collector current; typical values PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 11 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 103 006aad178 103 006aad179 RCEsat RC(ΩE)sat (Ω) (1) 102 102 (2) 10 10 (3) 1 1 (1) 10-1 (2) (3) 10-1 10-2 10-1 1 10 102 103 104 10-1 1 10 102 103 104 IC (mA) IC (mA) I /I = 20 T = 25 °C C B amb (1) T = 100 °C (1) I /I = 100 amb C B (2) T = 25 °C (2) I /I = 50 amb C B (3) T = −55 °C (3) I /I = 10 amb C B Fig. 16. Collector-emitter saturation resistance as a Fig. 17. Collector-emitter saturation resistance as a function of collector current; typical values function of collector current; typical values PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 12 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 11. Test information IB 90% inputpulse (idealizedwaveform) IBon(100%) 10% IBoff outputpulse IC (idealizedwaveform) 90% IC(100%) 10% t td tr ts tf ton toff 006aaa003 Fig. 18. BISS transistor switching time definition VBB VCC RB RC (probe) Vo (probe) oscilloscope oscilloscope 450Ω 450Ω R2 VI DUT R1 mlb826 Fig. 19. Test circuit for switching times 11.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 13 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 12. Package outline 2.1 0.65 1.9 max 1.1 0.04 0.9 max 0.77 0.57 3 4 0.65 (2×) 2.1 (4×) 1.9 0.54 0.44 0.35 (2×) 1 6 0.25 (6×) 0.3 0.2 Dimensionsinmm 10-05-31 Fig. 20. Package outline DFN2020-6 (SOT1118) 13. Soldering 2.1 0.65 0.65 0.49 0.49 0.3 0.4 (6×) (6×) solderlands 0.875 solderpaste 1.05 1.15 2.25 (2×) (2×) solderresist 0.875 occupiedarea Dimensionsinmm 0.35 0.72 (6×) (2×) 0.45 0.82 (6×) (2×) sot1118_fr Fig. 21. Reflow soldering footprint for DFN2020-6 (SOT1118) 14. Revision history Table 8. Revision history Data sheet ID Release date Data sheet status Change notice Supersedes PBSS4130PAN v.1 20130111 Product data sheet - - PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 14 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - 15. Legal information lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 15.1 Data sheet status Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance Document Product Definition with the Terms and conditions of commercial sale of Nexperia. status [1][2] status [3] Objective Development This document contains data from Right to make changes — Nexperia reserves the right to [short] data the objective specification for product make changes to information published in this document, including without sheet development. limitation specifications and product descriptions, at any time and without Preliminary Qualification This document contains data from the notice. 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In no event however, the Absolute Maximum Ratings System of IEC 60134) will cause permanent shall an agreement be valid in which the Nexperia product damage to the device. Limiting values are stress ratings only and (proper) is deemed to offer functions and qualities beyond those described in the operation of the device at these or any other conditions above those Product data sheet. given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 15.3 Disclaimers Terms and conditions of commercial sale — Nexperia Limited warranty and liability — Information in this document is believed products are sold subject to the general terms and conditions of commercial to be accurate and reliable. However, Nexperia does not give sale, as published at http://www.nexperia.com/profile/terms, unless otherwise any representations or warranties, expressed or implied, as to the accuracy agreed in a valid written individual agreement. In case an individual or completeness of such information and shall have no liability for the agreement is concluded only the terms and conditions of the respective consequences of use of such information. Nexperia takes no agreement shall apply. Nexperia hereby expressly objects to responsibility for the content in this document if provided by an information applying the customer’s general terms and conditions with regard to the source outside of Nexperia. purchase of Nexperia products by customer. PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 15 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 16 / 17

Nexperia PBSS4130PAN 30 V, 1 A NPN/NPN low VCEsat (BISS) transistor 16. Contents 1 General description ...............................................1 2 Features and benefits ............................................1 3 Applications ...........................................................1 4 Quick reference data .............................................1 5 Pinning information ...............................................2 6 Ordering information .............................................2 7 Marking ...................................................................2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics .......................................................9 11 Test information ...................................................13 11.1 Quality information ......................................... 12 Package outline ...................................................14 13 Soldering ..............................................................14 14 Revision history ...................................................14 15 Legal information .................................................15 15.1 Data sheet status ...............................................15 15.2 Definitions ...........................................................15 15.3 Disclaimers .........................................................15 15.4 Trademarks ........................................................16 © Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 11 January 2013 PBSS4130PAN All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 11 January 2013 17 / 17