QorIQ Communications Platforms P1 Series P1013/P1022 embedded processors with advanced energy management Freescale QorIQ communications platforms the same family of system peripherals, High-Speed Connectivity are the next-generation evolution of our interconnect technology and advanced power Freescale’s P1022 processor is positioned to leading PowerQUICC communications and energy management features. offer a wide range of high-speed connectivity processors. The P1022 family of processors, options. The flexibility of the processor is a Freescale Energy-Efficient product solution, Highlights due to highly integrated speed- and latency- is designed to deliver complex application optimized technology. It is a highly scalable Dual-Core Processing processing performance with exceptional processor designed to handle complex, The pace of technology development, spurred feature integration and high-speed connectivity computationally demanding processing tasks by the Internet and ubiquitous connectivity, for IP networking and advanced media with ease. The P1022 processor includes is putting additional challenges on design processing applications. It combines dual e500 virtualized enhanced three-speed Ethernet engineers building state-of-the-art embedded processor cores, built on Power Architecture® with TCP/UDP/IP offload, direct FIFO mode appliances or equipment. The P1022 technology, with enhanced system peripherals for ASIC connectivity, SATA for local storage provides the designer exceptional flexibility and interconnect technology to balance and support for three PCI Express® interface for leveraging symmetric and asymmetric processor performance with I/O system options. Moreover, the P1022 processor multiprocessing strategies to reach nearly two throughput. The P1022 processor includes features a field-proven, next-generation gigahertz equivalent single-core performance advanced power and energy management memory controller and an optional hardware in ultra-low-power envelopes. Equally features that enable developers to design acceleration engine for encryption protocols important are the robust operating systems next-generation embedded Internet media and RAID processing. and tool support to streamline designers’ processing applications with energy adoption of dual-core processing available on efficiency levels under the environmental and the P1022 through Freescale and Freescale governmental energy regulatory requirements. partners. The P1013 single-core processor includes QorIQ P1022 and P1013 Block Diagram Not on P1013 Security Power Architecture® Power Architecture DDR2/DDR3 Acceleration e500 Core 256 KB e500 Core SDRAM Controller L2 Cache XOR 32 KB 32 KB 32 KB 32 KB L1 I-Cache L1 D-Cache L1 I-Cache L1 D-Cache DUART, 2 x I2C, Timers, Interrupt Control, Advanced SD/MMC, SPI, Power 2 x USB 2.0/ULPI, MPIC Management Coherency Module Enhanced Local Bus System Bus Controller (eLBC) LCD TDM/ 2 x 2 x OOnn--CChhiipp NNeettwwoorrkk Gigabit (DIU) I2S SATA Ethernet 3 x PCI Express® 22--cchh.. DDMMAA CCoonnttrroolllleerr x2 SerDes 4-lane SerDes RGMII (PCI Express/ (PCI Express/ SATA/SGMII) SGMII) Cores

System-Level Cost Saving Key Features • Audio visual interfaces The P1022 processor’s highly integrated • Dual (P1022) or single (P1013) high- LCD interface supporting a display of architecture is designed to enhance performance e500v2 cores built on Power 1280 x 1024P @ 60 Hz, 24 bits per pixel performance and deliver system-level cost Architecture technology I2S interface with maximum sampling savings in a small board footprint. Key 36-bit physical addressing frequency of 192 kHz system-level peripherals include dual Gigabit Ethernet, dual USB 2.0, dual SATA, SD/ Double precision floating point support • VoIP TDM interface MMC and triple PCI Express interconnects. Signal processing engine (SPE) APU Support for up to 128 channels Furthermore, the P1022 integrates LCD (auxiliary processing unit) • Two High-Speed USB controllers (USB 2.0) controller, I2S audio and VoIP TDM interfaces 32 KB L1 instruction cache and 32 KB L1 Host and device support for use in creating engaging human interfaces. data cache for each core Special care was taken to design the P1022 Enhanced host controller interface (EHCI) processor’s pin locations for mounting on 600 MHz to 1055 MHz core ULPI interface to PHY low-cost six layer PCBs. The P1022 is a clock frequency • Enhanced secure digital host controller full-featured, high-performance gigahertz • 256 KB L2 cache with ECC, also (SD/MMC) processor that is designed to support fanless configurable as SRAM and stashing • Serial peripheral interface operation for power-sensitive applications. memory • Programmable interrupt controller (PIC) Advanced Energy-Efficient Modes • 64-bit DDR2/DDR3 SDRAM memory compliant with Open-PIC standard Balancing the performance requirements controller with ECC support • Dual four-channel DMA controllers for powerful new networking- and Internet- • Two 10/100/1000 Mbps virtualized centric applications, with the increasing enhanced three-speed Ethernet controllers • Dual I2C controllers, DUART, timers concerns over energy consumption, is driving • Enhanced local bus controller (eLBC) (eTSECs) manufacturers to develop intelligent strategies • Advanced power and energy management TCP/IP acceleration and classification for optimizing performance within specific capabilities Low power operation energy budgets. This is a key challenge for the next-generation green embedded IEEE® 1588 support Support for dynamic and static power systems. The P1022 processor implements Loseless flow control management sophisticated power-saving modes for Doze, nap and sleep modes for dynamic RMII, RGMII, SGMII managing energy consumption in both power management • Integrated security engine (optional) dynamic and static power modes. These Packet-lossless deep sleep: power include the traditional nap, doze plus the Crypto algorithm support includes 3DES, removed from major portion of the chip jog (dynamic frequency scaling) and packet- AES, RSA/ECC, MD5/SHA, ARC4, lossless deep-sleep modes. Designers may Kasumi, Snow 3G and FIPS deterministic PMC wake on: filtered LAN activity, leverage these modes to efficiently match RNG USB connection, GPIO, internal timer or work accomplished with the correct level of external interrupt event Single pass encryption/message energy consumed. • Up to 87 general-purpose signals authentication for common security The combination of these features makes protocols (IPsec, SSL, SRTP, WiMAX) • Available in extended temperature (optional) the P1022 processor an optimal embedded XOR acceleration • 689-pin TEPBGA package processing solution for Ethernet or PCI • High-speed interfaces (not all available Express interworking applications, such as simultaneously) enterprise networking, industrial, storage, Six SerDes lanes (multiplexed across security and office automation applications. controllers) Examples include control plane processing, protocol processing, media processing while One x4 and two x1 PCI Express producing an engaging human machine interfaces interface. Two serial ATA (SATA) interfaces Two SGMII interfaces Learn More: For current information about Freescale products and documentation, please visit freescale.com/QorIQ. Freescale, the Freescale logo and PowerQUICC are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. The Energy Efficient Solutions Logo, QorIQ and QUICC Engine are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2009, 2010, 2011 Freescale Semiconductor, Inc. Document Number: QP1022FS / REV 1