End of Life P048F048T24AL P048F048M24AL PRMTM Regulator (cid:129) 48 V input V(cid:129)I ChipTMPRM (cid:129)Adaptive Loop feedback © (cid:129) Vin range 36 – 75 Vdc (cid:129)ZVS buck-boost regulator (cid:129) High density – 813 W/in3 (cid:129)1.45 MHz switching frequency Vin = 36 – 75 V (cid:129)Small footprint – 215 W/in2 (cid:129)96% Efficiency Vf= 26 – 55 V Pf= 240 W (cid:129)Low weight – 0.5 oz (15 g) (cid:129)125˚C operation (Tj) If= 5 A Product Description Absolute Maximum Ratings The V(cid:129)I Chip regulator is a very efficient non-isolated Parameter Values Unit Notes regulator capable of both boosting and bucking a wide range input voltage. It is specifically designed to provide a controlled +In to -In -1.0 to 85.0 Vdc Factorized Bus distribution voltage for powering downstream PC to -In -0.3 to 6.0 Vdc VTMTMTransformer — fast, efficient, isolated, low noise PR to -In -0.3 to 9.0 Vdc Point-of-Load (POL) converters. In combination, PRMs and IL to -In -0.3 to 6.0 Vdc VTMsTMform a complete DC-DC converter subsystem VC to -In -0.3 to 18.0 Vdc offering all of the unique benefits of Vicor’s Factorized Power ArchitectureTM(FPA)TM: high density and efficiency; low noise +Out to -Out -0.3 to 59 Vdc operation; architectural flexibility; extremely fast transient SC to -Out -0.3 to 3.0 Vdc response; and elimination of bulk capacitance at the Point-of- VH to -Out -0.3 to 9.5 Vdc Load (POL). OS to -Out -0.3 to 9.0 Vdc In FPA systems, the POL voltage is the product of the CD to -Out -0.3 to 9.0 Vdc Factorized Bus voltage delivered by the PRM and the SG to -Out 100 mA "K-factor" (the fixed voltage transformation ratio) of a Continuous output current 5 Adc downstream VTM. The PRM controls the Factorized Bus Continuous output power 240 W voltage to provide regulation at the POL. Because VTMs perform true voltage division and current multiplication, 225 °C MSL 5 Case temperature during reflow the Factorized Bus voltage may be set to a value that is 245 °C MSL 6 substantially higher than the bus voltages typically found in -55 to 125 °C M-Grade "intermediate bus" systems, reducing distributionlossesand Operating junction temperature -40 to 125 °C T-Grade enabling use of narrower distribution bus traces. A PRM-VTM -65 to 125 °C M-Grade chip set can provide up to 100 A or 230 W ata FPA system Storage temperature -40 to 125 °C T-Grade density of 169 A/in3or 390 W/in3— and because the PRM can be located, or "factorized," remotelyfrom the POL, these power densities can be effectively doubled. DC-DC Converter The PRM described in this data sheet features a unique "Adaptive Loop" compensation feedback: a single wire alternative to traditional remote sensing and feedback loops that enables precise control of an isolated POL voltage VPCC VSHC Factorized +Out 0.01 µF TM SG +In wori tfhoor unto tihsee sneenesdit ifvoer, ebiathnedrw ai ddtihre lcimt citoinngn,e icstoiolant ioton tdheev ilcoeasd 10 kΩ IPNLRCPRMMo™du -lAeL ONCCDS RRCODS Bus (VF ) TM VTM™+Out OL in the feedback path. +In +Out 0.4 µH PVCC Modul–e Out A VIN 10 Ω K D –In –Out – In Ro– Out P048F048T24AL is used with 048 input series VTM to provide a regulated & isolated output. vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 1of 14

End of Life General Specifications V(cid:129)I Chip Regulator Part Numbering P 048 F 048 T 24 AL Input Voltage Configuration Nominal Product Grade Temperatures (°C) Output Power AL = Adaptive Loop Regulator Designator F = J-lead Factorized Bus Grade Storage Operating (TJ) Designator T = Through hole Voltage T -40 to125 -40 to125 (=Pf/10) M -65 to125 -55 to125 Overview of Adaptive Loop Compensation Adaptive Loop compensation, illustrated in Figure 1, contributes to the The V(cid:129)I Chip’s bi-directional VC port : bandwidth and speed advantage of Factorized Power. The PRM 1.Provides a wake up signal from the PRM to the VTM that monitors its output current and automatically adjusts its output voltage synchronizes the rise of the VTM output voltage to that of the PRM. to compensate for the voltage drop in the output resistance of the 2.Provides feedback from the VTM to the PRM to enable the PRM to VTM. R sets the desired value of the VTM output voltage, Vout; R OS CD compensate for the voltage drop in VTM output resistance, R . is set to a value that compensates for the output resistance of the VTM O (which, ideally, is located at the point of load). For selection of R and OS R , refer to Table 1 below or Page 9. CD VC VH PC SC Factorized +Out 0.01 µF TM SG +In 10 kΩ IPNLRC PRMMo™du -lAeL ONCCDS RRCODS Bus (VF ) TM VTM™+Out OL +In +Out 0.4 µH PVCC Module A – Out VIN 10 Ω K D –In –Out – In Ro – Out Figure 1 — With Adaptive Loop control, the output of the VTM is regulated over the load current range with only a single interconnect between the PRM and VTM and without the need for isolation in the feedback path. Desired Load Voltage (Vdc) VTM P/N(1) Max VTM Output Current (A)(2) ROS(kΩ) (3) RCD(Ω) (3) 1.0 V048F015T100 100 3.57 26.1 1.2 V048F015T100 100 2.94 32.4 1.5 V048F015T100 100 2.37 39.2 1.8 V048F020T080 80 2.61 35.7 2.0 V048F020T080 80 2.37 39.2 3.0 V048F030T070 70 2.37 39.2 3.3 V048F040T050 50 2.89 32.6 5.0 V048F060T040 40 2.87 33.2 8.0 V048F080T030 30 2.37 32.9 9.6 V048F096T025 25 2.37 32.9 10 V048F120T025 25 2.86 32.9 12 V048F120T025 25 2.37 39.2 15 V048F160T015 15 2.49 37.4 24 V048F240T012 12.5 2.37 39.2 28 V048F320T009 9.4 2.74 35.7 36 V048F480T006 6.3 3.16 30.1 48 V048F480T006 6.3 2.37 39.2 Note: (1) See Table 2 on page 9 for nominal Vout range and K factors. (2) See “PRM output power vs. VTM output power” on Page 10 (3) 1% precision resistors recommended Table 1 — Configure your Chip Set using the PRM-AL vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 2of 14

End of Life Electrical Specifications V(cid:129)I Chip Regulator Input Specs (Conditions are at 48 Vin, 48 Vf, full load, and 25°C ambient unless otherwise specified) Parameter Min Typ Max Unit Note Input voltage range 36 48 75 Vdc Input dV/dt 1 V/µs Input undervoltage turn-on 33.8 35.3 Vdc Input undervoltage turn-off 30.4 31.8 Vdc Input overvoltage turn-on 75.7 77.3 Vdc Input overvoltage turn-off 78.8 81.0 Vdc Input quiescent current 0.5 1 mA PC low Input current 5.2 Adc Input reflected ripple current 107 mA p-p See Figures 4 & 5 No load power dissipation 1.0 3.0 6.0 W Internal input capacitance 5 µF Ceramic Recommended external input capacitance 100 µF See Figure 5 for input filter circuit. Source impedance dependent Input Waveforms Figure 2— Vf and PC response from power up Figure 3— Vf turn-on waveform with inrush current – PC enabled VC VH PC SC Reflected 0.01 μF TM SG Ripple IL OS Measurement NC NC 2.37 kΩ 10 A 10 kΩ PRPRM-ALCD +IN + OUT +In +Out 100 μF Al-Electrolytic –IN –In –Out – OUT Figure 4— Input reflected ripple current Figure 5— Input filter capacitor recommendation vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 3of 14

End of Life Electrical Specifications (continued) V(cid:129)I Chip Regulator Output Specs (Conditions are at 48 Vin, 48 Vf, full load, and 25°C ambient unless otherwise specified) Parameter Min Typ Max Unit Note Output voltage range 26 48 55 Vdc Factorized Bus voltage (Vf) set by R OS Output power 0 240 W Output current 0 5 Adc DC current limit 5.25 6.0 6.6 Adc I pin floating L Average short circuit current 0.5 A Auto recovery Set point accuracy 1.5 % Line regulation 0.17 0.2 % Low line to high line Load regulation 0.5 0.7 % No CD resistor Load regulation (at VTM output) 1.0 2.0 % Adaptive Loop Current share accuracy 5 10 % Efficiency Full load 96 % See Figure 6,7 & 8 Output overvoltage set point 56 59.4 Vdc Output ripple voltage No external bypass 2.3 2.5 % Factorized Bus, see Figure 13 With 10 µF capacitor 0.35 1.1 % Factorized Bus, see Figure 14 Switching frequency 1.35 1.45 1.55 MHz Fixed frequency Output turn-on delay From application of power 135 300 ms See Figure 2 From PC pin high 100 µs See Figure 3 Internal output capacitance 5 µF Ceramic Factorized Bus capacitance 47 µF vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 4of 14

End of Life Electrical Specifications (continued) V(cid:129)I Chip Regulator Efficiency Graphs Efficiency vs. Output Current Efficiency vs. Output Current 98 98 96 96 94 94 %) 92 %) 92 y ( 90 Vin y ( 90 Vin enc 88 4386 VV enc 88 4386 VV Effici 8846 75 V Effici 8846 75 V 82 82 80 80 78 78 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Current (A) Output Current (A) Figure 6— Efficiency vs. output current at 48 Vf Figure 7 — Efficiency vs. output current at 36 Vf Efficiency vs. Output Current 98 96 94 %) 92 y ( 90 Vin nc 88 36 V e 48 V ci 86 75 V Effi 84 82 80 78 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Current (A) Figure 8— Efficiency vs. output current at 26 Vf vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 5of 14

End of Life Electrical Specifications (continued) V(cid:129)I Chip Regulator Output Waveforms Figure 9— Transient response; PRM alone 48 Vin, 0-5-0A, no load Figure 10— Transient response; PRM alone 36 Vin, 0-5-0A no load capacitance, local loop capacitance, local loop Figure 11— Transient response; PRM alone 75 Vin, 0-5-0A no load Figure 12— PC during fault – frequency will vary as a function of line voltage capacitance, local loop. Figure 13— Output ripple full load no bypass capacitance Figure 14— Output ripple full load 10µF bypass capacitance vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 6of 14

End of Life Electrical Specifications (continued) V(cid:129)I Chip Regulator Auxiliary Pins (Conditions are at 48 Vin, 48 Vf, full load, and 25°C ambient unless otherwise specified) Parameter Min Typ Max Unit Note VC (VTM Control) Pulse width 8 12 18 ms Peak voltage 12 14 18 V Referenced to –Out PC (Primary Control) DC voltage 4.8 5.0 5.2 Vdc Referenced to –In Module disable voltage 2.3 2.4 Vdc Referenced to –In Module enable voltage 2.5 2.6 Vdc Disable hysteresis 100 mV Source only after start up; not to be used for Current limit 1.75 1.90 mA aux. supply; 100 kΩ minimum load impedance to assure start up Enable delay time 100 µs Disable delay time 1 µs IL (Current Limit Adjust) Voltage 1 V Accuracy ± 15 % Based on DC current limit set point PR (Parallel Port) Voltage 0.6 7.5 V Referenced to SG; See description Page 8 Source current 1 mA External capacitance 100 pF VH (Auxiliary Voltage) Typical internal bypass C=0.1 µF Range 8.7 9.0 9.3 Vdc Maximum external C=0.1 µF, referenced to SG Regulation 0.04 %/mA Current 5 mA p SC (Secondary Control) Voltage 1.23 1.24 1.25 Vdc Referenced to SG Internal capacitance 0.22 µF External capacitance 0.7 µF OS (Output Set) Set point accuracy ± 1.5 % Includes 1% external resistor Reference offset ± 4 mV CD (Compensation Device) External resistance 20 Ω Omit resistor for regulation at output of PRM General Specs Parameter Min Typ Max Unit Note MTBF MIL-HDBK-217F 2.2 Mhrs 25°C, GB cTÜVus UL/CSA 60950-1, EN60950-1 Agency approvals CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable Mechanical parameters See Mechanical Drawings, Figures 19 – 22 Weight 0.53/15 oz/g Dimensions Length 1.28/32,5 in/mm Width 0.87/22,0 in/mm Height 0.265/6,73 in/mm Thermal Over temperature shutdown 130 135 140 °C Junction temperature Thermal capacity 9.3 Ws/°C Junction-to-case thermal impedance (RθJC) 1.1 °C/W Junction-to-board thermal impedance (RθJB) 2.1 °C/W Case-to-ambient 3.7 °C/W With 0.25” heat sink @ 300 LFM vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 7of 14

End of Life Pin / Control Functions V(cid:129)I Chip Regulator +In / -In DC Voltage Ports The V(cid:129)I Chip maximum input voltage should not be exceeded. PRMs AL Version 4 3 2 1 have internal over / undervoltage lockout functions that prevent VH A A VC SC B B PC operation outside of the specified input range. PRMs will turn on when SG C C TM the input voltage rises above its undervoltage lockout. If the input OS D D IL NC E E NC voltage exceeds the overvoltage lockout, PRMs will shut down until the CD F F PR overvoltage fault clears. PC will toggle indicating an out of bounds G G condition. +OUT HJ HJ +IN K K +Out / -Out Factorized Voltage Output Ports L L –OUT M M –IN These ports provide the Factorized Bus voltage output. The –Out port is N N P P connected internally to the –In port through a current sense resistor. The PRM has a maximum power and a maximum current rating and is Bottom View protected if either rating is exceeded. Do not short –Out to –In. Signal Name Designation +In G1-K1,G2-K2 –In L1-P1, L2-P2 VC – VTM Control VC A1,A2 The VTM Control (VC) port supplies an initial V voltage to PC B1, B2 CC TM C1, C2 downstreamVTMs, enabling the VTMs and synchronizing the rise of IL D1, D2 the VTM output voltage to that of the PRM. The VC port also provides PR F1, F2 feedback to the PRM to compensate for voltage drop due to the VTM VH A3, A4 SC B3, B4 output resistance. The PRM’s VC port should be connected to the VTM SG C3, C4 VC port. A PRM VC port can drive a maximum of two (2) VTM VC ports. OS D3, D4 CD F3, F4 +Out G3-K3, G4-K4 PC – Primary Control –Out L3-P3, L4-P4 The PRM voltage output is enabled when the PC pin is open circuit Figure 15 — PRM pin configuration (floating). To disable the PRM output voltage, the PC pin is pulled low. Open collector optocouplers, transistors, or relays can be used to control the PC pin. When using multiple PRMs in a high power array, the PC ports must be tied together to synchronize their turn on. SC – Secondary Control During an abnormal condition the PC pin will pulse (Fig.12) as the PRM The load voltage may be controlled by connecting a resistor or voltage initiates a restart cycle. This will continue until the abnormal condition source to the SC port referenced to SG. The slew rate of the output is rectified. The PC should not be used as an auxiliary voltage supply, voltage may be controlled by controlling the rate-of-rise of the voltage nor should it be switched at a rate greater than 1 Hz. at the SC port (e.g., to limit inrush current into a capacitive load). TM – Factory Use Only SG – Signal Ground This port provides a low inductance Kelvin connection to –In and IL – Current Limit Adjust should be used as reference for the OS, CD, SC,VH and IL ports. The PRM has a preset, maximum, current limit set point. The IL port may be used to reduce the current limit set point to a lower value. See OS – Output Set “adjusting current limits” on page 10. The application-specific value of the Factorized Bus voltage (Vf) is set by connecting a resistor between OS and SG. Resistor value selection is PR – Parallel Port shown in Table 1 on Page 2, and described on Page 9. If no resistor is connected, the PRM output will be approximately one volt. If set The PR port signal, which is proportional to the PRM output power, resistor is not collocated with the PRM, a local bypass capacitor of supports current sharing of two PRMs. To enable current sharing, ~200 pF may be required. PR ports should be interconnected. Steps should be taken to minimize coupling noise into the interconnecting bus. Terminate this port with a 10 k equivalent resistance to SG, e.g. 10 k for a single PRM, 20 k each CD – Compensation Device for 2 PRMs in parallel, 30 k each for 3 PRMs in parallel etc.. Please Adaptive Loop control is configured by connecting an external resistor consult Vicor Applications Engineering regarding additional between the CD port and SG. Selection of an appropriate resistor value considerations when paralleling more than two PRMs. (see Equation 2 on Page 9 and Table 1 on Page 2) configures the PRM to compensate for voltage drops in the equivalent output resistance of VH – Auxiliary Voltage the VTM and the PRM-VTM distribution bus. If no resistor is connected to CD, the PRM will be in Local Loop mode and will regulate the VH is a gated (e.g. mirrors PC), non-isolated, nominally 9 Volt, +Out / –Out voltage to a fixed value. regulated DC voltage (see “Auxiliary Pins” specifications, on Page 7) that is referenced to SG. VH may be used to power external circuitry having a total current consumption of no more than 5 mA under either transient or steady state conditons including turn-on. vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 8of 14

End of Life Application Information V(cid:129)I Chip Regulator Regulator Current Multiplier 0.01 µF PTVCMC SSVCGH VF = KVL + (IL(cid:129)KRo) +In +Out IL OS L NC NC ROS 10 kΩ PR PRM™-AL CD RCD 0.4 µH TM VTM™+Out O +In +Out VC A PC – Out VIN 10 Ω K D –In –Out – In Ro – Out Figure 16— Adaptive Loop compensation with output voltage trimming and soft start using the SC port. Output Voltage Setting with Adaptive Loop Output Voltage Trimming (optional) The equations for calculating R and R to set a VTM output After setting the output voltage from the procedure above the output OS CD voltage are: may be margined down (26 Vf min) by a resistor from SC-SG using this formula: 93100 10000 V ROS= ( VL (cid:129) 0.8395 ) – 1 (1) RdΩ= fd V - V fs fd K Where V is the desired factorized bus and V is the set factorized bus. fd fs 91238 (2) R = + 1 A low voltage source can be applied to the SC port to margin the load CD ROS voltage in proportion to the SC reference voltage. An external capacitor can be added to the SC port as shown in Figure 16 VL= Desired load voltage to control the output voltage slew rate for soft start. V = VTM output voltage OUT K = VTM transformation ratio (available from appropriate VTM data sheet) V = PRM output voltage, the Factorized Bus (see Figure 16) f Nominal Vout VTM Range (Vdc) K Factor R = VTM output resistance O ↔ 0.8 1.6 1/32 (available from appropriate VTM data sheet) ↔ 1.1 2.2 1/24 IL= Load Current 1.6 ↔ 3.3 1/16 (actual current delivered to the load) 2.2 ↔ 4.4 1/12 ↔ 3.3 6.6 1/8 ↔ 4.3 8.8 1/6 ↔ 6.5 13.4 1/4 ↔ 8.7 17.9 1/3 ↔ 13.0 26.9 1/2 ↔ 17.4 36.0 2/3 ↔ 26.0 54.0 1 Table 2 — 048 input series VTM K factor selection guide vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 9of 14

End of Life Application Information (continued) V(cid:129)I Chip Regulator OVP – Overvoltage Protection Adjusting Current Limit The output Overvoltage Protection set point of the P048F048T24AL is The current limit can be lowered by placing an external resistor factory preset for 56 V. If this threshold is exceeded the output shuts between the I and SG ports (see Figure 18 for resistor values) . With L down and a restart sequence is initiated, also indicated by PC pulsing. the I port open-circuit, the current limit is preset to be within the L If the condition that causes OVP is still present, the unit will again shut range specified in the output specifications table on Page 4. down. This cycle will be repeated until the fault condition is removed. The OVP set point may be set at the factory to meet unique high voltage requirements. DC CURRENT LIMIT 100 PRM Output Power Versus VTM Output Power As shown in Figure 17, the P048F048T24AL is rated to deliver 5 A maximum, when it is delivering an output voltage in the range from Ω) 26 V to 48 V, and 240 W, maximum, when delivering an output k voltage in the range from 48 V to 55 V. When configuring a PRM for ue ( 10 use with a specific VTM, refer to the appropriate VTM data sheet. The Val VTM input power can be calculated by dividing the VTM output power xt e by the VTM efficiency (available from the VTM data sheet). The input R power required by the VTM should not exceed the output power rating of the PRM. 1 0 1 2 3 4 5 6 Desired PRM Output Current Limit (A) 5.1 Figure 18 — Calculated external resistor value for adjusting current limit, 5.0 actual value may vary. 4.9 A) 4.8 nt ( 4.7 Input Fuse Recommendations e Safe Operating Area urr 4.6 A fuse should be incorporated at the input to the PRM, in series with C the +In port. A fast acting fuse, NANO2 FUSE 451/453 Series 10 A 4.5 125 V, or equivalent, may be required to meet certain safety agency 4.4 Conditions of Acceptability. Always ascertain and observe the safety, 4.3 regulatory, or other agency specifications that apply to your specific ~~ application. 0 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Factorized Bus Voltage (Vf) Product Safety Considerations If the input of the PRM is connected to SELV or ELV circuits, the output Figure 17 — P048F048T24AL rating based on Factorized Bus voltage of the PRM can be considered SELV or ELV respectively. If the input of the PRM is connected to a centralized DC power system where the working or float voltage is above SELV, but less than or The Factorized Bus voltage should not exceed an absolute limit of equal to 75 V, the input and output voltage of the PRM should be 55 V, including steady state, ripple and transient conditions. Exceeding classified as a TNV-2 circuit and spaced 1.3 mm from SELV circuitry or this limit may cause the internal OVP set point to be exceeded. accessible conductive parts according to the requirements of UL60950-1, CSA 22.2 60950-1, EN60950-1, and IEC60950-1. Parallel Considerations The PR port is used to connect two PRMs in parallel to form a higher power array. When configuring arrays, PR port interconnection terminating impedance is 10 k to SG. See note Page 8 and refer to Application Note AN002. Additionally one PRM should be designated as the master while all other PRMs are set as slaves by shorting their SC pin to SG. The PC pins must be directly connected (no diodes) to assure a uniform start up sequence. Consult Vicor applications engineering for applications requiring more than two PRMs. Applications Assistance Please contact Vicor Applications Engineering for assistance, 1-800-927-9474, or email at apps@vicorpower.com. vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 10of 14

End of Life Mechanical Drawings V(cid:129)I Chip Regulator NOTES: mm 1. DIMENSIONS ARE in c h . 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 3. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com Figure 19 —PRM J-Lead mechanical outline RECOMMENDED LAND PATTERN NOTES: mm ( COMPONENT SIDE SHOWN ) 1. DIMENSIONS ARE in c h . 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 3. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com Figure 20 — PRM J-Lead PCB layout information vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 11of 14

Not Recommended for New Designs Mechanical Drawings (continued) V(cid:129)I Chip Regulator NOTES: (mm) 1. DIMENSIONS AREinch. 2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE: X.X [X.XX] = ±0.25 [0.01]; X.XX [X.XXX] = ±0.13 [0.005] 3. RoHS COMPLIANT PER CST-0001 LATEST REVISION DXF and PDF files are available on vicorpower.com Figure 21 — PRM Through-hole mechanical outline NOTES: (mm) 1. DIMENSIONS AREinch. 2. UNLESS OTHERWISE SPECIFIED TOLERANCES ARE: X.X [X.XX] = ±0.25 [0.01]; X.XX [X.XXX] = ±0.13 [0.005] 3. RoHS COMPLIANT PER CST-0001 LATEST REVISION DXF and PDF files are available on vicorpower.com Figure 22 — PRM Through-hole PCB layout information vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 12of 14

Not Recommended for New Designs Configuration Options V(cid:129)I Chip Regulator RECOMMENDED LAND PATTERN (NO GROUNDING CLIPS) TOP SIDE SHOWN NOTES: 1. MAINTAIN 3.50 [0.138] DIA. KEEP-OUT ZONE FREE OF COPPER, ALL PCB LAYERS. 2. (A) MINIMUM RECOMMENDED PITCH IS 39.50 [1.555], THIS PROVIDES 7.00 [0.275] COMPONENT EDGE-TO-EDGE SPACING, AND 0.50 [0.020] CLEARANCE BETWEEN VICOR HEAT SINKS. (B) MINIMUM RECOMMENDED PITCH IS 41.00 [1.614], THIS PROVIDES 8.50 [0.334] COMPONENT EDGE-TO-EDGE SPACING, AND 2.00 [0.079] CLEARANCE BETWEEN VICOR HEAT SINKS. 3. V(cid:129)I CHIP™ MODULE LAND PATTERN SHOWN FOR REFERENCE ONLY; ACTUAL LAND PATTERN MAY DIFFER. DIMENSIONS FROM EDGES OF LAND PATTERN RECOMMENDED LAND PATTERN TO PUSH-PIN HOLES WILL BE THE SAME FOR (With GROUNDING CLIPS) ALL FULL SIZE V(cid:129)ICHIP PRODUCTS. TOP SIDE SHOWN 4. RoHS COMPLIANT PER CST-0001 LATEST REVISION. 5. UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE MM [INCH]. TOLERANCES ARE: X.X [X.XX] = ±0.3 [0.01] X.XX [X.XXX] = ±0.13 [0.005] 6. PLATED THROUGH HOLES FOR GROUNDING CLIPS (33855) SHOWN FOR REFERENCE. HEAT SINK ORIENTATION AND DEVICE PITCH WILL DICTATE FINAL GROUNDING SOLUTION. Figure 23 — Hole location for push pin heat sink relative to V(cid:129)I Chip vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 Page 13of 14

Not Recommended for New Designs Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. Specifications are subject to change without notice. Vicor’s Standard Terms and Conditions All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request. Product Warranty In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the “Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment and is not transferable. UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER. This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and operating safeguards. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Life Support Policy VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages. Intellectual Property Notice Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,788,033; 6,940,013; 6,969,909; 7,038,917; 7,154,250; 7,166,898; 7,187,263; 7,202,646; 7,361,844; 7,368,957; RE40,072; 7,361,844; 7,368,957; RE40,072; D496,906; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com vicorpower.com 800-735-6200 V(cid:129)I Chip Regulator P048F048T24AL Rev. 3.9 (cid:202)(cid:202)12(cid:201)(cid:163)(cid:206)