Product Sample & Technical Tools & Support & Folder Buy Documents Software Community OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 OPA820 Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier 1 Features 3 Description • HighBandwidth(240MHz,G=2) The OPA820 device provides a wideband, unity-gain 1 stable, voltage-feedback amplifier with a very-low • High-OutputCurrent(±110mA) input-noise voltage and high-output current using a • Low-InputNoise(2.5nV/√Hz) low 5.6-mA supply current. At unity-gain, the OPA820 • Low-SupplyCurrent(5.6mA) device gives more than 800-MHz bandwidth with less than1-dBpeaking.TheOPA820devicecomplements • FlexibleSupplyVoltage: this high-speed operation with excellent DC precision – Dual ±2.5Vto ±6V in a low-power device. A worst-case input-offset – Single5Vto12V voltage of ±750 µV and an offset current of ±400 nA provide excellent absolute DC precision for pulse • ExcellentDCAccuracy: amplifierapplications. – Maximum25°CInputOffsetVoltage= ±750 µV Minimal input and output voltage-swing headroom – Maximum25°CInputOffsetCurrent= ±400nA allow the OPA820 device to operate on a single 5-V supply with more than 2-V output swing. While not 2 Applications PP a rail-to-rail (RR) output, this swing supports most • Low-CostVideoLineDrivers emerging analog-to-digital converter (ADC) input ranges with lower power and noise than typical RR • ADCPreamplifiers outputopamps. • ActiveFilters Exceptionally low dG/dP (0.01% or 0.03°) supports • Low-NoiseIntegrators low-cost composite-video line-driver applications. • PortableTestEquipment Existing designs can use the industry-standard • OpticalChannelAmplifiers pinout, 8-pin SOIC package while emerging high- density portable applications can use the 5-pin SOT- • Low-Power,BasebandAmplifiers 23. Offering the lowest thermal impedance of the • CCDImagingChannelAmplifiers industry in a SOT package, along with full • OPA650andOPA620Upgrade specification over both the commercial and industrial temperature ranges, provides solid performance over awidetemperaturerange. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) SOIC(8) 4.90mm×3.91mm OPA820 SOT-23(5) 2.90mm×1.60mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. AC-Coupled,14-BitADS850Interface 5 V 5 V VIN + 0.1 PF 24R.9S (cid:13) 2 k(cid:13) 2 k(cid:13) R(3E VFT) OPA820 IN 50 (cid:13) 100 pF ADS850 14-Bit –5 V 10 MSPS 2 k(cid:13) 402 (cid:13) IN 402 (cid:13) 0.1 µF (2 V) (1 V) 2 k(cid:13) REFB VREF SEL Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 9.3 DeviceFunctionalModes........................................24 2 Applications........................................................... 1 10 ApplicationandImplementation........................ 28 3 Description............................................................. 1 10.1 ApplicationInformation..........................................28 4 RevisionHistory..................................................... 2 10.2 TypicalApplications..............................................28 5 DeviceComparisonTable..................................... 3 11 PowerSupplyRecommendations..................... 34 6 PinConfigurationandFunctions......................... 3 12 Layout................................................................... 35 12.1 LayoutGuidelines.................................................35 7 Specifications......................................................... 3 12.2 LayoutExample....................................................36 7.1 AbsoluteMaximumRatings......................................3 13 DeviceandDocumentationSupport................. 37 7.2 ESDRatings..............................................................4 7.3 RecommendedOperatingConditions.......................4 13.1 DeviceSupport......................................................37 7.4 ThermalInformation..................................................4 13.2 DocumentationSupport........................................37 7.5 ElectricalCharacteristics:V =±5V.........................4 13.3 ReceivingNotificationofDocumentationUpdates37 S 7.6 ElectricalCharacteristics:V =5V...........................7 13.4 CommunityResources..........................................38 S 7.7 TypicalCharacteristics............................................10 13.5 Trademarks...........................................................38 13.6 ElectrostaticDischargeCaution............................38 8 ParameterMeasurementInformation................18 13.7 Glossary................................................................38 9 DetailedDescription............................................ 20 14 Mechanical,Packaging,andOrderable 9.1 Overview.................................................................20 Information........................................................... 38 9.2 FeatureDescription.................................................20 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(August2008)toRevisionD Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection............................... 1 • DeletedOrderingInformationtable;seePackageOptionAddendumattheendofthedatasheet...................................... 1 • DeletedLeadtemperature(soldering,300°Cmaximum)fromAbsoluteMaximumRatingstable......................................... 3 • AddedThermalInformationtable........................................................................................................................................... 4 • ChangedOpen-loopvoltagegaintestconditioninElectricalCharacteristics:V =±5VtableFrom:V To:V ................5 S O CM • ChangedOpen-loopvoltagegaintestconditioninElectricalCharacteristics:V =5VtableFrom:V To:V ..................8 S O CM • ChangedR From:505ΩTo:517Ω,C From:150pFTo:100pF,andC From:100pFTo:160pFin5-MHz 2 1 2 ButterworthLow-PassActiveFilterimage............................................................................................................................ 28 ChangesfromRevisionB(March2006)toRevisionC Page • ChangedStorageTemperatureminimumvaluefrom–40°Cto–65°C.................................................................................. 3 ChangesfromRevisionA(July2004)toRevisionB Page • ChangedtheboardpartnumberintheDesign-InToolssection.......................................................................................... 37 2 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 5 Device Comparison Table Table1.RelatedProducts SINGLECHANNEL DUALCHANNEL TRIPLECHANNEL QUADCHANNEL FEATURES OPA354 OPA2354 — OPA4354 CMOSRRoutput OPA690 OPA2690 OPA3690 — High-slewrate — OPA2652 — — 8-PinSOT23 — OPA2822 — — Lownoise — — — OPA4820 QuadOPA820 6 Pin Configuration and Functions DPackage DBVPackage 8-PinSOIC 5-PinSOT-23 TopView TopView NC 1 8 NC Output 1 5 +VS Inverting Input 2 7 +VS Noninverting Input –VS 2 Noninverting Input Noninverting Input 3 + 6 Output + –VS 4 5 NC Noninverting Input 3 4 Inverting Input PinFunctions PIN I/O DESCRIPTION NAME SOIC SOT-23 Disable 8 — I Disabletheopamp(Low=Disable;High=Enable) InvertingInput 2 4 I Invertinginput NC 1,5,8 — — Noconnection NoninvertingInput 3 3 I Noninvertinginput Output 6 1 O Outputofamplifier +V 7 5 — Positivepowersupply S –V 4 2 — Negativepowersupply S 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Powersupply ±6.5 V DC Internalpowerdissipation SeeThermalInformation Differentialinputvoltage ±1.2 V Inputcommon-modevoltage ±V V S Junctiontemperature,T 150 °C J Storagetemperature,T –65 125 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±3000 V Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 V (ESD) Machinemodel(MM) ±300 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Totalsupplyvoltage 5 10 12 V S T Operatingambienttemperature –45 25 85 °C A 7.4 Thermal Information OPA820 THERMALMETRIC(1) DBV(SOT-23) D(SOIC) UNIT 5PINS 8PINS R Junction-to-ambientthermalresistance 150 125 °C/W θJA R Junction-to-case(top)thermalresistance 141.1 72.6 °C/W θJC(top) R Junction-to-boardthermalresistance 42.9 68.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 23.5 28.1 °C/W JT ψ Junction-to-boardcharacterizationparameter 42 67.8 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 7.5 Electrical Characteristics: V = ±5 V S R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted)(1)(2)(3) F L A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ACPERFORMANCE G=1,V =0.1V ,R =0Ω,Testlevel=C 800 O PP F T =25°C 170 240 A G=2,V =0.1V , O PP T =0°Cto70°C 160 Testlevel=B A Small-signalbandwidth T =–40°Cto85°C 155 MHz A T =25°C 23 30 A G=10,V =0.1V , O PP T =0°Cto70°C 21 Testlevel=B A T =–40°Cto85°C 20 A T =25°C 220 280 A Gain-bandwidthproduct G≥20,Testlevel=B T =0°Cto70°C 204 MHz A T =–40°Cto85°C 200 A Bandwidthfor0.1-dBgainflatness G=2,V =0.1V ,Testlevel=C 38 MHz O PP Peakingatagainof1 V =0.1V ,R =0Ω,Testlevel=C 0.5 dB O PP F Large-signalbandwidth G=2,V =2V ,Testlevel=C 85 MHz O PP T =25°C 192 240 A G=2,2-Vstep, Slewrate T =0°Cto70°C 186 V/µs Testlevel=B A T =–40°Cto85°C 180 A Risetimeandfalltime G=2,V =0.2-Vstep,Testlevel=C 1.5 ns O (1) Testlevels:(A)100%testedat25°C.Overtemperaturelimitsbycharacterizationandsimulation.(B)Limitssetbycharacterizationand simulation.(C)Typicalvalueonlyforinformation. (2) T =T for25°Cspecifications. J A (3) T =T atlowtemperaturelimits;T =T +9°Cathightemperaturelimitforovertemperature. J A J A 4 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 Electrical Characteristics: V = ±5 V (continued) S R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted)(1)(2)(3) F L A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT G=2,V =2-Vstep, To0.02% 22 Settlingtime O ns Testlevel=C To0.1% 18 T =25°C –85 –81 G=2,f=1MHz, A V =2V ,R =200Ω, T =0°Cto70°C –80 O PP L A Testlevel=B T =–40°Cto85°C –79 A Harmonicdistortion,2nd-harmonic dBc T =25°C –90 –85 G=2,f=1MHz, A V =2V ,R ≥500Ω, T =0°Cto70°C –83 O PP L A Testlevel=B T =–40°Cto85°C –81 A T =25°C –95 –90 G=2,f=1MHz, A V =2V ,R =200Ω, T =0°Cto70°C –89 O PP L A Testlevel=B T =–40°Cto85°C –88 A Harmonicdistortion,3rd-harmonic dBc T =25°C –110 –105 G=2,f=1MHz, A V =2V ,R ≥500Ω, T =0°Cto70°C –102 O PP L A Testlevel=B T =–40°Cto85°C –100 A T =25°C 2.5 2.7 A Inputvoltagenoise f>100kHz,Testlevel=B T =0°Cto70°C 2.8 nV/√Hz A T =–40°Cto85°C 2.9 A T =25°C 1.7 2.6 A Inputcurrentnoise f>100kHz,Testlevel=B T =0°Cto70°C 2.8 pA/√Hz A T =–40°Cto85°C 3 A Differentialgain G=2,PAL,V =1.4V ,R =150Ω,Testlevel=C 0.01% O PP L Differentialphase G=2,PAL,V =1.4V ,R =150Ω,Testlevel=C 0.03 ° O PP L DCPERFORMANCE(4) T =25°C 62 66 A A Open-loopvoltagegain V =0V,Testlevel=A T =0°Cto70°C 61 dB OL CM A T =–40°Cto85°C 60 A ±0.7 T =25°C ±0.2 A 5 Inputoffsetvoltage V =0V,Testlevel=A mV CM T =0°Cto70°C ±1 A T =–40°Cto85°C ±1.2 A T =0°Cto70°C 4 A Averageinputoffsetvoltagedrift V =0V,Testlevel=B µV/°C CM T =–40°Cto85°C 4 A T =25°C –9 –17 A Inputbiascurrent V =0V,Testlevel=A T =0°Cto70°C –19 µA CM A T =–40°Cto85°C –23 A T =0°Cto70°C 30 A Averageinputbiascurrentdrift V =0V,Testlevel=B nA/°C CM T =–40°Cto85°C 50 A T =25°C ±100 ±400 A Inputoffsetcurrent V =0V,Testlevel=A T =0°Cto70°C ±600 nA CM A T =–40°Cto85°C ±700 A T =0°Cto70°C 5 A Invertinginputbias-currentdrift V =0V,Testlevel=B nA/°C CM T =–40°Cto85°C 5 A (4) Currentisconsideredpositiveout-of-node.V istheinputcommon-modevoltage. CM Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com Electrical Characteristics: V = ±5 V (continued) S R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted)(1)(2)(3) F L A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUT T =25°C ±3.8 ±4 A CMIR Common-modeinputrange(5) Testlevel=A T =0°Cto70°C ±3.7 V A T =–40°Cto85°C ±3.6 A T =25°C 76 85 A V =0V,Input-referred, CMRR Common-moderejectionratio CM T =0°Cto70°C 75 dB Testlevel=A A T =–40°Cto85°C 73 A Inputimpedance,differentialmode V =0V,T =25°C,Testlevel=C 18||0.8 kΩ||pF CM A Inputimpedance,commonmode V =0V,T =25°C,Testlevel=C 6||1 MΩ||pF CM A OUTPUT T =25°C ±3.5 ±3.7 A ±3.4 Noload,Testlevel=A T =0°Cto70°C A 2 T =–40°Cto85°C ±3.4 A Outputvoltageswing V T =25°C ±3.5 ±3.6 A ±3.4 R =100Ω,Testlevel=A T =0°Cto70°C L A 5 T =–40°Cto85°C ±3.4 A T =25°C ±90 ±110 A Outputcurrent V =0V,Testlevel=A T =0°Cto70°C ±80 mA O A T =–40°Cto85°C ±75 A Short-circuitoutputcurrent Outputshortedtoground,Testlevel=C ±125 mA Closed-loopoutputimpedance G=2,f≤100kHz,Testlevel=C 0.04 Ω POWERSUPPLY T =25°C 5.45 5.6 5.75 A Quiescentcurrent V =±5V,Testlevel=A T =0°Cto70°C 5 6.2 mA S A T =–40°Cto85°C 4.8 6.4 A T =25°C 64 72 A PSRR Power-supplyrejectionratio Inputreferred,Testlevel=A T =0°Cto70°C 63 dB A T =–40°Cto85°C 62 A (5) Testedatlessthan3dBbelowtheminimumspecifiedCMRRat±CMIRlimits. 6 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 7.6 Electrical Characteristics: V = 5 V S R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted)(1)(2)(3) F L A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ACPERFORMANCE G=1,V =0.1V ,R =0Ω,Testlevel=C 550 O PP F T =25°C 168 230 A G=2,V =0.1V , O PP T =0°Cto70°C 155 Testlevel=B A Small-signalbandwidth T =–40°Cto85°C 151 MHz A T =25°C 21 28 A G=10,V =0.1V , O PP T =0°Cto70°C 20 Testlevel=B A T =–40°Cto85°C 19 A T =25°C 200 260 A Gain-bandwidthproduct G≥20,Testlevel=B T =0°Cto70°C 190 MHz A T =–40°Cto85°C 185 A Peakingatagainof1 V =0.1V ,R =0Ω,Testlevel=C 0.5 dB O PP F Large-signalbandwidth G=2,V =2V ,Testlevel=C 70 MHz O PP T =25°C 145 200 A G=2,2-Vstep, Slewrate T =0°Cto70°C 140 V/µs Testlevel=B A T =–40°Cto85°C 135 A Risetimeandfalltime G=2,V =2-Vstep,Testlevel=C 1.7 ns O G=2,V =2-Vstep, To0.02% 24 Settlingtime O ns Testlevel=C To0.1% 21 T =25°C –80 –76 G=2,f=1MHz, A V =2V ,R =200Ω, T =0°Cto70°C –75 O PP L A Testlevel=B T =–40°Cto85°C –74 A Harmonicdistortion,2nd-harmonic dBc T =25°C –83 –79 G=2,f=1MHz, A V =2V ,R ≥500Ω, T =0°Cto70°C –77 O PP L A Testlevel=B T =–40°Cto85°C –75 A T =25°C –100 –92 G=2,f=1MHz, A V =2V ,R =200Ω, T =0°Cto70°C –91 O PP L A Testlevel=B T =–40°Cto85°C –90 A Harmonicdistortion,3rd-harmonic dBc T =25°C –98 –95 G=2,f=1MHz, A V =2V ,R ≥500Ω, T =0°Cto70°C –93 O PP L A Testlevel=B T =–40°Cto85°C –92 A T =25°C 2.5 2.8 A Inputvoltagenoise f>100kHz,Testlevel=B T =0°Cto70°C 2.9 nV/√Hz A T =–40°Cto85°C 3 A T =25°C 1.6 2.5 A Inputcurrentnoise f>100kHz,Testlevel=B T =0°Cto70°C 2.7 pA/√Hz A T =–40°Cto85°C 2.9 A (1) Testlevels:(A)100%testedat25°C.Overtemperaturelimitsbycharacterizationandsimulation.(B)Limitssetbycharacterizationand simulation.(C)Typicalvalueonlyforinformation. (2) T =T for25°Cspecifications. J A (3) T =T atlowtemperaturelimits;T =T +9°Cathightemperaturelimitforovertemperature. J A J A Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com Electrical Characteristics: V = 5 V (continued) S R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted)(1)(2)(3) F L A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DCPERFORMANCE(4) T =25°C 60 65 A A Open-loopvoltagegain V =2.5V,Testlevel=A T =0°Cto70°C 59 dB OL O A T =–40°Cto85°C 58 A T =25°C ±0.3 ±1.1 A Inputoffsetvoltage V =2.5V,Testlevel=A T =0°Cto70°C ±1.4 mV CM A T =–40°Cto85°C ±1.6 A T =0°Cto70°C 4 A Averageinputoffsetvoltagedrift V =2.5V,Testlevel=B µV/°C CM T =–40°Cto85°C 4 A T =25°C –8 –16 A Inputbiascurrent V =2.5V,Testlevel=A T =0°Cto70°C –18 µA CM A T =–40°Cto85°C –22 A T =0°Cto70°C 30 A Averageinputbiascurrentdrift V =2.5V,Testlevel=B nA/°C CM T =–40°Cto85°C 50 A T =25°C ±100 ±400 A Inputoffsetcurrent V =2.5V,Testlevel=A T =0°Cto70°C ±600 nA CM A T =–40°Cto85°C ±700 A T =0°Cto70°C 5 A Invertinginputbias-currentdrift V =2.5V,Testlevel=B nA/°C CM T =–40°Cto85°C 5 A INPUT T =25°C 0.9 1.1 A Leasepositiveinputvoltage Testlevel=A T =0°Cto70°C 1.2 V A T =–40°Cto85°C 1.3 A T =25°C 4.2 4.5 A Mostpositiveinputvoltage Testlevel=A T =0°Cto70°C 4.1 V A T =–40°Cto85°C 4 A T =25°C 74 83 A V =2.5V,Input-referred, CMRR Common-moderejectionratio CM T =0°Cto70°C 73 dB Testlevel=A A T =–40°Cto85°C 72 A Inputimpedance,differentialmode V =2.5V,T =25°C,Testlevel=C 15||1 kΩ||pF CM A 5|| Inputimpedance,commonmode V =2.5V,T =25°C,Testlevel=C MΩ||pF CM A 1.3 (4) Currentisconsideredpositiveout-of-node.V istheinputcommon-modevoltage. CM 8 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 Electrical Characteristics: V = 5 V (continued) S R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted)(1)(2)(3) F L A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OUTPUT T =25°C 3.8 3.9 A Noload,Testlevel=A T =0°Cto70°C 3.75 A T =–40°Cto85°C 3.7 A Mostpositiveoutputvoltage V T =25°C 3.7 3.8 A R =100Ωto2.5V, L T =0°Cto70°C 3.65 Testlevel=A A T =–40°Cto85°C 3.6 A T =25°C 1.2 1.3 A Noload,Testlevel=A T =0°Cto70°C 1.35 A T =–40°Cto85°C 1.4 A Leastpositiveoutputvoltage V T =25°C 1.2 1.3 A R =100Ωto2.5V, L T =0°Cto70°C 1.35 Testlevel=A A T =–40°Cto85°C 1.4 A T =25°C ±80 ±105 A Outputcurrent V =2.5V,Testlevel=A T =0°Cto70°C ±70 mA O A T =–40°Cto85°C ±65 A Short-circuitoutputcurrent Outputshortedtoground,Testlevel=C ±115 mA Closed-loopoutputimpedance G=2,f≤100kHz,Testlevel=C 0.04 Ω POWERSUPPLY T =25°C 4.4 5 5.4 A Quiescentcurrent V =±5V,Testlevel=A T =0°Cto70°C 4.25 5.5 mA S A T =–40°Cto85°C 4.1 5.6 A PSRR Power-supplyrejectionratio Inputreferred,T =25°C,Testlevel=A 68 dB A Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 7.7 Typical Characteristics 7.7.1 ±5-VSupplyVoltage V =±5V,R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted) S F L A 3 3 0 0 dB) −3 dB) −3 ( ( n n Gai −6 Gai −6 d d e e z −9 z −9 ali ali m m Nor −12 G = 1 Nor −12 G =–1 G = 2 G =–2 −15 G = 5 −15 G =–5 G = 10 G =–10 −18 −18 1M 10M 100M 1G 1 10 100 500 Frequency(Hz) Frequency(MHz) V =0.1V R =0ΩatG=1 SeeFigure55 V =0.1V SeeFigure56 O PP F O PP Figure1.NoninvertingSmall-SignalFrequencyResponse Figure2.InvertingSmall-SignalFrequencyResponse 9 3 6 0 3 −3 B) 0 B) −6 d d ( ( n n ai −3 ai −9 G G −6 −12 V = 0.5 V V = 0.5 V O PP O PP V = 1 V V = 1 V −9 VO= 2 VPP −15 VO= 2 VPP O PP O PP V = 4 V V = 4 V O PP O PP −12 −18 1 10 100 500 1 10 100 500 Frequency(MHz) Frequency(MHz) G=2 SeeFigure55 G=–1 SeeFigure56 Figure3.NoninvertingLarge-SignalFrequencyResponse Figure4.InvertingLarge-SignalFrequencyResponse v) 0.4 2.0 v) v) 0.4 2.0 v) mV/di 0.3 1.5 mV/di mV/di 0.3 LSamrgaell SSiiggnnaall ±± 110 V0 mV 1.5 mV/di 0 0 0 0 10 0.2 1.0 50 10 0.2 1.0 50 ( ( ( ( e e e e ag 0.1 0.5 ag ag 0.1 0.5 ag olt olt olt olt V 0 0 V V 0 0 V ut ut ut ut p p p p ut −0.1 −0.5 ut ut −0.1 −0.5 ut O O O O nal −0.2 −1.0 nal nal −0.2 −1.0 nal g g g g Si Si Si Si − −0.3 Large Signal ± 1 V −1.5 − − −0.3 −1.5 − Small −0.4 Small Signal ± 100 mV −2.0 Large Small −0.4 −2.0 Large Time(10 ns/div) Time(10 ns/div) G=2 SeeFigure55 G=–1 SeeFigure56 Figure5.NoninvertingPulseResponse Figure6.InvertingPulseResponse 10 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 ±5-V Supply Voltage (continued) V =±5V,R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted) S F L A −70 −75 2nd−Harmonic 2nd−Harmonic 3rd−Harmonic 3rd−Harmonic −75 −80 c) c) B B d d n( −80 n( −85 o o orti orti Dist −85 Dist −90 monic −90 monic −95 Har −95 Har −100 −100 −105 100 1k 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Resistance(Ω) SupplyVoltage(±VS) f=1MHz VO=2VPP G=2V/V VO=2VPP RL=200Ω G=2V/V SeeFigure55 SeeFigure55 Figure7.HarmonicDistortionvsLoadResistance Figure8.1-MHzHarmonicDistortionvsSupplyVoltage −60 −75 2nd−Harmonic 2nd−Harmonic −65 3rd−Harmonic −80 3rd−Harmonic Bc) −70 Bc) d d −85 n( −75 n( o o orti −80 orti −90 st st Di −85 Di −95 c c ni ni o −90 o m m −100 Har −95 Har −105 −100 −105 −110 0.1 1 10 0.1 1 10 Frequency(MHz) OutputVoltage(V ) PP V =2V G=2V/V f=1MHz R =200Ω G=2V/V O PP L SeeFigure55 SeeFigure55 Figure9.HarmonicDistortionvsFrequency Figure10.HarmonicDistortionvsOutputVoltage −70 −70 2nd−Harmonic 2nd−Harmonic −75 3rd−Harmonic 3rd−Harmonic −75 c) c) B −80 B d d on( −85 on( −80 orti orti st −90 st −85 Di Di c c ni −95 ni o o −90 m m ar −100 ar H H −95 −105 −110 −100 1 10 1 10 Gain(V/V) Gain(|V/V|) f=1MHz R =200Ω V =2V f=1MHz R =200Ω V =2V L O PP L O PP SeeFigure55 SeeFigure56 Figure11.HarmonicDistortionvsNoninvertingGain Figure12.HarmonicDistortionvsInvertingGain Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com ±5-V Supply Voltage (continued) V =±5V,R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted) S F L A 100 50 Voltage Noise (2.5 nV/√HZ) Current Noise (1.7 pA/√HZ) 45 Hz)Hz) m) 40 √√ B V/A/ +d oise(noise(p 10 Point( 35 NN pt 30 VoltageCurrent Interce 25 20 1 15 10 100 1k 10k 100k 1M 10M 0 5 10 15 20 25 30 Frequency(Hz) Frequency(MHz) SeeFigure48 Figure13.InputVoltageandCurrentNoise Figure14.Two-Tone,3rd-OrderIntermodulationIntercept 100 B) 8 (d 7 d oa 6 L e 5 v citi 4 a Ω) ap 3 ( 10 C RS to 2 n ai 1 G d 0 C = 10 pF e L 1 Normaliz −−−123 CCCLLL=== 241270 0pp FFpF 1 10 100 1000 1 10 100 400 CapacitiveLoad(pF) Frequency(MHz) 0-dBpeakingtargeted SeeFigure49 Figure15.RecommendedR vsCapacitiveLoad Figure16.FrequencyResponsevsCapacitiveLoad S 90 80 0 mon−ModeRejectionRatio(dB)er−SupplyRejectionRatio(dB) 87654320000000 CMRR Open−LoopGain(dB) 76543210000000 2∠0A lOoLg (AOL) −−−−−−−24681110000024000 Open−LoopPhase(°) ComPow 10 +–PPSSRRRR 0 −160 0 −10 −180 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M 1G Frequency(Hz) Frequency(Hz) Figure17.CMRRandPSRRvsFrequency Figure18.Open-LoopGainandPhase 12 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 ±5-V Supply Voltage (continued) V =±5V,R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted) S F L A 5 10 1-WInternal OutputCurrent 4 PowerLimit Limit 3 Ω) ut Voltage (V) −2101 Impedance( 1 Outp −2 utput 0.1 O −3 OutputCurrent −4 1-WInternal −5 Limit RL= 25Ω RL= 50Ω RL= 100Ω PowerLimit 0.01 −150 −100 −50 0 50 100 150 1k 10k 100k 1M 10M 100M Output Current (mA) Frequency(Hz) Figure19.OutputVoltageandCurrentLimitations Figure20.Closed-LoopOutputImpedancevsFrequency 8 4 5 5 Input 4 4 6 Output 3 OutputVoltage(2V/div) −−42024 210−−12 InputVoltage(1 V/div) OutputVoltage(1 V/div) −−−3210123 OIuntppuutt 3210−−−123 InputVoltage(1V/div) −6 −3 −4 −4 −8 −4 −5 −5 Time(40ns/div) Time(40 ns/div) G=2V/V SeeFigure55 G=2V/V SeeFigure56 Figure21.NoninvertingOverdriveRecovery Figure22.InvertingOverdriveRecovery 0.20 0.40 1.0 20 dG Negative Video 10×InputOffsetCurrent (I ) 0.18 dG Positive Video 0.36 Input Offset Voltage (V )OS V) OS µ DifferentialGain(%) 0000000.......11110006420864 ddPPNPoesgiatitvivee V Vidideeoo 0000000.......32221108406282 DifferentialPhase(°) InputOffsetVoltage(mV) −00..505 Input Bias current (IB) 10−010 utBiasandOffsetCurrent( p 0.02 0.04 In 0 0 −1.0 −20 1 2 3 4 −50 −25 0 25 50 75 100 125 VideoLoads AmbientTemperature (°C) G=2V/V Figure23.CompositeVideodG/dP Figure24.TypicalDCDriftOverTemperature Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com ±5-V Supply Voltage (continued) V =±5V,R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted) S F L A 125 12 6 Supply Current –V IN Source Output Current +V Sink Output Current 5 –VIN urrent(mA) 17005 96 urrent(mA) Range(V) 43 +VOOUUTT C C e Output 50 3 Supply Voltag 2 1 25 0 0 −50 −25 0 25 50 75 100 125 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 AmbientTemperature(°C) SupplyVoltage(±VS) Figure25.SupplyandOutputCurrentvsTemperature Figure26.Common-ModeInputRangeandOutputSwing vsSupplyVoltage 10M 2500 2000 Ω) 1M ( ce 1500 edan 100k Count mp 1000 I ut p In 10k 500 Common-Mode Input Impedance Differential Input Impedance 0 1k 000000000000000000000 3681479257 7529741863 100 1k 10k 100k 1M 10M 100M −7−6−5−5−4−3−2−2−1− 122345567 Frequency(Hz) InputOffsetVoltage(µV) Mean=–30µV Totalcount=6115 Standarddeviation=80µV Figure27.Common-ModeandDifferentialInput Figure28.TypicalInputOffsetVoltageDistribution Impedance 2000 1800 1600 1400 1200 nt ou 1000 C 800 600 400 200 0 024680246808642086420 8406295173 3715926048 33322111−− 11122333 −−−−−−−− InputOffsetCurrent(nA) Mean=26nA Standarddeviation=57nA Totalcount=6115 Figure29.TypicalInputOffsetCurrentDistribution 14 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 7.7.2 5-VSupplyVoltage V =5V,R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted) S F L A 3 3 0 0 dB) −3 dB) −3 ( ( n n Gai −6 Gai −6 d d e e z −9 z −9 ali ali m m or −12 or −12 N G = 1 N G =–1 G = 2 G =–2 −15 G = 5 −15 G =–5 G = 10 G =–10 −18 −18 1M 10M 100M 1G 1 10 100 500 Frequency(Hz) Frequency(MHz) V =0.1V SeeFigure57 V =0.1V SeeFigure58 O PP O PP Figure30.NoninvertingSmall-SignalFrequencyResponse Figure31.InvertingSmall-SignalFrequencyResponse 9 3 6 0 B) 3 −3 d ( n Gai 0 dB) −6 zed −3 ain( −9 ali G m or −6 −12 N VO= 0.5 VPP VO= 0.5 VPP V = 1 V V = 1 V −9 VO= 2 VPP −15 VO= 2 VPP O PP O PP V = 4 V V = 4 V O PP O PP −12 −18 1 10 100 600 1 10 100 500 Frequency(MHz) Frequency(MHz) G=2V/V SeeFigure57 G=–1 SeeFigure58 Figure32.NoninvertingLarge-SignalFrequencyResponse Figure33.InvertingLarge-SignalFrequencyResponse v) 2.9 4.5 v) v) 2.9 4.5 v) mV/di 2.8 4.0 mV/di mV/di 2.8 LSamrgaell SSiiggnnaall ±± 110 V0 mV 4.0 mV/di 0 0 0 0 10 2.7 3.5 50 10 2.7 3.5 50 ( ( ( ( e e e e ag 2.6 3.0 ag ag 2.6 3.0 ag olt olt olt olt V 2.5 2.5 V V 2.5 2.5 V ut ut ut ut p p p p ut 2.4 2.0 ut ut 2.4 2.0 ut O O O O nal 2.3 1.5 nal nal 2.3 1.5 nal g g g g Si Si Si Si − 2.2 Large Signal ± 1 V 1.0 − − 2.2 1.0 − Small 2.1 Small Signal ± 100 mV 0.5 Large Small 2.1 0.5 Large Time(10ns/div) Time(10ns/div) G=2 SeeFigure57 G=–1 SeeFigure58 Figure34.NoninvertingPulseResponse Figure35.InvertingPulseResponse Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 5-V Supply Voltage (continued) V =5V,R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted) S F L A −75 −60 2nd−Harmonic 2nd−Harmonic 3rd−Harmonic 3rd−Harmonic −80 c) c) −70 B B d d n( −85 n( ortio ortio −80 st −90 st Di Di nic nic −90 o −95 o m m ar ar H H −100 −100 −105 −110 100 1k 0.1 1 10 Resistance(Ω) Frequency(MHz) G=2V/V f=1MHz V =2V G=2V/V R =200Ω V =2V O PP L O PP SeeFigure57 SeeFigure57 Figure36.HarmonicDistortionvsLoadResistance Figure37.HarmonicDistortionvsFrequency −70 −60 2nd−Harmonic 2nd−Harmonic 3rd−Harmonic 3rd−Harmonic Bc) −80 Bc) −70 d d ( ( n n ortio ortio −80 Dist −90 Dist nic nic −90 o o m m ar −100 ar H H −100 −110 −110 0.1 1 10 1 10 OutputVoltageSwing(V ) Gain(V/V) PP f=1MHz RL=200Ω VO=2VPP f=1MHz RL=200Ω VO=2VPP G=2V/V Figure38.HarmonicDistortionvsOutputVoltage Figure39.HarmonicDistortionvsNoninvertingGain −70 40 2nd−Harmonic 3rd−Harmonic −75 c) 35 dB m) n( −80 dB ortio nt(+ 30 st −85 oi Di P nic ept 25 o −90 c m er ar nt H I 20 −95 −100 15 1 10 0 5 10 15 20 25 30 Gain(|V/V|) Frequency(MHz) f=1MHz RL=200Ω VO=2VPP SeeFigure50 Figure40.HarmonicDistortionvsInvertingGain Figure41.Two-Tone,3rd-OrderIntermodulationIntercept 16 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 5-V Supply Voltage (continued) V =5V,R =402Ω,R =100Ω,G=2,andT =25°C(unlessotherwisenoted) S F L A 100 B) 8 (d 7 d oa 6 L e 5 v citi 4 a Ω) ap 3 ( 10 C RS to 2 n ai 1 G d 0 C = 10 pF e L 1 Normaliz −−−123 CCCLLL=== 241270 0pp FFpF 1 10 100 1000 1 10 100 300 CapacitiveLoad(pF) Frequency(MHz) 0-dBpeakingtargeted SeeFigure51 Figure42.RecommendedR vsCapacitiveLoad Figure43.FrequencyResponsevsCapacitiveLoad S 1.5 15 125 12 10×InputOffsetCurrent (I ) Supply Current Input Offset Voltage (V )OS V) Source Output Current 1.0 OS 10 µ ge(mV) 0.5 Input Bias current (IB) 5 Current( (mA) 100 Sink Output Current 9 (mA) nputOffsetVolta −0.05 0−5 BiasandOffset OutputCurrent 7550 63 SupplyCurrent I −1.0 −10 ut p n I −1.5 −15 25 0 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 AmbientTemperature(°C) AmbientTemperature( C) Figure44.TypicalDCDriftOverTemperature Figure45.SupplyandOutputCurrentvsTemperature 3500 2000 1800 3000 1600 2500 1400 1200 nt 2000 nt ou ou 1000 C 1500 C 800 1000 600 400 500 200 0 0 −1.08−0.97−0.86−0.76−0.65−0.54−0.43−0.32−0.22−0.1100.110.220.320.430.540.650.760.860.971.08 −380−342−304−266−228−190−152−114−76−3803876114152190228266304342380 InputOffsetVoltage(mV) InputOffsetCurrent(nA) Mean=490µV Totalcount=6115 Mean=43nA Totalcount=6115 Standarddeviation=90µV Standarddeviation=50nA Figure46.TypicalInputOffsetVoltageDistribution Figure47.TypicalInputOffsetCurrentDistribution Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 8 Parameter Measurement Information PI + OPA820 PO 50 (cid:13) 200 (cid:13) 402 (cid:13) 402 (cid:13) Copyright © 2016, Texas Instruments Incorporated Figure48. Circuitfor ±5-VTwo-Tone,3rd-OrderIntermodulationIntercept(Figure14) VI + RS OPA820 VO 50 (cid:13) CL 1 k(cid:13)(1) 402 (cid:13) 402 (cid:13) Copyright © 2016, Texas Instruments Incorporated (1) 1kΩisoptional. Figure49. Circuitfor ±5-VFrequencyResponsevsCapacitiveLoad(Figure55) 5 V 806 (cid:13) 0.01 µF PI + OPA820 PO 57.6 (cid:13) 806 (cid:13) 200 k(cid:13) 402 (cid:13) 402 (cid:13) 0.01 µF Copyright © 2016, Texas Instruments Incorporated Figure50. Circuitfor5-VTwo-Tone,3rd-OrderIntermodulationIntercept(Figure41) 18 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 Parameter Measurement Information (continued) 5 V 806 (cid:13) 0.01 µF VI + RS OPA820 VO 57.6 (cid:13) 806 (cid:13) CL 1 k(cid:13)(1) 402 (cid:13) 402 (cid:13) 0.01 µF Copyright © 2016, Texas Instruments Incorporated (1) Thisresistorisoptional. Figure51. Circuitfor5-VFrequencyResponsevsCapacitiveLoad(Figure43) Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 9 Detailed Description 9.1 Overview The OPA820 provides an exceptional combination of DC precision, wide bandwidth, and low noise while consuming 5.6 mA of quiescent current. With excellent performance extending from DC to high frequencies, the OPA820 can be used in a variety of applications ranging from driving the inputs of high-precision SAR ADCs to videodistributionssystems. 9.2 Feature Description 9.2.1 InputandESDProtection The OPA820 device is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in Absolute Maximum Ratings. All device pins are protected with internal ESD-protection diodes to the power supplies,asshowninFigure52. VCC External Pin –VCC Copyright © 2016, Texas Instruments Incorporated Figure52. InternalESDProtection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in systems with ±15-V supply parts driving into the OPA820 device), add current-limiting series resistors into the two inputs. Keep these resistor values as low as possible because high values degrade both noise performance and frequency response. Figure 53 shows an example protection circuit for I/O voltages that may exceed the supplies. 5 V 50-(cid:13)(cid:3)Source Power-supply decoupling not shown. 174 (cid:13) V1 + 50 (cid:13) 50 (cid:13) D1 D2 OPA820 VO – 50 (cid:13) RF 301 (cid:13) RG –5 V 301 (cid:13) Copyright © 2016, Texas Instruments Incorporated D1=D2;IN5911(orequivalent) Figure53. Gainof2WithInputProtection 20 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 Feature Description (continued) 9.2.2 BandwidthversusGain Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the GBP listed in Specifications. Ideally, dividing GBP by the noninverting signal gain (also called the noise gain, or NG) predicts the closed-loop bandwidth. In practice, this prediction only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At low signal gains, most amplifiers exhibit a more complex response with lower phase margin. The OPA820 device is optimized to give a maximally-flat, 2nd-order Butterworth response in a gain of 2. In this configuration, the OPA820 device has approximately 64° of phase margin and shows a typical –3-dB bandwidth of 240 MHz. When the phase margin is 64°, the closed-loop bandwidth is approximately √2 greater than the value predicted by dividing GBP by the noisegain. Increasing the gain causes the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of GBP / NG. At a gain of 10, the 30-MHz bandwidth shown in Electrical Characteristics: V = ±5 S VmatchesthepredictionofthesimpleformulausingthetypicalGBPof280MHz. 9.2.3 OutputDriveCapability The OPA820 device has been optimized to drive the demanding load of a doubly-terminated transmission line. When a 50-Ω line is driven, a series 50-Ω source resistor leading into the cable and a terminating 50-Ω load resistor at the end of the cable are used. Under these conditions, the cable impedance seems resistive over a wide frequency range, and the total effective load on the OPA820 device is 100 Ω in parallel with the resistance of the feedback network. Specifications lists a ±3.6-V swing into this load—which is then reduced to a ±1.8-V swing at the termination resistor. The ±75-mA output drive over temperature provides adequate current-drive margin for this load. Higher voltage swings (and lower distortion) are achievable when driving higher impedance loads. A single video load typically appears as a 150-Ω load (using standard 75-Ω cables) to the driving amplifier. The OPA820 device provides adequate voltage and current drive to support up to three parallel video loads (50-Ω total load) for an NTSC signal. With only one load, the OPA820 device achieves an exceptionally low 0.01% or 0.03° dG/dPerror. 9.2.4 DrivingCapacitiveLoads One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. A high- speed, high open-loop gain amplifier like the OPA820 device can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple terms, the capacitiveloadreactswiththeopen-loopoutputresistanceoftheamplifiertointroduceanadditionalpoleintothe loop and thereby decrease the phase margin. This issue has become a popular topic of application notes and articles, and several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, distortion, or a combination, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This solution does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lagfromthecapacitiveloadpole,thusincreasingthephasemarginandimprovingstability. Figure 15 (±5 V) and Figure 42 (5 V) show the recommended R versus capacitive load and the resulting S frequency response at the load. The criterion for setting the recommended resistor is the maximum-bandwidth, flat-frequency response at the load. Because a passive low-pass filter is now between the output pin and the load capacitance, the response at the output pin is typically somewhat peaked, and becomes flat after the roll-off action of the RC network. This response is not a concern in most applications, but can cause clipping if the desired signal swing at the load is very close to the swing limit of the amplifier. Such clipping most likely to occurs in pulse response applications where the frequency peaking is manifested as an overshoot in the step response. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA820 device. Long printed-circuit board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possibletotheOPA820outputpin(seeLayoutGuidelines). Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com Feature Description (continued) 9.2.5 DistortionPerformance The OPA820 device is capable of delivering an exceptionally-low distortion signal at high frequencies and low gains.ThedistortionplotsinTypicalCharacteristicsshowthetypicaldistortionunderawidevarietyofconditions. Most of these plots are limited to 100-dB dynamic range. The OPA820 distortion does not rise above –90 dBc until either the signal level exceeds 0.9 V, the fundamental frequency exceeds 500 kHz, or both occur. Distortion intheaudiobandislessthanorequalto–100dBc. Generally, until the fundamental signal reaches very high frequencies or powers, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration this is the sum of R + R , whereas in the inverting configuration this is just R (see F G F Figure 55). Increasing the output voltage swing directly increases harmonic distortion. Increasing the signal gain also increases the 2nd-harmonic distortion. Again, a 6-dB increase in gain increases the 2nd and 3rd-harmonic by 6 dB even with a constant output power and frequency. Finally, the distortion increases as the fundamental frequency increases because of the roll-off in the loop gain with frequency. Conversely, the distortion improves going to lower frequencies down to the dominant open-loop pole at approximately 100 kHz. Starting from the –85-dBc 2nd-harmonic for 2 V into 200 Ω, G = 2 distortion at 1 MHz (from Typical Characteristics), the 2nd- PP harmonicdistortiondoesnotshowanyimprovementbelow100kHzandthenbecomesEquation1. –100dB–20log(1MHz/100kHz)=–105dBc (1) 9.2.6 NoisePerformance The OPA820 device complements low harmonic distortion with low input-noise terms. Both the input-referred voltage noise and the two input-referred current noise terms combine to give a low output noise under a wide variety of operating conditions. Figure 54 shows the op amp noise analysis model with all the noise terms included.Inthismodel,allthenoisetermsaretakentobenoisevoltageorcurrentdensitytermsineithernV/√Hz orpA/√Hz. ENI OPA820 EO + RS IBN ERS RF 4kTR S 4kTR RG IBI F 4kT 4kT = 1.6E – 20J RG at 290° K Copyright © 2016, Texas Instruments Incorporated Figure54. OpAmpNoiseAnalysisModel The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, then taking the square root to get back to a spot noise voltage. Equation 2 shows the general form for this output noisevoltageusingthetermspresentedinFigure54. E “E2 (cid:14)(cid:11)I R (cid:12)(cid:14)4kTR ”NG2 (cid:14)(cid:11)I R (cid:12)2 (cid:14)4kTR NG O ‹ NI BN S S… BI F F (2) 22 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 Feature Description (continued) Dividing this expression by the noise gain (NG = 1 + R / R ) gives the equivalent input referred spot noise F G voltageatthenoninvertinginput,asshowninEquation3. 2 EN EN2I(cid:14)(cid:11)IBNRS(cid:12)2 (cid:14)4kTRS (cid:14)§¤IBIRF•‚ (cid:14) 4kTRF ' NG „ NG (3) Evaluating these two equations for the OPA820 circuit shown in Figure 55 gives a total output spot noise voltage of6.44nV/√Hzandanequivalentinputspotnoisevoltageof3.22nV/√Hz. 9.2.7 DCOffsetControl The OPA820 device can provide excellent DC-signal accuracy because of high open-loop gain, high common- mode rejection, high power-supply rejection, low input-offset voltage, and low bias-current offset errors. To take full advantage of this low input-offset voltage, careful attention to input bias-current cancellation is also required. Thehigh-speedinputstagefortheOPA820devicehasamoderatelyhighinputbiascurrent(9 µAtypicalintothe pins) but with a very close match between the two input currents—typically 100-nA input offset current. The total output-offset voltage can be considerably reduced by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 55 is to insert a 175-Ω series resistor into the noninverting input from the 50-Ω terminating resistor. When the 50-Ω source resistor is DC-coupled,thesourceimpedanceforthenoninvertinginputbiascurrentincreasesto200Ω.Becausethisvalue is now equal to the impedance looking out of the inverting input (R || R ), the circuit cancels the gains for the F G bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using a 402-Ω feedback resistor, this output error is now less than ±0.4 µA × 402 Ω = ±160 µV at 25°C. 9.2.8 ThermalAnalysis The OPA820 device does not require heat sinking or airflow in most applications. The maximum desired junction temperature sets the maximum allowed internal power dissipation as described in this section. Make sure that themaximumjunctiontemperaturedoesnotexceed150°C. UseEquation4tocalculatetheoperatingjunctiontemperature(T ). J T +P ×R (4) A D θJA The total internal power dissipation (P ) is the sum of quiescent power (P ) and additional power dissipated in D DQ the output stage (P ) to deliver load power. Quiescent power is the specified no-load supply current times the DL total supply voltage across the part. P depends on the required output signal and load but, for a grounded DL resistiveload,isatamaximumwhentheoutputisfixedatavoltageequalto ½ ofeithersupplyvoltage(forequal bipolarsupplies).Underthisworst-casecondition,useEquation5tocalculateP . DL P =V 2/(4×R ) DL S L where • R includesfeedbacknetworkloading. (5) L NOTE Thepowerintheoutputstageandnotintheloadthatdeterminesinternalpower dissipation. As a worst-case example, compute the maximum T using an OPA820IDBV (SOT23-5 package) in the circuit of J Figure55operatingatthemaximumspecifiedambienttemperatureof85°C. P =10V(6.4mA)+52/(4×(100Ω||800Ω))=134mW (6) D MaximumT =85°C+(134mW×150°C/W)=105°C (7) J Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 9.3 Device Functional Modes 9.3.1 WidebandNoninvertingOperation The combination of speed and dynamic range offered by the OPA820 device is easily achieved in a wide variety of application circuits, providing that simple principles of good design practice are observed. For example, good power-supply decoupling, as shown in Figure 55, is essential to achieve the lowest-possible harmonic distortion andsmoothfrequencyresponse. Proper PCB layout and careful component selection maximize the performance of the OPA820 device in all applications,asdiscussedinthefollowingsectionsofthisdatasheet. Figure 55 shows the gain of 2 configuration used as the basis for most of the typical characteristics. Most of the curves in Typical Characteristics were characterized using signal sources with a 50-Ω driving impedance and with measurement equipment presenting 50-Ω load impedance. In Figure 55, the 50-Ω shunt resistor at the V I terminal matches the source impedance of the test generator while, the 50-Ω series resistor at the V terminal O provides a matching resistor for the measurement equipment load. Generally, data sheet specifications refer to the voltage swings at the output pin (V in Figure 55). The 100-Ω load, combined with the 804-Ω total feedback O networkload,presentstheOPA820devicewithaneffectiveloadofapproximately90 Ω inFigure55. 5 V +VS + 0.1 µF 2.2 µF 50-(cid:13)(cid:3)Source VIN + VO 50 (cid:13) 50-(cid:13)(cid:3)Load OPA820 50 (cid:13) RF 402 (cid:13) RG 402 (cid:13) + 0.1 µF 2.2 µF –VS –5 V Copyright © 2016, Texas Instruments Incorporated Figure55. Gainof2,High-FrequencyApplicationandCharacterizationCircuit 9.3.2 WidebandInvertingOperation Operating the OPA820 device as an inverting amplifier has several benefits and is particularly useful when a matched 50-Ω source and input impedance is required. Figure 56 shows the inverting gain of –1 circuit used as thebasisoftheinvertingmodecurvesinTypicalCharacteristics. 24 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 Device Functional Modes (continued) 5 V + 0.1 µF 2.2 µF + VO 50 (cid:13) 50-(cid:13)(cid:3)Load OPA820 RT 0.01 µF 205 (cid:13) 50-(cid:13)(cid:3)Source 40R2G (cid:13) 40R2F (cid:13) VI RM 57.6 (cid:13) + 0.1 µF 2.2 µF –5 V Copyright © 2016, Texas Instruments Incorporated Figure56. InvertingG= –1SpecificationsandTestCircuit In the inverting case, only the feedback resistor appears as part of the total output load in parallel with the actual load. For the 100-Ω load used in the curves in Typical Characteristics, this results in a total load of 80 Ω in this inverting configuration. The gain resistor is set to get the desired gain (in this case 402 Ω for a gain of –1) while an additional input-matching resistor (R ) can be used to set the total input impedance equal to the source if M desired. In this case, R is 57.6 Ω in parallel with the 402-Ω gain setting resistor results in a matched input M impedance of 50 Ω. This matching is only required when the input must be matched to a source impedance, as inthecharacterizationtestingdoneusingthecircuitofFigure56. The OPA820 device offers extremely good DC accuracy as well as low noise and distortion. To take full advantage of that DC precision, the total DC impedance at each of the input nodes must be matched to get bias current cancellation. For the circuit of Figure 56, this matching requires the 205-Ω resistor to ground on the noninverting input. The calculation for this resistor includes a DC-coupled 50-Ω source impedance along with R G and R . Although this resistor provides cancellation for the bias current, it must be well decoupled (0.01 µF in M Figure56)tofilterthenoisecontributionoftheresistorandtheinputcurrentnoise. As the required R resistor approaches 50 Ω at higher gains, the bandwidth for the circuit in Figure 56 exceeds G the bandwidth at that same gain magnitude for the noninverting circuit of Figure 55 which occurs because of the lower noise gain for the circuit of Figure 56 when the 50-Ω source impedance is included in the analysis. For instance, at a signal gain of –10 (R = 50 Ω, R = open, R = 499 Ω) the noise gain for the circuit of Figure 56 is G M F showninEquation8. 1+499Ω/(50Ω+50Ω)=6 (8) Equation 8 is a result of adding the 50-Ω source in the noise gain equation which results in a considerably higher bandwidth than the noninverting gain of 10. Using the 240-MHz gain bandwidth product for the OPA820 device, an inverting gain of –10 from a 50-Ω source to a 50-Ω R gives 55-MHz bandwidth, whereas the noninverting G gainof10gives30MHz. Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com Device Functional Modes (continued) 9.3.3 WidebandSingle-SupplyOperation Figure 57 shows the AC-coupled, single 5-V supply, gain of 2-V/V circuit configuration used as a basis only for the5-VspecificationsinSpecifications.Themostimportantrequirementforsingle-supplyoperationistomaintain input and output-signal swings within the useable voltage ranges at both the input and the output. The circuit of Figure 57 establishes an input midpoint bias using a simple resistive divider from the 5-V supply (two 806-Ω resistors) to the noninverting input. The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 0.9 V of the negative supply and 0.5 V of the positive supply, giving a 3.6-V input- PP signal range. The input impedance-matching resistor (57.6 Ω) used in Figure 57 is adjusted to give a 50-Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (R ) is AC- G coupled,givingthecircuitaDCgainof1whichputstheinputDCbiasvoltage(2.5V)ontheoutputaswell.Ona single 5-V supply, the output voltage can swing to within 1.3 V of either supply pin while delivering more than 80- mAoutputcurrentgiving2.4-Voutputswinginto100 Ω(5.6dBmmaximumatthematchedload). Figure 58 shows the AC-coupled, single 5-V supply, gain of –1-V/V circuit configuration used as a basis only for the 5-V specifications in Specifications. In this case, the midpoint DC bias on the noninverting input is also decoupled with an additional 0.01-µF decoupling capacitor which reduces the source impedance at higher frequencies for the noninverting-input bias-current noise. This 2.5-V bias on the noninverting input pin appears ontheinvertinginputpinand,becauseR isDCblockedbytheinputcapacitor,alsoappearsattheoutputpin. G The single-supply test circuits of Figure 57 and Figure 58 show 5-V operation. These same circuits can be used with a single-supply of 5 V to 12 V. Operating on a single 12-V supply, with the absolute-maximum supply- voltagespecificationof13V,givesadequatedesignmarginforthetypical ±5%supplytolerance. 5 V +VS + 0.1 µF 6.8 µF 50-(cid:13)(cid:3)Source 806 (cid:13) DIS 0.01 µF VI + VO 100 (cid:13) OPA820 VS/2 57.6 (cid:13) 806 (cid:13) RF 402 (cid:13) RG 402 (cid:13) 0.01 µF Copyright © 2016, Texas Instruments Incorporated Figure57. AC-Coupled,G=2V/V,Single-SupplySpecificationsandTestCircuit 26 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 Device Functional Modes (continued) 5 V +VS + 0.1 µF 6.8 µF 806 (cid:13) DIS + VO 100 (cid:13) OPA820 VS/2 806 (cid:13) 0.01 µF RG RF 0.01 µF 402 (cid:13) 402 (cid:13) VI Copyright © 2016, Texas Instruments Incorporated Figure58. AC-Coupled,G= –1V/V,Single-SupplySpecificationsandTestCircuit Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 10.1 Application Information 10.1.1 OptimizingResistorValues BecausetheOPA820deviceisaunity-gainstable,voltage-feedbackopamp,awiderangeofresistorvaluescan be used for the feedback and gain-setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. Usually, the feedback resistor value is from 200 Ω to 1 kΩ. At less than 200 Ω, the feedback network presents additional output loading which can degrade the harmonic distortion performance of the OPA820 device. At greater than 1 kΩ, the typical parasitic capacitance (approximately 0.2 pF) across the feedback resistor can cause unintentional band limiting in the amplifierresponse.AdirectshortissuggestedasafeedbackforAV=1V/V. A good design practice is to target the parallel combination of R and R (see Figure 55) to be less than F G approximately200Ω.ThecombinedimpedanceR ||R interactswiththeinvertinginputcapacitance,placingan F G additional pole in the feedback network, and thus a zero in the forward response. Assuming a total parasitic of 2 pF on the inverting node, holding R || R < 200 Ω keeps this pole above 400 MHz. This constraint implies that F G the feedback resistor R can increase to several kΩ at high gains which is acceptable as long as the pole formed F byR andanyparasiticcapacitanceappearinginparalleliskeptoutofthefrequencyrangeofinterest. F In the inverting configuration, an additional design consideration must be considered. R becomes the input G resistor and therefore the load impedance to the driving source. If impedance matching is desired, R can be set G equaltotherequiredterminationvalue.However,atlowinvertinggains,theresultingfeedbackresistorvaluecan present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50-Ω input matching resistor (R ) requires a 100-Ω feedback resistor, which contributes to output loading in parallel with the external G load. In such a case, increasing both the R and R values is preferable, and then achieve the input matching F G impedance with a third resistor to ground (see Figure 56). The total input impedance becomes the parallel combinationofR andtheadditionalshuntresistor. G 10.2 Typical Applications 10.2.1 ActiveFilterDesign Most active filter topologies have exceptional performance using the broad bandwidth and unity-gain stability of the OPA820 device. Topologies employing capacitive feedback require a unity-gain stable, voltage-feedback op amp. Sallen-Key filters simply use the op amp as a noninverting gain stage inside an RC network. Either current feedbackorvoltage-feedbackopampscanbeusedinSallen-Keyimplementations. 28 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 Typical Applications (continued) C2 R3 160 pF 500 (cid:13) + OPA820 R4 500 (cid:13) 5 V R1 R2 124 (cid:13) 517 (cid:13) R5 158 (cid:13) V1 + C2 OPA820 VO 1000 pF C1010 pF RF 1.5R81 k(cid:13) R1528 (cid:13) OPA820 VOUT 402 (cid:13) VIN + C1 1000 pF RG –5 V 402 (cid:13) Copyright © 2016, Texas Instruments Incorporated Copyright © 2016, Texas Instruments Incorporated Figure59.5-MHzButterworthLow-PassActive Figure60.High-Q1-MHzBandpassFilter Filter 10.2.1.1 DesignRequirements ThedesignrequirementsfortheactivefiltersaregiveninTable2: Table2.DesignRequirements FILTERCUTOFFFREQUENCY FILTERTYPE Q DCGAIN(dB) f (MHz) -3dB SecondorderButterworth,low-passfilter 0.707 5 6 High-Q,bandpassfilter 10 1 — 10.2.1.2 DetailedDesignProcedure 10.2.1.2.1 High-QBandpassFilterDesignProcedure Thetransferfunctionofahigh-QbandpassfiltershowninFigure64isgivenbyEquation9. R (cid:14)R S 3 4 V RR C OUT 1 4 1 V 1 R IN S2 (cid:14)S (cid:14) 3 R C R R R CC 1 1 2 4 5 1 2 (9) R3 Z 2 O R R R CC 2 4 5 1 2 (10) Z 1 O Q R C 1 1 (11) w f = O ;1MHz O 2p (12) Use Equation 11 and Equation 12, along with the filter specifications in table to find the relationship between ω , 0 Q, R , and C . Set C = 1000 pF, which results in R = 1.5915 kΩ. The closest E96 standard value resistor value 1 1 1 1 is1.58kΩ. Notice that the DC load driven by the OPA820 driving the output V = R + R . Select the total load to be 1 kΩ OUT 3 4 andR =R ,whichresultsinavalueof500Ω. 3 4 Tosimplifythefilterdesign,setC =C =1000pF. 1 2 Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com Plugging the values of R , R , C , and C into Equation 10 and assuming R = R results in a value of 159.15 Ω. 3 4 1 2 2 5 ThecloseststandardE96valueis158Ω. SeeFigure61forthefrequencyresponseofthefiltershowninFigure60. 10.2.1.2.2 Low-PassButterworthFilterDesignProcedure Thetransferfunctionofalow-passButterworthfiltershowninFigure59 isgivenbyEquation13. V K OUT = VIN s2(R1R2C1C2)+s(R1C1+R2C1+R1C2(1-K))+1 where æ R ö K = ç1+ F ÷ R • è G øisthelow-frequencyDCgain (13) ThevaluesforR andR arethestandardrecommendedvaluesinthedatasheet. F G ThecutofffrequencyisinEquation14. 1 w = 0 (R CR C ) 1 1 2 2 (14) TheQofthefilterisgivenbyEquation15. RR CC Q = 1 2 1 2 R C +R C +R C (1-K) 1 1 2 1 1 2 (15) From Table 1, Q = 0.707 and ω = 2π × 5 MHz. To aid in solving this circuit, assume C = 100 pF and 0 1 R = 124 Ω. Plugging these values into Equation 14 and Equation 15 and finding the closest standard value 1 components results in R = 517 Ω and C = 160 pF. See Figure 62 for the frequency response of the filter shown 2 2 inFigure59. 10.2.1.3 ApplicationCurves 6 9 0 −6 6 −12 −18 3 −24 Gain(dB) −−−334062 Gain (dB) 0 −48 -3 −54 −60 -6 −66 −72 -9 100k 1M 10M 100M 10k 100k 1M 10M Frequency(Hz) Frequency (Hz) D001 Figure61.High-Q1-MHzBandpassFilterFrequency Figure62.FrequencyResponse Response 10.2.2 BufferingHigh-PerformanceADCs To achieve full performance from a high-dynamic range ADC, take considerable care in the design of the input- amplifier interface circuit. The example circuit in Figure 63 shows a typical AC-coupled interface to a very-high dynamic-range converter. This AC-coupled example allows the OPA820 device to operate using a signal range that swings symmetrically around ground (0 V). The 2-V swing is then level-shifted through the blocking PP capacitor to a midscale reference level, which is created by a well-decoupled resistive divider off the internal reference voltages of the converter. To have a negligible effect (1 dB) on the rated spurious-free dynamic range 30 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 (SFDR) of the converter, the SFDR of the amplifier must be at least 18 dB greater than the converter. The OPA820 device has a minimal effect on the rated distortion of the ADS850 device, given the 79-dB SFDR at 2 V , 1 MHz of the ADS850 device. The greater than 90-dB (<1 MHz) SFDR for the OPA820 device in this PP configuration implies a less than 3-dB degradation (for the system) from the specification of the converter. For additionalSFDRimprovementwiththeOPA820device,useadifferentialconfiguration. Successful application of the OPA820 device for ADC driving requires careful selection of the series resistor at the amplifier output and the additional shunt capacitor at the ADC input. To some extent, the selection of this RC network is determined empirically for each converter. Many high-performance CMOS ADCs, such as the ADS850, perform better with the shunt capacitor at the input pin. This capacitor provides low source impedance for the transient currents produced by the sampling process. Improved SFDR is often obtained by adding this external capacitor, whose value is often recommended in the data sheet of the converter. The external capacitor, in combination with the built-in capacitance of the ADC input, presents a significant capacitive load to the OPA820 device. Without a series isolation resistor, an undesirable peaking or loss of stability in the amplifier can occur. Because the DC bias current of the CMOS ADC input is negligible, the resistor has no effect on overall gain or offset accuracy. See Figure 15 (±5 V) and Figure 42 (5 V) to obtain a good starting value for the series resistor which ensures a flat-frequency response to the ADC input. Increasing the external capacitor value allows the series resistor to be reduced. Intentionally band limiting using this RC network can also be used to limit noise at theconverterinput. 5 V 5 V VIN + 0.1 PF 24R.9S (cid:13) 2 k(cid:13) 2 k(cid:13) R(3E VFT) OPA820 IN 50 (cid:13) 100 pF ADS850 14-Bit –5 V 10 MSPS 2 k(cid:13) 402 (cid:13) IN 402 (cid:13) 0.1 µF (2 V) (1 V) 2 k(cid:13) REFB VREF SEL Copyright © 2016, Texas Instruments Incorporated Figure63. HighDynamic-RangeConverter 10.2.3 VideoLineDriving Most video distribution systems are designed with 75-Ω series resistors to drive a matched 75-Ω cable. To deliver a net gain of 1 to the 75-Ω matched load, the amplifier is typically set up for a voltage gain of 2, compensating for the 6-dB attenuation of the voltage divider formed by the series and shunt 75-Ω resistors at eitherendofthecable. The circuit of Figure 55 applies to this requirement if all references to 50-Ω resistors are replaced by 75-Ω values. Often, the amplifier gain is further increased to 2.2, which recovers the additional DC loss of a typical longcablerun.Thischangewouldrequirethegainresistor(R )inFigure55tobereducedfrom402 Ωto335Ω. G In either case, both the gain flatness and the differential gain and phase performance of the OPA820 device provides exceptional results in video-distribution applications. Differential gain and phase measure the change in overall small-signal gain and phase for the color sub-carrier frequency (3.58 MHz in NTSC systems) versus changes in the large-signal output level (which represents luminance information in a composite video signal). The OPA820 device, with the typical 150-Ω load of a single-matched video cable, shows less than 0.01% differential gain and 0.01° phase errors over the standard luminance range for a positive video (negative sync) signal.Similarperformancecanbeobservedformultiplevideosignals,asshowninFigure64. Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 335 (cid:13) 402 (cid:13) 75-(cid:13)(cid:3)Transmission Line 75 (cid:13) OPA820 VOUT Video + Input 75 (cid:13) 75 (cid:13) 75 (cid:13) VOUT 75 (cid:13) 75 (cid:13) VOUT 75 (cid:13) Copyright © 2016, Texas Instruments Incorporated Highoutputcurrentdrivecapabilityallowsthreeback-terminated75-Ωtransmissionlinestobesimultaneouslydriven. Figure64. VideoDistributionAmplifier 10.2.4 SingleDifferentialOpAmp The voltage-feedback architecture of the OPA820 device, with the high common-mode rejection ratio (CMRR), provides exceptional performance in differential amplifier configurations. Figure 65 shows a typical configuration. The starting point for this design is the selection of the R value from 200 Ω to 2 kΩ. Lower values reduce the F required R , increasing the load on the V source and on the OPA820 output. Higher values increase output G 2 noise as well as the effects of parasitic board and device capacitances. Following the selection of R , R must F G be set to achieve the desired inverting gain for V . Remember that the bandwidth is set approximately by the 2 gain bandwidth product (GBP) divided by the noise gain (1 + R / R ). For accurate differential operation (that is, F G goodCMRR),theratioR /R mustbesetequaltoR /R . 2 1 F G Usually,settingtheabsolutevaluesofR andR equaltoR andR (respectively)isbest.Thissettingequalizes 2 1 F G the divider resistances and cancels the effect of input bias currents. However, scaling the values of R and R to 2 1 adjust the loading on the driving source, V , can be useful. In most cases, the achievable low-frequency CMRR 1 is limited by the accuracy of the resistor values. The 85-dB CMRR of the OPA820 device does not determine the overall circuit CMRR unless the resistor ratios are matched to better than 0.003%. If trimming the CMRR is required,R isthesuggestedadjustmentpoint. 2 5 V Power-supply decoupling not shown. R1 V1 + 50 (cid:13) R OPA820 V F(V (cid:16)V ) R2 O RG 1 2 R R when 2 F RG RF R1 RG V2 –5 V Copyright © 2016, Texas Instruments Incorporated Figure65. High-Speed,SingleDifferentialAmplifier 32 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 10.2.5 TripleDifferencingOpAmp(InstrumentationTopology) The primary drawback of the single differential amplifier is the relatively low input impedances of the topology. Where high impedance is required at the differential input, a standard instrumentation amplifier (INA) topology can be built using the OPA820 device as the differencing stage. Figure 66 shows an example of this, in which thetwoinputamplifiersarepackagedtogetherasadualvoltage-feedbackopamp,theOPA2822device. This approach saves board space, cost, and power compared to using two additional OPA820 devices, and still achievesverygoodnoiseanddistortionperformanceasaresultofthemoderateloadingontheinputamplifiers. In this circuit, the common-mode gain to the output is always 1, because of the four matched 500-Ω resistors, whereasthedifferentialgainissetbyEquation16whichisequalto2usingthevaluesinFigure66. 1+2R /R (16) F1 G The differential to single-ended conversion is still performed by the OPA820 output stage. The high-impedance inputs allow the V and V sources to be terminated or impedance-matched as required. If the V and V inputs 1 2 1 2 are already truly differential, such as the output from a signal transformer, then a single-matching termination resistor can be used between them. Remember, however, that a defined DC signal path must always exist for the V and V inputs; for the transformer case, a center-tapped secondary connected to ground would provide an 1 2 optimumDCoperatingpoint. 5 V V1 + OPA2822 5 V RF1 500 (cid:13) 500 (cid:13) + OPA820 VO RG 500 (cid:13) 500 (cid:13) RF1 500 (cid:13) –5 V 500 (cid:13) 500 (cid:13) OPA2822 V2 + –5 V Copyright © 2016, Texas Instruments Incorporated Figure66. Wideband3-DifferencingAmplifier 10.2.6 DACTransimpedanceAmplifier High-frequency digital-to-analog converters (DACs) require a low-distortion output amplifier to retain the SFDR performanceintopracticalloads.Figure67showsasingle-endedoutput-driveimplementation.Inthiscircuit,only one side of the complementary output drive signal is used. Figure 67 shows the signal output current connected intothevirtualground-summingjunctionoftheOPA820device,whichissetupasatransimpedancestageorI-V converter. The unused current output of the DAC is connected to ground. If the DAC requires the outputs to be terminated to a compliance voltage other than ground for operation, then the appropriate voltage level can be appliedtothenoninvertinginputoftheOPA820device. TheDCgainforthiscircuitisequaltoR .Athighfrequencies,theDACoutputcapacitance(C )producesazero F D in the noise gain for the OPA820 device that can cause peaking in the closed-loop frequency response. C is F added across R to compensate for this noise-gain peaking. To achieve a flat transimpedance-frequency F response, this pole in the feedback network must be set to the value shown in Equation 17 which gives a corner frequencyf ofapproximatelyasshowninEquation18. –3dB Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 1 GBP 2SR C 4SR C F F F D (17) GBP f (cid:16)3dB 2SR C F D (18) + OPA820 VO = IDRF High-Speed DAC 500 (cid:13) ID CD CF *%3(cid:3):(cid:3)*DLQ(cid:3)%DQGZLGWK(cid:3) Product (Hz) for the OPA820. ID Copyright © 2016, Texas Instruments Incorporated Figure67. Wideband,Low-DistortionDACTransimpedanceAmplifier 11 Power Supply Recommendations High-speed amplifiers require low-inductance power supply traces and low-ESR bypass capacitors. When possible both power and ground planes must be used in the printed-circuit board design and the power plane must be adjacent to the ground plane in the board stack-up. The power supply voltage must be centered on the desired amplifier output voltage; so for ground referenced output signals, split supplies are required. The power supplyvoltagemustbefrom5Vto12V. 34 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 12 Layout 12.1 Layout Guidelines Achieving optimum performance with a high-frequency amplifier such as the OPA820 device requires careful attention to board layout parasitics and external component types. This section lists recommendations to optimizeperformance. 12.1.1 MinimizingParasiticCapacitance MinimizeparasiticcapacitancetoanyACgroundforallofthesignalI/Opins.Parasiticcapacitanceontheoutput and inverting input pins can cause instability. On the noninverting input, parasitic capacitance can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins must be opened in all of the ground and power planes around those pins. Otherwise, ground and powerplanesmustbeunbrokenelsewhereontheboard. 12.1.2 MinimizingDistancefromPowerSupplytoDecouplingCapacitors Minimize the distance, less than 0.25 inches, from the power-supply pins to high-frequency 0.1-µF decoupling capacitors. At the device pins, the ground and power-plane layout must not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the main supply pins. Place these capacitors somewhat farther from the device. These capacitors can be shared among several devices in thesameareaofthePCB. 12.1.3 SelectingandPlacingExternalComponents Careful selection and placement of external components preserves the high-frequency performance of the OPA820 device. Resistors must be a very-low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also provide good high- frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possibletotheoutputpin.Othernetworkcomponents,suchasnoninvertinginputterminationresistors,mustalso be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 1.5 kΩ, this parasitic capacitance can add a pole, a zero, or both below 500 MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load-driving considerations. A good starting point for design is to set R || R = 200 Ω. G F Using this setting automatically keeps the resistor noise terms low, and minimizes the effect of the parasitic capacitance. 12.1.4 ConnectingOtherWidebandDevices Connections to other wideband devices on the board can be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set R from the plot of Figure 15 (±5 V) S and Figure 42 (5 V). Low parasitic capacitive loads (<5 pF) may not require an R because the OPA820 device S is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R S are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in Figure 7 and Figure 36. With a characteristic board-trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA820 device is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com Layout Guidelines (continued) resistor and input impedance of the destination device; this total effective impedance must be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Figure 15 (±5 V) and Figure 42 (5 V) which does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, some signal attenuationoccursbecauseofthevoltagedividerformedbytheseriesoutputintotheterminatingimpedance. 12.1.5 Socketing TI does not recommend socketing a high-speed part like the OPA820 device. The additional lead length and pin- to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make achieving a smooth, stable frequency response almost impossible. The best results are obtained by solderingtheOPA820deviceontotheboard. 12.2 Layout Example Ground and power plane exist on inner layers Ground and power plane removed Place output resistors close from inner layers to output pins to minimize 1 6 parasitic capacitance Place bypass capacitors Place bypass capacitors close to power pins close to power pins 2 5 + – Place input resistor close to pin 4 to 3 4 minimize stray capacitance Place feedback resistor on the bottom of PCB between pins 4 and 6 Remove GND and Power plane under pins 1 and 4 to minimize stray PCB capacitance Figure68. OPA820LayoutExample 36 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

OPA820 www.ti.com SBOS303D–JUNE2004–REVISEDDECEMBER2016 13 Device and Documentation Support 13.1 Device Support 13.1.1 Design-InTools 13.1.1.1 DemonstrationFixtures Two printed-circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA820 device in the two package options. Both of these boards are offered free of charge as unpopulated PCBs,deliveredwithauser’sguide.Table3listsasummaryinformationforthesefixtures. Table3.DemonstrationFixtures DEVICENUMBER PACKAGE ORDERINGNUMBER USER'SGUIDE OPA820 SOIC(8) DEM-OPA-SO-1A DEM-OPA-SO-1ADemonstrationFixture OPA820 SOT-23(5) DEM-OPA-SOT-1A DEM-OPA-SOT-1ADemonstrationFixture ThedemonstrationfixturescanberequestedthroughtheOPA820productfolder. 13.1.1.2 MacromodelsandApplicationsSupport Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the OPA820 device and the device circuit designs. This is particularly true for video and R amplifier circuits where F parasitic capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA820 device is available through www.ti.com. The applications department is also available for design assistance. These models predict typical small-signal AC, transient steps, DC performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of the data sheet. These models do not attempt to distinguish between the package types in their small-signal AC performance. 13.1.2 DevelopmentSupport FortheOPA820PSpiceModel,seeSBOC048. FortheOPA820TINA-TIReferenceDesign,seeSBOC094. FortheOPA820TINA-TISpiceModel,seeSBOM176. 13.2 Documentation Support 13.2.1 RelatedDocumentation Forrelateddocumentation,seethefollowing: • ADS85014-Bit,10MSPSSelf-CalibratingAnalog-to-DigitalConverter (SBAS154) • DEM-OPA-SO-1ADemonstrationFixture (SBOU009) • DEM-OPA-SOT-1ADemonstrationFixture (SBOU010) • MeasuringBoardParasiticsinHigh-SpeedAnalogDesign (SBOA094) • NoiseAnalysisforHigh-SpeedOpAmps(SBOA066) • OPA2822Dual,Wideband,Low-NoiseOperationalAmplifier (SBOS188) • RLCFilterDesignforADCInterfaceApplications (SBAA108) • Wideband Complementary Current Output DAC to Single-Ended Interface: Improved Matching for the Gain andComplianceVoltageSwing (SBAA135) 13.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. Copyright©2004–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:OPA820

OPA820 SBOS303D–JUNE2004–REVISEDDECEMBER2016 www.ti.com 13.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 13.5 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 13.6 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 13.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 38 SubmitDocumentationFeedback Copyright©2004–2016,TexasInstrumentsIncorporated ProductFolderLinks:OPA820

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA820ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 820 OPA820IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 NSO & no Sb/Br) OPA820IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 NSO & no Sb/Br) OPA820IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 NSO & no Sb/Br) OPA820IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 NSO & no Sb/Br) OPA820IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 820 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF OPA820 : NOTE: Qualified Version Definitions: Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA820IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA820IDR SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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