OPA703 OPA2703 OPA703 OPA4703 OPA704 OPA703 OPA703 OPA2704 OPA703® OPA4704 SBOS180A – MARCH 2001 CMOS, Rail-to-Rail, I/O OPERATIONAL AMPLIFIERS FEATURES DESCRIPTION (cid:1) RAIL-TO-RAIL INPUT AND OUTPUT The OPA703 and OPA704 series op amps are optimized for (cid:1) WIDE SUPPLY RANGE: applications requiring rail-to-rail input and output swing. Single Supply: 4V to 12V Single, dual, and quad versions are offered in a variety of Dual Supplies: ±2 to ±6 packages. While the quiescent current is less than 200µA per (cid:1) LOW QUIESCENT CURRENT: 160µA amplifier, the OPA703 still offers excellent dynamic perfor- mance (1MHz GBW and 0.6V/µs SR) and unity-gain stabil- (cid:1) FULL-SCALE CMRR: 90dB ity. The OPA704 is optimized for gains of 5 or greater and (cid:1) LOW OFFSET: 160µV provides 3MHz GBW and 3V/µs slew rate. (cid:1) HIGH SPEED: The OPA703 and OPA704 series are fully specified and µ OPA703: 1MHz, 0.6V/ s guaranteed over the supply range of ±2V to ±6V. Input µ OPA704: 3MHz, 3V/ s swing extends 300mV beyond the rail and the output swings (cid:1) MicroSIZE PACKAGES: to within 40mV of the rail. SOT23-5, MSOP-8, TSSOP-14 The single versions (OPA703 and OPA704) are available in (cid:1) LOW INPUT BIAS CURRENT: 1pA the MicroSIZE SOT23-5 and in the standard SO-8 surface- mount, as well as the DIP-8 packages. Dual versions APPLICATIONS (OPA2703 and OPA2704) are available in the MSOP-8, (cid:1) AUTOMOTIVE APPLICATIONS: SO-8, and DIP-8 packages. The quad OPA4703 and OPA4704 are available in the TSSOP-14 and SO-14 pack- Audio, Sensor Applications, Security Systems ages. All are specified for operation from –40°C to +85°C. (cid:1) PORTABLE EQUIPMENT (cid:1) ACTIVE FILTERS OPA703 (cid:1) TRANSDUCER AMPLIFIER OPA704 (cid:1) TEST EQUIPMENT NC 1 8 NC (cid:1) DATA ACQUISITION –In 2 7 V+ OPA4703 OPA4704 OPA703 +In 3 6 Out OPA704 Out A 1 14 Out D V– 4 5 NC –In A 2 13 –In D Out 1 5 V+ OPA2703 SO-8, DIP-8 A D V– 2 OPA2704 +In A 3 12 +In D V+ 4 11 V– +In 3 4 –In Out A 1 8 V+ +In B 5 10 +In C A –In A 2 7 Out B B C SOT23-5 –In B 6 9 –In C B +In A 3 6 –In B Out B 7 8 Out C V– 4 5 +In B TSSOP-14, SO-14 MSOP-8, SO-8, DIP-8 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2001, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC Supply Voltage, V+ to V–.................................................................13.2V DISCHARGE SENSITIVITY Signal Input Terminals, Voltage(2).....................(V–) –0.3V to (V+) +0.3V Current(2)....................................................10mA This integrated circuit can be damaged by ESD. Texas Instru- Output Short-Circuit(3)..............................................................Continuous Operating Temperature..................................................–55°C to +125°C ments recommends that all integrated circuits be handled with Storage Temperature.....................................................–65°C to +150°C appropriate precautions. Failure to observe proper handling Junction Temperature....................................................................+150°C and installation procedures can cause damage. Lead Temperature (soldering, 10s)...............................................+300°C ESD damage can range from subtle performance degrada- NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may tion to complete device failure. Precision integrated circuits degrade device reliability. (2) Input terminals are diode-clamped to the power may be more susceptible to damage because very small supply rails. Input signals that can swing more than 0.3V beyond the supply parametric changes could cause the device not to meet its rails should be current-limited to 10mA or less. (3) Short-circuit to ground, one amplifier per package. published specifications. PACKAGE/ORDERING INFORMATION MINIMUM PACKAGE RECOMMENDED DRAWING PACKAGE ORDERING TRANSPORT PRODUCT DESCRIPTION GAIN PACKAGE NUMBER MARKING NUMBER(1) MEDIA OPA703NA Single, GBW = 1MHz 1 SOT23-5 331 A03 OPA703NA/250 Tape and Reel " " " " " " OPA703NA/3K Tape and Reel OPA703UA Single, GBW = 1MHz 1 SO-8 182 OPA703UA OPA703UA Rails " " " " " " OPA703UA/2K5 Tape and Reel OPA703PA Single, GBW = 1MHz 1 DIP-8 006 OPA703PA OPA703PA Rails OPA2703EA Dual, GBW = 1MHz 1 MSOP-8 337 B03 OPA2703EA/250 Tape and Reel " " " " " " OPA2703EA/2K5 Tape and Reel OPA2703UA Dual, GBW = 1MHz 1 SO-8 182 OPA2703UA OPA2703UA Rails " " " " " " OPA2703UA/2K5 Tape and Reel OPA2703PA Dual, GBW = 1MHz 1 DIP-8 006 OPA2703PA OPA2703PA Rails OPA4703EA Quad, GBW = 1MHz 1 TSSOP-14 357 OPA4703EA OPA4703EA/250 Tape and Reel " " " " " " OPA4703EA/2K5 Tape and Reel OPA4703UA Quad, GBW = 1MHz 1 SO-14 235 OPA4703UA OPA4703UA Rails " " " " " " OPA4703UA/2K5 Tape and Reel OPA704NA Single, GBW = 5MHz 5 SOT23-5 331 A04 OPA704NA/250 Tape and Reel " " " " " " OPA704NA/3K Tape and Reel OPA704UA Single, GBW = 5MHz 5 SO-8 182 OPA704UA OPA704UA Tape and Reel " " " " " " OPA704UA/2K5 Tape and Reel OPA704PA Single, GBW = 5MHz 5 DIP-8 006 OPA704PA OPA704PA Rails OPA2704EA Dual, GBW = 5MHz 5 MSOP-8 337 B04 OPA2703EA/250 Tape and Reel " " " " " " OPA2703EA/2K5 Tape and Reel OPA2704UA Dual, GBW = 5MHz 5 SO-8 182 OPA2704UA OPA2704UA Rails " " " " " " OPA2704UA/2K5 Tape and Reel OPA2704PA Dual, GBW = 5MHz 5 DIP-8 006 OPA2704PA OPA2704PA Rails OPA4704EA Quad, GBW = 5MHz 5 TSSOP-14 357 OPA4704EA OPA4704EA/250 Tape and Reel " " " " " " OPA4704EA/2K5 Tape and Reel OPA4704UA Quad, GBW = 5MHz 5 SO-14 235 OPA4704UA OPA4704UA Rails " " " " " " OPA4704UA/2K5 Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /3K indicates 3000 devices per reel). Ordering 3000 pieces of “OPA703NA/3K” will get a single 3000-piece Tape and Reel. OPA703, OPA704 2 SBOS180A

OPA703 ELECTRICAL CHARACTERISTICS: V = 4V to 12V S ° ° Boldface limits apply over the specified temperature range, T = –40 C to +85 C A At T = +25°C, R = 20kΩ connected to V /2 and V = V /2, unless otherwise noted. A L S OUT S OPA703NA, UA, PA OPA2703EA, UA, PA OPA4703EA, UA PARAMETER CONDITION MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage V V = ±5V, V = 0V ±160 ±750 µV OS S CM Drift dV /dT T = –40°C to +85°C ±4 µV/°C OS A vs Power Supply PSRR V = ±2V to ±6V, V = 0V 20 100 µV/V S CM Over Temperature V = ±2V to ±6V, V = 0V 200 µV/V S CM Channel Separation, dc R = 20kΩ 1 µV/V L f = 1kHz 98 dB INPUT VOLTAGE RANGE Common-Mode Voltage Range V (V–) – 0.3 (V+) + 0.3 V CM Common-Mode Rejection Ratio CMRR V = ±5V, (V–) – 0.3V < V < (V+) + 0.3V 70 90 dB S CM over Temperature V = ±5V, (V–) < V < (V+) 68 dB S CM V = ±5V, (V–) – 0.3V < V < (V+) – 2V 80 96 dB S CM over Temperature V = ±5V, (V–) < V < (V+) – 2V 74 dB S CM INPUT BIAS CURRENT Input Bias Current I V = ±5V, V = 0V ±1 ±10 pA B S CM Input Offset Current I V = ±5V, V = 0V ±0.5 ±10 pA OS S CM INPUT IMPEDANCE Differential 4 • 109 || 4 Ω || pF Common-Mode 5 • 1012 || 4 Ω || pF NOISE Input Voltage Noise, f = 0.1Hz to 10Hz V = ±5V, V = 0V 6 µVp-p S CM Input Voltage Noise Density, f = 1kHz e V = ±5V, V = 0V 45 nV/√Hz n S CM Current Noise Density, f = 1kHz i V = ±5V, V = 0V 2.5 fA/√Hz n S CM OPEN-LOOP GAIN Open-Loop Voltage Gain A R = 100kΩ, (V–)+0.1V < V < (V+)–0.1V 120 dB OL L O R = 20kΩ, (V–)+0.075V < V < (V+)–0.075V 100 110 dB L O over Temperature R = 20kΩ, (V–)+0.075V < V < (V+)–0.075V 96 dB L O R = 5kΩ, (V–)+0.15V < V < (V+)–0.15V 100 110 dB L O over Temperature R = 5kΩ, (V–)+0.15V < V < (V+)–0.15V 96 dB L O OUTPUT Voltage Output Swing from Rail R = 100kΩ, A > 80dB 40 mV L OL R = 20kΩ, A > 100dB 75 mV L OL over Temperature R = 20kΩ, A > 96dB 75 mV L OL R = 5kΩ, A > 100dB 150 mV L OL over Temperature R = 5kΩ, A > 96dB 150 mV L OL Output Current I |V – V | < 1V ±10 mA OUT S OUT Short-Circuit Current I ±40 mA SC Capacitive Load Drive C See Typical Performance Curves LOAD FREQUENCY RESPONSE C = 100pF L Gain-Bandwidth Product GBW G = +1 1 MHz Slew Rate SR V = ±5V, G = +1 0.6 V/µs S Settling Time, 0.1% t V = ±5V, 5V Step, G = +1 15 µs S S 0.01% V = ±5V, 5V Step, G = +1 20 µs S Overload Recovery Time V • Gain = V 3 µs IN S Total Harmonic Distortion + Noise THD+N V = ±5V, V = 3Vp-p, G = +1, f = 1kHz 0.02 % S O POWER SUPPLY Specified Voltage Range, Single Supply V 4 12 V S Specified Voltage Range, Dual Supplies V ±2 ±6 V S Operating Voltage Range 3.6 to 12 V Quiescent Current (per amplifier) I I = 0 160 200 µA Q O over Temperature 300 µA TEMPERATURE RANGE Specified Range –40 85 °C Operating Range –55 125 °C Storage Range –65 150 °C Thermal Resistance θ JA SOT23-5 Surface-Mount 200 °C/W MSOP-8 Surface-Mount 150 °C/W TSSOP-14 Surface-Mount 100 °C/W SO-8 Surface Mount 150 °C/W SO-14 Surface Mount 100 °C/W DIP-8 100 °C/W OPA703, OPA704 3 SBOS180A

OPA704 ELECTRICAL CHARACTERISTICS: V = 4V to 12V S ° ° Boldface limits apply over the specified temperature range, T = –40 C to +85 C A At T = +25°C, R = 20kΩ connected to V /2 and V = V /2, unless otherwise noted. A L S OUT S OPA704NA, UA, PA OPA2704EA, UA, PA OPA4704EA, UA PARAMETER CONDITION MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage V V = ±5V, V = 0V ±160 ±750 µV OS S CM Drift dV /dT T = –40°C to +85°C ±4 µV/°C OS A vs Power Supply PSRR V = ±2V to ±6V, V = 0V 20 100 µV/V S CM Over Temperature V = ±2V to ±6V, V = 0V 200 µV/V S CM Channel Separation, dc R = 20kΩ 1 µV/V L f = 1kHz 98 dB INPUT VOLTAGE RANGE Common-Mode Voltage Range V (V–) – 0.3 (V+) + 0.3 V CM Common-Mode Rejection Ratio CMRR V = ±5V, (V–) – 0.3V < V < (V+) + 0.3V 70 90 dB S CM over Temperature V = ±5V, (V–) < V < (V+) 68 dB S CM V = ±5V, (V–) – 0.3V < V < (V+) – 2V 80 96 dB S CM over Temperature V = ±5V, (V–) < V < (V+) – 2V 74 dB S CM INPUT BIAS CURRENT Input Bias Current I V = ±5V, V = 0V ±1 ±10 pA B S CM Input Offset Current I V = ±5V, V = 0V ±0.5 ±10 pA OS S CM INPUT IMPEDANCE Differential 4 • 109 || 4 Ω || pF Common-Mode 5 • 1012 || 4 Ω || pF NOISE Input Voltage Noise, f = 0.1Hz to 10Hz V = ±5V, V = 0V 6 µVp-p S CM Input Voltage Noise Density, f = 1kHz e V = ±5V, V = 0V 45 nV/√Hz n S CM Current Noise Density, f = 1kHz i V = ±5V, V = 0V 2.5 fA/√Hz n S CM OPEN-LOOP GAIN Open-Loop Voltage Gain A R = 100kΩ, (V–)+0.1V < V < (V+)–0.1V 120 dB OL L O R = 20kΩ, (V–)+0.075V < V < (V+)–0.075V 100 110 dB L O over Temperature R = 20kΩ, (V–)+0.075V < V < (V+)–0.075V 96 dB L O R = 5kΩ, (V–)+0.15V < V < (V+)–0.15V 100 110 dB L O over Temperature R = 5kΩ, (V–)+0.15V < V < (V+)–0.15V 96 dB L O OUTPUT Voltage Output Swing from Rail R = 100kΩ, A > 80dB 40 mV L OL R = 20kΩ, A > 100dB 75 mV L OL over Temperature R = 20kΩ, A > 96dB 75 mV L OL R = 5kΩ, A > 100dB 150 mV L OL over Temperature R = 5kΩ, A > 96dB 150 mV L OL Output Current I |V – V | < 1V ±10 mA OUT S OUT Short-Circuit Current I ±40 mA SC Capacitive Load Drive C See Typical Performance Curves LOAD FREQUENCY RESPONSE C = 100pF L Gain-Bandwidth Product GBW G = +5 3 MHz Slew Rate SR V = ±5V, G = +5 3 V/µs S Settling Time, 0.1% t V = ±5V, 5V Step, G = +5 18 µs S S 0.01% V = ±5V, 5V Step, G = +5 21 µs S Overload Recovery Time V • Gain = V 0.6 µs IN S Total Harmonic Distortion + Noise THD+N V = ±5V, V = 3Vp-p, G = +5, f = 1kHz 0.025 % S O POWER SUPPLY Specified Voltage Range, Single Supply V 4 12 V S Specified Voltage Range, Dual Supplies V ±2 ±6 V S Operating Voltage Range 3.6 to 12 V Quiescent Current (per amplifier) I I = 0 160 200 µA Q O over Temperature 300 µA TEMPERATURE RANGE Specified Range –40 85 °C Operating Range –55 125 °C Storage Range –65 150 °C Thermal Resistance θ JA SOT23-5 Surface-Mount 200 °C/W MSOP-8 Surface-Mount 150 °C/W TSSOP-14 Surface-Mount 100 °C/W SO-8 Surface Mount 150 °C/W SO-14 Surface Mount 100 °C/W DIP-8 100 °C/W OPA703, OPA704 4 SBOS180A

TYPICAL CHARACTERISTICS At T = +25°C, V = ±5V, and R = 20kΩ, unless otherwise noted. A S L OPA703 GAIN AND PHASE vs FREQUENCY OPA704 GAIN AND PHASE vs FREQUENCY 120 120 120 120 100 100 100 100 80 80 80 80 60 60 60 60 Gain (dB) 4200 4200 °Phase () Gain (dB) 4200 4200 °Phase () 0 0 0 0 –20 –20 –40 –40 –20 –20 –60 –60 –40 –40 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) CMRR vs FREQUENCY PSRR vs FREQUENCY 120 140 CMRR Limited Range 100 120 100 80 R (dB) 60 CMRR Full Scale R (dB) 80 MR SR 60 C P 40 40 20 20 0 0 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) MAXIMUM AMPLITUDE vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY 7 160 (V+) – (V–) = 12V 6 140 B) 120 5 d V) OPA704 on ( 100 ude ( 4 parati 80 plit 3 Se Am nel 60 2 n OPA703 Cha 40 1 20 0 0 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) OPA703, OPA704 5 SBOS180A

TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = ±5V, and R = 20kΩ, unless otherwise noted. A S L INPUT CURRENT AND VOLTAGE COMMON-MODE REJECTION RATIO SPECTRAL NOISE vs FREQUENCY vs TEMPERATURE 10000 10000 120 Current e 1000 Noise 1000 110 nput Current and Voltag√Spectral Noise nV/Hz 101001 VNooltiasgee 111000 Output Current Spectral√Noise fA/Hz CMRR (dB) 1098000 LiFmuitlel Sd cSacleale I 70 0.1 0.1 60 0.1 1 10 100 1k 10k 100k 1M –80 –60 –40 –20 0 20 40 60 80 100 120 140 Frequency (Hz) Temperature (°C) INPUT BIAS (I ) AND OFFSET (I ) B OS OPEN-LOOP GAIN vs TEMPERATURE CURRENT vs TEMPERATURE 140 100000 10000 130 1000 B) 120 nt (pA) 100 IB d e A (OL110 s Curr 10 IOS a Bi 1 100 0.1 90 0.0 –100 –75 –50 –25 0 25 50 75 100 125 150 175 –50 –25 0 25 50 75 100 125 150 175 Temperature (°C) Temperature (°C) QUIESCENT CURRENT vs TEMPERATURE PSRR vs TEMPERATURE 250 120 110 200 100 150 B) µ (A)Q RR (d 90 I 100 S P 80 50 70 0 60 –100 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 10 25 50 75 100 110 130 150 Temperature (°C) Temperature (°C) OPA703, OPA704 6 SBOS180A

TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = ±5V, and R = 20kΩ, unless otherwise noted. A S L INPUT BIAS CURRENT (I ) B TOTAL HARMONIC DISTORTION PLUS NOISE vs COMMON-MODE VOLTAGE (VCM) (Load = 5kΩ, BW = 8kHz, 1.0Vrms) TEMPERATURE = °25C 1.000 15 10 A) G = +5 p 0.100 OPA704 nt ( 5 D (%) Curre 0 H s T Bia 0.010 ut –5 p n OPA703 I –10 G = +1 0.001 –15 1 10 100 1k 10k 100k –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 Frequency (Hz) Common-Mode Voltage, V (V) CM INPUT BIAS CURRENT (I ) B vs COMMON-MODE VOLTAGE (V ) CM TEMPERATURE = 125°C QUIESCENT CURRENT vs SUPPLY VOLTAGE 15 200 190 10 A) A) 180 Current (n 50 µCurrent ( 117600 Bias cent 150 put –5 uies 140 n Q I –10 130 –15 120 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 2 4 6 8 10 12 14 Common-Mode Voltage, V (V) Supply Voltage (V) CM SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 60 6 I N (Sinking) SC +125°C mA) 50 4 Sourcing +25°C –55°C Current ( 4300 oltage (V) 20 hort-Circuit 20 ISC P (Sourcing) Output V –2 Sinking –55°C S 10 –4 +125°C +25°C 0 –6 2 4 6 8 10 12 14 0 10 20 30 40 50 60 70 Supply Voltage (V) Output Current (±mA) OPA703, OPA704 7 SBOS180A

TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = ±5V, and R = 20kΩ, unless otherwise noted. A S L OPA703 SMALL-SIGNAL OVERSHOOT (%) OPA704 SMALL-SIGNAL OVERSHOOT (%) vs CAPACITIVE LOAD AND GAIN vs CAPACITIVE LOAD 90 90 G = +1 80 80 70 70 %) 60 %) 60 hoot ( 50 G = –1 hoot ( 50 G = +5 s 40 s 40 er er v v O 30 O 30 20 20 G= +5 10 10 0 0 10 100 1k 10k 10 100 1k 10k Load Capacitance Value (pF) Capacitance Load (pF) OPA703 SETTLING TIME vs GAIN OPA704 SETTLING TIME vs GAIN 100 50 90 45 80 40 s) 70 s) µme ( 60 0.01% µme ( 35 0.01% Ti Ti 30 g 50 g n n ettli 40 ettli 25 S S 20 30 0.1% 0.10% 20 15 10 10 1 10 100 1 10 100 Non-Inverting Gain (V/V) Non-Inverting Gain (V/V) VOS PRODUCTION DISTRIBUTION VOS DRIFT PRODUCTION DISTRIBUTION 25 25 20 20 %) %) Frequency ( 1150 Frequency ( 1150 5 5 0 0 0 5 0 5 0 5 0 5 0 5 ≤ 0.6 ≤ 0.4 ≤ 0.3 ≤ 0.1 < 0.0 < 0.1 < 0.3 < 0.4 < 0.6 < 0.7 ≤ 30≤ 27≤ 24≤ 21≤ 18≤ 15≤ 12≤ 9≤ 6≤ 3< 0< 3< 6< 9< 12< 15< 18< 21< 24< 27< 30> 30 Voltage Offset (µV) Voltage Offset (µV/°C) OPA703, OPA704 8 SBOS180A

TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = ±5V, and R = 20kΩ, unless otherwise noted. A S L OPA704 SMALL SIGNAL STEP RESPONSE OPA703 SMALL SIGNAL STEP RESPONSE (G = +5V/V, C = 3pF, R = 100kΩ, F F (G = +1V/V, R = 20kΩ, C = 100pF) C = 100pF, R = 20kΩ,) L L L L v v di di V/ V/ m m 0 0 5 5 5µs/div 5µs/div OPA703 LARGE SIGNAL STEP RESPONSE OPA704 LARGE SIGNAL STEP RESPONSE (G = +1V/V, R = 20kΩ, C = 100pF) (G = +5V/V, R = 20kΩ, C = 3pF, C = 100pF) L L L F L v v di di V/ V/ 1 1 10µs/div 2µs/div OPA703, OPA704 9 SBOS180A

APPLICATIONS INFORMATION Power-supply pins should be bypassed with 1000pF ceramic capacitors in parallel with 1µF tantalum capacitors. OPA703 and OPA704 series op amps can operate on 160µA quiescent current from a single (or split) supply in the range OPERATING VOLTAGE of 4V to 12V (±2V to ±6V), making them highly versatile OPA703 and OPA704 series op amps are fully specified and and easy to use. The OPA703 is unity-gain stable and offers guaranteed from +4V to +12V over a temperature range of 1MHz bandwidth and 0.6V/µs slew rate. The OPA704 is –40ºC to +85ºC. Parameters that vary significantly with optimized for gains of 5 or greater with a 3MHz bandwidth operating voltages or temperature are shown in the Typical and 3V/µs slew rate. Performance Curves. Rail-to-rail input and output swing helps maintain dynamic range, especially in low supply applications. Figure 1 shows RAIL-TO-RAIL INPUT the input and output waveforms for the OPA703 in unity- gain configuration. Operation is from a ±5V supply with a The input common-mode voltage range of the OPA703 series 100kΩ load connected to V /2. The input is a 10Vp-p extends 300mV beyond the supply rails at room temperature. S sinusoid. Output voltage is approximately 10Vp-p. This is achieved with a complementary input stage—an N- channel input differential pair in parallel with a P-channel differential pair, as shown in Figure 2. The N-channel pair is active for input voltages close to the positive rail, typically Input G = +1, VS = ±5V (V+) – 2.0V to 300mV above the positive supply, while the P- channel pair is on for inputs from 300mV below the negative supply to approximately (V+) – 1.5V. There is a small v transition region, typically (V+) – 2.0V to (V+) – 1.5V, in di V/ which both pairs are on. This 500mV transition region can 0 2. vary ±100mV with process variation. Thus, the transition region (both stages on) can range from (V+) – 2.1V to (V+) – 1.4V on the low end, up to (V+) – 1.9V to (V+) – 1.6V on the high end. Within the 500mV transition region PSRR, Output (inverted on scope) CMRR, offset voltage, and offset drift, and THD may vary 200µs/div compared to operation outside this region. FIGURE 1. Rail-to-Rail Input and Output. V+ V O VIN+ VIN– V– FIGURE 2. Simplified Schematic. OPA703, OPA704 10 SBOS180A

INPUT VOLTAGE CAPACITIVE LOAD AND STABILITY The OPA703 and OPA704 series op amps can drive up to Device inputs are protected by ESD diodes that will conduct 1000pF pure capacitive load. Increasing the gain enhances if the input voltages exceed the power supplies by more than the amplifier’s ability to drive greater capacitive loads (see approximately 300mV. Momentary voltages greater than the typical performance curve “Small Signal Overshoot vs 300mV beyond the power supply can be tolerated if the Capacitive Load”). current is limited to 10mA. This is easily accomplished with an input resistor, as shown in Figure 3. Many input signals One method of improving capacitive load drive in the unity- are inherently current-limited to less than 10mA; therefore, gain configuration is to insert a 10Ω to 20Ω resistor inside a limiting resistor is not always required. The OPA703 the feedback loop, as shown in Figure 5. This reduces features no phase inversion when the inputs extend beyond ringing with large capacitive loads while maintaining DC supplies if the input current is limited, as seen in Figure 4. accuracy. +V R S 20Ω I OVERLOAD OPA703 V 10mA max OUT OPA703 VOUT VIN VIN CL RL R V– FIGURE 3. Input Current Protection for Voltages Exceeding the Supply Voltage. FIGURE 5. Series Resistor in Unity-Gain Buffer Configura- tion Improves Capacitive Load Drive. APPLICATION CIRCUITS V = ±5.0V, V = 11Vp-p S IN Figure 6 shows a G = 5 non-inverting amplifier implemented with the OPA703 and OPA704 op amps. It demonstrates the increased speed characteristics (bandwidth, slew rate and settling time) that can be achieved with the OPA704 family v di when used in gains of five or greater. Some optimization of V/ 2.0 feedback capacitor value may be required to achieve best dynamic response. Circuits with closed-loop gains of less than five should use the OPA703 family for good stability and capacitive load drive. The OPA703 can be used in gains greater than five, but will not provide the increased speed benefits of the OPA704 family. 20µs/div The OPA703 series op amps are optimized for driving medium-speed sampling data converters. The OPA703 op FIGURE 4. OPA703—No Phase Inversion with Inputs amps buffer the converter’s input capacitance and resulting Greater than the Power-Supply Voltage. charge injection while providing signal gain. RAIL-TO-RAIL OUTPUT Figure 7 shows the OPA2703 in a dual-supply buffered A class AB output stage with common-source transistors is reference configuration for the DAC7644. The DAC7644 is used to achieve rail-to-rail output. This output stage is a 16-bit, low-power, quad-voltage output converter. Small capable of driving 1kΩ loads connected to any point be- size makes the combination ideal for automatic test equip- tween V+ and ground. For light resistive loads (> 100kΩ), ment, data acquisition systems, and other low-power space- the output voltage can swing to 40mV from the supply rail. limited applications. With moderate resistive loads (20kΩ), the output can swing to within 75mV from the supply rails while maintaining high open-loop gain (see the typical performance curve “Output Voltage Swing vs Output Current”). OPA703, OPA704 11 SBOS180A

3pF 5kΩ 20kΩ 5kΩ 20kΩ OPA703 OPA704 V G = 5 V G = 5 IN IN LARGE-SIGNAL RESPONSE Demonstrates speed improvement that OPA703 can be achieved with OPA704 family in applications with G ≥ 5. v di V/ 2 OPA704 5µs/div FIGURE 6. OPA704 Provides higher Speed in G ≥ 5. NC 48 NC 47 DAC7644 NC 46 NC 45 +V V A Sense 44 OUT V– V A 43 V OUT OUT VREFL AB Sense 42 –2.5V Ref Negative 1/2 Reference VREFL AB 41 OPA2703 500pF V H AB 40 REF V H AB Sense 39 V+ REF 500pF 1/2 VOUTB Sense 38 OPA2703 +2.5V Positive Ref V B 37 V Reference OUT OUT –V FIGURE 7. OPA703 as Dual Supply Configuration-Buffered References for the DAC7644. OPA703, OPA704 12 SBOS180A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA2703EA/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B03 & no Sb/Br) OPA2703EA/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B03 & no Sb/Br) OPA2703EA/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B03 & no Sb/Br) OPA2703EA/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B03 & no Sb/Br) OPA2703UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2703UA OPA2703UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2703UA OPA2703UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2703UA OPA2704EA/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B04 & no Sb/Br) OPA2704EA/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B04 & no Sb/Br) OPA2704UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2704UA OPA2704UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2704UA OPA2704UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2704UA OPA4703EA/250 ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 4703EA OPA4703EA/250G4 ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 4703EA OPA4703EA/2K5 ACTIVE TSSOP PW 14 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 4703EA OPA4703EA/2K5G4 ACTIVE TSSOP PW 14 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 4703EA OPA4703UA ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA4703UA & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA4703UAG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA4703UA & no Sb/Br) OPA4704EA/250 ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 4704EA OPA4704EA/250G4 ACTIVE TSSOP PW 14 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 4704EA OPA4704EA/2K5 ACTIVE TSSOP PW 14 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 4704EA OPA4704UA ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA4704UA & no Sb/Br) OPA703NA/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A03 & no Sb/Br) OPA703NA/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A03 & no Sb/Br) OPA703NA/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A03 & no Sb/Br) OPA703NA/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A03 & no Sb/Br) OPA703PA ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 OPA703PA & no Sb/Br) OPA703UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 703UA OPA703UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 703UA OPA704NA/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A04 & no Sb/Br) OPA704NA/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A04 & no Sb/Br) OPA704NA/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A04 & no Sb/Br) OPA704NA/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A04 & no Sb/Br) OPA704UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 704UA OPA704UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 704UA Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA2703EA/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2703EA/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2703UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2704EA/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2704UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA4703EA/250 TSSOP PW 14 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 OPA4703EA/2K5 TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 OPA4704EA/250 TSSOP PW 14 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 OPA4704EA/2K5 TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 OPA703NA/250 SOT-23 DBV 5 250 178.0 8.4 3.3 3.2 1.4 4.0 8.0 Q3 OPA703NA/3K SOT-23 DBV 5 3000 178.0 8.4 3.3 3.2 1.4 4.0 8.0 Q3 OPA703UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA704NA/250 SOT-23 DBV 5 250 178.0 8.4 3.3 3.2 1.4 4.0 8.0 Q3 OPA704NA/3K SOT-23 DBV 5 3000 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA704UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA2703EA/250 VSSOP DGK 8 250 210.0 185.0 35.0 OPA2703EA/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 OPA2703UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA2704EA/250 VSSOP DGK 8 250 210.0 185.0 35.0 OPA2704UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA4703EA/250 TSSOP PW 14 250 210.0 185.0 35.0 OPA4703EA/2K5 TSSOP PW 14 2500 367.0 367.0 35.0 OPA4704EA/250 TSSOP PW 14 250 210.0 185.0 35.0 OPA4704EA/2K5 TSSOP PW 14 2500 367.0 367.0 35.0 OPA703NA/250 SOT-23 DBV 5 250 565.0 140.0 75.0 OPA703NA/3K SOT-23 DBV 5 3000 565.0 140.0 75.0 OPA703UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA704NA/250 SOT-23 DBV 5 250 565.0 140.0 75.0 OPA704NA/3K SOT-23 DBV 5 3000 565.0 140.0 75.0 OPA704UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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