Product Sample & Technical Tools & Support & Folder Buy Documents Software Community OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 OPA659 Wideband, Unity-Gain Stable, JFET-Input Operational Amplifier 1 Features 3 Description • HighBandwidth:650MHz(G=1V/V) The OPA659 combines a very wideband, unity-gain 1 stable, voltage-feedback operational amplifier with a • HighSlewRate:2550V/μs(4-VStep) JFET-input stage to offer an ultra-high dynamic range • ExcellentTHD: –78dBcat10MHz amplifier for high impedance buffering in data • LowInputVoltageNoise:8.9nV/√Hz acquisition applications such as oscilloscope front- end amplifiers and machine vision applications such • FastOverdriveRecovery:8ns as photodiode transimpedance amplifiers used in • FastSettlingtime(1%4-VStep):8ns waferinspection. • LowInputOffsetVoltage: ±1mV The wide 650-MHz unity-gain bandwidth is • LowInputBiasCurrent:±10pA complementedbyaveryhigh2550-V/μsslewrate. • HighOutputCurrent:70mA The high input impedance and low bias current provided by the JFET input are supported by the low 2 Applications 8.9-nV/√Hz input voltage noise to achieve a very low • High-ImpedanceDataAcquisitionInputAmplifiers integrated noise in wideband photodiode transimpedanceapplications. • High-ImpedanceOscilloscopeInputAmplifiers • WidebandPhotodiodeTransimpedanceAmplifiers Broad transimpedance bandwidths are possible with the high 350-MHz gain bandwidth product of this • WaferScanningEquipment device. • OpticalTime-DomainReflectometry(OTDR) Where lower speed with lower quiescent current is • High-SpeedTime-of-Flight(TOF)Sensing required, consider the OPA656. Where unity-gain stabilityisnotrequired,considertheOPA657. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) SOT-23(5) 2.90mm×1.60mm OPA659 SON(8) 3.00mm×3.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. TypicalApplication TransimpedanceGainvsFrequency +6V 130 R = 1MW, C = Open F F 120 0.1mF 10mF W) RF= 100kW, CF= Open OPA659 VOUT ROUT 50WLoad e Gain(dB 11019000 RCF== 100.50pkFW, RCFF== 1O0pkeWn, c F n R a 80 F ed R = 10kW, C = 1.5pF PDhioodteo ID CD simp 70 F RF=F 1kW, CF= Open CF an 60 Tr 0.1mF 10mF 50 RF= 1kW, CF= 4.7pF -V -6V B 40 100k 1M 10M 100M Frequency (Hz) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 9 ApplicationInformation....................................... 14 2 Applications........................................................... 1 9.1 ApplicationInformation............................................14 3 Description............................................................. 1 9.2 TypicalApplication..................................................18 4 RevisionHistory..................................................... 2 10 PowerSupplyRecommendations..................... 20 5 RelatedOperationalAmplifierProducts.............. 3 11 Layout................................................................... 21 6 PinConfigurationandFunctions......................... 3 11.1 LayoutGuidelines.................................................21 11.2 LayoutExample....................................................22 7 Specifications......................................................... 3 11.3 ThermalPadInformation......................................22 7.1 AbsoluteMaximumRatings......................................3 11.4 SchematicandPCBLayout..................................23 7.2 ESDRatings..............................................................4 11.5 EvaluationModule.................................................24 7.3 RecommendedOperatingConditions.......................4 12 DeviceandDocumentationSupport................. 25 7.4 ThermalInformation..................................................4 7.5 ElectricalCharacteristics...........................................4 12.1 DeviceSupport ....................................................25 7.6 TypicalCharacteristics..............................................6 12.2 CommunityResources..........................................25 12.3 Trademarks...........................................................25 8 DetailedDescription............................................ 13 12.4 ElectrostaticDischargeCaution............................25 8.1 Overview.................................................................13 12.5 Glossary................................................................25 8.2 FeatureDescription.................................................13 13 Mechanical,Packaging,andOrderable 8.3 DeviceFunctionalModes........................................13 Information........................................................... 25 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(August2009)toRevisionC Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 • DeletedTHERMALCHARACTERISTICSrowfromElectricalCharacteristics ..................................................................... 5 ChangesfromRevisionA(March,2009)toRevisionB Page • RemovedleadtemperaturespecificationfromAbsoluteMaximumRatingstable................................................................. 3 • AddedDRBpackagetotestconditionforInputOffsetVoltageparameter,T =–40°Cto85°C.......................................... 5 A • AddedperformancespecificationsforInputOffsetVoltageparameter,DBVpackage.......................................................... 5 • AddedperformancespecificationsforAverageOffsetVoltageDriftparameter,DBVpackage............................................ 5 • Addedfootnote(2)toElectricalCharacteristics(V =±6V)table.......................................................................................... 5 S • Addedparagraph(f)totheBoardLayoutsection................................................................................................................ 22 ChangesfromOriginal(December,2008)toRevisionA Page • ChangedChangedorderinginformationforSOTS23-5(DBV)packageandaddedfootnote;availabilityexpected2Q 2009 ....................................................................................................................................................................................... 3 2 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 5 Related Operational Amplifier Products SLEWRATE VOLTAGENOISE DEVICE V (V) BW(MHz) AMPLIFIERDESCRIPTION S (V/μs) (nV/√Hz) OPA659 ±6 350 2550 8.9 Unity-GainStableFET-Input OPA656 ±5 230 290 7 Unity-GainStableFET-Input OPA657 ±5 1600 700 4.8 Gainof+7stableFETInput LMH6629 5 4000 1600 0.69 Gainof+10stableBipolarInput THS4631 ±15 210 1000 7 Unity-GainStableFET-Input ProgrammableGain(5kΩ/20kΩ) OPA857 5 4750 220 — TransimpedanceAmplifier 6 Pin Configuration and Functions DRBPackage 8-PinVSONWithExposedThermalPad DRVPackage TopView 5-PinSOT23 TopView NC 1 8 NC Output 1 5 +VS Inverting Input 2 7 +VS Noninverting Input 3 6 Output -VS 2 -VS 4 5 NC Noninverting Input 3 4 Inverting Input NC:Notconnected. PinFunctions PIN TYPE DESCRIPTION NAME SOIC SOT-23 1 NC 5 — — NoConnection 8 V 2 4 I InvertingInput IN– V 3 3 I NoninvertingInput IN+ V 6 1 O Outputofamplifier OUT –V 4 2 POW NegativePowerSupply S +V 7 5 POW PositivePowerSupply S 7 Specifications 7.1 Absolute Maximum Ratings Overoperatingfree-airtemperaturerange(unlessotherwisenoted). MIN MAX UNIT PowerSupplyVoltageVS+toVS– ±6.5 V InputVoltage ±VS V InputCurrent 100 mA OutputCurrent 100 mA ContinuousPowerDissipation SeeThermalInformation OperatingFreeAirTemperature,TA –40 85 °C MaximumJunctionTemperature,TJ 150 °C MaximumJunctionTemperature,TJ(continuousoperationforlongtermreliability) 125 °C StorageTemperature,Tstg –65 150 °C Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com 7.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±4000 Charged-devicemodel(CDM),perJEDECspecificationJESD22- V(ESD) Electrostaticdischarge C101(2) ±1000 V Machinemodel(MM) ±200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Totalsupplyvoltage 7 12 13 V S T Ambienttemperature –40 25 85 °C A 7.4 Thermal Information OPA659 THERMALMETRIC(1) DRB(VSON) DRV(SOT23) UNIT 8PINS 5PINS R Junction-to-ambientthermalresistance 56.3 209 °C/W θJA R Junction-to-case(top)thermalresistance 63.7 124 °C/W θJC(top) R Junction-to-boardthermalresistance 31.9 38.1 °C/W θJB ψ Junction-to-topcharacterizationparameter 3.2 15 °C/W JT ψ Junction-to-boardcharacterizationparameter 32.1 37.2 °C/W JB R Junction-to-case(bottom)thermalresistance 15.3 — °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 7.5 Electrical Characteristics AtR =0Ω,G=1V/V,andR =100Ω,T =25°C,V =±6Vunlessotherwisenoted. F L A S TEST PARAMETER TESTCONDITIONS LEVEL(1 MIN TYP MAX UNIT ) ACPERFORMANCE VO=200mVPP,G=1V/V C 650 MHz VO=200mVPP,G=2V/V C 335 MHz Small-SignalBandwidth VO=200mVPP,G=5V/V C 75 MHz VO=200mVPP,G=10V/V C 35 MHz GainBandwidthProduct G>10V/V C 350 MHz Bandwidthfor0.1dBFlatness G=2V/V,VO=2VPP C 55 MHz Large-SignalBandwidth VO=2VPP,G=1V/V B 575 MHz SlewRate VO=4-VStep,G=1V/V B 2550 V/μs RiseandFallTime VO=4-VStep,G=1V/V C 1.3 ns SettlingTimeto1% VO=4-VStep,G=1V/V C 8 ns PulseResponseOvershoot VO=4-VStep,G=1V/V C 12% HarmonicDistortion,2ndharmonic VO=2VPP,G=1V/V,f=10MHz C –79 dBc HarmonicDistortion,3rdharmonic VO=2VPP,G=1V/V,f=10MHz C –100 dBc IntermodulationDistortion,2nd VO=2VPPEnvelope(eachtone1VPP), C –72 dBc intermodulation G=2V/V,f1=10MHz,f2=11MHz IntermodulationDistortion,3rd VO=2VPPEnvelope(eachtone1VPP), C –96 dBc intermodulation G=2V/V,f1=10MHz,f2=11MHz (1) Testlevels:(A)100%testedat25°C.Overtemperaturelimitssetbycharacterizationandsimulation.(B)Limitssetbycharacterization andsimulation.(C)Typicalvalueonlyforinformation. 4 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 Electrical Characteristics (continued) AtR =0Ω,G=1V/V,andR =100Ω,T =25°C,V =±6Vunlessotherwisenoted. F L A S TEST PARAMETER TESTCONDITIONS LEVEL(1 MIN TYP MAX UNIT ) InputVoltageNoise f>100kHz C 8.9 nV/√Hz InputCurrentNoise f<10MHz C 1.8 fA/√Hz DCPERFORMANCE TA=25°C,VCM=0V,RL=100Ω A 52 58 dB Open-LoopVoltageGain(AOL) TA=–40°Cto85°C,VCM=0V,RL=100Ω B 49 55 dB TA=25°C,VCM=0V A ±1 ±5 mV InputOffsetVoltage TA=–40°Cto85°C,VCM=0VDRB DRBpackage B ±1.5 ±7.6 mV package DBVpackage B ±1.5 ±8.9 mV DRBpackage B ±10 ±40 μV/°C Averageinput-offsetvoltagedrift(2) TA=–40°Cto85°C,VCM=0V DBVpackage B ±10 ±60 μV/°C TA=25°C,VCM=0V A ±10 ±50 pA InputBiasCurrent TA=0°Cto70°C,VCM=0V B ±240 ±1200 pA TA=–40°Cto85°C,VCM=0V B ±640 ±3200 pA TA=0°Cto70°C,VCM=0V B ±5 ±26 pA/°C Averageinputbiascurrentdrift TA=–40°Cto85°C,VCM=0V B ±7 ±34 pA/°C TA=25°C,VCM=0V A ±5 ±25 pA InputOffsetCurrent TA=0°Cto70°C,VCM=0V B ±120 ±600 pA TA=–40°Cto85°C,VCM=0V B ±320 ±1600 pA INPUT Common-ModeInputRange(3) TA=25°C A ±3 ±3.5 V TA=–40°Cto85°C B ±2.87 ±3.37 V TA=25°C,VCM=±0.5V A 68 70 dB Common-ModeRejectionRatio TA=–40°Cto85°C,VCM=±0.5V B 64 66 dB InputImpedance Inputimpedance,differential C 1012∥1 Ω∥pF 1012∥ Inputimpedance,common-mode C Ω∥pF 2.5 OUTPUT NoLoad A ±4.6 ±4.8 V TA=25°C, RL=100Ω A ±3.8 ±4 V OutputVoltageSwing NoLoad B ±4.45 ±4.65 V TA=–40°Cto85°C RL=100Ω B ±3.65 ±3.85 V TA=25°C A ±60 ±70 mA OutputCurrent,Sourcing,Sinking TA=–40°Cto85°C B ±56 ±65 mA Closed-LoopOutputImpedance G=1V/V,f=100kHz C 0.04 Ω POWERSUPPLY OperatingVoltage B ±3.5 ±6 ±6.5 V TA=25°C A 30.5 32 33.5 mA QuiescentCurrent TA=–40°Cto85°C B 28.3 35.7 mA TA=25°C,VS=±5.5Vto±6.5V A 58 62 dB Power-SupplyRejectionRatio(PSRR) TA=–40°Cto85°C,VS=±5.5Vto±6.5V A 56 60 dB (2) DRBpackageonly. (3) Tested<6dBbelowminimumspecifiedCMRRat±CMIRlimits. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com 7.6 Typical Characteristics AtV =±6V,R =0Ω,G=1V/V,andR =100Ω,unlessotherwisenoted. S F L Table1.TableofGraphs TITLE FIGURE NoninvertingSmall-SignalFrequencyResponse V =200mV Figure1 O PP NoninvertingLarge-SignalFrequencyResponse V =2V Figure2 O PP NoninvertingLarge-SignalFrequencyResponse V =6V Figure3 O PP InvertingSmall-SignalFrequencyResponse V =200mV Figure4 O PP InvertingLarge-SignalFrequencyResponse V =2V Figure5 O PP InvertingLarge-SignalFrequencyResponse V =6V Figure6 O PP NoninvertingTransientResponse 0.5-VStep Figure7 NoninvertingTransientResponse 2-VStep Figure8 NoninvertingTransientResponse 5-VStep Figure9 InvertingTransientResponse 0.5-VStep Figure10 InvertingTransientResponse 2-VStep Figure11 InvertingTransientResponse 5-VStep Figure12 HarmonicDistortionvsFrequency Figure13 HarmonicDistortionvsNoninvertingGain Figure14 HarmonicDistortionvsInvertingGain Figure15 HarmonicDistortionvsLoadResistance Figure16 HarmonicDistortionvsOutputVoltage Figure17 HarmonicDistortionvs±SupplyVoltage Figure18 Two-Tone,Second-andThird-OrderIntermodulationDistortionvsFrequency Figure19 OverdriveRecovery Gain=2V/V Figure20 OverdriveRecovery Gain=–2V/V Figure21 Input-ReferredVoltageSpectralNoiseDensity Figure22 Common-ModeRejectionRatioandPower-SupplyRejectionRatiovsFrequency Figure23 RecommendedR vsCapacitiveLoad Figure24 ISO FrequencyResponsevsCapacitiveLoad Figure25 Open-LoopGainandPhase Figure26 Closed-LoopOutputImpedancevsFrequency Figure27 TransimpedanceGainvsFrequency C =10pF Figure28 D TransimpedanceGainvsFrequency C =22pF Figure29 D TransimpedanceGainvsFrequency C =47pF Figure30 D TransimpedanceGainvsFrequency C =100pF Figure31 D Maximum/Minimum±V vsR Figure32 OUT LOAD SlewRatevsV Step Figure33 OUT 6 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 AtV =±6V,R =0Ω,G=1V/V,andR =100Ω,unlessotherwisenoted. S F L 4 4 G =+1V/V G =+1V/V 2 2 G = +2V/V G = +2V/V B) 0 B) 0 d d gnal Gain ( ---246 G = +5V/V gnal Gain ( ---246 G = +5V/V Si Si G = +10V/V d -8 d -8 ze G = +10V/V ze ali -10 ali -10 orm -12 VS=±6.0V orm -12 VS=±6.0V N R = 100W N R = 100W -14 L -14 L V = 200mV V = 2V O PP O PP -16 -16 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) Figure1.NoninvertingSmall-SignalFrequencyResponse Figure2.NoninvertingLarge-SignalFrequencyResponse (V =200mV ) (V =2V ) O PP O PP 4 4 G =+1V/V G =-1V/V 2 2 G =-2V/V G = +2V/V B) 0 B) 0 d d al Gain ( --24 G = +5V/V al Gain ( --24 G =-5V/V gn -6 gn -6 Si G = +10V/V Si G =-10V/V d -8 d -8 e e z z ali -10 ali -10 orm -12 VS=±6.0V orm -12 VS=±6.0V N R = 100W N R = 100W -14 L -14 L V = 6V V = 200mV O PP O PP -16 -16 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) Figure3.NoninvertingLarge-SignalFrequencyResponse Figure4.InvertingSmall-SignalFrequencyResponse (VO=6VPP) (VO=200mVPP) 4 4 G =-1V/V G =-2V/V G =-1V/V 2 G =-2V/V 2 B) 0 B) 0 d d al Gain ( --24 G =-5V/V al Gain ( --24 G =-5V/V gn -6 gn -6 Si G =-10V/V Si G =-10V/V d -8 d -8 e e z z ali -10 ali -10 orm -12 VS=±6.0V orm -12 VS=±6.0V N R = 100W N R = 100W -14 L -14 L V = 2V V = 6V O PP O PP -16 -16 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) Figure5.InvertingLarge-SignalFrequencyResponse Figure6.InvertingLarge-SignalFrequencyResponse (V =2V ) (V =6V ) O PP O PP Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com AtV =±6V,R =0Ω,G=1V/V,andR =100Ω,unlessotherwisenoted. S F L 0.3 1.5 V V OUT OUT V V 0.2 IN 1.0 IN 0.1 0.5 V) V) ( ( OUT 0 OUT 0 V V /N /N VI -0.1 VI -0.5 -0.2 -1.0 -0.3 -1.5 0 10 20 30 40 50 0 10 20 30 40 50 Time (ns) Time (ns) Figure7.NoninvertingTransientResponse(0.5-VStep) Figure8.NoninvertingTransientResponse(2-VStep) 3.5 0.3 V OUT V 2.5 IN 0.2 V OUT 1.5 VIN 0.1 V) V) ( 0.5 ( OUT OUT 0 /VN -0.5 /VN VI VI -0.1 -1.5 -2.5 -0.2 -3.5 -0.3 0 10 20 30 40 50 0 10 20 30 40 50 Time (ns) Time (ns) Figure9.NoninvertingTransientResponse(5-VStep) Figure10.InvertingTransientResponse(0.5-VStep) 1.5 3.5 VOUT VOUT 1.0 VIN 2.5 VIN 1.5 0.5 V) V) ( ( 0.5 OUT 0 OUT /VN /VN -0.5 VI -0.5 VI -1.5 -1.0 -2.5 -1.5 -3.5 0 10 20 30 40 50 0 10 20 30 40 50 Time (ns) Time (ns) Figure11.InvertingTransientResponse(2-VStep) Figure12.InvertingTransientResponse(5-VStep) 8 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 AtV =±6V,R =0Ω,G=1V/V,andR =100Ω,unlessotherwisenoted. S F L -50 -50 VGS == 1±V6/.V0V Second -55 VRS== 1±060.0WV HSaermcoonndic ortion (dBc) --6700 RRVOFLU==T 10=0W 20VWPP Harmonic ortion (dBc) ---667050 Vf =OL U1T0=M 2HVzPP st -80 st -75 Di Di c c -80 Third Harmoni -1-0900 HaTrmhirodnic Harmoni --8950 Harmonic -95 -110 -100 1 10 100 0 2 4 6 8 10 Frequency (MHz) Noninverting Gain (V/V) Figure13.HarmonicDistortionvsFrequency Figure14.HarmonicDistortionvsNoninvertingGainat 10MHz -50 -50 -55 VRS== 1±060.0WV HSaermcoonndic -55 VGSai=n ±=6 1.0VV/V L n (dBc) --6605 Vf =O U1T0=M 2HVzPP n (dBc) --6605 RVf =OF U1=T0 0=MW 2HVzPP ortio -70 ortio -70 st -75 st -75 Di Di Second nic -80 Third nic -80 Harmonic mo -85 Harmonic mo -85 Har -90 Har -90 Third Harmonic -95 -95 -100 -100 0 2 4 6 8 10 0 100 200 300 400 500 600 700 800 900 1k Inverting Gain (V/V) RLOAD(W) Figure15.HarmonicDistortionvsInvertingGainat10MHz Figure16.HarmonicDistortionvsLoadResistanceat 10MHz -50 -70 V =±6.0V on (dBc) --6700 GRRf =SFLa i=1=n0 10=M0W 1H0VWz/V HSaermc6oonndic on (dBc) ---788505 HSaermc6oonndic orti orti st -80 st -90 Di Third Di onic -90 Harmonic onic -95 HaTrmhirodnic arm arm -100 f = 10MHz H -100 H -105 GRLai=n 1=0 +02WV/V V =2V -110 -110 OUT PP 0 2 4 6 4.0 4.5 5.0 5.5 6.0 VOUT(VPP) ±Supply Voltage (V) Figure17.HarmonicDistortionvsOutputVoltage Figure18.HarmonicDistortionvs±SupplyVoltage Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com AtV =±6V,R =0Ω,G=1V/V,andR =100Ω,unlessotherwisenoted. S F L -40 3 6 Second-Order VIN VS=±6.0V Bc) -50 2 Left Scale RL= 100W 4 d Gain = +2V/V n ( ortio -60 Third-Order 1 2 odulation Dist --7800 VRS== ±160.00WV V(V)IN -01 RigVhtO SUTcale 0-2 OUTV(V) m L nter -90 Two-Tone, 1GMaHinz S= p+a2cVin/Vg -2 -4 I 1V Each Tone -100 PP -3 -6 0 50 100 150 0 20 40 60 80 100 120 Frequency (MHz) Time (ns) Figure19.Two-Tone,Second-andThird-OrderIMDvs Figure20.OverdriveRecovery(Gain=2V/V) Frequency 3 6 1000 21 LeftV SINcale RigVhtO SUTcale 42 Öoise (nV/)HzÖoise (fA/Hz) 100 NN V(V)IN -01 0-2 OUTV(V) ed Voltage ed Current 10 IVnoplutat-gRee Nfeorriseed errerr V =±6.0V efef Input-R6eferred -2 RGSLai=n 1=0-02WV/V -4 nput-Rnput-R Current Noise -3 -6 II 1 0 20 40 60 80 100 120 10 100 1k 10k 100k 1M 10M Time (ns) Frequency (Hz) Figure21.OverdriveRecovery(Gain=–2V/V) Figure22.Input-ReferredVoltageandCurrentNoiseDensity 80 100 +PSRR 70 60 B) -PSRR d RR ( 50 CMRR W) R, PS 40 R(ISO 10 R 30 M C 20 10 0 1 100k 1M 10M 100M 10 100 1000 Frequency (Hz) Capacitive Load (pF) Figure23.Common-ModeRejectionRatioandPower- Figure24.RecommendedR vsCapacitiveLoad ISO SupplyRejectionRatiovsFrequency (R =1kΩ) LOAD 10 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 AtV =±6V,R =0Ω,G=1V/V,andR =100Ω,unlessotherwisenoted. S F L 5 60 0 C = 10pF, R = 30.1W L ISO 50 0 C = 100pF, R = 12.1W B) 40 -45 O Gain (dB) --11-055 LCL= 1000pISFO, RISO= 5W en-Loop Gain (d 321000 AOLPhase AOLGain -90 pen-Loop Phase Op 0 -135 ()° -20 V =±6.0V -10 S G = +1V/V -25 -20 -180 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) Figure25.FrequencyResponsevsCapacitiveLoad Figure26.Open-LoopGainandPhase (R =1kΩ) LOAD 1k 130 V =±6.0V R = 1MW, C = Open Wutput Impedance () 10100 GS = +1V/V Wance Gain (dB) 1112109800000 RCFF== 100.205kpWFF, RF=F 100kW,R CCFFF=== 1 OO0ppkeWenn, op O 1 mped 70 RF= 10kW, CF= 1pF sed Lo 0.1 Transi 60 RF= 1kW, CF= Open Clo 50 R = 1kW, C = 3.3pF F F 0.01 40 100k 1M 10M 100M 1G 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure27.Closed-LoopOutputImpedancevsFrequency Figure28.TransimpedanceGainvsFrequency(C =10pF) D 130 130 R = 1MW, C = Open R = 1MW, C = Open F F F F 120 120 W) RF= 100kW, CF= Open W) RF= 1MW, RF= 100kW, CF= Open (dB 110 RF= 10kW, (dB 110 CF= 0.25pF RF= 10kW, nce Gain 10900 RCFF== 100.50pkFW, CF= Open nce Gain 10900 RCFF== 100.50pkFW, CF= Open a 80 a 80 simped 70 RF= 10kWR, FC=F 1=k 1W.5, pCFF= Open simped 70 RF= 10kW, CRFF== 1 1.5kpWF, CF= Open an 60 an 60 Tr Tr R = 1kW, C = 4.7pF 50 R = 1kW, C = 4.7pF 50 F F F F 40 40 100k 1M 10M 100M 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure29.TransimpedanceGainvsFrequency(C =22pF) Figure30.TransimpedanceGainvsFrequency(C =47pF) D D Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com AtV =±6V,R =0Ω,G=1V/V,andR =100Ω,unlessotherwisenoted. S F L 130 5 R = 1MW, C = Open F F 120 4 W(dB) 110 RCFF== 10M.2W5p,F RF= 100RkFW=, C1F0k=W O, pCeFn= Open 32 VOUTHigh n 100 mpedance Gai 987000 RFRC=FF ==1 010k0.5W0p,k FWCF,= 1.5pF RCFF== 1OkpWe,n ±V(V)OUT --1012 VRGSF === + ±2164V.90/WVV si an 60 -3 Tr 50 RF= 1kW, CF= 4.7pF -4 VOUTLow 40 -5 100k 1M 10M 100M 10 100 1000 Frequency (Hz) R (W) LOAD Figure31.TransimpedanceGainvsFrequency Figure32.Maximum/Minimum±VOUTvsRLOAD (C =100pF) D 3000 VS=±6.0V Ris6ing G = +2V/V Slew Rate R = 100W LOAD Falling s) 2000 Slew Rate m V/ e ( at R w Sle 1000 0 0 1 2 3 4 5 V / V (V) OUT STEP Figure33.SlewRatevsV Step OUT 12 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 8 Detailed Description 8.1 Overview The OPA659 is high gain-bandwidth, voltage feedback operational amplifier featuring a low noise JFET input stage. The OPA659 is compensated to be unity gain stable. The OPA659 finds wide use in optical front-end applicationsandintestandmeasurementsystemsthatrequirehighinputimpedance. 8.2 Feature Description 8.2.1 InputandESDProtection The OPA659 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies,asFigure34shows. +V CC External Internal Pin Circuitry -V CC Figure34. InternalESDProtection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30-mA continuous current. Where higher currents are possible (for example, in systems with ±12-V supply parts driving into the OPA659), current limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible because high values degrade both noise performanceandfrequencyresponse. 8.3 Device Functional Modes 8.3.1 Split-SupplyOperation(±3.5Vto ±6.5V) To facilitate testing with common lab equipment, the OPA659 may be configured to allow for split-supply operation. This configuration eases lab testing because the mid-point between the power rails is ground, and mostsignalgenerators,networkanalyzers,oscilloscopes,spectrumanalyzersandotherlabequipmentreference their inputs and outputs to ground. Figure 36 and Figure 37 show the OPA659 configured in a simple noninverting and inverting configuration respectively with ±6-V supplies. The input and output will swing symmetrically around ground. Due to its ease of use, split-supply operation is preferred in systems where signals swingaroundground,butitrequiresgenerationoftwosupplyrails. 8.3.2 Single-SupplyOperation(7Vto13V) Many newer systems use single power supply to improve efficiency and reduce the cost of the extra power supply. The OPA659 is designed for use with split-supply configuration; however, it can be used with a single- supply with no change in performance, as long as the input and output are biased within the linear operation of the device. To change the circuit from split supply to single supply, level shift all the voltages by 1/2 the difference between the power supply rails. An additional advantage of configuring an amplifier for single-supply operationisthattheeffectsof–PSRRwillbeminimizedbecausethelowsupplyrailhasbeengrounded. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com 9 Application Information NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information 9.1.1 Wideband,NoninvertingOperation The OPA659 is a very broadband, unity-gain stable, voltage-feedback amplifier with a high impedance JFET- input stage. Its very high gain bandwidth product (GBP) of 350 MHz can be used to either deliver high signal bandwidths for low-gain buffers, or to deliver broadband, low-noise, transimpedance bandwidth to photodiode- detector applications. The OPA659 is designed to provide very low distortion and accurate pulse response with low overshoot and ringing. To achieve the full performance of the OPA659, careful attention to printed-circuit board (PCB) layout and component selection are required, as discussed in the remaining sections of this data sheet. Figure 35 shows the noninverting gain of +1 circuit; Figure 36 shows the more general circuit used for other noninverting gains. These circuits are used as the basis for most of the noninverting gain Typical Characteristics graphs. Most of the graphs were characterized using signal sources with 50-Ω driving impedance, and with measurement equipment presenting a 50-Ω load impedance. In Figure 35, the shunt resistor R at V should be T IN set to 50 Ω to match the source impedance of the test generator and cable, while the series output resistor, R , at V should also be set to 50 Ω to provide matching impedance for the measurement equipment load OUT OUT and cable. Generally, data sheet voltage swing specifications are measured at the output pin, V , in Figure 35 OUT andFigure36. +6V 0.1mF 10mF V 50WSource IN VOUT ROUT 50WLoad OPA659 R T 0.1mF 10mF -6V Figure35. NoninvertingGainof+1TestCircuit Voltage-feedback op amps can use a wide range of resistor values to set the gain. To retain a controlled frequencyresponseforthenoninvertingvoltageamplifierofFigure36,theparallelcombinationofR ||R should F G always be less than 200 Ω. In the noninverting configuration, the parallel combination of R || R forms a pole with the parasitic input and board layout capacitance at the inverting input of the OPA659. F G For best performance, this pole should be at a frequency greater than the closed-loop bandwidth for the OPA659. For this reason, TI recommends a direct short from the output to the inverting input for the unity-gain follower application. Table 2 lists several recommended resistor values for noninverting gains with a 50-Ω input andoutputmatch. 14 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 Application Information (continued) +6V 0.1mF 10mF V 50WSource IN VOUT ROUT 50WLoad OPA659 R T R F R G 0.1mF 10mF -6V Figure36. GeneralNoninvertingTestCircuit Table2.ResistorValuesforNoninvertingGainsWith50-ΩInput/OutputMatch NONINVERTINGGAIN R R R R F G T OUT +1 0 Open 49.9 49.9 +2 249 249 49.9 49.9 +5 249 61.9 49.9 49.9 +10 249 27.4 49.9 49.9 9.1.2 Wideband,InvertingGainOperation The circuit of Figure 37 shows the inverting gain test circuit used for most of the inverting Typical Characteristics graphs. As with the noninverting applications, most of the curves were characterized using signal sources with 50-Ω driving impedance, and with measurement equipment that presents a 50-Ω load impedance. In Figure 37, the shunt resistor R at V should be set so the parallel combination of the shunt resistor and R equals 50 Ω to T IN G matchthesourceimpedanceofthetestgeneratorandcable,whiletheseriesoutputresistorR atV should OUT OUT also be set to 50 Ω to provide matching impedance for the measurement equipment load and cable. Generally, datasheetvoltageswingspecificationsaremeasuredattheoutputpin,V ,inFigure37. OUT +6V 0.1mF 10mF VOUT ROUT 50WLoad OPA659 50WSource VIN RG RF R T 0.1mF 10mF -6V Figure37. GeneralInvertingTestCircuit Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com The inverting circuit can also use a wide range of resistor values to set the gain; Table 3 lists several recommendedresistorvaluesforinvertinggainswitha50-Ω inputandoutputmatch. Table3.ResistorValuesForInvertingGainsWith50-ΩInput/OutputMatch INVERTINGGAIN R R R R F G T OUT –1 249 249 61.9 49.9 –2 249 124 84.5 49.9 –5 249 49.9 Open 49.9 –10 499 49.9 Open 49.9 Figure 37 shows the noninverting input tied directly to ground. Often, a bias current-cancelling resistor to ground is included here to nullify the DC errors caused by input bias current effects. For a JFET input op amp such as the OPA659, the input bias currents are so low that dc errors caused by input bias currents are negligible. Thus, TIdoesnotrecommendabiascurrent-cancellingresistoratthenoninvertinginput. 9.1.3 OperatingSuggestions 9.1.3.1 SettingResistorValuesToMinimizeNoise The OPA659 provides a very low input noise voltage. To take full advantage of this low input noise, designers mustpaycarefulattentiontootherpossiblenoisecontributors.Figure38showstheopampnoiseanalysismodel with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current densitytermsineithernV/√HzorpA/√Hz. e N RT IBN OPA659 eO 4kTR T R F I BI 4kTR F 4kT R R G G Figure38. OpAmpNoiseAnalysisModel The total output spot noise voltage can be computed as the square root of the squared contributing terms to the outputnoisevoltage.Thiscomputationaddsallthecontributingnoisepowersattheoutputbysuperposition,then takes the square root to arrive at a spot noise voltage. Equation 1 shows the general form for this output noise voltageusingthetermsshowninFigure38. 2 e = [4kTR + (I R )2+ e 2] 1 + RF + (I R )2+ 4kTR 1 + RF O T BN T N R BI F F R G G (1) Dividingthisexpressionbythenoisegain(G =1+R /R )givestheequivalentinput-referredspotnoisevoltage N F G atthenoninvertinginput,asEquation2 shows. 2 I R 4kTR eNI= 4kTRT+ (IBNRT)2+ eN2+ NoisBeI GFain + Noise GFain (2) space space 16 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 Putting high resistor values into Equation 2 can quickly dominate the total equivalent input-referred noise. A source impedance on the noninverting input of 5 kΩ adds a Johnson voltage noise term equal to that of the amplifier alone (8.9 nV/Hz). While the JFET input of the OPA659 is ideal for high source impedance applications in the noninverting configuration of Figure 35 or Figure 36, both the overall bandwidth and noise are limited by highsourceimpedances. 9.1.3.2 FrequencyResponseControl Voltage-feedback op amps such as the OPA659 exhibit decreasing signal bandwidth as the signal gain increases. In theory, this relationship is described by the gain bandwidth product (GBP) shown in the Electrical Characteristics. Ideally, dividing the GBP by the noninverting signal gain (also called the Noise Gain, or NG) can predict the closed-loop bandwidth. In practice, this guideline is valid only when the phase margin approaches 90 degrees, as it does in high gain configurations. At low gains (with increased feedback factors), most high-speed amplifiers exhibit a more complex response with lower phase margins. The OPA659 is compensated to give a maximally-flat frequency response at a noninverting gain of +1 (see Figure 35). This compensation results in a typical gain of +1 bandwidth of 650 MHz, far exceeding that predicted by dividing the 350-MHz GBP by 1. Increasing the gain causes the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the OPA659 shows the 35-MHz bandwidth predicted using the simple formula and the typical GBP of 350 MHz. Unity-gain stable op amps such as the OPA659 can also be band-limited in gains other than +1 by placing a capacitor across the feedback resistor. For the noninverting configuration of Figure 36, a capacitor across the feedback resistor decreases the gain with frequency down to a gain of +1. For instance, to band-limit a gain of +2 design to 20 MHz, a 32-pF capacitor can be placed in parallel with the 249-Ω feedback resistor. This configuration, however, only decreases the gain from 2 to 1. Using a feedback capacitor to limit the signal bandwidth is more effective in the inverting configuration of Figure 37. Adding that same capacitance to the feedback of Figure 37 sets a pole in the signal frequency response at 20 MHz, but in this case it continues to attenuate the signal gain to less than 1. Note, however, that the noise gain ofthecircuitisonlyreducedtoagainof1withtheadditionofthefeedbackcapacitor. 9.1.3.3 DrivingCapacitiveLoads One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. The OPA659 is very robust, but care should be taken with light loading scenarios so that output capacitance does not decreasestabilityandincreaseclosed-loopfrequencyresponsepeakingwhenacapacitiveloadisplaceddirectly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor, R , between the amplifier output and the capacitive ISO load. In effect, this resistor isolates the phase shift from the loop gain of the amplifier, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended R versus capacitive load ISO and the resulting frequency response with a 1-kΩ load (see Figure 24). Note that larger R values are required ISO forlowercapacitiveloading.Inthiscase,adesigntargetofamaximally-flatfrequencyresponsewasused.Lower values of R may be used if some peaking can be tolerated. Also, operating at higher gains (instead of the +1 ISO gain used in the Typical Characteristics) requires lower values of R for a minimally-peaked frequency ISO response. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA659. Moreover, long PCB traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possibletotheOPA659outputpin(seetheLayout section). With heavier loads (for example, the 100-Ω load presented in the test circuits and used for testing typical characteristic performance), the OPA659 is very robust; R can be as low as 10 Ω with capacitive loads less ISO than5pFandcontinuetoshowaflatfrequencyresponse. space space Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com 9.1.3.4 DistortionPerformance The OPA659 is capable of delivering a low distortion signal at high frequencies over a wide range of gains. The distortion plots in the Typical Characteristics show the typical distortion under a wide variety of conditions. Generally,untilthefundamentalsignalreachesveryhighfrequenciesorpowers,thesecondharmonicdominates the distortion with a negligible third harmonic component. Focusing then on the second harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network: in the noninverting configuration, this network is the sum of R + R , while in the inverting configuration the network is F G only R (see Figure 36). Increasing the output voltage swing directly increases harmonic distortion. A 6dB F increase in output swing generally increases the second harmonic by 12 dB and the third harmonic by 18 dB. Increasing the signal gain also increases the second-harmonic distortion. Again, a 6-dB increase in gain increases the second and third harmonics by about 6 dB, even with a constant output power and frequency. Finally, the distortion increases as the fundamental frequency increases because of the rolloff in the loop gain with frequency. Conversely, the distortion improves going to lower frequencies, down to the dominant open-loop poleatapproximately300kHz. Note that power-supply decoupling is critical for harmonic distortion performance. In particular, for optimal second-harmonicperformance,thepower-supplyhigh-frequency0.1-μFdecouplingcapacitorstothepositiveand negativesupplypinsshouldbebroughttoasinglepointgroundlocatedawayfromtheinputpins. The OPA659 has an extremely low third-order harmonic distortion. This characteristic also shows up in the two- tone, third-order intermodulation spurious (IMD3) response curves (see Figure 19). The third-order spurious levels are extremely low (less than –100 dBc) at low output power levels and frequencies below 10 MHz. The output stage continues to hold these levels low even as the fundamental power reaches higher levels. As with mostopamps,thespuriousintermodulationpowersdonotincreaseaspredictedbyatraditionalinterceptmodel. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centeredat10MHz,with–2dBm/toneintoamatched50-Ω load(thatis,0.5V foreachtoneattheload,which PP requires 2 V for the overall two-tone envelope at the output pin), the Typical Characteristics show a 96-dBc PP difference between the test tones and the third-order intermodulation spurious levels. This exceptional performanceimprovesfurtherwhenoperatingatlowerfrequenciesand/orhigherloadimpedances. 9.2 Typical Application The high GBP and low input voltage and current noise for the OPA659 make it an ideal wideband, transimpedance amplifier for low to moderate transimpedance gains. Higher transimpedance gains (above 100 kΩ) can benefit from the low input noise current of a JFET input op amp such as the OPA659. Designs that requirehighbandwidthfromalargeareadetectorcanbenefitfromthelowinputvoltagenoisefortheOPA659. +6V 0.1mF 10mF VOUT ROUT 50WLoad OPA659 R F l Photo I C Diode D D C F 0.1mF 10mF -VB -6V Figure39. Wideband,Low-Noise,TransimpedanceAmplifier(TIA) 18 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 Typical Application (continued) 9.2.1 DesignRequirements Designahigh-gaintransimpedanceamplifierwiththespecificationsshowninTable4. Table4.DesignParameters PARAMETER VALUE Closedloopbandwidth(MHz) 7.5MHz Transimpedancegain 10KΩ Photodiodecapacitance 100pF 9.2.2 DetailedDesignProcedure The input voltage noise of a transimpedance amplifier is peaked up over frequency by the diode source capacitance, and in many cases, may become the limiting factor to input sensitivity. The key elements to the design are the expected diode capacitance (C ) with the reverse bias voltage (–V ) applied, the desired D B transimpedance gain, R , and the GBP for the OPA659 (350 MHz). Figure 39 shows a general transimpedance F amplifier circuit, or TIA, using the OPA659. Given the source diode capacitance plus parasitic input capacitance for the OPA659, the transimpedance gain, and known GBP, the feedback capacitor value, C , may be calculated F toavoidexcessivepeakinginthefrequencyresponse. Toachieveamaximallyflatsecond-orderButterworthfrequencyresponse,thefeedbackpoleshouldbesetto: 1 GBP = 2pR C 4pR C F F F D (3) For example, adding the common mode and differential mode input capacitance (0.7 + 2.8 = 3.5)pF to the diode source with the 20-pF capacitance, and targeting a 100-kΩ transimpedance gain using the 350-MHz GBP for the OPA659, requires a feedback pole set to 3.44 MHz. This pole in turn requires a total feedback capacitance of 0.46 pF. Typical surface mount resistors have a parasitic capacitance of 0.2 pF, leaving the required 0.26 pF value to achieve the required feedback pole. This calculation gives an approximate 4.9 MHz, –3-dB bandwidth computedby: GBP f = -3dB 2pR C F D (4) Table 5 lists the calculated component values and –3-dB bandwidths for various TIA gains and diode capacitance. Table5.OPA659TIAComponentValuesandBandwidthforVariousDiodeCapacitanceandGains C R C f D F F –3dB C =10pF DIODE 13.5pF 1kΩ 3.50pF 64.24MHz 13.5pF 10kΩ 1.11pF 20.31MHz 13.5pF 100kΩ 0.35pF 6.42MHz 13.5pF 1MΩ 0.11pF 2.03MHz C =20pF DIODE 23.5pF 1kΩ 4.62pF 48.69MHz 23.5pF 10kΩ 1.46pF 15.40MHz 23.5pF 100kΩ 0.46pF 4.87MHz 23.5pF 1MΩ 0.15pF 1.54MHz C =50pF DIODE 53.5pF 1kΩ 6.98pF 32.27MHz 53.5pF 10kΩ 2.21pF 10.20MHz 53.5pF 100kΩ 0.70pF 3.23MHz 53.5pF 1MΩ 0.22pF 1.02MHz Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com Table5.OPA659TIAComponentValuesandBandwidthforVariousDiodeCapacitanceand Gains(continued) C R C f D F F –3dB C =100pF DIODE 103.5pF 1kΩ 9.70pF 23.20MHz 103.5pF 10kΩ 3.07pF 7.34MHz 103.5pF 100kΩ 0.97pF 2.32MHz 103.5pF 1MΩ 0.31pF 0.73MHz 9.2.3 ApplicationCurves 1000 1000 (cid:151)put Noise (nV/Hz) 10100 (cid:151)659 Noise (nV/Hz) 10100 Out OPA 1 1 10k 100k 1M 10M 100M 10k 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) C001 C002 Figure40.SimulatedTotalOutputNoise Figure41.MeasuredTotalOutputNoise 80 75 70 B) 65 d ut ( 60 p ut O 55 50 45 40 1k 10k 100k 1M 10M 100M Frequency (Hz) C003 Figure42.MeasuredTransimpedanceBandwidth 10 Power Supply Recommendations The OPA659 is intended for operation on ±6-V supplies. Single-supply operation is allowed with minimal change from the stated specifications and performance from a single supply of 7 V to 13 V maximum. The limit to lower supply voltage operation is the useable input voltage range for the JFET-input stage. Operating from a single supply can have numerous advantages. With the negative supply at ground, the DC errors due to the –PSRR term can be minimized. Typically, AC performance improves slightly at 13-V operation with minimal increase in supplycurrent. 20 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 11 Layout 11.1 Layout Guidelines Achievingoptimumperformancewithahigh-frequencyamplifiersuchastheOPA659requirescarefulattentionto PCB layout parasitics and external component types. Recommendations that can optimize device performance includethefollowing 1. Minimize parasitic capacitance to any AC ground for all of the signal input/output (I/O) pins. Parasitic capacitanceontheoutputandinvertinginputpinscancauseinstability:onthenoninvertinginput,itcanreact with the source impedance to cause unintentional band-limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise,groundandpowerplanesshouldbeunbrokenelsewhereontheboard. 2. Minimize the distance (less than 0.25 inches, or 6.35 mm) from the power-supply pins to the high- frequency, 0.1-μF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Use a single point ground, located away from the input pins, for the positive and negative supply high-frequency, 0.1-μF decoupling capacitors. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2 μF to 10 μF) decoupling capacitors, effective at lower frequencies, should also be used on the supply pins. These larger capacitors may be placed somewhat farther from the device and may be shared among several devices in the same areaofthePCB. 3. Careful selection and placement of external components preserves the high-frequency performance of the OPA659. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wirewound-type resistors in a high-frequency application. The inverting input pin is the most sensitive to parasitic capacitance; consequently, always position the feedback resistor as close to the negative input as possible. The output is also sensitive to parasitic capacitance; therefore, position a series output resistor (in thiscase,R )asclosetotheoutputpinaspossible.Othernetworkcomponents,suchasnoninvertinginput ISO termination resistors, should also be placed close to the package. Even with a low parasitic capacitance, excessively high resistor values can create significant time constants that can degrade device performance. Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 1.5 kΩ, this parasitic capacitance can add a pole and/or zero below 500 MHz that can affect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. TI recommends keeping R || R less than 250 Ω. This low value ensures that the resistor F G noise terms remain low, and minimizes the effects of the parasitic capacitance. Transimpedance applications (for example, see Figure 39) can use the feedback resistor required by the application as long as the feedback compensation capacitor is set given consideration to all parasitic capacitance terms on the invertingnode. 4. Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils, or 1.27 cm to 2.54 cm) should be used. EstimatethetotalcapacitiveloadandsetR fromFigure24.Lowparasiticcapacitiveloads(lessthan5pF) ISO may not need an R because the OPA659 is nominally compensated to operate with a 2-pF parasitic load. ISO Higher parasitic capacitive loads without an R are allowed as the signal gain increases (increasing the ISO unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA659 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6- dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series- terminated at the source end only. Treat the trace as a capacitive load in this case, and set the series resistor value as shown in Figure 24. This configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com Layout Guidelines (continued) attenuationasaresultofthevoltagedividerformedbytheseriesoutputintotheterminatingimpedance. 5. Socketing a high-speed part such as the OPA659 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by solderingtheOPA659directlyontotheboard. 6. The thermal slug on bottom of OPA659 DRB package must be tied to the most negative supply. The DRB package is a thermally-enhanced package. Best results are obtained by soldering the exposed metal tab on the bottom of the OPA659 DRB directly to a metal plane on the PCB that is connected to the most negative supply voltage of the operational amplifier. For general layout guidelines, refer to the EVM layout in theSchematicandPCBLayout section. 11.2 Layout Example Bypass Capacitors Output-matching resistor close to Minimize the trace length of VOUT minimizes the feedback parasitic output element capacitance Ground plane removed under VIN Bypass Capacitors Figure43. LayoutRecommendation 11.3 Thermal Pad Information The DRB package includes an exposed thermal pad for increased thermal performance. When using this package, TI recommends to distribute the negative supply as a power plane, and tie the thermal pad to this supply with multiple vias for proper power dissipation. For proper operation, the thermal pad must be tied to the most negative supply voltage. TI recommends using five evenly-spaced vias under the device as shown in the EVM layer views (see Figure 45). For more general data and detailed information about the exposed thermal pad,gotowww.ti.com/thermal. 22 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 11.4 Schematic and PCB Layout Figure44istheOPA659EVMschematic.Layers1through4ofthePCBareshowninFigure45.TIrecommends following the layout of the external components near to the amplifier, ground plane construction, and power routingascloselyaspossible. 2 7 - 6 3 + 4 + + Figure44. OPA659EVMSchematic Figure45. OPA659EVMLayers1Through4 Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:OPA659

OPA659 SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 www.ti.com 11.5 Evaluation Module 11.5.1 BillofMaterials Table6liststhebillofmaterialfortheOPA659EVMassuppliedfromTI. Table6.OPA659EVMPartsList REFERENCE MANUFACTURER ITEM DESCRIPTION SMDSIZE QUANTITY DESIGNATOR PARTNUMBER 1 Cap,10μF,Tantalum,10%,35V D C1,C2 2 (AVX)TAJ106K035R 2 Cap,0.1μF,Ceramic,X7R,16V 0603 C3,C4 2 (AVX)0603YC104KAT2A 3 Open 0603 R1,R2 2 4 Resistor,0Ω 0603 R4 1 (ROHM)MCR03EZPJ000 5 Resistor,49.9Ω,1/10W,1% 0603 R3,R5 2 (ROHM)MCR03EZPFX49R9 Jack,BananaReceptance,0.25inch 6 J4,J5,J8 3 (SPC)813 diameterhole 7 Connector,Edge,SMAPCBJack J1,J2,J3 3 (JOHNSON)142-0701-801 8 TestPoint,Black TP1 1 (KEYSTONE)5001 9 IC,OPA659 U1 1 (TI)OPA659DRB Standoff,4-40HEX,0.625inch 10 4 (KEYSTONE)1808 length 11 Screw,Phillips,4-40,0.25inch 4 SHR-0440-016-SN 12 Board,PrintedCircuit 1 (TI)EDGE#6506173 (STEWARD)HI1206N800R- 13 Bead,Ferrite,3A,80Ω 1206 FB1,FB2 2 00 24 SubmitDocumentationFeedback Copyright©2008–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA659

OPA659 www.ti.com SBOS342C–DECEMBER2008–REVISEDNOVEMBER2015 12 Device and Documentation Support 12.1 Device Support 12.1.1 DevelopmentSupport Forthermalinformationgotowww.ti.com/thermal. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2008–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:OPA659

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA659IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BZX & no Sb/Br) OPA659IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BZX & no Sb/Br) OPA659IDRBR ACTIVE SON DRB 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OBFI & no Sb/Br) OPA659IDRBT ACTIVE SON DRB 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OBFI & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA659IDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 OPA659IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA659IDRBR SON DRB 8 3000 367.0 367.0 35.0 OPA659IDRBT SON DRB 8 250 210.0 185.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DRB0008A VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.08 C DIM A 0.00 OPT 1 OPT 2 1.5 0.1 (0.1) (0.2) 4X (0.23) EXPOSED (DIM A) TYP THERMAL PAD 4 5 2X 1.95 1.75 0.1 8 1 6X 0.65 0.37 8X 0.25 PIN 1 ID 0.1 C A B (OPTIONAL) (0.65) 0.05 C 0.5 8X 0.3 4218875/A 01/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRB0008A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.5) (0.65) SYMM 8X (0.6) (0.825) 8X (0.31) 1 8 SYMM (1.75) (0.625) 6X (0.65) 4 5 (R0.05) TYP ( 0.2) VIA TYP (0.23) (0.5) (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND EXPOSED EXPOSED METAL METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218875/A 01/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRB0008A VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.65) 4X (0.23) SYMM METAL TYP 8X (0.6) 4X (0.725) 8X (0.31) 1 8 (2.674) SYMM (1.55) 6X (0.65) 4 5 (R0.05) TYP (1.34) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218875/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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