OPA404 Quad High-Speed Precision Difet® OPERATIONAL AMPLIFIER FEATURES APPLICATIONS l WIDE BANDWIDTH: 6.4MHz l PRECISION INSTRUMENTATION l HIGH SLEW RATE: 35V/m s l OPTOELECTRONICS l LOW OFFSET: – 750m V max l SONAR, ULTRASOUND l LOW BIAS CURRENT: – 4pA max l PROFESSIONAL AUDIO EQUIPMENT l LOW SETTLING: 1.5m s to 0.01% l MEDICAL EQUIPMENT l STANDARD QUAD PINOUT l DETECTOR ARRAYS DESCRIPTION The OPA404 is a high performance monolithic +VCC Difet®(dielectrically-isolated FET) quad operational amplifier. It offers an unusual combination of very- low bias current together with wide bandwidth and fast slew rate. –In Noise, bias current, voltage offset, drift, and speed are superior to BIFET® amplifiers. +In Cascode Laser-trimming of thin-film resistors gives very low offset and drift—the best available in a quad FET op Output amp. The OPA404's input cascode design allows high pre- cision input specifications and uncompromised high- speed performance. Standard quad op amp pin configuration allows up- grading of existing designs to higher performance levels. The OPA404 is unity-gain stable. –V CC OPA404 Simplified Circuit(cid:13) (Each Amplifier) Difet®, Burr-Brown Corp. BIFET®, National Semiconductor Corp. International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1986 Burr-Brown Corporation PDS-677F Printed in U.S.A. August 1995 SBOS149

SPECIFICATIONS ELECTRICAL At V = – 15VDC and T = +25(cid:176)C unless otherwise noted. CC A OPA404AG, KP, KU (1) OPA404BG OPA404SG PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT NOISE Voltage: fO = 10Hz 32 * * nV/(cid:214) Hz f = 100Hz 19 * * nV/(cid:214) Hz O fO = 1kHz 15 * * nV/(cid:214) Hz f = 10kHz 12 * * nV/(cid:214) Hz O fB = 10Hz to 10kHz 1.4 * * m Vrms f = 0.1Hz to 10Hz 0.95 * * m Vp-p B Current: fB = 0.1Hz to 10Hz 12 * * fA, p-p f = 0.1Hz thru 20kHz 0.6 * * fA/(cid:214) Hz O OFFSET VOLTAGE Input Offset Voltage V = 0VDC – 260 – 1mV * – 750 * * m V CM KP, KU – 750 – 2.5mV m V Average Drift T = T to T – 3 * * m V/(cid:176)C A MIN MAX KP, KU – 5 m V/(cid:176)C Supply Rejection – V = 12V to 18V 80 100 86 * * * dB CC KP, KU 76 100 dB Channel Separation 100Hz, R = 2kW 125 * * dB L BIAS CURRENT Input Bias Current V = 0VDC – 1 – 8 * – 4 * * pA CM KP, KU – 1 – 12 pA OFFSET CURRENT Input Offset Current V = 0VDC 0.5 8 * 4 * * pA CM KP, KU 0.5 12 pA IMPEDANCE Differential 1013 || 1 * * W || pF Common-Mode 1014 || 3 * * W || pF VOTAGE RANGE Common-Mode Input Range – 10.5 +13, –11 * * * * V Common-Mode Rejection VIN = – 10VDC 88 100 92 * * * dB KP, KU 84 100 dB OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R ‡ 2kW 88 100 92 * * * dB L FREQUENCY RESPONSE Gain Bandwidth Gain = 100 4 6.4 5 * * * MHz Full Power Response 20Vp-p, RL = 2kW 570 * * kHz Slew Rate V = – 10V, R = 2kW 24 35 28 * * * V/m s O L Settling Time: 0.1% Gain = –1, RL = 2kW 0.6 * * m s 0.01% C = 100 pF, 10V Step 1.5 * * m s L RATED OUTPUT Voltage Output R = 2kW – 11.5 +13.2, –13.8 * * * * V L Current Output V = – 10VDC – 5 – 10 * * * * mA O Output Resistance 1MHz, Open Loop 80 * * W Load Capacitance Stability Gain = +1 1000 * * pF Short Circuit Current – 10 – 27 – 40 * * * * * * mA POWER SUPPLY Rated Voltage – 15 * * VDC Voltage Range, Derated Performance – 5 – 18 * * * * VDC Current, Quiescent I = 0mADC 9 10 * * * * mA O TEMPERATURE RANGE Specification Ambient Temperature –25 +85 * * –55 +125 (cid:176)C KP, KU 0 +70 (cid:176)C Operating Ambient Temperature –55 +125 * * * * (cid:176)C KP, KU –25 +85 (cid:176)C Storage Ambient Temperature –65 +150 * * * * (cid:176)C KP, KU –40 +125 (cid:176)C q Junction-Ambient 100 * * (cid:176)C/W KP, KU 120/100 (cid:176)C/W *Specifications same as OPA404AG. NOTE: (1) OPA404KU may be marked OPA404U. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA404 2

ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At V = – 15VDC and T = T to T unless otherwise noted. CC A MIN MAX OPA404AG, KP, KU OPA404BG OPA404SG PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS TEMPERATURE RANGE Specification Range Ambient Temperature –25 +85 * * –55 +125 (cid:176)C KP, KU 0 +70 (cid:176)C INPUT OFFSET VOLTAGE Input Offset Voltage VCM = 0VDC – 450 2mV * – 1.5mV – 550 – 2.5mV m V KP KU – 1 – 3.5 mV Average Drift – 3 * * m V/(cid:176)C KP, KU – 5 m V/(cid:176)C Supply Rejection 75 96 80 * 70 93 dB BIAS CURRENT Input Bias Current VCM = 0VDC – 32 – 200 * – 100 – 500 – 5nA pA OFFSET CURRENT Input Offset Current VCM = 0VDC 17 100 * 50 260 2.5nA pA VOLTAGE RANGE Common-Mode Input Range – 10 – 12.7, –10.6 * * – 10 +12.6, –10.5 V Common-Mode Rejection V = – 10VDC 82 99 86 * 80 88 dB IN KP, KU 80 99 dB OPEN-LOOP GAIN, DC Open-Loop Voltage Gain R ‡ 2kW 82 94 86 * 80 88 dB L RATED OUTPUT Voltage Output R = 2kW – 11.5 – 12.9, –13.8 * * – 11 +12.7, –13.8 V L Current Output VO = – 10VDC – 5 – 9 * * * – 8 mA Short Circuit Current V = 0VDC – 8 – 20 – 50 * * * * * * mA O POWER SUPPLY Current, Quiescent I = 0mADC 9.3 10.5 * * 9.4 11 mA O * Specification same as OPA404AG. ORDERING INFORMATION PACKAGE INFORMATION TEMPERATURE PACKAGE DRAWING MODEL PACKAGE RANGE MODEL PACKAGE NUMBER(1) OPA404KP 14-Pin Plastic DIP 0(cid:176)C to +70(cid:176)C OPA404KP 14-Pin Plastic DIP 010 OPA404KU(1) 16-Pin Plastic SOIC 0(cid:176)C to +70(cid:176)C OPA404KU(2) 16-Pin Plastic SOIC 211 OPA404AG 14-Pin Ceramic DIP –25(cid:176)C to +85(cid:176)C OPA404AG 14-Pin Ceramic DIP 169 OPA404BG 14-Pin Ceramic DIP –25(cid:176)C to +85(cid:176)C OPA404BG 14-Pin Ceramic DIP 169 OPA404SG 14-Pin Ceramic DIP –55(cid:176)C to +125(cid:176)C OPA404SG 14-Pin Ceramic DIP 169 NOTE: (1) OPA404KU may be marked OPA404U. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. (2) OPA404KU may be marked OPA404U. ABSOLUTE MAXIMUM RATINGS Supply.............................................................................................– 18VDC Operating Temperature Range..P, U = –25(cid:176)C/+85(cid:176)C, G = –55(cid:176)C/+125(cid:176)C Internal Power Dissipation(1).........................................................1000mW Lead Temperature (soldering, 10s)....................................................300(cid:176)C Differential Input Voltage(2).............................................................– 36VDC SOIC (soldering, 3s).....................................................................+260(cid:176)C Input Voltage Range(2)...................................................................– 18VDC Output Short-Circuit Duration(3) .................................................Continuous Storage Temperature Range...P, U = –40(cid:176)C/+125(cid:176)C, G = –65(cid:176)C/+150(cid:176)C Junction Temperature.......................................................................+175(cid:176)C NOTES: (1) Packages must be derated based on q = 30(cid:176)C/W or q = 120(cid:176)C/W. (2) For supply voltages less than – 18VDC the absolute maximum input voltage is equal JC JA to: 18V > VIN > –VCC – 8V. See Figure 2. (3) Short circuit may be to power supply common only. Rating applies to +25(cid:176)C ambient. Observe dissipation limit and TJ. PIN CONFIGURATION Top View “U” (SOIC) Package Top View “G” or “P” (DIP) Package Out A(cid:13) 1(cid:13) 16(cid:13) Out D(cid:13) Out A(cid:13) 1(cid:13) 14(cid:13) Out D(cid:13) –In A(cid:13) 2(cid:13) 15(cid:13) –In D(cid:13) A D –In A(cid:13) 2(cid:13) 13(cid:13) –In D(cid:13) + In A(cid:13) 3(cid:13) 14(cid:13) +In D(cid:13) A D + In A(cid:13) 3(cid:13) 12(cid:13) +In D(cid:13) + VCC(cid:13) 4(cid:13) 13(cid:13) –VCC(cid:13) + VCC(cid:13) 4(cid:13) 11(cid:13) –VCC(cid:13) +In B(cid:13) 5(cid:13) 12(cid:13) +In C(cid:13) B C +In B(cid:13) 5(cid:13) 10(cid:13) +In C(cid:13) – In B(cid:13) 6(cid:13) 11(cid:13) –In C(cid:13) B C – In B(cid:13) 6(cid:13) 9(cid:13) –In C(cid:13) Out B(cid:13) 7(cid:13) 10(cid:13) Out C(cid:13) Out B(cid:13) 7(cid:13) 8(cid:13) Out C(cid:13) NC 8 9 NC (cid:13) (cid:13) (cid:13) (cid:13) ® 3 OPA404

DICE INFORMATION 2 1 NC 14 3 13 PAD FUNCTION PAD FUNCTION 4 12 1 Output A 8 Output C 2 –Input A 9 –Input C NC NC 3 +Input A 10 +Input C 4 +VCC 11 –VCC 5 +Input B 12 +Input D 6 –Input B 13 –Input D 7 Output B 14 Output D Substrate Bias: –VCC NC: No connection MECHANICAL INFORMATION MILS (0.001") MILLIMETERS Die Size 108 x 108 – 5 2.74 x 2.74 – 0.13 NC NC Die Thickness 20 – 3 0.51 – 0.08 Min. Pad Size 4 x 4 0.10 x 0.10 5 11 Backing None 6 10 7 NC 8 9 OPA404 DIE TOPOGRAPHY TYPICAL PERFORMANCE CURVES T = +25(cid:176)C, V = – 15VDC unless otherwise noted. A CC POWER SUPPLY REJECTION AND COMMON-MODE(cid:13) INPUT CURRENT NOISE SPECTRAL DENSITY REJECTION vs TEMPERATURE 100 110 PSR z) 105 Noise (fA/ H 10 nd PSR (dB) 100 CMR Current 1 CMR a 95 0.1 90 1 10 100 1k 10k 100k 1M –75 –50 –25 0 +25 +50 +75 +100 +125 Frequency (Hz) Temperature (°C) TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY(cid:13) BIAS AND OFFSET CURRENT(cid:13) AT 1kHz vs SOURCE RESISTANCE vs TEMPERATURE 1k 10nA 10nA E O z) 1nA 1nA H age Noise, E(nV/ O 10100 OPA404 + RRSesistor Bias Current (pA) 11000 Bias Current 11000 Offset Current (pA) Volt 1 Offset Current 1 Resistor noise only 1 0.1 0.1 100 1k 10k 100k 1M 10M 100M –50 –25 0 +25 +50 +75 +100 +125 Source Resistance (W ) Ambient Temperature (°C) ® OPA404 4

TYPICAL PERFORMANCE CURVES (CONT) TA = +25(cid:176)C, VCC = – 15VDC unless otherwise noted. BIAS AND OFFSET CURRENT(cid:13) POWER SUPPLY REJECTION(cid:13) vs INPUT COMMON-MODE VOLTAGE vs FREQUENCY 10 10 140 120 B) d s Current (pA) 1 Bias Current Offset Current 1 et Current (pA) pply Rejection ( 1680000 – + Bia 0.1 0.1 Offs er Su 40 w o P 20 0.01 0.01 0 –15 –10 –5 0 +5 +10 +15 1 10 100 1k 10k 100k 1M 10M Common-Mode Voltage (V) Frequency (Hz) COMMON-MODE REJECTION(cid:13) COMMON-MODE REJECTION(cid:13) vs FREQUENCY vs INPUT COMMON-MODE VOLTAGE 140 120 dB) 120 dB) 110 on ( 100 on ( ejecti 80 ejecti 100 R R e e Mod 60 Mod 90 n- n- mo 40 mo m m 80 Co 20 Co 0 70 1 10 100 1k 10k 100k 1M 10M –15 –10 –5 0 +5 +10 +15 Frequency (Hz) Common-Mode Voltage (V) GAIN BANDWIDTH AND SLEW RATE(cid:13) OPEN-LOOP FREQUENCY RESPONSE vs TEMPERATURE 140 10 40 R = 2kW (cid:13) 120 L –45 C = 100pF L Voltage Gain (dB) 146800000 A Ø ––19305 Phase Shift (Degrees) Gain Bandwidth (MHz) 684 SlewG RBaWte 333645 Slew Rate (V/µs) OL 20 0 –180 2 33 1 10 100 1k 10k 100k 1M 10M –75 –50 –25 0 +25 +50 +75 +100 +125 Frequency (Hz) Ambient Temperature (°C) ® 5 OPA404

TYPICAL PERFORMANCE CURVES (CONT) TA = +25(cid:176)C, VCC = – 15VDC unless otherwise noted. GAIN-BANDWIDTH AND SLEW RATE(cid:13) vs SUPPLY VOLTAGE OPEN-LOOP GAIN vs TEMPERATURE 8 38 120 A = +1 V Bandwidth (MHz) 7 RL = 10kW GBW 36 ew Rate (V/µs) age Gain (dB) 111000 ain 6 34 Sl Volt G 90 Slew Rate 5 32 80 0 5 10 15 20 –75 –50 –25 0 +25 +50 +75 +100 +125 Supply Voltage (±VCC) Ambient Temperature (°C) MAXIMUM OUTPUT(cid:13) VOLTAGE SWING vs FREQUENCY LARGE SIGNAL TRANSIENT RESPONSE 30 (cid:13) p) 10 p- V) Output Voltage (V 2100 Output Voltage ( 0 –10 R = 2kW L 0 10k 100k 1M 10M 0 1 2 3 4 5 Frequency (Hz) Time(µs) SMALL SIGNAL TRANSIENT RESPONSE SETTLING TIME vs CLOSED-LOOP GAIN 5 (cid:13) 150 4 100 V) s) e (m 50 me (µ 3 ag 0 Ti Output Volt–1–0500 Settling 12 0.01% RL = 2kW –150 CL = 100pF 0.1% 0 –1 –10 –100 –1k 0 1 2 Time(µs) Closed-Loop Gain (V/V) ® OPA404 6

TYPICAL PERFORMANCE CURVES (CONT) TA = +25(cid:176)C, VCC = – 15VDC unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE CHANNEL SEPARATION vs FREQUENCY 11(cid:13) 150(cid:13) B) 140(cid:13) RL = ¥ mA) 10(cid:13) on (d y Current ( 9(cid:13) el Separati 113200(cid:13)(cid:13) Suppl 8(cid:13) Chann RL = 2kW 110(cid:13) 7 0 –75 –50 –25 0 +25 +50 +75 +100 +125 10 100 1k 10k 100k Ambient Temperature (°C) Frequency (Hz) TOTAL HARMONIC DISTORTION vs FREQUENCY OPEN-LOOP GAIN vs SUPPLY VOLTAGE 1(cid:13) 104 40.2kW AV = +101V/V 402W 6.5Vrms ms) 0.1(cid:13) 2kW n 100 % r(cid:13) Gai N ( ge THD + 0.01(cid:13) AV = +101V/V Volta 96 A = +1V/V V Test(cid:13) Limit 0.001 92 0.1 1 10 100 1k 10k 100k 0 5 10 15 20 Frequency (Hz) Supply Voltage (±V ) CC INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k(cid:13) z) H V/ 100(cid:13) n e ( s oi N e ag 10(cid:13) olt V 1 1 10 100 1k 10k 100k 1M Frequency (Hz) ® 7 OPA404

APPLICATIONS INFORMATION GUARDING AND SHIELDING As in any situation where high impedances are involved, OFFSET VOLTAGE ADJUSTMENT careful shielding is required to reduce “hum” pickup in input The OPA404 offset voltage is laser-trimmed and will require leads. If large feedback resistors are used, they should also no further trim for most applications. If desired, offset volt- be shielded along with the external input circuitry. age can be trimmed by summing (see Figure 1). With this Leakage currents across printed circuit boards can easily trim method there will be no degradation of input offset drift. exceed the bias current of the OPA404. To avoid leakage, utmost care must be used in planning the board layout. A “guard” pattern should completely surround the high imped- ance input leads and should be connected to a low-impedance point which is at the signal input potential. (See Figure 3). In 1/4(cid:13) OPA404 Out Non-Inverting Buffer –15V 100kW ±2mV Offset(cid:13) 20W 150kW Trim +15V Out Out FIGURE 1. Offset Voltage Trim. In In Inverting INPUT PROTECTION Conventional monolithic FET operational amplifiers require In external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-to- Out substrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –V . CC Unlike BIFET amplifiers, the Difet OPA404 requires input current limiting resistors only if its input voltage is greater For input guarding,(cid:13) than 8 volts more negative than –VCC. A 10kW series resistor guard top and bottom of board. will limit the input current to a safe value with up to – 15V input levels even if both supply voltages are lost. (See Figure FIGURE 3. Connection of Input Guard. 2 and Absolute Maximum Ratings). Static damage can cause subtle changes in amplifier input HANDLING AND TESTING characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET Measuring the unusually low bias current of the OPA404 is types), this may cause a noticeable degradation of offset difficult without specialized test equipment; most commer- cial benchtop testers cannot accurately measure the OPA404 voltage and drift. bias current. Low-leakage test sockets and special test Static protection is recommended when handling any preci- fixtures are recommended if incoming inspection of bias sion IC operational amplifier. current is to be performed. To prevent surface leakage between pins, the DIP package INPUT CURRENT vs INPUT VOLTAGE(cid:13) should not be handled by bare fingers. Oils and salts from WITH ±V PINS GROUNDED CC +2 fingerprints or careless handling can create leakage currents that exceed the specified OPA404 bias currents. +1 IIN Maximum Safe Current If necessary, DIP packages and PC board assemblies can be A) cleaned with Freon TF®, baked for 30 minutes at 85(cid:176) C, m nt ( V rinsed with de-ionized water, and baked again for 30 min- urre 0 utes at 85(cid:176) C. Surface contamination can be prevented by the C application of a high-quality conformal coating to the cleaned ut np PC board assembly. I –1 Maximum Safe Current –2 –15 –10 –5 0 +5 +10 +15 Input Voltage (V) FIGURE 2. Input Current vs Input Voltage with – V Pins CC Grounded. ® OPA404 8

BIAS CURRENT CHANGE APPLICATIONS CIRCUITS vs COMMON-MODE VOLTAGE Figures 5 through 11 are circuit diagrams of various appli- The input bias currents of most popular BIFET operational cations for the OPA404. amplifiers are affected by common-mode voltage (Figure 4). Higher input FET gate-to-drain voltage causes leakage and ionization (bias) currents to increase. Due to its cascode input stage, the extremely low bias current of the OPA404 is 1MW not compromised by common-mode voltage. Operate 10kW 2 80 In 1/4(cid:13) 1 70 TA = +25°C; curves taken from (cid:13) LF156/157 Zero 100W 3 OPA404 Out mfg. published typical data 100kW 60 A) urrent (p 4500 LF156/157 AD5L4F7155(cid:13)(cid:13) 100kW Polyp1roµpFylene(cid:13) GVDOraiSfint < »= 10 –0.01µ50Vµ0(cid:13)V(cid:13) /°C(cid:13) s C 30 Zero Droop » 1µV/s(cid:13) Bia 20 Referred to Input ut 10 LF155(cid:13) 6 p In 0 OPAAD450447(cid:13) OPA404 7 OP1A/44(cid:13)04 5 –10 OP-15/16/17 –20 –15 –10 –5 0 +5 +10 +15 Common-Mode Voltage (VDC) FIGURE 4. Input Bias Current vs Common-Mode Voltage. FIGURE 5. Auto-Zero Amplifier. 10kW (cid:13) (cid:13) » 10pF (1) 1MW 6 IN914 1/4(cid:13) 7 2 OPA404 Output (1) 5 1/4(cid:13) 1 (1) OPA404 Input 3 IN914 Droop » 0.1mV/s 2N4117 0.01µF Polstyrene NO(cid:13)TE: (1) Reverse polarity for negative peak detection. FIGURE 6. Low-Droop Positive Peak Detector. ® 9 OPA404

2 1 1 1/4(cid:13) OPA404 3 Output = 1µA/V Differential(cid:13) Input 3 E1 6 1MW IO 2 E R 1 Load 5 IO = (E1 – E2) /R INA105 FIGURE 7. Voltage-Controlled Microamp Current Source. <1pF to prevent gain peaking 1000MW Pin Photodiode(cid:13) UDT Pin-040A Guard +15V 0.01µF 2 8 Output 1/4 (cid:13) 3 OPA404 1 4 0.1µF 0.01µF 5 x 88 V/W 1000MW –15V Circuit must be well shielded. FIGURE 8. Sensitive Photodiode Amplifier. 3 20kW 20kW 1/4(cid:13) OPA404 2 1 R(cid:13) F 10kW Guard R /2(cid:13) G + 100W 10 12 Input 8 1/4(cid:13) 1/4(cid:13) OPA404 9 13 OPA404 14 – RG/2(cid:13) 100W Guard A = 101µV/V(cid:13) V R(cid:13) IR B I N » »1 p1A0(cid:13)13W (cid:13) 6 10kFW BW » 100kHz(cid:13) 1/4(cid:13) Differential Voltage Gain = 1+ (2RF/RG) 5 OPA404 7 20kW 20kW FIGURE 9. FET Instrumentation Amplifier with Shield Driver. ® OPA404 10

13 1µF 9 14 1µF 127kW D 4 8 12 Out 1µF 61.9kW C 1µF 2 44.2kW B 7 10 60.4kW In 57.6kW 3 A 1 12.1kW 5 18.7kW 0.22µF 0.033µF 9.53kW 0.47µF 0.47µF Gain = +1V/V(cid:13) 48dB/Octave, 10Hz LPF(cid:13) Butterworth Response FIGURE 10. 8-Pole 10Hz Low-Pass Filter. 4.02kW 4.02kW 4.02kW 4.02kW A B C D Out In A = +635(cid:13) V 1kW 1kW 1kW 1kW BW » 650kHz(cid:13) Gain-Bandwidth » 410MHz FIGURE 11. Wide-Band Amplifier. ® 11 OPA404

PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA404AG NRND CDIP SB JD 14 1 Green (RoHS AU N / A for Pkg Type OPA404AG & no Sb/Br) OPA404BG NRND CDIP SB JD 14 1 Green (RoHS AU N / A for Pkg Type OPA404BG & no Sb/Br) OPA404KP ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type OPA404KP & no Sb/Br) OPA404KPG4 ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type OPA404KP & no Sb/Br) OPA404KU ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR 0 to 70 OPA404KU & no Sb/Br) OPA404KU/1K ACTIVE SOIC DW 16 1000 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR 0 to 70 OPA404KU & no Sb/Br) OPA404SG NRND CDIP SB JD 14 1 Green (RoHS AU N / A for Pkg Type OPA404SG & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA404KU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA404KU/1K SOIC DW 16 1000 367.0 367.0 38.0 PackMaterials-Page2

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