OPA2822 OPA2822 www.ti.com SBOS188E – MARCH 2001 – REVISED AUGUST 2008 Dual, Wideband, Low-Noise Operational Amplifier FEATURES DESCRIPTION (cid:1) LOW INPUT NOISE VOLTAGE: 2.0nV/√Hz The OPA2822 offers very low 2.0nV/√Hz input noise in a (cid:1) HIGH UNITY GAIN BANDWIDTH: 500MHz wideband, unity-gain stable, voltage-feedback architecture. (cid:1) HIGH GAIN BANDWIDTH PRODUCT: 240MHz Intended for xDSL receiver applications, the OPA2822 also (cid:1) HIGH OUTPUT CURRENT: 90mA supports this low input noise with exceptionally low harmonic distortion, particularly in differential configurations. Adequate (cid:1) SINGLE +5V TO +12V OPERATION output current is provided to drive the potentially heavy load (cid:1) LOW SUPPLY CURRENT: 4.8mA/ch of a passive filter between this amplifier and the codec. Harmonic distortion for a 2V differential output operating PP APPLICATIONS from +5V to +12V supplies is ≤ –100dBc through 1MHz input frequencies. Operating on a low 4.8mA/ch supply current, (cid:1) xDSL DIFFERENTIAL LINE RECEIVERS the OPA2822 can satisfy all xDSL receiver requirements (cid:1) HIGH DYNAMIC RANGE ADC DRIVERS over a wide range of possible supply voltages—from a single (cid:1) LOW NOISE PLL INTEGRATORS +5V condition, to ±5V, up to a single +12V design. (cid:1) TRANSIMPEDANCE AMPLIFIERS General-purpose applications on a single +5V supply will (cid:1) PRECISION BASEBAND I/Q AMPLIFIERS benefit from the high input and output voltage swing available (cid:1) ACTIVE FILTERS on this reduced supply voltage. Low-cost precision integra- tors for PLLs will also benefit from the low voltage noise and offset voltage. Baseband I/Q receiver channels can achieve OPA2677 almost perfect channel match with noise and distortion to R support signals through 5MHz with > 14-bit dynamic range. n:1 O OPA2822 RELATED PRODUCTS xDSL Driver FEATURES SINGLES DUALS TRIPLES RO High Slew Rate OPA690 OPA2690 OPA3690 R/R Input/Output OPA353 OPA2353 — 1.3nV Input Noise OPA846 OPA2686 — 500Ω 1kΩ 1.5nV Input Noise — THS6062 — 500Ω OPA2822 500Ω 1kΩ xDSL Receiver OPA2822 500Ω Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2001-2008, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

PACKAGE/ORDERING INFORMATION(1) SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY OPA2822U SO-8 Surface-Mount D –40°C to +85°C OPA2822U OPA2822U Rails, 100 " " " " " OPA2822U/2K5 Tape and Reel, 2500 OPA2822E MSOP-8 Surface-Mount DGK –40°C to +85°C D22 OPA2822E/250 Tape and Reel, 250 " " " " " OPA2822E/2K5 Tape and Reel, 2500 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC Supply Voltage.................................................................................±6.5V DISCHARGE SENSITIVITY Internal Power Dissipation...........................See Thermal Characteristics Differential Input Voltage..................................................................±1.2V Electrostatic discharge can cause damage ranging from per- Input Voltage Range............................................................................±V S Storage Temperature Range.........................................–65°C to +125°C formance degradation to complete device failure. Texas In- Lead Temperature(SO-8).............................................................+260°C struments recommends that all integrated circuits be handled Junction Temperature (T )...........................................................+150°C J and stored using appropriate ESD protection methods. ESD Rating (Human Body Model)..................................................2000V (Machine Model)...........................................................200V ESD damage can range from subtle performance degradation NOTE: (1) Stresses above these ratings may cause permanent damage. to complete device failure. Precision integrated circuits may be Exposure to absolute maximum conditions for extended periods may degrade more susceptible to damage because very small parametric device reliability. These are stress ratings only, and functional operation of the changes could cause the device not to meet published speci- device at these or any other conditions beyond those specified is not implied. fications. PIN CONFIGURATION/MSOP PACKING MARKING Top View SO MSOP PACKAGE MARKING OPA2822 8 7 6 5 Out A 1 8 +V S D22 –In A 2 7 Out B +In A 3 6 –In B –V 4 5 +In B S 1 2 3 4 OPA2822 2 www.ti.com SBOS188E

± ELECTRICAL CHARACTERISTICS: V = 6V S ° Boldface limits are tested at +25 C. R = 402Ω, R = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. F L OPA2822U, E TYP MIN/MAX OVER TEMPERATURE 0°C to –40°C to MIN/ TEST PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3) AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth G = +1, V = 0.1V , R = 0Ω 400 MHz typ C O PP F G = +2, V = 0.1V 200 120 110 105 MHz min B O PP G = +10, V = 0.1V 24 15 13 12 MHz min B O PP Gain-Bandwidth Product G ≥ 20 240 150 130 125 MHz min B Bandwidth for 0.1dB Gain Flatness G = +2, V < 0.1V 16 MHz typ C O PP Peaking at a Gain of +1 V < 0.1V 5 dB typ C O PP Large-Signal Bandwidth G = +2, V = 2V 27 MHz typ C O PP Slew Rate G = +2, 4V Step 170 110 105 100 V/µs min B Rise-and-Fall Time G = +2, V = 0.2V Step 1.5 ns typ C O Settling Time to 0.02% G = +2, V = 2V Step 35 ns typ C O 0.1% G = +2, V = 2V Step 32 ns typ C O Harmonic Distortion G = +2, f = 1MHz, V = 2V O PP 2nd-Harmonic R = 200Ω –91 –88 –87 –86 dBc max B L R ≥ 500Ω –95 –91 –90 –89 dBc max B L 3rd-Harmonic R = 200Ω –100 –95 –92 –91 dBc max B L R ≥ 500Ω –105 –99 –96 –95 dBc max B L Input Voltage Noise f > 10kHz 2.0 2.2 2.3 2.5 nV/√Hz max B Input Current Noise f > 10kHz 1.6 2.0 2.1 2.3 pA/√Hz max B Differential Gain G = +2, PAL, V = 1.4Vp, R = 150 0.02 % typ C O L Differential Phase G = +2, PAL, V = 1.4Vp, R = 150 0.03 deg typ C O L Channel-to-Channel Crosstalk f = 1MHz, Input Referred –95 dBc typ C DC PERFORMANCE(4) Open-Loop Voltage Gain (A ) V = 0V, R = 100Ω 100 85 82 80 dB min A Input Offset Voltage OL O V =L 0V ±0.2 ±1.2 ±1.4 ±1.5 mV max A CM Average Offset Voltage Drift V = 0V 5 5 µV/°C max B CM Input Bias Current V = 0V –9 –18 –19 –21 µA max A CM Average Bias Current Drift (magnitude) V = 0V 50 50 nA/°C max B Input Offset Current VCM = 0V ±100 ±400 ±600 ±700 nA max A CM Average Offset Current Drift V = 0V 5 5 nA/°C max B CM INPUT Common-Mode Input Range (CMIR)(5) ±4.8 ±4.5 ±4.4 ±4.4 V min A Common-Mode Rejection Ratio (CMRR) V = ±1V 110 85 82 80 dB min A CM Input Impedance Differential-Mode V = 0 18  0.6 kΩ || pF typ C CM Common-Mode V = 0 7  1 MΩ || pF typ C CM OUTPUT Voltage Output Swing No Load ±4.9 ±4.7 ±4.6 ±4.6 V min A 100Ω Load ±4.7 ±4.5 ±4.4 ±4.4 V min A Current Output, Sourcing V = 0, Linear Operation +150 +90 +85 +80 mA min A O Current Output, Sinking V = 0, Linear Operation –150 –90 –85 –80 mA min A O Short-Circuit Current Output Shorted to Ground 220 mA typ C Closed-Loop Output Impedance G = +2, f = 100kHz 0.01 Ω typ C POWER SUPPLY Specified Operating Voltage ±6 V typ C Maximum Operating Voltage Range ±6.3 ±6.3 ±6.3 V max A Max Quiescent Current V = ±6V, both channels 9.6 11.8 11.9 12.0 mA max A S Min Quiescent Current V = ±6V, both channels 9.6 8.2 8.1 8.0 mA min A S Power-Supply Rejection Ratio (–PSRR) Input Referred 95 85 82 80 dB min A THERMAL CHARACTERISTICS Specified Operating Range U, E Package –40 to +85 °C typ C Thermal Resistance, θ Junction-to-Ambient JA U SO-8 125 °C/W typ C E MSOP 150 °C/W typ C NOTES: (1)Junction temperature = ambient for +25°C tested specifications. (2)Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature tested specifications. (3)Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4)Current is considered positive-out-of node. V is the input common-mode voltage. CM (5)Tested < 3dB below minimum CMRR specification at ± CMIR limits. OPA2822 3 SBOS188E www.ti.com

ELECTRICAL CHARACTERISTICS: V = +5V S ° Boldface limits are tested at +25 C. R = 402Ω, R = 100Ω to V /2, and G = +2, (see Figure 3 for AC performance only), unless otherwise noted. F L S OPA2822U, E TYP MIN/MAX OVER TEMPERATURE 0°C to –40°C to MIN/ TEST PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3) AC PERFORMANCE (see Figure 3) Small-Signal Bandwidth G = +1, V = 0.1V , R = 0Ω 350 MHz typ C O PP F G = +2, V = 0.1V 180 105 102 100 MHz min B O PP G = +10, V = 0.1V 20 13 11 10 MHz min B O PP Gain-Bandwidth Product G > 20 200 130 110 105 MHz min B Peaking at a Gain of +1 V < 0.1V 6 dB typ C O PP Large-Signal Bandwidth G = +2, V = 2V 20 MHz typ C O PP Slew Rate G = +2, 2V Step 120 90 85 80 V/µs min B Rise-and-Fall Time G = +2, V = 0.2V Step 2.0 2.7 3.2 3.3 ns max B O Settling Time to 0.02% G = +2, V = 2V Step 40 ns typ C O 0.1% G = +2, V = 2V Step 38 ns typ C O Harmonic Distortion G = +2, f = 1MHz, V = 2V O PP 2nd-Harmonic R = 200Ω to V /2 –85 –82 –81 –80 dBc max B L S R = 500Ω to V /2 –87 –83 –82 –81 dBc max B L S 3rd-Harmonic R = 100Ω to V /2 –99 –94 –91 –90 dBc max B L S R = 1500Ω to V /2 –103 –98 –95 –94 dBc max B L S Input Voltage Noise f > 1MHz 2.1 2.3 2.4 2.6 nV/√Hz max B Input Current Noise f > 1MHz 1.5 1.9 2.0 2.1 pA/√Hz max B DC PERFORMANCE(4) Open-Loop Voltage Gain V = 0V, R = 200Ω to 2.5V 90 81 78 76 dB min A Input Offset Voltage O V L = 2.5V ±0.3 ±1.3 ±1.5 ±1.6 mV max A CM Average Offset Voltage Drift V = 2.5V 5.5 5.5 µV/°C max B CM Input Bias Current V = 2.5V –8 –16 –19 –20 µA max A CM Average Bias Current Drift V = 2.5V 50 50 nA/°C max B Input Offset Current VCM = 2.5V ±100 ±400 ±600 ±700 nA max A CM Average Offset Current Drift V = 2.5V 5 5 nA/°C max B CM INPUT Least Positive Input Voltage 1.2 1.5 1.6 1.65 V min A Most Positive Input Voltage 3.8 3.5 3.4 3.35 V max A Common-Mode Rejection Ratio (CMRR) V = +2.5V 110 85 82 80 dB min A CM Input Impedance Differential-Mode V = +2.5V 15  1 kΩ || pF typ C CM Common-Mode V = +2.5V 5 1.3 MΩ || pF typ C CM OUTPUT Most Positive Output Voltage No Load 3.9 3.8 3.6 3.5 V min A R = 100Ω to 2.5V 3.7 3.5 3.4 3.35 V min A L Least Positive Output Voltage No Load 1.3 1.4 1.5 1.55 V min A R = 100Ω to 2.5V 1.4 1.5 1.6 1.65 V min A L Current Output, Sourcing +150 +90 +85 +80 mA min A Current Output, Sinking –150 –90 –85 –80 mA min A Short-Circuit Current Output Shorted to Either Supply 200 mA typ C Closed-Loop Output Impedance G = +1, f = 100kHz 0.01 Ω typ C POWER SUPPLY Specified Single-Supply Operating Voltage 5 V typ C Maximum Single-Supply Operating Voltage 12.6 12.6 12.6 V max A Max Quiescent Current V = +5V, both channels 8 10 10.2 10.4 mA max A S Min Quiescent Current V = +5V, both channels 8 7.2 7.0 6.9 mA min A S Power-Supply Rejection Ratio Input Referred 90 dB typ C THERMAL CHARACTERISTICS Specified Operating Range U, E Package –40 to +85 °C typ C Thermal Resistance, θ Junction-to-Ambient JA U SO-8 125 °C/W typ C E MSOP 150 °C/W typ C NOTES:(1)Junction temperature = ambient for +25°C tested specifications. (2)Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature tested specifications. (3)Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4)Current is considered positive-out-of node. V is the input common-mode voltage. CM OPA2822 4 www.ti.com SBOS188E

± TYPICAL CHARACTERISTICS: V = 6V S T = +25°C, G= +2, R = 402Ω, and R = 100Ω, unless otherwise noted. A F L NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL FREQUENCY RESPONSE FREQUENCY RESPONSE 6 6 3 VO = 0.1VPP RGF == +01Ω 3 VROF == 600.14VΩPP G = –1 G = –2 0 0 dB) –3 dB) –3 ain ( –6 G = +2 ain ( –6 G G G = –5 d –9 d –9 e G = +5 e maliz –12 maliz –12 G = –10 Nor –15 G = +10 Nor –15 –18 –18 –21 –21 See Figure 1 See Figure 2 –24 –24 0.5 1 10 100 500 0.5 1 10 100 500 Frequency (MHz) Frequency (MHz) NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL FREQUENCY RESPONSE FREQUENCY RESPONSE 12 6 G = +2 VO = 0.1VPP G = –1 VO = 0.1VPP 9 3 R = 604Ω F 6 0 3 –3 V = 0.5V V = 0.5V B) 0 O PP B) –6 O PP d d n ( –3 VO = 1VPP n ( –9 VO = 1VPP ai ai G –6 G –12 –9 VO = 2VPP –15 VO = 2VPP –12 –18 –15 –21 See Figure 1 See Figure 2 –18 –24 0.5 1 10 100 500 0.5 1 10 100 500 Frequency (MHz) Frequency (MHz) NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE 400 2.0 400 2.0 Small-Signal Output Voltage (100mv/div) –––1233210000000000000 SGe =e F+i2gure 1LSamrgael-lS-Sigignnaal lR Liegfht tS Sccaalele 1100–––...011505...505 Larege-Signal Output Voltage (500mv/div) Small-Signal Output Voltage (100mv/div) –––3211230000000000000 SGe =e –F1igure 2 LSamrgael-lS-Sigignnaal lR Liegfht tS Sccaalele 1100–––...011505...505 Larege-Signal Output Voltage (500mv/div) –400 –2.0 –400 –2.0 Time (20ns/div) Time (20ns/div) OPA2822 5 SBOS188E www.ti.com

± TYPICAL CHARACTERISTICS: V = 6V (Cont.) S T = +25°C, G= +2, R = 402Ω, and R = 100Ω, unless otherwise noted. A F L HARMONIC DISTORTION vs LOAD RESISTANCE 1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE –85 –85 V = 2V O PP V = 2V f = 1MHz RO = 200PΩP L Bc) –90 Bc) –90 Distortion (d –95 2nd-Harmonic Distortion (d –95 2nd-Harmonic monic monic 3rd-Harmonic Har –100 3rd-Harmonic Har –100 See Figure 1 See Figure 1 –105 –105 100 1k ±2.5 ±3.0 ±3.5 ±4.0 ±4.5 ±5.0 ±5.5 ±6.0 Load Resistance (Ω) Supply Voltage (V) HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE –65 –85 VO = 2VPP RL = 200Ω R = 200Ω f = 1MHz Bc) –75 L Bc) –90 2nd-Harmonic d d n ( n ( o o orti 2nd-Harmonic orti Dist –85 Dist –95 nic nic mo 3rd-Harmonic mo 3rd-Harmonic ar –95 ar –100 H H See Figure 1 See Figure 1 –105 –105 1 10 0.1 1 10 Frequency (MHz) Output Voltage Swing (VPP) HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN –70 –70 V = 2V V = 2V O PP O PP R = 200Ω R = 200Ω L L dBc) –80 f = 1MHz dBc) –80 Rf =F 1=M 6H04zΩ n ( n ( o o orti 2nd-Harmonic orti 2nd-Harmonic st –90 st –90 Di Di c c ni ni o o m 3rd-Harmonic m 3rd-Harmonic ar –100 ar –100 H H See Figure 1 See Figure 2 –110 –110 1 10 1 10 Gain (V/V) Gain (V/V) OPA2822 6 www.ti.com SBOS188E

± TYPICAL CHARACTERISTICS: V = 6V (Cont.) S T = +25°C, G= +2, R = 402Ω, and R = 100Ω, unless otherwise noted. A F L 2-TONE, 3rd-ORDER INPUT VOLTAGE AND CURRENT NOISE DENSITY INTERMODULATION INTERCEPT 10 60 55 z z m) 50 √V/H√A/H +dB 45 e n e p nt ( Voltage Nois Current Nois Voltage Noise 2nV/√Hz Intercept Poi 433050 5P0IΩ OPA14/202822Ω2 50Ω 50PΩO Current Noise 1.6pA/√Hz 25 402Ω 1 20 102 103 104 105 106 107 1 10 20 Frequency (Hz) Frequency (MHz) CHANNEL-TO-CHANNEL CROSSTALK GAIN FLATNESS –40 0.50 erred (dB) ––5600 IRGnL p= u= +t 1R20e0fΩerred n (0.1dB/div) 000...432000 RNNGG = = 9 20.45Ω RNNGG == 2∞ ef ai 0.10 R G G = 2 Cross-Talk Input –––789000 viation from 6dB –––0000....01230000 NG = 3.5 RNNGG = = 4 35.20Ω NoAisdeju Gstaeind e –0.40 D RNG = 301Ω See Figure 12 –100 –0.50 0.1 1 10 100 500 0 50 100 150 200 Frequency (MHz) Frequency (MHz) RECOMMENDED R vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD S 1000 B) 9 d d ( 6 Loa C = 100pF CL = 10pF 100 citive 3 L CL = 22pF ΩR ()S 10 Gain to Capa –03 VI OPA14/202822Ω2 RS CL 1kVΩO CL = 47pF d –6 e For Maximally Flat Response, maliz –9 402Ω 1kΩ is optional. See Figure 12 or 1 N –12 10 100 1k 1 10 100 500 Capacitive Load (pF) Frequency (MHz) OPA2822 7 SBOS188E www.ti.com

± TYPICAL CHARACTERISTICS: V = 6V (Cont.) S T = +25°C, G= +2, R = 402Ω, and R = 100Ω, unless otherwise noted. A F L CMRR AND PSRR vs FREQUENCY OPEN-LOOP GAIN AND PHASE 120 120 0 CMRR n-Mode Rejection Ratio (dB) Supply Rejection Ratio (dB) 108640000 +P–SPRSRRR Open-Loop Gain (dB) 10864200000 20 log(AOL) ∠ AOL –––––369110002500°en-Loop Phase (30/div) mmo wer- 20 0 –180 Op Co Po 0 –20 –210 103 104 105 106 107 108 102 103 104 105 106 107 108 109 Frequency (Hz) Frequency (Hz) CLOSED-LOOP OUTPUT IMPEDANCE OUTPUT VOLTAGE AND CURRENT LIMITATIONS vs FREQUENCY 6 100 1W Internal 5 Power Limit 1/2 4 Single-Channel R = 100Ω 10 OPA2822 3 L Ω) ZO 2 R = 25Ω ce ( 402Ω V (V)O ––1012 RL = 50Ω L put Impedan 0.11 402Ω ut –3 O –4 1W Internal 0.01 Power Limit –5 Single-Channel –6 0.001 –200 –150 –100 –50 0 50 100 150 200 0.1 1 10 100 I (mA) Frequency (MHz) O NONINVERTING OVERDRIVE RECOVERY INVERTING OVERDRIVE RECOVERY 8 4 8 RL = 100Ω RL = 100Ω 6 G = +2 3 6 RF = 604Ω See Figure 1 G = –1 Output 4 2 e 4 Output g Output Voltage –202 Left Scale 10–1 Input Voltage ut/Output Volta –202 p –4 –2 In –4 Input –6 –3 –6 Input Right Scale See Figure 2 –8 –4 –8 Time (40ns/div) Time (40ns/div) OPA2822 8 www.ti.com SBOS188E

± TYPICAL CHARACTERISTICS: V = 6V (Cont.) S T = +25°C, G= +2, R = 402Ω, and R = 100Ω, unless otherwise noted. A F L SETTLING TIME VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE 0.25 0.30 R = 100Ω 0.20 VL = 2V step O 0.25 %) 0.15 G = +2 alue ( 0.10 °se () n (%) 0.20 al V 0.05 Pha Gai ercent of Fin ––00..01050 Differential Differential 00..1150 dP P –0.15 0.05 dG –0.20 See Figure 1 –0.25 0 0 5 10 15 20 25 30 35 40 45 50 55 60 1 2 3 4 5 6 7 8 Time (ns) Video Loads SUPPLY AND OUTPUT CURRENT TYPICAL DC DRIFT OVER TEMPERATURE vs TEMPERATURE 1 10 250 12 A) Sourcing Output Current Input Offset Voltage (mV) –00..505 10IxnIn pIpnuupt tuO Bt fOfiasfesfs tC eVuto rClrteuanrgrteent 50–5 µut Bias and Offset Current ( Output Current (25mA/div) 221112075250505 (SbuoRptihgp hlcyth CSacunarnrleeelnst) LSefitnL SkeCicnfutag rSlr eeOcnautlteput 1198710 Supply Current (1mA/div) p In Current Limited Output –1 –10 100 6 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) COMMON-MODE INPUT RANGE AND COMMON-MODE AND DIFFERENTIAL OUTPUT SWING vs SUPPLY VOLTAGE INPUT IMPEDANCE 6 107 Ω) Positive Input g ( Common-Mode 4 and Output 0Lo 106 2 Range (V) 20 Magnitude 105 Differential Voltage –2 edance 104 p Negative Input m 103 –4 and Output ut I p n –6 I 102 ±2 ±3 ±4 ±5 ±6 103 104 105 106 107 108 Supply Voltage (±V) Frequency (Hz) OPA2822 9 SBOS188E www.ti.com

± TYPICAL CHARACTERISTICS: V = 6V S T = +25°C, Differential Gain= 2, R = 604Ω, and R = 400Ω, unless otherwise noted. A F L DIFFERENTIAL PERFORMANCE DIFFERENTIAL SMALL-SIGNAL TEST CIRCUIT FREQUENCY RESPONSE 6 V = 200mV G = +1 +6V O PP D 3 G = +2 D 0 OPA1/22822 GD = 6R04GΩ ain (dB) ––36 GD = +5 G RG 604Ω alized ––192 GD = +10 VI RG 604Ω RL VO Norm –15 –18 –21 1/2 –24 OPA2822 0.5 1 10 100 500 Frequency (MHz) –6V DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE 12 –85 9 RGD == 4200Ω VO = 200mVPP VGO == 42VPP L D 6 VO = 1VPP Bc) –90 f = 1MHz 3 d n ( dB) 0 ortio 3rd-Harmonic Gain ( ––36 VO = 2VPP c Dist –95 ni 2nd-Harmonic –9 mo –12 VO = 5VPP Har –100 –15 –18 –105 0.5 1 10 100 500 10 100 1k Frequency (MHz) Load Resistance (Ω) DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE –65 –95 V = 4V f = 1MHz O PP G = 2 G = 2 c) RLD = 400Ω 3rd-Harmonic c) RLD = 400Ω 3rd-Harmonic B –75 B –100 d d n ( n ( o o orti orti st –85 st –105 Di Di c c 2nd-Harmonic ni 2nd-Harmonic ni o o m m ar –95 ar –110 H H –105 –115 1 10 1 10 Frequency (MHz) Differential Output Voltage Swing (V ) PP OPA2822 10 www.ti.com SBOS188E

TYPICAL CHARACTERISTICS: V = +5V S T = +25°C, G= +2, R = 402Ω, and R = 100Ω, unless otherwise noted. A F L NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL FREQUENCY RESPONSE FREQUENCY RESPONSE 9 6 6 VO = 0.1VPP RGF == +01Ω 3 VROF == 600.14VΩPP G = –1 G = –2 3 0 ain (dB) –03 G = +2 ain (dB) ––36 G –6 G G = –5 d G = +5 d –9 e –9 e maliz –12 maliz –12 G = –10 or –15 G = +10 or –15 N N –18 –18 –21 –21 See Figure 3 See Figure 4 –24 –24 0.5 1 10 100 500 0.5 1 10 100 500 Frequency (MHz) Frequency (MHz) NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE 0.4 2.0 0.4 2.0 div) 0.3 1.5 div) div) 0.3 1.5 div) mv/ Large-Signal Right Scale mv/ mv/ mv/ 00 0.2 1.0 00 00 0.2 1.0 00 1 5 1 5 ge ( 0.1 0.5 ge ( ge ( 0.1 0.5 ge ( a a a a olt Small-Signal Left Scale olt olt olt put V 0 0 put V put V 0 Small-Signal Left Scale 0 put V Out –0.1 –0.5 Out Out –0.1 –0.5 Out al al al al gn –0.2 –1.0 gn gn –0.2 –1.0 gn Si Si Si Si Small- –0.3 See Figure 3 –1.5 Large- Small- –0.3 See Figure 4 Large-Signal Right Scale –1.5 Large- –0.4 –2.0 –0.4 –2.0 Time (20ns/div) Time (20ns/div) RECOMMENDED R vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD S Ωg () 1000 d (dB) 96 CL = 10pF o a agnitude 20L 100 Capacitive Lo 30 VI 0.01µF 804Ω +51V/2 CRSL = 100pF VO CL C= L2 =2 p4F7pF ce M n to –3 804Ω OPA2822 CL 1kΩ nput Impedan 10 FSoere M Faigxuimrea 1lly2 Flat Response, ormalized Gai ––69 04.00214Ωµ0F2Ω 1kΩ is optional. I 1 N –12 10 100 1000 1 10 100 500 Capacitive Load (pF) Frequency (MHz) OPA2822 11 SBOS188E www.ti.com

TYPICAL CHARACTERISTICS: V = +5V (Cont.) S T = +25°C, G= +2, R = 402Ω, and R = 100Ω, unless otherwise noted. A F L HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY –75 –60 VO = 2VPP VO = 2VPP f = 1MHz R = 200Ω –80 L dBc) 2nd-Harmonic dBc) –70 on ( –85 on ( 2nd-Harmonic orti orti Dist –90 Dist –80 onic –95 onic m m ar 3rd-Harmonic ar –90 H H –100 3rd-Harmonic See Figure 3 See Figure 3 –105 –100 100 1k 1 10 Load Resistance (Ω) Frequency (MHz) 2-TONE, 3rd-ORDER HARMONIC DISTORTION vs OUTPUT VOLTAGE INTERMODULATION INTERCEPT –85 50 R = 200Ω L f = 1MHz 2nd-Harmonic 45 Bc) –90 m) monic Distortion (d –95 3rd-Harmonic ercept Point (+dB 433050 PI 507..16µΩF 880044ΩΩ O+P5A1V/22822 50Ω 5P0ΩO Har –100 Int 402Ω 25 402Ω See Figure 3 0.1µF –105 20 0.1 1 10 1 10 20 Output Voltage Swing (V ) Frequency (MHz) PP SUPPLY AND OUTPUT CURRENT TYPICAL DC DRIFT OVER TEMPERATURE vs TEMPERATURE 1 10 200 12 A) µ 11 Input Offset Voltage (mV) –00..505 10InIxnp pIunutp tO uBtf fiaOsesf ftCs Veuotr lrCteaungrterent 50–5 ut Bias and Offset Current ( Output Current (25mA/div) 111752505 SSinokuirncgin LOge uOfttp uSutcpt auClteu Crruernretnt (SbuoRptihgp hlcyth CSaucnarnrleeelnst) 19870 Supply Current (1mA/div) Inp Left Scale Current Limited Output –1 –10 100 6 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) OPA2822 12 www.ti.com SBOS188E

TYPICAL CHARACTERISTICS: V = +5V S T = +25°C, Differential Gain= +2, R = 604Ω, and R = 400Ω, unless otherwise noted. A F L DIFFERENTIAL PERFORMANCE DIFFERENTIAL SMALL-SIGNAL TEST CIRCUIT FREQUENCY RESPONSE 6 +5V 3 VRO == 420000ΩmVPP GD = +1 L +2.5V OPA1/22822 GD = 6R04GΩ ain (dB) ––036 GD = +2 G G = +5 0.01µF RG 604Ω ed –9 D aliz –12 VI 0.01µF RG 604Ω RL VO Norm –15 GD = +10 –18 –21 1/2 –24 OPA2822 0.5 1 10 100 500 +2.5V Frequency (MHz) DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE 12 –85 V = 200mV V = 4V 9 O PP GO = 2 PP D 6 V = 1V Bc) –90 f = 1MHz 3 O PP n (d 3rd-Harmonic dB) 0 ortio Gain ( ––36 VO = 2VPP c Dist –95 2nd-Harmonic ni o –9 m –12 VO = 5VPP Har –100 –15 –18 –105 0.5 1 10 100 500 10 100 1k Frequency (MHz) Resistance (Ω) DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE –55 –95 V = 2V f = 1MHz O PP –65 c) c) B B –100 d d n ( –75 n ( ortio 3rd-Harmonic ortio st –85 st –105 Di Di c c 2nd-Harmonic oni –95 oni m m ar 2nd-Harmonic ar –110 H H –105 3rd-Harmonic –115 –115 1 10 1 10 Frequency (MHz) Output Voltage Swing (V ) PP OPA2822 13 SBOS188E www.ti.com

APPLICATIONS INFORMATION For higher gains, the feedback resistor (R ) was held at 402Ω F and the gain resistor (R ) adjusted to develop the Typical G WIDEBAND NONINVERTING OPERATION Characteristics. The OPA2822 provides a unique combination of features in Voltage-feedback op amps, unlike current-feedback designs, a wideband dual, unity-gain stable, voltage-feedback ampli- can use a wide range of resistor values to set their gains. A low- fier to support the extremely high dynamic range require- noise part like the OPA2822 will deliver low total output noise ments of emerging communications technologies. Combin- only if the resistor values are kept relatively low. For the circuit ing low 2nV/√Hz input voltage noise with harmonic distortion of Figure 1, the resistors contribute an input-referred voltage performance that can exceed 100dBc SFDR through 2MHz, noise component of 1.8nV/√Hz, which is approaching the value the OPA2822 provides the highest dynamic range input of the amplifier’s intrinsic 2nV/√Hz. For a more complete interface for emerging high speed 14-bit (and higher) con- description of the feedback network’s impact on noise, see the verters. To achieve this level of performance, careful atten- Setting Resistor Values to Minimize Noise section later in this tion to circuit design and board layout is required. data sheet. In general, the parallel combination of R and R F G Figure 1 shows the gain of +2 configuration used as the basis should be < 300Ω to retain the low-noise performance of the for the Electrical Characteristics table and most of the Typical OPA2822. However, setting these values too low can impair Characteristics at ±6V operation. While the characteristics are distortion performance due to output loading, as shown in the given using split ±6V supplies, most of the electrical and typical distortion versus load data in the Typical Characteristics. characteristics also apply to a single-supply +12V design where the input and output operating voltages are centered at the WIDEBAND INVERTING OPERATION midpoint of the +12V supply. Operation at ±5V will very nearly Operating the OPA2822 as an inverting amplifier has several match that shown for the ±6V operating point. Most of the benefits and is particularly appropriate as part of the hybrid reference curves were characterized using signal sources with design in an xDSL receiver application. Figure 2 shows the 50Ω driving impedance, and with measurement equipment inverting gain of –1 circuit used as the basis of the inverting presenting a 50Ω load impedance. In Figure 1, the 50Ω shunt mode Typical Characteristics. resistor at the V terminal matches the source impedance of the I test signal generator, while the 50Ω series resistor at the V O terminal provides a matching resistor for the measurement +5V +V equipment load. Generally, data sheet voltage swing specifica- S tions are at the output pin (V in Figure 1), while output power 0.1µF 6.8µF O + (dBm) specifications are at the matched 50Ω load. The total 100Ω load at the output, combined with the total 804Ω total feedback network load for the noninverting configuration of 50Ω Load Figure 1, presents the OPA2822 with an effective output load of R 1/2 VO 50Ω 89Ω. While this is a good load value for frequency response 0.1µF 30S9Ω OPA2822 measurements, distortion will improve rapidly with lighter output loads. Keeping the same feedback network and increasing the 50Ω Source RG RF load to 200Ω will result in a total load of 160Ω for the distortion 604Ω 604Ω V performance reported in the Electrical Characteristics table. I R M 54.9Ω + 0.1µF 6.8µF +5V –V +V S S –5V 0.1µF 6.8µF + FIGURE 2. Inverting G = –1 Specification and Test 50Ω Source Circuit. V 50Ω Load I 50Ω OPA1/22822 VO 50Ω nIne ttwheo rkin vaeprptienagr sc aasse ,p aornt lyo ft hthee R tFo tealle omuetpnut to lfo athde infe epdabraalclekl with the actual load. For the 100Ω load used in the Typical R 402FΩ Characteristics, this gives an effective load of 86Ω in this inverting configuration. Gain resistor R is set to achieve the G R desired inverting gain (in this case 604Ω for a gain of –1), G 402Ω 0.1µF + 6.8µF while an additional input matching resistor (RM) can be used to set the total input impedance equal to the source if –V S desired. In this case, R = 54.9Ω in parallel with the 604Ω –5V M gain setting resistor yields a matched input impedance of 50Ω. R is needed only when the input must be matched to FIGURE 1. Noninverting G = +2 Specification and Test M a source impedance, as in the characterization testing done Circuit. using the circuit of Figure 2. OPA2822 14 www.ti.com SBOS188E

To take full advantage of the OPA2822’s excellent DC input The key requirement of broadband single-supply operation is accuracy, the total DC impedance seen at of each of the to maintain input and output signal swings within the usable input terminals must be matched to get bias current cancel- voltage range at both input and output. The circuit of Figure 3 lation. For the circuit of Figure 2, this requires the grounded establishes an input midpoint bias using a simple resistive 309Ω resistor on the noninverting input. The calculation for divider from the +5V supply (two 804Ω resistors). These two this resistor value assumes a DC-coupled 50Ω source resistors are selected to provide DC bias current cancellation impedance along with R and R . While this resistor will because their parallel combination matches the DC imped- G M provide cancellation for the input bias current, it must be ance looking out of the inverting node, which equals R . The F well decoupled (0.1µF in Figure 2) to filter the noise contri- gain setting resistor is not part of the DC impedance looking bution of the resistor itself and of the amplifier’s input out of the inverting node, due to the blocking capacitor in current noise. series with it. The input signal is then AC-coupled into the As the required R resistor approaches 50Ω at higher gains, midpoint voltage bias. The input impedance matching resistor G (57.6Ω) is selected for testing to give a 50Ω input match (at the bandwidth for the circuit in Figure 2 will far exceed the high frequencies) when the parallel combination of the biasing bandwidth at the same gain magnitude for the noninverting circuit of Figure 1. This occurs due to the lower noise gain for divider network is included. The gain resistor (RG) is AC- the circuit of Figure 2 when the 50Ω source impedance is coupled, giving a DC gain of +1. This centers the output also included in the analysis. For example, at a signal gain of at the input midpoint bias voltage (VS/2). While this circuit is –12 (R = 50Ω, R = open, R = 604Ω) the noise gain for the shown using a +5V supply, this same circuit may be applied G M F circuit of Figure 2 will be 1 + 604Ω/(50Ω + 50Ω) = 7, due to for single-supply operation as high as +12V. the addition of the 50Ω source in the noise gain equation. This will give considerably higher bandwidth than the nonin- SINGLE-SUPPLY INVERTING OPERATION verting gain of +12. For those single +5V Typical Characteristics that require inverting gain of –1 operation, the test circuit in Figure 4 was SINGLE-SUPPLY NONINVERTING OPERATION used. The OPA2822 can also support single +5V operation with its exceptional input and output voltage swing capability. +5V While not a rail-to-rail input/output design, both inputs and +V S outputs can swing to within 1.2V of either supply rail. For a single amplifier channel, this gives a very clean 2V output + PP R 0.1µF 6.8µF capability on a single +5V supply, or 4VPP output for a 1.B21kΩ differential configuration using both channels together. Fig- VS/2 RL ure 3 shows the AC-coupled noninverting gain of +2 used R 1/2 VO 100Ω as the basis of the Electrical Characteristics table and most 0.1µF 1.B21kΩ OPA2822 VS/2 of the Typical Characteristics for single +5V supply opera- tion. 50Ω Source RG RF 0.1µF 604Ω 604Ω V I +5V +VS R54M.9Ω + R 0.1µF 6.8µF B 0.1µF 804Ω FIGURE 4. AC-Coupled, G = –1, Single-Supply VI RVS/2 1/2 VO 10R0LΩ Operation: Specification and Test Circuit. 57.6Ω 80B4Ω OPA2822 VS/2 As with the circuit of Figure 2, the feedback resistor (R ) has F been increased to 604Ω to reduce the loading effect it has R F 402Ω in parallel with the 100Ω actual load. The noninverting input is biased at V /2 (2.5V in this case) using the two 1.21kΩ S RG resistors for RB. The parallel combination of these two 402Ω resistors (605Ω) provides input bias current cancellation by 0.1µF matching the DC impedance looking out of the inverting input node. The noninverting input bias is also well de- coupled using the 0.1µF capacitor to both reduce both FIGURE 3. AC-Coupled, G = +2, Single-Supply power-supply noise and the resistor and bias current noise Operation: Specification and Test Circuit. at this input. OPA2822 15 SBOS188E www.ti.com

The gain resistor (R ) is set to equal the feedback resistor (R ) The two sets of resistors, R and R , are set to provide the G F 1 2 at 604Ω to achieve the desired gain of –1 from V to V . A DC desired gain from the transformer windings for the signal I O blocking capacitor is included in series with R to reduce the DC arriving on the line side of the transformer, and also to provide G gain for the noninverting input bias and offset voltages to +1. nominal cancellation for the driver output signal (V ) to the D This places the V /2 bias voltage at the output pin and reduces receiver output. Typically, the two R resistors are set to S S the output DC offset error terms. The signal input impedance is provide impedance matching through the transformer. This is matched to the 50Ω source using the additional R resistor set accomplished by setting R = 0.5 • (R /N2), where N is the M S L to 54.9Ω. At higher frequencies, the parallel combination of R turns ratio used for the line driver design. If R is set in this M S and R provides the input impedance match at 50Ω. This is fashion, and the actual twisted pair line shows the expected R G L principally used for test and characterization purposes—system impedance value, the voltage swing produced at V will be cut D applications do not necessarily require this input impedance in half at the transformer input. In this case, setting R = 2 • R 1 2 match, particularly if the source device is physically near the will achieve cancellation of the driver output signal at the OPA2822 and/or does not require a 50Ω input impedance output of the receiver. Essentially, the driver output voltage match. At higher gains, the signal source impedance will start to produces a current in R that is exactly matched by the current 1 materially impact the apparent noise gain (and hence, band- pulled out of R due to the attenuated and inverted version of 2 width) of the OPA2822. the output signal at the transformer input. In actual practice, R 1 and R are usually RC networks to achieve cancellation over 2 ADSL RECEIVE AMPLIFIER the frequency varying line impedance. As the transformer turns ratio changes to support different line One of the principal applications for the OPA2822 is as a low- driver and supply voltage combinations, the impact of receiver power, low-noise receive amplifier in ADSL modem designs. Applications ranging from single +5V, ±5V, and up to single +12V amplifier noise changes. Typically, DSL systems incur a line referred noise contribution for the receiver that can be com- supplies can be well supported by the OPA2822. For higher puted for the circuit of Figure 5. For example, targeting an supplies, consider the dual, low-noise THS6062 ADSL receive amplifier that can support up to ±15V supplies. Figure 5 shows a overall gain of 1 from the line to the receiver output, and picking the input resistor R , the remaining resistors will be set typical ADSL receiver design where the OPA2822 is used as an 2 by the driver cancellation and gain requirements. With the inverting summing amplifier to provide both driver output signal resistor values set, a line referred noise contribution due to the cancellation and receive channel gain. In the circuit of Figure 5, OPA2822 can be computed. R will be set to 2x the value of the driver differential output voltage is shown as V , while the 1 D R , and the feedback resistor will be set to recover the gain receiver channel output is shown as V . 2 R loss through the transformer. Table I shows the total line referred noise floor (in dBm/Hz) using three different values for R over a range of transformer turns ratio (where the amplifier +5V 2 gain is adjusted at each turns ratio). 1/2 TABLE I. Line Referred Noise dBm/Hz, Due to Receiver OPA2822 Driver Op Amp. RS R2 RF N R2 = 200 R2 = 500 R2 = 1000 1 –151.5 –150.2 –148.5 R 1.5 –149.1 –147.6 –145.8 1 2 –147.2 –145.6 –143.7 2.5 –145.6 –144.0 –142.1 1:n 3 –144.3 –142.7 –140.7 VD RL Line VR 34.5 ––114423..22 ––114401..55 ––113389..45 4.5 –141.3 –139.5 –137.5 R1 5 –140.4 –138.7 –136.6 RS R2 RF Table I shows that a lower transformer turns ratio results in reduced line referred noise, and that the resistor noise will start to degrade the noise at higher values—particularly in 1/2 going from 500Ω to 1kΩ. In general, line referred noise floor OPA2822 due to the receiver channel will not be the limit to ADSL modem performance, if it is lower than –145dBm. –5V FIGURE 5. Example ADSL Receiver Amplifier. OPA2822 16 www.ti.com SBOS188E

ACTIVE FILTER APPLICATIONS As a low-noise, low-distortion, unity-gain stable, voltage- +V S feedback amplifier, the OPA2822 provides an ideal building +5V block for high-performance active filters. With two channels 365Ω available, it can be used either as a cascaded 2-stage active filter or as a differential filter. Figure 6 shows a 6th-order 2.2µF 2.2µF bandpass filter cascaded with two 2nd-order Sallen-Key sections, with transmission zeroes along with a passive post 1/2 filter made up of a high-pass and a low-pass section. The first OPA2822 amplifier provides a 2nd-order high-pass stage while the 2kΩ second amplifier provides the 2nd-order low-pass stage. 730Ω Figure 7 shows the frequency response for this example 1µF filter. V A differential active filter is shown in Figure 8. This circuit VI 2S VO shows a single-supply, 2nd-order high-pass filter with the 2kΩ corner frequencies set to provide the required high-pass 730Ω function for an ADSL CPE modem application. To use this circuit, the hybrid would be implemented as a passive sum- 1/2 ming circuit at the input to this filter. For +5V only ADSL 2.2µF 2.2µF OPA2822 designs, it is preferable to implement a portion of the filtering prior to the amplifier, thus limiting the amplitude of the 365Ω uncancelled line driver signals. This type of receiver stage would typically then drive a low-pass filter prior to the codec setting the high-frequency cutoff of the ADC (Analog-to- Digital Converter) input signal. Figure 9 shows the frequency FIGURE 8. Single-Supply, 2nd-Order High-Pass Active response for the high-pass circuit of Figure 8. Filter with Differential I/O. 2.2pF 180pF +5V 140Ω 2.1kΩ 158Ω 225Ω 1.8nF 300Ω 1/2 18pF 1/2 VI 1.0nF 1.0nF 1.3kΩ OPA2822 150pF 12pF OPA2822 VO 150Ω 66pF 143Ω 107Ω –5V FIGURE 6. 6th-Order Bandpass Filter. 10 3 0 0 –3 –10 –6 –9 B) –20 B) Gain (d –30 Gain (d ––1125 –18 –40 –21 –24 –50 –27 –60 –30 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+04 1.0E+05 1.0E+06 1.0E+07 Frequency (Hz) Frequency (Hz) FIGURE 7. Frequency Response for the Filter in Figure 6. FIGURE 9. Frequency Response for the Filter in Figure 8. OPA2822 17 SBOS188E www.ti.com

HIGH DYNAMIC RANGE ADC DRIVER transformer) and then R is set to get the desired overall F gain. With these constraints (and 0Ω on the noninverting Numerous circuit approaches exist to provide the last stage inputs), the noise figure equation simplifies considerably. of amplification before the ADC in high-performance applica- tsiiognnsa. l Fcohra vnenreyl hciagnh dbyen aAmCic-c oraunpgleed ,a pthpelic actiirocnusit wshheorwen t hine  4 2en21 + α1/n2+ 21(innRS)2 Figure 10 provides exceptional performance. Most very high NF=10log 2+ +  α kTR (1) performance ADCs > 12-bit performance require differential  S  inputs to achieve the dynamic range. The circuit of Figure 10   converts a single-ended source to differential via a 1:2 turns where R = 1/2 n2R ratio transformer, which then drives the inverting gain setting G S resistors (R ). These resistors are fixed at 100Ω to provide n = Transformer Turns Ratio G input matching to a 50Ω source on the transformer primary α = R /R F G side. The gain can then be adjusted by setting the feedback e = Op Amp Input Voltage Noise n resistor values. For best performance, this circuit operates i = Inverting Input Current Noise with a ground centered output on ±5V supplies, although a n kT = 4E – 21J[T = 290°K] +12V supply can also provide excellent results. Since most high-performance converters operate on a single +5V sup- Gain (dB)= 20 log[nα] ply, the output is level shifted through an AC blocking capacitor to the common-mode input voltage (V ) for the TABLE II. Noise Figure versus Gain with n = 2 Trans- CM converter input, and then low-pass filtered prior to the input former. of the converter. This circuit is intended for inputs from 10kHz REQUIRED to 10MHz, so the output high-pass corner is set to 1.6kHz, TOTAL GAIN LOG GAIN AMPLIFIER GAIN NOISE FIGURE while the low-pass cutoff is set to 20MHz. These are example (V/V) (dB) (α) (dB) cutoff frequencies; the actual filtering requirements would be 4 12.0 2 11.2 set by the specific application. 5 14.0 2.5 10.4 6 15.6 3 9.9 The 1:2 turns ratio transformer also provides an improvement 7 16.9 3.5 9.5 in input referred noise figure. Equation 1 shows the Noise 8 18.1 4 9.1 Figure (NF) calculation for this circuit, where R has been 9 19.1 4.5 8.9 G 10 20.0 5 8.6 constrained to provide an input match to R (through the S +5V +5V 0.1µF 80Ω 1/2 V I OPA2822 RS = 50Ω RG 100pF 100Ω R F 1kΩ V I 1:2 500Ω 14-Bit V R O VCM ADC G 100Ω RF 1µF Noise 1kΩ Figure Defined Here 0.1µF 80Ω 1/2 VI VO = 2 RF OPA2822 V R I G 100pF –5V FIGURE 10. Single-Ended to Differential High Dynamic Range ADC Driver. OPA2822 18 www.ti.com SBOS188E

DESIGN-IN TOOLS DEMONSTRATION BOARDS E NI Two printed circuit boards (PCBs) are available to assist in 1/2 the initial evaluation of circuit performance using the OPA2822 OPA2822 EO R in its two package options. Both of these are offered free of S IBN charge as unpopulated PCBs, delivered with a user’s guide. The summary information for these fixtures is shown in E RS Table III. R √4kTR F S TABLE III. Demonstration Fixtures by Package. √4kTR F 4kT RG IBI ORDERING LITERATURE 4kT = 1.6E –20J PRODUCT PACKAGE NUMBER NUMBER RG at 290°K OPA2822U SO-8 DEM-OPA-SO-2A SBOU003 OPA2822E MSOP-8 DEM-OPA-MSOP-2A SBOU004 FIGURE 11. Op Amp Noise Analysis Model. The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA2822 Dividing this expression by the noise gain (NG = 1 = R /R ) F G product folder. will give the total equivalent spot noise voltage referred to the noninverting input, as shown in Equation 3: MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is EN= ENI2 +(IBNRS)2 +4kTRS +IBNIRGF2+ 4kNTGRF (3) often a quick way to analyze the performance of the OPA2822 in its intended application. This is particularly true for video Inserting high resistor values into Equation 3 can quickly and RF amplifier circuits where parasitic capacitance and dominate the total equivalent input referred voltage noise. A inductance can play a major role in circuit performance. A 250Ω source impedance on the noninverting input will add as SPICE model for the OPA2822 is available through the TI much noise as the amplifier itself. If the noninverting input is web site (www.ti.com). These models do a good job of a DC bias path (as in inverting or in some single-supply predicting small-signal AC and transient performance under applications), it is critical to include a noise shunting capaci- a wide variety of operating conditions. They do not do as well tor with that resistor to limit the added noise impact of those in predicting the harmonic distortion characteristics. These resistors (see the example in Figure 2). models do not attempt to distinguish between the package types in their small-signal AC performance. FREQUENCY RESPONSE CONTROL OPERATING SUGGESTIONS Voltage-feedback op amps such as the OPA2822 exhibit decreasing closed-loop bandwidth as the signal gain is SETTING RESISTOR VALUES TO MINIMIZE NOISE increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the Electrical Char- Getting the full advantage of the OPA2822’s low input noise acteristics. Ideally, dividing GBP by the noninverting signal requires careful attention to the external gain setting and DC gain (also called the Noise Gain, NG) will predict the closed- biasing networks. The feedback resistor is part of the overall loop bandwidth. In practice, this principle holds true only output load (which can begin to degrade distortion if set too when the phase margin approaches 90°, as it does in higher low). With this in mind, a good starting point for design is to gain configurations. At low gains, most high-speed amplifiers select the feedback resistor as low as possible (consistent will show a more complex response with lower phase margin with loading distortion concerns), then continue with the and higher bandwidth than predicted by the GBP. The design, and set the other resistors as needed. To retain full OPA2822 is compensated to give a slightly peaked fre- performance, setting the feedback resistor in the range of 200Ω to 750Ω can provide a good start to the design. quency response at a gain of +2 (see the circuit in Figure 1). The 200MHz typical bandwidth at a gain of +2 far exceeds Figure 11 shows the full output noise analysis model for any that predicted by dividing the GBP of 240MHz by a gain of 2. op amp. The bandwidth predicted by the GBP is more closely correct The total output spot noise voltage can be computed as the as the gain increases. As shown in the Typical Characteris- square root of the sum of all squared output noise voltage tics, at a gain of +10, the –3dB bandwidth of 24MHz matches terms. Equation 2 shows the general form of this output noise that predicted by dividing the GBP by 10. voltage expression using the terms shown in Figure 11. EO= (ENI2+(IBNRS)2+4kTRS)NG2+(IBIRF)2+ 4kNTGRF (2) OPA2822 19 SBOS188E www.ti.com

Inverting operation offers some interesting opportunities to The resistor across the two inputs, R , can be used to NG increase the available signal bandwidth. When the source increase the noise gain while retaining the desired signal impedance is matched by the gain resistor (Figure 10 for gain. This can be used either to improve flatness at low gains example), the signal gain is (1 + R /R ) while the noise gain or to reduce the required value of R in capacitive load F G S is (1 + R /2R ). This reduces the noise gain almost by half, driving applications. This circuit was used with R adjusted F G NG extending the signal bandwidth and increasing the loop gain. to produce the gain flatness curve in the Typical Character- For instance, setting R = 500Ω in Figure 10 will give a signal istics. As shown in that curve, an R of 452Ω will give an NG F NG gain for the amplifier of 5V/V. However, including the 50Ω of 3 giving exceptional frequency response flatness at a source impedance reflected through the 1:2 transformer will signal gain of +2. Equation 4 shows the calculation for R NG give an additional 100Ω source impedance for the noise gain given a target noise gain (NG) and signal gain (G): analysis for each of the amplifiers. This reduces the noise gain tboa n1d w+id t5h0 o0fΩ a/2t 0le0aΩs t =2 430.M5VH/zV/3 .a5n =d 6r8eMsuHltzs. in an amplifier RNG=RNFG+R−SGG (4) where R = Total Source Impedance on the Noninverting S DRIVING CAPACITIVE LOADS Input [25Ω in Figure 12] One of the most demanding and yet very common load G = Signal Gain [1 + (RF/RG)] conditions for an op amp is capacitive loading. Often, the NG = Noise Gain Target capacitive load is the input of an ADC, including additional external capacitance which may be recommended to im- prove ADC linearity. A high-speed, high open-loop gain Using this technique to get initial frequency response flat- amplifier like the OPA2822 can be very susceptible to de- ness will significantly reduce the required series resistor creased stability and closed-loop frequency response peak- value to get a flat response at the capacitive load. Using the ing when a capacitive load is placed directly on the output best-case noise gain of 3 with a signal gain of 2 allows the pin. When the amplifier’s open-loop output resistance is required R to be reduced, as shown in Figure 13. Here, the S considered, this capacitive load introduces an additional pole required R versus Capacitive Load is replotted along with S in the signal path that can decrease the phase margin. data from the Typical Characteristics. This demonstrates that Several external solutions to this problem have been sug- the use of R = 452Ω across the inputs results in much NG gested. When the primary considerations are frequency lower required R values to achieve a flat response. S response flatness with low noise and distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor 100 between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but instead shifts it and adds a zero at a higher frequency. The NG = 2, RNG = ∞ additional zero acts to cancel the phase lag from the capaci- Ω) tive load pole, thus increasing the phase margin and improv- (S 10 ing stability. R NG = 3, R = 452Ω NG The Typical Characteristics show the recommended R ver- S sus capacitive load and the resulting frequency response at the load. For the OPA2822 operating at a gain of +2, the frequency response at the output pin is already slightly 1 peaked without the capacitive load, requiring relatively high 10 100 1000 values of R to flatten the response at the load. One way to Capacitive Load (pF) S reduce the required R value is to use the noise gain S FIGURE 13. Required R vs Noise Gain. adjustment circuit of Figure 12. S DISTORTION PERFORMANCE 50Ω Source The OPA2822 is capable of delivering exceptionally low distortion through approximately 5MHz signal frequency. 1/2 50Ω RNG OPA2822 While principally intended to provide very low noise and distortion through the maximum ADSL frequency of 1.1MHz, R the OPA2822 in a differential configuration can deliver lower F 402Ω than –85dBc distortions for a 4V swing through 5MHz. For PP applications requiring extremely low distortion through higher RG frequencies, consider higher slew rate amplifiers such as the 402Ω OPA687 or OPA2681. FIGURE 12. Noise Gain Tuning for Noninverting Circuit. OPA2822 20 www.ti.com SBOS188E

As the Typical Characteristics show, until the fundamental test frequencies. For example, at 1MHz in a gain of +2 signal reaches very high frequencies or power levels, the configuration, the OPA2822 exhibits an intercept of 57dBm limit to SFDR will be 2nd-harmonic distortion rather than the at a matched 50Ω load. If the full envelope of the two negligible 3rd-harmonic component. Focusing then on the frequencies needs to be 2V , each tone will be set to 4dBm. PP second harmonic, increasing the load impedance improves The 3rd-order intermodulation spurious tones will then be distortion directly. However, operating differentially offers 2 • (57 – 4) = 106dBc below the test-tone power level the most significant improvement in even-order distortion (–102dBm). If this same 2V 2-tone envelope were deliv- PP terms. For example, the Electrical Characteristics show that ered directly into the input of an ADC without the matching a single channel of the OPA2822, delivering 2V at 1MHz loss or loading of the 50Ω network, the intercept would PP into a 200Ω load, will typically show a 2nd-harmonic product increase to at least 63dBm. With the same signal and gain at –92dBc versus the 3rd-harmonic at –102dBc. Changing conditions but now driving directly into a light load, the the configuration to a differential driver where each output spurious tones would then be at least 2 • (63 – 4) = 118dBc still drives 2V results in a 4V total differential output into below the test-tone power levels. PP PP a 400Ω differential load, giving the same single-ended load of 200Ω for each amplifier. This configuration drops the DC ACCURACY AND OFFSET CONTROL 2nd-harmonic to –103dBc and the 3rd-harmonic to approxi- The OPA2822 can provide excellent DC signal accuracy due mately –105dBc—an overall dynamic range improvement to its high open-loop gain, high common-mode rejection, high of more than 10dB. power-supply rejection, and low input offset voltage and bias For general distortion analysis, remember that the total current offset errors. To take full advantage of the low input loading on the amplifier includes the feedback network; in the offset voltage (±1.2mV maximum at 25°C), careful attention noninverting configuration, this is the sum of R + R , while F G to input bias current cancellation is also required. The high- in the inverting configuration this additional loading is simply speed input stage for the OPA2822 has relatively high input RF. Increasing the output voltage swing increases the har- bias current (8µA typical into the pins) but with a very close monic distortion directly. A 6dB increase in the output swing match between the two input currents, typically 100nA input will generally increase the 2nd-harmonic 12dB and the 3rd- offset current. The total output offset voltage may be reduced harmonic 18dB. Increasing the signal gain will also generally considerably by matching the source impedances looking out increase both the 2nd- and 3rd-harmonics because the loop of the two inputs. For example, one way to add bias current gain decreases at higher gains. Again, a 6dB increase in cancellation to the circuit of Figure 1 would be to insert a voltage gain will increase the 2nd-harmonic distortion by 175Ω series resistor into the noninverting input from the 50Ω approximately 6dB. The distortion characteristic curves for terminating resistor. If the 50Ω source resistor is DC coupled, the OPA2822 show little change in the 3rd-harmonic distor- this will increase the source impedance for the noninverting tion versus gain. Finally, the overall distortion generally input bias current to 200Ω. Since this is now equal to the increases as the fundamental frequency increases due to the impedance looking out of the inverting input (R || R ), the F G rolloff in the loop gain with frequency. Conversely, the distor- circuit will cancel the bias current effects, leaving only the tion will improve going to lower frequencies, down to the offset current times the feedback resistor as a residual DC dominant open-loop pole at approximately 50kHz. This will error term at the output. Using a 402Ω feedback resistor, the give essentially unmeasurable levels of harmonic distortion output DC error due to the input bias currents will now be less in the audio band. than 0.7µA • 402Ω = 0.28mV over the full temperature range. The OPA2822 exhibits an extremely low 3rd-order harmonic This is significantly lower than the contribution due to the distortion. This also gives exceptionally good 2-tone 3rd- input offset voltage. At a gain of +2, the maximum input offset order intermodulation intercept as shown in the Typical voltage is 1.5mV, giving a total maximum output offset of Characteristics. This intercept curve is defined at the 50Ω (±3mV ± 0.28mV) = ±3.3mV over the –40°C to +85°C load when driven through a 50Ω matching resistor to allow temperature range (for the circuit of Figure 1, including the direct comparisons to RF MMIC devices. This network at- additional 175Ω resistor at the noninverting input). tenuates the voltage swing from the output pin to the load by 6dB. If the OPA2822 drives directly into the input of a high- THERMAL ANALYSIS impedance device, such as an ADC, this 6dB attenuation The OPA2822 will not require heatsinking or airflow under does not occur. Under these conditions, the intercept will most operating conditions. Maximum desired junction tem- improve by at least 6dBm. The intercept is used to predict the perature will limit the maximum allowed internal power dissi- intermodulation spurs for two closely spaced frequencies. If pation as described below. In no case should the maximum the two test frequencies, f and f , are specified in terms of average and delta frequenc1y, f =2 (f + f )/2 and ∆ = |f – f |, junction temperature be allowed to exceed +150°C. O 1 2 F 2 1 the two, 3rd-order, close-in spurious tones will appear at Operating junction temperature (T) is given by T + P θ . J A D JA f ± 3 • ∆ . The difference between two equal test-tone power The total internal power dissipation (P ) is the sum of the O F D levels and the spurious intermodulation power levels is given quiescent power (P ) and additional power dissipated in the DO by ∆dBc = 2 • (IM3 – P ), where IM3 is the intercept taken output stage (P ) to deliver load power. Quiescent power is O DL from the Typical Specification and P is the power level in simply the specified no-load supply current times the total O dBm at the 50Ω load for either one of the two closely spaced supply voltage across the part. P will depend on the required DL OPA2822 21 SBOS188E www.ti.com

output signal and load but would, for a grounded resistive load, c) Careful selection and placement of external compo- be at a maximum when the output is fixed at a voltage equal nents will preserve the high-frequency performance of to half of either supply voltage (assuming equal bipolar sup- the OPA2822. Resistors should be a very low reactance plies). Under this condition P = V 2/(4 • R ) where R type. Surface-mount resistors work best and allow a tighter DL S L L includes feedback network loading. overall layout. Metal film and carbon composition axially leaded resistors can also provide good high-frequency per- Note that it is the power dissipated in the output stage and not in formance. Again, keep their leads and PCB trace length as the load that determines internal power dissipation. As a worst- short as possible. Never use wire-wound type resistors in a case example, compute the maximum T for the OPA2822E with J both channels operating at A = +2, R = 100Ω, R = 400Ω, high-frequency application. Since the output pin and invert- V L F ±V = ±5V, and at the specified maximum T = 85°C. ing input pin are the most sensitive to parasitic capacitance, S A always position the feedback and series output resistor, if P = 10V • 11.4mA + 2 • (52)/(4 • (100 || 804)) = 255mW D any, as close as possible to the output pin. Other network Maximum TJ = 85°C + 0.255W • 150°C/W = 123°C components, such as noninverting input termination resis- This calculation represents a worst-case combination of tors, should also be placed close to the package. Even with conditions to reach a maximum possible operating junction a low parasitic capacitance shunting the external resistors, temperature. Under most operating conditions, the junction excessively high resistor values can create significant time temperature will be far lower than the 123°C calculated here. constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in The output current is limited in the OPA2822 to protect shunt with the resistor. For resistor values > 1.5kΩ, this against damage under short-circuit conditions. This current- parasitic capacitance can add a pole and/or zero below limited output of approximately 220mA exceeds the rated 500MHz that can effect circuit operation. Keep resistor val- typical output current of 150mA. The typical and minimum ues as low as possible consistent with parasitic load, distor- output current limits are set for linear operation while the tion, and noise considerations. The 402Ω feedback used in maximum output shown in the Typical Characteristics is the Typical Characteristics is a good starting point for design. nonlinear limited performance. d) Connections to other wideband devices on the board may BOARD LAYOUT be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to Achieving optimum performance with a high-frequency am- the next device as a lumped capacitive load. Relatively wide plifier like the OPA2822 requires careful attention to board traces (50mils to 100mils) should be used, preferably with ground layout parasitics and external component types. Recommen- and power planes opened up around them. Estimate the total dations that will optimize performance include: capacitive load and set R from the plot of recommended R S S a) Minimize parasitic capacitance to any AC ground for all versus capacitive load. If a long trace is required, and the 6dB of the signal I/O pins. Parasitic capacitance on the output and signal loss intrinsic to a doubly-terminated transmission line is inverting input pins can cause instability: on the noninverting acceptable, implement a matched impedance transmission line input, it can react with the source impedance to cause using microstrip or stripline techniques (consult an ECL design unintentional bandlimiting. To reduce unwanted capacitance, handbook for microstrip and stripline layout techniques). A 50Ω a window around the signal I/O pins should be opened in all environment is normally not necessary onboard, and in fact a of the ground and power planes around those pins. Other- higher impedance environment will improve distortion as shown wise, ground and power planes should be unbroken else- in the distortion versus load plots. With a characteristic board where on the board. trace impedance defined based on board material and trace b) Minimize the distance (< 0.25") from the power-supply dimensions, a matching series resistor into the trace from the pins to high-frequency 0.1µF decoupling capacitors. At the output of the OPA2822 is used as well as a terminating shunt device pins, the ground and power plane layout should not resistor at the input of the destination device. Remember also that be in close proximity to the signal I/O pins. Avoid narrow the terminating impedance will be the parallel combination of the power and ground traces to minimize inductance between shunt resistor and the input impedance of the destination device; the device pins and the decoupling capacitors. The primary this total effective impedance should be set to match the trace power-supply connections (on pins 4 and 8) should always impedance. Multiple destination devices are best handled as be decoupled with these capacitors. Larger (2.2µF to 6.8µF) separate transmission lines, each with their own series and shunt decoupling capacitors, effective at lower frequencies, should terminations. If the 6dB attenuation of a doubly-terminated trans- also be used on the main supply pins. These may be placed mission line is unacceptable, a long trace can be series-termi- somewhat farther from the device and may be shared among nated at the source end only. Treat the trace as a capacitive load several devices in the same area of the PCB. in this case and set the series resistor value as shown in the plot of R vs Capacitive Load. This will not preserve signal integrity as S OPA2822 22 www.ti.com SBOS188E

well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation +V CC due to the voltage divider formed by the series output into the terminating impedance. External Internal e) Socketing a high-speed part like the OPA2822 is not Pin Circuitry recommended. The additional lead length and pin-to-pin ca- pacitance introduced by the socket can create an extremely –V troublesome parasitic network, which can make it almost impos- CC sible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2822 onto the board. FIGURE 14. Internl ESD Protection. These diodes provide moderate protection to input overdrive INPUT AND ESD PROTECTION voltages above the supplies as well. The protection diodes can The OPA2822 is built using a very high-speed complementary typically support 30mA continuous current. Where higher cur- bipolar process. The internal junction breakdown voltages are rents are possible (for example, in systems with ±15V supply relatively low due to these very small geometry devices. These parts driving into the OPA2822), current-limiting series resistors breakdowns are reflected in the Absolute Maximum Rating should be added into the two inputs. Keep these resistor values table. All device pins are protected with internal ESD protection as low as possible since high values degrade both noise diodes to the power supplies, as shown in Figure 14. performance and frequency response. OPA2822 23 SBOS188E www.ti.com

Revision History DATE REVISION PAGE SECTION DESCRIPTION 8/08 E 2 Abs Max Ratings Changed Storage Temperature Range from −40°C to +125°C to −65°C to +125°C. 8 Typical Characteristics Axis text change on, Closed-Loop Output Impedance vs Frequency. 5/06 D 19 Design-In Tools Demonstration fixture numbers changed. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. OPA2822 24 www.ti.com SBOS188E

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA2822E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D22 & no Sb/Br) OPA2822E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D22 & no Sb/Br) OPA2822U ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2822U OPA2822U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2822U OPA2822UG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2822U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA2822E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2822E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2822U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA2822E/250 VSSOP DGK 8 250 210.0 185.0 35.0 OPA2822E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 OPA2822U/2K5 SOIC D 8 2500 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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