OPA2694 SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 Dual, Wideband, Low-Power, Current Feedback Operational Amplifier FEATURES DESCRIPTION (cid:2) UNITY GAIN STABLE BANDWIDTH: 1500MHz The OPA2694 is a dual, ultra-wideband, low-power, current (cid:2) HIGH GAIN OF 2V/V BANDWIDTH: 690MHz feedback operational amplifier f eaturing high slew rate and (cid:2) low differential gain/phase errors. An improved output stage LOW SUPPLY CURRENT: 5.8mA/ch provides ±70mA output drive with < 1.5V output voltage (cid:2) HIGH SLEW RATE: 1700V/μs headroom. Low supply current with > 500MHz bandwidth (cid:2) HIGH FULL-POWER BANDWIDTH: 670MHz meets the requirements of high density video routers. Being (cid:2) LOW DIFFERENTIAL GAIN/PHASE: a current feedback design, the OPA2694 holds its bandwidth 0.03%/0.015(cid:2) to very high gains—at a gain of 10, the OPA2694 will still provide > 200MHz bandwidth. RF applications can use the OPA2694 as a low-power SAW APPLICATIONS pre-amplifier. Extremely high 3rd-order intercept is provided through 70MHz at much lower quiescent power than many (cid:2) MEDICAL IMAGING typical RF amplifiers. (cid:2) WIDEBAND VIDEO LINE DRIVER The OPA2694 is available in an industry-standard pinout in (cid:2) DIFFERENTIAL RECEIVER an SO-8 package. (cid:2) ADC DRIVER (cid:2) HIGH-SPEED SIGNAL PROCESSING 100pF (cid:2) PULSE AMPLIFIER (cid:2) IMPROVED REPLACEMENT FOR OPA2658 +5V 50Ω 232Ω 20Ω 1/2 RELATED PRODUCTS OPA2694 SINGLES DUALS TRIPLES QUADS FEATURES OPA694 — — — 800Ω 357Ω OPA683 OPA2683 — — Low-Power, CFBPLUS OPA684 OPA2684 OPA3684 OPA4684 Low-Power, CFBPLUS VI 75pF 400Ω 800Ω 357Ω 22pF VO OPA691 OPA2691 OPA3691 — High Output Current OPA695 OPA2695 OPA3695 — High Intercept 1/2 50Ω 232Ω 20Ω OPA2694 100pF −5V Low-Power, Differential I/O, 3rd-Order Butterworth Active Filter Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products Copyright © 2004−2008, Texas Instruments Incorporated conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS(1) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6.5VDC handled with appropriate precautions. Failure to observe Internal Power Dissipation. . . . . . . . . See Thermal Characteristics proper handling and installation procedures can cause damage. Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2V ESD damage can range from subtle performance degradation to Input Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS complete device failure. Precision integrated circuits may be more Storage Temperature Range: D, DBV . . . . . . . . . −65°C to +125°C susceptible to damage because very small parametric changes could Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C cause the device not to meet its published specifications. Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 3000V Charge Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . 1000V Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. PACKAGE/ORDERING INFORMATION(1) SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY OPA2694ID Rails, 100 OOPPAA22669944 SSOO-88 DD −4400°°CC tto +8855°°CC OOPPAA22669944 OPA2694IDR Tape and Reel, 2500 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATION TOP VIEW SO-8 OutA 1 8 +V S −InA 2 7 OutB +InA 3 6 −InB −V 4 5 +InB S 2

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS: V = ±5V S Boldface limits are tested at +25°C. At R = 402Ω, R = 100Ω, and G = +2V/V, unless otherwise noted. F L OPA2694ID TYP MIN/MAX OVER TEMPERATURE 0°C to −40°C to MIN/ TEST PARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3) AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth G = +1, VO = 0.5VPP, RF = 430Ω 1500 MHz typ C G = +2, VO = 0.5VPP, RF =390Ω 690 340 330 320 MHz min B G = +5, VO = 0.5VPP, RF = 330Ω 250 190 170 150 MHz min B G = +10, VO = 0.5VPP, RF = 180Ω 200 140 120 110 MHz min B Bandwidth for 0.1dB Gain Flatness G = +1, VO = 0.5VPP, RF = 430Ω 90 MHz min B Peaking at a Gain of +1 VO ≤ 0.1VPP, RF = 430Ω 2 dB typ C Large-Signal Bandwidth G = +2, VO = 2VPP 670 MHz typ C Slew Rate G = +2, 2V Step 1700 1300 1275 1250 V/μs min B Rise Time and Fall Time G = +2, VO = 0.2V Step 0.8 ns typ C Settling Time to 0.01% G = +2, VO = 2V Step 20 ns typ C to 0.1% G = +2, VO = 2V Step 13 ns typ C Harmonic Distortion G = +2, f = 5MHz, VO = 2VPP — — — — 2nd-Harmonic RL = 100Ω −85 −78 −72 −70 dBc max B RL ≥ 500Ω −92 −87 −85 −83 dBc max B 3rd-Harmonic RL = 100Ω −72 −68 −66 −65 dBc max B RL ≥ 500Ω −93 −87 −85 −83 dBc max B Input Voltage Noise f > 1MHz 2.1 2.5 2.9 3.1 nV/√Hz max B Inverting Input Current Noise f > 1MHz 22 25 26 29 pA/√Hz max B Non-inverting Input Current Noise f > 1MHz 24 27 28 30 pA/√Hz max B NTSC Differential Gain VO = 1.4VPP, RL = 150Ω 0.03 % max C VO = 1.4VPP, RL = 37.5Ω 0.05 % max C NTSC Differential Phase G = +2, VO − 1.4VPP, RL = 150Ω 0.015 ° typ C VO − 1.4VPP, RL = 37.5Ω 0.15 ° typ C Channel-to-Channel Crosstalk f = 5MHz 63 dB typ C DC PERFORMANCE(4) Open-Loop Transimpedance VO = 0V, RL = 100Ω 145 88 63 58 kΩ min A Input Offset Voltage VCM = 0V ±0.7 ±3.2 ±3.9 ±4.3 mV max A Average Input Offset Voltage Drift VCM = 0V — 12 15 μV/°C max B Channel to Channel ΔVIO VCM = 0V ±0.5 mV typ C Noninverting Input Bias Current VCM = 0V ±5 ±22 ±28 ±33 μA max A Average Input Bias Current Drift VCM = 0V — ±100 ±150 nA/°C max B Channel to Channel ΔIBI VCM = 0V ±5 μA typ C Inverting Input Bias Current VCM = 0V ±4 ±20 ±28 ±40 μA max A Average Input Bias Current Drift VCM = 0V — ±150 ±200 nA/°C max B Channel to Channel ΔIBN VCM = 0V ±4 μA typ C INPUT Common-Mode Input Voltage(5) (CMIR) ±2.5 ±2.3 ±2.2 ±2.1 V min A Common-Mode Rejection Ratio (CMRR) VCM = 0V 60 54 52 50 dB min A Noninverting Input Impedance 280 || 1.2 kΩ || pF typ C Inverting Input Resistance Open-Loop 30 Ω typ C OUTPUT Voltage Output Voltage No Load ±4 ±3.8 ±3.7 ±3.6 V min A RL = 100Ω ±3.4 ±3.1 ±3.1 ±3.0 V min A Output Current VO = 0V ±70 ±55 ±53 ±45 mA min A Short-Circuit Output Current VO = 0V ±200 mA typ C Closed-Loop Output Impedance G = +2, f =100kHz 0.02 Ω typ C (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits. 3

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS: V = ±5V (continued) S Boldface limits are tested at +25°C. At R = 402Ω, R = 100Ω, and G = +2V/V, unless otherwise noted. F L OPA2694ID TYP MIN/MAX OVER TEMPERATURE 0°C to −40°C to MMMIIINNN/// TTTEEESSSTTT PPPAAARRRAAAMMMEEETTTEEERRR CCCOOONNNDDDIIITTTIIIOOONNNSSS +25°C +25°C(1) 70°C(2) +85°C(2) UUUNNNIIITTTSSS MMMAAAXXX LLLEEEVVVEEELLL(((333))) POWER SUPPLY Specified Operating Voltage ±5 V typ C Maximum Operating Voltage Range — ±6.3 ±6.3 ±6.3 V max A Minimum Operating Voltage Range — ±3.5 ±3.5 ±3.5 mA max B Maximum Quiescent Current VS = ±5V, Both Channels 11.6 12.1 12.5 12.7 mA max A Minimum Quiescent Current VS = ±5V, Both Channels 11.6 11.1 10.5 9.9 mA min A Power-Supply Rejection Ratio (PSRR) Input-Referred 58 53 51 49 dB min A THERMAL CHARACTERISTICS Specification: ID −40 to +85 °C typ C Thermal Resistance (cid:2)JA Junction-to-Ambient — — — — D SO-8 125 °C/W typ C (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limits; junction temperature = ambient +15°C at high temperature limit for over temperature specifications. (3) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at ±CMIR limits. 4

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: V = ±5V S RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted NONINVERTINGSMALL−SIGNAL INVERTINGSMALL−SIGNAL FREQUENCYRESPONSE FREQUENCYRESPONSE 3 3 0 RGF==+420V2/ΩV VORL==0.150V0PΩP 0 RGF==−413V0/ΩV VORL==0.150V0PΩP B) B) −3 d d Gain( −3 Gain( −6 RG==−420V2/ΩV F d d malize −6 G=+10V/V G=+5V/V malize −9 G=−10V/V Nor −9 RF=178Ω RF=318Ω Nor−−1125 RF=500Ω G=−5V/V R =318Ω See Figure 1 See Figure 2 F −12 −18 0 200 400 600 800 1000 0 200 400 600 800 1000 1200 Frequency(MHz) Frequency(MHz) NONINVERTINGLARGE−SIGNAL INVERTINGLARGE−SIGNAL FREQUENCYRESPONSE FREQUENCYRESPONSE 9 9 6 VO=1VPP RGF==+420V2/ΩV 6 VO=2VPP RGF==−420V2/ΩV V =4V O PP 3 3 B) 0 B) 0 d d ( ( n n ai −3 ai −3 G G V =2V −6 O PP −6 VO=7VPP VO=7VPP −9 −9 See Figure 1 VO=4VPP See Figure 2 VO=1VPP −12 −12 0 200 400 600 800 1000 1200 1400 0 200 400 600 800 1000 1200 1400 Frequency(MHz) Frequency(MHz) NONINVERTING INVERTING PULSERESPONSE PULSERESPONSE 3 0.6 3 0.6 G=+2V/V SeeFigure1 G=−2V/V SeeFigure2 2 LargeSignal,5VPP 0.4 v) 2 LargeSignal,5VPP 0.4 v) Voltage(1V/div) 10 SmaRllLiSegifhgttnSSaccla,al0ele.5VPP 00.2 oltage(200mV/di Voltage(1V/div) 10 SmaRllLiSegifhgttnSSaccla,al0ele.5VPP 00.2 oltage(200mV/di ut −1 −0.2 V ut −1 −0.2 V utp put utp put O ut O ut −2 −0.4 O −2 −0.4 O −3 −0.6 −3 −0.6 Time(5ns/div) Time(5ns/div) 5

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: V = ±5V (continued) S RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted HARMONICDISTORTION HARMONICDISTORTION vsLOADRESISTANCE vsSUPPLYVOLTAGE −65 −65 G=+2V/V −70 f=5MHz −70 Bc) VO=2VPP Bc) 3rdHarmonic n(d −75 n(d −75 o o storti −80 storti −80 Di 3rdHarmonic Di onic −85 onic −85 m m G=+2V/V Har −90 2ndHarmonic Har −90 f=5MHz 2ndHarmonic V =2V O PP −95 See Figure 1 −95 RL=100Ω See Figure 1 100 1000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Resistance(Ω) SupplyVoltage(±VS) HARMONICDISTORTION 5MHzHARMONICDISTORTION vsFREQUENCY vsOUTPUTVOLTAGE −65 −65 G=+2V/V G=+2V/V −70 RL=100Ω −70 RL=100Ω Bc) VO=2VPP 3rdHarmonic Bc) f=5MHz 3rdHarmonic n(d −75 n(d −75 o o Distorti −80 Distorti −80 onic −85 onic −85 2ndHarmonic m m ar ar H −90 H −90 2ndHarmonic See Figure 1 See Figure 1 −95 −95 0.1 1 10 0.1 1 10 Frequency(MHz) OutputVoltageSwing(VPP) HARMONICDISTORTION HARMONICDISTORTION vsNONINVERTINGGAIN vsINVERTINGGAIN −60 −60 SeeFigure1 −65 −65 c) c) dB dB 3rdHarmonic ( −70 ( −70 n n o o storti −75 3rdHarmonic storti −75 Di Di onic −80 onic −80 2ndHarmonic m m ar 2ndHarmonic R =100Ω ar R =100Ω H −85 f=L5MHz H −85 f=L5MHz VO=2VPP See Figure 2 VO=2VPP −90 −90 1 10 1 10 Gain(V/V) Gain(|V/V|) 6

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: V = ±5V (continued) S RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted INPUTVOLTAGE 2−TONE,3rd−ORDER ANDCURRENTNOISE INTERMODULATIONINTERCEPT 1k 55 P 50Ω I 50 50Ω PO Hz) Hz) NoninvertingCurrentNoise(24pA/√Hz) m) 45 390Ω 50Ω √V/√A/ 100 +dB se(n se(p oint( 40 390Ω oi oi P VoltageN CurrentN 10 InvertingCurrentNoise(22pA/√Hz) Intercept 3350 VoltageNoise(2.1nV/√Hz) 25 1 20 10 100 1k 10k 100k 1M 10M 100M 0 10 20 30 40 50 60 70 80 90 100 Frequency(Hz) Frequency(MHz) RECOMMENDEDR FREQUENCYRESPONSE S vsCAPACITIVELOAD vsCAPACITIVELOAD 60 3 0dBPeakingTargeted CL=10pF 0 50 C =22pF B) −3 CL=100pF L 40 (d C =47pF n L ai −6 Ω) G R(S30 alized −9 5V0IΩ OP1A/22694 RS VO 20 orm−12 390Ω CL 1kΩ(1) N 10 −15 390Ω NOTE:(1)1kΩloadisoptional 0 −18 10 100 1M 10M 100M 1G CapacitiveLoad(pF) Frequency(Hz) COMMON−MODEREJECTIONRATIO OPEN−LOOPZ ANDPOWER−SUPPLYREJECTIONRATIO OL GAINANDPHASE vsFREQUENCY 120 30 70 CMRR 110 0 60 +PSRR ΩB)100 −30 (cid:3)() d e (dB) (dB) 5400 Gain(OL 9800 <ZOL −−6900 ZPhasOL CMRR PSRR 3200 −PSRR n−LoopZ 7600 20log|ZOL| −−112500 en−Loop e p p O 10 O 50 −180 40 −210 0 100 1K 10K 100K 1M 10M 100M 1G 100 1K 10K 100K 1M 10M 100M Frequency(Hz) Frequency(Hz) 7

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: V = ±5V (continued) S RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted VIDEODIFFERENTIALGAIN/DIFFERNTIALPHASE TYPICALDCDRIFT (NoPulldown) OVERTEMPERATURE 0.08 0.16 1.0 10 dPPositiveVideo InputOffsetVoltage(VOS) μA) DifferentialGain(%) 000...000642 ddGGNPeogsaittiivveeVViiddeeoo 000...100284 (cid:3)DifferentialPhase() nputOffsetVoltage(mV) −00..505 NoLneinftveSrctianlgeRInigphuttSBInciavaelsertCinugrrIenRnpitgu(htIBtBNSi)acsalCeurrent(IBI) 50−5 BiasandOffsetCurrent( I ut p n dPNegativeVideo I 0 0 −1.0 −10 1 2 3 4 −50 −25 0 +25 +50 +75 +100 +125 VideoLoads AmbientTemperature((cid:3)C) OUTPUTVOLTAGE SUPPLYANDOUTPUTCURRENT ANDCURRENTLIMITATIONS vsTEMPERATURE 4 75.0 18 1WInternalPowerLimit 3 R =100Ω L Voltage(V) 210 Output RL=50Ω RL=25Ω COLuuirtmrpeuitntt Current(mA) 7720..50 Sinking,SouLrecfitnSgcOaluetputCurrent 1164 Current(mA) Output −−12 CLuirmreitnt Output 67.5 12 Supply −3 SupplyCurrent RightScale −4 1WInternalPowerLimit 65.0 10 −200 −100 0 100 200 −50 −25 0 +25 +50 +75 +100 +125 OutputCurrent(mA) AmbientTemperature((cid:3)C) NONINVERTING INVERTING OVERDRIVERECOVERY OVERDRIVERECOVERY 8 4 4 4 RL=100Ω RL=100Ω G=+2V/V G=−1V/V 4 2 2 2 Voltage(V) 0 (LeOftuStpcuatle) 0 Voltage(V) Voltage(V) 0 IRnipguhttScale 0 Voltage(V) Output −4 −2 Input Output −2 LeftOSuctpaulet −2 Input Input See Figure 1 (RightScale) See Figure 2 −8 −4 −4 −4 Time(10ns/div) Time(10ns/div) 8

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: V = ±5V (continued) S RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted CHANNEL−TO−CHANNEL CROSSTALK −10 −20 B) (d−30 k al st−40 s o Cr−50 d e err−60 ef R ut−70 p In−80 −90 1 10 100 Frequency(MHz) 9

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 TYPICAL CHARACTERISTICS: V = ±5V (continued) S RF = 402Ω, RL = 100Ω, and G = +2V/V, unless otherwise noted DifferentialPerformanceTestCircuit DIFFERENTIALSMALL−SIGNAL FREQUENCYRESPONSE +5V 3 G =10V/V G =5V/V D D R =250Ω R =330Ω 1/2 0 F F OPA2694 B) (d −3 RG RF ain V G I RT RG RF R40L0Ω VO malized −−69 RGFD==420V2/ΩV Nor RGD==413V0/ΩV −12 F 1/2 R =400Ω L OPA2694 V R V =200mV VO =RF = GD −15 O PP I G 0 50 100 150 200 250 300 350 400 450 500 550600 −5V Frequency(MHz) DIFFERENTIALLARGE−SIGNAL DIFFERENTIALDISTORTION FREQUENCYRESPONSE vsLOADRESISTANCE 9 −60 VO=4VPP GRLD==420V0/VΩ −65 Gf=D5=M2HVz/V dB) 6 VO=2VPP (dBc)−70 VO=4VPP 3rdHarmonic ( n Gain 3 ortio−75 d st ze VO=1VPP Di−80 ormali 0 VO=8VPP monic−85 N −3 Har 2ndHarmonic −90 −6 −95 0 50 100 150 200 250 300 350 400 450 500 10 100 1k Frequency(MHz) Resistance(Ω) DIFFERENTIALDISTORTION DIFFERENTIALDISTORTION vsFREQUENCY vsOUTPUTVOLTAGE −65 −60 −70 GRLD==4+020VΩ/V −65 Gf=D5=M+H2zV/V Bc) VO=4VPP Bc) −70 RL=400Ω on(d −75 on(d −75 3rdHarmonic Distorti −80 3rdHarmonic Distorti −−8805 c 2ndHarmonic c oni −85 oni −90 m m ar ar −95 H −90 H 2ndHarmonic −100 −95 −105 1 10 100 0.1 1 10 20 Frequency(MHz) OutputVoltageSwing(VPP) 10

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 APPLICATION INFORMATION Figure 2 shows the DC-coupled, gain of −2V/V, dual power-supply circuit used as the basis of the inverting WIDEBAND CURRENT FEEDBACK OPERATION Typical Characteristic curves. Inverting operation offers several performance benefits. Since there is no The OPA2694 provides exceptional AC performance for a common-mode signal across the input stage, the slew rate wideband, low-power, current-feedback operational for inverting operation is higher and the distortion amplifier. Requiring only 5.8mA/ch quiescent current, the performance is slightly improved. An additional input OPA2694 offers a 690MHz bandwidth at a gain of +2, resistor, R , is included in Figure 2 to set the input T along with a 1700V/μs slew rate. An improved output stage impedance equal to 50Ω. The parallel combination of R T provides ±70mA output drive, along with < 1.5V output and R sets the input impedance. Both the noninverting G voltage headroom. This combination of low power and and inverting applications of Figure 1 and Figure 2 will high bandwidth can benefit high-resolution video benefit from optimizing the feedback resistor (R ) value for F applications. bandwidth (see the discussion in Setting Resistor Values to Optimize Bandwidth). The typical design sequence is to Figure 1 shows the DC-coupled, gain of +2, dual power- supply circuit configuration used as the basis of the ±5V select the RF value for best bandwidth, set RG for the gain, then set R for the desired input impedance. As the gain Electrical Characteristic tables and Typical Characteristic T increases for the inverting configuration, a point will be curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is reached where RG will equal 50Ω, where RT is removed set to 50Ω with a series output resistor. Voltage swings and the input match is set by RG only. With RG fixed to achieve an input match to 50Ω, R is simply increased, to reported in the Electrical Charateristics are taken directly F increase gain. This will, however, quickly reduce the at the input and output pins, while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, achievable bandwidth, as shown by the inverting gain of the total effective load will be 100Ω || 804Ω = 89Ω. One –10 frequency response in the Typical Characteristic curves. For gains > 10V/V (14dB at the matched load), optional component is included in Figure 1. In addition to noninverting operation is recommended to maintain the usual power-supply decoupling capacitors to ground, a 0.01μF capacitor is included between the two broader bandwidth. power-supply pins. In practical PCB layouts, this optional added capacitor will typically improve the 2nd-harmonic +5V distortion performance by 3dB to 6dB. +VS + 0.1μF 6.8μF +5V +V S + 20Ω 50ΩLoad 50ΩSource 0.1μF 6.8μF 1/2 VO 50Ω OPA2694 50ΩLoad VI 50Ω 1/2 VO 50Ω OPA2694 Optional 0.01μF Optional 50ΩSource 20R0GΩ 40R2FΩ 0.01μF R VI F 402Ω R T 66.5Ω 0.1μF 6.8μF R 402GΩ −VS−5V +6.8μF 0.1μF −5V−VS + Figure 1. DC-Coupled, G = +2, Bipolar-Supply Figure 2. DC-Coupled, G = −2V/V, Bipolar-Supply Specification and Test Circuit Specification and Test Circuit 11

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 ADC DRIVER gain), wideband inverting summing stages may be implemented using the OPA2694. The circuit in Figure 4 Most modern, high-performance analog-to-digital shows an example inverting summing amplifier, where the converters (ADCs), such as Texas Instruments ADS522x resistor values have been adjusted to maintain both series, require a low-noise, low-distortion driver. The maximum bandwidth and input impedance matching. If OPA2694 combines low-voltage noise (2.1nV/√Hz) with each RF signal is assumed to be driven from a 50Ω source, low harmonic distortion. Figure 3 shows an example of a the NG for this circuit will be (1 + 100Ω/(100Ω/5)) = 6. The wideband, AC-coupled, 12-bit ADC driver. total feedback impedance (from V to the inverting error O current) is the sum of R + (R • NG). where R is the One OPA2694 is used in the circuit of Figure 3 to form a F I I impedance looking into the inverting input from the differential driver for the ADS5220. The OPA2694 offers summing junction (see the Setting Resistor Values to > 150MHz bandwidth at a differential gain of 5V/V, with a Optimize Performance section). Using 100Ω feedback (to 2V output swing. A 2nd-order RLC filter is used in order to PP get a signal gain of –2 from each input to the output pin) limit the noise from the amplifier and provide some requires an additional 30Ω in series with the inverting input attenuation for higher-frequency harmonic distortion. to increase the feedback impedance. With this resistor added to the typical internal R = 30Ω, the total feedback WIDEBAND INVERTING SUMMING AMPLIFIER I impedance is 100Ω + (60Ω • 6) = 460Ω, which is equal to Since the signal bandwidth for a current-feedback op amp the required value to get a maximum bandwidth flat can be controlled independently of the noise gain (NG), frequency response for NG = 6. which is normally the same as the noninverting signal Power−supplydecouplingnotshown. +5V 1/2 C1 R1 L 25Ω OPA2694 V+ 1:2 100Ω 500Ω C R 2 V I 12−Bit 50Ω V 40MSPS CM ADS5220 100Ω 500Ω 0.1μF R 2 Single−to−Differential 1/2 C1 R1 L Gainof10 OPA2694 V− 25Ω −5V Figure 3. Wideband, AC-Coupled, Low-Power ADC Driver +5V 50Ω DIS V1 50Ω V =−(V +V +V +V +V) 1/2 O 1 2 3 4 5 50Ω OPA2694 V RG−58 2 50Ω 50Ω V3 30Ω 100Ω 50Ω 100MHz,−1dBCompression=15dBm V 4 50Ω −5V V 5 Figure 4. 200MHz RF Summing Amplifier 12

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 SAW FILTER BUFFER +V CC One common requirement in an IF strip is to buffer the output of a mixer with enough gain to recover the insertion loss of a narrowband SAW filter. Figure 5 shows one 1/2 possible configuration driving a SAW filter. The 2-Tone, OPA2694 3rd-Order Intermodulation Intercept plot is shown in the R F Typical Characteritics curves. Operating in the inverting mode at a voltage gain of –8V/V, this circuit provides a 50Ω input match using the gain set resistor, has the feedback VI RG R VO F optimized for maximum bandwidth (250MHz in this case), and drives through a 50Ω output resistor into the matching network at the input of the SAW filter. If the SAW filter gives a 12dB insertion loss, a net gain of 0dB to the 50Ω load at 1/2 OPA2694 the output of the SAW (which could be the input impedance of the next IF amplifier or mixer) will be delivered in the passband of the SAW filter. Using the −V OPA2694 in this application will isolate the first mixer from CC the impedance of the SAW filter and provide very low two-tone, 3rd-order spurious levels in the SAW filter Figure 6. Noninverting Differential I/O Amplifier bandwidth. This approach provides for a source termination impedance that is independent of the signal gain. For instance, simple differential filters may be included in the signal path right up to the noninverting inputs without +12V interacting with the gain setting. The differential signal gain for the circuit of Figure 6 is shown in Equation (1): 5kΩ 1000pF 0.1μF 5kΩ OPA1/22694 50Ω MNaettcwhoinrkg PO AD(cid:2)1(cid:3)2(cid:4)RRGF (1) 50Ω SAW The differential gain, however, may be adjusted with 50Ω Filter considerable freedom using just the R resistor. In fact, R Source 1000pF 50Ω 400Ω G G may be a reactive network providing a very isolated PI PPOI =12dB−(SAWLoss) shaping to the differential frequency response. Since the inverting inputs of the OPA2694 are low-impedance closed-loop buffer outputs, the R element does not G interact with the amplifier bandwidth. Wide ranges of resistor values and/or filter elements may be inserted here with minimal amplifier bandwidth interaction. Figure 5. IF Amplifier Driving SAW Filter Various combinations of single-supply or AC-coupled gain can also be delivered using the basic circuit of Figure 6. DIFFERENTIAL INTERFACE APPLICATIONS Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of 1, since an equal Dual op amps are particularly suitable to differential input DC voltage at each inverting node creates no current to differential output applications. Typically, these fall into through R . This circuit does show a common-mode gain G either ADC input interface or line driver applications. Two of 1 from input to output. The source connection should basic approaches to differential I/O are noninverting or either remove this common-mode signal if undesired inverting configurations. Since the output is differential, the (using an input transformer can provide this function), or signal polarity is somewhat meaningless—the the common-mode voltage at the inputs can be used to set noninverting and inverting terminology applies here to the output common-mode bias. If the low common-mode where the input is brought into the OPA2694. Each has its rejection of this circuit is a problem, the output interface advantages and disadvantages. Figure 6 shows a basic may also be used to reject that common-mode. For starting point for noninverting differential I/O applications. instance, most modern differential input ADCs reject 13

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 common-mode signals very well, while a line driver DC-COUPLED SINGLE-TO-DIFFERENTIAL application through a transformer also attenuates the CONVERSION common-mode signal through to the line. The previous differential output circuits were set up to Figure 7 shows a differential I/O stage configured as an receive a differential input as well. A simple way to provide inverting amplifier. In this case, the gain resistors (RG) a DC-coupled single-to-differential conversion using a become part of the input resistance for the source. This dual op amp is shown in Figure 8. Here, the output of the provides a better noise performance than the noninverting first stage is simply inverted by the second to provide an configuration, but does limit the flexibility in setting the inverting version of a single amplifier design. This input impedance separately from the gain. approach works well for lower frequencies, but will start to depart from ideal differential outputs as the propagation delay and distortion of the inverting stage adds +V CC significantly to that present at the noninverting output pin. V CM 1/2 OPA2694 +5V RG RF 1V PP VI RG RF VO 50Ω OPA1/22694 1/2 402Ω OPA2694 VCM 80.6Ω −VCC 402Ω 12VPPDifferential Figure 7. Inverting Differential I/O Amplifier 402Ω The two noninverting inputs provide an easy common-mode control input. This is particularly easy if the 1/2 source is AC-coupled through either blocking caps or a OPA2694 transformer. In either case, the common-mode input voltages on the two noninverting inputs again have a gain of 1 to the output pins, giving particularly easy −5V common-mode control for single-supply operation. Once R is fixed, the input resistors can be adjusted to the F desired gain, but will also be changing the input Figure 8. Single-to-Differential Conversion impedance as well. The high-frequency, common-mode gain for this circuit from input to output is the same as for The circuit of Figure 8 is set up for a single-ended gain of the signal gain. Again, if the source includes an undesired 6 to the output of the first amplifier, then an inverting gain common-mode signal, it can be rejected at the input using of –1 through the second stage to provide a total blocking caps (for low-frequency and DC common-mode) differential gain of 12. or a transformer coupling. 14

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 DIFFERENTIAL ACTIVE FILTER DESIGN-IN TOOLS The OPA2694 can provide a very capable gain block for DEMONSTRATION FIXTURES low-noise active filters. The dual design lends itself very well to differential active filters. Where the filter topology is Two printed circuit boards (PCBs) are available to assist looking for a simple gain function to implement the filter, in the initial evaluation of circuit performance using the the noninverting configuration is preferred to isolate the OPA2694 in either of two possible configurations: inverting filter elements from the gain elements in the design. or noninverting. Both of these are offered free of charge as Figure 9 shows an example of a very low power, 10MHz unpopulated PCBs, delivered with a user’s guide. The 3rd-order Butterworth low-pass, Sallen-Key filter. The summary information for these fixtures is shown in Table 1. example of Figure 9 designs the filter for a differential gain of 1 using the OPA2694. The resistor values have been Table 1. Demonstration Fixtures by Package adjusted slightly to account for the amplifier bandwidth ORDERING LITERATURE effects. PRODUCT PACKAGE NUMBER NUMBER While this circuit is bipolar (using ±5V supplies), it can DEM-OPA-SO-2B easily be adapted to single-supply operation. This is OPA2694ID SO-8 (noninverting) SBOU030 typically done by providing a supply midpoint reference at DEM-OPA-SO-2C the noninverting inputs, and then adding DC blocking caps OPA2694ID SO-8 (inverting) SBOU029 at each input and in series with the amplifier gain resistor, R . This will add two real zeroes in the response, G The demonstration fixtures can be requested at the Texas transforming the circuit into a bandpass. Instruments web site (www.ti.com) through the OPA2694 product folder. 100pF MACROMODELS AND APPLICATIONS SUPPORT +5V 50Ω 232Ω 20Ω Computer simulation of circuit performance using SPICE 1/2 is often useful when analyzing the performance of analog OPA2694 circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and 800Ω 357Ω inductance can have a major effect on circuit performance. A SPICE model for the OPA2694 is available through the VI 75pF 400Ω 800Ω 357Ω 22pF VO TI web site (www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dφ 1/2 characteristics. These models do not attempt to 50Ω 232Ω 20Ω OPA2694 distinguish between package types in their small-signal AC performance. 100pF −5V Figure 9. Low-Power, Differential I/O, 3rd-Order Butterworth Active Filter 15

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 OPERATING SUGGESTIONS A current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error SETTING RESISTOR VALUES TO voltage for a voltage-feedback op amp) and passes this on OPTIMIZE BANDWIDTH to the output through an internal frequency dependent transimpedance gain. The Typical Characteristics show A current-feedback op amp like the OPA2694 can hold an this open-loop transimpedance response. This is almost constant bandwidth over signal gain settings with analogous to the open-loop voltage gain curve for a the proper adjustment of the external resistor values. This voltage-feedback op amp. Developing the transfer is shown in the Typical Characteristic curves; the function for the circuit of Figure 10 gives Equation (2): small-signal bandwidth decreases only slightly with (cid:5) (cid:6) increasing gain. Those curves also show that the feedback (cid:2) 1(cid:3)RF resistor has been changed for each gain setting. The VO(cid:2) (cid:5)RG (cid:6)(cid:2) (cid:2)NG resistor values on the inverting side of the circuit for a V R (cid:3)R NG current-feedback op amp can be treated as frequency I RF(cid:3)RI 1(cid:3)RRF 1(cid:3) F Z(SI) response compensation elements while their ratios set 1(cid:3) G the signal gain. Figure 10 shows the small-signal Z(S) (2) frequency response analysis circuit for the OPA2694. where: (cid:5) (cid:6) R NG (cid:2) 1(cid:3) F R G V I This is written in a loop-gain analysis format, where the α errors arising from a noninfinite open-loop gain are shown in the denominator. If Z were infinite over all frequencies, V (S) O the denominator of Equation (2) would reduce to 1 and the RI ideal desired signal gain shown in the numerator would be Z i (S) ERR achieved. The fraction in the denominator of Equation (2) i determines the frequency response. Equation (3) shows ERR R F this as the loop-gain equation: Z RG (S) (cid:2)Loop Gain RF(cid:3)RING (3) If 20 × log(R + NG × R) were drawn on top of the F I open-loop transimpedance plot, the difference between Figure 10. Recommended Feedback Resistor the two would be the loop gain at a given frequency. Versus Noise Gain Eventually, Z rolls off to equal the denominator of (S) Equation (3), at which point the loop gain reduces to 1 (and The key elements of this current-feedback op amp model the curves intersect). This point of equality is where the are: amplifier closed-loop frequency response given by α → Buffer gain from the noninverting input to the Equation (2) starts to roll off, and is exactly analogous to inverting input the frequency at which the noise gain equals the open-loop voltage gain for a voltage-feedback op amp. The R → Buffer output impedance I difference here is that the total impedance in the i → Feedback error current signal denominator of Equation (3) may be controlled somewhat ERR separately from the desired signal gain (or NG). Z → Frequency dependent open-loop transimpe- (s) dance gain from i to V The OPA2694 is internally compensated to give a ERR O maximally flat frequency response for R = 402Ω at F The buffer gain is typically very close to 1.00 and is NG = 2 on ±5V supplies. Evaluating the denominator of normally neglected from signal gain considerations. It will, Equation (3) (which is the feedback transimpedance) however, set the CMRR for a single op amp differential gives an optimal target of 462Ω. As the signal gain amplifier configuration. For a buffer gain α < 1.0, the changes, the contribution of the NG × R term in the CMRR = –20 × log (1– α) dB. I feedback transimpedance will change, but the total can be RI, the buffer output impedance, is a critical portion of the held constant by adjusting RF. Equation (4) gives an bandwidth control equation. RI for the OPA2694 is typically approximate equation for optimum RF over signal gain: about 30Ω. RF(cid:2)462(cid:3)(cid:7)NG(cid:8)RI (4) 16

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 As the desired signal gain increases, this equation will The specifications described above, though familiar in the eventually predict a negative R . A somewhat subjective industry, consider voltage and current limits separately. In F limit to this adjustment can also be set by holding R to a many applications, it is the voltage × current, or V−I G minimum value of 20Ω. Lower values will load both the product, which is more relevant to circuit operation. Refer buffer stage at the input and the output stage, if R gets too to the Output Voltage and Current Limitations plot in the F low, actually decreasing the bandwidth. Figure 11 shows Typical Characteristics. The X and Y axes of this graph the recommended R versus NG for ±5V operation. The show the zero-voltage output current limit and the F values for R versus gain shown here are approximately zero-current output voltage limit, respectively. The four F equal to the values used to generate the Typical quadrants give a more detailed view of the OPA2694 Characteristics. They differ in that the optimized values output drive capabilities, noting that the graph is bounded used in the Typical Characteristics are also correcting for by a Safe Operating Area of 1W maximum internal power board parasitics not considered in the simplified analysis dissipation. Superimposing resistor load lines onto the plot leading to Equation (3). The values shown in Figure 11 shows that the OPA2694 can drive ±2.5V into 25Ω or give a good starting point for design where bandwidth ±3.5V into 50Ω without exceeding the output capabilities optimization is desired. or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.4V output swing capability, as shown in the Electrical Charateristics. 450 The minimum specified output voltage and current over-temperature are set by worst-case simulations at the 400 ) cold temperature extreme. Only at cold startup will the Ω or( 350 output current and voltage decrease to the numbers st shown in the Electrical Characteristic tables. As the output si Re 300 transistors deliver power, the junction temperatures will ack increase, decreasing both VBE (increasing the available db 250 output voltage swing) and increasing the current gains e e F (increasing the available output current). In steady-state 200 operation, the available output voltage and current will always be greater than that shown in the over-temperature 150 specifications, since the output stage junction 0 5 10 15 20 NoiseGain temperatures will be higher than the minimum specified operating ambient. Figure 11. Feedback Resistor vs Noise Gain DRIVING CAPACITIVE LOADS The total impedance going into the inverting input may be used to adjust the closed-loop signal bandwidth. Inserting One of the most demanding and yet very common load a series resistor between the inverting input and the conditions for an op amp is capacitive loading. Often, the summing junction will increase the feedback impedance capacitive load is the input of an ADC—including (denominator of Equation (2)), decreasing the bandwidth. additional external capacitance that may be This approach to bandwidth control is used for the recommended to improve ADC linearity. A high-speed, inverting summing circuit of Figure 4. The internal buffer high open-loop gain amplifier like the OPA2694 can be output impedance for the OPA2694 is slightly influenced very susceptible to decreased stability and closed-loop by the source impedance looking out of the noninverting response peaking when a capacitive load is placed directly input terminal. High source resistors will have the effect of on the output pin. When the amplifier open-loop output increasing RI, decreasing the bandwidth. resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem OUTPUT CURRENT AND VOLTAGE have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, The OPA2694 provides output voltage and current and/or distortion, the simplest and most effective solution capabilities that are not usually found in wideband is to isolate the capacitive load from the feedback loop by amplifiers. Under no-load conditions at 25°C, the output inserting a series isolation resistor between the amplifier voltage typically swings closer than 1.2V to either supply output and the capacitive load. This does not eliminate the rail; the +25°C swing limit is within 1.2V of either rail. Into pole from the loop response, but rather shifts it and adds a 15Ω load (the minimum tested load), it is tested to deliver more than ±55mA. 17

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 a zero at a higher frequency. The additional zero acts to significantly lower than earlier solutions, while the input cancel the phase lag from the capacitive load pole, thus voltage noise (2.1nV/√Hz) is lower than most unity-gain increasing the phase margin and improving stability. stable, wideband, voltage-feedback op amps. This low input voltage noise was achieved at the price of higher The Typical Characteristics show the recommended R vs S noninverting input current noise (22pA/√Hz). As long as Capacitive Load and the resulting frequency response at the AC source impedance looking out of the noninverting the load. Parasitic capacitive loads greater than 2pF can node is less than 100Ω, this current noise will not begin to degrade the performance of the OPA2694. Long contribute significantly to the total output noise. The op PCB traces, unmatched cables, and connections to amp input voltage noise and the two input current noise multiple devices can easily cause this value to be terms combine to give low output noise under a wide exceeded. Always consider this effect carefully, and add variety of operating conditions. Figure 12 shows the op the recommended series resistor as close as possible to amp noise analysis model with all the noise terms the OPA2694 output pin (see the Board Layout Guidelines included. In this model, all noise terms are taken to be section). noise voltage or current density terms in either nV/√Hz or pA/√Hz. DISTORTION PERFORMANCE E The OPA2694 provides good distortion performance into NI a 100Ω load on ±5V supplies. Generally, until the 1/2 fundamental signal reaches very high frequency or power OPA2694 EO levels, the 2nd-harmonic will dominate the distortion with RS I BN a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance E improves distortion directly. Remember that the total load RS R includes the feedback network—in the noninverting √4kTRS F configuration (see Figure 1), this is the sum of R + R , F G √4kTR while in the inverting configuration it is just RF. Also, RG IBI F providing an additional supply decoupling capacitor 4kT 4kT=1.6×10−20J (0.1μF) between the supply pins (for bipolar operation) RG at290K improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing Figure 12. Op Amp Noise Analysis Model increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a The total output spot noise voltage can be computed as the little less than the expected 2x rate, while the 3rd-harmonic square root of the sum of all squared output noise voltage increases at a little less than the expected 3x rate. Where contributors. Equation (5) shows the general form for the the test power doubles, the 2nd-harmonic increases by output noise voltage using the terms shown in Figure 12. less than the expected 6dB, while the 3rd-harmonic (cid:9) (cid:5) (cid:6) increases by less than the expected 12dB. This also E (cid:2) E 2(cid:3)(cid:5)I R (cid:6)2(cid:3)4kTR NG2(cid:3)(cid:5)I R (cid:6)2(cid:3)4kTR NG shows up in the 2-tone, 3rd-order intermodulation spurious O NI BN S S BI F F (5) (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power Dividing this expression by the noise gain (NG = reaches very high levels. As the Typical Characteristics (1 + R /R )) will give the equivalent input-referred spot F G show, the spurious intermodulation powers do not noise voltage at the noninverting input, as shown in increase as predicted by a traditional intercept model. As Equation 6. the fundamental power level increases, the dynamic range (cid:9) does not decrease significantly. (cid:5) (cid:6) 2 E (cid:2) E 2(cid:3)(cid:5)I R (cid:6)2(cid:3)4kTR (cid:3) IBIRF (cid:3)4kTRF N NI BN S S NG NG (6) NOISE PERFORMANCE Evaluating these two equations for the OPA2694 circuit Wideband, current-feedback op amps generally have a and component values (see Figure 1) gives a total output higher output noise than comparable voltage-feedback op spot noise voltage of 11.2nV/√Hz and a total equivalent amps. The OPA2694 offers an excellent balance between input spot noise voltage of 5.6nV/√Hz. This total voltage and current noise terms to achieve low output input-referred spot noise voltage is higher than the noise. The inverting current noise (24pA/√Hz) is 2.1nV/√Hz specification for the op amp voltage noise 18

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. If the feedback resistor is reduced in high-gain configurations +5V Power−supply (as suggested previously), the total input-referred voltage decouplingnotshown. DIS noise given by Equation (5) will approach just the VI 1/2 2.1nV/√Hz of the op amp itself. For example, going to a OPA2694 VO gain of +10 using RF = 178Ω will give a total input-referred 1.8kΩ noise of 2.36nV/√Hz. +5V 2.86kΩ −5V 180Ω OPA237 DC ACCURACY AND OFFSET CONTROL 20Ω A current-feedback op amp like the OPA2694 provides −5V 18kΩ exceptional bandwidth in high gains, giving fast pulse settling, but only moderate DC accuracy. The Electrical 2kΩ Characteristics show an input offset voltage comparable to high-speed, voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage-feedback Figure 13. Wideband, DC-Connected Composite op amps, they do not generally reduce the output DC offset Circuit for wideband, current-feedback op amps. Since the two input bias currents are unrelated in both magnitude and This DC-coupled circuit provides very high signal polarity, matching the source impedance looking out of bandwidth using the OPA2694. At lower frequencies, the each input to reduce their error contribution to the output output voltage is attenuated by the signal gain and is ineffective. Evaluating the configuration of Figure 1, compared to the original input voltage at the inputs of the using worst-case +25°C input offset voltage and the two OPA237 (this is a low-cost, precision voltage-feedback op input bias currents, gives a worst-case output offset range amp with 1.5MHz gain bandwidth product). If these two do equal to: not agree (due to DC offsets introduced by the OPA2694), ± (NG × V ) ± (I × R /2 × NG) ± (I × R ) the OPA237 sums in a correction current through the OS BN S BI F 2.86kΩ inverting summing path. Several design where NG = noninverting signal gain considerations will allow this circuit to be optimized. First, = ± (2 × 3.2mV) ± (22μA × 25Ω × 2) ± (402Ω × 20μA) the feedback to the OPA237 noninverting input must be precisely matched to the high-speed signal gain. Making = ±6.4mV + 1.1mV ± 8.04mV = ±15.54mV the 2kΩ resistor to ground an adjustable resistor would allow the low- and high-frequency gains to be precisely A fine-scale, output offset null, or DC operating point matched. Second, the crossover frequency region where adjustment, is sometimes required. Numerous techniques the OPA237 passes control to the OPA2694 must occur are available for introducing DC offset control into an op with exceptional phase linearity. These two issues reduce amp circuit. Most simple adjustment techniques do not to designing for pole/zero cancellation in the overall correct for temperature drift. It is possible to combine a transfer function. Using the 2.86kΩ resistor will nominally lower speed, precision op amp with the OPA2694 to get satisfy this requirement for the circuit in Figure 13. Perfect the DC accuracy of the precision op amp along with the cancellation over process and temperature is not possible. signal bandwidth of the OPA2694. Figure 13 shows a However, this initial resistor setting and precise gain noninverting G = +10 circuit that holds an output offset matching will minimize long-term pulse settling tails. voltage less than ±7.5mV over-temperature with > 150MHz signal bandwidth. 19

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 THERMAL ANALYSIS capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around Due to the high output power capability of the OPA2694, those pins. Otherwise, ground and power planes should heatsinking or forced airflow may be required under be unbroken elsewhere on the board. extreme operating conditions. Maximum desired junction b) Minimize the distance (< 0.25”) from the power-supply temperature will set the maximum allowed internal power pins to high-frequency 0.1μF decoupling capacitors. At the dissipation, as described below. In no case should the device pins, the ground and power plane layout should not maximum junction temperature be allowed to exceed 150°C. be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between Operating junction temperature (TJ) is given by TA + PD × θJA. the pins and the decoupling capacitors. The power-supply The total internal power dissipation (PD) is the sum of connections (on pins 4 and 7) should always be decoupled quiescent power (PDQ) and additional power dissipated in with these capacitors. An optional supply decoupling the output stage (PDL) to deliver load power. Quiescent capacitor across the two power supplies (for bipolar power is simply the specified no-load supply current times operation) will improve 2nd-harmonic distortion the total supply voltage across the part. PDL will depend on performance. Larger (2.2μF to 6.8μF) decoupling the required output signal and load but would, for a grounded capacitors, effective at lower frequencies, should also be resistive load, be at a maximum when the output is fixed at used on the main supply pins. These may be placed a voltage equal to 1/2 either supply voltage (for equal bipolar somewhat farther from the device and may be shared supplies). Under this condition PDL = VS2/(4 × RL) where RL among several devices in the same area of the PCB. includes feedback network loading. c) Careful selection and placement of external Note that it is the power in the output stage and not in the components will preserve the high-frequency load that determines internal power dissipation. performance of the OPA2694. Resistors should be a very low reactance type. Surface-mount resistors work best As a worst-case example, compute the maximum T using J and allow a tighter overall layout. Metal-film and carbon an OPA2694ID (SO-8 package) in the circuit of Figure 1, composition, axially-leaded resistors can also provide with both amplifiers operating at the maximum specified ambient temperature of +85°C and driving a grounded good high-frequency performance. Again, keep their leads 20Ω load to +2.5V DC: and PC-board trace length as short as possible. Never use wirewound type resistors in a high-frequency application. PD = 10V × 12.7mA + 2 × [52/(4 × (20Ω || 804Ω))] = 768mW Since the output pin and inverting input pin are the most Maximum T = +85°C + (0.45W × (125°C/W)) = 180°C sensitive to parasitic capacitance, always position the J feedback and series output resistor, if any, as close as This absolute worst-case condition exceeds the specified possible to the output pin. Other network components, maximum junction temperature. Remember, this is a such as noninverting input termination resistors, should worst-case internal power dissipation—use your actual also be placed close to the package. Where double-side signal and load to compute PDL. The highest possible component mounting is allowed, place the feedback internal dissipation will occur if the load requires current to resistor directly under the package on the other side of the be forced into the output for positive output voltages or board between the output and inverting input pins. The sourced from the output for negative output voltages. This frequency response is primarily determined by the puts a high current through a large internal voltage drop in feedback resistor value, as described previously. the output transistors. The Output Voltage and Current Increasing its value will reduce the bandwidth, while Limitations plot shown in the Typical Characteristics decreasing it will give a more peaked frequency response. includes a boundary for 1W maximum internal power The 402Ω feedback resistor used in the Electrical dissipation under these conditions. Characteristic tables at a gain of +2 on ±5V supplies is a good starting point for design. Note that a 430Ω feedback resistor, rather than a direct short, is recommended for the BOARD LAYOUT GUIDELINES unity-gain follower application. A current-feedback op amp requires a feedback resistor even in the unity-gain follower Achieving optimum performance with a high-frequency configuration to control stability. amplifier like the OPA2694 requires careful attention to board layout parasitics and external component types. d) Connections to other wideband devices on the board Recommendations that will optimize performance include: may be made with short, direct traces or through onboard transmission lines. For short connections, consider the a) Minimize parasitic capacitance to any AC ground for trace and the input to the next device as a lumped all of the signal I/O pins. Parasitic capacitance on the capacitive load. Relatively wide traces (50mils to 100mils) output and inverting input pins can cause instability: on the should be used, preferably with ground and power planes noninverting input, it can react with the source impedance opened up around them. Estimate the total capacitive load to cause unintentional bandlimiting. To reduce unwanted 20

OPA2694 www.ti.com SBOS320D − SEPTEMBER 2004 − REVISED APRIL 2013 and set R from the plot of Recommended R vs INPUT AND ESD PROTECTION S S Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an R , since the OPA2694 is nominally The OPA2694 is built using a very high speed S compensated to operate with a 2pF parasitic load. If a long complementary bipolar process. The internal junction trace is required, and the 6dB signal loss intrinsic to a breakdown voltages are relatively low for these very small doubly-terminated transmission line is acceptable, geometry devices. These breakdowns are reflected in the implement a matched impedance transmission line using Absolute Maximum Ratings table. All device pins have microstrip or stripline techniques (consult an ECL design limited ESD protection using internal diodes to the power handbook for microstrip and stripline layout techniques). A supplies, as shown in Figure 14. 50Ω environment is normally not necessary onboard, and These diodes provide moderate protection to input in fact, a higher impedance environment will improve overdrive voltages above the supplies as well. The distortion, as shown in the Distortion versus Load plots. protection diodes can typically support 30mA continuous With a characteristic board trace impedance defined current. Where higher currents are possible (for example, based on board material and trace dimensions, a matching in systems with ±15V supply parts driving into the series resistor into the trace from the output of the OPA2694), current-limiting series resistors should be OPA2694 is used as well as a terminating shunt resistor at added into the two inputs. Keep these resistor values as the input of the destination device. Remember also that the low as possible, since high values degrade both noise terminating impedance will be the parallel combination of performance and frequency response. the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2694 allows +VCC multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated External Internal Pin Circuitry transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor −VCC value as shown in the plot of Recommended R vs S Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of Figure 14. Internal ESD Protection the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA2694 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2694 directly onto the board. 21

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA2694ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2694 OPA2694IDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2694 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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