OPA337, OPA2337 OPA338, OPA2338 SBOS077B − JUNE 1997 − REVISED MARCH 2005 MicroSIZE, Single-Supply CMOS OPERATIONAL AMPLIFIERS (cid:1) MicroAmplifier Series FEATURES DESCRIPTION (cid:1) MicroSIZE PACKAGES: The OPA337 and OPA338 series rail-to-rail output CMOS SOT23-5, SOT23-8 operational amplifiers are designed for low cost and miniature applications. Packaged in the SOT23-8, the (cid:1) SINGLE-SUPPLY OPERATION OPA2337EA and OPA2338EA are Texas Instruments’ (cid:1) RAIL-TO-RAIL OUTPUT SWING smallest dual op amps. At 1/4 the size of a conventional (cid:1) SO-8 surface-mount, they are ideal for space-sensitive FET-INPUT: I = 10pA max B applications. (cid:1) HIGH SPEED: Utilizing advanced CMOS technology, the OPA337 and OPA337: 3MHz, 1.2V/µs (G = 1) OPA338 op amps provide low bias current, high-speed OPA338: 12.5MHz, 4.6V/µs (G = 5) operation, high open-loop gain, and rail-to-rail output (cid:1) OPERATION FROM 2.5V to 5.5V swing. They operate on a single supply with operation as (cid:1) low as 2.5V while drawing only 525µA quiescent current. HIGH OPEN-LOOP GAIN: 120dB In addition, the input common-mode voltage range (cid:1) LOW QUIESCENT CURRENT: 525µA/amp includes ground—ideal for single-supply operation. (cid:1) SINGLE AND DUAL VERSIONS The OPA337 series is unity-gain stable. The OPA338 series is optimized for gains greater than or equal to 5. They are easy-to-use and free from phase inversion and overload APPLICATIONS problems found in some other op amps. Excellent (cid:1) BATTERY-POWERED INSTRUMENTS performance is maintained as the amplifiers swing to their specified limits. The dual versions feature completely (cid:1) PHOTODIODE PRE-AMPS independent circuitry for lowest crosstalk and freedom from (cid:1) MEDICAL INSTRUMENTS interaction, even when overdriven or overloaded. (cid:1) TEST EQUIPMENT G = 1 STABLE G ≥ 5 STABLE (cid:1) AUDIO SYSTEMS SINGLE DUAL SINGLE DUAL (cid:1) DRIVING ADCs PACKAGE OPA337 OPA2337 OPA338 OPA2338 (cid:1) SOT23-5 (cid:2) (cid:2) CONSUMER PRODUCTS SOT23-8 (cid:2) (cid:2) SPICE model available at www.ti.com. MSOP-8 (cid:2) SO-8 (cid:2) (cid:2) (cid:2) (cid:2) DIP-8 (cid:2) (cid:2) OPA337,OPA338 OPA337,OPA338 OPA2337,OPA2338 NC 1 8 NC Out 1 5 V+ OutA 1 8 V+ −In 2 7 V+ V− 2 −InA 2 A 7 OutB +In 3 6 Output +In 3 4 −In +InA 3 B 6 −InB V− 4 5 NC SOT23−5 V− 4 5 +InB DIP−8(1),SO−8,MSOP−8(1) NC=NoConnection NOTE:(1)DIPANDMSOP−8versionsforOPA337,OPA2337only. DIP−8(1),SO−8,SOT23−8 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9) (cid:4)(cid:10)(cid:7)(cid:10) (cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12) (cid:11)(cid:19) (cid:20)(cid:21)(cid:15)(cid:15)(cid:22)(cid:12)(cid:18) (cid:17)(cid:19) (cid:14)(cid:13) (cid:23)(cid:21)(cid:24)(cid:25)(cid:11)(cid:20)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12) (cid:26)(cid:17)(cid:18)(cid:22)(cid:27) (cid:1)(cid:15)(cid:14)(cid:26)(cid:21)(cid:20)(cid:18)(cid:19) Copyright  1997-2005, Texas Instruments Incorporated (cid:20)(cid:14)(cid:12)(cid:13)(cid:14)(cid:15)(cid:16) (cid:18)(cid:14) (cid:19)(cid:23)(cid:22)(cid:20)(cid:11)(cid:13)(cid:11)(cid:20)(cid:17)(cid:18)(cid:11)(cid:14)(cid:12)(cid:19) (cid:23)(cid:22)(cid:15) (cid:18)(cid:28)(cid:22) (cid:18)(cid:22)(cid:15)(cid:16)(cid:19) (cid:14)(cid:13) (cid:7)(cid:22)(cid:29)(cid:17)(cid:19) (cid:8)(cid:12)(cid:19)(cid:18)(cid:15)(cid:21)(cid:16)(cid:22)(cid:12)(cid:18)(cid:19) (cid:19)(cid:18)(cid:17)(cid:12)(cid:26)(cid:17)(cid:15)(cid:26) (cid:30)(cid:17)(cid:15)(cid:15)(cid:17)(cid:12)(cid:18)(cid:31)(cid:27) (cid:1)(cid:15)(cid:14)(cid:26)(cid:21)(cid:20)(cid:18)(cid:11)(cid:14)(cid:12) (cid:23)(cid:15)(cid:14)(cid:20)(cid:22)(cid:19)(cid:19)(cid:11)(cid:12)! (cid:26)(cid:14)(cid:22)(cid:19) (cid:12)(cid:14)(cid:18) (cid:12)(cid:22)(cid:20)(cid:22)(cid:19)(cid:19)(cid:17)(cid:15)(cid:11)(cid:25)(cid:31) (cid:11)(cid:12)(cid:20)(cid:25)(cid:21)(cid:26)(cid:22) (cid:18)(cid:22)(cid:19)(cid:18)(cid:11)(cid:12)! (cid:14)(cid:13) (cid:17)(cid:25)(cid:25) (cid:23)(cid:17)(cid:15)(cid:17)(cid:16)(cid:22)(cid:18)(cid:22)(cid:15)(cid:19)(cid:27) www.ti.com

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 ABSOLUTE MAXIMUM RATINGS(1) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V handled with appropriate precautions. Failure to observe Input Voltage(2). . . . . . . . . . . . . . . . . . . . (V−) − 0.5V to (V+) + 0.5V proper handling and installation procedures can cause damage. Input Current(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD damage can range from subtle performance degradation to Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C complete device failure. Precision integrated circuits may be more Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2)Input signal voltage is limited by internal diodes connected to power supplies. See text. (3)Short-circuit to ground, one amplifier per package. ORDERING INFORMATION(1) SPECIFIED PACKAGE PACKAGE ORDERING TRANSPORT PRODUCT DESCRIPTION PACKAGE-LEAD TEMPERATURE DESIGNATOR MARKING NUMBER MEDIA, QUANTITY RANGE OPA337 Series OPA337NA/250 Tape and Reel, 250 SSOOTT2233--55 DDBBVV CC3377 OPA337NA/3K Tape and Reel, 3000 OPA337EA/250 Tape and Reel, 250 SSiinnggllee,, MMSSOOPP--88 DDGGKK GG3377 OOPPAA333377 −−4400°CC ttoo ++8855°CC OPA337EA/2K5 Tape and Reel, 2500 GG == 11 SSttaabbllee DIP-8 P OPA337PA OPA337PA Rails SSOO--88 OPA337UA Rails DD OOPPAA333377UUAA Surface-Mount OPA337UA/2K5 Tape and Reel, 2500 OPA2337EA/250 Tape and Reel, 250 SSOOTT2233--88 DDCCNN AA77 OPA2337EA/3K Tape and Reel, 3000 DDuuaall,, OOPPAA22333377 DIP-8 P −−4400°CC ttoo ++8855°CC OPA2337PA OPA2337PA Rails GG == 11 SSttaabbllee SSOO--88 OPA2337UA Rails DD OOPPAA22333377UUAA Surface-Mount OPA2337UA/2K5 Tape and Reel, 2500 OPA338 Series OPA338NA/250 Tape and Reel, 250 SSOOTT2233--55 DDBBVV AA3388 SSiinnggllee,, OPA338NA/3K Tape and Reel, 3000 OOPPAA333388 G ≥ 5 Stable SSOO--88 −−4400°°CC ttoo ++8855°°CC OPA338UA Rails DD OOPPAA333388UUAA Surface-Mount OPA338UA/2K5 Tape and Reel, 2500 OPA2338EA/250 Tape and Reel, 250 SSOOTT2233--88 DDCCNN AA88 DDuuaall,, OPA2338EA/3K Tape and Reel, 3000 OOPPAA22333388 G ≥ 5 Stable SSOO--88 −−4400°°CC ttoo ++8855°°CC OPA2338UA Rails DD OOPPAA22333388UUAA Surface-Mount OPA2338UA/2K5 Tape and Reel, 2500 (1)For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. 2

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 ELECTRICAL CHARACTERISTICS: V = 2.7V to 5.5V S Boldface limits apply over the specified temperature range, −40(cid:1)C to +85(cid:1)C, V = 5V. S At TA = +25°C and RL = 25kΩ connected to VS/2, unless otherwise noted. OPA337, OPA2337, OPA338, OPA2338 PARAMETER CONDITION MIN TYP(1) MAX UNIT OFFSET VOLTAGE Input Offset Voltage VOS ±0.5 ±3 mV TA = −40°C to +85°C ±3.5 mV vs Temperature dVOS/dT ±2 µV/°C vs Power-Supply Rejection Ratio PSRR VS = 2.7V to 5.5V 25 125 µV/V TA = −40°C to +85°C VS = 2.7V to 5.5V 125 µV/V Channel Separation (dual versions) dc 0.3 µV/V INPUT BIAS CURRENT Input Bias Current IB ±0.2 ±10 pA TA = −40°C to +85°C See Typical Curve Input Offset Current IOS ±0.2 ±10 pA NOISE Input Voltage Noise, f = 0.1Hz to 10Hz 6 µVPP Input Voltage Noise Density, f = 1kHz en 26 nV/√Hz Current Noise Density, f = 1kHz in 0.6 fA/√Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range VCM TA = −40°C to +85°C −0.2 (V+) − 1.2 V Common-Mode Rejection Ratio CMRR −0.2V < VCM < (V+) − 1.2V 74 90 dB TA = −40°C to +85°C −0.2V < VCM < (V+) − 1.2V 74 dB INPUT IMPEDANCE Differential 1013 2 Ω  pF Common-Mode 1013 4 Ω  pF OPEN-LOOP GAIN Open-Loop Voltage Gain AOL RL = 25kΩ, 125mV < VO < (V+) − 125mV 100 120 dB TA = −40°C to +85°C RL = 25kΩ, 125mV < VO < (V+) − 125mV 100 dB RL = 5kΩ, 500mV < VO < (V+) − 500mV 100 114 dB TA = −40°C to +85°C RL = 5kΩ, 500mV < VO < (V+) − 500mV 100 dB OPA337 FREQUENCY RESPONSE Gain-Bandwidth Product GBW VS = 5V, G = 1 3 MHz Slew Rate SR VS = 5V, G = 1 1.2 V/µs Settling TIme: 0.1% VS = 5V, 2V Step, CL = 100pF, G = 1 2 µs 0.01% VS = 5V, 2V Step, CL = 100pF, G = 1 2.5 µs Overload Recovery Time VIN × G = VS 2 µs Total Harmonic Distortion + Noise THD+N VS = 5V, VO = 3VPP, G = 1, f = 1kHz 0.001 % OPA338 FREQUENCY RESPONSE Gain-Bandwidth Product GBW VS = 5V, G = 5 12.5 MHz Slew Rate SR VS = 5V, G = 5 4.6 V/µs Settling TIme: 0.1% VS = 5V, 2V Step, CL = 100pF, G = 5 1.4 µs 0.01% VS = 5V, 2V Step, CL = 100pF, G = 5 1.9 µs Overload Recovery Time VIN × G = VS 0.5 µs Total Harmonic Distortion + Noise THD+N VS = 5V, VO = 3VPP, G = 5, f = 1kHz 0.0035 % (1)VS = 5V. (2)Output voltage swings are measured between the output and negative and positive power-supply rails. 3

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 ELECTRICAL CHARACTERISTICS: V = 2.7V to 5.5V (continued) S Boldface limits apply over the specified temperature range, −40(cid:1)C to +85(cid:1)C, V = 5V. S At TA = +25°C and RL = 25kΩ connected to VS/2, unless otherwise noted. OPA337, OPA2337, OPA338, OPA2338 PARAMETER CONDITION MIN TYP(1) MAX UNIT OUTPUT Voltage Output Swing from Rail(2) RL = 25kΩ, AOL ≥ 100dB 40 125 mV TA = −40°C to +85°C RL = 25kΩ, AOL ≥ 100dB 125 mV RL = 5kΩ, AOL ≥ 100dB 150 500 mV TA = −40°C to +85°C RL = 5kΩ, AOL ≥ 100dB 500 mV Short-Circuit Current ±9 mA Capacitive Load Drive See Typical Curve POWER SUPPLY Specified Voltage Range VS TA = −40°C to +85°C 2.7 5.5 V Minimum Operating Voltage 2.5 V Quiescent Current (per amplifier) IQ IO = 0 0.525 1 mA TA = −40°C to +85°C IO = 0 1.2 mA TEMPERATURE RANGE Specified Range −40 +85 °C Operating Range −55 +125 °C Storage Range −55 +125 °C Thermal Resistance (cid:1)JA SOT23-5 Surface-Mount 200 °C/W SOT23-8 Surface-Mount 200 °C/W MSOP-8 150 °C/W SO-8 Surface-Mount 150 °C/W DIP-8 100 °C/W (1)VS = 5V. (2)Output voltage swings are measured between the output and negative and positive power-supply rails. 4

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted. POWER−SUPPLYREJECTIONRATIOAND OPEN−LOOPGAIN/PHASEvsFREQUENCY COMMON−MODEREJECTIONRATIOvsFREQUENCY 160 0 100 140 OPA337 90 +PSRR OPA338 dB) 120 −45 B) 80 −PSRR Gain( 10800 φ −90 (cid:3)() RR(d 7600 Open−Loop 642000 G −135 Phase PSRR,CM 543000 CMRR 0 −180 20 −20 10 1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M Frequency(Hz) Frequency(Hz) INPUTVOLTAGEANDCURRENTNOISE CHANNELSEPARATIONvsFREQUENCY SPECTRALDENSITYvsFREQUENCY 140 1k 1k 130 VoltageNoise B) √Noise(nVHz) 10100 11000 √Noise(fAHz) Separation(d 112100 Voltage 1 1 Current hannel 100 DualVersions C CurrentNoise 90 0.1 0.1 80 1 10 100 1k 10k 100k 1M 100 1k 10k 100k 1M Frequency(Hz) Frequency(Hz) INPUTBIASCURRENT INPUTBIASCURRENTvsTEMPERATURE vsINPUTCOMMON−MODEVOLTAGE 100 0.5 0.4 A) 10 A) p p Current( 1 Current( 00..32 Bias Bias nput 0.1 put 0.1 I n I 0 0.01 −75 −50 −25 0 25 50 75 100 125 −0.1 −1 0 1 2 3 4 5 Temperature((cid:3)C) Common−ModeVoltage(V) 5

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted. QUIESCENTCURRENTANDSHORT−CIRCUITCURRENT A ,CMRR,PSRRvsTEMPERATURE OL vsTEMPERATURE 140 130 600 12 130 120 550 IQ 11 A,CMRR(dB)OL 111210000 PSAROLR 11910000 PSRR(dB) µuiescentCurrent(A) 544050000 +ISC−ISC 1980 ort−CircuitCurrent(mA) 90 80 Q Sh 350 7 CMRR 80 70 300 6 −75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125 Temperature((cid:3)C) Temperature((cid:3)C) QUIESCENTANDSHORT−CIRCUITCURRENT MAXIMUMOUTPUTVOLTAGEvsFREQUENCY vsSUPPLYVOLTAGE 6 700 ±12 Maximumoutput 5 voltagewithoutslew µnt(A) 665000 ±±180 ent(mA) e(V)PP 4 rate−induceddistortion. Curre 550 +ISC ±6 Curr oltag 3 OPA338 Quiescent 500 −ISC IQ ±4 hort−Circuit OutputV 2 OPA337 450 ±2 S 1 400 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 10k 100k 1M 10M 100M SupplyVoltage(V) Frequency(Hz) TOTALHARMONICDISTORTION+NOISE OUTPUTVOLTAGESWINGvsOUTPUTCURRENT vsFREQUENCY 0.1 2.5 V =±2.5V S 2.0 R TiedtoGround L 1.5 Sourcing −55(cid:3)C V) 1.0 0.01 G=+10,R =5kΩ,25kΩ ( %) L ge 0.5 N( G=+5,RL=5kΩ,25kΩ olta 0 25(cid:3)C 125(cid:3)C THD+ 0.001 G=+1 RL=5kΩ RL=25kΩ OutputV −−01..50 −55(cid:3)C −1.5 Sinking OPA337 −2.0 0.0001 OPA338 VO=3VPP −2.5 20 100 1k 10k 20k 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 Frequency(Hz) OutputCurrent(mA) 6

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted. OFFSETVOLTAGE OFFSETVOLTAGEDRIFT PRODUCTIONDISTRIBUTION PRODUCTIONDISTRIBUTION 25 30 Typicaldistribution Typicaldistribution ofpackagedunits. ofpackagedunits. 25 20 %) %) ( ( mplifiers 15 mplifiers 2105 A A of 10 of nt nt 10 e e Perc 5 Perc 5 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 −3. −2. −2. −1. −1. −0. 0. 1. 1. 2. 2. 3. OffsetVoltageDrift(µV/(cid:3)C) OffsetVoltage(mV) SMALL−SIGNALOVERSHOOTvsLOADCAPACITANCE SETTLINGTIMEvsCLOSED−LOOPGAIN 60 100 50 OPA338 0.01% (G=±5) OPA337 µs) %) 40 (G=±1) ( ( me oot 30 Ti 10 OPA338 sh ettling OPA337 Over 20 (OGP=A±31307) S 10 OPA338 (G=±50) 0.1% 0 1 10 100 1k 10k 1 10 100 1k LoadCapacitance(pF) Closed−LoopGain(V/V) SMALL−SIGNALSTEPRESPONSE LARGE−SIGNALSTEPRESPONSE CL=100pF CL=100pF OPA337 VS=+5V OPA338 VS=+5V G=1 G=5 v 50mV/div 500mV/di OPA337 G=1 OPA338 G=5 1µs/div 2µs/div 7

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 APPLICATIONS INFORMATION Normally, input currents are 0.2pA. However, large inputs (greater than 500mV beyond the supply rails) can cause The OPA337 and OPA338 series are fabricated on a excessive current to flow in or out of the input pins. state-of-the-art CMOS process. The OPA337 series is Therefore, as well as keeping the input voltage below the unity-gain stable. The OPA338 series is optimized for maximum rating, it is also important to limit the input gains greater than or equal to 5. Both are suitable for a current to less than 10mA. This is easily accomplished wide range of general-purpose applications. Power- with an input resistor as shown in Figure 2. supply pins should be bypassed with 0.01µF ceramic capacitors. OPERATING VOLTAGE +5V The OPA337 series and OPA338 series can operate from I a +2.5V to +5.5V single supply with excellent OVERLOAD 10mAmax performance. Unlike most op amps which are specified at OPA337 VOUT only one supply voltage, these op amps are specified for VIN 5kΩ real-world applications; a single limit applies throughout the +2.7V to +5.5V supply range. This allows a designer to have the same assured performance at any supply voltage within the specified voltage range. Most behavior Figure 2. Input Current Protection for Voltages Exceeding the Supply Voltage remains unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltage are shown in the Typical Characteristic curves. USING THE OPA338 IN LOW GAINS The OPA338 series is optimized for gains greater than or INPUT VOLTAGE equal to 5. It has significantly wider bandwidth (12.5MHz) The input common-mode range extends from (V−) − 0.2V and faster slew rate (4.6V/µs) when compared to the to (V+) − 1.2V. For normal operation, inputs should be OPA337 series. The OPA338 series can be used in lower limited to this range. The absolute maximum input voltage gain configurations at low frequencies while maintaining is 500mV beyond the supplies. Inputs greater than the its high slew rate with the proper compensation. input common-mode range but less than maximum input voltage, while not valid, will not cause any damage to the Figure 3 shows the OPA338 in a unity-gain buffer op amp. Furthermore, if input current is limited the inputs configuration. At dc, the compensation capacitor C1 is may go beyond the power supplies without phase effectively open resulting in 100% feedback (closed-loop inversion (as shown in Figure 1) unlike some other op gain = 1). As frequency increases, C1 becomes lower amps. impedance and closed-loop gain increases, eventually becoming 1 + R /R (in this case 5, which is equal to the 2 1 minimum gain required for stability). OPA337,V =±3VGreaterThanV =±2.5V IN S 3V (VnOotUTli,mGite=d−b1y IOmPpAro3v3e7d(1s.le2wV/rµast)ein(4u.6nVit/yµgsa)ivne.rsus 10Rk2Ω inputcommon− moderange) R 1 2.5kΩ C 0V 68p1F OPA338 VOUT V IN G=±1 VOUT,G=+1 1 (limitedbyinput C1= 2πf R common−mode C 1 −3V range) Wheref isthefrequencyatwhichclosed−loop C gainslessthan5arenotappropriateseetext. Figure 1. OPA337—No Phase Inversion with Figure 3. Compensation of the OPA338 for Inputs Greater than the Power-Supply Voltage Unity-Gain Buffer 8

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 The required compensation capacitor value can be C is determined from the desired high-frequency gain (G ): 1 H determined from the following equation: C = (G − 1) × C 1 H 2 C = 1/(2πf R ) 1 C 1 For a desired dc gain of 2 and high-frequency gain of 10, Since f may shift with process variations, it is the following resistor and capacitor values result: C recommended that a value less than fC be used for R = 10kΩ C = 150pF determining C . With f = 1MHz and R = 2.5kΩ, the 1 1 1 C 1 compensation capacitor is about 68pF. R2 = 5kΩ C2 = 15pF The capacitor values shown are the nearest standard The selection of the compensation capacitor C is 1 important. A proper value ensures that the closed-loop values. Capacitor values may need to be adjusted slightly to optimize performance. For more detailed information, circuit gain is greater than or equal to 5 at high frequencies. consult the section on Low Gain Compensation in the Referring to the Open-Loop Gain vs Frequency plot in the OPA846 data sheet (SBOS250) located at www.ti.com. Typical Characteristics section, the OPA338 gain line (dashed in the curve) has a constant slope Figure 5 shows the large-signal transient response using (−20dB/decade) up to approximately 3MHz. This the circuit given in Figure 4. As shown, the OPA338 is frequency is referred to as fC. Beyond fC the slope of the stable in low gain applications and provides improved slew curve increases, suggesting that closed-loop gains less rate performance when compared to the OPA337. than 5 are not appropriate. Figure 4 shows a compensation technique using an inverting configuration. The low-frequency gain is set by the resistor ratio while the high-frequency gain is set by the capacitor ratio. As with the noninverting circuit, for OPA338 frequencies above f the gain must be greater than the C v recommended minimum stable gain for the op amp. di V/ m 0 OPA337 0 5 C ImprovedslewrateversusOPA337 15p2F (seeFigure5). R R 1 2 5kΩ 10kΩ Time(2µs/div) V IN Figure 5. G = 2, Slew-Rate Comparison of the C OPA338 and the OPA337 1 OPA338 V 150pF OUT TYPICAL APPLICATION C = 1 ,C =(G −1)×C See Figure 6 for the OPA2337 in a typical application. The 2 2πfCR2 1 H 2 ADS7822 is a 12-bit, micropower, sampling analog-to- digital converter available in the tiny MSOP-8 package. As WhereG isthehigh−frequencygain, H G =1+C/C with the OPA2337, it operates with a supply voltage as low H 1 2 as +2.7V. When used with the miniature SOT23-8 package Figure 4. Inverting Compensation Circuit of the of the OPA2337, the circuit is ideal for space-limited and OPA338 for Low Gain low-power applications. In addition, the OPA2337’s high input impedance allows large value resistors to be used Resistors R and R are chosen to set the desired dc 1 2 which results in small physical capacitors, further reducing signal gain. Then the value for C is determined as follows: 2 circuit size. For further information, consult the ADS7822 C = 1/(2πf R ) data sheet (SBAS062) located at www.ti.com. 2 C 2 9

(cid:3)(cid:1)(cid:10)""#$ (cid:3)(cid:1)(cid:10)%""# (cid:3)(cid:1)(cid:10)""&$ (cid:3)(cid:1)(cid:10)%""& www.ti.com SBOS077B − JUNE 1997 − REVISED MARCH 2005 V+=+2.7Vto5V Passband300Hzto3kHz R 9 510kΩ 1.5kRΩ1 1MRΩ2 R204kΩ C1 C3 R R 7 8 1000pF 1/2 51kΩ 150kΩ 33pF VREF 1 V+ 8 DCLOCK OPA2337E MicErolepchtroente(1) 1MRΩ3 10R06kΩ C2 1000pF OPA12/2337E +IN−2IN 1A2D−SB7it8A2/2D 67 DCOSU/STHDN SIneterirafalce 5 3 GND 4 NOTE:(1)Electretmicrophone R withinternaltransistor(FET) 20kΩ5 G=100 poweredbyR. 1 Figure 6. Low-Power, Single-Supply, Speech Bandpass Filtered Data Acquisition System SOT23−5 SOT23−8 (PackageDesignator:D) (PackageDesignator:DCN) 0.075 (1.905) 0.027 (0.686) 59) 59) 38 38 08 08 0.0. 0.0. ( ( 04) 04) 15 15 0.2. 0.2. ( ( 0.0375 0.0375 (0.9525) (0.9525) 0.018 0.026 (0.457) (0.66) Forfurtherinformationonsolder padsforsurface−mountpackages,consultApplicationBulletinSBFA015A. Figure 7. Recommended SOT23-5 and SOT23-8 Solder Footprints 10

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA2337EA/250 ACTIVE SOT-23 DCN 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR A7 & no Sb/Br) OPA2337EA/3K ACTIVE SOT-23 DCN 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR A7 & no Sb/Br) OPA2337EA/3KG4 ACTIVE SOT-23 DCN 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR A7 & no Sb/Br) OPA2337PA ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type OPA2337PA & no Sb/Br) OPA2337UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR OPA & no Sb/Br) 2337UA OPA2337UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2337UA OPA2337UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2337UA OPA2338EA/250 ACTIVE SOT-23 DCN 8 250 Green (RoHS NIPDAU Level-1-260C-UNLIM A8 & no Sb/Br) OPA2338EA/3K ACTIVE SOT-23 DCN 8 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 A8 & no Sb/Br) OPA2338UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR OPA & no Sb/Br) 2338UA OPA2338UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2338UA OPA2338UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 2338UA OPA337EA/250 ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAUAG Level-2-260C-1 YEAR -40 to 85 G37 & no Sb/Br) OPA337NA/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C37 & no Sb/Br) OPA337NA/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C37 & no Sb/Br) OPA337NA/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C37 & no Sb/Br) OPA337NA/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 C37 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA337UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 337UA OPA337UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 337UA OPA337UAG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 337UA OPA338NA/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A38 & no Sb/Br) OPA338NA/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A38 & no Sb/Br) OPA338NA/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 A38 & no Sb/Br) OPA338UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 338UA OPA338UAG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA & no Sb/Br) 338UA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA2337EA/250 SOT-23 DCN 8 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA2337EA/3K SOT-23 DCN 8 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA2337UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2338UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA337EA/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA337NA/250 SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 OPA337NA/3K SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 OPA337NA/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 OPA337UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA338NA/250 SOT-23 DBV 5 250 178.0 8.4 3.3 3.2 1.4 4.0 8.0 Q3 OPA338NA/3K SOT-23 DBV 5 3000 178.0 8.4 3.3 3.2 1.4 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 30-Apr-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA2337EA/250 SOT-23 DCN 8 250 195.0 200.0 45.0 OPA2337EA/3K SOT-23 DCN 8 3000 195.0 200.0 45.0 OPA2337UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA2338UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA337EA/250 VSSOP DGK 8 250 210.0 185.0 35.0 OPA337NA/250 SOT-23 DBV 5 250 180.0 180.0 18.0 OPA337NA/3K SOT-23 DBV 5 3000 180.0 180.0 18.0 OPA337NA/3K SOT-23 DBV 5 3000 203.0 203.0 35.0 OPA337UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA338NA/250 SOT-23 DBV 5 250 565.0 140.0 75.0 OPA338NA/3K SOT-23 DBV 5 3000 565.0 140.0 75.0 PackMaterials-Page2

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PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated