Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with e-trim™ 1 Features 3 Description • LowOffsetVoltage: ±5µV The OPAx192 family (OPA192, OPA2192, and 1 OPA4192) is a new generation of 36-V, e-trim • LowOffsetVoltageDrift: ±0.2 µV/°C operationalamplifiers. • LowNoise:5.5nV/√Hzat1kHz These devices offer outstanding dc precision and ac • HighCommon-ModeRejection:140dB performance, including rail-to-rail input/output, low • LowBiasCurrent: ±5pA offset (±5 µV, typ), low offset drift (±0.2 µV/°C, typ), • Rail-to-RailInputandOutput and10-MHzbandwidth. • WideBandwidth:10MHzGBW Unique features such as differential input-voltage • HighSlewRate:20V/µs range to the supply rail, high output current (±65 mA), high capacitive load drive of up to 1 nF, and high • LowQuiescentCurrent:1mAperAmplifier slew rate (20 V/µs) make the OPA192 a robust, high- • WideSupply:±2.25Vto±18V,4.5Vto36V performance operational amplifier for high-voltage • EMI/RFIFilteredInputs industrialapplications. • DifferentialInputVoltageRangetoSupplyRail The OPA192 family of op amps is available in • HighCapacitiveLoadDriveCapability:1nF standard packages and is specified from –40°C to +125°C. • IndustryStandardPackages: – SingleinSOIC-8,SOT-23-5,andVSSOP-8 DeviceInformation(1) – DualinSOIC-8andVSSOP-8 PARTNUMBER PACKAGE BODYSIZE(NOM) – QuadinSOIC-14andTSSOP-14 SOIC(8) 4.90mm×3.90mm OPA192 SOT-23(5) 2.90mm×1.60mm 2 Applications VSSOP(8) 3.00mm×3.00mm • MultiplexedData-AcquisitionSystems SOIC(8) 4.90mm×3.90mm OPA2192 • TestandMeasurementEquipment VSSOP(8) 3.00mm×3.00mm • High-ResolutionADCDriverAmplifiers SOIC(14) 8.65mmx3.90mm OPA4192 • SARADCReferenceBuffers TSSOP(14) 5.00mmx4.40mm • ProgrammableLogicControllers (1) Forallavailablepackages,seethepackageoptionaddendum attheendofthedatasheet. • High-SideandLow-SideCurrentSensing • HighPrecisionComparator OPA192inaHigh-Voltage,Multiplexed,Data-AcquisitionSystem Analog Inputs REF3140 RC Filter OPA350 RC Filter Bridge Sensor Reference Driver OPA192 Gain Network Gain Network + 4:2 HV Thermocouple MUX + OPA192 VINP REF OPA192 Gain Network + Antialiasing Filter ADS8864 Current Sensing work VINM Net Gain Photo LED Detector High-Voltage Multiplexed Input High-Voltage Level Translation VCM Optical Sensor 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 8.1 Overview.................................................................23 2 Applications........................................................... 1 8.2 FunctionalBlockDiagram.......................................23 3 Description............................................................. 1 8.3 FeatureDescription.................................................24 8.4 DeviceFunctionalModes........................................30 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 31 5 PinConfigurationandFunctions......................... 4 9.1 ApplicationInformation............................................31 6 Specifications......................................................... 6 9.2 TypicalApplications................................................31 6.1 AbsoluteMaximumRatings .....................................6 10 Power-SupplyRecommendations..................... 35 6.2 ESDRatings..............................................................6 11 Layout................................................................... 35 6.3 RecommendedOperatingConditions.......................6 6.4 ThermalInformation:OPA192..................................7 11.1 LayoutGuidelines.................................................35 6.5 ThermalInformation:OPA2192................................7 11.2 LayoutExample....................................................36 6.6 ThermalInformation:OPA4192................................7 12 DeviceandDocumentationSupport................. 37 6.7 ElectricalCharacteristics:V =±4Vto±18V(V = 12.1 DeviceSupport......................................................37 S S +8Vto+36V)............................................................8 12.2 DocumentationSupport........................................37 6.8 ElectricalCharacteristics:VS=±2.25Vto±4V(VS= 12.3 RelatedLinks........................................................37 +4.5Vto+8V).........................................................10 12.4 CommunityResources..........................................37 6.9 TypicalCharacteristics............................................12 12.5 Trademarks...........................................................38 6.10 TypicalCharacteristics..........................................13 12.6 ElectrostaticDischargeCaution............................38 7 ParameterMeasurementInformation................21 12.7 Glossary................................................................38 7.1 InputOffsetVoltageDrift.........................................21 13 Mechanical,Packaging,andOrderable 8 DetailedDescription............................................ 23 Information........................................................... 38 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(September2015)toRevisionE Page • ChangedPWpackagefromproductpreviewtoproductiondata........................................................................................... 1 • AddedPWpackagetotestconditionforinputoffsetvoltagedrift.......................................................................................... 8 • AddedPWpackagetotestconditionforinputoffsetvoltagedrift........................................................................................ 10 • AddedPWpackageconditiontoFigure8 ........................................................................................................................... 13 • AddedPWpackageconditiontoFigure10 ......................................................................................................................... 13 • AddedPWpackageconditiontoFigure52 ......................................................................................................................... 22 • ChangedFigure70tofixtypos............................................................................................................................................ 36 ChangesfromRevisionC(March2015)toRevisionD Page • ChangeddevicestatustoProductionData;OPA4192releasedtoProduction .................................................................... 1 • Deletedfootnote2fromDeviceInformationtable ................................................................................................................. 1 • Deletedfootnote2fromPinConfigurationandFunctionssection......................................................................................... 4 • ChangedESDRatingstable:addedcorrectOPA4192CDMspecifications ......................................................................... 6 • AddedFrequencyResponse,CrosstalkparametertoElectricalCharacteristics:V =±4Vto±18Vtable.........................9 S • AddedFrequencyResponse,CrosstalkparametertoElectricalCharacteristics:V =±2.25Vto±4Vtable....................11 S • ChangedTypicalCharacteristicstocurrentstandards(splitcurvesandtableofgraphsintoseparatesectionstobe SDScompliant) .................................................................................................................................................................... 12 • AddedCrosstalkvsFrequencyrowtoTable1 ................................................................................................................... 12 • AddedFigure48 .................................................................................................................................................................. 20 2 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 ChangesfromRevisionB(March2014)toRevisionC Page • AddedCDMrowforOPA2192,OPA4192inESDRatingstable........................................................................................... 6 • ChangedinputoffsetvoltagevaluesforV ≥(V+)–1.5Vtestcondition............................................................................ 8 CM • ChangedInputoffsetvoltageparametertypicalspecsforV =(V+)–1.5Vtestconditions ............................................. 8 CM • ChangedtestconditionsfordV /dTparameter.................................................................................................................... 8 OS • ChangedinputoffsetvoltagemaxvaluesandtestconditionsforV =(V+)–3Vtestcondition...................................... 10 CM • ChangedinputoffsetvoltagevaluesandtestconditionsforV =(V+)–1.5Vtestcondition.......................................... 10 CM • ChangedInputoffsetvoltageparametertypicalspecsforV =(V+)–1.5Vtestconditions............................................ 10 CM • ChangedtestconditionsfordV /dTparameter ................................................................................................................. 10 OS • AddedtexttolastbulletofLayoutGuidelinessection.......................................................................................................... 35 ChangesfromRevisionA(January2014)toRevisionB Page • AddedESDRatingsandRecommendedOperatingConditionstables,andParameterMeasurementInformation, ApplicationandImplementation,Power-SupplyRecommendations,andDeviceandDocumentationSupport sections,andmovedexistingsections................................................................................................................................... 1 • ChangedallOPA192andOPA2192packagestoproductiondata........................................................................................ 1 • Changedpackagenamestolateststandard;changedallMSOPtoVSSOP,SOtoSOIC,andSOT23toSOT ................. 1 • DeletedDCKpackagepinconfiguration................................................................................................................................. 4 • AddedthermalinformationforOPA192DBVandDGKpackages......................................................................................... 7 • AddedOPA2192andOPA4192ThermalInformationtables ................................................................................................ 7 • Addedrowswithadditionaltestconditionstoinputoffsetvoltageparameter........................................................................ 8 • ChangedInputoffsetvoltagedriftparameter ........................................................................................................................ 8 • ChangedCMRRtestconditions ............................................................................................................................................ 8 • Addedrowswithadditionaltestconditionstoinputoffsetvoltageparameter...................................................................... 10 • ChangedInputoffsetvoltagedriftparameter....................................................................................................................... 10 • ChangedPSSRparameter .................................................................................................................................................. 10 • ChangedCMRRtestconditions .......................................................................................................................................... 10 • AddedOutputsection........................................................................................................................................................... 11 • AddedtypicalcharacteristiccurvestoTable1 .................................................................................................................... 12 • AddedT =25°CtoTypicalCharacteristicsconditionline.................................................................................................. 12 A • AddedninenewhistogramplotsfromFigure2toFigure10............................................................................................... 13 • ChangedFigure11toshowmoreunits............................................................................................................................... 13 • ChangedFigure19 .............................................................................................................................................................. 15 • AddedtexttoApplicationInformationsection...................................................................................................................... 31 • ChangedtextinLayoutGuidelinessection.......................................................................................................................... 35 ChangesfromOriginal(December2013)toRevisionA Page • Changedfirstparagraphof16-BitPrecisionMultiplexedData-AcquisitionSystemsection................................................ 31 • ChangedFigure66andtitle................................................................................................................................................. 31 • ChangedTIDU181referencedesigntitle............................................................................................................................. 32 Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 5 Pin Configuration and Functions DBVPackage:OPA192 5-PinSOT DandDGKPackages:OPA2192 TopView 8-PinSOICandVSSOP TopView OUT 1 5 V+ OUT A 1 8 V+ V- 2 -IN A 2 7 OUT B +IN 3 4 -IN +IN A 3 6 -IN B V- 4 5 +IN B DandDGKPackages:OPA192 8-PinSOICandVSSOP TopView DandPWPackages:OPA4192 14-PinSOICandTSSOP TopView NC(1) 1 8 NC(1) -IN 2 7 V+ OUT A 1 14 OUT D +IN 3 6 OUT -IN A 2 13 -IN D V- 4 5 NC(1) +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C (1) NC=Nointernalconnection. 4 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 PinFunctions:OPA192 PIN OPA192 I/O DESCRIPTION NAME D(SOIC), DBV(SOT) DGK(VSSOP) +IN 3 3 I Noninvertinginput –IN 2 4 I Invertinginput NC 1,5,8 — — Nointernalconnection(canbeleftfloating) OUT 6 1 O Output V+ 7 5 — Positive(highest)powersupply V– 4 2 — Negative(lowest)powersupply PinFunctions:OPA2192andOPA4192 PIN OPA2192 OPA4192 I/O DESCRIPTION NAME D(SOIC), D(SOIC), DGK(VSSOP) PW(TSSOP) +INA 3 3 I Noninvertinginput,channelA +INB 5 5 I Noninvertinginput,channelB +INC — 10 I Noninvertinginput,channelC +IND — 12 I Noninvertinginput,channelD –INA 2 2 I Invertinginput,channelA –INB 6 6 I Invertinginput,channelB –INC — 9 I Invertinginput,,channelC –IND — 13 I Invertinginput,channelD OUTA 1 1 O Output,channelA OUTB 7 7 O Output,channelB OUTC — 8 O Output,channelC OUTD — 14 O Output,channelD V+ 8 4 — Positive(highest)powersupply V– 4 11 — Negative(lowest)powersupply Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT ±20 Supplyvoltage,V =(V+)–(V–) V S (40,singlesupply) Common-mode (V–)–0.5 (V+)+0.5 Voltage V Signalinputpins Differential (V+)–(V–)+0.2 Current ±10 mA Outputshortcircuit(2) Continuous Operatingrange –55 150 Temperature Junction 150 °C Storage,T –65 150 stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Short-circuittoground,oneamplifierperpackage. 6.2 ESD Ratings VALUE UNIT V Electrostaticdischarge Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±4000 V (ESD) OPA192 V Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 V (ESD) OPA2192 V Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±750 V (ESD) OPA4192 V Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 V (ESD) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Supplyvoltage,V =(V+)–(V–) 4.5(±2.25) 36(±18) V S Specifiedtemperature –40 +125 °C 6 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 6.4 Thermal Information: OPA192 OPA192 THERMALMETRIC(1) D(SOIC) DBV(SOT) DGK(VSSOP) UNIT 8PINS 5PINS 8PINS R Junction-to-ambientthermalresistance 115.8 158.8 180.4 °C/W θJA R Junction-to-case(top)thermalresistance 60.1 60.7 67.9 °C/W θJC(top) R Junction-to-boardthermalresistance 56.4 44.8 102.1 °C/W θJB ψ Junction-to-topcharacterizationparameter 12.8 1.6 10.4 °C/W JT ψ Junction-to-boardcharacterizationparameter 55.9 4.2 100.3 °C/W JB R Junction-to-case(bottom)thermalresistance N/A N/A N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.5 Thermal Information: OPA2192 OPA2192 THERMALMETRIC(1) D(SOIC) DGK(VSSOP) UNIT 8PINS 8PINS R Junction-to-ambientthermalresistance 107.9 158 °C/W θJA R Junction-to-case(top)thermalresistance 53.9 48.6 °C/W θJC(top) R Junction-to-boardthermalresistance 48.9 78.7 °C/W θJB ψ Junction-to-topcharacterizationparameter 6.6 3.9 °C/W JT ψ Junction-to-boardcharacterizationparameter 48.3 77.3 °C/W JB R Junction-to-case(bottom)thermalresistance N/A N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. 6.6 Thermal Information: OPA4192 OPA4192 THERMALMETRIC(1) D(SOIC) PW(TSSOP) UNIT 14PINS 14PINS R Junction-to-ambientthermalresistance 86.4 92.6 °C/W θJA R Junction-to-case(top)thermalresistance 46.3 27.5 °C/W θJC(top) R Junction-to-boardthermalresistance 41.0 33.6 °C/W θJB ψ Junction-to-topcharacterizationparameter 11.3 1.9 °C/W JT ψ Junction-to-boardcharacterizationparameter 40.7 33.1 °C/W JB R Junction-to-case(bottom)thermalresistance N/A N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 6.7 Electrical Characteristics: V = ±4 V to ±18 V (V = +8 V to +36 V) S S AtT =+25°C,V =V =V /2,andR =10kΩconnectedtoV /2,unlessotherwisenoted. A CM OUT S LOAD S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OFFSETVOLTAGE ±5 ±25 TA=0°Cto85°C ±8 ±50 TA=–40°Cto+125°C ±10 ±75 VOS Inputoffsetvoltage µV ±10 ±40 VCM=(V+)–1.5V TA=0°Cto85°C ±25 ±150 TA=–40°Cto+125°C ±50 ±250 TA=0°Cto85°C ±0.1 ±0.5 Dpackagesonly TA=–40°Cto+125°C ±0.15 ±0.8 dVOS/dT Inputoffsetvoltagedrift µV/°C TA=0°Cto85°C ±0.1 ±0.8 DBV,DGK,andPWpackagesonly TA=–40°Cto+125°C ±0.2 ±1.0 Power-supplyrejection PSRR ratio TA=–40°Cto+125°C ±0.3 ±1.0 µV/V INPUTBIASCURRENT ±5 ±20 pA IB Inputbiascurrent TA=–40°Cto+125°C ±5 nA ±2 ±20 pA IOS Inputoffsetcurrent TA=–40°Cto+125°C ±2 nA NOISE (V–)–0.1V<VCM<(V+)–3V f=0.1Hzto10Hz 1.30 En Inputvoltagenoise µVPP (V+)–1.5V<VCM<(V+)+0.1V f=0.1Hzto10Hz 4 f=100Hz 10.5 (V–)–0.1V<VCM<(V+)–3V Inputvoltagenoise f=1kHz 5.5 en density f=100Hz 32 nV/√Hz (V+)–1.5V<VCM<(V+)+0.1V f=1kHz 12.5 NOISE(continued) Inputcurrentnoise in density f=1kHz 1.5 fA/√Hz INPUTVOLTAGE Common-modevoltage VCM range (V–)–0.1 (V+)+0.1 V 120 140 (V–)–0.1V<VCM<(V+)–3V TA=–40°Cto+125°C 114 126 Common-mode dB CMRR 100 120 rejectionratio (V+)–1.5V<VCM<(V+) TA=–40°Cto+125°C 86 100 (V+)–3V<VCM<(V+)–1.5V SeeTypicalCharacteristics INPUTIMPEDANCE ZID Differential 100||1.6 MΩ||pF 1013Ω|| ZIC Common-mode 1||6.4 pF OPEN-LOOPGAIN (V–)+0.6V<VO<(V+)–0.6V, 120 134 RLOAD=2kΩ TA=–40°Cto+125°C 114 126 AOL Open-loopvoltagegain dB (V–)+0.3V<VO<(V+)–0.3V, 126 140 RLOAD=10kΩ TA=–40°Cto+125°C 120 134 8 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 Electrical Characteristics: V = ±4 V to ±18 V (V = +8 V to +36 V) (continued) S S AtT =+25°C,V =V =V /2,andR =10kΩconnectedtoV /2,unlessotherwisenoted. A CM OUT S LOAD S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT FREQUENCYRESPONSE GBW Unitygainbandwidth 10 MHz SR Slewrate G=1,10-Vstep 20 V/µs VS=±18V,G=1,10-Vstep 1.4 To0.01% VS=±18V,G=1,5-Vstep 0.9 ts Settlingtime µs VS=±18V,G=1,10-Vstep 2.1 To0.001% VS=±18V,G=1,5-Vstep 1.8 tOR Overloadrecoverytime VIN×G=VS 200 ns Totalharmonic THD+N distortion+noise G=1,f=1kHz,VO=3.5VRMS 0.00008% OPA2192andOPA4192,atdc 150 Crosstalk dB OPA2192andOPA4192,f=100kHz 130 OUTPUT Noload 5 15 Positiverail RLOAD=10kΩ 95 110 Voltageoutputswing RLOAD=2kΩ 430 500 VO fromrail Noload 5 15 mV Negativerail RLOAD=10kΩ 95 110 RLOAD=2kΩ 430 500 ISC Short-circuitcurrent ±65 mA CLOAD Capacitiveloaddrive SeeTypicalCharacteristics Open-loopoutput ZO impedance f=1MHz,IO=0A,seeFigure31 375 Ω POWERSUPPLY Quiescentcurrentper IO=0A 1 1.2 IQ amplifier TA=–40°Cto+125°C,IO=0A 1.5 mA TEMPERATURE Thermalprotection(1) 140 °C (1) Foradetaileddescriptionofthermalprotection,seetheThermalProtectionsection. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 6.8 Electrical Characteristics: V = ±2.25 V to ±4 V (V = +4.5 V to +8 V) S S AtT =+25°C,V =V =V /2,andR =10kΩconnectedtoV /2,unlessotherwisenoted. A CM OUT S LOAD S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OFFSETVOLTAGE ±5 ±25 VCM=(V+)–3V TA=0°Cto85°C ±8 ±50 µV TA=–40°Cto+125°C ±10 ±75 VOS Inputoffsetvoltage (V+)–3.5V<VCM<(V+)–1.5V SeeCommon-ModeVoltageRangesection ±10 ±40 VCM=(V+)–1.5V TA=0°Cto85°C ±25 ±150 µV TA=–40°Cto+125°C ±50 ±250 VCM=(V+)–3V, TA=0°Cto85°C ±0.1 ±0.5 Dpackagesonly TA=–40°Cto+125°C ±0.15 ±0.8 dVOS/dT Inputoffsetvoltagedrift VCM=(V+)–3V, TA=0°Cto85°C ±0.1 ±0.8 µV/°C DBV,DGK,andPWpackagesonly TA=–40°Cto+125°C ±0.2 ±1.1 VCM=(V+)–1.5V,TA=–40°Cto+125°C ±0.5 ±3 Power-supplyrejection PSRR ratio TA=–40°Cto+125°C,VCM=VS/2–0.75V ±1 µV/V INPUTBIASCURRENT ±5 ±20 pA IB Inputbiascurrent TA=–40°Cto+125°C ±5 nA ±2 ±20 pA IOS Inputoffsetcurrent TA=–40°Cto+125°C ±2 nA NOISE (V–)–0.1V<VCM<(V+)–3V,f=0.1Hzto10Hz 1.30 En Inputvoltagenoise µVPP (V+)–1.5V<VCM<(V+)+0.1V,f=0.1Hzto10Hz 4 f=100Hz 10.5 (V–)–0.1V<VCM<(V+)–3V f=1kHz 5.5 en Inputvoltagenoisedensity nV/√Hz f=100Hz 32 (V+)–1.5V<VCM<(V+)+0.1V f=1kHz 12.5 in Inputcurrentnoisedensity f=1kHz 1.5 fA/√Hz INPUTVOLTAGE Common-modevoltage VCM range (V–)–0.1 (V+)+0.1 V 94 110 (V–)–0.1V<VCM<(V+)–3V TA=–40°Cto+125°C 90 104 Common-moderejection dB CMRR 100 120 ratio (V+)–1.5V<VCM<(V+) TA=–40°Cto+125°C 84 100 (V+)–3V<VCM<(V+)–1.5V SeeTypicalCharacteristics INPUTIMPEDANCE ZID Differential 100||1.6 MΩ||pF 1013Ω|| ZIC Common-mode 1||6.4 pF OPEN-LOOPGAIN (V–)+0.6V<VO<(V+)–0.6V, 110 120 RLOAD=2kΩ TA=–40°Cto+125°C 100 114 AOL Open-loopvoltagegain dB (V–)+0.3V<VO<(V+)–0.3V, 110 126 RLOAD=10kΩ TA=–40°Cto+125°C 110 120 10 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 Electrical Characteristics: V = ±2.25 V to ±4 V (V = +4.5 V to +8 V) (continued) S S AtT =+25°C,V =V =V /2,andR =10kΩconnectedtoV /2,unlessotherwisenoted. A CM OUT S LOAD S PARAMETER TESTCONDITIONS MIN TYP MAX UNIT FREQUENCYRESPONSE GBW Unitygainbandwidth 10 MHz SR Slewrate G=1,10-Vstep 20 V/µs ts Settlingtime To0.01% VS=±3V,G=1,5-Vstep 1 µs tOR Overloadrecoverytime VIN×G=VS 200 ns OPA2192andOPA4192,atdc 150 Crosstalk dB OPA2192andOPA4192,f=100kHz 130 OUTPUT Noload 5 15 Positiverail RLOAD=10kΩ 95 110 Voltageoutputswingfrom RLOAD=2kΩ 430 500 VO rail Noload 5 15 mV Negativerail RLOAD=10kΩ 95 110 RLOAD=2kΩ 430 500 ISC Short-circuitcurrent ±65 mA CLOAD Capacitiveloaddrive SeeTypicalCharacteristics Open-loopoutput ZO impedance f=1MHz,IO=0A,seeFigure31 375 Ω POWERSUPPLY Quiescentcurrentper 1 1.2 IQ amplifier IO=0A TA=–40°Cto+125°C 1.5 mA TEMPERATURE Thermalprotection(1) 140 °C (1) Foradetaileddescriptionofthermalprotection,seetheThermalProtectionsection. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 6.9 Typical Characteristics Table1.TableofGraphs DESCRIPTION FIGURE OffsetVoltageProductionDistribution Figure1toFigure6 OffsetVoltageDriftDistribution Figure7toFigure10 OffsetVoltagevsTemperature Figure11 OffsetVoltagevsCommon-ModeVoltage Figure12toFigure14 OffsetVoltagevsPowerSupply Figure15 Open-LoopGainandPhasevsFrequency Figure16 Closed-LoopGainandPhasevsFrequency Figure17 InputBiasCurrentvsCommon-ModeVoltage Figure18 InputBiasCurrentvsTemperature Figure19 OutputVoltageSwingvsOutputCurrent(maximumsupply) Figure20 CMRRandPSRRvsFrequency Figure21 CMRRvsTemperature Figure22 PSRRvsTemperature Figure23 0.1-Hzto10-HzNoise Figure24 InputVoltageNoiseSpectralDensityvsFrequency Figure25 THD+NRatiovsFrequency Figure26 THD+NvsOutputAmplitude Figure27 QuiescentCurrentvsSupplyVoltage Figure28 QuiescentCurrentvsTemperature Figure29 OpenLoopGainvsTemperature Figure30 OpenLoopOutputImpedancevsFrequency Figure31 SmallSignalOvershootvsCapacitiveLoad(100-mVOutputStep) Figure32,Figure33 NoPhaseReversal Figure34 PositiveOverloadRecovery Figure35 NegativeOverloadRecovery Figure36 Small-SignalStepResponse(100mV) Figure37,Figure38 Large-SignalStepResponse Figure39 SettlingTime Figure40toFigure43 Short-CircuitCurrentvsTemperature Figure44 MaximumOutputVoltagevsFrequency Figure45 PropagationDelayRisingEdge Figure46 PropagationDelayFallingEdge Figure47 CrosstalkvsFrequency Figure48 12 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 6.10 Typical Characteristics AtT =25°C,V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. A S CM S LOAD S L 22 50 Distribution Taken From 4715 Amplifiers Distribution Taken From 190 Amplifiers 20 T = 125 (cid:131)C %) 18 40 A s ( 16 Amplifier 1124 ers (%) 30 age of 108 Amplifi 20 ent 6 c Per 4 10 2 0 0 9 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 0 0 5 0 5 0 5 0 5 1--------- 1 7 5 2 2 5 7 - - - - Offset Voltage ((cid:29)V) Offset Voltage (µV) C032 C013 Figure1.OffsetVoltageProductionDistributionat25°C Figure2.OffsetVoltageProductionDistributionat125°C 70 Distribution Taken From 190 Amplifiers 70 Distribution Taken From 190 Amplifiers T = 85(cid:131)C T = 0(cid:131)C A A 60 60 %) 50 %) 50 ers ( 40 ers ( 40 mplifi 30 mplifi 30 A A 20 20 10 10 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 544332211- 112233445 544332211- 112233445 --------- --------- Offset Voltage (µV) Offset Voltage (µV) C013 C013 Figure3.OffsetVoltageProductionDistributionat85°C Figure4.OffsetVoltageProductionDistributionat0°C 50 50 Distribution Taken From 190 Amplifiers 45 TA = -25(cid:131)C 45 DTis =tr i-b4u0t(cid:131)ioCn Taken From 190 Amplifiers A 40 40 35 35 %) %) s ( 30 s ( 30 er 25 er 25 mplifi 20 mplifi 20 A A 15 15 10 10 5 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 7 5 2 2 5 7 7 5 2 2 5 7 - - - - - - Offset Voltage (µV) Offset Voltage (µV) C013 C013 Figure5.OffsetVoltageProductionDistributionat–25°C Figure6.OffsetVoltageProductionDistributionat–40°C Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com Typical Characteristics (continued) AtT =25°C,V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. A S CM S LOAD S L 70 50 Distribution Taken From 120 Amplifiers Distribution Taken From 75 Amplifiers 60 SOIC, TA = -40(cid:131)C to +125(cid:131)C SOT and VSSOP, TA = -40(cid:131)C to +125(cid:131)C 40 50 %) %) s ( 40 s ( 30 er er mplifi 30 mplifi 20 A A 20 10 10 0 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 0 1 9 7 5 3 1 1 3 5 7 9 1 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. - - - - - - - - - - - - - - Offset Voltage Drift (µV/(cid:131)C) Offset Voltage Drift (µV/(cid:131)C) C013 C013 OPA192IDandOPA2192ID OPA192IDBV,OPA192IDGK,OPA2192IDGK,andOPA4192IPW Figure7.OffsetVoltageDriftDistribution Figure8.OffsetVoltageDriftDistribution from–40°Cto+125°C from–40°Cto+125°C 70 30 Distribution Taken From 120 Amplifiers Distribution Taken From 75 Amplifiers 60 SOIC, TA = 0(cid:131)C to 85(cid:131)C 25 SOT and VSSOP, TA = 0(cid:131)C to 85(cid:131)C 50 %) %) 20 s ( 40 s ( er er 15 plifi 30 plifi m m A A 10 20 10 5 0 5 4 3 2 1 0 1 2 3 4 5 0 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. - - - - - - - - - - - - - Offset Voltage Drift (µV/(cid:131)C) Offset Voltage Drift (µV/(cid:131)C) C013 C013 OPA192IDandOPA2192ID OPA192IDBV,OPA192IDGK,OPA2192IDGK,andOPA4192IPW Figure9.OffsetVoltageDriftDistribution Figure10.OffsetVoltageDriftDistribution from0°Cto85°C from0°Cto85°C 100 50 190 Typical Units Shown 5 Typical Units Shown 75 50 25 25 V) V) (cid:29)V (OS –250 (cid:29)V (OS 0 V = -18.1 V CM –50 –25 –75 –100 –50 –75 –50 –25 0 25 50 75 100 125 150 –20 –15 –10 –5 0 5 10 15 20 Temperature ((cid:131)C) C001 VCM (V) C001 Figure11.OffsetVoltagevsTemperature Figure12.OffsetVoltagevsCommon-ModeVoltage 14 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 Typical Characteristics (continued) AtT =25°C,V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. A S CM S LOAD S L 100 200 5 Typical Units Shown 5 Typical Units Shown 75 150 V = ±2.25 V V = +18.1 V S CM 50 100 V) 25 VCM = -18.1 V V) 50 (cid:29)V (OS –250 (cid:29)V (OS –500 P-Channel N-Channel V = -2.35 V V = +2.35 V –50 –100 CM CM –75 –150 Transition P-Channel Transition N-Channel –100 –200 12.5 13.5 14.5 15.5 16.5 17.5 18.5 –2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 VCM (V) C001 VCM (V) C001 Figure13.OffsetVoltagevsCommon-ModeVoltage Figure14.OffsetVoltagevsCommon-ModeVoltage 50 140.0 180 10 Typical Units Shown 40 V = ±2.25 V to (cid:147)18 V CLOAD = 15 pF S 120.0 30 20 100.0 Open-loop Gain 135 (cid:29)V (V) OS––2110000 Gain (dB) 468000...000 Phase 90 Phase () (cid:131) –30 20.0 45 –40 0.0 –50 –20.0 0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 1 10 100 1k 10k 100k 1M 10M 100M VSUPPLY (V) C001 Frequency (Hz) C004 Figure15.OffsetVoltagevsPowerSupply Figure16.Open-LoopGainandPhasevsFrequency 60.0 20 G = -100 G = +1 15 G = -1 40.0 G = -10 pA) 10 IB- Gain (dB) 20.0 Bias Current ( –505 IB+ ut 0.0 np –10 I –15 –20.0 –20 1000 10k 100k 1M 10M –18.0 –9.0 0.0 9.0 18.0 Frequency (Hz) C003 VCM (V) C001 Figure17.Closed-LoopGainandPhasevsFrequency Figure18.InputBiasCurrentvsCommon-ModeVoltage Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com Typical Characteristics (continued) AtT =25°C,V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. A S CM S LOAD S L 6000 (V-) + 5 I B+ 5000 IB - (V-) + 4 A) Ios +125°C p 4000 nt ( (V-) + 3 urre 3000 V) as C 2000 V (out (V-) + 2 -40°C Bi put 1000 (V-) + 1 n I 0 Ios (V-) –1000 (V-) - 1 –75 –50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60 70 80 Temperature ((cid:131)C) C001 Iout (mA) C001 Figure19.InputBiasCurrentvsTemperature Figure20.OutputVoltageSwingvsOutputCurrent (MaximumSupply) 160.0 10 Rejection Ratio (dB), Rejection Ratio (dB) 11102480000....0000 Rejection Ratio (µV/V) 02468 VS = ±2.25 V, VCM = V+ - 3 V Common-Mode Power-Supply 246000...000 +C-PPMSSRRRRRR Common-Mode ––––8642 VS = ±18 V, VCM = 0 V 0.0 –10 1 10 100 1k 10k 100k 1M –75 –50 –25 0 25 50 75 100 125 150 Frequency (Hz) C012 Temperature ((cid:131)C) C001 Figure21.CMRRandPSRRvsFrequency Figure22.CMRRvsTemperature 1 V) 0.8 V/ o (µ 0.6 ati 0.4 R y Rejection -00..220 400 nV/div ppl-0.4 u S er--0.6 w Po-0.8 Peak-to-Peak Noise = VRMS × 6.6 = 1.30 (cid:29)Vpp -1 –75 –50 –25 0 25 50 75 100 125 150 Time (1 s/div) Temperature ((cid:131)C) C001 C001 Figure23.PSRRvsTemperature Figure24.0.1-Hzto10-HzNoise 16 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 Typical Characteristics (continued) AtT =25°C,V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. A S CM S LOAD S L 1000 0.1 -60 %) G = +1 V/V, RL = 10 k(cid:13) To Noise Density (nV/rtHz) 10100 VNC-CM h=a Vnn+e -l 1In0p0u mt V onic Distortion + Noise ( 0.00.0011 GGG === +--111 VVV///VVV,,, RRRLLL === 1220 kk (cid:13)k(cid:13)(cid:13) --8100 0 tal Harmonic Distortion + Voltage 1 VPC-CMh =a n0n Ve l Input Total Harm 0.00.00000011 VBOWUT = = 8 30. 5k HVzR MS --114200 Noise (dB) 0.1 1 10 100 1k 10k 100k 10 100 1k 10k Frequency (Hz) C002 Frequency (Hz) C007 Figure25.InputVoltageNoiseSpectralDensity Figure26.THD+NRatiovsFrequency vsFrequency 0.1 -60 1.2 %) f = 1 kHz To se ( BW = 80 kHz tal H Noi 0.01 -80 arm 1.1 + o on nic c Distorti 0.001 -100 Distortio I (mA) Q1.0 oni n + Harm 0.0001 G = +1 V/V, RL = 10 k(cid:13) -120 Nois 0.9 Total 0.00001 GGG === +--111 VVV///VVV,,, RRRLLL === 1220 kk (cid:13)k(cid:13)(cid:13) -140 e (dB) 0.8 0.01 0.1 1 10 0 4 8 12 16 20 24 28 32 36 Output Amplitude (VRMS) C008 Supply Voltage (V) C001 Figure27.THD+NvsOutputAmplitude Figure28.QuiescentCurrentvsSupplyVoltage 1.2 3.0 V = 4.5 V s 2.0 Vs = 36 V 1.1 1.0 A) Vs = ±18 V V/V) m 1 µ 0.0 I (Q V = ±2.25 V A(OL s –1.0 0.9 –2.0 R = 10 k(cid:159) 0.8 –3.0 L –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 Temperature ((cid:131)C) C001 Temperature ((cid:131)C) C001 Figure29.QuiescentCurrentvsTemperature Figure30.Open-LoopGainvsTemperature Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com Typical Characteristics (continued) AtT =25°C,V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. A S CM S LOAD S L 10k 50 45 RRII =(cid:3) (cid:20)1N k(cid:159)O RRFF = (cid:3) 1(cid:20) Nk(cid:159)O G = -1 + 18 V 40 – (cid:13)dance ( ) 1k ot (%) 3305 VIN +– +OPA–11982 V RISO CL e o 25 p h m s utput I 100 Over 1250 RR II SS OO == 02 0 5 (cid:13) 2 (cid:13)5 O 10 R I S O = 5 0 (cid:13)50 5 10 0 0 1 10 100 1k 10k 100k 1M 10M 10p 100p 1n Frequency (Hz) Capacitive Load (F) C016 C013 Figure31.Open-LoopOutputImpedancevsFrequency Figure32.Small-SignalOvershootvsCapacitiveLoad (100-mVOutputStep) 50 45 + 18 V G = +1 + 18 V VIN – – RISO hoot (%) 23345050 VIN+– O+PA–11982 V RL CL V/div +– S(i±n31e78 WV.5+POaVPvP)eA–11982 V VOUT ers 20 5 v O 15 V 10 R IS O = 0 (cid:13) 0 OUT 5 R IS O = 2255 (cid:13) R = 5500 (cid:13) 0 ISO 10p 100p 1n Time (200 (cid:29)s/div) Capacitive Load (F) C013 C011 Figure33.Small-SignalOvershootvsCapacitiveLoad Figure34.NoPhaseReversal (100-mVOutputStep) RRI I =(cid:3) 1(cid:20) NkO(cid:159) RRFF = (cid:3)1(cid:20)0(cid:19) kNO(cid:159) VOUT –+ 18 V RRII = (cid:3)1(cid:20) kNO(cid:159) RRFF =+ (cid:3) 1(cid:20)108(cid:19) kNVO(cid:159) VIN+– +OPA192 VOUT VOUT – –18 V div VIN+– +OPA192 VOUT div G = -10 V/ –18 V V/ 5 G = -10 5 VIN VIN Time (200 ns/div) Time (200 ns/div) C009 C010 Figure35.PositiveOverloadRecovery Figure36.NegativeOverloadRecovery 18 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 Typical Characteristics (continued) AtT =25°C,V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. A S CM S LOAD S L RRI I =(cid:3)(cid:20) 1N k(cid:159)O RRF F =(cid:3)(cid:20) 1N (cid:159)kO G = -1 + 18 V – + OPA192 VIN – + CL div div –18 V V/ G = +1 V/ m m 20 –+ 18 V 20 OPA192 + + VIN – –18 V RL CL R = 1 k(cid:159) L CL = 10 pF CL = 10 pF Time (100 ns/div) Time (120 ns/div) C015 C006 Figure37.Small-SignalStepResponse(100mV) Figure38.Small-SignalStepResponse(100mV) 4 RCLL == 11 0k (cid:159)pF mV) 3 G = +1 ue ( 2 al V al 1 2 V/div RI R I(cid:3)=(cid:20) (cid:3)1N k(cid:159)O RF– R F(cid:3)=(cid:20)+ (cid:3)11N 8(cid:159)k OV G = -1 elta from Fin-10 0.01% Settling = ±1 mV + OPA192 D-2 VIN – + CL put –18 V ut-3 O Step Applied at t = 0 -4 Time (300 ns/div) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Time ((cid:29)s) C005 C034 Figure39.Large-SignalStepResponse Figure40.SettlingTime(10-VPositiveStep) 4 4 mV) 3 G = +1 mV) 3 G = +1 ue ( 2 ue ( 2 al al V V al 1 al 1 n n Fi Fi m 0 m 0 o o a fr-1 0.01% Settling = ±500 (cid:29)V a fr-1 elt elt 0.01% Settling = ±1 mV D-2 D-2 ut ut p p ut-3 ut-3 O O Step Applied at t = 0 Step Applied at t = 0 -4 -4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Time ((cid:29)s) Time ((cid:29)s) C034 C034 Figure41.SettlingTime(5-VPositiveStep) Figure42.SettlingTime(10-VNegativeStep) Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com Typical Characteristics (continued) AtT =25°C,V =±18V,V =V /2,R =10kΩconnectedtoV /2,andC =100pF,unlessotherwisenoted. A S CM S LOAD S L 4 80 mV) 3 G = +1 ISC, Source ue ( 2 60 ISC, Sink al V al 1 Fin A) m 0 m 40 a fro-1 0.01% Settling = ±500 (cid:29)V I (SC elt D-2 20 ut p ut-3 O Step Applied at t = 0 -4 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 –75 –50 –25 0 25 50 75 100 125 150 Time ((cid:29)s) Temperature ((cid:131)C) C034 C001 Figure43.SettlingTime(5-VNegativeStep) Figure44.Short-CircuitCurrentvsTemperature 30 Maximum output voltage without V = ±15 V S slew-rate induced distortion. Overdrive = 100 mV ) P25 div) Voltage (VP1250 oltage (5 V/ tpLH = 0.97 (cid:29)s utput 10 VS = ±5 V put V VOUT Voltage O ut V = ±2.25 V O 5 S 0 10k 100k 1M 10M Time (200 ns/div) Frequency (Hz) C033 C025 Figure45.MaximumOutputVoltagevsFrequency Figure46.PropagationDelayRisingEdge -80 v) -100 V/di VOUT Voltage Voltage (1 tpLH = 1.1 (cid:29)s sstalk (db) -120 put Overdrive = 100 mV Cro -140 ut O -160 Time (200 ns/div) -180 1k 10k 100k 1M C026 Frequency (Hz) Figure47.PropagationDelayFallingEdge Figure48.CrosstalkvsFrequency 20 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 7 Parameter Measurement Information 7.1 Input Offset Voltage Drift The OPAx192 family of operational amplifiers is manufactured using TI’s e-trim technology. Each amplifier input offset voltage and input offset voltage drift is trimmed in production, thereby minimizing errors associated with input offset voltage and input offset voltage drift. The e-trim technology is a TI proprietary method of trimming internaldeviceparametersduringeitherwaferprobingorfinaltesting.Whentrimminginputoffsetvoltagedriftthe systematic or linear drift error on each device is trimmed to zero. This results in the remaining errors associated with input offset drift are minimal and are the result from only nonlinear error sources. Figure 49 illustrates this concept. VOS Before e-trim VOS After e-trim Linear component of drift Linear component of drift e g a olt V et s Off ut p n I Temperature Figure49. InputOffsetBeforeandAfterDriftTrim A common method of specifying input offset voltage drift is the box method. The box method estimates a maximum input offset drift by bounding the offset voltage versus temperature curve with a box and using the corners of this bounding box to determine the drift. The slope of the line connecting the diagonal corners of the box corresponds to the input offset voltage drift. Figure 50 shows the box method concept. The box method works particularly well when the input offset drift is dominated by the linear component of drift, but because the OPA192 family uses TI’s e-trim technology to remove the linear component input offset voltage drift, the box method is not a particularly useful method of accurately performing an error analysis. Figure 50 shows 30 typical units of the OPAx192 with the box method superimposed for illustrative purposes. The boundaries of the box are determined by the specified temperature range along the x-axis and the maximum specified input offset voltage across that same temperature range along the y-axis. Using the box method predicts an input offset voltage drift of 0.9 µV/°C. As shown in Figure 50, the slopes of the actual input offset voltage versus temperature are much less than that predicted by the box method. The box method predicts a pessimistic value for the maximum input offsetvoltagedriftandisnotrecommendedwhenperforminganerroranalysis. Offset Voltage vs Temperature 100 75 50 V) e (P 25 g a olt 0 V et -25 s Off -50 -75 -100 -50 -25 0 25 50 75 100 125 150 Temperature (qC) Figure50. TheBoxMethod Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com Input Offset Voltage Drift (continued) Instead of the box method, a convenient way to illustrate input offset drift is to compute the slopes of the input offset voltage versus temperature curve. This is the same as computing the input offset drift at each point along the input offset voltage versus temperature curve. The results for the OPAx192 family are shown in Figure 51 andFigure52. 1 1.1 C) 0.8 SOIC C) 0.9 SOT and VSSOP +3 1 (cid:131)V/ 0.6 +3 1 (cid:131)V/ 0.7 (cid:29)ge Drift ( 00..24 + 1 (cid:29)ge Drift ( 000...135 + 1 a 0 a olt olt-0.1 V-0.2 V et et -0.3 put Offs--00..64 -3 1 - 1 put Offs--00..75 - 1 In-0.8 In-0.9 -3 1 -1 -1.1 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 Temperature ((cid:131)C) Temperature ((cid:131)C) C001 C001 Figure51.InputOffsetVoltageDriftvsTemperature Figure52.InputOffsetVoltageDriftvsTemperature (OPA192IDandOPA2192ID) (OPA192IDBV,OPA192IDGK,OPA2192IDGK,and OPA4192IPW) As shown in Figure 51, the input offset drift is typically less than ±0.3 µV/°C over the range from –40°C to +125°C. When performing an error analysis over the full specified temperature range, use the typical and maximum values for input offset voltage drift as described in the Electrical Characteristics tables. If a reduced temperature range is applicable, use the information shown in Figure 51 or Figure 52 when performing an error analysis.Todeterminethechangeininputoffsetvoltage,useEquation1: ΔV =ΔT×dV /dT OS OS where • ΔV =Changeininputoffsetvoltage OS • ΔT=Changeintemperature • dV /dT=Inputoffsetvoltagedrift (1) OS For example, determine the amount of OPA192ID input offset voltage change over the temperature range of 25°C to 75°C for 1 σ (68%) of the units. As shown in Figure 51, the input offset drift is typically 0.15 µV/°C. This inputoffsetdriftresultsinatypicalinputoffsetvoltagechangeof(75°C–25°C)× 0.15µV/°C=7.5 µV. For 3 σ (99.7%) of the units, Figure 51 shows a typical input offset drift of 0.4 µV/°C. This input offset drift results inatypicalinputoffsetvoltagechangeof(75°C– 25°C) ×0.4 µV/°C=20 µV. Figure53showssixtypicalunits. 75 6 Typical Units Shown 50 3 1 25 V) (cid:29) (OS 0 V –25 -3 1 –50 –75 –75 –50 –25 0 25 50 75 100 125 150 Temperature ((cid:131)C) C001 Figure53. InputOffsetVoltageDriftvsTemperatureforSixTypicalUnits 22 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 8 Detailed Description 8.1 Overview The OPAx192 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset temperature drift implemented during the final steps of manufacturing after the plastic molding process. This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are set, further communication to the trim structure is permanently disabled. The Functional Block Diagram section showsthesimplifieddiagramoftheOPA192withe-trim. Unlike previous e-trim op amps, the OPAx192 uses a patented two-temperature trim architecture to achieve a very low offset voltage of 25 µV (max) and low voltage offset drift of 0.5 µV/°C (max) over the full specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for high-impedanceindustrialsensors,filters,andhigh-voltagedataacquisition. 8.2 Functional Block Diagram OPAx192 (cid:16) NCH Input Stage (cid:14) IN+ (cid:16) DFirfof3en6rte- VEnntiadl BSoleowst CCaopmacpHietiignvhesa Ltiooand OSutatpguet VOUT (cid:14) IN(cid:16) (cid:14) PCH Input Stage t e-trim Package Level Trim Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 8.3 Feature Description 8.3.1 InputProtectionCircuitry The OPAx192 uses a unique input architecture to eliminate the need for input protection diodes but still provides robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure 54 can be activated by fast transient step responses and can introduce signal distortion and settling time delays because of alternate current paths, as shown in Figure 55. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling time,asshowninFigure56. V+ V+ VIN+ VIN+ VOUT VOUT 36 V OPA192 ~0.7 V VIN(cid:16) VIN(cid:16) V(cid:16) V(cid:16) OPA192 Provides Full 36-V Conventional Input Protection Differential Input Range Limits Differential Input Range Figure54. OPA192InputProtectionDoesNotLimitDifferentialInputCapability 1 Vn = +10 V RFILT +10 V Sn Ron_mux D 1 2 +10 V ~–9.3 V CFILT CS C D 2 Vin– Vn+1 = –10 V RFILT –10 V Sn+1 Ron_mux ~0.7 V CFILT CS Idiode_transient Vout Vin+ –10 V Input Low Pass Filter Simplified Mux Model Buffer Amplifier Figure55. Back-to-BackDiodesCreateSettlingIssues 100 V) 80 Standard Input Diode Structure m Extends Settling Time e ( 60 u al 40 V nal 20 0.1% Settling = ±10 mV Fi m 0 o Fr –20 a OPA192 Input Structure elt –40 Offers Fast Settling D ut –60 p Out –80 –100 0 5 10 15 20 25 30 35 40 45 50 55 60 Time ((cid:29)s) C040 Figure56. OPA192ProtectionCircuitMaintainsFast-SettlingTransientResponse 24 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 Feature Description (continued) TheOPAx192familyofoperationalamplifiersprovidesatruehigh-impedancedifferentialinputcapabilityforhigh- voltage applications. This patented input protection architecture does not introduce additional signal distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The OPA192 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping inputsignalssuchasmultiplexeddata-acquisitionsystems;seeFigure66. 8.3.2 EMIRejection The OPAx192 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx192 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure57showstheresultsofthistestingontheOPA192.Table2 showstheEMIRRIN+valuesfortheOPA192 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the application report EMI Rejection Ratio of Operational Amplifiers, SBOA128, available for download from www.ti.com. 160.0 P = -10 dBm RF 140.0 V = ±18 V SUPPLY V = 0 V CM 120.0 B) d 100.0 + ( R IN 80.0 R MI 60.0 E 40.0 20.0 0.0 10M 100M 1G 10G Frequency (Hz) C017 Figure57. EMIRRTesting Table2.OPA192EMIRRIN+ForFrequenciesofInterest FREQUENCY APPLICATIONORALLOCATION EMIRRIN+ Mobileradio,mobilesatellite,spaceoperation,weather,radar,ultra-highfrequency(UHF) 400MHz 44.1dB applications Globalsystemformobilecommunications(GSM)applications,radiocommunication,navigation, 900MHz 52.8dB GPS(to1.6GHz),GSM,aeronauticalmobile,UHFapplications 1.8GHz GSMapplications,mobilepersonalcommunications,broadband,satellite,L-band(1GHzto2GHz) 61.0dB 802.11b,802.11g,802.11n,Bluetooth®,mobilepersonalcommunications,industrial,scientificand 2.4GHz 69.5dB medical(ISM)radioband,amateurradioandsatellite,S-band(2GHzto4GHz) 3.6GHz Radiolocation,aerocommunicationandnavigation,satellite,mobile,S-band 88.7dB 802.11a,802.11n,aerocommunicationandnavigation,mobilecommunication,spaceandsatellite 5.0GHz 105.5dB operation,C-band(4GHzto8GHz) Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 8.3.3 PhaseReversalProtection The OPAx192 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverseintotheoppositerail.TheOPAx192isarail-to-railinputopamp;therefore,thecommon-moderangecan extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into theappropriaterail.ThisperformanceisshowninFigure58. V + 18 V IN – OPA192 VOUT + + – Sin3e7 WVPaPve–18 V v (±18.5V) di V/ 5 V OUT Time (200 (cid:29)s/div) C011 Figure58. NoPhaseReversal 8.3.4 ThermalProtection The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the OPAx192 is 150°C. Exceeding this temperature causes damage to the device. The OPAx192 has a thermal protection feature that prevents damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 140°C. Figure 59 shows an application example for the OPA192 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 59 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal protectionforcestheoutputtoahigh-impedancestateandtheoutputispulledtogroundthroughresistorRL. OUT 3 V NOopremraatlion +30 V TA = 65°C V PD = 0.81W (cid:25)JA = 116°C/W 0 V Output TJ = 116°C/W × 0.81W + 65°C High-Z (cid:16) TJ = 159°C (expected) 150°C OPA192 (cid:14) e 140ºC +– 3V IVN IOUT = 30 mA R10L0 (cid:159)(cid:3)3+– V mperatur e T Figure59. ThermalProtection 8.3.5 CapacitiveLoadandStability The OPAx192 features a patented output stage capable of driving large capacitive loads, and in a unity-gain configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 60 and Figure 61. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifierwillbestableinoperation. 26 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 50 50 45 RRII =(cid:3) (cid:20)1N k(cid:159)O RRFF = (cid:3) 1(cid:20) Nk(cid:159)O G = -1 45 + 18 V G = +1 – + 18 V RISO 40 – 40 OPA192 ot (%) 3305 VIN +– +OPA–11982 V RISO CL ot (%) 3305 VIN+– +–18 V RL CL o 25 o 25 h h s s Over 20 R I S O = 0 0 (cid:13) Over 20 15 R = 2 5 2 (cid:13)5 15 ISO 10 R I S O = 5 0 (cid:13)50 10 R IS O = 0 (cid:13) 0 5 5 R IS O = 2255 (cid:13) R = 5500 (cid:13) 0 0 ISO 10p 100p 1n 10p 100p 1n Capacitive Load (F) Capacitive Load (F) C013 C013 Figure60.Small-SignalOvershootvsCapacitiveLoad Figure61.Small-SignalOvershootvsCapacitiveLoad (100-mVOutputStep) (100-mVOutputStep) For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10 Ω to 20 Ω) resistor, R , in series with the output, as shown in Figure 62. This resistor significantly reduces ISO ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducingtheoutputswing.TheerrorintroducedisproportionaltotheratioR /R ,andisgenerallynegligibleat ISO L low output levels. A high capacitive load drive makes the OPA192 well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 62 uses an isolation resistor, R , to stabilize the output of an op amp. R modifies the open-loop gain of the system for increased phase ISO ISO margin, and results using the OPA192 are summarized in Table 3. For additional information on techniques to optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation, andtestresults. +V s V out R iso + + Cload V in – -V s Figure62. ExtendingCapacitiveLoadDrivewiththeOPA192 Table3.OPA192CapacitiveLoadDriveSolutionUsingIsolationResistorComparisonofCalculatedand MeasuredResults PARAMETER VALUE CapacitiveLoad 100pF 1000pF 0.01µF 0.1µF 1µF PhaseMargin 45° 60° 45° 60° 45° 60° 45° 60° 45° 60° R (Ω) 47.0 360.0 24.0 100.0 20.0 51.0 6.2 15.8 2.0 4.7 ISO Measured 23.28.6 10.4 22.5 9.0 22.1 8.7 23.1 8.6 21.0 8.6 Overshoot(%) CalculatedPM 45.1° 58.1° 45.8° 59.7° 46.1° 60.1° 45.2° 60.2° 47.2° 60.2° Forstep-by-stepdesignprocedure,circuitschematics,billofmaterials,printedcircuitboard(PCB)files, simulationresults,andtestresults,refertoTIPrecisionDesignTIDU032,CapacitiveLoadDriveSolutionusing anIsolationResistor. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 8.3.6 Common-ModeVoltageRange The OPAx192 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 63. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD performancemaybedegradedcomparedtooperationoutsidethisregion. +Vsupply IS1 VIN- PCH1 PCH2 NCH3 NCH4 VIN+ e-TrimTM FUSE BANK VOS TRIM VOS DRIFT TRIM -Vsupply Figure63. Rail-to-RailInputStage To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when possible. The OPAx192 uses a precision trim for both the N-channel and P-channel regions. This technique enables significantly lower levels of offset than previous-generation devices, causing variance in the transition regionoftheinputstagestoappearexaggeratedrelativetooffsetoverthefullcommon-moderange,asshownin Figure64. P-Channel Transition N-Channel P-Channel Transition N-Channel Region Region Region Region Region Region 200 200 V) 100 V) 100 (cid:29) (cid:29) e ( e ( g g a 0 a 0 olt olt V V et et put Offs –100 OInPpuAt1 O92ff see-tT Vrimoltage vs Vcm put Offs –100 In –200 In –200 Input Offset Voltage vs Vcm without e-Trim Input –300 –300 –15.0 –14.0 «(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)11.0 12.0 13.0 14.0 15.0 –15.0 –14.0 «(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)11.0 12.0 13.0 14.0 15.0 Common-Mode Voltage (V) Common-Mode Voltage (V) Figure64. Common-ModeTransitionvsStandardRail-to-RailAmplifiers 28 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 8.3.7 ElectricalOverstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the outputpin.Eachofthesedifferentpinfunctionshaveelectricalstresslimitsdeterminedbythevoltagebreakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidentalESDeventsbothbeforeandduringproductassembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 65 shows an illustration of the ESD circuits contained in the OPAx192 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactiveduringnormalcircuitoperation. TVS RF +– +VS VDD OPA192 R1 IN– 100 (cid:159)(cid:3) – RS IN+ 100 (cid:159)(cid:3) + ID PoEwSeDr- SCuepllply RL + VIN – VSS –+ –VS TVS Figure65. EquivalentInternalESDCircuitryRelativetoaTypicalCircuitApplication Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com AnESDeventisveryshortindurationandveryhighvoltage(forexample,1kV,100ns),whereasanEOSevent is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). DuringanESDevent,theESDsignalispassedthroughtheESDsteeringdiodestoanabsorptioncircuit(labeled ESDpower-supplycircuit).TheESDabsorptioncircuitclampsthesuppliestoasafelevel. Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistorsandTVSdiodesallowsfortheuseofdeviceESDdiodestoprotectagainstEOSevents. 8.3.8 OverloadRecovery Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. TheoverloadrecoverytimefortheOPAx192isapproximately200ns. 8.4 Device Functional Modes The OPAx192 has a single functional mode and is operational when the power-supply voltage is greater than 4.5V(±2.25V).ThemaximumpowersupplyvoltagefortheOPAx192is36V(±18V). 30 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The OPAx192 family offers outstanding dc precision and ac performance. These devices operate up to 36-V supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as 10-MHz bandwidth and high capacitive load drive. These features make the OPAx192 a robust, high- performanceoperationalamplifierforhigh-voltageindustrialapplications. 9.2 Typical Applications 9.2.1 16-BitPrecisionMultiplexedData-AcquisitionSystem Figure 66 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the OPA192andOPA140toachieveexcellentdynamicperformanceandlinearitywiththeADS8864. 1 2 3 4 Very Low Output Impedance High-Impedance Inputs Attenuate High-Voltage Input Signal Attenuate ADC Kickback Noise Input-Filter Bandwidth No Differential Input Clamps Fast-Settling Time Requirements VREF Output: Value and Accuracy Fast Settling-Time Requirements Stability of the Input Driver Low Temp and Long-Term Drift ±20-V, +OPA192 CH0+ RVeofeltraegnece RC Filter Buffer RC Filter 10-kHz Sine Wave +OPA192 CH0- OPA192 NeGtawionr k NeGtawionr k Reference Driver + 4:2 Mux REFP + OPA140 VINP 1±02-0k-HVz, +OPA192 CH3+ OPA192 NeGtawionr k + AntFiailltiaesring ASDARC Sine Wave + VINM OPA192 CHn3- Gain Network CONV 16 Bits High-Voltage Level Translation 400 kSPS High-Voltage Multiplexed Input M C V REF3240 VDoivltiadgeer OPA350 VCM Generation Circuit Counter Shmidtt Delay n Trigger Digital Counter For Multiplexer 5 Fast logic transition Figure66. OPA192in16-Bit,400-kSPS,4-Channel,MultiplexedDataAcquisitionSystemforHigh-Voltage InputswithLowestDistortion 9.2.1.1 DesignRequirements The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input. Thedesignrequirementsforthisblockdesignare: Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com Typical Applications (continued) • SystemSupplyVoltage: ±15V • ADCSupplyVoltage:3.3V • ADCSamplingRate:400kSPS • ADCReferenceVoltage(REFP):4.096V • System Input Signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency (f )of10kHzareappliedtoeachdifferentialinputofthemux. IN 9.2.1.2 DetailedDesignProcedure The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 66. The circuit isamultichanneldataacquisitionsignalchainconsistingofaninputlow-passfilter,multiplexer(mux),muxoutput buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit resolution and lowest distortion system. The diagram includes the most important specifications for each individualanalogblock. This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next step is to design a digital interface to switch the mux input channels with minimum delay. The final design challengeistodesignahigh-precision,reference-drivercircuitthatprovidestherequiredREFPreferencevoltage withlowoffset,drift,andnoisecontributions. 9.2.1.3 ApplicationCurve 2.0 B) 1.5 S L or ( 1.0 Err 0.5 y arit 0 e n onli –0.5 N gral –1.0 e nt –1.5 I –2.0 –20 –15 –10 –5 0 5 10 15 20 ADC Differential Input (V) Figure67.ADC16-BitLinearityErrorfortheMultiplexedDataAcquisitionBlock Forstep-by-stepdesignprocedure,circuitschematics,billofmaterials,PCBfiles,simulationresults,andtest results,refertoTIPrecisionDesignTIDU181,16-bit,400-kSPS,4-Channel,MultiplexedDataAcquisition SystemforHighVoltageInputswithLowestDistortion. 32 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 9.2.2 SlewRateLimitforInputProtection In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages. Bycontrollingtheslewrateofthecommandvoltagesintothedrivecircuits,theloadvoltagesrampsupanddown at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output current and slew rate of the OPAx192 make the device an optimal amplifier to achieve slew rate control forbothdual-andsingle-supplysystems.Figure68showstheOPA192inaslew-ratelimitdesign. Op Amp Gain Stage Slew Rate Limiter C1 R1 470 nF 1.69 k(cid:159) VEE VEE R2 (cid:16) 1.6 M(cid:159) OPA192 (cid:16) + VIN (cid:14) V+ OPA192 VOUT (cid:14) V+ VCC RL VCC 10 k(cid:159) Figure68. SlewRateLimiterUsesOneOpAmp Forstep-by-stepdesignprocedure,circuitschematics,billofmaterials,PCBfiles,simulationresults,andtest results,refertoTIPrecisionDesignTIDU026,SlewRateLimiterUsesOneOpAmp. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 9.2.3 PrecisionReferenceBuffer The OPAx192 features high output current drive capability and low input offset voltage, making the device an excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the 10-µF ceramic capacitor shown in Figure 69, R , a 37.4-Ω isolation resistor, provides separation of two ISO feedback paths for optimal stability. Feedback path number one is through R and is directly at the output, V . F OUT Feedback path number two is through R and C and is connected at the output of the op amp. The optimized Fx F stability components shown for the 10-µF load give a closed-loop signal bandwidth at V of 4 kHz and still OUT provides a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability components:R ,R ,C ,andR . F Fx F ISO RF 1 k(cid:159) 10R Fkx(cid:159) 39C nFF RISO (cid:16) 37.4 (cid:159) OPA192 VOUT (cid:14) V+ (cid:14) C10L µF VREF VCC 2.5 V Figure69. PrecisionReferenceBuffer 34 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 10 Power-Supply Recommendations The OPAx192 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperaturearepresentedintheTypicalCharacteristics. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the AbsoluteMaximumRatings. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout section. 11 Layout 11.1 Layout Guidelines Forbestoperationalperformanceofthedevice,usegoodPCBlayoutpractices,including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sourceslocaltotheanalogcircuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supplyapplications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed informationrefertoCircuitBoardLayoutTechniques,SLOA089. • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much betterasopposedtoinparallelwiththenoisytrace. • Place the external components as close to the device as possible. As illustrated in Figure 70, keeping RF andRGclosetotheinvertinginputminimizesparasiticcapacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitivepartofthecircuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakagecurrentsfromnearbytracesthatareatdifferentpotentials. • CleaningthePCBfollowingboardassemblyisrecommendedforbestperformance. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A lowtemperature,postcleaningbakeat85°Cfor30minutesissufficientformostcircumstances. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 11.2 Layout Example VIN + RG VOUT RF (Schematic Representation) Place components Run the input traces close to device and to as far away from each other to reduce the supply lines parasitic errors VS+ RF as possible N/C N/C RG GND –IN V+ GND VIN +IN OUTPUT V– N/C Use low-ESR, ceramic bypass capacitor Use low-ESR, GND VS– VOUT ceramic bypass Ground (GND) plane on another layer capacitor Figure70. OperationalAmplifierBoardLayoutforNoninvertingConfiguration 36 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 www.ti.com SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 12 Device and Documentation Support 12.1 Device Support 12.1.1 DevelopmentSupport 12.1.1.1 TINA-TI™(FreeSoftwareDownload) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysisofSPICE,aswellasadditionaldesigncapabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select inputwaveformsandprobecircuitnodes,voltages,andwaveforms,creatingadynamicquick-starttool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software beinstalled.DownloadthefreeTINA-TIsoftwarefromtheTINA-TIfolder. 12.1.1.2 TIPrecisionDesigns The OPA192 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, completePCBschematicandlayout,billofmaterials,andmeasuredperformanceofmanyusefulcircuits. 12.2 Documentation Support 12.2.1 RelatedDocumentation CircuitBoardLayoutTechniques,SLOA089. OpAmpsforEveryone,SLOD006. 12.3 Related Links Table 4 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table4.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY OPA192 Clickhere Clickhere Clickhere Clickhere Clickhere OPA2192 Clickhere Clickhere Clickhere Clickhere Clickhere OPA4192 Clickhere Clickhere Clickhere Clickhere Clickhere 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. Copyright©2013–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:OPA192 OPA2192 OPA4192

OPA192,OPA2192,OPA4192 SBOS620E–DECEMBER2013–REVISEDNOVEMBER2015 www.ti.com 12.5 Trademarks e-trim,E2EaretrademarksofTexasInstruments. TINA-TIisatrademarkofTexasInstruments,IncandDesignSoft,Inc. BluetoothisaregisteredtrademarkofBluetoothSIG,Inc. TINA,DesignSoftaretrademarksofDesignSoft,Inc. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 38 SubmitDocumentationFeedback Copyright©2013–2015,TexasInstrumentsIncorporated ProductFolderLinks:OPA192 OPA2192 OPA4192

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA192ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA192 & no Sb/Br) OPA192IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OUYS & no Sb/Br) OPA192IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OUYS & no Sb/Br) OPA192IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OUXS & no Sb/Br) OPA192IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OUXS & no Sb/Br) OPA192IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA192 & no Sb/Br) OPA2192ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2192 & no Sb/Br) OPA2192IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OVLM & no Sb/Br) OPA2192IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OVLM & no Sb/Br) OPA2192IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2192 & no Sb/Br) OPA4192ID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA4192 & no Sb/Br) OPA4192IDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA4192 & no Sb/Br) OPA4192IPW ACTIVE TSSOP PW 14 90 Green (RoHS SN Level-3-260C-168 HR -40 to 125 OPA4192 & no Sb/Br) OPA4192IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS SN Level-3-260C-168 HR -40 to 125 OPA4192 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF OPA192, OPA2192 : •Automotive: OPA192-Q1, OPA2192-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA192IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA192IDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA192IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA192IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA192IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2192IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2192IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2192IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA4192IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 OPA4192IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA192IDBVR SOT-23 DBV 5 3000 223.0 270.0 35.0 OPA192IDBVT SOT-23 DBV 5 250 223.0 270.0 35.0 OPA192IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 OPA192IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 OPA192IDR SOIC D 8 2500 367.0 367.0 35.0 OPA2192IDGKR VSSOP DGK 8 2500 346.0 346.0 29.0 OPA2192IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 OPA2192IDR SOIC D 8 2500 367.0 367.0 35.0 OPA4192IDR SOIC D 14 2500 367.0 367.0 38.0 OPA4192IPWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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