Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 OPAx140 High-precision, low-noise, rail-to-rail output, 11-MHz JFET op amp 1 Features 3 Description • Very-LowOffsetDrift:1μV/°Cmaximum The OPA140, OPA2140, and OPA4140 operational 1 amplifier (op amp) family is a series of low-power • Very-LowOffset:120μV JFET input amplifiers that features good drift and low • LowInputBiasCurrent:10pAmaximum input bias current. The rail-to-rail output swing and • Very-Low1/fNoise:250nV ,0.1Hzto10Hz input range that includes V– allow designers to take PP advantage of the low-noise characteristics of JFET • LowNoise:5.1nV/√Hz amplifiers while also interfacing to modern, single- • SlewRate:20V/μs supply, precision analog-to-digital converters (ADCs) • LowSupplyCurrent:2mAmaximum anddigital-to-analogconverters(DACs). • InputVoltageRangeIncludesV–supply The OPA140 achieves 11-MHz unity-gain bandwidth • Single-SupplyOperation:4.5Vto36V and 20-V/μs slew rate while consuming only 1.8 mA (typical) of quiescent current. It runs on a single 4.5-V • Dual-SupplyOperation:±2.25Vto ±18V to36-Vsupplyordual±2.25-Vto ±18-Vsupplies. • NoPhaseReversal All versions are fully specified from –40°C to +125°C • Industry-StandardSOICPackages for use in the most challenging environments. The • VSSOP,TSSOP,andSOT-23Packages OPA140 (single) is available in the 5-pin SOT-23, 8- pin VSSOP, and 8-pin SOIC packages; the OPA2140 2 Applications (dual) is available in both 8-pin VSSOP and 8-pin SOIC packages; and the OPA4140 (quad) is • Battery-PoweredInstruments available in the 14-pin SOIC and 14-pin TSSOP • IndustrialControls packages. • MedicalInstrumentation • PhotodiodeAmplifiers DeviceInformation(1) • ActiveFilters PARTNUMBER PACKAGE BODYSIZE(NOM) • DataAcquisitionSystems SOIC(8) 4.90mm×3.90mm OPA140 SOT23(5) 2.90mm×1.60mm • AutomaticTestSystems VSSOP(8) 3.00mm×3.00mm SOIC(8) 4.90mm×3.90mm OPA2140 VSSOP(8) 3.00mm×3.00mm SOIC(14) 8.65mm×3.90mm OPA4140 TSSOP(14) 5.00mm×4.40mm (1) Forallavailablepackages,seethepackageoptionaddendum attheendofthedatasheet. 0.1-Hzto10-HzNoise V =±18V SUPPLY Competitor’s Device OPAx140 v di V/ n 0 0 2 Time (1s/div) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................22 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 23 3 Description............................................................. 1 8.1 ApplicationInformation............................................23 4 RevisionHistory..................................................... 2 8.2 TypicalApplication .................................................23 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 24 6 Specifications......................................................... 5 10 Layout................................................................... 25 6.1 AbsoluteMaximumRatings......................................5 10.1 LayoutGuidelines.................................................25 6.2 ESDRatings ............................................................5 10.2 LayoutExample....................................................25 6.3 RecommendedOperatingConditions.......................5 11 DeviceandDocumentationSupport................. 26 6.4 ThermalInformation:OPA140..................................6 11.1 DeviceSupport......................................................26 6.5 ThermalInformation:OPA2140................................6 11.2 DocumentationSupport........................................26 6.6 ThermalInformation:OPA4140................................6 11.3 RelatedLinks........................................................27 6.7 ElectricalCharacteristics:V =4.5Vto36V;±2.25V 11.4 ReceivingNotificationofDocumentationUpdates27 S to±18V...................................................................... 7 11.5 CommunityResources..........................................27 6.8 TypicalCharacteristics..............................................8 11.6 Trademarks...........................................................27 7 DetailedDescription............................................ 15 11.7 ElectrostaticDischargeCaution............................27 7.1 Overview.................................................................15 11.8 Glossary................................................................27 7.2 FunctionalBlockDiagram.......................................15 12 Mechanical,Packaging,andOrderable 7.3 FeatureDescription.................................................15 Information........................................................... 27 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(August2016)toRevisionD Page • ChangedFigure12x-axistitleFrom:Frequency(Hz)To:OutputAmplitude(V )........................................................... 10 RMS ChangesfromRevisionB(November2015)toRevisionC Page • ChangedunitsforE InputvoltagenoiseFrom:µVTo:nVinElectricalCharacteristics:V =4.5Vto36V;±2.25V n S to±18V ................................................................................................................................................................................. 7 ChangesfromRevisionA(August2010)toRevisionB Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection ................................................................................................. 1 • ChangedtitleofTable1From:CharacteristicPerformanceMeasurementsTo:TableofGraphs ....................................... 8 • Changedsection7.37titleFrom:PowerDissipationandThermalProtectionTo:ThermalProtection .............................. 18 ChangesfromOriginal(July2010)toRevisionA Page • Changeddeviceanddatasheetstatustoproductiondatastatus......................................................................................... 1 • AddedSOIC(8)(MSOP)packages........................................................................................................................................ 3 2 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 5 Pin Configuration and Functions DBVPackage:OPA140 5-PinSOT-23 TopView OUT 1 5 V+ V- 2 +IN 3 4 -IN DandDGKPackages:OPA140 8-PinSOICandVSSOP TopView NC 1 8 NC –IN 2 – 7 V+ +IN 3 + 6 OUT V– 4 5 NC PinFunctions:OPA140 PIN OPA140 I/O DESCRIPTION NAME D(SOIC), DBV(SOT) DGK(VSSOP) +IN 3 3 I Noninvertinginput –IN 2 4 I Invertinginput NC 1,5,8 — — Nointernalconnection(canbeleftfloating) OUT 6 1 O Output V+ 7 5 — Positive(highest)powersupply V– 4 2 — Negative(lowest)powersupply Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com DandDGKPackages:OPA2140 8-PinSOICandVSSOP TopView OUTA 1 8 V+ –INA 2 A 7 OUTB – + +INA 3 B 6 –IN B + – V– 4 5 +IN B DandPWPackages:OPA4140 14-PinSOICandTSSOP TopView OUT A 1 14 OUT D –IN A 2 13 –IN D A D +IN A 3 12 +IN D V+ 4 11 V– + IN B 5 10 + IN C B C –IN B 6 9 –IN C OUT B 7 8 OUT C PinFunctions:OPA2140andOPA4140 PIN OPA2140 OPA4140 I/O DESCRIPTION NAME D(SOIC), D(SOIC), DGK(VSSOP) PW(TSSOP) +INA 3 3 I Noninvertinginput,channelA +INB 5 5 I Noninvertinginput,channelB +INC — 10 I Noninvertinginput,channelC +IND — 12 I Noninvertinginput,channelD –INA 2 2 I Invertinginput,channelA –INB 6 6 I Invertinginput,channelB –INC — 9 I Invertinginput,channelC –IND — 13 I Invertinginput,channelD OUTA 1 1 O Output,channelA OUTB 7 7 O Output,channelB OUTC — 8 O Output,channelC OUTD — 14 O Output,channelD V+ 8 4 — Positive(highest)powersupply V– 4 11 — Negative(lowest)powersupply 4 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT Supplyvoltage,V =(V+)–(V–) 40 V S Voltage(2) (V–)–0.5 (V+)+0.5 V Signalinputpins Current(2) –10 10 mA Outputshortcircuit(3) Continuous Operating –55 150 Temperature Junction 150 °C Storage,T –65 150 stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Inputterminalsarediode-clampedtothepower-supplyrails.Inputsignalsthatcanswingmorethan0.5Vbeyondthesupplyrailsshould becurrent-limitedto10mAorless. (3) Short-circuittoV /2(groundinsymmetricaldual-supplysetups),oneamplifierperpackage. S 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V V Electrostaticdischarge (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Supplyvoltage ±2.25 ±18 V Specifiedtemperature –40 125 °C Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com 6.4 Thermal Information: OPA140 OPA140 THERMALMETRIC(1) D(SOIC) DBV(SOT) DGK(VSSOP) UNIT 8PINS 5PINS 8PINS R Junction-to-ambientthermalresistance 160 210 180 °C/W θJA R Junction-to-case(top)thermalresistance 75 200 55 °C/W θJC(top) R Junction-to-boardthermalresistance 60 110 130 °C/W θJB ψ Junction-to-topcharacterizationparameter 9 40 N/A °C/W JT ψ Junction-to-boardcharacterizationparameter 50 105 120 °C/W JB R Junction-to-case(bottom)thermalresistance N/A N/A N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Thermal Information: OPA2140 OPA2140 THERMALMETRIC(1) D(SOIC) DGK(VSSOP) UNIT 8PINS 8PINS R Junction-to-ambientthermalresistance 160 180 °C/W θJA R Junction-to-case(top)thermalresistance 75 55 °C/W θJC(top) R Junction-to-boardthermalresistance 60 130 °C/W θJB ψ Junction-to-topcharacterizationparameter 9 N/A °C/W JT ψ Junction-to-boardcharacterizationparameter 50 120 °C/W JB R Junction-to-case(bottom)thermalresistance N/A N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.6 Thermal Information: OPA4140 OPA4140 THERMALMETRIC(1) D(SOIC) PW(TSSOP) UNIT 14PINS 14PINS R Junction-to-ambientthermalresistance 97 135 °C/W θJA R Junction-to-case(top)thermalresistance 56 45 °C/W θJC(top) R Junction-to-boardthermalresistance 53 66 °C/W θJB ψ Junction-to-topcharacterizationparameter 19 N/A °C/W JT ψ Junction-to-boardcharacterizationparameter 46 60 °C/W JB R Junction-to-case(bottom)thermalresistance N/A N/A °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 6.7 Electrical Characteristics: V = 4.5 V to 36 V; ±2.25 V to ±18 V S atT =25°C,R =2kΩconnectedtomidsupply,andV =V =midsupply(unlessotherwisenoted) A L CM OUT PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OFFSETVOLTAGE 30 120 µV VOS Inputoffsetvoltage VS=±18V,TA=–40°Cto125°C 220 VS=±2.25Vto±18V,TA=–40°Cto125°C ±4 µV/V dVOS/dT Inputoffsetvoltagedrift VS=±18V,TA=–40°Cto125°C ±0.35 1 µV/°C Power-supplyrejection PSRR ratio VS=±2.25Vto±18V,TA=–40°Cto125°C ±0.1 ±0.5 µV/V INPUTBIASCURRENT ±0.5 ±10 pA IB Inputbiascurrent TA=–40°Cto125°C ±3 nA ±0.5 ±10 pA IOS Inputoffsetcurrent TA=–40°Cto125°C ±1 nA NOISE f=0.1Hzto10Hz 250 nVPP En Inputvoltagenoise f=0.1Hzto10Hz 42 nVRMS f=10Hz 8 Inputvoltagenoise en density f=100Hz 5.8 nV/√Hz f=1kHz 5.1 Inputcurrentnoise in density f=1kHz 0.8 fA/√Hz INPUTVOLTAGE VCM Common-modevoltage TA=–40°Cto125°C (V–)–0.1 (V+)–3.5 V CMRR Common-mode VS=±18V,VCM=(V–)–0.1V 126 140 dB rejectionratio to(V+)–3.5V TA=–40°Cto125°C 120 INPUTIMPEDANCE ZID Differential 1013||10 Ω||pF ZIC Common-mode VCM=(V–)–0.1Vto(V+)–3.5V 1013||7 Ω||pF OPEN-LOOPGAIN VO=(V–)+0.35Vto(V+)–0.35V, 120 126 RL=10kΩ AOL Open-loopvoltagegain VO=(V–)+0.35Vto(V+)–0.35V, 114 126 dB RL=2kΩ TA=–40°Cto125°C 108 FREQUENCYRESPONSE BW Gainbandwidthproduct 11 MHz SR Slewrate 20 V/µs 12-bit 880 ns ts Settlingtime 16-bit 1.6 µs tOR Overloadrecoverytime 600 ns Totalharmonic THD+N distortion+noise 1kHz,G=1,VO=3.5VRMS 0.00005% OUTPUT RLOAD=10kΩ,AOL≥108dB (V–)+0.2 (V+)–0.2 VO Voltageoutput (V–)+ (V+)– V RLOAD=2kΩ,AOL≥108dB 0.35 0.35 Source 36 ISC Short-circuitcurrent mA Sink –30 CLOAD Capacitiveloaddrive SeeFigure19andFigure20 Open-loopoutput ZO impedance f=1MHz,IO=0A(SeeFigure18) 16 Ω Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com Electrical Characteristics: V = 4.5 V to 36 V; ±2.25 V to ±18 V (continued) S atT =25°C,R =2kΩconnectedtomidsupply,andV =V =midsupply(unlessotherwisenoted) A L CM OUT PARAMETER TESTCONDITIONS MIN TYP MAX UNIT POWERSUPPLY VS Power-supplyvoltage 4.5(±2.25) 9(±18) V Quiescentcurrentper IO=0A 1.8 2 IQ amplifier TA=–40°Cto125°C 2.7 mA CHANNELSEPARATION Atdc 0.02 Channelseparation μV/V At100kHz 10 6.8 Typical Characteristics Table1.TableofGraphs DESCRIPTION FIGURE OffsetVoltageProductionDistribution Figure1 OffsetVoltageDriftDistribution Figure2 OffsetVoltagevsCommon-ModeVoltage(MaximumSupply) Figure3 I vsCommon-ModeVoltage Figure5 B InputOffsetVoltagevsTemperature Figure4 OutputVoltageSwingvsOutputCurrent Figure6 CMRRandPSRRvsFrequency(RTI) Figure7 Common-ModeRejectionRatiovsTemperature Figure8 0.1-Hzto10-HzNoise Figure9 InputVoltageNoiseDensityvsFrequency Figure10 THD+NRatiovsFrequency(80-kHzAPBandwidth) Figure11 THD+NRatiovsOutputAmplitude Figure12 QuiescentCurrentvsTemperature Figure13 QuiescentCurrentvsSupplyVoltage Figure14 GainandPhasevsFrequency Figure15 Closed-LoopGainvsFrequency Figure16 Open-LoopGainvsTemperature Figure17 Open-LoopOutputImpedancevsFrequency Figure18 Small-SignalOvershootvsCapacitiveLoad(G=1) Figure19 Small-SignalOvershootvsCapacitiveLoad(G=–1) Figure20 NoPhaseReversal Figure21 PositiveOverloadRecovery Figure23 NegativeOverloadRecovery Figure24 Large-SignalPositiveandNegativeSettlingTime Figure25,Figure26 Small-SignalStepResponse(G=1) Figure27 Small-SignalStepResponse(G=–1) Figure28 Large-SignalStepResponse(G=1) Figure29 Large-SignalStepResponse(G=–1) Figure30 Short-CircuitCurrentvsTemperature Figure31 MaximumOutputVoltagevsFrequency Figure22 ChannelSeparationvsFrequency Figure32 8 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 atT =25°C,V =±18V,R =2kΩconnectedtomidsupply,andV =V =midsupply(unlessotherwisenoted) A S L CM OUT Population Population -120-110-100-90-80-70-60-50-40-30-20-100102030405060708090100110120 00.050.100.150.200.250.300.350.400.450.500.550.600.650.700.750.800.850.900.951.00 Offset Voltage (mV) Offset Voltage Drift (mV/°C) Figure1.OffsetVoltageProductionDistribution Figure2.OffsetVoltageDriftDistribution 120 160 100 18 Typical Units Shown 120 80 60 mV) 80 40 e ( g 40 mV(V)OS --2240000 ut Offset Volta -400 -60 p -80 n -80 I -120 -100 -120 -160 -18 -12 -6 0 6 12 18 -40 -25 -10 5 20 35 50 65 80 95 110 125 V (V) Temperature (?C) CM Figure3.OffsetVoltagevsCommon-ModeVoltage Figure4.InputOffsetVoltagevsTemperature (144Amplifiers) 10 18.0 17.5 8 Specified Common-Mode 17.0 -0.1V Voltage Range +14.5V V) 16.5 6 ge ( 16.0 -40°C +25°C pA) olta +85°C ( V IB 4 put -16.0 +125°C ut +I O -16.5 B 2 -17.0 -17.5 -I 0 B -18.0 -18 -15 -12 -9 -6 -3 0 3 6 9 12 15 18 0 10 20 30 40 50 60 70 V (V) Output Current (mA) CM Figure5.I vsCommon-ModeVoltage Figure6.OutputVoltageSwingvsOutputCurrent B (MaximumSupply) Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com atT =25°C,V =±18V,R =2kΩconnectedtomidsupply,andV =V =midsupply(unlessotherwisenoted) A S L CM OUT 180 0.12 Mode Rejection Ratio (dB)pply Rejection Ratio (dB) 1111642086000000 +CPMSRRRR -PSRR CMRR (V/V)m 0000....10000864 n-Su mmower- 40 0.02 CoPo 20 0 0 1 10 100 1k 10k 100k 1M 10M 100M -75 -50 -25 0 25 50 75 100 125 150 Frequency (Hz) Temperature (°C) Figure7.CMRRandPSRRvsFrequency Figure8.Common-ModeRejectionRatiovsTemperature (ReferredtoInput) 100 )z H Ö V/ n nV/div Density ( 10 100 oise N e g a olt V 1 Time (1s/div) 0.1 1 10 100 1k 10k 100k Frequency (Hz) Figure9.0.1-Hzto10-HzNoise Figure10.InputVoltageNoiseDensityvsFrequency 0.001 -100 0.01 -80 on + Noise (%) VBRWOLU= T= 2= 8k 03WkVHRMzS G =-1 Total Harmonicon + Noise (%) 0.001 BR1kWLH= z= 2 S8ki0WgknHazl GG == -+11 -100 Total Harmonic Total Harmonic Distorti 0.00.00000011 G = +1 --112400 Distortion + Noise (dB)Total Harmonic Distorti0.00.00000011 NOTE: Ionfc irnecaresea saetd lo %w csoignntraibl luetvioenls o ifs naorisees.ult --112400 Distortion + Noise (dB) 10 100 1k 10k 20k 0.1 1 10 100 Frequency (Hz) OutputAmplitude (V ) RMS Figure11.THD+NRatiovsFrequency Figure12.THD+NRatiovsOutputAmplitude 10 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 atT =25°C,V =±18V,R =2kΩconnectedtomidsupply,andV =V =midsupply(unlessotherwisenoted) A S L CM OUT 2.5 2.00 OPA140 1.75 2.0 1.50 1.5 1.25 A) A) m m 1.00 ( ( Q Q I 1.0 I 0.75 0.50 0.5 0.25 Specified Supply-Voltage Range 0 0 -75 -50 -25 0 25 50 75 100 125 150 0 4 8 12 16 20 24 28 32 36 Temperature (°C) Supply Voltage (V) Figure13.QuiescentCurrentvsTemperature Figure14. QuiescentCurrentvsSupplyVoltage 140 180 40 C = 30pF L 120 30 G = +10 Gain 100 135 20 P Gain (dB) 864000 90 hase (degre Gain (dB) -11000 G = +1 e Phase s) 20 45 -20 G =-1 0 -30 -20 0 -40 10 100 1k 10k 100k 1M 10M 100M 100k 1M 10M 100M Frequency (Hz) Frequency (Hz) Figure15.GainandPhasevsFrequency Figure16.Closed-LoopGainvsFrequency 0 1k 10kWLoad -0.2 -0.4 100 V/V) -0.6 W) m 2kWLoad ( ( O OL -0.8 Z A 10 -1.0 -1.2 -1.4 1 -75 -50 -25 0 25 50 75 100 125 150 10 100 1k 10k 100k 1M 10M 100M Temperature (°C) Frequency (Hz) Figure17.Open-LoopGainvsTemperature Figure18.Open-LoopOutputImpedancevsFrequency Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com atT =25°C,V =±18V,R =2kΩconnectedtomidsupply,andV =V =midsupply(unlessotherwisenoted) A S L CM OUT 40 50 35 ROUT= 0W +15V G = +1 45 OPA140 ROUT 40 ROUT= 0W 30 -15V RL CL 35 ROUT= 24W %) 25 %) ot ( ROUT= 24W ot ( 30 ho 20 ho 25 s s er er 20 Ov 15 Ov 15 ROUT= 51W RI=2kW RF= 2kW G =-1 10 +15V 5 ROUT= 51W 105 OPA140 ROUT CL -15V 0 0 0 200 400 600 800 1000 1200 1400 1600 0 500 1000 1500 2000 Capacitive Load (pF) Capacitive Load (pF) Figure19.Small-SignalOvershootvsCapacitiveLoad Figure20. Small-SignalOvershootvsCapacitiveLoad (100-mVOutputStep) (100-mVOutputStep) 35 Maximum Output 30 VS= ±15 V Voltage Range Without Slew-Rate Output )P 25 Induced Distortion P V v ge ( 20 5V/di +18V ut Volta 15 OPA140 Outp 10 VS= ±5 V Output 37V-PP18V 5 VS= ±2.25 V Sine Wave (±18.5V) 0 Time (0.4ms/div) 10k 100k 1M 10M Frequency (Hz) Figure22.MaximumOutputVoltagevsFrequency Figure21.NoPhaseReversal V OUT V IN div div V/ V/ 5 20kW 5 20kW V 2kW 2kW IN OPA140 VOUT OPA140 VOUT VIN VIN V G =-10 OUT G =-10 Time (0.4ms/div) Time (0.4ms/div) Figure23.PositiveOverloadRecovery Figure24.NegativeOverloadRecovery 12 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 atT =25°C,V =±18V,R =2kΩconnectedtomidsupply,andV =V =midsupply(unlessotherwisenoted) A S L CM OUT 1000 1000 800 800 V) 600 V) 600 m m e ( 400 e ( 400 Valu 200 16-bit Settling Valu 200 16-bit Settling al al n 0 n 0 Fi Fi m -200 m -200 o (±1/2LSB =±0.00075%) o (±1/2LSB =±0.00075%) a fr -400 a fr -400 Delt -600 Delt -600 -800 -800 -1000 -1000 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 Time (ms) Time (ms) Figure25.Large-SignalPositiveSettlingTime Figure26.Large-SignalNegativeSettlingTime (10-VStep) (10-VStep) C = 100pF C = 100pF L L mV/div +15V G = +1 mV/div RI=2kW RF=2kW 10 OPA140 10 +15V -15V RL CL OPA140 -15V CL G =-1 Time (100ns/div) Time (100ns/div) Figure27. Small-SignalStepResponse(100mV) Figure28. Small-SignalStepResponse(100mV) v v di di V/ V/ 2 2 Time (400 ns/div) Time (400 ns/div) Figure29.Large-SignalStepResponse Figure30. Large-SignalStepResponse Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com atT =25°C,V =±18V,R =2kΩconnectedtomidsupply,andV =V =midsupply(unlessotherwisenoted) A S L CM OUT 60 -90 ISC, Source VOUT= 3VRMS 50 ISC, Sink -100 G = +1 B) d 40 n ( -110 I(mA)SC 3200 nel Separatio --112300 RL= 2kW n a h C 10 -140 Short-circuiting causes thermal shutdown; seeApplications Informationsection. RL= 5kW 0 -150 -75 -50 -25 0 25 50 75 100 125 150 10 100 1k 10k 100k Temperature (°C) Frequency (Hz) Figure31.ShortCircuitCurrentvsTemperature Figure32.ChannelSeparationvsFrequency 14 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 7 Detailed Description 7.1 Overview The OPAx140 family of operational amplifiers is a series of low-power JFET input amplifiers that feature superior drift performance and low input bias current. The rail-to-rail output swing and input range that includes V– allow designers to use the low-noise characteristics of JFET amplifiers while also interfacing to modern, single-supply, precision analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The OPAx140 series achieves 11-MHz unity-gain bandwidth and 20-V/μs slew rate, and consumes only 1.8 mA (typical) of quiescent current.Thesedevicesoperateonasingle4.5-Vto36-Vsupplyordual ±2.25-Vto ±18-Vsupplies. TheFunctionalBlockDiagramsectionshowsthesimplifieddiagramoftheOPAx140. 7.2 Functional Block Diagram V+ Pre-Output Driver OUT IN– IN+ V– 7.3 Feature Description 7.3.1 OperatingVoltage The OPA140, OPA2140, and OPA4140 series of op amps can be used with single or dual supplies from an operating range of V = 4.5 V (±2.25 V) and up to V = 36 V (±18 V). These devices do not require symmetrical S S supplies; they only require a minimum supply voltage of 4.5 V (±2.25 V). For V less than ±3.5 V, the common- S mode input range does not include midsupply. Supply voltages higher than 40 V can permanently damage the device; see the Absolute Maximum Ratings table. Key parameters are specified over the operating temperature range, T = –40°C to 125°C. Key parameters that vary over the supply voltage or temperature range are shown A intheTypicalCharacteristicssectionofthisdatasheet. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com Feature Description (continued) 7.3.2 CapacitiveLoadandStability The dynamic characteristics of the OPAx140 have been optimized for commonly encountered gains, loads, and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolatedfromtheoutput.Thesimplestwaytoachievethisisolationistoaddasmallresistor(R equalto50Ω, OUT forexample)inserieswiththeoutput. Figure 19 and Figure 20 illustrate graphs of Small-Signal Overshoot vs Capacitive Load for several values of R . Also, see the Feedback Plots Define Op Amp AC Performance Application Bulletin, available for download OUT fromwww.ti.com,fordetailsofanalysistechniquesandapplicationcircuits. 7.3.3 OutputCurrentLimit The output current of the OPAx140 series is limited by internal circuitry to 36 mA/–30 mA (sourcing/sinking), to protect the device if the output is accidentally shorted. This short circuit current depends on temperature, as showninFigure31. 7.3.4 NoisePerformance Figure 33 shows the total circuit noise for varying source impedances with the operational amplifier in a unity- gain configuration (with no feedback resistor network and therefore no additional noise contributions). The OPA140 and OPA211 are shown with total circuit noise calculated. The op amp itself contributes both a voltage noise component and a current noise component. The voltage noise is commonly modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying component of the input bias currentandreactswiththesourceresistancetocreateavoltagecomponentofnoise.Therefore,thelowestnoise op amp for a given application depends on the source impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The OPA140, OPA2140, and OPA4140 family has both low voltage noise and extremely low current noise because of the FET input of the op amp. As a result, the current noise contribution of the OPAx140 series is negligible for any practical source impedance, which makes it the betterchoiceforapplicationswithhighsourceimpedance. TheequationinFigure33showsthecalculationofthetotalcircuitnoise,withtheseparameters: • e =voltagenoise n • I =currentnoise n • R =sourceimpedance S • k=Boltzmann'sconstant=1.38× 10–23J/K • T=temperatureindegreesKelvin(K) Formoredetailsoncalculatingnoise,seeBasicNoiseCalculations. 10k O E nsity, 1k EO OPA211 De RS al ctr pe 100 S e ois OPA140 N Resistor Noise e 10 g a otl V 2 2 2 E = e + (i R ) + 4kTR O n n S S 1 100 1k 10k 100k 1M Source Resistance, R (W) S Figure33. NoisePerformanceoftheOPA140andOPA211inUnity-GainBufferConfiguration 16 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 Feature Description (continued) 7.3.5 BasicNoiseCalculations Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuitistheroot-sum-squarecombinationofallnoisecomponents. The resistive portion of the source impedance produces thermal noise proportional to the square root of the resistance. This function is plotted in Figure 33. The source impedance is usually fixed; consequently, select the opampandthefeedbackresistorstominimizetherespectivecontributionstothetotalnoise. Figure 34 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the op amp reacts with the feedback resistors to create additional noise components. However, the extremely low currentnoiseoftheOPAx140meansthatitscurrentnoisecontributioncanbeneglected. The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance feedback resistors load the output of the amplifier. The equations for total noise are shown for both configurations. A) Noise in Noninverting Gain Configuration Noise at the output: R 2 2 2 2 R R R R E 2= 1 + 2 e 2+ 2 e 2+ e 2+ 1 + 2 e2 1 O R n R 1 2 R s 1 1 1 E O Where e = 4kTR = thermal noise of R R S S S S e = 4kTR = thermal noise of R 1 1 1 V S e = 4kTR = thermal noise of R 2 2 2 B) Noise in Inverting Gain Configuration Noise at the output: R2 2 2 2 R R R E 2= 1 + 2 e 2+ 2 e 2+ e 2+ 2 e2 R1 O R1+ RS n R1+ RS 1 2 R1+ RS s E R O S Where e = 4kTR = thermal noise of R S S S V S e = 4kTR = thermal noise of R 1 1 1 e = 4kTR = thermal noise of R 2 2 2 FortheOPAx140seriesofoperationalamplifiersat1kHz,e =5.1nV/√Hz. n Figure34. NoiseCalculationinGainConfigurations 7.3.6 Phase-ReversalProtection The OPA140, OPA2140, and OPA4140 family has internal phase-reversal protection. Many FET- and bipolar- input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input circuitry of the OPA140, OPA2140, and OPA4140 prevents phase reversal with excessive common-mode voltage; instead, the outputlimitsintotheappropriaterail(seeFigure21). Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com Feature Description (continued) 7.3.7 ThermalProtection The OPAx140 series of op amps are capable of driving 2-kΩ loads with power-supply voltages of up to ±18 V over the specified temperature range. In a single-supply configuration, where the load is connected to the negative supply voltage, the minimum load resistance is 2.8 kΩ at a supply voltage of 36 V. For lower supply voltages (either single-supply or symmetrical supplies), a lower load resistance may be used, as long as the outputcurrentdoesnotexceed13mA;otherwise,thedeviceshortcircuitcurrentprotectioncircuitmayactivate. Internal power dissipation increases when operating at high supply voltages. Copper leadframe construction used in the OPA140, OPA2140, and OPA4140 series devices improves heat dissipation compared to conventional materials. Printed-circuit-board (PCB) layout can also help reduce a possible increase in junction temperature. Wide copper traces help dissipate the heat by acting as an additional heatsink. Temperature rise canbefurtherminimizedbysolderingthedevicesdirectlytothePCBratherthanusingasocket. Although the output current is limited by internal protection circuitry, accidental shorting of one or more output channels of a device can result in excessive heating. For instance, when an output is shorted to mid-supply, the typicalshort-circuitcurrentof36mAleadstoaninternalpowerdissipationofover600mWatasupplyof ±18V. In the case of a dual OPA2140 in an 8-pin VSSOP package (thermal resistance θ = 180°C/W), such power JA dissipation would lead the die temperature to be 220°C above ambient temperature, when both channels are shorted.Thistemperatureincreasesignificantlydecreasestheoperatinglifeofthedevice. To prevent excessive heating, the OPAx140 series has an internal thermal shutdown circuit that shuts down the deviceifthedietemperatureexceedsapproximately180°C.Whenthisthermalshutdowncircuitactivates,abuilt- in hysteresis of 15°C makes sure that the die temperature must drop to approximately 165°C before the device switchesonagain. Additional consideration should be given to the combination of maximum operating voltage, maximum operating temperature, load, and package type. Figure 35 and Figure 36 show several practical considerations when evaluatingtheOPA2140(dualversion)andtheOPA4140(quadversion). As an example, the OPA4140 has a maximum total quiescent current of 10.8 mA (2.7 mA/channel) over temperature. The 14-pin TSSOP package has a typical thermal resistance of 135°C/W. This parameter means that because the junction temperature should not exceed 150°C to provide reliable operation, either the supply voltage must be reduced, or the ambient temperature should remain low enough so that the junction temperature does not exceed 150°C. This condition is illustrated in Figure 35 for various package types. Moreover, resistive loading of the output causes additional power dissipation and thus self-heating, which also must be considered when establishing the maximum supply voltage or operating temperature. To this end, Figure 36 shows the maximumsupplyvoltageversustemperatureforaworst-casedcloadresistanceof2kΩ. 20 20 18 18 e (V) 16 e (V) 16 ag 14 ag 14 olt olt V 12 V 12 y y pl 10 pl 10 p p u u m S 8 m S 8 mu 6 TSSOP Quad mu 6 TSSOP Quad xi xi a 4 SOIC Quad a 4 SOIC Quad M M 2 MSOP Dual 2 MSOP Dual SOIC Dual SOIC Dual 0 0 80 90 100 110 120 130 140 150 160 80 90 100 110 120 130 140 150 160 Ambient Temperature (°C) Ambient Temperature (°C) Figure35.MaximumSupplyVoltagevsTemperature Figure36.MaximumSupplyVoltagevsTemperature (OPA2140andOPA4140),QuiescentCondition (OPA2140andOPA4140),MaximumDCLoad 18 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 Feature Description (continued) 7.3.8 ElectricalOverstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidentalESDeventsbothbeforeandduringproductassembly. It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event. Figure 37 shows an illustration of the ESD circuits contained in the OPAx140 series (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where they meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. (2) TVS R F +V S +V OPA140 R I -In ESD Current- Steering Diodes (3) Op Amp Out R S +In Core Edge-Triggered ESD R I Absorption Circuit L D VIN(1) -V -V S (2) TVS (1) V =+V +500mV. IN S (2) TVS:+V >V >+V S(max) TVSBR(Min) S (3) Suggestedvalueapproximately1kΩ. Figure37. EquivalentInternalESDCircuitryandItsRelationtoaTypicalCircuitApplication An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high- current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbedbytheprotectioncircuitryisthendissipatedasheat. When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or more of the steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx140 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device quicklyactivatesandclampsthevoltageacrossthesupplyrailstoasafelevel. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com Feature Description (continued) When the operational amplifier connects into a circuit such as the one Figure 37 shows, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorptiondevice. Figure 37 depicts a specific example where the input voltage, V , exceeds the positive supply voltage (+V ) by IN S 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +V can sink the S current, one of the upper input steering diodes conducts and directs current to +V . Excessively high current S levels can flow with increasingly higher V . As a result, the data sheet specifications recommend that IN applicationslimittheinputcurrentto10mA. Ifthesupplyisnotcapableofsinkingthecurrent,V maybeginsourcingcurrenttotheoperationalamplifier,and IN then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levelsthatexceedtheoperationalamplifierabsolutemaximumratings. Another common question involves what happens to the amplifier if an input signal is applied to the input while thepowersupplies+V or–V areat0V. S S Again, it depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source through the current steering diodes. This state is not a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistanceintheinputpath. If there is an uncertainty about the ability of the supply to absorb this current, external Zener diodes may be added to the supply pins as shown in Figure 37. The Zener voltage must be selected such that the diode does notturnonduringnormaloperation. However, its Zener voltage should be low enough so that the Zener diode conducts if the supply pin begins to riseabovethesafeoperatingsupplyvoltagelevel. 20 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 Feature Description (continued) 7.3.9 EMIRejection The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF signal rectification. An op amp that is more efficient at rejecting this change in offset as a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in many ways, but this section provides the EMIRR IN+, which specifically describes the EMIRR performance when the RF signal is appliedtothenoninvertinginputpinoftheopamp.Ingeneral,onlythenoninvertinginputistestedforEMIRRfor thefollowingthreereasons: • Op amp input pins are known to be the most sensitive to EMI, and typically rectify RF signals better than the supplyoroutputpins. • The noninverting and inverting op amp inputs have symmetrical physical layouts and exhibit nearly matching EMIRRperformance • EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal can be isolated on a PCB. This isolation allows the RF signal to be applied directly to the noninverting input terminalwithnocomplexinteractionsfromothercomponentsorconnectingPCBtraces.Figure38 120 PRF = -10 dbm VS = r12 V 100 VCM = 0 V b) 80 d + ( N R I 60 R MI E 40 20 0 10 100 1k 10k Frequency (MHz) Figure38. OPA2140EMIRR TheEMIRRIN+oftheOPA2140isplottedversusfrequencyasshownin.Ifavailable,anydualandquadopamp deviceversionshavenearlysimilarEMIRRIN+performance.TheOPA2140unity-gainbandwidthis 11 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the op amp bandwidth. For more information, see the EMI Rejection Ratio of Operational Amplifiers Application Report, available for downloadfromwww.ti.com. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com Feature Description (continued) Table 2 lists the EMIRR IN+ values for the OPA2140 at particular frequencies commonly encountered in real- world applications. Applications listed in Table 2 may be centered on or operated near the particular frequency shown. This information may be of special interest to designers working with these types of applications, or working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific, andmedical(ISM)radioband. Table2.OPA2140EMIRRIN+forFrequenciesofInterest FREQUENCY APPLICATIONORALLOCATION EMIRRIN+ Mobileradio,mobilesatellite,spaceoperation,weather,radar,ultra-highfrequency(UHF) 400MHz 53.1dB applications Globalsystemformobilecommunications(GSM)applications,radiocommunication,navigation, 900MHz 72.2dB GPS(to1.6GHz),GSM,aeronauticalmobile,UHFapplications 1.8GHz GSMapplications,mobilepersonalcommunications,broadband,satellite,L-band(1GHzto2GHz) 80.7dB 802.11b,802.11g,802.11n,Bluetooth®,mobilepersonalcommunications,industrial,scientificand 2.4GHz 86.8dB medical(ISM)radioband,amateurradioandsatellite,S-band(2GHzto4GHz) 3.6GHz Radiolocation,aerocommunicationandnavigation,satellite,mobile,S-band 91.7dB 802.11a,802.11n,aerocommunicationandnavigation,mobilecommunication,spaceandsatellite 5GHz 96.6dB operation,C-band(4GHzto8GHz) 7.3.10 EMIRR+INTestConfiguration Figure 39 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the op amp noninverting input terminal using a transmission line. The op amp is configured in a unity gain buffer topology withtheoutputconnectedtoalow-passfilter(LPF)andadigitalmultimeter(DMM).Alargeimpedancemismatch at the op amp input causes a voltage reflection; however, this effect is characterized and accounted for when determining the EMIRR IN+. The resulting DC offset voltage is sampled and measured by the multimeter. The LPFisolatesthemultimeterfromresidualRFsignalsthatmayinterferewithmultimeteraccuracy. Ambient temperature: 25(cid:219)& +VS – 50 (cid:13)(cid:3) Low-Pass Filter + RF source DC Bias: 0 V -VS Sample / Modulation: None (CW) Digital Multimeter Frequency Sweep: 201 pt. Log Not shown: 0.1 µF and 10 µF Averaging supply decoupling Figure39. EMIRR+INTestConfiguration 7.4 Device Functional Modes The OPAx140 has a single functional mode and is operational when the power-supply voltage is greater than 4.5V(±2.25V).ThemaximumpowersupplyvoltagefortheOPAx140is36V(±18V). 22 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The OPA140, OPA2140, and OPA4140 are unity-gain stable, operational amplifiers with very low noise, input bias current, and input offset voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-μF capacitors are adequate. Designers can easily use the rail-to-rail output swing and input range that includes V– to take advantage of the low-noise characteristicsofJFETamplifierswhilealsointerfacingtomodern,single-supply,precisiondataconverters. 8.2 Typical Application R4 C5 2.94 k(cid:13)(cid:3) 1 nF – R1 R3 Output 590 (cid:13)(cid:3) 499 (cid:13)(cid:3) + Input OPA140 C2 39 nF Copyright © 2016, Texas Instruments Incorporated Figure40. 25-kHzLow-passFilter 8.2.1 DesignRequirements Lowpass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing. The OPAx140 are an excellent choice to construct high-speed, high-precision active filters. Figure 40 shows a second-order,low-passfiltercommonlyencounteredinsignalprocessingapplications. Usethefollowingparametersforthisdesignexample: • Gain=5V/V(invertinggain) • Low-passcutofffrequency=25kHz • Second-orderChebyshevfilterresponsewith3-dBgainpeakinginthepassband 8.2.2 DetailedDesignProcedure The infinite-gain multiple-feedback circuit for a low-pass network function is shown in. Use Equation 1 to calculatethevoltagetransferfunction. Output (cid:16)1RR C C (cid:11)s(cid:12) 1 3 2 5 Input s2(cid:14)(cid:11)s C (cid:12)(cid:11)1R (cid:14)1R (cid:14)1R (cid:12)(cid:14)1R R C C 2 1 3 4 3 4 2 5 (1) This circuit produces a signal inversion. For this circuit, the gain at DC and the lowpass cutoff frequency are calculatedbyEquation2: R Gain 4 R 1 1 f (cid:11)1R R C C (cid:12) C 3 4 2 5 2S (2) Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com Typical Application (continued) Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH® Filter Designer lets you create optimized filter designsusingaselectionofTIoperationalamplifiersandpassivecomponentsfromTI'svendorpartners. Available as a web based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows you to design,optimize,andsimulatecompletemultistageactivefiltersolutionswithinminutes. 8.2.3 ApplicationCurve 20 0 b) d n ( -20 ai G -40 -60 100 1k 10k 100k 1M Frequency (Hz) Figure41. OPAx140Second-Order,25-kHz,Chebyshev,Low-PassFilter 9 Power Supply Recommendations The OPAx140 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature arepresentedintheTypicalCharacteristics. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the AbsoluteMaximumRatings. Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout section. 24 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 10 Layout 10.1 Layout Guidelines Forbestoperationalperformanceofthedevice,usegoodPCBlayoutpractices,including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sourceslocaltotheanalogcircuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supplyapplications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information,seeCircuitBoardLayoutTechniques (SLOA089). • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much betterasopposedtoinparallelwiththenoisytrace. • Place the external components as close to the device as possible. As illustrated in Figure 42, keeping RF andRGclosetotheinvertinginputminimizesparasiticcapacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitivepartofthecircuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakagecurrentsfromnearbytracesthatareatdifferentpotentials. • Forbestperformance,TIrecommendscleaningthePCBfollowingboardassembly. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low temperature,postcleaningbakeat85°Cfor30minutesissufficientformostcircumstances. 10.2 Layout Example Place components close Run the input traces to device and to each VS+ as far away from other to reduce parasitic the supply lines errors as possible RF NC NC Use a low-ESR, RG ceramic bypass GND –IN V+ capacitor VIN +IN OUTPUT V– NC GND VS– GND VOUT Ground (GND) plane on another layer Use low-ESR, ceramic bypass capacitor Figure42. OperationalAmplifierBoardLayoutforNoninvertingConfiguration Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 SBOS498D–JULY2010–REVISEDJANUARY2019 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 DevelopmentSupport 11.1.1.1 TINA-TI™(FreeSoftwareDownload) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysisofSPICE,aswellasadditionaldesigncapabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select inputwaveformsandprobecircuitnodes,voltages,andwaveforms,creatingadynamicquick-starttool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software beinstalled.DownloadthefreeTINA-TIsoftwarefromtheTINA-TIfolder. 11.1.1.2 WEBENCHFilterDesignerTool WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive componentsfromTI'svendorpartners. 11.1.1.3 TIPrecisionDesigns TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performanceofmanyusefulcircuits. 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • TexasInstruments,CircuitBoardLayoutTechniques • TexasInstruments,OpAmpsforEveryoneDesignReference • TexasInstruments,OPA140,OPA2140,OPA4140EMIImmunityPerformanceTechnicalBrief • TexasInstruments,CompensateTransimpedanceAmplifiersIntuitivelyApplicationReport • TexasInstruments,Operationalamplifiergainstability,Part3:ACgain-erroranalysis • TexasInstruments,Operationalamplifiergainstability,Part2:DCgain-erroranalysis • TexasInstruments,Usinginfinite-gain,MFBfiltertopologyinfullydifferentialactivefilters • TexasInstruments,OpAmpPerformanceAnalysisApplicationBulletin • TexasInstruments,Single-SupplyOperationofOperationalAmplifiersApplicationBulletin • TexasInstruments,TuninginAmplifiersApplicationBulletin • TexasInstruments,Shelf-LifeEvaluationofLead-FreeComponentFinishesApplicationReport • TexasInstruments,FeedbackPlotsDefineOpAmpACPerformanceApplicationBulletin • TexasInstruments,EMIRejectionRatioofOperationalAmplifiersApplicationReport 26 SubmitDocumentationFeedback Copyright©2010–2019,TexasInstrumentsIncorporated ProductFolderLinks:OPA140 OPA2140 OPA4140

OPA140,OPA2140,OPA4140 www.ti.com SBOS498D–JULY2010–REVISEDJANUARY2019 11.3 Related Links Table 3 lists quick access links. Categories include technical documents, support and community resources, toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY OPA140 Clickhere Clickhere Clickhere Clickhere Clickhere OPA2140 Clickhere Clickhere Clickhere Clickhere Clickhere OPA4140 Clickhere Clickhere Clickhere Clickhere Clickhere 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.6 Trademarks E2EisatrademarkofTexasInstruments. TINA-TIisatrademarkofTexasInstruments,IncandDesignSoft,Inc. WEBENCHisaregisteredtrademarkofTexasInstruments. BluetoothisaregisteredtrademarkofBluetoothSIG,Inc. TINA,DesignSoftaretrademarksofDesignSoft,Inc. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.7 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.8 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2010–2019,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:OPA140 OPA2140 OPA4140

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA140AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA140 & no Sb/Br) OPA140AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 O140 & no Sb/Br) OPA140AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 O140 & no Sb/Br) OPA140AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 (140, O140) & no Sb/Br) OPA140AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS Call TI | NIPDAU Level-2-260C-1 YEAR -40 to 125 140 & no Sb/Br) OPA140AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA140 & no Sb/Br) OPA2140AID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 O2140A & no Sb/Br) OPA2140AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2140 & no Sb/Br) OPA2140AIDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 2140 & no Sb/Br) OPA2140AIDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 O2140A & no Sb/Br) OPA4140AID ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 O4140A & no Sb/Br) OPA4140AIDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 O4140A & no Sb/Br) OPA4140AIPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 O4140A & no Sb/Br) OPA4140AIPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 O4140A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Jan-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA140AIDBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA140AIDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA140AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA140AIDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA140AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2140AIDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2140AIDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2140AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA4140AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 OPA4140AIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Jan-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA140AIDBVR SOT-23 DBV 5 3000 202.0 201.0 28.0 OPA140AIDBVT SOT-23 DBV 5 250 202.0 201.0 28.0 OPA140AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 OPA140AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 OPA140AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA2140AIDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 OPA2140AIDGKT VSSOP DGK 8 250 210.0 185.0 35.0 OPA2140AIDR SOIC D 8 2500 367.0 367.0 35.0 OPA4140AIDR SOIC D 14 2500 367.0 367.0 38.0 OPA4140AIPWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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