OPA130 OPA130 OPA2130 OPA4130 OPA2130 OPA130 OPA2130 OPA4130 OPA4130 SBOS053A – MAY 1998 – REVISED MARCH 2006 Low Power, Precision FET-INPUT OPERATIONAL AMPLIFIERS FEATURES OPA130 (cid:1) LOW QUIESCENT CURRENT: 530µA/amp (cid:1) LOW OFFSET VOLTAGE: 1mV max Offset Trim 1 8 NC (cid:1) HIGH OPEN-LOOP GAIN: 120dB min –In 2 7 V+ (cid:1) HIGH CMRR: 90dB min +In 3 6 Output (cid:1) FET INPUT: I = 20pA max V– 4 5 Offset Trim B (cid:1) EXCELLENT BANDWIDTH: 1MHz DIP-8, SO-8 (cid:1) WIDE SUPPLY RANGE: ±2.25 to ±18V (cid:1) SINGLE, DUAL, AND QUAD VERSIONS OPA2130 DESCRIPTION Out A 1 8 V+ The OPA130 series of FET-input op amps combine precision A –In A 2 7 Out B dc performance with low quiescent current. Single, dual, and B quad versions have identical specifications for maximum +In A 3 6 –In B design flexibility. They are ideal for general-purpose, por- V– 4 5 +In B table, and battery operated applications, especially with high source impedance. DIP-8, SO-8 OPA130 op amps are easy to use and free from phase inversion and overload problems often found in common FET-input op amps. Input cascode circuitry pro- vides excellent common-mode rejection and maintains low OPA4130 input bias current over its wide input voltage range. OPA130 series op amps are stable in unity gain and provide excellent Out A 1 14 Out D dynamic behavior over a wide range of load conditions, –In A 2 13 –In D including high load capacitance. Dual and quad designs A D feature completely independent circuitry for lowest crosstalk +In A 3 12 +In D and freedom from interaction, even when overdriven or V+ 4 11 V– overloaded. +In B 5 10 +In C Single and dual versions are available in DIP-8 and SO-8 B C –In B 6 9 –In C surface-mount packages. Quad is available in DIP-14 and SO-14 surface-mount packages. All are specified for Out B 7 8 Out C –40°C to +85°C operation. DIP-14, SO-14 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 1998-2006, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC Supply Voltage, V+ to V–....................................................................36V DISCHARGE SENSITIVITY Input Voltage.....................................................(V–) –0.7V to (V+) +0.7V Output Short-Circuit(2)..............................................................Continuous Operating Temperature..................................................–40°C to +125°C This integrated circuit can be damaged by ESD. Texas Instru- Storage Temperature.....................................................–40°C to +125°C ments recommends that all integrated circuits be handled with Junction Temperature......................................................................150°C appropriate precautions. Failure to observe proper handling NOTE: (1) Stresses above these ratings may cause permanent damage. and installation procedures can cause damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. (2) Short-circuit to ground, one amplifier per package. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric PACKAGE/ORDERING INFORMATION changes could cause the device not to meet its published For the most current package and ordering information, see specifications. the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. OPA130, OPA2130, OPA4130 2 www.ti.com SBOS053A

ELECTRICAL CHARACTERISTICS At T = +25°C, V = ±15V, and R = 10kΩ, unless otherwise noted. A S L OPA130PA, UA OPA2130PA, UA OPA4130PA, UA PARAMETER CONDITION MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage ±0.2 ±1 mV vs Temperature(1) Operating Temperature Range ±2 ±10 µV/°C vs Power Supply V = ±2.25V to ±18V 2 20 µV/V S Channel Separation (dual and quad) 0.3 µV/V INPUT BIAS CURRENT(2) Input Bias Current V = 0V +5 ±20 pA CM vs Temperature See Typical Characteristics Input Offset Current V = 0V ±2 ±20 pA CM NOISE Input Voltage Noise Noise Density, f = 10Hz 30 nV/√Hz f = 100Hz 18 nV/√Hz f = 1kHz 16 nV/√Hz f = 10kHz 16 nV/√Hz Current Noise Density, f = 1kHz 4 fA/√Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range, Positive (V+)–2 (V+)–1.5 V Negative (V–)+2 (V–)+1.2 V Common-Mode Rejection V = –13V to +13V 90 105 dB CM INPUT IMPEDANCE Differential 1013 || 1 Ω || pF Common-Mode V = –13V to +13V 1013 || 3 Ω || pF CM OPEN-LOOP GAIN Open-loop Voltage Gain V = –13.8V to +13V 120 135 dB O R = 2kΩ, V = –13V to +12V 120 135 dB L O FREQUENCY RESPONSE Gain-Bandwidth Product 1 MHz Slew Rate 2 V/µs Settling Time: 0.1% G = 1, 10V Step, C = 100pF 5.5 µs L 0.01% G = 1, 10V Step, C = 100pF 7 µs L Overload Recovery Time G = 1, V = ±15V 2 µs IN Total Harmonic Distortion + Noise 1kHz, G = 1, V = 3.5Vrms 0.0003 % O OUTPUT Voltage Output, Positive (V+)–2 (V+)–1.5 V Negative (V–)+1.2 (V–)+1 V Positive R = 2kΩ (V+)–3 (V+)–2.5 V L Negative R = 2kΩ (V–)+2 (V–)+1.5 V L Short-Circuit Current ±18 mA Capacitive Load Drive (Stable Operation) 10 nF POWER SUPPLY Specified Operating Voltage ±15 V Operating Voltage Range ±2.25 ±18 V Quiescent Current (per amplifier) I = 0 ±530 ±650 µA O TEMPERATURE RANGE Operating Range –40 +85 °C Storage –40 +125 °C Thermal Resistance, θ JA DIP-8 100 °C/W SO-8 Surface-Mount 150 °C/W DIP-14 80 °C/W SO-14 Surface-Mount 110 °C/W NOTES: (1) Ensured by wafer test. (2) High-speed test at T = 25°C. J OPA130, OPA2130, OPA4130 3 SBOS053A www.ti.com

TYPICAL CHARACTERISTICS At T = +25°C, V = ±15V, and R = 10kΩ, unless otherwise noted. A S L POWER SUPPLY AND COMMON-MODE REJECTION OPEN-LOOP GAIN/PHASE vs FREQUENCY vs FREQUENCY 120 0 120 110 –PSR 100 100 CL = 100pF –45 90 80 oltage Gain (dB) 6400 φ ––91035 Phase Shift (°) PSR, CMR (dB) 8765400000 +PSR CMR V 20 30 G 20 0 –180 10 –20 0 1 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY 1k 1k 160 Hz) Hz) dB) 140 √V/ 100 100 √A/ on ( Voltage Noise (n 10 Voltage Noise 10 Current Noise (f Channel Separati 112000 DGQA u ut=oaa ld1 Da ,m n oaderl laBq csu hutaoard enC dnd— eeclvhosiat.chneensr.el R = 10kΩ Current Noise combinations yield improved L rejection. 1 1 80 1 10 100 1k 10k 100k 1M 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) INPUT BIAS AND INPUT OFFSET CURRENT INPUT BIAS CURRENT vs TEMPERATURE vs INPUT COMMON-MODE VOLTAGE 10k 10 A) p nt ( 1k e nd Input Offset Curr 101001 VCM = 0V IB IOS ut Bias Current (pA) 5 a p as In Bi 0.1 ut p In 0.01 0 –75 –50 –25 0 25 50 75 100 125 –15 –10 –5 0 5 10 15 Ambient Temperature (°C) Common-Mode Voltage (V) OPA130, OPA2130, OPA4130 4 www.ti.com SBOS053A

TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = ±15V, and R = 10kΩ, unless otherwise noted. A S L QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT A , CMR, PSR vs TEMPERATURE vs TEMPERATURE OL 140 0.65 40 A) m 0.60 35 CMR, PSR (dB) 113200 PSR OpeGna-Linoop Current Per Amp ( 00..5550 IS–C IQ 3205 Circuit Current (mA) A, OL 110 scent 0.45 IS+C 20 Short- uie 0.40 15 Q CMR 100 0.35 10 –75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125 Ambient Temperature (°C) Temperature (°C) OFFSET VOLTAGE OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION PRODUCTION DISTRIBUTION 15 20 18 16 %) %) mplifiers ( 10 mplifiers ( 111420 A A Percent of 5 Percent of 864 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 –7 –6 –5 –4 –3 –2 –1 1 2 3 4 5 6 7 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. 5. 6. 6. 7. 7. 8. Offset Voltage (µV) Offset Voltage Drift (µV/°C) TOTAL HARMONIC DISTORTION + NOISE MAXIMUM OUTPUT VOLTAGE vs FREQUENCY vs FREQUENCY 0.1 30 25 V = ±15V THD + Noise (%) 00.0.0011 G = +10 utput Voltage (Vp-p) 211050 VS = ±5VS Mwdiisathtxooimrutituo smnle owu-trpautet vinodltuacgeed R = 10kΩ O G = +1 RL = 2kΩ 5 L V = ±2.25V S 0.0001 0 100 1k 10k 100k 10k 100k 1M Frequency (Hz) Frequency (Hz) OPA130, OPA2130, OPA4130 5 SBOS053A www.ti.com

TYPICAL CHARACTERISTICS (Cont.) At T = +25°C, V = ±15V, and R = 10kΩ, unless otherwise noted. A S L SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE G =1, CL = 100pF G = 1, CL = 1000pF V/div V/div m m 50 50 500ns/div 5µs/div LARGE-SIGNAL STEP RESPONSE G = 1, C = 100pF SETTLING TIME vs GAIN L 100 0.01% s) µ div me ( V/ Ti 10 0.1% 5 g n ettli S 1 5µs/div ±1 ±10 ±100 Gain (V/V) SMALL-SIGNAL OVERSHOOT OUTPUT VOLTAGE SWING vs OUTPUT CURRENT vs LOAD CAPACITANCE 15 80 14 70 G = +1 13 g (V) 12 –55°C 60 win 11 +125°C %) 50 e S 10 +25°C ot ( ut Voltag ––1101 +125°C Oversho 4300 G = –1 utp –12 +85°C 20 O –13 G = ±5 +25°C 10 –14 –55°C –15 0 0 ±5 ±10 ±15 ±20 10pF 100pF 1nF 10nF 100nF Output Current (mA) Load Capacitance (F) OPA130, OPA2130, OPA4130 6 www.ti.com SBOS053A

APPLICATIONS INFORMATION V+ Trim Range: ±5mV typ OPA130 series op amps are unity-gain stable and suitable for a wide range of general-purpose applications. Power 10nF supply pins should be bypassed with 10nF ceramic capaci- 100kΩ tors or larger. 7 2 1 OPA130 op amps are free from unexpected output phase- 5 reversal common with FET op amps. Many FET-input op OPA130 3 6 amps exhibit phase-reversal of the output when the input OPA130 single op amp only. common-mode voltage range is exceeded. This can occur in 4 10nF Use offset adjust pins only to null voltage-follower circuits, causing serious problems in offset voltage of op amp—see text. control loop applications. OPA130 series op amps are free from this undesirable behavior. All circuitry is completely V– independent in dual and quad versions, assuring normal behavior when one amplifier in a package is overdriven or FIGURE 1. OPA130 Offset Voltage Trim Circuit. short-circuited. INPUT BIAS CURRENT OPERATING VOLTAGE The input bias current is approximately 5pA at room tem- OPA130 series op amps operate with power supplies from perature and increases with temperature as shown in the ±2.25V to ±18V with excellent performance. Although speci- Typical Characteristic curve Input Bias Current vs Tempera- fications are production tested with ±15V supplies, most ture. behavior remains unchanged throughout the full operating Input stage cascode circuitry assures that the input bias voltage range. Parameters which vary significantly with current remains virtually unchanged throughout the full input operating voltage are shown in the typical performance common-mode range of the OPA130. See the Typical curves. Characteristic curve Input Bias Current vs Common-Mode Voltage. OFFSET VOLTAGE TRIM Offset voltage of OPA130 series amplifiers is laser trimmed and usually requires no user adjustment. The OPA130 (single op amp version) provides offset voltage trim con- nections on pins 1 and 5. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure 1. This adjustment should be used only to null the offset of the op amp, not to adjust system offset or offset produced by the signal source. Nulling offset that is not produced by the amplifier will change the offset voltage drift behavior of the op amp. OPA130, OPA2130, OPA4130 7 SBOS053A www.ti.com

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OPA130UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA & no Sb/Br) 130UA OPA130UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA & no Sb/Br) 130UA OPA130UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA & no Sb/Br) 130UA OPA130UAE4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA & no Sb/Br) 130UA OPA2130UA ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA & no Sb/Br) 2130UA OPA2130UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA & no Sb/Br) 2130UA OPA2130UAE4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 OPA & no Sb/Br) 2130UA OPA4130UA ACTIVE SOIC D 14 50 Green (RoHS NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4130UA & no Sb/Br) OPA4130UA/2K5 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4130UA & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OPA130UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2130UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA4130UA/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OPA130UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA2130UA/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA4130UA/2K5 SOIC D 14 2500 367.0 367.0 38.0 PackMaterials-Page2

None

None

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated