Low Power, High Precision Operational Amplifier OP97 FEATURES PIN CONNECTIONS Low supply current: 600 μA maximum NULL 1 OP97 8 NULL OP07 type performance –IN 2 7 V+ Offset voltage: 20 μV maximum +IN 3 6 OUT VeOryf flsoewt vboialtsa cguer rderniftt : 0.6 μV/°C maximum V– 4 5 OCOVEMRP 00299-001 Figure 1. 8-Lead PDIP (P Suffix) 25°C: 100 pA maximum 8-Lead SOIC (S Suffix) −55°C to +125°C: 250 pA maximum High common-mode rejection: 114 dB minimum Extended industrial temperature range: −40°C to +85°C GENERAL DESCRIPTION The OP97 is a low power alternative to the industry-standard Common-mode rejection and power supply rejection are also OP07 precision amplifier. The OP97 maintains the standards of improved with the OP97, at 114 dB minimum over wider performance set by the OP07 while utilizing only 600 μA supply ranges of common-mode or supply voltage. Outstanding PSR, a current, less than 1/6 that of an OP07. Offset voltage is an ultralow supply range specified from ±2.25 V to ±20 V, and the minimal 25 μV, and drift over temperature is below 0.6 μV/°C. External power requirements of the OP97 combine to make the OP97 a offset trimming is not required in the majority of circuits. preferred device for portable and battery-powered instruments. Improvements have been made over OP07 specifications in The OP97 conforms to the OP07 pinout, with the null potenti- several areas. Notable is bias current, which remains below ometer connected between Pin 1 and Pin 8 with the wiper to 250 pA over the full military temperature range. The OP97 is V+. The OP97 upgrades circuit designs using AD725, OP05, ideal for use in precision long-term integrators or sample-and- OP07, OP12, and PM1012 type amplifiers. It may replace 741- hold circuits that must operate at elevated temperatures. type amplifiers in circuits without nulling or where the nulling circuitry has been removed. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1997–2009 Analog Devices, Inc. All rights reserved.

OP97 TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution...................................................................................5  Pin Connections ............................................................................... 1  Typical Performance Characteristics ..............................................6  General Description ......................................................................... 1  Application Information ................................................................ 11  Revision History ............................................................................... 2  AC Performance ............................................................................. 12  Specifications ..................................................................................... 3  Guarding and Shielding ................................................................. 13  Electrical Characteristics ............................................................. 3  Outline Dimensions ....................................................................... 15  Absolute Maximum Ratings ............................................................ 5  Ordering Guide .......................................................................... 16  Thermal Resistance ...................................................................... 5  REVISION HISTORY 3/09—Rev. F to Rev. G 01/02—Rev. C to Rev. D Changes to Figure 20 and Figure 23 ............................................... 9 Edits to Absolute Maximum Ratings .............................................. 3 Changes to Figure 26 and Figure 27 ............................................. 10 Edits to Ordering Guide ................................................................... 3 Updated Outline Dimensions ....................................................... 15 Deleted DICE Characteristics .......................................................... 3 Changes to Ordering Guide .......................................................... 16 Deleted Wafer Test Limits ................................................................ 3 Edits to Applications Information ................................................... 7 11/07—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Ordering Guide .......................................................... 16 07/03—Rev. D to Rev. E Deleted H-08A .................................................................... Universal Deleted Q-8 ......................................................................... Universal Deleted E-20A ..................................................................... Universal Deleted Die Characteristics ............................................................. 4 Deleted Wafer Test Limits ............................................................... 4 Updated TPC 14 ............................................................................... 5 Updated Outline Dimensions ....................................................... 10 Rev. G | Page 2 of 16

OP97 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = ±15 V, V = 0 V, T = 25°C, unless otherwise noted. S CM A Table 1. OP97E OP97F Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Input Offset Voltage V 10 25 30 75 μV OS Long-Term Offset Voltage Stability ΔV /Time 0.3 0.3 μV/month OS Input Offset Current I 30 100 30 150 pA OS Input Bias Current I ±30 ±100 ±30 ±150 pA B Input Noise Voltage e p-p 0.1 Hz to 10 Hz 0.5 0.5 μV p-p n Input Noise Voltage Density e f = 10 Hz1 17 30 17 30 nV/√Hz n O f = 1000 Hz2 14 22 14 22 nV/√Hz O Input Noise Current Density i f = 10 Hz 20 20 fA/√Hz n O Large Signal Voltage Gain A V = ±10 V; R = 2 kΩ 300 2000 200 2000 V/mV VO O L Common-Mode Rejection CMR V = ±13.5 V 114 132 110 132 dB CM Input Voltage Range3 IVR ±13.5 ±14.0 ±13.5 ±14.0 V OUTPUT CHARACTERISTICS Output Voltage Swing V R = 10 kΩ ±13 ±14 ±13 ±14 V O L Differential Input Resistance4 R 30 30 MΩ IN POWER SUPPLY Power Supply Rejection PSR V = ±2 V to ±20 V 114 132 110 132 dB S Supply Current I 380 600 380 600 μA SY Supply Voltage V Operating range ±2 ±15 ±20 ±2 ±15 ±20 V S DYNAMIC PERFORMANCE Slew Rate SR 0.1 0.2 0.1 0.2 V/μs Closed-Loop Bandwidth BW A = 1 0.4 0.9 0.4 0.9 MHz VCL 1 10 Hz noise voltage density is sample tested. Devices 100% tested for noise are available on request. 2 Sample tested. 3 Guaranteed by CMR test. 4 Guaranteed by design. Rev. G | Page 3 of 16

OP97 V = ±15 V, V = 0 V, −40°C ≤ T ≤ +85°C for the OP97E/OP97F, unless otherwise noted. S CM A Table 2. OP97E OP97F Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Input Offset Voltage V 25 60 60 200 μV OS Average Temperature TCV S suffix 0.2 0.6 0.3 2.0 μV/°C OS Coefficient of V 0.3 OS Input Offset Current I 60 250 80 750 pA OS Average Temperature TCI 0.4 2.5 0.6 7.5 pA/°C OS Coefficient of I OS Input Bias Current I ±60 ±250 ±80 ±750 pA B Average Temperature Coefficient of I TCI 0.4 2.5 0.6 7.5 pA/°C B B Large Signal Voltage Gain A V = 10 V; R = 2 kΩ 200 1000 150 1000 V/mV VO O L Common-Mode Rejection CMR V = ±13.5 V 108 128 108 128 dB CM Power Supply Rejection PSR V = ±2.5 V to ±20 V 108 126 108 128 dB S Input Voltage Range1 IVR ±13.5 ±14.0 ±13.5 ±14.0 V Output Voltage Swing V R = 10 kΩ ±13 ±14 ±13 ±14 V O L Slew Rate SR 0.05 0.15 0.05 0.15 V/μs Supply Current I 400 800 400 800 μA SY Supply Voltage V Operating range ±2.5 ±15 ±20 ±2.5 ±15 ±20 V S 1 Guaranteed by CMR test. Rev. G | Page 4 of 16

OP97 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Table 3. Parameter Rating Table 4. Supply Voltage ±20 V Package Type θ 1 θ Unit JA JC Input Voltage1 ±20 V 8-Lead PDIP (P Suffix) 103 43 °C/W Differential Input Voltage2 ±1 V 8-Lead SOIC (S Suffix) 158 43 °C/W Differential Input Current2 ±10 mA 1 θJA is specified for worst-case mounting conditions, that is, θJA is specified for Output Short-Circuit Duration Indefinite device in socket for PDIP package; θJA is specified for device soldered to printed circuit board for SOIC package. Operating Temperature Range −40°C to +85°C OP97E, OP97F (P, S) ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C 1 For supply voltages less than ±20 V, the absolute maximum input voltage is equal to the supply voltage. 2 The inputs of the OP97 are protected by back-to-back diodes. Current- limiting resistors are not used in order to achieve low noise. Differential input voltages greater than 1 V cause excessive current to flow through the input protection diodes unless limiting resistance is used. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. G | Page 5 of 16

OP97 TYPICAL PERFORMANCE CHARACTERISTICS 400 60 1894UNITS VTAS == 2±51°5CV TVAC M= =2 50°VC VCM= 0V 40 300 IB– NITS T (pA) 20 U N R OF 200 URRE 0 IB+ E C NUMB NPUT –20 100 I IOS –40 0–40 –20INPUT OFFSET0 VOLTAGE (µV2)0 40 00299-002 –60–75 –50 –25 TE0MPERA25TURE (5°C0) 75 100 125 00299-005 Figure 2. Typical Distribution of Input Offset Voltage Figure 5. Input Bias, Offset Current vs. Temperature 400 60 1920UNITS VS = ±15V TA = 25°C TA = 25°C VS=±15V VCM= 0V 40 IB– 300 NITS T (pA) 20 IB+ U N R OF 200 URRE 0 NUMBE NPUT C –20 IOS I 100 –40 –0100 –50INPUT BIAS C0URRENT (pA) 50 100 300299-00 –60–15 –10 COM–5MON-MOD0E VOLTAG5E (V) 10 15 00299-006 Figure 3. Typical Distribution of Input Bias Current Figure 6. Input Bias, Offset Current vs. Common-Mode Voltage 500 ±5 400 1894UNITS VTVASC M== =2± 510°5VCV µV) ±4 TVVASC M== =±21505°VCV E ( U UNITS300 ALVAL ±3 OF FIN R M E O MB200 FR ±2 NU ON J PACKAGES TI A 100 EVI ±1 Z, P PACKAGES D 0–60 –40 INP–U2T0 OFFSET0 CURREN2T0 (pA) 40 60400299-00 00 T1IMEAFTER P2OWERAPPL3IED (Minute4s) 5 00299-007 Figure 4. Typical Distribution of Input Offset Current Figure 7. Input Offset Voltage Warmup Drift Rev. G | Page 6 of 16

OP97 1000 450 BALANCED OR UNBALANCED NO LOAD VS = ±15V V) VCM = 0V 425 µ E ( SET VOLTAG 100 –55°C ≤ TA ≤ +125°C URRENT (µA) 430705 TTAA == ++12255°C°C F C CTIVE OF 10 TA = 25°C SUPPLY 350 TA = –55°C E F EF 325 11k 3k 10kSOU3R0CkE RE10S0ISkTAN30C0Ek (Ω)1M 3M 10M 9-0080029 3000 5 SUPPLY V1O0LTAGE (±V) 15 20 00299-011 Figure 8. Effective Offset Voltage vs. Source Resistance Figure 11. Supply Current vs. Supply Voltage 100 140 C) BALANCED OR UNBALANCED TA = 25°C DRIFT (µV/° VVSC M= =± 105VV ON (dB) 112000 VVSCM==±1±51V0V E 10 TI G C A E OLT REJ 80 V E ET OD 60 S M FF 1 N- O O VE MM 40 CTI CO E 20 F F E 0.11k 10k SOUR10C0Ek RESISTA1NMCE (Ω) 10M 100M 9-0090029 01 10 100FREQUE1NkCY (Hz)10k 100k 1M 00299-012 Figure 9. Effective TCVOS vs. Source Resistance Figure 12. Common-Mode Rejection vs. Frequency 20 140 15 TA = –55°C TVAS == ±2155°CV A) TA = +25°C dB) 120 ΔVS=10V p-p T (m 10 ON ( URREN 5 TA = +125°C EJECTI 100 –PSR T-CIRCUIT C –50 VOSU T= P±U15TV SHORTED TO GROUNTDA = +125°C R SUPPLY R 8600 +PSR R E HO –10 TA = +25°C OW S P 40 –15 TA = –55°C –200 TIME FR1OM OUTPUT SHORT 2(Minutes) 3 00299-010 200.1 1 10 FR1E0Q0UENCY1 k(Hz) 10k 100k 1M 00299-013 Figure 10. Short-Circuit Current vs. Time, Temperature Figure 13. Power Supply Rejection vs. Frequency Rev. G | Page 7 of 16

OP97 10k VVSO == ±±1150VV µV/DIV) TA = +125°C RVVSCL M== =±1 1005kVVΩ 0 V) TA = –55°C E (1 m G AIN (V/ TA = +25°C VOLTA TA = +25°C P G 1k UT N-LOO TA = +125°C AL INP TA = –55°C OPE ENTI R E F F DI 1001 2 LOAD RESISTA5NCE (kΩ) 10 20 9-0140029 –15 –10 –O5UTPUT VO0LTAGE (V5) 10 15 00299-017 Figure 14. Open-Loop Gain vs. Load Resistance Figure 17. Open-Loop Gain Linearity 1k 1k 35 TA = 25°C TA = 25°C VS = ±2V TO ±20V 30 VS = ±15V NSITY (nV/ Hz) 100 CURRENT NOISE 100 NSITY (fA/ Hz) NG (V p-p) 2250 fA1O%V C= TL 1H =kD H+z1 DE DE WI SE SE T S 15 E NOI 10 VOLTAGE NOISE 10 T NOI UTPU G N O 10 LTA 1/1 C2.O5HRzNER RRE O U V C 5 1/1 CORNER 120Hz 11 10FREQUENCY (Hz)100 1k1 9-0150029 010 1L0O0AD RESISTANCE (1Ωk) 10k 00299-018 Figure 15. Noise Density vs. Frequency Figure 18. Maximum Output Swing vs. Load Resistance 10 35 Hz) TVAS == 2±52°VC TO ±20V 30 TVA1%ASV C ==TL H2 ±=51D °5+CV1 SITY (µV/ 1 R NG (V p-p) 2250 RL = 10kΩ EN WI D R S E T 15 NOIS 0.1 RS = 2R UTPU L O 10 A OT 10Hz T 1kHz 5 RESISTOR NOISE 0.01100 1k S1O0UkRCE R1E0S0ISkTANCE1 M(Ω) 10M 100M 00299-016 0100 1kFREQUENCY (Hz)10k 100k 00299-019 Figure 16. Total Noise Density vs. Source Resistance Figure 19. Maximum Output Swing vs. Frequency Rev. G | Page 8 of 16

OP97 80 80 GAIN PHASE 60 TA = –55°C 60 TA = –55°C N (dB) 40 PHASE TA = +125°C 90 grees) N (dB) 40 GAIN TA = +125°C 90 grees) OPEN-LOOP GAI –22000 TA = +125°CTA = –55°C 112382505 PHASE SHIFT (De OPEN-LOOP GAI –22000 TA = +125°C TA = –55°C 112382505 PHASE SHIFT (De –40 CRVSLL === ±2110M5pΩVF –40 CRVSLL === 21±10M5pΩVF –60100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 9-0200029 –60100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 00299-023 Figure 20. Open-Loop Gain, Phase vs. Frequency (COC = 0 pF) Figure 23. Open-Loop Gain, Phase vs. Frequency (COC = 100 pF) 10 1 TA = 25°C RL = 10kΩ VS = ±15V VS = ±15V 1 R1%L =T H10DkΩ TA = +125°C CL = 100pF VOUT = 3V rms µs) 0.1 TA = –55°C THD + N (%) 0.00.11 AVCL = 100 EW RATE (V/ AVCL = 10 SL 0.01 0.001 AVCL = 1 0.000110 100FREQUENCY (Ω)1k 10k 9-0210029 0.0011 OVE1R0COMPENSAT1I0O0N CAPACITOR1k (pF) 10k 00299-024 Figure 21. Total Harmonic Distortion Plus Noise vs. Frequency Figure 24. Slew Rate vs. Overcompensation 70 1000 TA = 25°C 60 VASV C=L ± =1 5+V1 TA = +125°C VOUT = 100mV p-p +EDGE 50 COC = 0pF Hz) TA = –55°C OT (%) 40 –EDGE DTH (k 100 O WI OVERSH 30 N BAND 10 20 GAI VS = ±15V CL = 20pF 10 RL = 1MΩ AV = 100 010 L1O0A0D CAPACITANCE (1pkF) 10k 00299-022 11 OVE1R0COMPENSAT1I0O0N CAPACITOR1k (pF) 10k 00299-025 Figure 22. Small Signal Overshoot vs. Capacitive Load Figure 25. Gain Bandwidth Product vs. Overcompensation Rev. G | Page 9 of 16

OP97 80 1k 60 TA =T A– 5=5 +°C25°C 100 TVAS == ±2155°CV OPEN-LOOP GAIN (dB) –2420000 TA = –55°C GAIN TPTAHA =A = +S +1E12255°C°C 91120382505 PHASE SHIFT (Degrees) OUTPUT IMPEDANCE (Ω) 01.011 AVCL = 10A0V0CL = 1 VS = ±15V 0.01 –40 CL = 20pF RL = 1MΩ –60100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 9-0260029 0.0011 10 F1R0E0QUENCY (1Hkz) 10k 100k 00299-028 Figure 26. Open-Loop Gain, Phase vs. Frequency (COC = 1000 pF) Figure 28. Closed-Loop Output Resistance vs. Frequency 80 ` TA = –55°C 60 TA = +25°C PHASE N (dB) 40 90 grees) OPEN-LOOP GAI –22000 GAIN TTAA == +–15255°C°C 112382505 PHASE SHIFT (De TA = +125°C VS = ±15V –40 CL = 20pF RL = 1MΩ –60100 1k F1R0EkQUENCY1 (0H0zk) 1M 10M 00299-027 Figure 27. Open-Loop Gain, Phase vs. Frequency (COC = 10,000 pF) Rev. G | Page 10 of 16

OP97 APPLICATION INFORMATION The OP97 is a low power alternative to the industry-standard The input pins of the OP97 are protected against large precision op amp, the OP07. The OP97 can be substituted differential voltage by back-to-back diodes. Current-limiting directly into OP07, OP77, AD725, and PM1012 sockets with resistors are not used to maintain low noise performance. If improved performance and/or less power dissipation and can be differential voltages above ±1 V are expected at the inputs, inserted into sockets conforming to the 741 pinout if nulling series resistors must be used to limit the current flow to a circuitry is not used. Generally, nulling circuitry used with earlier maximum of 10 mA. Common-mode voltages at the inputs are generation amplifiers is rendered superfluous by the extremely not restricted and may vary over the full range of the supply low offset voltage of the OP97 and can be removed without voltages used. compromising circuit performance. The OP97 requires very little operating headroom about the Extremely low bias current over the full military temperature supply rails and is specified for operation with supplies as low as range makes the OP97 attractive for use in sample-and-hold ±2 V. Typically, the common-mode range extends to within 1 V amplifiers, peak detectors, and log amplifiers that must operate of either rail. The output typically swings to within 1 V of the over a wide temperature range. Balancing input resistances is rails when using a 10 kΩ load. not necessary with the OP97. Offset voltage and TCV are OS Offset nulling is achieved utilizing the same circuitry as an degraded only minimally by high source resistance, even when OP07. A potentiometer between 5 kΩ and 100 kΩ is connected unbalanced. between Pin 1 and Pin 8 with the wiper connected to the positive supply. The trim range is between 300 μV and 850 μV, depending upon the internal trimming of the device. +V 1 RPOT = 5kΩ TO 100kΩ 8 2 7 OP97 6 3 5 4 COC –V 00299-029 Figure 29. Optional Input Offset Voltage Nulling and Overcompensation Circuit Rev. G | Page 11 of 16

OP97 AC PERFORMANCE The ac characteristics of the OP97 are highly stable over its full operating temperature range. Unity-gain small-signal response is shown in Figure 30. Extremely tolerant of capacitive loading 100 on the output, the OP97 displays excellent response even with 90 1000 pF loads (see Figure 31). In large signal applications, the input protection diodes effectively short the input to the output during the transients if the amplifier is connected in the usual unity-gain configuration. The output enters short-circuit current limit, with the flow going through the protection diodes. 10 Improved large signal transient response is obtained by using a 0% fFeiegdubrea c3k2 rsehsioswtosr tbheet wlaeregne -tshieg nouatl pruets paonnd steh eo fi ntvheer OtinPg9 i7n pinu tu. nity- 2V 20µs 00299-032 gain with a 10 kΩ feedback resistor. The unity-gain follower Figure 32. Large Signal Transient Response (AVCL = 1) circuit is shown in Figure 33. The overcompensation pin (Pin 5) can be used to increase the 10kΩ phase margin of the OP97 or to decrease gain bandwidth product at gains greater than 10. 2 6 VIN 3 OP97 VOUT 00299-033 Figure 33. Unity-Gain Follower 100 90 100 90 10 0% 20mV 5µs 00299-030 Figure 30. Small Signal Transient Response 10 (CLOAD = 100 pF, AVCL = 1) 0% 20mV 5µs 00299-034 Figure 34. Small Signal Transient Response with Overcompensation (CLOAD = 1000 pF, AVCL = 1, COC = 220 pF) 100 90 10 0% 20mV 5µs 00299-031 Figure 31. Small-Signal Transient Response (CLOAD = 1000 pF, AVCL = 1) Rev. G | Page 12 of 16

OP97 GUARDING AND SHIELDING The OP97 is an excellent choice as an output amplifier for To maintain the extremely high input impedances of the OP97, higher resolution CMOS DACs. Its tightly trimmed offset care must be taken in circuit board layout and manufacturing. voltage and minimal bias current result in virtually no Board surfaces must be kept scrupulously clean and free of degradation of linearity, even over wide temperature ranges. moisture. Conformal coating is recommended to provide a humidity barrier. Even a clean PCB can have 100 pA of leakage Figure 36 shows a versatile monitor circuit that can typically currents between adjacent traces; therefore, use guard rings sense current at any point between the ±15 V supplies. This around the inputs. Guard traces are operated at a voltage close makes it ideal for sensing current in applications such as full to that on the inputs, so that leakage currents are minimal. In bridge drivers where bidirectional current is associated with noninverting applications, connect the guard ring to the common- large common-mode voltage changes. The 114 dB CMRR of the mode voltage at the inverting input (Pin 2). In inverting appli- OP97 makes the contribution of the amplifier to common- cations, both inputs remain at ground, so that the guard trace mode error negligible, leaving only the error due to the resistor should be grounded. Make guard traces on both sides of the ratio inequality. Ideally, R2/R4 = R3/R5. circuit board. High impedance circuitry is extremely susceptible to RF pickup, R1 IL line frequency hum, and radiated noise from switching power V1 10kΩ R5 supplies. Enclosing sensitive analog sections within grounded 10kΩ RL R2 R3 shields is generally necessary to prevent excessive noise pickup. 10kΩ 10kΩ +15V Twisted-pair cable aid in rejection of line frequency hum. 2 7 OP97 6 VOUT 3 4 RFB 30IOpF 2 10kRΩ4 –15V 00299-036 6 Figure 36. Current Monitor AD7548 OP97 VOUT 3 IO DINIGPIUTTASL 00299-035 Figure 35. DAC Output Amplifier UNITY-GAIN FOLLOWER NONINVERTING AMPLIFIER 2 2 6 6 OP97 OP97 3 3 PDIP INVERTING AMPLIFIER BOTTOM VIEW 8 1 2 6 OP97 3 00299-037 Figure 37. Guard Ring Layout and Connections Rev. G | Page 13 of 16

OP97 The digitally programmable gain amplifier shown in Figure 38 +15V has 12-bit gain resolution with 10-bit gain linearity over the VIN range of −1 to −1024. The low bias current of the OP97 main- ±2.5mV TO ±10V 18 16 0.1µF RANGE DEPENDING tains this linearity, while C1 limits the noise voltage bandwidth, ON GAIN SETTING RFB allowing accurate measurement down to microvolt levels. 1 IOUT1 VREF 17 2 Table 5. 3 IOUT2 AD7541A C1 220pF DIGITAL IN GAIN (A) v 4095 −1.00024 +15V 2048 −2 1024 −4 2 0.1µF 512 −8 OP97 6 VOUT 256 −16 3 16248 −−3624 –15V 0.1µF 00299-038 32 −128 Figure 38. Precision Programmable Gain Amplifier 16 −256 R2 8 −512 20kΩ 4 −1024 5pF 2 −2048 R1 1µF 1 −4096 2kΩ 2 VIN 0 Open Loop 10kΩ AD8610 6 VOUT 10kΩ 3 Many high speed amplifiers suffer from less-than-perfect low 2 far heqiguhe nprceyc ipseiornfo, rsmlowan dceev. iAce c loikme bthine aOtiPo9n7 a amnpdl aif ifearst ceor ndseivsitcien gsu ocfh 3 OP97 6 AV = –RR21 5 as the AD8610 results in uniformly accurate performance from 0.1µF 0.1µF dbacn tod wthide thhi gphro fdreuqcut eonf c2y5 lMimHitz o. fT thhee cAirDcu8i6t1 s0h,o wwhnic ihn hFaigs uar eg a3i9n - 00299-039 accomplishes this, with the AD8610 providing high frequency Figure 39. Combination High Speed, Precision Amplifier amplification and the OP97 operating on low frequency signals and providing offset correction. Offset voltage and drift of the circuit are controlled by the OP97. 5V 100 90 10 0% 1V 2µs 00299-040 Figure 40. Combination Amplifier Transient Response Rev. G | Page 14 of 16

OP97 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRERERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 41. 8-Lead Plastic Dual In-Line Package [PDIP] P-Suffix (N-8) Dimensions shown in inches and (millimeters) 5.00(0.1968) 4.80(0.1890) 8 5 4.00 (0.1574) 6.20 (0.2441) 3.80 (0.1497) 1 4 5.80 (0.2284) 1.27 (0.0500) 0.50 (0.0196) BSC 1.75 (0.0688) 0.25 (0.0099) 45° 0.25 (0.0098) 1.35 (0.0532) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 0.10 SEATING 0.31 (0.0122) 0.25 (0.0098) 10..2470 ((00..00510507)) PLANE 0.17 (0.0067) COMPLIANTTO JEDEC STANDARDS MS-012-AA C(RINOEFNPETARRREOENNLCLTEIHN EOGSN DELSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 012407-A Figure 42. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body S-Suffix (R-8) Dimensions shown in millimeters and (inches) Rev. G | Page 15 of 16

OP97 ORDERING GUIDE Model Temperature Range Package Description Package Option OP97EP –40°C to +85°C 8-Lead PDIP N-8 OP97EPZ1 –40°C to +85°C 8-Lead PDIP N-8 OP97FP −40°C to +85°C 8-Lead PDIP N-8 OP97FPZ1 −40°C to +85°C 8-Lead PDIP N-8 OP97FS −40°C to +85°C 8-Lead SOIC_N R-8 OP97FS-REEL −40°C to +85°C 8-Lead SOIC_N R-8 OP97FS-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 OP97FSZ1 −40°C to +85°C 8-Lead SOIC_N R-8 OP97FSZ-REEL1 −40°C to +85°C 8-Lead SOIC_N R-8 OP97FSZ-REEL71 −40°C to +85°C 8-Lead SOIC_N R-8 1 Z = RoHS Compliant Part. ©1997–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00299-0-3/09(G) Rev. G | Page 16 of 16