Precision Low Noise, Low Input Bias Current Operational Amplifiers Data Sheet OP1177/OP2177/OP4177 FEATURES PIN CONFIGURATIONS Low offset voltage: 60 μV maximum Very low offset voltage drift: 0.7 μV/°C maximum NC 1 8 NC Low input bias current: 2 nA maximum NC 1 8 NC –IN 2 OP1177 7 V+ Low noise: 8 nV/√Hz typical –IN OP1177 V+ +IN 3 6 OUT +IN OUT V– 4 5 NC CLoMwR sRu, pPpSRlyR c, uarnrde nAtV: O4 >0 01 2μ0A dpBe rm aimnipmliufimer V– NC =4 NO CON5NECTNC 02627-001 NC = NO CONNECT 02627-002 Dual supply operation: ±2.5 V to ±15 V Figure 1. 8-Lead MSOP (RM Suffix) Figure 2. 8-Lead SOIC_N (R Suffix) Unity-gain stable No phase reversal OUT A 1 8 V+ Inputs internally protected beyond supply voltage –IN A 2 7 OUT B OUT A 1 8 V+ OP2177 AWPirePlLesICs bAaTsIeO sNtaSti on control circuits +–IINNV AA– 4OP21775 –O+IIUNNT BB B 02627-003 +INV A– 34 65 +–IINN BB 02627-004 Optical network control circuits Figure 3. 8-Lead MSOP (RM Suffix) Figure 4. 8-Lead SOIC_N (R Suffix) Instrumentation Sensors and controls OUT A 1 14 OUT D Thermocouples –IN A 2 13 –IN D Resistor thermal detectors (RTDs) +IN A 3 12 +IN D OP4177 Strain bridges V+ 4 11 V– OUT A 1 14 OUT D Shunt current measurements +IN B 5 10 +IN C –IN A –IN D +IN A +IN D Precision filters –IN B 6 9 –IN C V+ OP4177 V– OUT B 7 8 OUT C 02627-005 O+–UIINNT BBB 7 8 –O+IIUNNT CC C 02627-006 Figure 5. 14-Lead SOIC_N (R Suffix) Figure 6. 14-Lead TSSOP (RU Suffix) GENERAL DESCRIPTION The OPx177 family consists of very high precision, single, dual, performance in the SOIC package. MSOP and TSSOP are and quad amplifiers featuring extremely low offset voltage and available in tape and reel only. drift, low input bias current, low noise, and low power consump- The OPx177 family offers the widest specified temperature tion. Outputs are stable with capacitive loads of over 1000 pF range of any high precision amplifier in surface-mount packaging. with no external compensation. Supply current is less than 500 μA All versions are fully specified for operation from −40°C to per amplifier at 30 V. Internal 500 Ω series resistors protect the +125°C for the most demanding operating environments. inputs, allowing input signal levels several volts beyond either Applications for these amplifiers include precision diode supply without phase reversal. power measurement, voltage and current level setting, and Unlike previous high voltage amplifiers with very low offset level detection in optical and wireless transmission systems. voltages, the OP1177 (single) and OP2177 (dual) amplifiers Additional applications include line-powered and portable are available in tiny 8-lead surface-mount MSOP and 8-lead instrumentation and controls—thermocouple, RTD, strain- narrow SOIC packages. The OP4177 (quad) is available in bridge, and other sensor signal conditioning—and precision filters. TSSOP and 14-lead narrow SOIC packages. Moreover, specified performance in the MSOP and the TSSOP is identical to Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2001–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

OP1177/OP2177/OP4177 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Overload Recovery Time .......................................................... 15 Applications ....................................................................................... 1 THD + Noise ............................................................................... 16 Pin Configurations ........................................................................... 1 Capacitive Load Drive ............................................................... 16 General Description ......................................................................... 1 Stray Input Capacitance Compensation .................................. 17 Revision History ............................................................................... 2 Reducing Electromagnetic Interference .................................. 17 Specifications ..................................................................................... 3 Proper Board Layout .................................................................. 18 Electrical Characteristics ............................................................. 3 Difference Amplifiers ................................................................ 18 Electrical Characteristics ............................................................. 4 A High Accuracy Thermocouple Amplifier ........................... 19 Absolute Maximum Ratings ............................................................ 5 Low Power Linearized RTD ...................................................... 19 Thermal Resistance ...................................................................... 5 Single Operational Amplifier Bridge ....................................... 20 ESD Caution .................................................................................. 5 Realization of Active Filters .......................................................... 21 Typical Performance Characteristics ............................................. 6 Band-Pass KRC or Sallen-Key Filter ........................................ 21 Functional Description .................................................................. 14 Channel Separation .................................................................... 21 Total Noise-Including Source Resistors................................... 14 References on Noise Dynamics and Flicker Noise ............... 21 Gain Linearity ............................................................................. 14 Outline Dimensions ....................................................................... 22 Input Overvoltage Protection ................................................... 15 Ordering Guide .......................................................................... 24 Output Phase Reversal ............................................................... 15 Settling Time ............................................................................... 15 REVISION HISTORY 9/2018—Rev. G to Rev. H Changes to Figure 64 ...................................................................... 19 Changes to Ordering Guide .......................................................... 24 Changes to Figure 65 and Figure 66 ............................................ 20 Changes to Figure 67 and Figure 68 ............................................ 21 11/2009—Rev. F to Rev. G Removed SPICE Model Section ................................................... 21 Changes to Figure 64 ...................................................................... 19 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 24 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 22 4/2004—Rev. B to Rev. C 5/2009—Rev. E to Rev. F Changes to Ordering Guide ............................................................. 4 Changes to Figure 64 ...................................................................... 19 Changes to TPC 6 .............................................................................. 5 Changes to Ordering Guide .......................................................... 24 Changes to TPC 26 ............................................................................ 7 Updated Outline Dimensions ....................................................... 17 10/2007—Rev. D to Rev. E Changes to General Description .................................................... 1 4/2002—Rev. A to Rev. B Changes to Table 4 ............................................................................ 5 Added OP4177 ......................................................................... Global Updated Outline Dimensions ....................................................... 22 Edits to Specifications ....................................................................... 2 Edits to Electrical Characteristics Headings .................................. 4 7/2006—Rev. C to Rev. D Edits to Ordering Guide ................................................................... 4 Changes to Table 4 ............................................................................ 5 Changes to Figure 51 ...................................................................... 14 11/2001—Rev. 0 to Rev. A Changes to Figure 52 ...................................................................... 15 Edit to Features .................................................................................. 1 Changes to Figure 54 ...................................................................... 16 Edits to TPC 6 ................................................................................... 5 Changes to Figure 58 to Figure 61 ................................................ 17 Changes to Figure 62 and Figure 63 ............................................. 18 7/2001—Revision 0: Initial Version Rev. H | Page 2 of 24

Data Sheet OP1177/OP2177/OP4177 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = ±5.0 V, V = 0 V, T = 25°C, unless otherwise noted. S CM A Table 1. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit INPUT CHARACTERISTICS Offset Voltage OP1177 V 15 60 μV OS OP2177/OP4177 V 15 75 μV OS OP1177/OP2177 V −40°C < T < +125°C 25 100 μV OS A OP4177 V −40°C < T < +125°C 25 120 μV OS A Input Bias Current I −40°C < T < +125°C −2 +0.5 +2 nA B A Input Offset Current I −40°C < T < +125°C −1 +0.2 +1 nA OS A Input Voltage Range −3.5 +3.5 V Common-Mode Rejection Ratio CMRR V = −3.5 V to +3.5 V 120 126 dB CM −40°C < T < +125°C 118 125 dB A Large Signal Voltage Gain A R = 2 kΩ, V = −3.5 V to +3.5 V 1000 2000 V/mV VO L O Offset Voltage Drift OP1177/OP2177 ΔV /ΔT −40°C < T < +125°C 0.2 0.7 μV/°C OS A OP4177 ΔV /ΔT −40°C < T < +125°C 0.3 0.9 μV/°C OS A OUTPUT CHARACTERISTICS Output Voltage High V I = 1 mA, −40°C < T < +125°C +4 +4.1 V OH L A Output Voltage Low V I = 1 mA, −40°C < T < +125°C −4.1 −4 V OL L A Output Current I V < 1.2 V ±10 mA OUT DROPOUT POWER SUPPLY Power Supply Rejection Ratio OP1177 PSRR V = ±2.5 V to ±15 V 120 130 dB S −40°C < T < +125°C 115 125 dB A OP2177/OP4177 PSRR V = ±2.5 V to ±15 V 118 121 dB S −40°C < T < +125°C 114 120 dB A Supply Current per Amplifier I V = 0 V 400 500 μA SY O −40°C < T < +125°C 500 600 μA A DYNAMIC PERFORMANCE Slew Rate SR R = 2 kΩ 0.7 V/μs L Gain Bandwidth Product GBP 1.3 MHz NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.4 μV p-p n Voltage Noise Density e f = 1 kHz 7.9 8.5 nV/√Hz n Current Noise Density i f = 1 kHz 0.2 pA/√Hz n MULTIPLE AMPLIFIERS CHANNEL SEPARATION C DC 0.01 μV/V S f = 100 kHz −120 dB 1 Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as typical give unrealistically low estimates for parameters that can have both positive and negative values. Rev. H | Page 3 of 24

OP1177/OP2177/OP4177 Data Sheet ELECTRICAL CHARACTERISTICS V = ±15 V, V = 0 V, T = 25°C, unless otherwise noted. S CM A Table 2. Parameter Symbol Conditions Min Typ1 Max Unit INPUT CHARACTERISTICS Offset Voltage OP1177 V 15 60 μV OS OP2177/OP4177 V 15 75 μV OS OP1177/OP2177 V −40°C < T < +125°C 25 100 μV OS A OP4177 V −40°C < T < +125°C 25 120 μV OS A Input Bias Current I −40°C < T < +125°C −2 +0.5 +2 nA B A Input Offset Current I −40°C < T < +125°C −1 +0.2 +1 nA OS A Input Voltage Range −13.5 +13.5 V Common-Mode Rejection Ratio CMRR V = −13.5 V to +13.5 V, CM −40°C < T < +125°C 120 125 dB A Large Signal Voltage Gain A R = 2 kΩ, V = –13.5 V to +13.5 V 1000 3000 V/mV VO L O Offset Voltage Drift OP1177/OP2177 ΔV /ΔT −40°C < T < +125°C 0.2 0.7 μV/°C OS A OP4177 ΔV /ΔT −40°C < T < +125°C 0.3 0.9 μV/°C OS A OUTPUT CHARACTERISTICS Output Voltage High V I = 1 mA, −40°C < T < +125°C +14 +14.1 V OH L A Output Voltage Low V I = 1 mA, −40°C < T < +125°C −14.1 −14 V OL L A Output Current I V < 1.2 V ±10 mA OUT DROPOUT Short-Circuit Current I ±25 mA SC POWER SUPPLY Power Supply Rejection Ratio OP1177 PSRR V = ±2.5 V to ±15 V 120 130 dB S −40°C < T < +125°C 115 125 dB A OP2177/OP4177 PSRR V = ±2.5 V to ±15 V 118 121 dB S −40°C < T < +125°C 114 120 dB A Supply Current per Amplifier I V = 0 V 400 500 μA SY O −40°C < T < +125°C 500 600 μA A DYNAMIC PERFORMANCE Slew Rate SR R = 2 kΩ 0.7 V/μs L Gain Bandwidth Product GBP 1.3 MHz NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 0.4 μV p-p n Voltage Noise Density e f = 1 kHz 7.9 8.5 nV/√Hz n Current Noise Density i f = 1 kHz 0.2 pA/√Hz n MULTIPLE AMPLIFIERS CHANNEL SEPARATION C DC 0.01 μV/V S f = 100 kHz −120 dB 1 Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as typical give unrealistically low estimates for parameters that can have both positive and negative values. Rev. H | Page 4 of 24

Data Sheet OP1177/OP2177/OP4177 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. θ is specified for the worst-case conditions, that is, a device Parameter Rating JA soldered in a circuit board for surface-mount packages. Supply Voltage 36 V Input Voltage V to V S− S+ Table 4. Thermal Resistance Differential Input Voltage ±Supply Voltage Package Type1 θ θ Unit JA JC Storage Temperature Range 8-Lead MSOP (RM-8) 190 44 °C/W R, RM, and RU Packages −65°C to +150°C 8-Lead SOIC_N (R-8) 158 43 °C/W Operating Temperature Range 14-Lead SOIC_N (R-14) 120 36 °C/W OP1177/OP2177/OP4177 −40°C to +125°C 14-Lead TSSOP (RU-14) 240 43 °C/W Junction Temperature Range R, RM, and RU Packages −65°C to +150°C 1 MSOP is available in tape and reel only. Lead Temperature, Soldering (10 sec) 300°C Stresses at or above those listed under Absolute Maximum ESD CAUTION Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. H | Page 5 of 24

OP1177/OP2177/OP4177 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 50 1.8 VSY = ±15V VSY = ±15V 45 1.6 TA = 25°C 40 1.4 S F AMPLIFIER332505 VOLTAGE (V)11..20 ER O20 PUT 0.8 SOURCE NUMB15 ΔOUT0.6 SINK 10 0.4 5 0.2 0–40 –30 –2I0NPUT– 1O0FFSE0TVOLTA1G0E (µV2)0 30 40 02627-007 00.001 0.01 LOAD CUR0.R1ENT (mA) 1 10 02627-010 Figure 7. Input Offset Voltage Distribution Figure 10. Output Voltage to Supply Rail vs. Load Current 90 3 VSY = ±15V VSY = ±15V 80 2 S70 A) R n LIFIE60 ENT ( 1 P R M50 R A U ER OF 40 BIAS C 0 MB30 UT –1 U P N N 20 I –2 10 0 0.05 0.I1N5PUT O0F.F2S5ET VO0L.3T5AGE D0R.4IF5T (µV/0°C.5)5 0.65 02627-008 –3–50 0 TEMPERA50TURE (°C) 100 150 02627-011 Figure 8. Input Offset Voltage Drift Distribution Figure 11. Input Bias Current vs. Temperature 140 60 270 VSY = ±15V VSY = ±15V 120 50 RCLL == ∞0 225 S 40 180 NUMBER OF AMPLIFIER108640000 OPEN-LOOP GAIN (dB)3210000 GAIN PHASE 19403055 PHASE SHIFT (Degrees) 20 –10 –45 0 0 0.1 IN0.P2UT BI0A.3S CUR0R.4ENT (n0A.5) 0.6 0.7 02627-009 –20100k FREQUE1MNCY (Hz) 10M–90 02627-012 Figure 9. Input Bias Current Distribution Figure 12. Open-Loop Gain and Phase Shift vs. Frequency Rev. H | Page 6 of 24

Data Sheet OP1177/OP2177/OP4177 120 VSY = ±15V VSY = ±15V 100 VIN = 4mV p-p CL = 1,000pF CL = 0 RL = 2kΩ 80 RL =∞ VIN = 100mV dB) 60 V) AV = 1 GAIN ( 40 AV = 100 mV/DI P AV = 10 00 OO 20 E (1 D-L 0 AG SE AV = 1 LT LO–20 VO C GND –40 –60 –801k 10k F1R00EkQUENCY (1HMz) 10M 100M 02627-013 TIME (100µs/DIV) 02627-016 Figure 13. Closed-Loop Gain vs. Frequency Figure 16. Small Signal Transient Response 500 50 450 VVSINY == 5±01m5VV p-p 45 VRSLY = = 2 k±Ω15V 400 %) 40 VIN = 100mV p-p DANCE (Ω)335000 AV = 10 AV = 1 VERSHOOT ( 3350 UT IMPE225000 AV = 100 GNAL O 2250 +OS UTP150 L SI 15 O AL 100 SM 10 –OS 50 5 0100 1k FREQ1U0kENCY (Hz)100k 1M 02627-014 01 10 CAPACIT1A00NCE (pF) 1k 10k 02627-017 Figure 14. Output Impedance vs. Frequency Figure 17. Small Signal Overshoot vs. Load Capacitance VSY = ±15V VSY = ±15V CL = 300pF RL = 10kΩ RVILN == 24kVΩ 0V VAIVN == –210000mV OUTPUT AV = 1 V) DI –15V V/ 1 E ( G A T OL +200mV V GND INPUT 0V TIME (100µs/DIV) 02627-015 TIME (10µs/DIV) 02627-018 Figure 15. Large Signal Transient Response Figure 18. Positive Overvoltage Recovery Rev. H | Page 7 of 24

OP1177/OP2177/OP4177 Data Sheet VSY = ±15V 15V OUTPUT 0V VSY = ±15V V) RALV == 1–01k0Ω0 µV/DI VIN = 200mV 0.2 (E S 0V NOI V –200mV INPUT TIME (4µs/DIV) 02627-019 TIME (1s/DIV) 02627-022 Figure 19. Negative Overvoltage Recovery Figure 22. 0.1 Hz to 10 Hz Input Voltage Noise 140 18 VSY = ±15V VSY = ±15V 120 Hz)16 √ V/14 100 n Y ( B) 80 NSIT12 d E CMRR ( 60 OISE D10 N 8 E 40 TAG 6 L O 20 V 4 010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 02627-020 20 50 F1R0E0QUENCY 1(H50z) 200 250 02627-023 Figure 20. CMRR vs. Frequency Figure 23. Voltage Noise Density vs. Frequency 140 35 VSY = ±15V VSY = ±15V 120 30 mA) +ISC 100 T (25 –PSRR REN –ISC PSRR (dB) 8600 +PSRR RCUIT CUR2105 CI 40 RT-10 O H S 20 5 010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 02627-021 0–50 0 TEMPERA50TURE (°C) 100 150 02627-024 Figure 21. PSRR vs. Frequency Figure 24. Short-Circuit Current vs. Temperature Rev. H | Page 8 of 24

Data Sheet OP1177/OP2177/OP4177 14.40 133 VSY = ±15V 132 VSY = ±15V 14.35 V) 131 G (14.30 WIN +VOH 130 E S14.25 B)129 OLTAG14.20 –VOL MRR (d128 V C127 T 14.15 U P 126 T U14.10 O 125 14.05 124 14.00–50 0 TEMPERA50TURE (°C) 100 150 02627-025 123–50 0 TEMPE5R0ATURE (°C) 100 150 02627-028 Figure 25. Output Voltage Swing vs. Temperature Figure 28. CMRR vs. Temperature 0.5 133 VSY = ±15V VSY = ±15V 0.4 132 V) 0.3 131 µ GE ( 0.2 130 A ET VOLT 0.10 RR (dB)112289 S S F –0.1 P127 F O Δ –0.2 126 –0.3 125 –0.4 124 –0.50 20TIME FR40OM POW60ER SUP8P0LY TUR1N00-ON (Se1c2)0 140 02627-026 123–50 0 TEMPE5R0ATURE (°C) 100 150 02627-029 Figure 26. Warm-Up Drift Figure 29. PSRR vs. Temperature 18 50 VSY = ±15V VSY = ±5V 16 45 V) 14 40 µ S LTAGE ( 12 PLIFIER 3305 O 10 M V A T F 25 FFSE 8 ER O 20 PUT O 6 NUMB 15 N 4 I 10 2 5 0–50 0 TEMPE5R0ATURE (°C) 100 150 02627-027 0–40 –30 –2I0NPUT– 1O0FFSET0 VOLT1A0GE (µ2V0) 30 40 02627-030 Figure 27. Input Offset Voltage vs. Temperature Figure 30. Input Offset Voltage Distribution Rev. H | Page 9 of 24

OP1177/OP2177/OP4177 Data Sheet 1.4 500 1.2 VTASY = = 2 5±°5CV 450 VVSINY == 5±05mVV p-p 400 PUT VOLTAGE (V)001...860 SSINOKURCE UT IMPEDANCE (Ω)332250500000 T P ∆OU0.4 OUT150 AV = 100 AV = 1 100 AV = 10 0.2 50 00.001 0.01 LOAD C0U.1RRENT (mA) 1 10 02627-031 0100 1k FREQ1U0kENCY (Hz) 100k 1M 02627-034 Figure 31. Output Voltage to Supply Rail vs. Load Current Figure 34. Output Impedance vs. Frequency 60 270 VSY = ±5V VSY = ±5V 50 CRLL == ∞0 225 CRLL == 320k0ΩpF 40 180 VIN = 1V N (dB) 30 135grees) DIV) AV = 1 AI GAIN De V/ OPEN-LOOP G 21000 PHASE 94005 PHASE SHIFT ( VOLTAGE (1GND –10 –45 –21000k FREQUE1NMCY (Hz) 10M–90 02627-032 TIME (100µs/DIV) 02627-035 Figure 32. Open-Loop Gain and Phase Shift vs. Frequency Figure 35. Large Signal Transient Response 120 VSY = ±5V VSY = ±5V 100 VIN = 4mV p-p CL = 1,000pF GAIN (dB) 864000 AV = 100 CRLL == ∞0 mV/DIV) RVAILVN === 211k0Ω0mV OOP 20 AV = 10 E (50 L G D- 0 A LOSE–20 AV = 1 VOLT C GND –40 –60 –801k 10k F1R00EkQUENCY (1HMz) 10M 100M 02627-033 TIME (10µs/DIV) 02627-036 Figure 33. Closed-Loop Gain vs. Frequency Figure 36. Small Signal Transient Response Rev. H | Page 10 of 24

Data Sheet OP1177/OP2177/OP4177 50 %) 4450 VRVSILNY = == 2 1k±0Ω50VmV INPUT VARSVL === ±1150VkΩ T ( SHOO 35 DIV) OVER 3205 E (2V/GND AL +OS AG SIGN 20 VOLT L 15 L A M 10 S –OS OUTPUT 5 01 10 CAPACIT1A00NCE (pF) 1k 10k 02627-037 TIME (200µs/DIV) 02627-040 Figure 37. Small Signal Overshoot vs. Load Capacitance Figure 40. No Phase Reversal 140 VSY = ±5V VSY = ±5V RL = 10kΩ 120 AV = –100 OUTPUT 0V VIN = 200mV 100 –15V B) 80 d R ( R M 60 C +200mV 40 INPUT 0V 20 TIME (4µs/DIV) 02627-038 010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 02627-041 Figure 38. Positive Overvoltage Recovery Figure 41. CMRR vs. Frequency 200 VSY = ±5V VSY = ±5V RL = 10kΩ 180 AV = –100 160 5V OUTPUT VIN = 200mV 140 0V B) 120 d R ( 100 R –PSRR INPUT S P 80 0V 60 +PSRR 40 –200mV 20 TIME (4µs/DIV) 02627-039 010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 02627-042 Figure 39. Negative Overvoltage Recovery Figure 42. PSRR vs. Frequency Rev. H | Page 11 of 24

OP1177/OP2177/OP4177 Data Sheet 4.40 VSY = ±5V VSY = ±5V 4.35 V) G (4.30 2µV/DIV) GE SWIN4.25 +VOH –VOL (0.SE OLTA4.20 VNOI UT V4.15 P T U4.10 O 4.05 TIME (1s/DIV) 02627-043 4.00–50 0 TEMPERA50TURE (°C) 100 150 02627-046 Figure 43. 0.1 Hz to 10 Hz Input Voltage Noise Figure 46. Output Voltage Swing vs. Temperature 18 25 VSY = ±5V VSY = ±5V 16 √Hz) V) 20 Y (nV/14 GE (µ OISE DENSIT1120 FSET VOLTA 1105 N 8 F GE T O OLTA 6 INPU 5 V 4 20 50 F1R0E0QUENCY 1(H50z) 200 250 02627-044 0–50 0 TEMPE5R0ATURE (°C) 100 150 02627-047 Figure 44. Voltage Noise Density vs. Frequency Figure 47. Input Offset Voltage vs. Temperature 35 600 VSY = ±5V 30 500 mA) +ISC VSY = ±15V T CURRENT (2250 –ISC URRENT (µA) 340000 VSY = ±5V CUI15 Y C R L RT-CI10 SUPP 200 O H S 100 5 0–50 0 TEMPERA50TURE (°C) 100 150 02627-045 0–50 0 TEMPE5R0ATURE (°C) 100 150 02627-048 Figure 45. Short-Circuit Current vs. Temperature Figure 48. Supply Current vs. Temperature Rev. H | Page 12 of 24

Data Sheet OP1177/OP2177/OP4177 450 0 TA = 25°C 400 –20 A)350 dB) –40 T (µ300 ON ( Y CURREN220500 SEPARATI ––6800 SUPPL150 ANNEL –100 H–120 100 C 50 –140 00 5 10 SUP1P5LY VOL2T0AGE (V2)5 30 35 02627-049 –16010 100 FR1EkQUENCY 1(H0zk) 100k 1M 02627-050 Figure 49. Supply Current vs. Supply Voltage Figure 50. Channel Separation vs. Frequency Rev. H | Page 13 of 24

OP1177/OP2177/OP4177 Data Sheet FUNCTIONAL DESCRIPTION For R < 3.9 kΩ, e dominates and The OPx177 series is the fourth generation of Analog Devices, S n Inc., industry-standard OP07 amplifier family. OPx177 is a high e ≈ e n,TOTAL n precision, low noise operational amplifier with a combination of For 3.9 kΩ < R < 412 kΩ, voltage noise of the amplifier, the S extremely low offset voltage and very low input bias currents. current noise of the amplifier translated through the source Unlike JFET amplifiers, the low bias and offset currents are resistor, and the thermal noise from the source resistor all relatively insensitive to ambient temperatures, even up to 125°C. contribute to the total noise. Analog Devices proprietary process technology and linear design For R > 412 kΩ, the current noise dominates and S expertise has produced a high voltage amplifier with superior e ≈ iR performance to the OP07, OP77, and OP177 in a tiny MSOP n,TOTAL n S 8­lead package. Despite its small size, the OPx177 offers numerous The total equivalent rms noise over a specific bandwidth is improvements, including low wideband noise, very wide input expressed as and output voltage range, lower input bias current, and complete   e  e BW freedom from phase inversion. n n,TOTAL where BW is the bandwidth in hertz. OPx177 has a specified operating temperature range as wide as any similar device in a plastic surface-mount package. This is The preceding analysis is valid for frequencies larger than 50 Hz. increasingly important as PCB and overall system sizes continue When considering lower frequencies, flicker noise (also known to shrink, causing internal system temperatures to rise. Power as 1/f noise) must be taken into account. consumption is reduced by a factor of four from the OP177, and For a reference on noise calculations, refer to the Band-Pass bandwidth and slew rate increase by a factor of two. The low KRC or Sallen-Key Filter section. power dissipation and very stable performance vs. temperature GAIN LINEARITY also act to reduce warmup drift errors to insignificant levels. Open-loop gain linearity under heavy loads is superior to compet- Gain linearity reduces errors in closed-loop configurations. The itive parts, such as the OPA277, improving dc accuracy and straighter the gain curve, the lower the maximum error over the reducing distortion in circuits with high closed-loop gains. input signal range. This is especially true for circuits with high Inputs are internally protected from overvoltage conditions closed-loop gains. referenced to either supply rail. The OP1177 has excellent gain linearity even with heavy loads, Like any high performance amplifier, maximum performance is as shown in Figure 51. Compare its performance to the OPA277, achieved by following appropriate circuit and PCB guidelines. shown in Figure 52. Both devices are measured under identical The following sections provide practical advice on getting the conditions, with RL = 2 kΩ. The OP2177 (dual) has virtually no most out of the OPx177 under a variety of application conditions. distortion at lower voltages. Compared to the OPA277 at several supply voltages and various loads, OP1177 performance far TOTAL NOISE-INCLUDING SOURCE RESISTORS exceeds that of its counterpart. The low input current noise and input bias current of the OPx177 make it useful for circuits with substantial input source resistance. VSY = ±15V Input offset voltage increases by less than 1 μV maximum per RL = 2kΩ 500 Ω of source resistance. The total noise density of the OPx177 is e  e 2i R  24kTR DIV) OP1177 n,TOTAL n n S S V/ µ 0 1 where: ( e is the input voltage noise density. n i is the input current noise density. n R is the source resistance at the noninverting terminal. S k is Boltzmann’s constant (1.38 × 10−23 J/K). Tin ids etghree aems Cbieelnsitu tse)m. perature in Kelvin (T = 273 + temperature (5V/DIV) 02627-051 Figure 51. Gain Linearity Rev. H | Page 14 of 24

Data Sheet OP1177/OP2177/OP4177 VSY = ±15V VSY= 10V RL = 2kΩ AV= 1 VIN V) DI 0µV/DIV) OPA277 AGE (5V/ VOUT (1 LT O V (5V/DIV) 02627-052 TIME (400µs/DIV) 02627-053 Figure 52. Gain Linearity Figure 53. No Phase Reversal INPUT OVERVOLTAGE PROTECTION SETTLING TIME When input voltages exceed the positive or negative supply Settling time is defined as the time it takes an amplifier output voltage, most amplifiers require external resistors to protect to reach and remain within a percentage of its final value after them from damage. application of an input pulse. It is especially important in measure- ment and control circuits in which amplifiers buffer ADC inputs The OPx177 has internal protective circuitry that allows voltages as or DAC outputs. high as 2.5 V beyond the supplies to be applied at the input of either terminal without any harmful effects. To minimize settling time in amplifier circuits, use proper bypassing of power supplies and an appropriate choice of circuit Use an additional resistor in series with the inputs if the voltage components. Resistors should be metal film types, because they exceeds the supplies by more than 2.5 V. The value of the resistor have less stray capacitance and inductance than their wire-wound can be determined from the formula counterparts. Capacitors should be polystyrene or polycarbonate VIN VS  5mA types to minimize dielectric absorption. R 500  S The leads from the power supply should be kept as short as With the OPx177 low input offset current of <1 nA maximum, possible to minimize capacitance and inductance. The OPx177 placing a 5 kΩ resistor in series with both inputs adds less than has a settling time of about 45 μs to 0.01% (1 mV) with a 10 V 5 μV to input offset voltage and has a negligible impact on the step applied to the input in a noninverting unity gain. overall noise performance of the circuit. OVERLOAD RECOVERY TIME 5 kΩ protects the inputs to more than 27 V beyond either supply. Overload recovery is defined as the time it takes the output Refer to the THD + Noise section for additional information on voltage of an amplifier to recover from a saturated condition to noise vs. source resistance. its linear response region. A common example is one in which OUTPUT PHASE REVERSAL the output voltage demanded by the transfer function of the circuit lies beyond the maximum output voltage capability of Phase reversal is defined as a change of polarity in the amplifier the amplifier. A 10 V input applied to an amplifier in a closed- transfer function. Many operational amplifiers exhibit phase loop gain of 2 demands an output voltage of 20 V. This is beyond reversal when the voltage applied to the input is greater than the the output voltage range of the OPx177 when operating at ±15 V maximum common-mode voltage. In some instances, this can supplies and forces the output into saturation. cause permanent damage to the amplifier. In feedback loops, it can result in system lockups or equipment damage. The OPx177 Recovery time is important in many applications, particularly is immune to phase reversal problems even at input voltages where the operational amplifier must amplify small signals in beyond the supplies. the presence of large transient voltages. Rev. H | Page 15 of 24

OP1177/OP2177/OP4177 Data Sheet R2 Figure 56 is a scope shot of the output of the OPx177 in response 100kΩ to a 400 mV pulse. The load capacitance is 2 nF. The circuit is V+ configured in positive unity gain, the worst-case condition for R1 1kΩ 2 7 stability. 200mV + OP1177 6 VOUT As shown in Figure 58, placing an R-C network parallel to the – 3 10kΩ load capacitance (C) allows the amplifier to drive higher values 4V– 02627-054 of CL without causinLg oscillation or excessive overshoot. Figure 54. Test Circuit for Overload Recovery Time There is no ringing, and overshoot is reduced from 27% to 5% using the snubber network. Figure 18 shows the positive overload recovery time of the OP1177. The output recovers in less than 4 μs after being Optimum values for RS and CS are tabulated in Table 5 for several overdriven by more than 100%. capacitive loads, up to 200 nF. Values for other capacitive loads can be determined experimentally. The negative overload recovery of the OP1177 is 1.4 μs, as seen in Figure 19. Table 5. Optimum Values for Capacitive Loads THD + NOISE CL RS CS 10 nF 20 Ω 0.33 μF The OPx177 has very low total harmonic distortion. This indicates 50 nF 30 Ω 6.8 nF excellent gain linearity and makes the OPx177 a great choice for 200 nF 200 Ω 0.47 μF high closed-loop gain precision circuits. Figure 55 shows that the OPx177 has approximately 0.00025% distortion in unity gain, the worst-case configuration for distortion. VSY = ±5V 0.1 RL = 10kΩ VSY = ±15V CL = 2nF RL = 10kΩ BW = 22kHz V) DI V/ m 0.01 0 0 THD + N (%) VOLTAGE (2GND0 0.001 0.000120 100 FREQUENCY (Hz) 1k 6k 02627-055 Figure 56. CapacitivTe ILMoEa (d1 0Dµrsi/vDeIV W)ithout Snubber 02627-056 Figure 55. THD + N vs. Frequency CAPACITIVE LOAD DRIVE VSY = ±5V RL = 10kΩ OPx177 is inherently stable at all gains and capable of driving RS = 200Ω large capacitive loads without oscillation. With no external CL = 2nF compensation, the OPx177 safely drives capacitive loads up to V) CS = 0.47µF DI 1000 pF in any configuration. As with virtually any amplifier, mV/ 0 driving larger capacitive loads in unity gain requires additional 20 circuitry to assure stability. GE ( LTAGND In this case, a snubber network is used to prevent oscillation O V and reduce the amount of overshoot. A significant advantage of this method is that it does not reduce the output swing because the Resistor R is not inside the feedback loop. S TIME (10µs/DIV) 02627-057 Figure 57. Capacitive Load Drive with Snubber Rev. H | Page 16 of 24

Data Sheet OP1177/OP2177/OP4177 Cf V+ 2 7 R1 R2 6 OP1177 VOUT 400mV +– 3 4V– RCSS CL 02627-058 –+ V1 Ct 2 OP17V1+77 6 VOUT Figure 58. Snubber Network Configuration 3 Cbaanudtiwonid: tThh ine dsnuucebdb ebry t leacrhgne icqaupea ccaitnivneo lto raedcso.v er the loss of 4V– 02627-060 Figure 60. Compensation Using Feedback Capacitor STRAY INPUT CAPACITANCE COMPENSATION REDUCING ELECTROMAGNETIC INTERFERENCE The effective input capacitance in an operational amplifier A number of methods can be utilized to reduce the effects of circuit (C) consists of three components. These are the internal t EMI on amplifier circuits. differential capacitance between the input terminals, the internal common-mode capacitance of each input to ground, and the In one method, stray signals on either input are coupled to the external capacitance including parasitic capacitance. In the opposite input of the amplifier. The result is that the signal is circuit in Figure 59, the closed-loop gain increases as the signal rejected according to the CMRR of the amplifier. frequency increases. This is usually achieved by inserting a capacitor between the inputs The transfer function of the circuit is of the amplifier, as shown in Figure 61. However, this method can also cause instability, depending on the value of capacitance. 1 RR21 1sCtR1 R1 R2 indicating a zero at V+ + R2R1 1 V1 2 7 s  R2R1C  2 R1/R2 C – C OP1177 6 VOUT t t 3 Dtheep celnodseind-gl ooonp t hgea ivna cluaen obfe R w1e alln bde Rlo2w, tthhee ccurotosfsfo fvreerq fureenqcuye nocf y. 4V– 02627-061 In this case, the phase margin (Φ ) can be severely degraded, Figure 61. EMI Reduction M resulting in excessive ringing or even oscillation. Placing a resistor in series with the capacitor (see Figure 62) A simple way to overcome this problem is to insert a capacitor increases the dc loop gain and reduces the output error. Positioning in the feedback path, as shown in Figure 60. the breakpoint (introduced by R-C) below the secondary pole of the operational amplifier improves the phase margin and, The resulting pole can be positioned to adjust the phase margin. therefore, stability. Setting C = (R1/R2) C achieves a phase margin of 90°. f t R can be chosen independently of C for a specific phase margin R1 R2 according to the formula V+ R2  R2 + V1 2 7 R  a  jf2  1  R1 – Ct OP1177 6 VOUT where: 3 a is the open-loop gain of the amplifier. 4V– 02627-059 f2 is the frequency at which the phase of a = ΦM − 180°. Figure 59. Stray Input Capacitance R2 V+ R1 2 7 + V1 R OP1177 6 VOUT – C 3 4V– 02627-062 Figure 62. Compensation Using Input R-C Network Rev. H | Page 17 of 24

OP1177/OP2177/OP4177 Data Sheet PROPER BOARD LAYOUT In the single instrumentation amplifier (see Figure 63), where The OPx177 is a high precision device. To ensure optimum R4 R2 = performance at the PCB level, care must be taken in the design R3 R1 of the board layout. V = R2 (V −V ) To avoid leakage currents, the surface of the board should be O R1 2 1 kept clean and free of moisture. Coating the surface creates a a mismatch between the ratio R2/R1 and R4/R3 causes the barrier to moisture accumulation and helps reduce parasitic common-mode rejection ratio to be reduced. resistance on the board. To better understand this effect, consider that, by definition, Keeping supply traces short and properly bypassing the power A supplies minimizes power supply disturbances due to output CMRR = DM current variation, such as when driving an ac signal into a heavy ACM load. Bypass capacitors should be connected as closely as possible where ADM is the differential gain and ACM is the common- to the device supply pins. Stray capacitances are a concern at the mode gain. outputs and the inputs of the amplifier. It is recommended that V V signal traces be kept at least 5 mm from supply lines to A = O andA = O minimize coupling. DM VDIFF CM VCM A variation in temperature across the PCB can cause a mismatch in V = V −V andV = 1 (V +V ) the Seebeck voltages at solder joints and other points where dissi- DIFF 1 2 CM 2 1 2 milar metals are in contact, resulting in thermal voltage errors. To For this circuit to act as a difference amplifier, its output must minimize these thermocouple effects, orient resistors so heat be proportional to the differential input signal. sources warm both ends equally. Input signal paths should contain From Figure 63, matching numbers and types of components, where possible to match the number and type of thermocouple junctions. For  R2 example, dummy components such as zero value resistors can R2 1+ R1 V = −  V +  V be used to match real resistors in the opposite input path. O R1 1  R3 2 Matching components should be located in close proximity and 1+R4 should be oriented in the same manner. Ensure leads are of equal length so that thermal conduction is in equilibrium. Keep heat Arranging terms and combining the previous equations yields sources on the PCB as far away from amplifier input circuitry as R4R1+R3R2+2R4R2 CMRR = (1) is practical. 2R4R1−2R2R3 The use of a ground plane is highly recommended. A ground The sensitivity of CMRR with respect to the R1 is obtained by plane reduces EMI noise and also helps to maintain a constant taking the derivative of CMRR, in Equation 1, with respect to R1. temperature across the circuit board. δCMRR δ  R1R4 2R2R4+R2R3  DIFFERENCE AMPLIFIERS =  +  δR1 δR1 2R1R4−2R2R3 2R1R4−2R2R3 Difference amplifiers are used in high accuracy circuits to improve δCMRR 1 the common-mode rejection ratio (CMRR). δR1 = (2R2R3) 2− R2 R1R4 100kΩ V+ Assuming that R1 2 7 R1 ≈ R2 ≈ R3 ≈ R4 ≈ R V1 6 OP1177 VOUT and 3 4 R(1 − δ) < R1, R2, R3, R4 < R(1 + δ) V– the worst-case CMRR error arises when V2 R3 = R1 R4 = R1 R1 = R4 = R(1 + δ) and R2 = R3 = R(1 − δ) RR43=RR21 02627-063 Figure 63. Difference Amplifier Rev. H | Page 18 of 24

Data Sheet OP1177/OP2177/OP4177 Plugging these values into Equation 1 yields VCC R9 CMRRMIN ≅ 21δ 2.2CµF1 ADR293 200kΩ where δ is the tolerance of the resistors. 47kRΩ3 8R07.6kΩ V+ 0.1µF 10µF Lower tolerance value resistors result in higher common-mode D1 rejection (up to the CMRR of the operational amplifier). D1 R2 R506Ω 10µF 4.02kΩ R8 7 Using 5% tolerance resistors, the highest CMRR that can be (–) TR Cu 1kΩ 2 6 guaranteed is 20 dB. Alternatively, using 0.1% tolerance resistors TJ VTC OP1177 VOUT R5 3 results in a common-mode rejection ratio of at least 54 dB TR Cu (+) 100Ω 10µF (assuming that the operational amplifier CMRR × 54 dB). 10µF 4 R1 R4 50Ω 50Ω With the CMRR of OPx177 at 120 dB minimum, the resistor mcaant cbhe iuss tehde tloim fuitritnhge rfa icmtoprr oinv em roessits ctoirrc muiatst.c hAi ntrgim anmdi nCgM reRsiRst oorf ISOBTLHOECRKMAL V– 0.1µF 02627-064 Figure 64. Type K Thermocouple Amplifier Circuit the difference amplifier circuit. LOW POWER LINEARIZED RTD A HIGH ACCURACY THERMOCOUPLE AMPLIFIER A common application for a single element varying bridge is an A thermocouple consists of two dissimilar metal wires placed in RTD thermometer amplifier, as shown in Figure 65. The excita- contact. The dissimilar metals produce a voltage tion is delivered to the bridge by a 2.5 V reference applied at the V = α(T − T ) TC J R top of the bridge. where: RTDs may have thermal resistance as high as 0.5°C to 0.8°C T is the temperature at the measurement of the hot junction. J per mW. To minimize errors due to resistor drift, the current T is the temperature at the cold junction. R through each leg of the bridge must be kept low. In this circuit, α is the Seebeck coefficient specific to the dissimilar metals used the amplifier supply current flows through the bridge. However, in the thermocouple. at the OPx177 maximum supply current of 600 µA, the RTD V is the thermocouple voltage and becomes larger with TC dissipates less than 0.1 mW of power, even at the highest resis- increasing temperature. tance. Errors due to power dissipation in the bridge are kept Maximum measurement accuracy requires cold junction compen- under 0.1°C. sation of the thermocouple. To perform the cold junction compen- Calibration of the bridge is made at the minimum value of sation, apply a copper wire short across the terminating junctions temperature to be measured by adjusting R until the output is zero. P (inside the isothermal block) simulating a 0°C point. Adjust the To calibrate the output span, set the full-scale and linearity output voltage to zero using the R5 trimming resistor, and remove potentiometers to midpoint and apply a 500°C temperature to the copper wire. the sensor or substitute the equivalent 500°C RTD resistance. The OPx177 is an ideal amplifier for thermocouple circuits Adjust the full-scale potentiometer for a 5 V output. Finally, because it has a very low offset voltage, excellent PSRR and apply 250°C or the equivalent RTD resistance and adjust the CMRR, and low noise at low frequencies. linearity potentiometer for 2.5 V output. The circuit achieves It can be used to create a thermocouple circuit with great better than ±0.5°C accuracy after adjustment. linearity. Resistor R1, Resistor R2, and Diode D1, shown in Figure 64, are mounted in an isothermal block. Rev. H | Page 19 of 24

OP1177/OP2177/OP4177 Data Sheet +15V where δ = ∆R/R is the fractional deviation of the RTD resistance with respect to the bridge resistance due to the change in temper- 0.1µF 500Ω ature at the RTD. ADR421 For δ << 1, the preceding expression becomes 4.12kΩ 4.37kΩ 200Ω   6 R2  δ  4.12kΩ 100Ω 5 OP12/2177 7 VOUT VO≅  R  VREF 1+R1+ R1 =  R R2 100Ω 20Ω R2 R1 R1  R  1+R2+R2 VREFδ 5kΩ 49.9kΩ With V constant, the output voltage is linearly proportional 100Ω V+ REF RTD to δ with a gain factor of 2 8 R2 R1 R1 OP12/2177 1 VOUT VREF  R  1+R2+R2 3 15V Figure 65. Low4V P–ower Linearized RTD Circuit 02627-065 0.1µF ADR421 RF V+ R R SINGLE OPERATIONAL AMPLIFIER BRIDGE 2 7 6 VOUT The low input offset voltage drift of the OP1177 makes it very R(1+δ) R OP1177 3 effective for bridge amplifier circuits used in RTD signal condi- 4 tioning. It is often more economical to use a single bridge V– Ionp ethraet icoirncaul iat mshpoliwfiner ians Foipgpuorsee 6d6 t,o t hane ionusttpruumt veonlttaatgioen a ta mthpel ifier. RF 02627-066 operational amplifier is Figure 66. Single Bridge Amplifier       V = R2 V  δ  O R  REF  R1+1+ R1 (1+δ)   R  R2  Rev. H | Page 20 of 24

Data Sheet OP1177/OP2177/OP4177 REALIZATION OF ACTIVE FILTERS BAND-PASS KRC OR SALLEN-KEY FILTER CHANNEL SEPARATION The low offset voltage and the high CMRR of the OPx177 make Multiple amplifiers on a single die are often required to reject it an excellent choice for precision filters, such as the band-pass any signals originating from the inputs or outputs of adjacent KRC filter shown in Figure 67. This filter type offers the capability channels. OP2177 input and bias circuitry is designed to prevent to tune the gain and the cutoff frequency independently. feedthrough of signals from one amplifier channel to the other. As a result, the OP2177 has an impressive channel separation of Because the common-mode voltage into the amplifier varies with greater than −120 dB for frequencies up to 100 kHz and greater the input signal in the KRC filter circuit, a high CMRR is required than −115 dB for signals up to 1 MHz. to minimize distortion. Also, the low offset voltage of the OPx177 C3 allows a wider dynamic range when the circuit gain is chosen to 680pF R2 be high. 10kΩ The circuit of Figure 67 consists of two stages. The first stage is a simple high-pass filter where the corner frequency (f ) is C V+ 2 1 (2) 6 8 R3 R4 OP12/2177 1 VOUT 2π C1C2R1R2 C2 C1 1/2 7 33kΩ 33kΩ 3 10nF 10nF OP2177 5 and + R1 4 330CpF4 Q=K RR21 (3) –V1 20kΩ V– 02627-067 Figure 67. Two-Stage, Band-Pass KRC Filter where K is the dc gain. Choosing equal capacitor values minimizes the sensitivity and 10kΩ simplifies Equation 2 to V+ 1 6 8 2 100Ω 2πC R1R2 1/2 7 1 1/2 OP2177 OP2177 The value of Q determines the peaking of the gain vs. frequency 5 3 + 4 (arrien ggeinnge rianl ltyr annesaire nutn riteys.p onse). Commonly chosen values for Q 50mVV1 – V– 02627-068 1 Figure 68. Channel Separation Test Circuit Setting Q= yields minimum gain peaking and minimum 2 REFERENCES ON NOISE DYNAMICS ringing. Determine values for R1 and R2 by using Equation 3. AND FLICKER NOISE 1 For Q= , R1/R2 = 2 in the circuit example. Select R1 = 5 kΩ S. Franco, Design with Operational Amplifiers and Analog 2 Integrated Circuits. McGraw-Hill, 1998. and R2 = 10 kΩ for simplicity. Analog Devices, Inc., The Best of Analog Dialogue, 1967 to The second stage is a low-pass filter where the corner frequency 1991. Analog Devices, Inc., 1991. can be determined in a similar fashion. For R3 = R4 = R 1 1 C3 fC = C3 and Q= 2 C4 2πR C4 Rev. H | Page 21 of 24

OP1177/OP2177/OP4177 Data Sheet OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 01..2407((00..00515070)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA R(CINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 2407-A01 Figure 69. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINEOFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 70. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. H | Page 22 of 24

Data Sheet OP1177/OP2177/OP4177 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0. 2T5O JEDEC STA0°NDARDS 0M.0O9-187-AA 0.40 10-07-2009-B Figure 71. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.A20X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. H | Page 23 of 24

OP1177/OP2177/OP4177 Data Sheet ORDERING GUIDE Model1 Temperature Range Package Description Package Option Marking Code OP1177ARZ −40°C to +125°C 8-Lead SOIC_N R-8 OP1177ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 OP1177ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 OP1177ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 AZA OP1177ARMZ −40°C to +125°C 8-Lead MSOP RM-8 AZA OP1177ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 AZA OP1177ARMZ-R7 −40°C to +125°C 8-Lead MSOP RM-8 AZA OP2177ARZ −40°C to +125°C 8-Lead SOIC_N R-8 OP2177ARZ-REEL −40°C to +125°C 8-Lead SOIC_N R-8 OP2177ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 OP2177CRZ −40°C to +125°C 8-Lead SOIC_N R-8 OP2177CRZ-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8 OP2177ARMZ −40°C to +125°C 8-Lead MSOP RM-8 B2A OP2177ARMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 B2A OP2177ARMZ-R7 −40°C to +125°C 8-Lead MSOP RM-8 B2A OP2177CRMZ −40°C to +125°C 8-Lead MSOP RM-8 A3L OP2177CRMZ-REEL −40°C to +125°C 8-Lead MSOP RM-8 A3L OP4177AR −40°C to +125°C 14-Lead SOIC_N R-14 OP4177AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 OP4177ARZ −40°C to +125°C 14-Lead SOIC_N R-14 OP4177ARZ-REEL −40°C to +125°C 14-Lead SOIC_N R-14 OP4177ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14 OP4177ARU −40°C to +125°C 14-Lead TSSOP RU-14 OP4177ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14 OP4177ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 OP4177ARUZ-REEL −40°C to +125°C 14-Lead TSSOP RU-14 1 Z = RoHS Compliant Part. ©2001–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02627-0-9/18(H) Rev. H | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: OP2177ARMZ-REEL OP1177ARZ OP1177ARMZ OP4177ARZ OP4177AR-REEL7 OP2177ARZ-REEL7 OP4177AR OP4177ARZ-REEL7 OP2177ARZ-REEL OP2177ARMZ-R7 OP1177ARMZ-REEL OP1177ARZ-REEL7 OP4177ARU-REEL OP4177ARUZ-REEL OP1177ARM-REEL OP4177ARU OP1177ARZ-REEL OP2177ARZ OP1177ARMZ-R7 OP4177ARZ-REEL OP4177ARUZ OP2177ARMZ